drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint16_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid.
 708          */
 709         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 710         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 711                 vec = vec - 1; /* the last interrupt is reserved */
 712         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 713         for (i = 0; i < hw->intr_tqps_num; i++) {
 714                 /*
 715                  * Set gap limiter/rate limiter/quanity limiter algorithm
 716                  * configuration for interrupt coalesce of queue's interrupt.
 717                  */
 718                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 719                                        HNS3_TQP_INTR_GL_DEFAULT);
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 723                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 724
 725                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 726                                                    HNS3_RING_TYPE_TX, i);
 727                 if (ret) {
 728                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 729                                           "vector: %d, ret=%d", i, vec, ret);
 730                         return ret;
 731                 }
 732
 733                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 734                                                    HNS3_RING_TYPE_RX, i);
 735                 if (ret) {
 736                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 737                                           "vector: %d, ret=%d", i, vec, ret);
 738                         return ret;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3vf_dev_configure(struct rte_eth_dev *dev)
 747 {
 748         struct hns3_adapter *hns = dev->data->dev_private;
 749         struct hns3_hw *hw = &hns->hw;
 750         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 751         struct rte_eth_conf *conf = &dev->data->dev_conf;
 752         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 753         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 754         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 755         struct rte_eth_rss_conf rss_conf;
 756         uint16_t mtu;
 757         bool gro_en;
 758         int ret;
 759
 760         /*
 761          * Hardware does not support individually enable/disable/reset the Tx or
 762          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 763          * and Rx queues at the same time. When the numbers of Tx queues
 764          * allocated by upper applications are not equal to the numbers of Rx
 765          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 766          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 767          * these fake queues are imperceptible, and can not be used by upper
 768          * applications.
 769          */
 770         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 771         if (ret) {
 772                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 773                 return ret;
 774         }
 775
 776         hw->adapter_state = HNS3_NIC_CONFIGURING;
 777         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 778                 hns3_err(hw, "setting link speed/duplex not supported");
 779                 ret = -EINVAL;
 780                 goto cfg_err;
 781         }
 782
 783         /* When RSS is not configured, redirect the packet queue 0 */
 784         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 785                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 786                 rss_conf = conf->rx_adv_conf.rss_conf;
 787                 if (rss_conf.rss_key == NULL) {
 788                         rss_conf.rss_key = rss_cfg->key;
 789                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 790                 }
 791
 792                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 793                 if (ret)
 794                         goto cfg_err;
 795         }
 796
 797         /*
 798          * If jumbo frames are enabled, MTU needs to be refreshed
 799          * according to the maximum RX packet length.
 800          */
 801         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 802                 /*
 803                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 804                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 805                  * can safely assign to "uint16_t" type variable.
 806                  */
 807                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 808                 ret = hns3vf_dev_mtu_set(dev, mtu);
 809                 if (ret)
 810                         goto cfg_err;
 811                 dev->data->mtu = mtu;
 812         }
 813
 814         ret = hns3vf_dev_configure_vlan(dev);
 815         if (ret)
 816                 goto cfg_err;
 817
 818         /* config hardware GRO */
 819         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 820         ret = hns3_config_gro(hw, gro_en);
 821         if (ret)
 822                 goto cfg_err;
 823
 824         hns->rx_simple_allowed = true;
 825         hns->tx_simple_allowed = true;
 826         hns->tx_vec_allowed = true;
 827
 828         hns3_init_rx_ptype_tble(dev);
 829
 830         hw->adapter_state = HNS3_NIC_CONFIGURED;
 831         return 0;
 832
 833 cfg_err:
 834         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 835         hw->adapter_state = HNS3_NIC_INITIALIZED;
 836
 837         return ret;
 838 }
 839
 840 static int
 841 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 842 {
 843         int ret;
 844
 845         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 846                                 sizeof(mtu), true, NULL, 0);
 847         if (ret)
 848                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 849
 850         return ret;
 851 }
 852
 853 static int
 854 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 855 {
 856         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 857         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 858         int ret;
 859
 860         /*
 861          * The hns3 PF/VF devices on the same port share the hardware MTU
 862          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 863          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 864          * driver, there is no need to stop the port for hns3 VF device, and the
 865          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 866          * PF's MTU.
 867          */
 868         if (rte_atomic16_read(&hw->reset.resetting)) {
 869                 hns3_err(hw, "Failed to set mtu during resetting");
 870                 return -EIO;
 871         }
 872
 873         rte_spinlock_lock(&hw->lock);
 874         ret = hns3vf_config_mtu(hw, mtu);
 875         if (ret) {
 876                 rte_spinlock_unlock(&hw->lock);
 877                 return ret;
 878         }
 879         if (frame_size > RTE_ETHER_MAX_LEN)
 880                 dev->data->dev_conf.rxmode.offloads |=
 881                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 882         else
 883                 dev->data->dev_conf.rxmode.offloads &=
 884                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 885         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 886         rte_spinlock_unlock(&hw->lock);
 887
 888         return 0;
 889 }
 890
 891 static int
 892 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 893 {
 894         struct hns3_adapter *hns = eth_dev->data->dev_private;
 895         struct hns3_hw *hw = &hns->hw;
 896         uint16_t q_num = hw->tqps_num;
 897
 898         /*
 899          * In interrupt mode, 'max_rx_queues' is set based on the number of
 900          * MSI-X interrupt resources of the hardware.
 901          */
 902         if (hw->data->dev_conf.intr_conf.rxq == 1)
 903                 q_num = hw->intr_tqps_num;
 904
 905         info->max_rx_queues = q_num;
 906         info->max_tx_queues = hw->tqps_num;
 907         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 908         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 909         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 910         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 911         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 912
 913         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 914                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 915                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 916                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 917                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 918                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 919                                  DEV_RX_OFFLOAD_SCATTER |
 920                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 921                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 922                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 923                                  DEV_RX_OFFLOAD_RSS_HASH |
 924                                  DEV_RX_OFFLOAD_TCP_LRO);
 925         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 926                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 927                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 928                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 929                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 930                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 931                                  DEV_TX_OFFLOAD_TCP_TSO |
 932                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 933                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 934                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 935                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 936                                  hns3_txvlan_cap_get(hw));
 937
 938         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 939                 .nb_max = HNS3_MAX_RING_DESC,
 940                 .nb_min = HNS3_MIN_RING_DESC,
 941                 .nb_align = HNS3_ALIGN_RING_DESC,
 942         };
 943
 944         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 945                 .nb_max = HNS3_MAX_RING_DESC,
 946                 .nb_min = HNS3_MIN_RING_DESC,
 947                 .nb_align = HNS3_ALIGN_RING_DESC,
 948                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 949                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
 950         };
 951
 952         info->default_rxconf = (struct rte_eth_rxconf) {
 953                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 954                 /*
 955                  * If there are no available Rx buffer descriptors, incoming
 956                  * packets are always dropped by hardware based on hns3 network
 957                  * engine.
 958                  */
 959                 .rx_drop_en = 1,
 960                 .offloads = 0,
 961         };
 962         info->default_txconf = (struct rte_eth_txconf) {
 963                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 964                 .offloads = 0,
 965         };
 966
 967         info->vmdq_queue_num = 0;
 968
 969         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 970         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 971         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 972         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 973         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 974
 975         return 0;
 976 }
 977
 978 static void
 979 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 980 {
 981         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 982 }
 983
 984 static void
 985 hns3vf_disable_irq0(struct hns3_hw *hw)
 986 {
 987         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 988 }
 989
 990 static void
 991 hns3vf_enable_irq0(struct hns3_hw *hw)
 992 {
 993         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 994 }
 995
 996 static enum hns3vf_evt_cause
 997 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 998 {
 999         struct hns3_hw *hw = &hns->hw;
1000         enum hns3vf_evt_cause ret;
1001         uint32_t cmdq_stat_reg;
1002         uint32_t rst_ing_reg;
1003         uint32_t val;
1004
1005         /* Fetch the events from their corresponding regs */
1006         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1007
1008         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1009                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1010                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1011                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1012                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1013                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1014                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1015                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1016                 if (clearval) {
1017                         hw->reset.stats.global_cnt++;
1018                         hns3_warn(hw, "Global reset detected, clear reset status");
1019                 } else {
1020                         hns3_schedule_delayed_reset(hns);
1021                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1022                 }
1023
1024                 ret = HNS3VF_VECTOR0_EVENT_RST;
1025                 goto out;
1026         }
1027
1028         /* Check for vector0 mailbox(=CMDQ RX) event source */
1029         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1030                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1031                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1032                 goto out;
1033         }
1034
1035         val = 0;
1036         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1037 out:
1038         if (clearval)
1039                 *clearval = val;
1040         return ret;
1041 }
1042
1043 static void
1044 hns3vf_interrupt_handler(void *param)
1045 {
1046         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1047         struct hns3_adapter *hns = dev->data->dev_private;
1048         struct hns3_hw *hw = &hns->hw;
1049         enum hns3vf_evt_cause event_cause;
1050         uint32_t clearval;
1051
1052         if (hw->irq_thread_id == 0)
1053                 hw->irq_thread_id = pthread_self();
1054
1055         /* Disable interrupt */
1056         hns3vf_disable_irq0(hw);
1057
1058         /* Read out interrupt causes */
1059         event_cause = hns3vf_check_event_cause(hns, &clearval);
1060
1061         switch (event_cause) {
1062         case HNS3VF_VECTOR0_EVENT_RST:
1063                 hns3_schedule_reset(hns);
1064                 break;
1065         case HNS3VF_VECTOR0_EVENT_MBX:
1066                 hns3_dev_handle_mbx_msg(hw);
1067                 break;
1068         default:
1069                 break;
1070         }
1071
1072         /* Clear interrupt causes */
1073         hns3vf_clear_event_cause(hw, clearval);
1074
1075         /* Enable interrupt */
1076         hns3vf_enable_irq0(hw);
1077 }
1078
1079 static void
1080 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1081 {
1082         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1083         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1084         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1085 }
1086
1087 static void
1088 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1089 {
1090         struct hns3_dev_specs_0_cmd *req0;
1091
1092         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1093
1094         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1095         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1096         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1097 }
1098
1099 static int
1100 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1101 {
1102         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1103         int ret;
1104         int i;
1105
1106         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1107                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1108                                           true);
1109                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1110         }
1111         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1112
1113         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1114         if (ret)
1115                 return ret;
1116
1117         hns3vf_parse_dev_specifications(hw, desc);
1118
1119         return 0;
1120 }
1121
1122 static int
1123 hns3vf_get_capability(struct hns3_hw *hw)
1124 {
1125         struct rte_pci_device *pci_dev;
1126         struct rte_eth_dev *eth_dev;
1127         uint8_t revision;
1128         int ret;
1129
1130         eth_dev = &rte_eth_devices[hw->data->port_id];
1131         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1132
1133         /* Get PCI revision id */
1134         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1135                                   HNS3_PCI_REVISION_ID);
1136         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1137                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1138                              ret);
1139                 return -EIO;
1140         }
1141         hw->revision = revision;
1142
1143         if (revision < PCI_REVISION_ID_HIP09_A) {
1144                 hns3vf_set_default_dev_specifications(hw);
1145                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1146                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1147                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1148                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1149                 return 0;
1150         }
1151
1152         ret = hns3vf_query_dev_specifications(hw);
1153         if (ret) {
1154                 PMD_INIT_LOG(ERR,
1155                              "failed to query dev specifications, ret = %d",
1156                              ret);
1157                 return ret;
1158         }
1159
1160         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1161         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1162         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1163         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1164
1165         return 0;
1166 }
1167
1168 static int
1169 hns3vf_check_tqp_info(struct hns3_hw *hw)
1170 {
1171         uint16_t tqps_num;
1172
1173         tqps_num = hw->tqps_num;
1174         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1175                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1176                                   "range: 1~%d",
1177                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1178                 return -EINVAL;
1179         }
1180
1181         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1182
1183         return 0;
1184 }
1185 static int
1186 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1187 {
1188         uint8_t resp_msg;
1189         int ret;
1190
1191         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1192                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1193                                 true, &resp_msg, sizeof(resp_msg));
1194         if (ret) {
1195                 if (ret == -ETIME) {
1196                         /*
1197                          * Getting current port based VLAN state from PF driver
1198                          * will not affect VF driver's basic function. Because
1199                          * the VF driver relies on hns3 PF kernel ether driver,
1200                          * to avoid introducing compatibility issues with older
1201                          * version of PF driver, no failure will be returned
1202                          * when the return value is ETIME. This return value has
1203                          * the following scenarios:
1204                          * 1) Firmware didn't return the results in time
1205                          * 2) the result return by firmware is timeout
1206                          * 3) the older version of kernel side PF driver does
1207                          *    not support this mailbox message.
1208                          * For scenarios 1 and 2, it is most likely that a
1209                          * hardware error has occurred, or a hardware reset has
1210                          * occurred. In this case, these errors will be caught
1211                          * by other functions.
1212                          */
1213                         PMD_INIT_LOG(WARNING,
1214                                 "failed to get PVID state for timeout, maybe "
1215                                 "kernel side PF driver doesn't support this "
1216                                 "mailbox message, or firmware didn't respond.");
1217                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1218                 } else {
1219                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1220                                 " ret = %d", ret);
1221                         return ret;
1222                 }
1223         }
1224         hw->port_base_vlan_cfg.state = resp_msg ?
1225                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1226         return 0;
1227 }
1228
1229 static int
1230 hns3vf_get_queue_info(struct hns3_hw *hw)
1231 {
1232 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1233         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1234         int ret;
1235
1236         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1237                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1238         if (ret) {
1239                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1240                 return ret;
1241         }
1242
1243         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1244         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1245
1246         return hns3vf_check_tqp_info(hw);
1247 }
1248
1249 static int
1250 hns3vf_get_queue_depth(struct hns3_hw *hw)
1251 {
1252 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1253         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1254         int ret;
1255
1256         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1257                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1258         if (ret) {
1259                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1260                              ret);
1261                 return ret;
1262         }
1263
1264         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1265         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1266
1267         return 0;
1268 }
1269
1270 static int
1271 hns3vf_get_tc_info(struct hns3_hw *hw)
1272 {
1273         uint8_t resp_msg;
1274         int ret;
1275
1276         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1277                                 true, &resp_msg, sizeof(resp_msg));
1278         if (ret) {
1279                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1280                          ret);
1281                 return ret;
1282         }
1283
1284         hw->hw_tc_map = resp_msg;
1285
1286         return 0;
1287 }
1288
1289 static int
1290 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1291 {
1292         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1293         int ret;
1294
1295         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1296                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1297         if (ret) {
1298                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1299                 return ret;
1300         }
1301
1302         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1303
1304         return 0;
1305 }
1306
1307 static int
1308 hns3vf_get_configuration(struct hns3_hw *hw)
1309 {
1310         int ret;
1311
1312         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1313         hw->rss_dis_flag = false;
1314
1315         /* Get device capability */
1316         ret = hns3vf_get_capability(hw);
1317         if (ret) {
1318                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1319                 return ret;
1320         }
1321
1322         /* Get queue configuration from PF */
1323         ret = hns3vf_get_queue_info(hw);
1324         if (ret)
1325                 return ret;
1326
1327         /* Get queue depth info from PF */
1328         ret = hns3vf_get_queue_depth(hw);
1329         if (ret)
1330                 return ret;
1331
1332         /* Get user defined VF MAC addr from PF */
1333         ret = hns3vf_get_host_mac_addr(hw);
1334         if (ret)
1335                 return ret;
1336
1337         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1338         if (ret)
1339                 return ret;
1340
1341         /* Get tc configuration from PF */
1342         return hns3vf_get_tc_info(hw);
1343 }
1344
1345 static int
1346 hns3vf_set_tc_info(struct hns3_adapter *hns)
1347 {
1348         struct hns3_hw *hw = &hns->hw;
1349         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1350         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1351         uint8_t i;
1352
1353         hw->num_tc = 0;
1354         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1355                 if (hw->hw_tc_map & BIT(i))
1356                         hw->num_tc++;
1357
1358         if (nb_rx_q < hw->num_tc) {
1359                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1360                          nb_rx_q, hw->num_tc);
1361                 return -EINVAL;
1362         }
1363
1364         if (nb_tx_q < hw->num_tc) {
1365                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1366                          nb_tx_q, hw->num_tc);
1367                 return -EINVAL;
1368         }
1369
1370         hns3_set_rss_size(hw, nb_rx_q);
1371         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1372
1373         return 0;
1374 }
1375
1376 static void
1377 hns3vf_request_link_info(struct hns3_hw *hw)
1378 {
1379         uint8_t resp_msg;
1380         int ret;
1381
1382         if (rte_atomic16_read(&hw->reset.resetting))
1383                 return;
1384         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1385                                 &resp_msg, sizeof(resp_msg));
1386         if (ret)
1387                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1388 }
1389
1390 static int
1391 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1392 {
1393 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1394         struct hns3_hw *hw = &hns->hw;
1395         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1396         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1397         uint8_t is_kill = on ? 0 : 1;
1398
1399         msg_data[0] = is_kill;
1400         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1401         memcpy(&msg_data[3], &proto, sizeof(proto));
1402
1403         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1404                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1405                                  0);
1406 }
1407
1408 static int
1409 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1410 {
1411         struct hns3_adapter *hns = dev->data->dev_private;
1412         struct hns3_hw *hw = &hns->hw;
1413         int ret;
1414
1415         if (rte_atomic16_read(&hw->reset.resetting)) {
1416                 hns3_err(hw,
1417                          "vf set vlan id failed during resetting, vlan_id =%u",
1418                          vlan_id);
1419                 return -EIO;
1420         }
1421         rte_spinlock_lock(&hw->lock);
1422         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1423         rte_spinlock_unlock(&hw->lock);
1424         if (ret)
1425                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1426                          vlan_id, ret);
1427
1428         return ret;
1429 }
1430
1431 static int
1432 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1433 {
1434         uint8_t msg_data;
1435         int ret;
1436
1437         msg_data = enable ? 1 : 0;
1438         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1439                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1440         if (ret)
1441                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1442
1443         return ret;
1444 }
1445
1446 static int
1447 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1448 {
1449         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1450         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1451         unsigned int tmp_mask;
1452         int ret = 0;
1453
1454         if (rte_atomic16_read(&hw->reset.resetting)) {
1455                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1456                              "mask = 0x%x", mask);
1457                 return -EIO;
1458         }
1459
1460         tmp_mask = (unsigned int)mask;
1461         /* Vlan stripping setting */
1462         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1463                 rte_spinlock_lock(&hw->lock);
1464                 /* Enable or disable VLAN stripping */
1465                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1466                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1467                 else
1468                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1469                 rte_spinlock_unlock(&hw->lock);
1470         }
1471
1472         return ret;
1473 }
1474
1475 static int
1476 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1477 {
1478         struct rte_vlan_filter_conf *vfc;
1479         struct hns3_hw *hw = &hns->hw;
1480         uint16_t vlan_id;
1481         uint64_t vbit;
1482         uint64_t ids;
1483         int ret = 0;
1484         uint32_t i;
1485
1486         vfc = &hw->data->vlan_filter_conf;
1487         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1488                 if (vfc->ids[i] == 0)
1489                         continue;
1490                 ids = vfc->ids[i];
1491                 while (ids) {
1492                         /*
1493                          * 64 means the num bits of ids, one bit corresponds to
1494                          * one vlan id
1495                          */
1496                         vlan_id = 64 * i;
1497                         /* count trailing zeroes */
1498                         vbit = ~ids & (ids - 1);
1499                         /* clear least significant bit set */
1500                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1501                         for (; vbit;) {
1502                                 vbit >>= 1;
1503                                 vlan_id++;
1504                         }
1505                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1506                         if (ret) {
1507                                 hns3_err(hw,
1508                                          "VF handle vlan table failed, ret =%d, on = %d",
1509                                          ret, on);
1510                                 return ret;
1511                         }
1512                 }
1513         }
1514
1515         return ret;
1516 }
1517
1518 static int
1519 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1520 {
1521         return hns3vf_handle_all_vlan_table(hns, 0);
1522 }
1523
1524 static int
1525 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1526 {
1527         struct hns3_hw *hw = &hns->hw;
1528         struct rte_eth_conf *dev_conf;
1529         bool en;
1530         int ret;
1531
1532         dev_conf = &hw->data->dev_conf;
1533         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1534                                                                    : false;
1535         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1536         if (ret)
1537                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1538                          ret);
1539         return ret;
1540 }
1541
1542 static int
1543 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1544 {
1545         struct hns3_adapter *hns = dev->data->dev_private;
1546         struct rte_eth_dev_data *data = dev->data;
1547         struct hns3_hw *hw = &hns->hw;
1548         int ret;
1549
1550         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1551             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1552             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1553                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1554                               "or hw_vlan_insert_pvid is not support!");
1555         }
1556
1557         /* Apply vlan offload setting */
1558         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1559         if (ret)
1560                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1561
1562         return ret;
1563 }
1564
1565 static int
1566 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1567 {
1568         uint8_t msg_data;
1569
1570         msg_data = alive ? 1 : 0;
1571         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1572                                  sizeof(msg_data), false, NULL, 0);
1573 }
1574
1575 static void
1576 hns3vf_keep_alive_handler(void *param)
1577 {
1578         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1579         struct hns3_adapter *hns = eth_dev->data->dev_private;
1580         struct hns3_hw *hw = &hns->hw;
1581         uint8_t respmsg;
1582         int ret;
1583
1584         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1585                                 false, &respmsg, sizeof(uint8_t));
1586         if (ret)
1587                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1588                          ret);
1589
1590         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1591                           eth_dev);
1592 }
1593
1594 static void
1595 hns3vf_service_handler(void *param)
1596 {
1597         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1598         struct hns3_adapter *hns = eth_dev->data->dev_private;
1599         struct hns3_hw *hw = &hns->hw;
1600
1601         /*
1602          * The query link status and reset processing are executed in the
1603          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1604          * and the query operation will time out after 30ms. In the case of
1605          * multiple PF/VFs, each query failure timeout causes the IMP reset
1606          * interrupt to fail to respond within 100ms.
1607          * Before querying the link status, check whether there is a reset
1608          * pending, and if so, abandon the query.
1609          */
1610         if (!hns3vf_is_reset_pending(hns))
1611                 hns3vf_request_link_info(hw);
1612         else
1613                 hns3_warn(hw, "Cancel the query when reset is pending");
1614
1615         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1616                           eth_dev);
1617 }
1618
1619 static int
1620 hns3_query_vf_resource(struct hns3_hw *hw)
1621 {
1622         struct hns3_vf_res_cmd *req;
1623         struct hns3_cmd_desc desc;
1624         uint16_t num_msi;
1625         int ret;
1626
1627         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1628         ret = hns3_cmd_send(hw, &desc, 1);
1629         if (ret) {
1630                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1631                 return ret;
1632         }
1633
1634         req = (struct hns3_vf_res_cmd *)desc.data;
1635         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1636                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1637         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1638                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1639                          num_msi, HNS3_MIN_VECTOR_NUM);
1640                 return -EINVAL;
1641         }
1642
1643         hw->num_msi = num_msi;
1644
1645         return 0;
1646 }
1647
1648 static int
1649 hns3vf_init_hardware(struct hns3_adapter *hns)
1650 {
1651         struct hns3_hw *hw = &hns->hw;
1652         uint16_t mtu = hw->data->mtu;
1653         int ret;
1654
1655         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1656         if (ret)
1657                 return ret;
1658
1659         ret = hns3vf_config_mtu(hw, mtu);
1660         if (ret)
1661                 goto err_init_hardware;
1662
1663         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1664         if (ret) {
1665                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1666                 goto err_init_hardware;
1667         }
1668
1669         ret = hns3_config_gro(hw, false);
1670         if (ret) {
1671                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1672                 goto err_init_hardware;
1673         }
1674
1675         /*
1676          * In the initialization clearing the all hardware mapping relationship
1677          * configurations between queues and interrupt vectors is needed, so
1678          * some error caused by the residual configurations, such as the
1679          * unexpected interrupt, can be avoid.
1680          */
1681         ret = hns3vf_init_ring_with_vector(hw);
1682         if (ret) {
1683                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1684                 goto err_init_hardware;
1685         }
1686
1687         ret = hns3vf_set_alive(hw, true);
1688         if (ret) {
1689                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1690                 goto err_init_hardware;
1691         }
1692
1693         hns3vf_request_link_info(hw);
1694         return 0;
1695
1696 err_init_hardware:
1697         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1698         return ret;
1699 }
1700
1701 static int
1702 hns3vf_clear_vport_list(struct hns3_hw *hw)
1703 {
1704         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1705                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1706                                  NULL, 0);
1707 }
1708
1709 static int
1710 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1711 {
1712         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1713         struct hns3_adapter *hns = eth_dev->data->dev_private;
1714         struct hns3_hw *hw = &hns->hw;
1715         int ret;
1716
1717         PMD_INIT_FUNC_TRACE();
1718
1719         /* Get hardware io base address from pcie BAR2 IO space */
1720         hw->io_base = pci_dev->mem_resource[2].addr;
1721
1722         /* Firmware command queue initialize */
1723         ret = hns3_cmd_init_queue(hw);
1724         if (ret) {
1725                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1726                 goto err_cmd_init_queue;
1727         }
1728
1729         /* Firmware command initialize */
1730         ret = hns3_cmd_init(hw);
1731         if (ret) {
1732                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1733                 goto err_cmd_init;
1734         }
1735
1736         /* Get VF resource */
1737         ret = hns3_query_vf_resource(hw);
1738         if (ret)
1739                 goto err_cmd_init;
1740
1741         rte_spinlock_init(&hw->mbx_resp.lock);
1742
1743         hns3vf_clear_event_cause(hw, 0);
1744
1745         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1746                                          hns3vf_interrupt_handler, eth_dev);
1747         if (ret) {
1748                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1749                 goto err_intr_callback_register;
1750         }
1751
1752         /* Enable interrupt */
1753         rte_intr_enable(&pci_dev->intr_handle);
1754         hns3vf_enable_irq0(hw);
1755
1756         /* Get configuration from PF */
1757         ret = hns3vf_get_configuration(hw);
1758         if (ret) {
1759                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1760                 goto err_get_config;
1761         }
1762
1763         ret = hns3vf_clear_vport_list(hw);
1764         if (ret) {
1765                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1766                 goto err_get_config;
1767         }
1768
1769         ret = hns3vf_init_hardware(hns);
1770         if (ret)
1771                 goto err_get_config;
1772
1773         hns3_set_default_rss_args(hw);
1774
1775         return 0;
1776
1777 err_get_config:
1778         hns3vf_disable_irq0(hw);
1779         rte_intr_disable(&pci_dev->intr_handle);
1780         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1781                              eth_dev);
1782 err_intr_callback_register:
1783 err_cmd_init:
1784         hns3_cmd_uninit(hw);
1785         hns3_cmd_destroy_queue(hw);
1786 err_cmd_init_queue:
1787         hw->io_base = NULL;
1788
1789         return ret;
1790 }
1791
1792 static void
1793 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1794 {
1795         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1796         struct hns3_adapter *hns = eth_dev->data->dev_private;
1797         struct hns3_hw *hw = &hns->hw;
1798
1799         PMD_INIT_FUNC_TRACE();
1800
1801         hns3_rss_uninit(hns);
1802         (void)hns3_config_gro(hw, false);
1803         (void)hns3vf_set_alive(hw, false);
1804         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1805         hns3vf_disable_irq0(hw);
1806         rte_intr_disable(&pci_dev->intr_handle);
1807         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1808                              eth_dev);
1809         hns3_cmd_uninit(hw);
1810         hns3_cmd_destroy_queue(hw);
1811         hw->io_base = NULL;
1812 }
1813
1814 static int
1815 hns3vf_do_stop(struct hns3_adapter *hns)
1816 {
1817         struct hns3_hw *hw = &hns->hw;
1818         bool reset_queue;
1819
1820         hw->mac.link_status = ETH_LINK_DOWN;
1821
1822         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1823                 hns3vf_configure_mac_addr(hns, true);
1824                 reset_queue = true;
1825         } else
1826                 reset_queue = false;
1827         return hns3_stop_queues(hns, reset_queue);
1828 }
1829
1830 static void
1831 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1832 {
1833         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1835         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1836         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1837         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1838         uint16_t q_id;
1839
1840         if (dev->data->dev_conf.intr_conf.rxq == 0)
1841                 return;
1842
1843         /* unmap the ring with vector */
1844         if (rte_intr_allow_others(intr_handle)) {
1845                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1846                 base = RTE_INTR_VEC_RXTX_OFFSET;
1847         }
1848         if (rte_intr_dp_is_en(intr_handle)) {
1849                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1850                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1851                                                            HNS3_RING_TYPE_RX,
1852                                                            q_id);
1853                         if (vec < base + intr_handle->nb_efd - 1)
1854                                 vec++;
1855                 }
1856         }
1857         /* Clean datapath event and queue/vec mapping */
1858         rte_intr_efd_disable(intr_handle);
1859         if (intr_handle->intr_vec) {
1860                 rte_free(intr_handle->intr_vec);
1861                 intr_handle->intr_vec = NULL;
1862         }
1863 }
1864
1865 static void
1866 hns3vf_dev_stop(struct rte_eth_dev *dev)
1867 {
1868         struct hns3_adapter *hns = dev->data->dev_private;
1869         struct hns3_hw *hw = &hns->hw;
1870
1871         PMD_INIT_FUNC_TRACE();
1872
1873         hw->adapter_state = HNS3_NIC_STOPPING;
1874         hns3_set_rxtx_function(dev);
1875         rte_wmb();
1876         /* Disable datapath on secondary process. */
1877         hns3_mp_req_stop_rxtx(dev);
1878         /* Prevent crashes when queues are still in use. */
1879         rte_delay_ms(hw->tqps_num);
1880
1881         rte_spinlock_lock(&hw->lock);
1882         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1883                 hns3vf_do_stop(hns);
1884                 hns3vf_unmap_rx_interrupt(dev);
1885                 hns3_dev_release_mbufs(hns);
1886                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1887         }
1888         hns3_rx_scattered_reset(dev);
1889         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1890         rte_spinlock_unlock(&hw->lock);
1891 }
1892
1893 static void
1894 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1895 {
1896         struct hns3_adapter *hns = eth_dev->data->dev_private;
1897         struct hns3_hw *hw = &hns->hw;
1898
1899         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1900                 return;
1901
1902         if (hw->adapter_state == HNS3_NIC_STARTED)
1903                 hns3vf_dev_stop(eth_dev);
1904
1905         hw->adapter_state = HNS3_NIC_CLOSING;
1906         hns3_reset_abort(hns);
1907         hw->adapter_state = HNS3_NIC_CLOSED;
1908         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1909         hns3vf_configure_all_mc_mac_addr(hns, true);
1910         hns3vf_remove_all_vlan_table(hns);
1911         hns3vf_uninit_vf(eth_dev);
1912         hns3_free_all_queues(eth_dev);
1913         rte_free(hw->reset.wait_data);
1914         rte_free(eth_dev->process_private);
1915         eth_dev->process_private = NULL;
1916         hns3_mp_uninit_primary();
1917         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1918 }
1919
1920 static int
1921 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1922                       size_t fw_size)
1923 {
1924         struct hns3_adapter *hns = eth_dev->data->dev_private;
1925         struct hns3_hw *hw = &hns->hw;
1926         uint32_t version = hw->fw_version;
1927         int ret;
1928
1929         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1930                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1931                                       HNS3_FW_VERSION_BYTE3_S),
1932                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1933                                       HNS3_FW_VERSION_BYTE2_S),
1934                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1935                                       HNS3_FW_VERSION_BYTE1_S),
1936                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1937                                       HNS3_FW_VERSION_BYTE0_S));
1938         ret += 1; /* add the size of '\0' */
1939         if (fw_size < (uint32_t)ret)
1940                 return ret;
1941         else
1942                 return 0;
1943 }
1944
1945 static int
1946 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1947                        __rte_unused int wait_to_complete)
1948 {
1949         struct hns3_adapter *hns = eth_dev->data->dev_private;
1950         struct hns3_hw *hw = &hns->hw;
1951         struct hns3_mac *mac = &hw->mac;
1952         struct rte_eth_link new_link;
1953
1954         memset(&new_link, 0, sizeof(new_link));
1955         switch (mac->link_speed) {
1956         case ETH_SPEED_NUM_10M:
1957         case ETH_SPEED_NUM_100M:
1958         case ETH_SPEED_NUM_1G:
1959         case ETH_SPEED_NUM_10G:
1960         case ETH_SPEED_NUM_25G:
1961         case ETH_SPEED_NUM_40G:
1962         case ETH_SPEED_NUM_50G:
1963         case ETH_SPEED_NUM_100G:
1964         case ETH_SPEED_NUM_200G:
1965                 new_link.link_speed = mac->link_speed;
1966                 break;
1967         default:
1968                 new_link.link_speed = ETH_SPEED_NUM_100M;
1969                 break;
1970         }
1971
1972         new_link.link_duplex = mac->link_duplex;
1973         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1974         new_link.link_autoneg =
1975             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1976
1977         return rte_eth_linkstatus_set(eth_dev, &new_link);
1978 }
1979
1980 static int
1981 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1982 {
1983         struct hns3_hw *hw = &hns->hw;
1984         int ret;
1985
1986         ret = hns3vf_set_tc_info(hns);
1987         if (ret)
1988                 return ret;
1989
1990         ret = hns3_start_queues(hns, reset_queue);
1991         if (ret)
1992                 hns3_err(hw, "Failed to start queues: %d", ret);
1993
1994         return ret;
1995 }
1996
1997 static int
1998 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1999 {
2000         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2001         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2002         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2004         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2005         uint32_t intr_vector;
2006         uint16_t q_id;
2007         int ret;
2008
2009         if (dev->data->dev_conf.intr_conf.rxq == 0)
2010                 return 0;
2011
2012         /* disable uio/vfio intr/eventfd mapping */
2013         rte_intr_disable(intr_handle);
2014
2015         /* check and configure queue intr-vector mapping */
2016         if (rte_intr_cap_multiple(intr_handle) ||
2017             !RTE_ETH_DEV_SRIOV(dev).active) {
2018                 intr_vector = hw->used_rx_queues;
2019                 /* It creates event fd for each intr vector when MSIX is used */
2020                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2021                         return -EINVAL;
2022         }
2023         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2024                 intr_handle->intr_vec =
2025                         rte_zmalloc("intr_vec",
2026                                     hw->used_rx_queues * sizeof(int), 0);
2027                 if (intr_handle->intr_vec == NULL) {
2028                         hns3_err(hw, "Failed to allocate %d rx_queues"
2029                                      " intr_vec", hw->used_rx_queues);
2030                         ret = -ENOMEM;
2031                         goto vf_alloc_intr_vec_error;
2032                 }
2033         }
2034
2035         if (rte_intr_allow_others(intr_handle)) {
2036                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2037                 base = RTE_INTR_VEC_RXTX_OFFSET;
2038         }
2039         if (rte_intr_dp_is_en(intr_handle)) {
2040                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2041                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2042                                                            HNS3_RING_TYPE_RX,
2043                                                            q_id);
2044                         if (ret)
2045                                 goto vf_bind_vector_error;
2046                         intr_handle->intr_vec[q_id] = vec;
2047                         if (vec < base + intr_handle->nb_efd - 1)
2048                                 vec++;
2049                 }
2050         }
2051         rte_intr_enable(intr_handle);
2052         return 0;
2053
2054 vf_bind_vector_error:
2055         rte_intr_efd_disable(intr_handle);
2056         if (intr_handle->intr_vec) {
2057                 free(intr_handle->intr_vec);
2058                 intr_handle->intr_vec = NULL;
2059         }
2060         return ret;
2061 vf_alloc_intr_vec_error:
2062         rte_intr_efd_disable(intr_handle);
2063         return ret;
2064 }
2065
2066 static int
2067 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2068 {
2069         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2070         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2071         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2072         uint16_t q_id;
2073         int ret;
2074
2075         if (dev->data->dev_conf.intr_conf.rxq == 0)
2076                 return 0;
2077
2078         if (rte_intr_dp_is_en(intr_handle)) {
2079                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2080                         ret = hns3vf_bind_ring_with_vector(hw,
2081                                         intr_handle->intr_vec[q_id], true,
2082                                         HNS3_RING_TYPE_RX, q_id);
2083                         if (ret)
2084                                 return ret;
2085                 }
2086         }
2087
2088         return 0;
2089 }
2090
2091 static void
2092 hns3vf_restore_filter(struct rte_eth_dev *dev)
2093 {
2094         hns3_restore_rss_filter(dev);
2095 }
2096
2097 static int
2098 hns3vf_dev_start(struct rte_eth_dev *dev)
2099 {
2100         struct hns3_adapter *hns = dev->data->dev_private;
2101         struct hns3_hw *hw = &hns->hw;
2102         int ret;
2103
2104         PMD_INIT_FUNC_TRACE();
2105         if (rte_atomic16_read(&hw->reset.resetting))
2106                 return -EBUSY;
2107
2108         rte_spinlock_lock(&hw->lock);
2109         hw->adapter_state = HNS3_NIC_STARTING;
2110         ret = hns3vf_do_start(hns, true);
2111         if (ret) {
2112                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2113                 rte_spinlock_unlock(&hw->lock);
2114                 return ret;
2115         }
2116         ret = hns3vf_map_rx_interrupt(dev);
2117         if (ret) {
2118                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2119                 rte_spinlock_unlock(&hw->lock);
2120                 return ret;
2121         }
2122         hw->adapter_state = HNS3_NIC_STARTED;
2123         rte_spinlock_unlock(&hw->lock);
2124
2125         hns3_rx_scattered_calc(dev);
2126         hns3_set_rxtx_function(dev);
2127         hns3_mp_req_start_rxtx(dev);
2128         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2129
2130         hns3vf_restore_filter(dev);
2131
2132         /* Enable interrupt of all rx queues before enabling queues */
2133         hns3_dev_all_rx_queue_intr_enable(hw, true);
2134         /*
2135          * When finished the initialization, enable queues to receive/transmit
2136          * packets.
2137          */
2138         hns3_enable_all_queues(hw, true);
2139
2140         return ret;
2141 }
2142
2143 static bool
2144 is_vf_reset_done(struct hns3_hw *hw)
2145 {
2146 #define HNS3_FUN_RST_ING_BITS \
2147         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2148          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2149          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2150          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2151
2152         uint32_t val;
2153
2154         if (hw->reset.level == HNS3_VF_RESET) {
2155                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2156                 if (val & HNS3_VF_RST_ING_BIT)
2157                         return false;
2158         } else {
2159                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2160                 if (val & HNS3_FUN_RST_ING_BITS)
2161                         return false;
2162         }
2163         return true;
2164 }
2165
2166 bool
2167 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2168 {
2169         struct hns3_hw *hw = &hns->hw;
2170         enum hns3_reset_level reset;
2171
2172         hns3vf_check_event_cause(hns, NULL);
2173         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2174         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2175                 hns3_warn(hw, "High level reset %d is pending", reset);
2176                 return true;
2177         }
2178         return false;
2179 }
2180
2181 static int
2182 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2183 {
2184         struct hns3_hw *hw = &hns->hw;
2185         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2186         struct timeval tv;
2187
2188         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2189                 /*
2190                  * After vf reset is ready, the PF may not have completed
2191                  * the reset processing. The vf sending mbox to PF may fail
2192                  * during the pf reset, so it is better to add extra delay.
2193                  */
2194                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2195                     hw->reset.level == HNS3_FLR_RESET)
2196                         return 0;
2197                 /* Reset retry process, no need to add extra delay. */
2198                 if (hw->reset.attempts)
2199                         return 0;
2200                 if (wait_data->check_completion == NULL)
2201                         return 0;
2202
2203                 wait_data->check_completion = NULL;
2204                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2205                 wait_data->count = 1;
2206                 wait_data->result = HNS3_WAIT_REQUEST;
2207                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2208                                   wait_data);
2209                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2210                 return -EAGAIN;
2211         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2212                 gettimeofday(&tv, NULL);
2213                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2214                           tv.tv_sec, tv.tv_usec);
2215                 return -ETIME;
2216         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2217                 return -EAGAIN;
2218
2219         wait_data->hns = hns;
2220         wait_data->check_completion = is_vf_reset_done;
2221         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2222                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2223         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2224         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2225         wait_data->result = HNS3_WAIT_REQUEST;
2226         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2227         return -EAGAIN;
2228 }
2229
2230 static int
2231 hns3vf_prepare_reset(struct hns3_adapter *hns)
2232 {
2233         struct hns3_hw *hw = &hns->hw;
2234         int ret = 0;
2235
2236         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2237                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2238                                         0, true, NULL, 0);
2239         }
2240         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2241
2242         return ret;
2243 }
2244
2245 static int
2246 hns3vf_stop_service(struct hns3_adapter *hns)
2247 {
2248         struct hns3_hw *hw = &hns->hw;
2249         struct rte_eth_dev *eth_dev;
2250
2251         eth_dev = &rte_eth_devices[hw->data->port_id];
2252         if (hw->adapter_state == HNS3_NIC_STARTED)
2253                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2254         hw->mac.link_status = ETH_LINK_DOWN;
2255
2256         hns3_set_rxtx_function(eth_dev);
2257         rte_wmb();
2258         /* Disable datapath on secondary process. */
2259         hns3_mp_req_stop_rxtx(eth_dev);
2260         rte_delay_ms(hw->tqps_num);
2261
2262         rte_spinlock_lock(&hw->lock);
2263         if (hw->adapter_state == HNS3_NIC_STARTED ||
2264             hw->adapter_state == HNS3_NIC_STOPPING) {
2265                 hns3vf_do_stop(hns);
2266                 hw->reset.mbuf_deferred_free = true;
2267         } else
2268                 hw->reset.mbuf_deferred_free = false;
2269
2270         /*
2271          * It is cumbersome for hardware to pick-and-choose entries for deletion
2272          * from table space. Hence, for function reset software intervention is
2273          * required to delete the entries.
2274          */
2275         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2276                 hns3vf_configure_all_mc_mac_addr(hns, true);
2277         rte_spinlock_unlock(&hw->lock);
2278
2279         return 0;
2280 }
2281
2282 static int
2283 hns3vf_start_service(struct hns3_adapter *hns)
2284 {
2285         struct hns3_hw *hw = &hns->hw;
2286         struct rte_eth_dev *eth_dev;
2287
2288         eth_dev = &rte_eth_devices[hw->data->port_id];
2289         hns3_set_rxtx_function(eth_dev);
2290         hns3_mp_req_start_rxtx(eth_dev);
2291         if (hw->adapter_state == HNS3_NIC_STARTED) {
2292                 hns3vf_service_handler(eth_dev);
2293
2294                 /* Enable interrupt of all rx queues before enabling queues */
2295                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2296                 /*
2297                  * When finished the initialization, enable queues to receive
2298                  * and transmit packets.
2299                  */
2300                 hns3_enable_all_queues(hw, true);
2301         }
2302
2303         return 0;
2304 }
2305
2306 static int
2307 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2308 {
2309         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2310         struct rte_ether_addr *hw_mac;
2311         int ret;
2312
2313         /*
2314          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2315          * on the host by "ip link set ..." command. If the hns3 PF kernel
2316          * ethdev driver sets the MAC address for VF device after the
2317          * initialization of the related VF device, the PF driver will notify
2318          * VF driver to reset VF device to make the new MAC address effective
2319          * immediately. The hns3 VF PMD driver should check whether the MAC
2320          * address has been changed by the PF kernel ethdev driver, if changed
2321          * VF driver should configure hardware using the new MAC address in the
2322          * recovering hardware configuration stage of the reset process.
2323          */
2324         ret = hns3vf_get_host_mac_addr(hw);
2325         if (ret)
2326                 return ret;
2327
2328         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2329         ret = rte_is_zero_ether_addr(hw_mac);
2330         if (ret) {
2331                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2332         } else {
2333                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2334                 if (!ret) {
2335                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2336                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2337                                               &hw->data->mac_addrs[0]);
2338                         hns3_warn(hw, "Default MAC address has been changed to:"
2339                                   " %s by the host PF kernel ethdev driver",
2340                                   mac_str);
2341                 }
2342         }
2343
2344         return 0;
2345 }
2346
2347 static int
2348 hns3vf_restore_conf(struct hns3_adapter *hns)
2349 {
2350         struct hns3_hw *hw = &hns->hw;
2351         int ret;
2352
2353         ret = hns3vf_check_default_mac_change(hw);
2354         if (ret)
2355                 return ret;
2356
2357         ret = hns3vf_configure_mac_addr(hns, false);
2358         if (ret)
2359                 return ret;
2360
2361         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2362         if (ret)
2363                 goto err_mc_mac;
2364
2365         ret = hns3vf_restore_promisc(hns);
2366         if (ret)
2367                 goto err_vlan_table;
2368
2369         ret = hns3vf_restore_vlan_conf(hns);
2370         if (ret)
2371                 goto err_vlan_table;
2372
2373         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2374         if (ret)
2375                 goto err_vlan_table;
2376
2377         ret = hns3vf_restore_rx_interrupt(hw);
2378         if (ret)
2379                 goto err_vlan_table;
2380
2381         ret = hns3_restore_gro_conf(hw);
2382         if (ret)
2383                 goto err_vlan_table;
2384
2385         if (hw->adapter_state == HNS3_NIC_STARTED) {
2386                 ret = hns3vf_do_start(hns, false);
2387                 if (ret)
2388                         goto err_vlan_table;
2389                 hns3_info(hw, "hns3vf dev restart successful!");
2390         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2391                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2392         return 0;
2393
2394 err_vlan_table:
2395         hns3vf_configure_all_mc_mac_addr(hns, true);
2396 err_mc_mac:
2397         hns3vf_configure_mac_addr(hns, true);
2398         return ret;
2399 }
2400
2401 static enum hns3_reset_level
2402 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2403 {
2404         enum hns3_reset_level reset_level;
2405
2406         /* return the highest priority reset level amongst all */
2407         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2408                 reset_level = HNS3_VF_RESET;
2409         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2410                 reset_level = HNS3_VF_FULL_RESET;
2411         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2412                 reset_level = HNS3_VF_PF_FUNC_RESET;
2413         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2414                 reset_level = HNS3_VF_FUNC_RESET;
2415         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2416                 reset_level = HNS3_FLR_RESET;
2417         else
2418                 reset_level = HNS3_NONE_RESET;
2419
2420         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2421                 return HNS3_NONE_RESET;
2422
2423         return reset_level;
2424 }
2425
2426 static void
2427 hns3vf_reset_service(void *param)
2428 {
2429         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2430         struct hns3_hw *hw = &hns->hw;
2431         enum hns3_reset_level reset_level;
2432         struct timeval tv_delta;
2433         struct timeval tv_start;
2434         struct timeval tv;
2435         uint64_t msec;
2436
2437         /*
2438          * The interrupt is not triggered within the delay time.
2439          * The interrupt may have been lost. It is necessary to handle
2440          * the interrupt to recover from the error.
2441          */
2442         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2443                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2444                 hns3_err(hw, "Handling interrupts in delayed tasks");
2445                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2446                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2447                 if (reset_level == HNS3_NONE_RESET) {
2448                         hns3_err(hw, "No reset level is set, try global reset");
2449                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2450                 }
2451         }
2452         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2453
2454         /*
2455          * Hardware reset has been notified, we now have to poll & check if
2456          * hardware has actually completed the reset sequence.
2457          */
2458         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2459         if (reset_level != HNS3_NONE_RESET) {
2460                 gettimeofday(&tv_start, NULL);
2461                 hns3_reset_process(hns, reset_level);
2462                 gettimeofday(&tv, NULL);
2463                 timersub(&tv, &tv_start, &tv_delta);
2464                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2465                        tv_delta.tv_usec / USEC_PER_MSEC;
2466                 if (msec > HNS3_RESET_PROCESS_MS)
2467                         hns3_err(hw, "%d handle long time delta %" PRIx64
2468                                  " ms time=%ld.%.6ld",
2469                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2470         }
2471 }
2472
2473 static int
2474 hns3vf_reinit_dev(struct hns3_adapter *hns)
2475 {
2476         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2477         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2478         struct hns3_hw *hw = &hns->hw;
2479         int ret;
2480
2481         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2482                 rte_intr_disable(&pci_dev->intr_handle);
2483                 hns3vf_set_bus_master(pci_dev, true);
2484         }
2485
2486         /* Firmware command initialize */
2487         ret = hns3_cmd_init(hw);
2488         if (ret) {
2489                 hns3_err(hw, "Failed to init cmd: %d", ret);
2490                 return ret;
2491         }
2492
2493         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2494                 /*
2495                  * UIO enables msix by writing the pcie configuration space
2496                  * vfio_pci enables msix in rte_intr_enable.
2497                  */
2498                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2499                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2500                         if (hns3vf_enable_msix(pci_dev, true))
2501                                 hns3_err(hw, "Failed to enable msix");
2502                 }
2503
2504                 rte_intr_enable(&pci_dev->intr_handle);
2505         }
2506
2507         ret = hns3_reset_all_queues(hns);
2508         if (ret) {
2509                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2510                 return ret;
2511         }
2512
2513         ret = hns3vf_init_hardware(hns);
2514         if (ret) {
2515                 hns3_err(hw, "Failed to init hardware: %d", ret);
2516                 return ret;
2517         }
2518
2519         return 0;
2520 }
2521
2522 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2523         .dev_configure      = hns3vf_dev_configure,
2524         .dev_start          = hns3vf_dev_start,
2525         .dev_stop           = hns3vf_dev_stop,
2526         .dev_close          = hns3vf_dev_close,
2527         .mtu_set            = hns3vf_dev_mtu_set,
2528         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2529         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2530         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2531         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2532         .stats_get          = hns3_stats_get,
2533         .stats_reset        = hns3_stats_reset,
2534         .xstats_get         = hns3_dev_xstats_get,
2535         .xstats_get_names   = hns3_dev_xstats_get_names,
2536         .xstats_reset       = hns3_dev_xstats_reset,
2537         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2538         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2539         .dev_infos_get      = hns3vf_dev_infos_get,
2540         .fw_version_get     = hns3vf_fw_version_get,
2541         .rx_queue_setup     = hns3_rx_queue_setup,
2542         .tx_queue_setup     = hns3_tx_queue_setup,
2543         .rx_queue_release   = hns3_dev_rx_queue_release,
2544         .tx_queue_release   = hns3_dev_tx_queue_release,
2545         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2546         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2547         .rxq_info_get       = hns3_rxq_info_get,
2548         .txq_info_get       = hns3_txq_info_get,
2549         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2550         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2551         .mac_addr_add       = hns3vf_add_mac_addr,
2552         .mac_addr_remove    = hns3vf_remove_mac_addr,
2553         .mac_addr_set       = hns3vf_set_default_mac_addr,
2554         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2555         .link_update        = hns3vf_dev_link_update,
2556         .rss_hash_update    = hns3_dev_rss_hash_update,
2557         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2558         .reta_update        = hns3_dev_rss_reta_update,
2559         .reta_query         = hns3_dev_rss_reta_query,
2560         .filter_ctrl        = hns3_dev_filter_ctrl,
2561         .vlan_filter_set    = hns3vf_vlan_filter_set,
2562         .vlan_offload_set   = hns3vf_vlan_offload_set,
2563         .get_reg            = hns3_get_regs,
2564         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2565 };
2566
2567 static const struct hns3_reset_ops hns3vf_reset_ops = {
2568         .reset_service       = hns3vf_reset_service,
2569         .stop_service        = hns3vf_stop_service,
2570         .prepare_reset       = hns3vf_prepare_reset,
2571         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2572         .reinit_dev          = hns3vf_reinit_dev,
2573         .restore_conf        = hns3vf_restore_conf,
2574         .start_service       = hns3vf_start_service,
2575 };
2576
2577 static int
2578 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2579 {
2580         struct hns3_adapter *hns = eth_dev->data->dev_private;
2581         struct hns3_hw *hw = &hns->hw;
2582         int ret;
2583
2584         PMD_INIT_FUNC_TRACE();
2585
2586         eth_dev->process_private = (struct hns3_process_private *)
2587             rte_zmalloc_socket("hns3_filter_list",
2588                                sizeof(struct hns3_process_private),
2589                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2590         if (eth_dev->process_private == NULL) {
2591                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2592                 return -ENOMEM;
2593         }
2594
2595         /* initialize flow filter lists */
2596         hns3_filterlist_init(eth_dev);
2597
2598         hns3_set_rxtx_function(eth_dev);
2599         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2600         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2601                 ret = hns3_mp_init_secondary();
2602                 if (ret) {
2603                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2604                                           "process, ret = %d", ret);
2605                         goto err_mp_init_secondary;
2606                 }
2607
2608                 hw->secondary_cnt++;
2609                 return 0;
2610         }
2611
2612         ret = hns3_mp_init_primary();
2613         if (ret) {
2614                 PMD_INIT_LOG(ERR,
2615                              "Failed to init for primary process, ret = %d",
2616                              ret);
2617                 goto err_mp_init_primary;
2618         }
2619
2620         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2621         hns->is_vf = true;
2622         hw->data = eth_dev->data;
2623
2624         ret = hns3_reset_init(hw);
2625         if (ret)
2626                 goto err_init_reset;
2627         hw->reset.ops = &hns3vf_reset_ops;
2628
2629         ret = hns3vf_init_vf(eth_dev);
2630         if (ret) {
2631                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2632                 goto err_init_vf;
2633         }
2634
2635         /* Allocate memory for storing MAC addresses */
2636         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2637                                                sizeof(struct rte_ether_addr) *
2638                                                HNS3_VF_UC_MACADDR_NUM, 0);
2639         if (eth_dev->data->mac_addrs == NULL) {
2640                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2641                              "to store MAC addresses",
2642                              sizeof(struct rte_ether_addr) *
2643                              HNS3_VF_UC_MACADDR_NUM);
2644                 ret = -ENOMEM;
2645                 goto err_rte_zmalloc;
2646         }
2647
2648         /*
2649          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2650          * on the host by "ip link set ..." command. To avoid some incorrect
2651          * scenes, for example, hns3 VF PMD driver fails to receive and send
2652          * packets after user configure the MAC address by using the
2653          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2654          * address strategy as the hns3 kernel ethdev driver in the
2655          * initialization. If user configure a MAC address by the ip command
2656          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2657          * start with a random MAC address in the initialization.
2658          */
2659         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2660                 rte_eth_random_addr(hw->mac.mac_addr);
2661         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2662                             &eth_dev->data->mac_addrs[0]);
2663
2664         hw->adapter_state = HNS3_NIC_INITIALIZED;
2665         /*
2666          * Pass the information to the rte_eth_dev_close() that it should also
2667          * release the private port resources.
2668          */
2669         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2670
2671         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2672                 hns3_err(hw, "Reschedule reset service after dev_init");
2673                 hns3_schedule_reset(hns);
2674         } else {
2675                 /* IMP will wait ready flag before reset */
2676                 hns3_notify_reset_ready(hw, false);
2677         }
2678         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2679                           eth_dev);
2680         return 0;
2681
2682 err_rte_zmalloc:
2683         hns3vf_uninit_vf(eth_dev);
2684
2685 err_init_vf:
2686         rte_free(hw->reset.wait_data);
2687
2688 err_init_reset:
2689         hns3_mp_uninit_primary();
2690
2691 err_mp_init_primary:
2692 err_mp_init_secondary:
2693         eth_dev->dev_ops = NULL;
2694         eth_dev->rx_pkt_burst = NULL;
2695         eth_dev->tx_pkt_burst = NULL;
2696         eth_dev->tx_pkt_prepare = NULL;
2697         rte_free(eth_dev->process_private);
2698         eth_dev->process_private = NULL;
2699
2700         return ret;
2701 }
2702
2703 static int
2704 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2705 {
2706         struct hns3_adapter *hns = eth_dev->data->dev_private;
2707         struct hns3_hw *hw = &hns->hw;
2708
2709         PMD_INIT_FUNC_TRACE();
2710
2711         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2712                 return -EPERM;
2713
2714         eth_dev->dev_ops = NULL;
2715         eth_dev->rx_pkt_burst = NULL;
2716         eth_dev->tx_pkt_burst = NULL;
2717         eth_dev->tx_pkt_prepare = NULL;
2718
2719         if (hw->adapter_state < HNS3_NIC_CLOSING)
2720                 hns3vf_dev_close(eth_dev);
2721
2722         hw->adapter_state = HNS3_NIC_REMOVED;
2723         return 0;
2724 }
2725
2726 static int
2727 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2728                      struct rte_pci_device *pci_dev)
2729 {
2730         return rte_eth_dev_pci_generic_probe(pci_dev,
2731                                              sizeof(struct hns3_adapter),
2732                                              hns3vf_dev_init);
2733 }
2734
2735 static int
2736 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2737 {
2738         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2739 }
2740
2741 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2742         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2743         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2744         { .vendor_id = 0, /* sentinel */ },
2745 };
2746
2747 static struct rte_pci_driver rte_hns3vf_pmd = {
2748         .id_table = pci_id_hns3vf_map,
2749         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2750         .probe = eth_hns3vf_pci_probe,
2751         .remove = eth_hns3vf_pci_remove,
2752 };
2753
2754 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2755 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2756 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");