drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 /* set PCI bus mastering */
  63 static void
  64 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  65 {
  66         uint16_t reg;
  67
  68         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  69
  70         if (op)
  71                 /* set the master bit */
  72                 reg |= PCI_COMMAND_MASTER;
  73         else
  74                 reg &= ~(PCI_COMMAND_MASTER);
  75
  76         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  77 }
  78
  79 /**
  80  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  81  * @cap: the capability
  82  *
  83  * Return the address of the given capability within the PCI capability list.
  84  */
  85 static int
  86 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  87 {
  88 #define MAX_PCIE_CAPABILITY 48
  89         uint16_t status;
  90         uint8_t pos;
  91         uint8_t id;
  92         int ttl;
  93
  94         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 100         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 101                 rte_pci_read_config(device, &id, sizeof(id),
 102                                     (pos + PCI_CAP_LIST_ID));
 103
 104                 if (id == 0xFF)
 105                         break;
 106
 107                 if (id == cap)
 108                         return (int)pos;
 109
 110                 rte_pci_read_config(device, &pos, sizeof(pos),
 111                                     (pos + PCI_CAP_LIST_NEXT));
 112         }
 113         return 0;
 114 }
 115
 116 static int
 117 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 118 {
 119         uint16_t control;
 120         int pos;
 121
 122         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 123         if (pos) {
 124                 rte_pci_read_config(device, &control, sizeof(control),
 125                                     (pos + PCI_MSIX_FLAGS));
 126                 if (op)
 127                         control |= PCI_MSIX_FLAGS_ENABLE;
 128                 else
 129                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 130                 rte_pci_write_config(device, &control, sizeof(control),
 131                                      (pos + PCI_MSIX_FLAGS));
 132                 return 0;
 133         }
 134         return -ENXIO;
 135 }
 136
 137 static int
 138 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 139                     __rte_unused uint32_t idx,
 140                     __rte_unused uint32_t pool)
 141 {
 142         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 143         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 144         int ret;
 145
 146         rte_spinlock_lock(&hw->lock);
 147         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 148                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 149                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 150         rte_spinlock_unlock(&hw->lock);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "Failed to add mac addr(%s) for vf: %d", mac_str,
 155                          ret);
 156         }
 157
 158         return ret;
 159 }
 160
 161 static void
 162 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 163 {
 164         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 165         /* index will be checked by upper level rte interface */
 166         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 167         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 168         int ret;
 169
 170         rte_spinlock_lock(&hw->lock);
 171         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 172                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 173                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 174                                 NULL, 0);
 175         rte_spinlock_unlock(&hw->lock);
 176         if (ret) {
 177                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 178                                       mac_addr);
 179                 hns3_err(hw, "Failed to remove mac addr(%s) for vf: %d",
 180                          mac_str, ret);
 181         }
 182 }
 183
 184 static int
 185 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 186                             struct rte_ether_addr *mac_addr)
 187 {
 188 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 189         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 190         struct rte_ether_addr *old_addr;
 191         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 192         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 193         int ret;
 194
 195         /*
 196          * It has been guaranteed that input parameter named mac_addr is valid
 197          * address in the rte layer of DPDK framework.
 198          */
 199         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 200         rte_spinlock_lock(&hw->lock);
 201         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 202         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 203                RTE_ETHER_ADDR_LEN);
 204
 205         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 206                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 207                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 208         if (ret) {
 209                 /*
 210                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 211                  * driver. When user has configured a MAC address for VF device
 212                  * by "ip link set ..." command based on the PF device, the hns3
 213                  * PF kernel ethdev driver does not allow VF driver to request
 214                  * reconfiguring a different default MAC address, and return
 215                  * -EPREM to VF driver through mailbox.
 216                  */
 217                 if (ret == -EPERM) {
 218                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 219                                               old_addr);
 220                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 221                                   mac_str);
 222                 } else {
 223                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 224                                               mac_addr);
 225                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 226                                  mac_str, ret);
 227                 }
 228         }
 229
 230         rte_ether_addr_copy(mac_addr,
 231                             (struct rte_ether_addr *)hw->mac.mac_addr);
 232         rte_spinlock_unlock(&hw->lock);
 233
 234         return ret;
 235 }
 236
 237 static int
 238 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 239 {
 240         struct hns3_hw *hw = &hns->hw;
 241         struct rte_ether_addr *addr;
 242         enum hns3_mbx_mac_vlan_subcode opcode;
 243         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 244         int ret = 0;
 245         int i;
 246
 247         if (del)
 248                 opcode = HNS3_MBX_MAC_VLAN_UC_REMOVE;
 249         else
 250                 opcode = HNS3_MBX_MAC_VLAN_UC_ADD;
 251         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 252                 addr = &hw->data->mac_addrs[i];
 253                 if (!rte_is_valid_assigned_ether_addr(addr))
 254                         continue;
 255                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 256                 hns3_dbg(hw, "rm mac addr: %s", mac_str);
 257                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, opcode,
 258                                         addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 259                                         false, NULL, 0);
 260                 if (ret) {
 261                         hns3_err(hw, "Failed to remove mac addr for vf: %d",
 262                                  ret);
 263                         break;
 264                 }
 265         }
 266         return ret;
 267 }
 268
 269 static int
 270 hns3vf_add_mc_mac_addr(struct hns3_adapter *hns,
 271                        struct rte_ether_addr *mac_addr)
 272 {
 273         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 274         struct hns3_hw *hw = &hns->hw;
 275         int ret;
 276
 277         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 278                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 279                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 280                                 NULL, 0);
 281         if (ret) {
 282                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 283                                       mac_addr);
 284                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 285                          mac_str, ret);
 286         }
 287
 288         return ret;
 289 }
 290
 291 static int
 292 hns3vf_remove_mc_mac_addr(struct hns3_adapter *hns,
 293                           struct rte_ether_addr *mac_addr)
 294 {
 295         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 296         struct hns3_hw *hw = &hns->hw;
 297         int ret;
 298
 299         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 300                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 301                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 302                                 NULL, 0);
 303         if (ret) {
 304                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 305                                       mac_addr);
 306                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 307                          mac_str, ret);
 308         }
 309
 310         return ret;
 311 }
 312
 313 static int
 314 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 315                             struct rte_ether_addr *mc_addr_set,
 316                             uint32_t nb_mc_addr)
 317 {
 318         struct hns3_adapter *hns = dev->data->dev_private;
 319         struct hns3_hw *hw = &hns->hw;
 320         struct rte_ether_addr *addr;
 321         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 322         int cur_addr_num;
 323         int set_addr_num;
 324         int num;
 325         int ret;
 326         int i;
 327
 328         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 329                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 330                          "invalid. valid range: 0~%d",
 331                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 332                 return -EINVAL;
 333         }
 334
 335         set_addr_num = (int)nb_mc_addr;
 336         for (i = 0; i < set_addr_num; i++) {
 337                 addr = &mc_addr_set[i];
 338                 if (!rte_is_multicast_ether_addr(addr)) {
 339                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 340                                               addr);
 341                         hns3_err(hw,
 342                                  "Failed to set mc mac addr, addr(%s) invalid.",
 343                                  mac_str);
 344                         return -EINVAL;
 345                 }
 346         }
 347         rte_spinlock_lock(&hw->lock);
 348         cur_addr_num = hw->mc_addrs_num;
 349         for (i = 0; i < cur_addr_num; i++) {
 350                 num = cur_addr_num - i - 1;
 351                 addr = &hw->mc_addrs[num];
 352                 ret = hns3vf_remove_mc_mac_addr(hns, addr);
 353                 if (ret) {
 354                         rte_spinlock_unlock(&hw->lock);
 355                         return ret;
 356                 }
 357
 358                 hw->mc_addrs_num--;
 359         }
 360
 361         for (i = 0; i < set_addr_num; i++) {
 362                 addr = &mc_addr_set[i];
 363                 ret = hns3vf_add_mc_mac_addr(hns, addr);
 364                 if (ret) {
 365                         rte_spinlock_unlock(&hw->lock);
 366                         return ret;
 367                 }
 368
 369                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 370                 hw->mc_addrs_num++;
 371         }
 372         rte_spinlock_unlock(&hw->lock);
 373
 374         return 0;
 375 }
 376
 377 static int
 378 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 379 {
 380         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 381         struct hns3_hw *hw = &hns->hw;
 382         struct rte_ether_addr *addr;
 383         int err = 0;
 384         int ret;
 385         int i;
 386
 387         for (i = 0; i < hw->mc_addrs_num; i++) {
 388                 addr = &hw->mc_addrs[i];
 389                 if (!rte_is_multicast_ether_addr(addr))
 390                         continue;
 391                 if (del)
 392                         ret = hns3vf_remove_mc_mac_addr(hns, addr);
 393                 else
 394                         ret = hns3vf_add_mc_mac_addr(hns, addr);
 395                 if (ret) {
 396                         err = ret;
 397                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 398                                               addr);
 399                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 400                                  del ? "Remove" : "Restore", mac_str, ret);
 401                 }
 402         }
 403         return err;
 404 }
 405
 406 static int
 407 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 408                         bool en_uc_pmc, bool en_mc_pmc)
 409 {
 410         struct hns3_mbx_vf_to_pf_cmd *req;
 411         struct hns3_cmd_desc desc;
 412         int ret;
 413
 414         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 415
 416         /*
 417          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 418          * so there are some features for promiscuous/allmulticast mode in hns3
 419          * VF PMD driver as below:
 420          * 1. The promiscuous/allmulticast mode can be configured successfully
 421          *    only based on the trusted VF device. If based on the non trusted
 422          *    VF device, configuring promiscuous/allmulticast mode will fail.
 423          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 424          *    kernel ethdev driver on the host by the following command:
 425          *      "ip link set <eth num> vf <vf id> turst on"
 426          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 427          *    driver can receive the ingress and outgoing traffic. In the words,
 428          *    all the ingress packets, all the packets sent from the PF and
 429          *    other VFs on the same physical port.
 430          * 3. Note: Because of the hardware constraints, By default vlan filter
 431          *    is enabled and couldn't be turned off based on VF device, so vlan
 432          *    filter is still effective even in promiscuous mode. If upper
 433          *    applications don't call rte_eth_dev_vlan_filter API function to
 434          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 435          *    the packets with vlan tag in promiscuoue mode.
 436          */
 437         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 438         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 439         req->msg[1] = en_bc_pmc ? 1 : 0;
 440         req->msg[2] = en_uc_pmc ? 1 : 0;
 441         req->msg[3] = en_mc_pmc ? 1 : 0;
 442
 443         ret = hns3_cmd_send(hw, &desc, 1);
 444         if (ret)
 445                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 446
 447         return ret;
 448 }
 449
 450 static int
 451 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 452 {
 453         struct hns3_adapter *hns = dev->data->dev_private;
 454         struct hns3_hw *hw = &hns->hw;
 455         int ret;
 456
 457         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 458         if (ret)
 459                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 460                         ret);
 461         return ret;
 462 }
 463
 464 static int
 465 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 466 {
 467         bool allmulti = dev->data->all_multicast ? true : false;
 468         struct hns3_adapter *hns = dev->data->dev_private;
 469         struct hns3_hw *hw = &hns->hw;
 470         int ret;
 471
 472         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 473         if (ret)
 474                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 475                         ret);
 476         return ret;
 477 }
 478
 479 static int
 480 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 481 {
 482         struct hns3_adapter *hns = dev->data->dev_private;
 483         struct hns3_hw *hw = &hns->hw;
 484         int ret;
 485
 486         if (dev->data->promiscuous)
 487                 return 0;
 488
 489         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 490         if (ret)
 491                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 492                         ret);
 493         return ret;
 494 }
 495
 496 static int
 497 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 498 {
 499         struct hns3_adapter *hns = dev->data->dev_private;
 500         struct hns3_hw *hw = &hns->hw;
 501         int ret;
 502
 503         if (dev->data->promiscuous)
 504                 return 0;
 505
 506         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 507         if (ret)
 508                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 509                         ret);
 510         return ret;
 511 }
 512
 513 static int
 514 hns3vf_restore_promisc(struct hns3_adapter *hns)
 515 {
 516         struct hns3_hw *hw = &hns->hw;
 517         bool allmulti = hw->data->all_multicast ? true : false;
 518
 519         if (hw->data->promiscuous)
 520                 return hns3vf_set_promisc_mode(hw, true, true, true);
 521
 522         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 523 }
 524
 525 static int
 526 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 527                              bool mmap, enum hns3_ring_type queue_type,
 528                              uint16_t queue_id)
 529 {
 530         struct hns3_vf_bind_vector_msg bind_msg;
 531         const char *op_str;
 532         uint16_t code;
 533         int ret;
 534
 535         memset(&bind_msg, 0, sizeof(bind_msg));
 536         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 537                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 538         bind_msg.vector_id = vector_id;
 539
 540         if (queue_type == HNS3_RING_TYPE_RX)
 541                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 542         else
 543                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 544
 545         bind_msg.param[0].ring_type = queue_type;
 546         bind_msg.ring_num = 1;
 547         bind_msg.param[0].tqp_index = queue_id;
 548         op_str = mmap ? "Map" : "Unmap";
 549         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 550                                 sizeof(bind_msg), false, NULL, 0);
 551         if (ret)
 552                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 553                          op_str, queue_id, bind_msg.vector_id, ret);
 554
 555         return ret;
 556 }
 557
 558 static int
 559 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 560 {
 561         uint8_t vec;
 562         int ret;
 563         int i;
 564
 565         /*
 566          * In hns3 network engine, vector 0 is always the misc interrupt of this
 567          * function, vector 1~N can be used respectively for the queues of the
 568          * function. Tx and Rx queues with the same number share the interrupt
 569          * vector. In the initialization clearing the all hardware mapping
 570          * relationship configurations between queues and interrupt vectors is
 571          * needed, so some error caused by the residual configurations, such as
 572          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 573          * constraints in hns3 hardware engine, we have to implement clearing
 574          * the mapping relationship configurations by binding all queues to the
 575          * last interrupt vector and reserving the last interrupt vector. This
 576          * method results in a decrease of the maximum queues when upper
 577          * applications call the rte_eth_dev_configure API function to enable
 578          * Rx interrupt.
 579          */
 580         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 581         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
 582         for (i = 0; i < hw->intr_tqps_num; i++) {
 583                 /*
 584                  * Set gap limiter and rate limiter configuration of queue's
 585                  * interrupt.
 586                  */
 587                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 588                                        HNS3_TQP_INTR_GL_DEFAULT);
 589                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 590                                        HNS3_TQP_INTR_GL_DEFAULT);
 591                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 592
 593                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 594                                                    HNS3_RING_TYPE_TX, i);
 595                 if (ret) {
 596                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 597                                           "vector: %d, ret=%d", i, vec, ret);
 598                         return ret;
 599                 }
 600
 601                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 602                                                    HNS3_RING_TYPE_RX, i);
 603                 if (ret) {
 604                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 605                                           "vector: %d, ret=%d", i, vec, ret);
 606                         return ret;
 607                 }
 608         }
 609
 610         return 0;
 611 }
 612
 613 static int
 614 hns3vf_dev_configure(struct rte_eth_dev *dev)
 615 {
 616         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 617         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 618         struct rte_eth_conf *conf = &dev->data->dev_conf;
 619         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 620         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 621         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 622         struct rte_eth_rss_conf rss_conf;
 623         uint16_t mtu;
 624         int ret;
 625
 626         /*
 627          * Hardware does not support individually enable/disable/reset the Tx or
 628          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 629          * and Rx queues at the same time. When the numbers of Tx queues
 630          * allocated by upper applications are not equal to the numbers of Rx
 631          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 632          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 633          * these fake queues are imperceptible, and can not be used by upper
 634          * applications.
 635          */
 636         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 637         if (ret) {
 638                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 639                 return ret;
 640         }
 641
 642         hw->adapter_state = HNS3_NIC_CONFIGURING;
 643         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 644                 hns3_err(hw, "setting link speed/duplex not supported");
 645                 ret = -EINVAL;
 646                 goto cfg_err;
 647         }
 648
 649         /* When RSS is not configured, redirect the packet queue 0 */
 650         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 651                 rss_conf = conf->rx_adv_conf.rss_conf;
 652                 if (rss_conf.rss_key == NULL) {
 653                         rss_conf.rss_key = rss_cfg->key;
 654                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 655                 }
 656
 657                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 658                 if (ret)
 659                         goto cfg_err;
 660         }
 661
 662         /*
 663          * If jumbo frames are enabled, MTU needs to be refreshed
 664          * according to the maximum RX packet length.
 665          */
 666         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 667                 /*
 668                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 669                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 670                  * can safely assign to "uint16_t" type variable.
 671                  */
 672                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 673                 ret = hns3vf_dev_mtu_set(dev, mtu);
 674                 if (ret)
 675                         goto cfg_err;
 676                 dev->data->mtu = mtu;
 677         }
 678
 679         ret = hns3vf_dev_configure_vlan(dev);
 680         if (ret)
 681                 goto cfg_err;
 682
 683         hw->adapter_state = HNS3_NIC_CONFIGURED;
 684         return 0;
 685
 686 cfg_err:
 687         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 688         hw->adapter_state = HNS3_NIC_INITIALIZED;
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 695 {
 696         int ret;
 697
 698         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 699                                 sizeof(mtu), true, NULL, 0);
 700         if (ret)
 701                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 702
 703         return ret;
 704 }
 705
 706 static int
 707 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 708 {
 709         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 711         int ret;
 712
 713         /*
 714          * The hns3 PF/VF devices on the same port share the hardware MTU
 715          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 716          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 717          * driver, there is no need to stop the port for hns3 VF device, and the
 718          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 719          * PF's MTU.
 720          */
 721         if (rte_atomic16_read(&hw->reset.resetting)) {
 722                 hns3_err(hw, "Failed to set mtu during resetting");
 723                 return -EIO;
 724         }
 725
 726         rte_spinlock_lock(&hw->lock);
 727         ret = hns3vf_config_mtu(hw, mtu);
 728         if (ret) {
 729                 rte_spinlock_unlock(&hw->lock);
 730                 return ret;
 731         }
 732         if (frame_size > RTE_ETHER_MAX_LEN)
 733                 dev->data->dev_conf.rxmode.offloads |=
 734                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 735         else
 736                 dev->data->dev_conf.rxmode.offloads &=
 737                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 738         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 739         rte_spinlock_unlock(&hw->lock);
 740
 741         return 0;
 742 }
 743
 744 static int
 745 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 746 {
 747         struct hns3_adapter *hns = eth_dev->data->dev_private;
 748         struct hns3_hw *hw = &hns->hw;
 749         uint16_t q_num = hw->tqps_num;
 750
 751         /*
 752          * In interrupt mode, 'max_rx_queues' is set based on the number of
 753          * MSI-X interrupt resources of the hardware.
 754          */
 755         if (hw->data->dev_conf.intr_conf.rxq == 1)
 756                 q_num = hw->intr_tqps_num;
 757
 758         info->max_rx_queues = q_num;
 759         info->max_tx_queues = hw->tqps_num;
 760         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 761         info->min_rx_bufsize = hw->rx_buf_len;
 762         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 763         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 764
 765         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 766                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 767                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 768                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 769                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 770                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 771                                  DEV_RX_OFFLOAD_KEEP_CRC |
 772                                  DEV_RX_OFFLOAD_SCATTER |
 773                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 774                                  DEV_RX_OFFLOAD_QINQ_STRIP |
 775                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 776                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
 777         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 778         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 779                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 780                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 781                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 782                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 783                                  DEV_TX_OFFLOAD_VLAN_INSERT |
 784                                  DEV_TX_OFFLOAD_QINQ_INSERT |
 785                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 786                                  DEV_TX_OFFLOAD_TCP_TSO |
 787                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 788                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 789                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 790                                  info->tx_queue_offload_capa);
 791
 792         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 793                 .nb_max = HNS3_MAX_RING_DESC,
 794                 .nb_min = HNS3_MIN_RING_DESC,
 795                 .nb_align = HNS3_ALIGN_RING_DESC,
 796         };
 797
 798         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 799                 .nb_max = HNS3_MAX_RING_DESC,
 800                 .nb_min = HNS3_MIN_RING_DESC,
 801                 .nb_align = HNS3_ALIGN_RING_DESC,
 802         };
 803
 804         info->vmdq_queue_num = 0;
 805
 806         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 807         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 808         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 809         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 810         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 811
 812         return 0;
 813 }
 814
 815 static void
 816 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 817 {
 818         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 819 }
 820
 821 static void
 822 hns3vf_disable_irq0(struct hns3_hw *hw)
 823 {
 824         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 825 }
 826
 827 static void
 828 hns3vf_enable_irq0(struct hns3_hw *hw)
 829 {
 830         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 831 }
 832
 833 static enum hns3vf_evt_cause
 834 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 835 {
 836         struct hns3_hw *hw = &hns->hw;
 837         enum hns3vf_evt_cause ret;
 838         uint32_t cmdq_stat_reg;
 839         uint32_t rst_ing_reg;
 840         uint32_t val;
 841
 842         /* Fetch the events from their corresponding regs */
 843         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 844
 845         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 846                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 847                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 848                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 849                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 850                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 851                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 852                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 853                 if (clearval) {
 854                         hw->reset.stats.global_cnt++;
 855                         hns3_warn(hw, "Global reset detected, clear reset status");
 856                 } else {
 857                         hns3_schedule_delayed_reset(hns);
 858                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 859                 }
 860
 861                 ret = HNS3VF_VECTOR0_EVENT_RST;
 862                 goto out;
 863         }
 864
 865         /* Check for vector0 mailbox(=CMDQ RX) event source */
 866         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 867                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 868                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 869                 goto out;
 870         }
 871
 872         val = 0;
 873         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 874 out:
 875         if (clearval)
 876                 *clearval = val;
 877         return ret;
 878 }
 879
 880 static void
 881 hns3vf_interrupt_handler(void *param)
 882 {
 883         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 884         struct hns3_adapter *hns = dev->data->dev_private;
 885         struct hns3_hw *hw = &hns->hw;
 886         enum hns3vf_evt_cause event_cause;
 887         uint32_t clearval;
 888
 889         if (hw->irq_thread_id == 0)
 890                 hw->irq_thread_id = pthread_self();
 891
 892         /* Disable interrupt */
 893         hns3vf_disable_irq0(hw);
 894
 895         /* Read out interrupt causes */
 896         event_cause = hns3vf_check_event_cause(hns, &clearval);
 897
 898         switch (event_cause) {
 899         case HNS3VF_VECTOR0_EVENT_RST:
 900                 hns3_schedule_reset(hns);
 901                 break;
 902         case HNS3VF_VECTOR0_EVENT_MBX:
 903                 hns3_dev_handle_mbx_msg(hw);
 904                 break;
 905         default:
 906                 break;
 907         }
 908
 909         /* Clear interrupt causes */
 910         hns3vf_clear_event_cause(hw, clearval);
 911
 912         /* Enable interrupt */
 913         hns3vf_enable_irq0(hw);
 914 }
 915
 916 static int
 917 hns3vf_check_tqp_info(struct hns3_hw *hw)
 918 {
 919         uint16_t tqps_num;
 920
 921         tqps_num = hw->tqps_num;
 922         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
 923                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
 924                                   "range: 1~%d",
 925                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
 926                 return -EINVAL;
 927         }
 928
 929         if (hw->rx_buf_len == 0)
 930                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
 931         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
 932
 933         return 0;
 934 }
 935
 936 static int
 937 hns3vf_get_queue_info(struct hns3_hw *hw)
 938 {
 939 #define HNS3VF_TQPS_RSS_INFO_LEN        6
 940         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
 941         int ret;
 942
 943         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
 944                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
 945         if (ret) {
 946                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
 947                 return ret;
 948         }
 949
 950         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
 951         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
 952         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
 953
 954         return hns3vf_check_tqp_info(hw);
 955 }
 956
 957 static int
 958 hns3vf_get_queue_depth(struct hns3_hw *hw)
 959 {
 960 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
 961         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
 962         int ret;
 963
 964         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
 965                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
 966         if (ret) {
 967                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
 968                              ret);
 969                 return ret;
 970         }
 971
 972         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
 973         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
 974
 975         return 0;
 976 }
 977
 978 static int
 979 hns3vf_get_tc_info(struct hns3_hw *hw)
 980 {
 981         uint8_t resp_msg;
 982         int ret;
 983
 984         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
 985                                 true, &resp_msg, sizeof(resp_msg));
 986         if (ret) {
 987                 hns3_err(hw, "VF request to get TC info from PF failed %d",
 988                          ret);
 989                 return ret;
 990         }
 991
 992         hw->hw_tc_map = resp_msg;
 993
 994         return 0;
 995 }
 996
 997 static int
 998 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
 999 {
1000         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1001         int ret;
1002
1003         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1004                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1005         if (ret) {
1006                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1007                 return ret;
1008         }
1009
1010         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1011
1012         return 0;
1013 }
1014
1015 static int
1016 hns3vf_get_configuration(struct hns3_hw *hw)
1017 {
1018         int ret;
1019
1020         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1021         hw->rss_dis_flag = false;
1022
1023         /* Get queue configuration from PF */
1024         ret = hns3vf_get_queue_info(hw);
1025         if (ret)
1026                 return ret;
1027
1028         /* Get queue depth info from PF */
1029         ret = hns3vf_get_queue_depth(hw);
1030         if (ret)
1031                 return ret;
1032
1033         /* Get user defined VF MAC addr from PF */
1034         ret = hns3vf_get_host_mac_addr(hw);
1035         if (ret)
1036                 return ret;
1037
1038         /* Get tc configuration from PF */
1039         return hns3vf_get_tc_info(hw);
1040 }
1041
1042 static int
1043 hns3vf_set_tc_info(struct hns3_adapter *hns)
1044 {
1045         struct hns3_hw *hw = &hns->hw;
1046         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1047         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1048         uint8_t i;
1049
1050         hw->num_tc = 0;
1051         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1052                 if (hw->hw_tc_map & BIT(i))
1053                         hw->num_tc++;
1054
1055         if (nb_rx_q < hw->num_tc) {
1056                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1057                          nb_rx_q, hw->num_tc);
1058                 return -EINVAL;
1059         }
1060
1061         if (nb_tx_q < hw->num_tc) {
1062                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1063                          nb_tx_q, hw->num_tc);
1064                 return -EINVAL;
1065         }
1066
1067         hns3_set_rss_size(hw, nb_rx_q);
1068         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1069
1070         return 0;
1071 }
1072
1073 static void
1074 hns3vf_request_link_info(struct hns3_hw *hw)
1075 {
1076         uint8_t resp_msg;
1077         int ret;
1078
1079         if (rte_atomic16_read(&hw->reset.resetting))
1080                 return;
1081         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1082                                 &resp_msg, sizeof(resp_msg));
1083         if (ret)
1084                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1085 }
1086
1087 static int
1088 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1089 {
1090 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1091         struct hns3_hw *hw = &hns->hw;
1092         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1093         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1094         uint8_t is_kill = on ? 0 : 1;
1095
1096         msg_data[0] = is_kill;
1097         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1098         memcpy(&msg_data[3], &proto, sizeof(proto));
1099
1100         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1101                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1102                                  0);
1103 }
1104
1105 static int
1106 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1107 {
1108         struct hns3_adapter *hns = dev->data->dev_private;
1109         struct hns3_hw *hw = &hns->hw;
1110         int ret;
1111
1112         if (rte_atomic16_read(&hw->reset.resetting)) {
1113                 hns3_err(hw,
1114                          "vf set vlan id failed during resetting, vlan_id =%u",
1115                          vlan_id);
1116                 return -EIO;
1117         }
1118         rte_spinlock_lock(&hw->lock);
1119         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1120         rte_spinlock_unlock(&hw->lock);
1121         if (ret)
1122                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1123                          vlan_id, ret);
1124
1125         return ret;
1126 }
1127
1128 static int
1129 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1130 {
1131         uint8_t msg_data;
1132         int ret;
1133
1134         msg_data = enable ? 1 : 0;
1135         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1136                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1137         if (ret)
1138                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1139
1140         return ret;
1141 }
1142
1143 static int
1144 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1145 {
1146         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1147         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1148         unsigned int tmp_mask;
1149         int ret = 0;
1150
1151         if (rte_atomic16_read(&hw->reset.resetting)) {
1152                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1153                              "mask = 0x%x", mask);
1154                 return -EIO;
1155         }
1156
1157         tmp_mask = (unsigned int)mask;
1158         /* Vlan stripping setting */
1159         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1160                 rte_spinlock_lock(&hw->lock);
1161                 /* Enable or disable VLAN stripping */
1162                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1163                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1164                 else
1165                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1166                 rte_spinlock_unlock(&hw->lock);
1167         }
1168
1169         return ret;
1170 }
1171
1172 static int
1173 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1174 {
1175         struct rte_vlan_filter_conf *vfc;
1176         struct hns3_hw *hw = &hns->hw;
1177         uint16_t vlan_id;
1178         uint64_t vbit;
1179         uint64_t ids;
1180         int ret = 0;
1181         uint32_t i;
1182
1183         vfc = &hw->data->vlan_filter_conf;
1184         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1185                 if (vfc->ids[i] == 0)
1186                         continue;
1187                 ids = vfc->ids[i];
1188                 while (ids) {
1189                         /*
1190                          * 64 means the num bits of ids, one bit corresponds to
1191                          * one vlan id
1192                          */
1193                         vlan_id = 64 * i;
1194                         /* count trailing zeroes */
1195                         vbit = ~ids & (ids - 1);
1196                         /* clear least significant bit set */
1197                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1198                         for (; vbit;) {
1199                                 vbit >>= 1;
1200                                 vlan_id++;
1201                         }
1202                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1203                         if (ret) {
1204                                 hns3_err(hw,
1205                                          "VF handle vlan table failed, ret =%d, on = %d",
1206                                          ret, on);
1207                                 return ret;
1208                         }
1209                 }
1210         }
1211
1212         return ret;
1213 }
1214
1215 static int
1216 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1217 {
1218         return hns3vf_handle_all_vlan_table(hns, 0);
1219 }
1220
1221 static int
1222 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1223 {
1224         struct hns3_hw *hw = &hns->hw;
1225         struct rte_eth_conf *dev_conf;
1226         bool en;
1227         int ret;
1228
1229         dev_conf = &hw->data->dev_conf;
1230         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1231                                                                    : false;
1232         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1233         if (ret)
1234                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1235                          ret);
1236         return ret;
1237 }
1238
1239 static int
1240 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1241 {
1242         struct hns3_adapter *hns = dev->data->dev_private;
1243         struct rte_eth_dev_data *data = dev->data;
1244         struct hns3_hw *hw = &hns->hw;
1245         int ret;
1246
1247         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1248             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1249             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1250                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1251                               "or hw_vlan_insert_pvid is not support!");
1252         }
1253
1254         /* Apply vlan offload setting */
1255         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1256         if (ret)
1257                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1258
1259         return ret;
1260 }
1261
1262 static int
1263 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1264 {
1265         uint8_t msg_data;
1266
1267         msg_data = alive ? 1 : 0;
1268         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1269                                  sizeof(msg_data), false, NULL, 0);
1270 }
1271
1272 static void
1273 hns3vf_keep_alive_handler(void *param)
1274 {
1275         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1276         struct hns3_adapter *hns = eth_dev->data->dev_private;
1277         struct hns3_hw *hw = &hns->hw;
1278         uint8_t respmsg;
1279         int ret;
1280
1281         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1282                                 false, &respmsg, sizeof(uint8_t));
1283         if (ret)
1284                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1285                          ret);
1286
1287         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1288                           eth_dev);
1289 }
1290
1291 static void
1292 hns3vf_service_handler(void *param)
1293 {
1294         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1295         struct hns3_adapter *hns = eth_dev->data->dev_private;
1296         struct hns3_hw *hw = &hns->hw;
1297
1298         /*
1299          * The query link status and reset processing are executed in the
1300          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1301          * and the query operation will time out after 30ms. In the case of
1302          * multiple PF/VFs, each query failure timeout causes the IMP reset
1303          * interrupt to fail to respond within 100ms.
1304          * Before querying the link status, check whether there is a reset
1305          * pending, and if so, abandon the query.
1306          */
1307         if (!hns3vf_is_reset_pending(hns))
1308                 hns3vf_request_link_info(hw);
1309         else
1310                 hns3_warn(hw, "Cancel the query when reset is pending");
1311
1312         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1313                           eth_dev);
1314 }
1315
1316 static int
1317 hns3_query_vf_resource(struct hns3_hw *hw)
1318 {
1319         struct hns3_vf_res_cmd *req;
1320         struct hns3_cmd_desc desc;
1321         uint16_t num_msi;
1322         int ret;
1323
1324         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1325         ret = hns3_cmd_send(hw, &desc, 1);
1326         if (ret) {
1327                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1328                 return ret;
1329         }
1330
1331         req = (struct hns3_vf_res_cmd *)desc.data;
1332         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1333                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1334         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1335                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1336                          num_msi, HNS3_MIN_VECTOR_NUM);
1337                 return -EINVAL;
1338         }
1339
1340         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
1341
1342         return 0;
1343 }
1344
1345 static int
1346 hns3vf_init_hardware(struct hns3_adapter *hns)
1347 {
1348         struct hns3_hw *hw = &hns->hw;
1349         uint16_t mtu = hw->data->mtu;
1350         int ret;
1351
1352         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1353         if (ret)
1354                 return ret;
1355
1356         ret = hns3vf_config_mtu(hw, mtu);
1357         if (ret)
1358                 goto err_init_hardware;
1359
1360         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1361         if (ret) {
1362                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1363                 goto err_init_hardware;
1364         }
1365
1366         ret = hns3_config_gro(hw, false);
1367         if (ret) {
1368                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1369                 goto err_init_hardware;
1370         }
1371
1372         ret = hns3vf_set_alive(hw, true);
1373         if (ret) {
1374                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1375                 goto err_init_hardware;
1376         }
1377
1378         hns3vf_request_link_info(hw);
1379         return 0;
1380
1381 err_init_hardware:
1382         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1383         return ret;
1384 }
1385
1386 static int
1387 hns3vf_clear_vport_list(struct hns3_hw *hw)
1388 {
1389         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1390                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1391                                  NULL, 0);
1392 }
1393
1394 static int
1395 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1396 {
1397         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1398         struct hns3_adapter *hns = eth_dev->data->dev_private;
1399         struct hns3_hw *hw = &hns->hw;
1400         int ret;
1401
1402         PMD_INIT_FUNC_TRACE();
1403
1404         /* Get hardware io base address from pcie BAR2 IO space */
1405         hw->io_base = pci_dev->mem_resource[2].addr;
1406
1407         /* Firmware command queue initialize */
1408         ret = hns3_cmd_init_queue(hw);
1409         if (ret) {
1410                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1411                 goto err_cmd_init_queue;
1412         }
1413
1414         /* Firmware command initialize */
1415         ret = hns3_cmd_init(hw);
1416         if (ret) {
1417                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1418                 goto err_cmd_init;
1419         }
1420
1421         /* Get VF resource */
1422         ret = hns3_query_vf_resource(hw);
1423         if (ret)
1424                 goto err_cmd_init;
1425
1426         rte_spinlock_init(&hw->mbx_resp.lock);
1427
1428         hns3vf_clear_event_cause(hw, 0);
1429
1430         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1431                                          hns3vf_interrupt_handler, eth_dev);
1432         if (ret) {
1433                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1434                 goto err_intr_callback_register;
1435         }
1436
1437         /* Enable interrupt */
1438         rte_intr_enable(&pci_dev->intr_handle);
1439         hns3vf_enable_irq0(hw);
1440
1441         /* Get configuration from PF */
1442         ret = hns3vf_get_configuration(hw);
1443         if (ret) {
1444                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1445                 goto err_get_config;
1446         }
1447
1448         /*
1449          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1450          * on the host by "ip link set ..." command. To avoid some incorrect
1451          * scenes, for example, hns3 VF PMD driver fails to receive and send
1452          * packets after user configure the MAC address by using the
1453          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1454          * address strategy as the hns3 kernel ethdev driver in the
1455          * initialization. If user configure a MAC address by the ip command
1456          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1457          * start with a random MAC address in the initialization.
1458          */
1459         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1460         if (ret)
1461                 rte_eth_random_addr(hw->mac.mac_addr);
1462
1463         ret = hns3vf_clear_vport_list(hw);
1464         if (ret) {
1465                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1466                 goto err_get_config;
1467         }
1468
1469         ret = hns3vf_init_hardware(hns);
1470         if (ret)
1471                 goto err_get_config;
1472
1473         hns3_set_default_rss_args(hw);
1474
1475         /*
1476          * In the initialization clearing the all hardware mapping relationship
1477          * configurations between queues and interrupt vectors is needed, so
1478          * some error caused by the residual configurations, such as the
1479          * unexpected interrupt, can be avoid.
1480          */
1481         ret = hns3vf_init_ring_with_vector(hw);
1482         if (ret)
1483                 goto err_get_config;
1484
1485         return 0;
1486
1487 err_get_config:
1488         hns3vf_disable_irq0(hw);
1489         rte_intr_disable(&pci_dev->intr_handle);
1490         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1491                              eth_dev);
1492 err_intr_callback_register:
1493 err_cmd_init:
1494         hns3_cmd_uninit(hw);
1495         hns3_cmd_destroy_queue(hw);
1496 err_cmd_init_queue:
1497         hw->io_base = NULL;
1498
1499         return ret;
1500 }
1501
1502 static void
1503 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1504 {
1505         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1506         struct hns3_adapter *hns = eth_dev->data->dev_private;
1507         struct hns3_hw *hw = &hns->hw;
1508
1509         PMD_INIT_FUNC_TRACE();
1510
1511         hns3_rss_uninit(hns);
1512         (void)hns3vf_set_alive(hw, false);
1513         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1514         hns3vf_disable_irq0(hw);
1515         rte_intr_disable(&pci_dev->intr_handle);
1516         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1517                              eth_dev);
1518         hns3_cmd_uninit(hw);
1519         hns3_cmd_destroy_queue(hw);
1520         hw->io_base = NULL;
1521 }
1522
1523 static int
1524 hns3vf_do_stop(struct hns3_adapter *hns)
1525 {
1526         struct hns3_hw *hw = &hns->hw;
1527         bool reset_queue;
1528
1529         hw->mac.link_status = ETH_LINK_DOWN;
1530
1531         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1532                 hns3vf_configure_mac_addr(hns, true);
1533                 reset_queue = true;
1534         } else
1535                 reset_queue = false;
1536         return hns3_stop_queues(hns, reset_queue);
1537 }
1538
1539 static void
1540 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1541 {
1542         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1544         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1545         uint8_t base = 0;
1546         uint8_t vec = 0;
1547         uint16_t q_id;
1548
1549         if (dev->data->dev_conf.intr_conf.rxq == 0)
1550                 return;
1551
1552         /* unmap the ring with vector */
1553         if (rte_intr_allow_others(intr_handle)) {
1554                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1555                 base = RTE_INTR_VEC_RXTX_OFFSET;
1556         }
1557         if (rte_intr_dp_is_en(intr_handle)) {
1558                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1559                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1560                                                            HNS3_RING_TYPE_RX,
1561                                                            q_id);
1562                         if (vec < base + intr_handle->nb_efd - 1)
1563                                 vec++;
1564                 }
1565         }
1566         /* Clean datapath event and queue/vec mapping */
1567         rte_intr_efd_disable(intr_handle);
1568         if (intr_handle->intr_vec) {
1569                 rte_free(intr_handle->intr_vec);
1570                 intr_handle->intr_vec = NULL;
1571         }
1572 }
1573
1574 static void
1575 hns3vf_dev_stop(struct rte_eth_dev *dev)
1576 {
1577         struct hns3_adapter *hns = dev->data->dev_private;
1578         struct hns3_hw *hw = &hns->hw;
1579
1580         PMD_INIT_FUNC_TRACE();
1581
1582         hw->adapter_state = HNS3_NIC_STOPPING;
1583         hns3_set_rxtx_function(dev);
1584         rte_wmb();
1585         /* Disable datapath on secondary process. */
1586         hns3_mp_req_stop_rxtx(dev);
1587         /* Prevent crashes when queues are still in use. */
1588         rte_delay_ms(hw->tqps_num);
1589
1590         rte_spinlock_lock(&hw->lock);
1591         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1592                 hns3vf_do_stop(hns);
1593                 hns3_dev_release_mbufs(hns);
1594                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1595         }
1596         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1597         rte_spinlock_unlock(&hw->lock);
1598
1599         hns3vf_unmap_rx_interrupt(dev);
1600 }
1601
1602 static void
1603 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1604 {
1605         struct hns3_adapter *hns = eth_dev->data->dev_private;
1606         struct hns3_hw *hw = &hns->hw;
1607
1608         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1609                 return;
1610
1611         if (hw->adapter_state == HNS3_NIC_STARTED)
1612                 hns3vf_dev_stop(eth_dev);
1613
1614         hw->adapter_state = HNS3_NIC_CLOSING;
1615         hns3_reset_abort(hns);
1616         hw->adapter_state = HNS3_NIC_CLOSED;
1617         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1618         hns3vf_configure_all_mc_mac_addr(hns, true);
1619         hns3vf_remove_all_vlan_table(hns);
1620         hns3vf_uninit_vf(eth_dev);
1621         hns3_free_all_queues(eth_dev);
1622         rte_free(hw->reset.wait_data);
1623         rte_free(eth_dev->process_private);
1624         eth_dev->process_private = NULL;
1625         hns3_mp_uninit_primary();
1626         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1627 }
1628
1629 static int
1630 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1631                        __rte_unused int wait_to_complete)
1632 {
1633         struct hns3_adapter *hns = eth_dev->data->dev_private;
1634         struct hns3_hw *hw = &hns->hw;
1635         struct hns3_mac *mac = &hw->mac;
1636         struct rte_eth_link new_link;
1637
1638         memset(&new_link, 0, sizeof(new_link));
1639         switch (mac->link_speed) {
1640         case ETH_SPEED_NUM_10M:
1641         case ETH_SPEED_NUM_100M:
1642         case ETH_SPEED_NUM_1G:
1643         case ETH_SPEED_NUM_10G:
1644         case ETH_SPEED_NUM_25G:
1645         case ETH_SPEED_NUM_40G:
1646         case ETH_SPEED_NUM_50G:
1647         case ETH_SPEED_NUM_100G:
1648                 new_link.link_speed = mac->link_speed;
1649                 break;
1650         default:
1651                 new_link.link_speed = ETH_SPEED_NUM_100M;
1652                 break;
1653         }
1654
1655         new_link.link_duplex = mac->link_duplex;
1656         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1657         new_link.link_autoneg =
1658             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1659
1660         return rte_eth_linkstatus_set(eth_dev, &new_link);
1661 }
1662
1663 static int
1664 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1665 {
1666         struct hns3_hw *hw = &hns->hw;
1667         int ret;
1668
1669         ret = hns3vf_set_tc_info(hns);
1670         if (ret)
1671                 return ret;
1672
1673         ret = hns3_start_queues(hns, reset_queue);
1674         if (ret)
1675                 hns3_err(hw, "Failed to start queues: %d", ret);
1676
1677         return ret;
1678 }
1679
1680 static int
1681 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1682 {
1683         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1684         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1685         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686         uint32_t intr_vector;
1687         uint8_t base = 0;
1688         uint8_t vec = 0;
1689         uint16_t q_id;
1690         int ret;
1691
1692         if (dev->data->dev_conf.intr_conf.rxq == 0)
1693                 return 0;
1694
1695         /* disable uio/vfio intr/eventfd mapping */
1696         rte_intr_disable(intr_handle);
1697
1698         /* check and configure queue intr-vector mapping */
1699         if (rte_intr_cap_multiple(intr_handle) ||
1700             !RTE_ETH_DEV_SRIOV(dev).active) {
1701                 intr_vector = hw->used_rx_queues;
1702                 /* It creates event fd for each intr vector when MSIX is used */
1703                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1704                         return -EINVAL;
1705         }
1706         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1707                 intr_handle->intr_vec =
1708                         rte_zmalloc("intr_vec",
1709                                     hw->used_rx_queues * sizeof(int), 0);
1710                 if (intr_handle->intr_vec == NULL) {
1711                         hns3_err(hw, "Failed to allocate %d rx_queues"
1712                                      " intr_vec", hw->used_rx_queues);
1713                         ret = -ENOMEM;
1714                         goto vf_alloc_intr_vec_error;
1715                 }
1716         }
1717
1718         if (rte_intr_allow_others(intr_handle)) {
1719                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1720                 base = RTE_INTR_VEC_RXTX_OFFSET;
1721         }
1722         if (rte_intr_dp_is_en(intr_handle)) {
1723                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1724                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1725                                                            HNS3_RING_TYPE_RX,
1726                                                            q_id);
1727                         if (ret)
1728                                 goto vf_bind_vector_error;
1729                         intr_handle->intr_vec[q_id] = vec;
1730                         if (vec < base + intr_handle->nb_efd - 1)
1731                                 vec++;
1732                 }
1733         }
1734         rte_intr_enable(intr_handle);
1735         return 0;
1736
1737 vf_bind_vector_error:
1738         rte_intr_efd_disable(intr_handle);
1739         if (intr_handle->intr_vec) {
1740                 free(intr_handle->intr_vec);
1741                 intr_handle->intr_vec = NULL;
1742         }
1743         return ret;
1744 vf_alloc_intr_vec_error:
1745         rte_intr_efd_disable(intr_handle);
1746         return ret;
1747 }
1748
1749 static void
1750 hns3vf_restore_filter(struct rte_eth_dev *dev)
1751 {
1752         hns3_restore_rss_filter(dev);
1753 }
1754
1755 static int
1756 hns3vf_dev_start(struct rte_eth_dev *dev)
1757 {
1758         struct hns3_adapter *hns = dev->data->dev_private;
1759         struct hns3_hw *hw = &hns->hw;
1760         int ret;
1761
1762         PMD_INIT_FUNC_TRACE();
1763         if (rte_atomic16_read(&hw->reset.resetting))
1764                 return -EBUSY;
1765
1766         rte_spinlock_lock(&hw->lock);
1767         hw->adapter_state = HNS3_NIC_STARTING;
1768         ret = hns3vf_do_start(hns, true);
1769         if (ret) {
1770                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1771                 rte_spinlock_unlock(&hw->lock);
1772                 return ret;
1773         }
1774         hw->adapter_state = HNS3_NIC_STARTED;
1775         rte_spinlock_unlock(&hw->lock);
1776
1777         ret = hns3vf_map_rx_interrupt(dev);
1778         if (ret)
1779                 return ret;
1780         hns3_set_rxtx_function(dev);
1781         hns3_mp_req_start_rxtx(dev);
1782         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
1783
1784         hns3vf_restore_filter(dev);
1785
1786         return ret;
1787 }
1788
1789 static bool
1790 is_vf_reset_done(struct hns3_hw *hw)
1791 {
1792 #define HNS3_FUN_RST_ING_BITS \
1793         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1794          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1795          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1796          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1797
1798         uint32_t val;
1799
1800         if (hw->reset.level == HNS3_VF_RESET) {
1801                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1802                 if (val & HNS3_VF_RST_ING_BIT)
1803                         return false;
1804         } else {
1805                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1806                 if (val & HNS3_FUN_RST_ING_BITS)
1807                         return false;
1808         }
1809         return true;
1810 }
1811
1812 bool
1813 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1814 {
1815         struct hns3_hw *hw = &hns->hw;
1816         enum hns3_reset_level reset;
1817
1818         hns3vf_check_event_cause(hns, NULL);
1819         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1820         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
1821                 hns3_warn(hw, "High level reset %d is pending", reset);
1822                 return true;
1823         }
1824         return false;
1825 }
1826
1827 static int
1828 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
1829 {
1830         struct hns3_hw *hw = &hns->hw;
1831         struct hns3_wait_data *wait_data = hw->reset.wait_data;
1832         struct timeval tv;
1833
1834         if (wait_data->result == HNS3_WAIT_SUCCESS) {
1835                 /*
1836                  * After vf reset is ready, the PF may not have completed
1837                  * the reset processing. The vf sending mbox to PF may fail
1838                  * during the pf reset, so it is better to add extra delay.
1839                  */
1840                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
1841                     hw->reset.level == HNS3_FLR_RESET)
1842                         return 0;
1843                 /* Reset retry process, no need to add extra delay. */
1844                 if (hw->reset.attempts)
1845                         return 0;
1846                 if (wait_data->check_completion == NULL)
1847                         return 0;
1848
1849                 wait_data->check_completion = NULL;
1850                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
1851                 wait_data->count = 1;
1852                 wait_data->result = HNS3_WAIT_REQUEST;
1853                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
1854                                   wait_data);
1855                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
1856                 return -EAGAIN;
1857         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
1858                 gettimeofday(&tv, NULL);
1859                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
1860                           tv.tv_sec, tv.tv_usec);
1861                 return -ETIME;
1862         } else if (wait_data->result == HNS3_WAIT_REQUEST)
1863                 return -EAGAIN;
1864
1865         wait_data->hns = hns;
1866         wait_data->check_completion = is_vf_reset_done;
1867         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
1868                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
1869         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
1870         wait_data->count = HNS3VF_RESET_WAIT_CNT;
1871         wait_data->result = HNS3_WAIT_REQUEST;
1872         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
1873         return -EAGAIN;
1874 }
1875
1876 static int
1877 hns3vf_prepare_reset(struct hns3_adapter *hns)
1878 {
1879         struct hns3_hw *hw = &hns->hw;
1880         int ret = 0;
1881
1882         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
1883                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
1884                                         0, true, NULL, 0);
1885         }
1886         rte_atomic16_set(&hw->reset.disable_cmd, 1);
1887
1888         return ret;
1889 }
1890
1891 static int
1892 hns3vf_stop_service(struct hns3_adapter *hns)
1893 {
1894         struct hns3_hw *hw = &hns->hw;
1895         struct rte_eth_dev *eth_dev;
1896
1897         eth_dev = &rte_eth_devices[hw->data->port_id];
1898         if (hw->adapter_state == HNS3_NIC_STARTED)
1899                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
1900         hw->mac.link_status = ETH_LINK_DOWN;
1901
1902         hns3_set_rxtx_function(eth_dev);
1903         rte_wmb();
1904         /* Disable datapath on secondary process. */
1905         hns3_mp_req_stop_rxtx(eth_dev);
1906         rte_delay_ms(hw->tqps_num);
1907
1908         rte_spinlock_lock(&hw->lock);
1909         if (hw->adapter_state == HNS3_NIC_STARTED ||
1910             hw->adapter_state == HNS3_NIC_STOPPING) {
1911                 hns3vf_do_stop(hns);
1912                 hw->reset.mbuf_deferred_free = true;
1913         } else
1914                 hw->reset.mbuf_deferred_free = false;
1915
1916         /*
1917          * It is cumbersome for hardware to pick-and-choose entries for deletion
1918          * from table space. Hence, for function reset software intervention is
1919          * required to delete the entries.
1920          */
1921         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
1922                 hns3vf_configure_all_mc_mac_addr(hns, true);
1923         rte_spinlock_unlock(&hw->lock);
1924
1925         return 0;
1926 }
1927
1928 static int
1929 hns3vf_start_service(struct hns3_adapter *hns)
1930 {
1931         struct hns3_hw *hw = &hns->hw;
1932         struct rte_eth_dev *eth_dev;
1933
1934         eth_dev = &rte_eth_devices[hw->data->port_id];
1935         hns3_set_rxtx_function(eth_dev);
1936         hns3_mp_req_start_rxtx(eth_dev);
1937         if (hw->adapter_state == HNS3_NIC_STARTED)
1938                 hns3vf_service_handler(eth_dev);
1939
1940         return 0;
1941 }
1942
1943 static int
1944 hns3vf_check_default_mac_change(struct hns3_hw *hw)
1945 {
1946         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1947         struct rte_ether_addr *hw_mac;
1948         int ret;
1949
1950         /*
1951          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1952          * on the host by "ip link set ..." command. If the hns3 PF kernel
1953          * ethdev driver sets the MAC address for VF device after the
1954          * initialization of the related VF device, the PF driver will notify
1955          * VF driver to reset VF device to make the new MAC address effective
1956          * immediately. The hns3 VF PMD driver should check whether the MAC
1957          * address has been changed by the PF kernel ethdev driver, if changed
1958          * VF driver should configure hardware using the new MAC address in the
1959          * recovering hardware configuration stage of the reset process.
1960          */
1961         ret = hns3vf_get_host_mac_addr(hw);
1962         if (ret)
1963                 return ret;
1964
1965         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
1966         ret = rte_is_zero_ether_addr(hw_mac);
1967         if (ret) {
1968                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
1969         } else {
1970                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
1971                 if (!ret) {
1972                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
1973                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1974                                               &hw->data->mac_addrs[0]);
1975                         hns3_warn(hw, "Default MAC address has been changed to:"
1976                                   " %s by the host PF kernel ethdev driver",
1977                                   mac_str);
1978                 }
1979         }
1980
1981         return 0;
1982 }
1983
1984 static int
1985 hns3vf_restore_conf(struct hns3_adapter *hns)
1986 {
1987         struct hns3_hw *hw = &hns->hw;
1988         int ret;
1989
1990         ret = hns3vf_check_default_mac_change(hw);
1991         if (ret)
1992                 return ret;
1993
1994         ret = hns3vf_configure_mac_addr(hns, false);
1995         if (ret)
1996                 return ret;
1997
1998         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
1999         if (ret)
2000                 goto err_mc_mac;
2001
2002         ret = hns3vf_restore_promisc(hns);
2003         if (ret)
2004                 goto err_vlan_table;
2005
2006         ret = hns3vf_restore_vlan_conf(hns);
2007         if (ret)
2008                 goto err_vlan_table;
2009
2010         if (hw->adapter_state == HNS3_NIC_STARTED) {
2011                 ret = hns3vf_do_start(hns, false);
2012                 if (ret)
2013                         goto err_vlan_table;
2014                 hns3_info(hw, "hns3vf dev restart successful!");
2015         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2016                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2017         return 0;
2018
2019 err_vlan_table:
2020         hns3vf_configure_all_mc_mac_addr(hns, true);
2021 err_mc_mac:
2022         hns3vf_configure_mac_addr(hns, true);
2023         return ret;
2024 }
2025
2026 static enum hns3_reset_level
2027 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2028 {
2029         enum hns3_reset_level reset_level;
2030
2031         /* return the highest priority reset level amongst all */
2032         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2033                 reset_level = HNS3_VF_RESET;
2034         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2035                 reset_level = HNS3_VF_FULL_RESET;
2036         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2037                 reset_level = HNS3_VF_PF_FUNC_RESET;
2038         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2039                 reset_level = HNS3_VF_FUNC_RESET;
2040         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2041                 reset_level = HNS3_FLR_RESET;
2042         else
2043                 reset_level = HNS3_NONE_RESET;
2044
2045         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2046                 return HNS3_NONE_RESET;
2047
2048         return reset_level;
2049 }
2050
2051 static void
2052 hns3vf_reset_service(void *param)
2053 {
2054         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2055         struct hns3_hw *hw = &hns->hw;
2056         enum hns3_reset_level reset_level;
2057         struct timeval tv_delta;
2058         struct timeval tv_start;
2059         struct timeval tv;
2060         uint64_t msec;
2061
2062         /*
2063          * The interrupt is not triggered within the delay time.
2064          * The interrupt may have been lost. It is necessary to handle
2065          * the interrupt to recover from the error.
2066          */
2067         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2068                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2069                 hns3_err(hw, "Handling interrupts in delayed tasks");
2070                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2071                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2072                 if (reset_level == HNS3_NONE_RESET) {
2073                         hns3_err(hw, "No reset level is set, try global reset");
2074                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2075                 }
2076         }
2077         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2078
2079         /*
2080          * Hardware reset has been notified, we now have to poll & check if
2081          * hardware has actually completed the reset sequence.
2082          */
2083         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2084         if (reset_level != HNS3_NONE_RESET) {
2085                 gettimeofday(&tv_start, NULL);
2086                 hns3_reset_process(hns, reset_level);
2087                 gettimeofday(&tv, NULL);
2088                 timersub(&tv, &tv_start, &tv_delta);
2089                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2090                        tv_delta.tv_usec / USEC_PER_MSEC;
2091                 if (msec > HNS3_RESET_PROCESS_MS)
2092                         hns3_err(hw, "%d handle long time delta %" PRIx64
2093                                  " ms time=%ld.%.6ld",
2094                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2095         }
2096 }
2097
2098 static int
2099 hns3vf_reinit_dev(struct hns3_adapter *hns)
2100 {
2101         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2102         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2103         struct hns3_hw *hw = &hns->hw;
2104         int ret;
2105
2106         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2107                 rte_intr_disable(&pci_dev->intr_handle);
2108                 hns3vf_set_bus_master(pci_dev, true);
2109         }
2110
2111         /* Firmware command initialize */
2112         ret = hns3_cmd_init(hw);
2113         if (ret) {
2114                 hns3_err(hw, "Failed to init cmd: %d", ret);
2115                 return ret;
2116         }
2117
2118         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2119                 /*
2120                  * UIO enables msix by writing the pcie configuration space
2121                  * vfio_pci enables msix in rte_intr_enable.
2122                  */
2123                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2124                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2125                         if (hns3vf_enable_msix(pci_dev, true))
2126                                 hns3_err(hw, "Failed to enable msix");
2127                 }
2128
2129                 rte_intr_enable(&pci_dev->intr_handle);
2130         }
2131
2132         ret = hns3_reset_all_queues(hns);
2133         if (ret) {
2134                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2135                 return ret;
2136         }
2137
2138         ret = hns3vf_init_hardware(hns);
2139         if (ret) {
2140                 hns3_err(hw, "Failed to init hardware: %d", ret);
2141                 return ret;
2142         }
2143
2144         return 0;
2145 }
2146
2147 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2148         .dev_start          = hns3vf_dev_start,
2149         .dev_stop           = hns3vf_dev_stop,
2150         .dev_close          = hns3vf_dev_close,
2151         .mtu_set            = hns3vf_dev_mtu_set,
2152         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2153         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2154         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2155         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2156         .stats_get          = hns3_stats_get,
2157         .stats_reset        = hns3_stats_reset,
2158         .xstats_get         = hns3_dev_xstats_get,
2159         .xstats_get_names   = hns3_dev_xstats_get_names,
2160         .xstats_reset       = hns3_dev_xstats_reset,
2161         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2162         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2163         .dev_infos_get      = hns3vf_dev_infos_get,
2164         .rx_queue_setup     = hns3_rx_queue_setup,
2165         .tx_queue_setup     = hns3_tx_queue_setup,
2166         .rx_queue_release   = hns3_dev_rx_queue_release,
2167         .tx_queue_release   = hns3_dev_tx_queue_release,
2168         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2169         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2170         .dev_configure      = hns3vf_dev_configure,
2171         .mac_addr_add       = hns3vf_add_mac_addr,
2172         .mac_addr_remove    = hns3vf_remove_mac_addr,
2173         .mac_addr_set       = hns3vf_set_default_mac_addr,
2174         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2175         .link_update        = hns3vf_dev_link_update,
2176         .rss_hash_update    = hns3_dev_rss_hash_update,
2177         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2178         .reta_update        = hns3_dev_rss_reta_update,
2179         .reta_query         = hns3_dev_rss_reta_query,
2180         .filter_ctrl        = hns3_dev_filter_ctrl,
2181         .vlan_filter_set    = hns3vf_vlan_filter_set,
2182         .vlan_offload_set   = hns3vf_vlan_offload_set,
2183         .get_reg            = hns3_get_regs,
2184         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2185 };
2186
2187 static const struct hns3_reset_ops hns3vf_reset_ops = {
2188         .reset_service       = hns3vf_reset_service,
2189         .stop_service        = hns3vf_stop_service,
2190         .prepare_reset       = hns3vf_prepare_reset,
2191         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2192         .reinit_dev          = hns3vf_reinit_dev,
2193         .restore_conf        = hns3vf_restore_conf,
2194         .start_service       = hns3vf_start_service,
2195 };
2196
2197 static int
2198 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2199 {
2200         struct hns3_adapter *hns = eth_dev->data->dev_private;
2201         struct hns3_hw *hw = &hns->hw;
2202         int ret;
2203
2204         PMD_INIT_FUNC_TRACE();
2205
2206         eth_dev->process_private = (struct hns3_process_private *)
2207             rte_zmalloc_socket("hns3_filter_list",
2208                                sizeof(struct hns3_process_private),
2209                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2210         if (eth_dev->process_private == NULL) {
2211                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2212                 return -ENOMEM;
2213         }
2214
2215         /* initialize flow filter lists */
2216         hns3_filterlist_init(eth_dev);
2217
2218         hns3_set_rxtx_function(eth_dev);
2219         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2220         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2221                 hns3_mp_init_secondary();
2222                 hw->secondary_cnt++;
2223                 return 0;
2224         }
2225
2226         hns3_mp_init_primary();
2227
2228         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2229         hns->is_vf = true;
2230         hw->data = eth_dev->data;
2231
2232         ret = hns3_reset_init(hw);
2233         if (ret)
2234                 goto err_init_reset;
2235         hw->reset.ops = &hns3vf_reset_ops;
2236
2237         ret = hns3vf_init_vf(eth_dev);
2238         if (ret) {
2239                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2240                 goto err_init_vf;
2241         }
2242
2243         /* Allocate memory for storing MAC addresses */
2244         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2245                                                sizeof(struct rte_ether_addr) *
2246                                                HNS3_VF_UC_MACADDR_NUM, 0);
2247         if (eth_dev->data->mac_addrs == NULL) {
2248                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2249                              "to store MAC addresses",
2250                              sizeof(struct rte_ether_addr) *
2251                              HNS3_VF_UC_MACADDR_NUM);
2252                 ret = -ENOMEM;
2253                 goto err_rte_zmalloc;
2254         }
2255
2256         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2257                             &eth_dev->data->mac_addrs[0]);
2258         hw->adapter_state = HNS3_NIC_INITIALIZED;
2259         /*
2260          * Pass the information to the rte_eth_dev_close() that it should also
2261          * release the private port resources.
2262          */
2263         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2264
2265         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2266                 hns3_err(hw, "Reschedule reset service after dev_init");
2267                 hns3_schedule_reset(hns);
2268         } else {
2269                 /* IMP will wait ready flag before reset */
2270                 hns3_notify_reset_ready(hw, false);
2271         }
2272         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2273                           eth_dev);
2274         return 0;
2275
2276 err_rte_zmalloc:
2277         hns3vf_uninit_vf(eth_dev);
2278
2279 err_init_vf:
2280         rte_free(hw->reset.wait_data);
2281
2282 err_init_reset:
2283         eth_dev->dev_ops = NULL;
2284         eth_dev->rx_pkt_burst = NULL;
2285         eth_dev->tx_pkt_burst = NULL;
2286         eth_dev->tx_pkt_prepare = NULL;
2287         rte_free(eth_dev->process_private);
2288         eth_dev->process_private = NULL;
2289
2290         return ret;
2291 }
2292
2293 static int
2294 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2295 {
2296         struct hns3_adapter *hns = eth_dev->data->dev_private;
2297         struct hns3_hw *hw = &hns->hw;
2298
2299         PMD_INIT_FUNC_TRACE();
2300
2301         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2302                 return -EPERM;
2303
2304         eth_dev->dev_ops = NULL;
2305         eth_dev->rx_pkt_burst = NULL;
2306         eth_dev->tx_pkt_burst = NULL;
2307         eth_dev->tx_pkt_prepare = NULL;
2308
2309         if (hw->adapter_state < HNS3_NIC_CLOSING)
2310                 hns3vf_dev_close(eth_dev);
2311
2312         hw->adapter_state = HNS3_NIC_REMOVED;
2313         return 0;
2314 }
2315
2316 static int
2317 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2318                      struct rte_pci_device *pci_dev)
2319 {
2320         return rte_eth_dev_pci_generic_probe(pci_dev,
2321                                              sizeof(struct hns3_adapter),
2322                                              hns3vf_dev_init);
2323 }
2324
2325 static int
2326 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2327 {
2328         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2329 }
2330
2331 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2332         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2333         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2334         { .vendor_id = 0, /* sentinel */ },
2335 };
2336
2337 static struct rte_pci_driver rte_hns3vf_pmd = {
2338         .id_table = pci_id_hns3vf_map,
2339         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2340         .probe = eth_hns3vf_pci_probe,
2341         .remove = eth_hns3vf_pci_remove,
2342 };
2343
2344 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2345 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2346 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");