drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <rte_ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 /* set PCI bus mastering */
  48 static int
  49 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  50 {
  51         uint16_t reg;
  52         int ret;
  53
  54         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  55         if (ret < 0) {
  56                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  57                              PCI_COMMAND);
  58                 return ret;
  59         }
  60
  61         if (op)
  62                 /* set the master bit */
  63                 reg |= PCI_COMMAND_MASTER;
  64         else
  65                 reg &= ~(PCI_COMMAND_MASTER);
  66
  67         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  68 }
  69
  70 /**
  71  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  72  * @cap: the capability
  73  *
  74  * Return the address of the given capability within the PCI capability list.
  75  */
  76 static int
  77 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  78 {
  79 #define MAX_PCIE_CAPABILITY 48
  80         uint16_t status;
  81         uint8_t pos;
  82         uint8_t id;
  83         int ttl;
  84         int ret;
  85
  86         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  87         if (ret < 0) {
  88                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  89                 return 0;
  90         }
  91
  92         if (!(status & PCI_STATUS_CAP_LIST))
  93                 return 0;
  94
  95         ttl = MAX_PCIE_CAPABILITY;
  96         ret = rte_pci_read_config(device, &pos, sizeof(pos),
  97                                   PCI_CAPABILITY_LIST);
  98         if (ret < 0) {
  99                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 100                              PCI_CAPABILITY_LIST);
 101                 return 0;
 102         }
 103
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 ret = rte_pci_read_config(device, &id, sizeof(id),
 106                                           (pos + PCI_CAP_LIST_ID));
 107                 if (ret < 0) {
 108                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 109                                      (pos + PCI_CAP_LIST_ID));
 110                         break;
 111                 }
 112
 113                 if (id == 0xFF)
 114                         break;
 115
 116                 if (id == cap)
 117                         return (int)pos;
 118
 119                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 120                                           (pos + PCI_CAP_LIST_NEXT));
 121                 if (ret < 0) {
 122                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 123                                      (pos + PCI_CAP_LIST_NEXT));
 124                         break;
 125                 }
 126         }
 127         return 0;
 128 }
 129
 130 static int
 131 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 132 {
 133         uint16_t control;
 134         int pos;
 135         int ret;
 136
 137         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 138         if (pos) {
 139                 ret = rte_pci_read_config(device, &control, sizeof(control),
 140                                     (pos + PCI_MSIX_FLAGS));
 141                 if (ret < 0) {
 142                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 143                                      (pos + PCI_MSIX_FLAGS));
 144                         return -ENXIO;
 145                 }
 146
 147                 if (op)
 148                         control |= PCI_MSIX_FLAGS_ENABLE;
 149                 else
 150                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 151                 ret = rte_pci_write_config(device, &control, sizeof(control),
 152                                           (pos + PCI_MSIX_FLAGS));
 153                 if (ret < 0) {
 154                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 155                                     (pos + PCI_MSIX_FLAGS));
 156                 }
 157                 return 0;
 158         }
 159         return -ENXIO;
 160 }
 161
 162 static int
 163 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 164 {
 165         /* mac address was checked by upper level interface */
 166         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 167         int ret;
 168
 169         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 170                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 171                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 172         if (ret) {
 173                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 174                                       mac_addr);
 175                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 176                          mac_str, ret);
 177         }
 178         return ret;
 179 }
 180
 181 static int
 182 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 183 {
 184         /* mac address was checked by upper level interface */
 185         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 186         int ret;
 187
 188         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 189                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 190                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 191                                 false, NULL, 0);
 192         if (ret) {
 193                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 194                                       mac_addr);
 195                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 196                          mac_str, ret);
 197         }
 198         return ret;
 199 }
 200
 201 static int
 202 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 203 {
 204         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 205         struct rte_ether_addr *addr;
 206         int ret;
 207         int i;
 208
 209         for (i = 0; i < hw->mc_addrs_num; i++) {
 210                 addr = &hw->mc_addrs[i];
 211                 /* Check if there are duplicate addresses */
 212                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 213                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 214                                               addr);
 215                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 216                                  "(%s) is added by the set_mc_mac_addr_list "
 217                                  "API", mac_str);
 218                         return -EINVAL;
 219                 }
 220         }
 221
 222         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 223         if (ret) {
 224                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 225                                       mac_addr);
 226                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 227                          mac_str, ret);
 228         }
 229         return ret;
 230 }
 231
 232 static int
 233 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 234                     __rte_unused uint32_t idx,
 235                     __rte_unused uint32_t pool)
 236 {
 237         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 238         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 239         int ret;
 240
 241         rte_spinlock_lock(&hw->lock);
 242
 243         /*
 244          * In hns3 network engine adding UC and MC mac address with different
 245          * commands with firmware. We need to determine whether the input
 246          * address is a UC or a MC address to call different commands.
 247          * By the way, it is recommended calling the API function named
 248          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 249          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 250          * may affect the specifications of UC mac addresses.
 251          */
 252         if (rte_is_multicast_ether_addr(mac_addr))
 253                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 254         else
 255                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 256
 257         rte_spinlock_unlock(&hw->lock);
 258         if (ret) {
 259                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 260                                       mac_addr);
 261                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 262                          ret);
 263         }
 264
 265         return ret;
 266 }
 267
 268 static void
 269 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 270 {
 271         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 272         /* index will be checked by upper level rte interface */
 273         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 274         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 275         int ret;
 276
 277         rte_spinlock_lock(&hw->lock);
 278
 279         if (rte_is_multicast_ether_addr(mac_addr))
 280                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 281         else
 282                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 283
 284         rte_spinlock_unlock(&hw->lock);
 285         if (ret) {
 286                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 287                                       mac_addr);
 288                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 289                          mac_str, ret);
 290         }
 291 }
 292
 293 static int
 294 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 295                             struct rte_ether_addr *mac_addr)
 296 {
 297 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 298         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 299         struct rte_ether_addr *old_addr;
 300         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 301         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 302         int ret;
 303
 304         /*
 305          * It has been guaranteed that input parameter named mac_addr is valid
 306          * address in the rte layer of DPDK framework.
 307          */
 308         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 309         rte_spinlock_lock(&hw->lock);
 310         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 311         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 312                RTE_ETHER_ADDR_LEN);
 313
 314         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 315                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 316                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 317         if (ret) {
 318                 /*
 319                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 320                  * driver. When user has configured a MAC address for VF device
 321                  * by "ip link set ..." command based on the PF device, the hns3
 322                  * PF kernel ethdev driver does not allow VF driver to request
 323                  * reconfiguring a different default MAC address, and return
 324                  * -EPREM to VF driver through mailbox.
 325                  */
 326                 if (ret == -EPERM) {
 327                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 328                                               old_addr);
 329                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 330                                   mac_str);
 331                 } else {
 332                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 333                                               mac_addr);
 334                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 335                                  mac_str, ret);
 336                 }
 337         }
 338
 339         rte_ether_addr_copy(mac_addr,
 340                             (struct rte_ether_addr *)hw->mac.mac_addr);
 341         rte_spinlock_unlock(&hw->lock);
 342
 343         return ret;
 344 }
 345
 346 static int
 347 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 348 {
 349         struct hns3_hw *hw = &hns->hw;
 350         struct rte_ether_addr *addr;
 351         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 352         int err = 0;
 353         int ret;
 354         int i;
 355
 356         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 357                 addr = &hw->data->mac_addrs[i];
 358                 if (rte_is_zero_ether_addr(addr))
 359                         continue;
 360                 if (rte_is_multicast_ether_addr(addr))
 361                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 362                               hns3vf_add_mc_mac_addr(hw, addr);
 363                 else
 364                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 365                               hns3vf_add_uc_mac_addr(hw, addr);
 366
 367                 if (ret) {
 368                         err = ret;
 369                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 370                                               addr);
 371                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 372                                  "ret = %d.", del ? "remove" : "restore",
 373                                  mac_str, i, ret);
 374                 }
 375         }
 376         return err;
 377 }
 378
 379 static int
 380 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 381                        struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 402                           struct rte_ether_addr *mac_addr)
 403 {
 404         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 405         int ret;
 406
 407         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 408                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 409                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 410                                 NULL, 0);
 411         if (ret) {
 412                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 413                                       mac_addr);
 414                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 415                          mac_str, ret);
 416         }
 417
 418         return ret;
 419 }
 420
 421 static int
 422 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 423                              struct rte_ether_addr *mc_addr_set,
 424                              uint32_t nb_mc_addr)
 425 {
 426         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 427         struct rte_ether_addr *addr;
 428         uint32_t i;
 429         uint32_t j;
 430
 431         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 432                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 433                          "invalid. valid range: 0~%d",
 434                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 435                 return -EINVAL;
 436         }
 437
 438         /* Check if input mac addresses are valid */
 439         for (i = 0; i < nb_mc_addr; i++) {
 440                 addr = &mc_addr_set[i];
 441                 if (!rte_is_multicast_ether_addr(addr)) {
 442                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 443                                               addr);
 444                         hns3_err(hw,
 445                                  "failed to set mc mac addr, addr(%s) invalid.",
 446                                  mac_str);
 447                         return -EINVAL;
 448                 }
 449
 450                 /* Check if there are duplicate addresses */
 451                 for (j = i + 1; j < nb_mc_addr; j++) {
 452                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 453                                 hns3_ether_format_addr(mac_str,
 454                                                       RTE_ETHER_ADDR_FMT_SIZE,
 455                                                       addr);
 456                                 hns3_err(hw, "failed to set mc mac addr, "
 457                                          "addrs invalid. two same addrs(%s).",
 458                                          mac_str);
 459                                 return -EINVAL;
 460                         }
 461                 }
 462
 463                 /*
 464                  * Check if there are duplicate addresses between mac_addrs
 465                  * and mc_addr_set
 466                  */
 467                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 468                         if (rte_is_same_ether_addr(addr,
 469                                                    &hw->data->mac_addrs[j])) {
 470                                 hns3_ether_format_addr(mac_str,
 471                                                       RTE_ETHER_ADDR_FMT_SIZE,
 472                                                       addr);
 473                                 hns3_err(hw, "failed to set mc mac addr, "
 474                                          "addrs invalid. addrs(%s) has already "
 475                                          "configured in mac_addr add API",
 476                                          mac_str);
 477                                 return -EINVAL;
 478                         }
 479                 }
 480         }
 481
 482         return 0;
 483 }
 484
 485 static int
 486 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 487                             struct rte_ether_addr *mc_addr_set,
 488                             uint32_t nb_mc_addr)
 489 {
 490         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 491         struct rte_ether_addr *addr;
 492         int cur_addr_num;
 493         int set_addr_num;
 494         int num;
 495         int ret;
 496         int i;
 497
 498         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 499         if (ret)
 500                 return ret;
 501
 502         rte_spinlock_lock(&hw->lock);
 503         cur_addr_num = hw->mc_addrs_num;
 504         for (i = 0; i < cur_addr_num; i++) {
 505                 num = cur_addr_num - i - 1;
 506                 addr = &hw->mc_addrs[num];
 507                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 508                 if (ret) {
 509                         rte_spinlock_unlock(&hw->lock);
 510                         return ret;
 511                 }
 512
 513                 hw->mc_addrs_num--;
 514         }
 515
 516         set_addr_num = (int)nb_mc_addr;
 517         for (i = 0; i < set_addr_num; i++) {
 518                 addr = &mc_addr_set[i];
 519                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 520                 if (ret) {
 521                         rte_spinlock_unlock(&hw->lock);
 522                         return ret;
 523                 }
 524
 525                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 526                 hw->mc_addrs_num++;
 527         }
 528         rte_spinlock_unlock(&hw->lock);
 529
 530         return 0;
 531 }
 532
 533 static int
 534 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 535 {
 536         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 537         struct hns3_hw *hw = &hns->hw;
 538         struct rte_ether_addr *addr;
 539         int err = 0;
 540         int ret;
 541         int i;
 542
 543         for (i = 0; i < hw->mc_addrs_num; i++) {
 544                 addr = &hw->mc_addrs[i];
 545                 if (!rte_is_multicast_ether_addr(addr))
 546                         continue;
 547                 if (del)
 548                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 549                 else
 550                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 551                 if (ret) {
 552                         err = ret;
 553                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 554                                               addr);
 555                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 556                                  del ? "Remove" : "Restore", mac_str, ret);
 557                 }
 558         }
 559         return err;
 560 }
 561
 562 static int
 563 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 564                         bool en_uc_pmc, bool en_mc_pmc)
 565 {
 566         struct hns3_mbx_vf_to_pf_cmd *req;
 567         struct hns3_cmd_desc desc;
 568         int ret;
 569
 570         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 571
 572         /*
 573          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 574          * so there are some features for promiscuous/allmulticast mode in hns3
 575          * VF PMD driver as below:
 576          * 1. The promiscuous/allmulticast mode can be configured successfully
 577          *    only based on the trusted VF device. If based on the non trusted
 578          *    VF device, configuring promiscuous/allmulticast mode will fail.
 579          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 580          *    kernel ethdev driver on the host by the following command:
 581          *      "ip link set <eth num> vf <vf id> turst on"
 582          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 583          *    driver can receive the ingress and outgoing traffic. In the words,
 584          *    all the ingress packets, all the packets sent from the PF and
 585          *    other VFs on the same physical port.
 586          * 3. Note: Because of the hardware constraints, By default vlan filter
 587          *    is enabled and couldn't be turned off based on VF device, so vlan
 588          *    filter is still effective even in promiscuous mode. If upper
 589          *    applications don't call rte_eth_dev_vlan_filter API function to
 590          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 591          *    the packets with vlan tag in promiscuoue mode.
 592          */
 593         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 594         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 595         req->msg[1] = en_bc_pmc ? 1 : 0;
 596         req->msg[2] = en_uc_pmc ? 1 : 0;
 597         req->msg[3] = en_mc_pmc ? 1 : 0;
 598         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 599
 600         ret = hns3_cmd_send(hw, &desc, 1);
 601         if (ret)
 602                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 609 {
 610         struct hns3_adapter *hns = dev->data->dev_private;
 611         struct hns3_hw *hw = &hns->hw;
 612         int ret;
 613
 614         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 615         if (ret)
 616                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 617                         ret);
 618         return ret;
 619 }
 620
 621 static int
 622 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 623 {
 624         bool allmulti = dev->data->all_multicast ? true : false;
 625         struct hns3_adapter *hns = dev->data->dev_private;
 626         struct hns3_hw *hw = &hns->hw;
 627         int ret;
 628
 629         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 630         if (ret)
 631                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 632                         ret);
 633         return ret;
 634 }
 635
 636 static int
 637 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 638 {
 639         struct hns3_adapter *hns = dev->data->dev_private;
 640         struct hns3_hw *hw = &hns->hw;
 641         int ret;
 642
 643         if (dev->data->promiscuous)
 644                 return 0;
 645
 646         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 647         if (ret)
 648                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 649                         ret);
 650         return ret;
 651 }
 652
 653 static int
 654 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 655 {
 656         struct hns3_adapter *hns = dev->data->dev_private;
 657         struct hns3_hw *hw = &hns->hw;
 658         int ret;
 659
 660         if (dev->data->promiscuous)
 661                 return 0;
 662
 663         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 664         if (ret)
 665                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 666                         ret);
 667         return ret;
 668 }
 669
 670 static int
 671 hns3vf_restore_promisc(struct hns3_adapter *hns)
 672 {
 673         struct hns3_hw *hw = &hns->hw;
 674         bool allmulti = hw->data->all_multicast ? true : false;
 675
 676         if (hw->data->promiscuous)
 677                 return hns3vf_set_promisc_mode(hw, true, true, true);
 678
 679         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 680 }
 681
 682 static int
 683 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 684                              bool mmap, enum hns3_ring_type queue_type,
 685                              uint16_t queue_id)
 686 {
 687         struct hns3_vf_bind_vector_msg bind_msg;
 688         const char *op_str;
 689         uint16_t code;
 690         int ret;
 691
 692         memset(&bind_msg, 0, sizeof(bind_msg));
 693         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 694                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 695         bind_msg.vector_id = vector_id;
 696
 697         if (queue_type == HNS3_RING_TYPE_RX)
 698                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 699         else
 700                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 701
 702         bind_msg.param[0].ring_type = queue_type;
 703         bind_msg.ring_num = 1;
 704         bind_msg.param[0].tqp_index = queue_id;
 705         op_str = mmap ? "Map" : "Unmap";
 706         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 707                                 sizeof(bind_msg), false, NULL, 0);
 708         if (ret)
 709                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 710                          op_str, queue_id, bind_msg.vector_id, ret);
 711
 712         return ret;
 713 }
 714
 715 static int
 716 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 717 {
 718         uint16_t vec;
 719         int ret;
 720         int i;
 721
 722         /*
 723          * In hns3 network engine, vector 0 is always the misc interrupt of this
 724          * function, vector 1~N can be used respectively for the queues of the
 725          * function. Tx and Rx queues with the same number share the interrupt
 726          * vector. In the initialization clearing the all hardware mapping
 727          * relationship configurations between queues and interrupt vectors is
 728          * needed, so some error caused by the residual configurations, such as
 729          * the unexpected Tx interrupt, can be avoid.
 730          */
 731         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 732         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 733                 vec = vec - 1; /* the last interrupt is reserved */
 734         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 735         for (i = 0; i < hw->intr_tqps_num; i++) {
 736                 /*
 737                  * Set gap limiter/rate limiter/quanity limiter algorithm
 738                  * configuration for interrupt coalesce of queue's interrupt.
 739                  */
 740                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 741                                        HNS3_TQP_INTR_GL_DEFAULT);
 742                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 743                                        HNS3_TQP_INTR_GL_DEFAULT);
 744                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 745                 /*
 746                  * QL(quantity limiter) is not used currently, just set 0 to
 747                  * close it.
 748                  */
 749                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 750
 751                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 752                                                    HNS3_RING_TYPE_TX, i);
 753                 if (ret) {
 754                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 755                                           "vector: %u, ret=%d", i, vec, ret);
 756                         return ret;
 757                 }
 758
 759                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 760                                                    HNS3_RING_TYPE_RX, i);
 761                 if (ret) {
 762                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 763                                           "vector: %u, ret=%d", i, vec, ret);
 764                         return ret;
 765                 }
 766         }
 767
 768         return 0;
 769 }
 770
 771 static int
 772 hns3vf_dev_configure(struct rte_eth_dev *dev)
 773 {
 774         struct hns3_adapter *hns = dev->data->dev_private;
 775         struct hns3_hw *hw = &hns->hw;
 776         struct rte_eth_conf *conf = &dev->data->dev_conf;
 777         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 778         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 779         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 780         struct rte_eth_rss_conf rss_conf;
 781         uint16_t mtu;
 782         bool gro_en;
 783         int ret;
 784
 785         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 786
 787         /*
 788          * Some versions of hardware network engine does not support
 789          * individually enable/disable/reset the Tx or Rx queue. These devices
 790          * must enable/disable/reset Tx and Rx queues at the same time. When the
 791          * numbers of Tx queues allocated by upper applications are not equal to
 792          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 793          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 794          * work as usual. But these fake queues are imperceptible, and can not
 795          * be used by upper applications.
 796          */
 797         if (!hns3_dev_indep_txrx_supported(hw)) {
 798                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 799                 if (ret) {
 800                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
 801                                  ret);
 802                         return ret;
 803                 }
 804         }
 805
 806         hw->adapter_state = HNS3_NIC_CONFIGURING;
 807         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 808                 hns3_err(hw, "setting link speed/duplex not supported");
 809                 ret = -EINVAL;
 810                 goto cfg_err;
 811         }
 812
 813         /* When RSS is not configured, redirect the packet queue 0 */
 814         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 815                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 816                 hw->rss_dis_flag = false;
 817                 rss_conf = conf->rx_adv_conf.rss_conf;
 818                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 819                 if (ret)
 820                         goto cfg_err;
 821         }
 822
 823         /*
 824          * If jumbo frames are enabled, MTU needs to be refreshed
 825          * according to the maximum RX packet length.
 826          */
 827         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 828                 /*
 829                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 830                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 831                  * can safely assign to "uint16_t" type variable.
 832                  */
 833                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 834                 ret = hns3vf_dev_mtu_set(dev, mtu);
 835                 if (ret)
 836                         goto cfg_err;
 837                 dev->data->mtu = mtu;
 838         }
 839
 840         ret = hns3vf_dev_configure_vlan(dev);
 841         if (ret)
 842                 goto cfg_err;
 843
 844         /* config hardware GRO */
 845         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 846         ret = hns3_config_gro(hw, gro_en);
 847         if (ret)
 848                 goto cfg_err;
 849
 850         hns->rx_simple_allowed = true;
 851         hns->rx_vec_allowed = true;
 852         hns->tx_simple_allowed = true;
 853         hns->tx_vec_allowed = true;
 854
 855         hns3_init_rx_ptype_tble(dev);
 856
 857         hw->adapter_state = HNS3_NIC_CONFIGURED;
 858         return 0;
 859
 860 cfg_err:
 861         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 862         hw->adapter_state = HNS3_NIC_INITIALIZED;
 863
 864         return ret;
 865 }
 866
 867 static int
 868 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 869 {
 870         int ret;
 871
 872         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 873                                 sizeof(mtu), true, NULL, 0);
 874         if (ret)
 875                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 876
 877         return ret;
 878 }
 879
 880 static int
 881 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 882 {
 883         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 884         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 885         int ret;
 886
 887         /*
 888          * The hns3 PF/VF devices on the same port share the hardware MTU
 889          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 890          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 891          * driver, there is no need to stop the port for hns3 VF device, and the
 892          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 893          * PF's MTU.
 894          */
 895         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 896                 hns3_err(hw, "Failed to set mtu during resetting");
 897                 return -EIO;
 898         }
 899
 900         /*
 901          * when Rx of scattered packets is off, we have some possibility of
 902          * using vector Rx process function or simple Rx functions in hns3 PMD
 903          * driver. If the input MTU is increased and the maximum length of
 904          * received packets is greater than the length of a buffer for Rx
 905          * packet, the hardware network engine needs to use multiple BDs and
 906          * buffers to store these packets. This will cause problems when still
 907          * using vector Rx process function or simple Rx function to receiving
 908          * packets. So, when Rx of scattered packets is off and device is
 909          * started, it is not permitted to increase MTU so that the maximum
 910          * length of Rx packets is greater than Rx buffer length.
 911          */
 912         if (dev->data->dev_started && !dev->data->scattered_rx &&
 913             frame_size > hw->rx_buf_len) {
 914                 hns3_err(hw, "failed to set mtu because current is "
 915                         "not scattered rx mode");
 916                 return -EOPNOTSUPP;
 917         }
 918
 919         rte_spinlock_lock(&hw->lock);
 920         ret = hns3vf_config_mtu(hw, mtu);
 921         if (ret) {
 922                 rte_spinlock_unlock(&hw->lock);
 923                 return ret;
 924         }
 925         if (mtu > RTE_ETHER_MTU)
 926                 dev->data->dev_conf.rxmode.offloads |=
 927                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 928         else
 929                 dev->data->dev_conf.rxmode.offloads &=
 930                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 931         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 932         rte_spinlock_unlock(&hw->lock);
 933
 934         return 0;
 935 }
 936
 937 static int
 938 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 939 {
 940         struct hns3_adapter *hns = eth_dev->data->dev_private;
 941         struct hns3_hw *hw = &hns->hw;
 942         uint16_t q_num = hw->tqps_num;
 943
 944         /*
 945          * In interrupt mode, 'max_rx_queues' is set based on the number of
 946          * MSI-X interrupt resources of the hardware.
 947          */
 948         if (hw->data->dev_conf.intr_conf.rxq == 1)
 949                 q_num = hw->intr_tqps_num;
 950
 951         info->max_rx_queues = q_num;
 952         info->max_tx_queues = hw->tqps_num;
 953         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 954         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 955         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 956         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 957         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 958
 959         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 960                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 961                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 962                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 963                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 964                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 965                                  DEV_RX_OFFLOAD_SCATTER |
 966                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 967                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 968                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 969                                  DEV_RX_OFFLOAD_RSS_HASH |
 970                                  DEV_RX_OFFLOAD_TCP_LRO);
 971         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 972                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 973                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 974                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 975                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 976                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 977                                  DEV_TX_OFFLOAD_TCP_TSO |
 978                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 979                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 980                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 981                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 982                                  hns3_txvlan_cap_get(hw));
 983
 984         if (hns3_dev_indep_txrx_supported(hw))
 985                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 986                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 987
 988         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 989                 .nb_max = HNS3_MAX_RING_DESC,
 990                 .nb_min = HNS3_MIN_RING_DESC,
 991                 .nb_align = HNS3_ALIGN_RING_DESC,
 992         };
 993
 994         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 995                 .nb_max = HNS3_MAX_RING_DESC,
 996                 .nb_min = HNS3_MIN_RING_DESC,
 997                 .nb_align = HNS3_ALIGN_RING_DESC,
 998                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 999                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1000         };
1001
1002         info->default_rxconf = (struct rte_eth_rxconf) {
1003                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1004                 /*
1005                  * If there are no available Rx buffer descriptors, incoming
1006                  * packets are always dropped by hardware based on hns3 network
1007                  * engine.
1008                  */
1009                 .rx_drop_en = 1,
1010                 .offloads = 0,
1011         };
1012         info->default_txconf = (struct rte_eth_txconf) {
1013                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1014                 .offloads = 0,
1015         };
1016
1017         info->vmdq_queue_num = 0;
1018
1019         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1020         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1021         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1022         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1023         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1024
1025         return 0;
1026 }
1027
1028 static void
1029 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1030 {
1031         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1032 }
1033
1034 static void
1035 hns3vf_disable_irq0(struct hns3_hw *hw)
1036 {
1037         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1038 }
1039
1040 static void
1041 hns3vf_enable_irq0(struct hns3_hw *hw)
1042 {
1043         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1044 }
1045
1046 static enum hns3vf_evt_cause
1047 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1048 {
1049         struct hns3_hw *hw = &hns->hw;
1050         enum hns3vf_evt_cause ret;
1051         uint32_t cmdq_stat_reg;
1052         uint32_t rst_ing_reg;
1053         uint32_t val;
1054
1055         /* Fetch the events from their corresponding regs */
1056         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1057
1058         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1059                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1060                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1061                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1062                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1063                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1064                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1065                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1066                 if (clearval) {
1067                         hw->reset.stats.global_cnt++;
1068                         hns3_warn(hw, "Global reset detected, clear reset status");
1069                 } else {
1070                         hns3_schedule_delayed_reset(hns);
1071                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1072                 }
1073
1074                 ret = HNS3VF_VECTOR0_EVENT_RST;
1075                 goto out;
1076         }
1077
1078         /* Check for vector0 mailbox(=CMDQ RX) event source */
1079         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1080                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1081                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1082                 goto out;
1083         }
1084
1085         val = 0;
1086         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1087 out:
1088         if (clearval)
1089                 *clearval = val;
1090         return ret;
1091 }
1092
1093 static void
1094 hns3vf_interrupt_handler(void *param)
1095 {
1096         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1097         struct hns3_adapter *hns = dev->data->dev_private;
1098         struct hns3_hw *hw = &hns->hw;
1099         enum hns3vf_evt_cause event_cause;
1100         uint32_t clearval;
1101
1102         if (hw->irq_thread_id == 0)
1103                 hw->irq_thread_id = pthread_self();
1104
1105         /* Disable interrupt */
1106         hns3vf_disable_irq0(hw);
1107
1108         /* Read out interrupt causes */
1109         event_cause = hns3vf_check_event_cause(hns, &clearval);
1110
1111         switch (event_cause) {
1112         case HNS3VF_VECTOR0_EVENT_RST:
1113                 hns3_schedule_reset(hns);
1114                 break;
1115         case HNS3VF_VECTOR0_EVENT_MBX:
1116                 hns3_dev_handle_mbx_msg(hw);
1117                 break;
1118         default:
1119                 break;
1120         }
1121
1122         /* Clear interrupt causes */
1123         hns3vf_clear_event_cause(hw, clearval);
1124
1125         /* Enable interrupt */
1126         hns3vf_enable_irq0(hw);
1127 }
1128
1129 static void
1130 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1131 {
1132         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1133         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1134         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1135         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1136 }
1137
1138 static void
1139 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1140 {
1141         struct hns3_dev_specs_0_cmd *req0;
1142
1143         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1144
1145         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1146         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1147         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1148         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1149 }
1150
1151 static int
1152 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1153 {
1154         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1155         int ret;
1156         int i;
1157
1158         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1159                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1160                                           true);
1161                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1162         }
1163         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1164
1165         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1166         if (ret)
1167                 return ret;
1168
1169         hns3vf_parse_dev_specifications(hw, desc);
1170
1171         return 0;
1172 }
1173
1174 static int
1175 hns3vf_get_capability(struct hns3_hw *hw)
1176 {
1177         struct rte_pci_device *pci_dev;
1178         struct rte_eth_dev *eth_dev;
1179         uint8_t revision;
1180         int ret;
1181
1182         eth_dev = &rte_eth_devices[hw->data->port_id];
1183         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1184
1185         /* Get PCI revision id */
1186         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1187                                   HNS3_PCI_REVISION_ID);
1188         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1189                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1190                              ret);
1191                 return -EIO;
1192         }
1193         hw->revision = revision;
1194
1195         if (revision < PCI_REVISION_ID_HIP09_A) {
1196                 hns3vf_set_default_dev_specifications(hw);
1197                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1198                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1199                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1200                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1201                 hw->rss_info.ipv6_sctp_offload_supported = false;
1202                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1203                 return 0;
1204         }
1205
1206         ret = hns3vf_query_dev_specifications(hw);
1207         if (ret) {
1208                 PMD_INIT_LOG(ERR,
1209                              "failed to query dev specifications, ret = %d",
1210                              ret);
1211                 return ret;
1212         }
1213
1214         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1215         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1216         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1217         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1218         hw->rss_info.ipv6_sctp_offload_supported = true;
1219         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1220
1221         return 0;
1222 }
1223
1224 static int
1225 hns3vf_check_tqp_info(struct hns3_hw *hw)
1226 {
1227         if (hw->tqps_num == 0) {
1228                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1229                 return -EINVAL;
1230         }
1231
1232         if (hw->rss_size_max == 0) {
1233                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1234                 return -EINVAL;
1235         }
1236
1237         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1238
1239         return 0;
1240 }
1241
1242 static int
1243 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1244 {
1245         uint8_t resp_msg;
1246         int ret;
1247
1248         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1249                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1250                                 true, &resp_msg, sizeof(resp_msg));
1251         if (ret) {
1252                 if (ret == -ETIME) {
1253                         /*
1254                          * Getting current port based VLAN state from PF driver
1255                          * will not affect VF driver's basic function. Because
1256                          * the VF driver relies on hns3 PF kernel ether driver,
1257                          * to avoid introducing compatibility issues with older
1258                          * version of PF driver, no failure will be returned
1259                          * when the return value is ETIME. This return value has
1260                          * the following scenarios:
1261                          * 1) Firmware didn't return the results in time
1262                          * 2) the result return by firmware is timeout
1263                          * 3) the older version of kernel side PF driver does
1264                          *    not support this mailbox message.
1265                          * For scenarios 1 and 2, it is most likely that a
1266                          * hardware error has occurred, or a hardware reset has
1267                          * occurred. In this case, these errors will be caught
1268                          * by other functions.
1269                          */
1270                         PMD_INIT_LOG(WARNING,
1271                                 "failed to get PVID state for timeout, maybe "
1272                                 "kernel side PF driver doesn't support this "
1273                                 "mailbox message, or firmware didn't respond.");
1274                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1275                 } else {
1276                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1277                                 " ret = %d", ret);
1278                         return ret;
1279                 }
1280         }
1281         hw->port_base_vlan_cfg.state = resp_msg ?
1282                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1283         return 0;
1284 }
1285
1286 static int
1287 hns3vf_get_queue_info(struct hns3_hw *hw)
1288 {
1289 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1290         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1291         int ret;
1292
1293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1294                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1295         if (ret) {
1296                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1297                 return ret;
1298         }
1299
1300         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1301         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1302
1303         return hns3vf_check_tqp_info(hw);
1304 }
1305
1306 static int
1307 hns3vf_get_queue_depth(struct hns3_hw *hw)
1308 {
1309 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1310         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1311         int ret;
1312
1313         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1314                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1315         if (ret) {
1316                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1317                              ret);
1318                 return ret;
1319         }
1320
1321         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1322         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1323
1324         return 0;
1325 }
1326
1327 static int
1328 hns3vf_get_tc_info(struct hns3_hw *hw)
1329 {
1330         uint8_t resp_msg;
1331         int ret;
1332         uint32_t i;
1333
1334         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1335                                 true, &resp_msg, sizeof(resp_msg));
1336         if (ret) {
1337                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1338                          ret);
1339                 return ret;
1340         }
1341
1342         hw->hw_tc_map = resp_msg;
1343
1344         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1345                 if (hw->hw_tc_map & BIT(i))
1346                         hw->num_tc++;
1347         }
1348
1349         return 0;
1350 }
1351
1352 static int
1353 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1354 {
1355         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1356         int ret;
1357
1358         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1359                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1360         if (ret) {
1361                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1362                 return ret;
1363         }
1364
1365         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1366
1367         return 0;
1368 }
1369
1370 static int
1371 hns3vf_get_configuration(struct hns3_hw *hw)
1372 {
1373         int ret;
1374
1375         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1376         hw->rss_dis_flag = false;
1377
1378         /* Get device capability */
1379         ret = hns3vf_get_capability(hw);
1380         if (ret) {
1381                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1382                 return ret;
1383         }
1384
1385         /* Get queue configuration from PF */
1386         ret = hns3vf_get_queue_info(hw);
1387         if (ret)
1388                 return ret;
1389
1390         /* Get queue depth info from PF */
1391         ret = hns3vf_get_queue_depth(hw);
1392         if (ret)
1393                 return ret;
1394
1395         /* Get user defined VF MAC addr from PF */
1396         ret = hns3vf_get_host_mac_addr(hw);
1397         if (ret)
1398                 return ret;
1399
1400         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1401         if (ret)
1402                 return ret;
1403
1404         /* Get tc configuration from PF */
1405         return hns3vf_get_tc_info(hw);
1406 }
1407
1408 static int
1409 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1410                             uint16_t nb_tx_q)
1411 {
1412         struct hns3_hw *hw = &hns->hw;
1413
1414         if (nb_rx_q < hw->num_tc) {
1415                 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).",
1416                          nb_rx_q, hw->num_tc);
1417                 return -EINVAL;
1418         }
1419
1420         if (nb_tx_q < hw->num_tc) {
1421                 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).",
1422                          nb_tx_q, hw->num_tc);
1423                 return -EINVAL;
1424         }
1425
1426         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1427 }
1428
1429 static void
1430 hns3vf_request_link_info(struct hns3_hw *hw)
1431 {
1432         uint8_t resp_msg;
1433         int ret;
1434
1435         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1436                 return;
1437         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1438                                 &resp_msg, sizeof(resp_msg));
1439         if (ret)
1440                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1441 }
1442
1443 static int
1444 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1445 {
1446 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1447         struct hns3_hw *hw = &hns->hw;
1448         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1449         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1450         uint8_t is_kill = on ? 0 : 1;
1451
1452         msg_data[0] = is_kill;
1453         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1454         memcpy(&msg_data[3], &proto, sizeof(proto));
1455
1456         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1457                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1458                                  0);
1459 }
1460
1461 static int
1462 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1463 {
1464         struct hns3_adapter *hns = dev->data->dev_private;
1465         struct hns3_hw *hw = &hns->hw;
1466         int ret;
1467
1468         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1469                 hns3_err(hw,
1470                          "vf set vlan id failed during resetting, vlan_id =%u",
1471                          vlan_id);
1472                 return -EIO;
1473         }
1474         rte_spinlock_lock(&hw->lock);
1475         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1476         rte_spinlock_unlock(&hw->lock);
1477         if (ret)
1478                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1479                          vlan_id, ret);
1480
1481         return ret;
1482 }
1483
1484 static int
1485 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1486 {
1487         uint8_t msg_data;
1488         int ret;
1489
1490         msg_data = enable ? 1 : 0;
1491         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1492                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1493         if (ret)
1494                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1495
1496         return ret;
1497 }
1498
1499 static int
1500 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1501 {
1502         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1504         unsigned int tmp_mask;
1505         int ret = 0;
1506
1507         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1508                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1509                              "mask = 0x%x", mask);
1510                 return -EIO;
1511         }
1512
1513         tmp_mask = (unsigned int)mask;
1514         /* Vlan stripping setting */
1515         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1516                 rte_spinlock_lock(&hw->lock);
1517                 /* Enable or disable VLAN stripping */
1518                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1519                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1520                 else
1521                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1522                 rte_spinlock_unlock(&hw->lock);
1523         }
1524
1525         return ret;
1526 }
1527
1528 static int
1529 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1530 {
1531         struct rte_vlan_filter_conf *vfc;
1532         struct hns3_hw *hw = &hns->hw;
1533         uint16_t vlan_id;
1534         uint64_t vbit;
1535         uint64_t ids;
1536         int ret = 0;
1537         uint32_t i;
1538
1539         vfc = &hw->data->vlan_filter_conf;
1540         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1541                 if (vfc->ids[i] == 0)
1542                         continue;
1543                 ids = vfc->ids[i];
1544                 while (ids) {
1545                         /*
1546                          * 64 means the num bits of ids, one bit corresponds to
1547                          * one vlan id
1548                          */
1549                         vlan_id = 64 * i;
1550                         /* count trailing zeroes */
1551                         vbit = ~ids & (ids - 1);
1552                         /* clear least significant bit set */
1553                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1554                         for (; vbit;) {
1555                                 vbit >>= 1;
1556                                 vlan_id++;
1557                         }
1558                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1559                         if (ret) {
1560                                 hns3_err(hw,
1561                                          "VF handle vlan table failed, ret =%d, on = %d",
1562                                          ret, on);
1563                                 return ret;
1564                         }
1565                 }
1566         }
1567
1568         return ret;
1569 }
1570
1571 static int
1572 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1573 {
1574         return hns3vf_handle_all_vlan_table(hns, 0);
1575 }
1576
1577 static int
1578 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1579 {
1580         struct hns3_hw *hw = &hns->hw;
1581         struct rte_eth_conf *dev_conf;
1582         bool en;
1583         int ret;
1584
1585         dev_conf = &hw->data->dev_conf;
1586         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1587                                                                    : false;
1588         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1589         if (ret)
1590                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1591                          ret);
1592         return ret;
1593 }
1594
1595 static int
1596 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1597 {
1598         struct hns3_adapter *hns = dev->data->dev_private;
1599         struct rte_eth_dev_data *data = dev->data;
1600         struct hns3_hw *hw = &hns->hw;
1601         int ret;
1602
1603         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1604             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1605             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1606                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1607                               "or hw_vlan_insert_pvid is not support!");
1608         }
1609
1610         /* Apply vlan offload setting */
1611         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1612         if (ret)
1613                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1614
1615         return ret;
1616 }
1617
1618 static int
1619 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1620 {
1621         uint8_t msg_data;
1622
1623         msg_data = alive ? 1 : 0;
1624         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1625                                  sizeof(msg_data), false, NULL, 0);
1626 }
1627
1628 static void
1629 hns3vf_keep_alive_handler(void *param)
1630 {
1631         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1632         struct hns3_adapter *hns = eth_dev->data->dev_private;
1633         struct hns3_hw *hw = &hns->hw;
1634         uint8_t respmsg;
1635         int ret;
1636
1637         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1638                                 false, &respmsg, sizeof(uint8_t));
1639         if (ret)
1640                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1641                          ret);
1642
1643         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1644                           eth_dev);
1645 }
1646
1647 static void
1648 hns3vf_service_handler(void *param)
1649 {
1650         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1651         struct hns3_adapter *hns = eth_dev->data->dev_private;
1652         struct hns3_hw *hw = &hns->hw;
1653
1654         /*
1655          * The query link status and reset processing are executed in the
1656          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1657          * and the query operation will time out after 30ms. In the case of
1658          * multiple PF/VFs, each query failure timeout causes the IMP reset
1659          * interrupt to fail to respond within 100ms.
1660          * Before querying the link status, check whether there is a reset
1661          * pending, and if so, abandon the query.
1662          */
1663         if (!hns3vf_is_reset_pending(hns))
1664                 hns3vf_request_link_info(hw);
1665         else
1666                 hns3_warn(hw, "Cancel the query when reset is pending");
1667
1668         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1669                           eth_dev);
1670 }
1671
1672 static int
1673 hns3_query_vf_resource(struct hns3_hw *hw)
1674 {
1675         struct hns3_vf_res_cmd *req;
1676         struct hns3_cmd_desc desc;
1677         uint16_t num_msi;
1678         int ret;
1679
1680         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1681         ret = hns3_cmd_send(hw, &desc, 1);
1682         if (ret) {
1683                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1684                 return ret;
1685         }
1686
1687         req = (struct hns3_vf_res_cmd *)desc.data;
1688         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1689                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1690         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1691                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1692                          num_msi, HNS3_MIN_VECTOR_NUM);
1693                 return -EINVAL;
1694         }
1695
1696         hw->num_msi = num_msi;
1697
1698         return 0;
1699 }
1700
1701 static int
1702 hns3vf_init_hardware(struct hns3_adapter *hns)
1703 {
1704         struct hns3_hw *hw = &hns->hw;
1705         uint16_t mtu = hw->data->mtu;
1706         int ret;
1707
1708         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1709         if (ret)
1710                 return ret;
1711
1712         ret = hns3vf_config_mtu(hw, mtu);
1713         if (ret)
1714                 goto err_init_hardware;
1715
1716         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1717         if (ret) {
1718                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1719                 goto err_init_hardware;
1720         }
1721
1722         ret = hns3_config_gro(hw, false);
1723         if (ret) {
1724                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1725                 goto err_init_hardware;
1726         }
1727
1728         /*
1729          * In the initialization clearing the all hardware mapping relationship
1730          * configurations between queues and interrupt vectors is needed, so
1731          * some error caused by the residual configurations, such as the
1732          * unexpected interrupt, can be avoid.
1733          */
1734         ret = hns3vf_init_ring_with_vector(hw);
1735         if (ret) {
1736                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1737                 goto err_init_hardware;
1738         }
1739
1740         ret = hns3vf_set_alive(hw, true);
1741         if (ret) {
1742                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1743                 goto err_init_hardware;
1744         }
1745
1746         return 0;
1747
1748 err_init_hardware:
1749         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1750         return ret;
1751 }
1752
1753 static int
1754 hns3vf_clear_vport_list(struct hns3_hw *hw)
1755 {
1756         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1757                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1758                                  NULL, 0);
1759 }
1760
1761 static int
1762 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1763 {
1764         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1765         struct hns3_adapter *hns = eth_dev->data->dev_private;
1766         struct hns3_hw *hw = &hns->hw;
1767         int ret;
1768
1769         PMD_INIT_FUNC_TRACE();
1770
1771         /* Get hardware io base address from pcie BAR2 IO space */
1772         hw->io_base = pci_dev->mem_resource[2].addr;
1773
1774         /* Firmware command queue initialize */
1775         ret = hns3_cmd_init_queue(hw);
1776         if (ret) {
1777                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1778                 goto err_cmd_init_queue;
1779         }
1780
1781         /* Firmware command initialize */
1782         ret = hns3_cmd_init(hw);
1783         if (ret) {
1784                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1785                 goto err_cmd_init;
1786         }
1787
1788         /* Get VF resource */
1789         ret = hns3_query_vf_resource(hw);
1790         if (ret)
1791                 goto err_cmd_init;
1792
1793         rte_spinlock_init(&hw->mbx_resp.lock);
1794
1795         hns3vf_clear_event_cause(hw, 0);
1796
1797         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1798                                          hns3vf_interrupt_handler, eth_dev);
1799         if (ret) {
1800                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1801                 goto err_intr_callback_register;
1802         }
1803
1804         /* Enable interrupt */
1805         rte_intr_enable(&pci_dev->intr_handle);
1806         hns3vf_enable_irq0(hw);
1807
1808         /* Get configuration from PF */
1809         ret = hns3vf_get_configuration(hw);
1810         if (ret) {
1811                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1812                 goto err_get_config;
1813         }
1814
1815         ret = hns3_tqp_stats_init(hw);
1816         if (ret)
1817                 goto err_get_config;
1818
1819         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1820         if (ret) {
1821                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1822                 goto err_set_tc_queue;
1823         }
1824
1825         ret = hns3vf_clear_vport_list(hw);
1826         if (ret) {
1827                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1828                 goto err_set_tc_queue;
1829         }
1830
1831         ret = hns3vf_init_hardware(hns);
1832         if (ret)
1833                 goto err_set_tc_queue;
1834
1835         hns3_set_default_rss_args(hw);
1836
1837         return 0;
1838
1839 err_set_tc_queue:
1840         hns3_tqp_stats_uninit(hw);
1841
1842 err_get_config:
1843         hns3vf_disable_irq0(hw);
1844         rte_intr_disable(&pci_dev->intr_handle);
1845         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1846                              eth_dev);
1847 err_intr_callback_register:
1848 err_cmd_init:
1849         hns3_cmd_uninit(hw);
1850         hns3_cmd_destroy_queue(hw);
1851 err_cmd_init_queue:
1852         hw->io_base = NULL;
1853
1854         return ret;
1855 }
1856
1857 static void
1858 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1859 {
1860         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1861         struct hns3_adapter *hns = eth_dev->data->dev_private;
1862         struct hns3_hw *hw = &hns->hw;
1863
1864         PMD_INIT_FUNC_TRACE();
1865
1866         hns3_rss_uninit(hns);
1867         (void)hns3_config_gro(hw, false);
1868         (void)hns3vf_set_alive(hw, false);
1869         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1870         hns3_tqp_stats_uninit(hw);
1871         hns3vf_disable_irq0(hw);
1872         rte_intr_disable(&pci_dev->intr_handle);
1873         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1874                              eth_dev);
1875         hns3_cmd_uninit(hw);
1876         hns3_cmd_destroy_queue(hw);
1877         hw->io_base = NULL;
1878 }
1879
1880 static int
1881 hns3vf_do_stop(struct hns3_adapter *hns)
1882 {
1883         struct hns3_hw *hw = &hns->hw;
1884         int ret;
1885
1886         hw->mac.link_status = ETH_LINK_DOWN;
1887
1888         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1889                 hns3vf_configure_mac_addr(hns, true);
1890                 ret = hns3_reset_all_tqps(hns);
1891                 if (ret) {
1892                         hns3_err(hw, "failed to reset all queues ret = %d",
1893                                  ret);
1894                         return ret;
1895                 }
1896         }
1897         return 0;
1898 }
1899
1900 static void
1901 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1902 {
1903         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1905         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1906         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1907         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1908         uint16_t q_id;
1909
1910         if (dev->data->dev_conf.intr_conf.rxq == 0)
1911                 return;
1912
1913         /* unmap the ring with vector */
1914         if (rte_intr_allow_others(intr_handle)) {
1915                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1916                 base = RTE_INTR_VEC_RXTX_OFFSET;
1917         }
1918         if (rte_intr_dp_is_en(intr_handle)) {
1919                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1920                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1921                                                            HNS3_RING_TYPE_RX,
1922                                                            q_id);
1923                         if (vec < base + intr_handle->nb_efd - 1)
1924                                 vec++;
1925                 }
1926         }
1927         /* Clean datapath event and queue/vec mapping */
1928         rte_intr_efd_disable(intr_handle);
1929         if (intr_handle->intr_vec) {
1930                 rte_free(intr_handle->intr_vec);
1931                 intr_handle->intr_vec = NULL;
1932         }
1933 }
1934
1935 static int
1936 hns3vf_dev_stop(struct rte_eth_dev *dev)
1937 {
1938         struct hns3_adapter *hns = dev->data->dev_private;
1939         struct hns3_hw *hw = &hns->hw;
1940
1941         PMD_INIT_FUNC_TRACE();
1942         dev->data->dev_started = 0;
1943
1944         hw->adapter_state = HNS3_NIC_STOPPING;
1945         hns3_set_rxtx_function(dev);
1946         rte_wmb();
1947         /* Disable datapath on secondary process. */
1948         hns3_mp_req_stop_rxtx(dev);
1949         /* Prevent crashes when queues are still in use. */
1950         rte_delay_ms(hw->tqps_num);
1951
1952         rte_spinlock_lock(&hw->lock);
1953         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1954                 hns3_stop_tqps(hw);
1955                 hns3vf_do_stop(hns);
1956                 hns3vf_unmap_rx_interrupt(dev);
1957                 hns3_dev_release_mbufs(hns);
1958                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1959         }
1960         hns3_rx_scattered_reset(dev);
1961         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1962         rte_spinlock_unlock(&hw->lock);
1963
1964         return 0;
1965 }
1966
1967 static int
1968 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1969 {
1970         struct hns3_adapter *hns = eth_dev->data->dev_private;
1971         struct hns3_hw *hw = &hns->hw;
1972         int ret = 0;
1973
1974         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1975                 return 0;
1976
1977         if (hw->adapter_state == HNS3_NIC_STARTED)
1978                 ret = hns3vf_dev_stop(eth_dev);
1979
1980         hw->adapter_state = HNS3_NIC_CLOSING;
1981         hns3_reset_abort(hns);
1982         hw->adapter_state = HNS3_NIC_CLOSED;
1983         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1984         hns3vf_configure_all_mc_mac_addr(hns, true);
1985         hns3vf_remove_all_vlan_table(hns);
1986         hns3vf_uninit_vf(eth_dev);
1987         hns3_free_all_queues(eth_dev);
1988         rte_free(hw->reset.wait_data);
1989         rte_free(eth_dev->process_private);
1990         eth_dev->process_private = NULL;
1991         hns3_mp_uninit_primary();
1992         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1993
1994         return ret;
1995 }
1996
1997 static int
1998 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1999                       size_t fw_size)
2000 {
2001         struct hns3_adapter *hns = eth_dev->data->dev_private;
2002         struct hns3_hw *hw = &hns->hw;
2003         uint32_t version = hw->fw_version;
2004         int ret;
2005
2006         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2007                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2008                                       HNS3_FW_VERSION_BYTE3_S),
2009                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2010                                       HNS3_FW_VERSION_BYTE2_S),
2011                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2012                                       HNS3_FW_VERSION_BYTE1_S),
2013                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2014                                       HNS3_FW_VERSION_BYTE0_S));
2015         ret += 1; /* add the size of '\0' */
2016         if (fw_size < (uint32_t)ret)
2017                 return ret;
2018         else
2019                 return 0;
2020 }
2021
2022 static int
2023 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2024                        __rte_unused int wait_to_complete)
2025 {
2026         struct hns3_adapter *hns = eth_dev->data->dev_private;
2027         struct hns3_hw *hw = &hns->hw;
2028         struct hns3_mac *mac = &hw->mac;
2029         struct rte_eth_link new_link;
2030
2031         memset(&new_link, 0, sizeof(new_link));
2032         switch (mac->link_speed) {
2033         case ETH_SPEED_NUM_10M:
2034         case ETH_SPEED_NUM_100M:
2035         case ETH_SPEED_NUM_1G:
2036         case ETH_SPEED_NUM_10G:
2037         case ETH_SPEED_NUM_25G:
2038         case ETH_SPEED_NUM_40G:
2039         case ETH_SPEED_NUM_50G:
2040         case ETH_SPEED_NUM_100G:
2041         case ETH_SPEED_NUM_200G:
2042                 new_link.link_speed = mac->link_speed;
2043                 break;
2044         default:
2045                 new_link.link_speed = ETH_SPEED_NUM_100M;
2046                 break;
2047         }
2048
2049         new_link.link_duplex = mac->link_duplex;
2050         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2051         new_link.link_autoneg =
2052             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2053
2054         return rte_eth_linkstatus_set(eth_dev, &new_link);
2055 }
2056
2057 static int
2058 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2059 {
2060         struct hns3_hw *hw = &hns->hw;
2061         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2062         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2063         int ret;
2064
2065         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2066         if (ret)
2067                 return ret;
2068
2069         ret = hns3_init_queues(hns, reset_queue);
2070         if (ret)
2071                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2072
2073         return ret;
2074 }
2075
2076 static int
2077 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2078 {
2079         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2080         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2081         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2083         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2084         uint32_t intr_vector;
2085         uint16_t q_id;
2086         int ret;
2087
2088         if (dev->data->dev_conf.intr_conf.rxq == 0)
2089                 return 0;
2090
2091         /* disable uio/vfio intr/eventfd mapping */
2092         rte_intr_disable(intr_handle);
2093
2094         /* check and configure queue intr-vector mapping */
2095         if (rte_intr_cap_multiple(intr_handle) ||
2096             !RTE_ETH_DEV_SRIOV(dev).active) {
2097                 intr_vector = hw->used_rx_queues;
2098                 /* It creates event fd for each intr vector when MSIX is used */
2099                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2100                         return -EINVAL;
2101         }
2102         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2103                 intr_handle->intr_vec =
2104                         rte_zmalloc("intr_vec",
2105                                     hw->used_rx_queues * sizeof(int), 0);
2106                 if (intr_handle->intr_vec == NULL) {
2107                         hns3_err(hw, "Failed to allocate %u rx_queues"
2108                                      " intr_vec", hw->used_rx_queues);
2109                         ret = -ENOMEM;
2110                         goto vf_alloc_intr_vec_error;
2111                 }
2112         }
2113
2114         if (rte_intr_allow_others(intr_handle)) {
2115                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2116                 base = RTE_INTR_VEC_RXTX_OFFSET;
2117         }
2118         if (rte_intr_dp_is_en(intr_handle)) {
2119                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2120                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2121                                                            HNS3_RING_TYPE_RX,
2122                                                            q_id);
2123                         if (ret)
2124                                 goto vf_bind_vector_error;
2125                         intr_handle->intr_vec[q_id] = vec;
2126                         if (vec < base + intr_handle->nb_efd - 1)
2127                                 vec++;
2128                 }
2129         }
2130         rte_intr_enable(intr_handle);
2131         return 0;
2132
2133 vf_bind_vector_error:
2134         rte_intr_efd_disable(intr_handle);
2135         if (intr_handle->intr_vec) {
2136                 free(intr_handle->intr_vec);
2137                 intr_handle->intr_vec = NULL;
2138         }
2139         return ret;
2140 vf_alloc_intr_vec_error:
2141         rte_intr_efd_disable(intr_handle);
2142         return ret;
2143 }
2144
2145 static int
2146 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2147 {
2148         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2149         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2150         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2151         uint16_t q_id;
2152         int ret;
2153
2154         if (dev->data->dev_conf.intr_conf.rxq == 0)
2155                 return 0;
2156
2157         if (rte_intr_dp_is_en(intr_handle)) {
2158                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2159                         ret = hns3vf_bind_ring_with_vector(hw,
2160                                         intr_handle->intr_vec[q_id], true,
2161                                         HNS3_RING_TYPE_RX, q_id);
2162                         if (ret)
2163                                 return ret;
2164                 }
2165         }
2166
2167         return 0;
2168 }
2169
2170 static void
2171 hns3vf_restore_filter(struct rte_eth_dev *dev)
2172 {
2173         hns3_restore_rss_filter(dev);
2174 }
2175
2176 static int
2177 hns3vf_dev_start(struct rte_eth_dev *dev)
2178 {
2179         struct hns3_adapter *hns = dev->data->dev_private;
2180         struct hns3_hw *hw = &hns->hw;
2181         int ret;
2182
2183         PMD_INIT_FUNC_TRACE();
2184         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2185                 return -EBUSY;
2186
2187         rte_spinlock_lock(&hw->lock);
2188         hw->adapter_state = HNS3_NIC_STARTING;
2189         ret = hns3vf_do_start(hns, true);
2190         if (ret) {
2191                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2192                 rte_spinlock_unlock(&hw->lock);
2193                 return ret;
2194         }
2195         ret = hns3vf_map_rx_interrupt(dev);
2196         if (ret) {
2197                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2198                 rte_spinlock_unlock(&hw->lock);
2199                 return ret;
2200         }
2201
2202         /*
2203          * There are three register used to control the status of a TQP
2204          * (contains a pair of Tx queue and Rx queue) in the new version network
2205          * engine. One is used to control the enabling of Tx queue, the other is
2206          * used to control the enabling of Rx queue, and the last is the master
2207          * switch used to control the enabling of the tqp. The Tx register and
2208          * TQP register must be enabled at the same time to enable a Tx queue.
2209          * The same applies to the Rx queue. For the older network enginem, this
2210          * function only refresh the enabled flag, and it is used to update the
2211          * status of queue in the dpdk framework.
2212          */
2213         ret = hns3_start_all_txqs(dev);
2214         if (ret) {
2215                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2216                 rte_spinlock_unlock(&hw->lock);
2217                 return ret;
2218         }
2219
2220         ret = hns3_start_all_rxqs(dev);
2221         if (ret) {
2222                 hns3_stop_all_txqs(dev);
2223                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2224                 rte_spinlock_unlock(&hw->lock);
2225                 return ret;
2226         }
2227
2228         hw->adapter_state = HNS3_NIC_STARTED;
2229         rte_spinlock_unlock(&hw->lock);
2230
2231         hns3_rx_scattered_calc(dev);
2232         hns3_set_rxtx_function(dev);
2233         hns3_mp_req_start_rxtx(dev);
2234         hns3vf_service_handler(dev);
2235
2236         hns3vf_restore_filter(dev);
2237
2238         /* Enable interrupt of all rx queues before enabling queues */
2239         hns3_dev_all_rx_queue_intr_enable(hw, true);
2240
2241         /*
2242          * After finished the initialization, start all tqps to receive/transmit
2243          * packets and refresh all queue status.
2244          */
2245         hns3_start_tqps(hw);
2246
2247         return ret;
2248 }
2249
2250 static bool
2251 is_vf_reset_done(struct hns3_hw *hw)
2252 {
2253 #define HNS3_FUN_RST_ING_BITS \
2254         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2255          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2256          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2257          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2258
2259         uint32_t val;
2260
2261         if (hw->reset.level == HNS3_VF_RESET) {
2262                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2263                 if (val & HNS3_VF_RST_ING_BIT)
2264                         return false;
2265         } else {
2266                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2267                 if (val & HNS3_FUN_RST_ING_BITS)
2268                         return false;
2269         }
2270         return true;
2271 }
2272
2273 bool
2274 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2275 {
2276         struct hns3_hw *hw = &hns->hw;
2277         enum hns3_reset_level reset;
2278
2279         /*
2280          * According to the protocol of PCIe, FLR to a PF device resets the PF
2281          * state as well as the SR-IOV extended capability including VF Enable
2282          * which means that VFs no longer exist.
2283          *
2284          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2285          * is in FLR stage, the register state of VF device is not reliable,
2286          * so register states detection can not be carried out. In this case,
2287          * we just ignore the register states and return false to indicate that
2288          * there are no other reset states that need to be processed by driver.
2289          */
2290         if (hw->reset.level == HNS3_VF_FULL_RESET)
2291                 return false;
2292
2293         /* Check the registers to confirm whether there is reset pending */
2294         hns3vf_check_event_cause(hns, NULL);
2295         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2296         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2297                 hns3_warn(hw, "High level reset %d is pending", reset);
2298                 return true;
2299         }
2300         return false;
2301 }
2302
2303 static int
2304 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2305 {
2306         struct hns3_hw *hw = &hns->hw;
2307         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2308         struct timeval tv;
2309
2310         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2311                 /*
2312                  * After vf reset is ready, the PF may not have completed
2313                  * the reset processing. The vf sending mbox to PF may fail
2314                  * during the pf reset, so it is better to add extra delay.
2315                  */
2316                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2317                     hw->reset.level == HNS3_FLR_RESET)
2318                         return 0;
2319                 /* Reset retry process, no need to add extra delay. */
2320                 if (hw->reset.attempts)
2321                         return 0;
2322                 if (wait_data->check_completion == NULL)
2323                         return 0;
2324
2325                 wait_data->check_completion = NULL;
2326                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2327                 wait_data->count = 1;
2328                 wait_data->result = HNS3_WAIT_REQUEST;
2329                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2330                                   wait_data);
2331                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2332                 return -EAGAIN;
2333         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2334                 gettimeofday(&tv, NULL);
2335                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2336                           tv.tv_sec, tv.tv_usec);
2337                 return -ETIME;
2338         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2339                 return -EAGAIN;
2340
2341         wait_data->hns = hns;
2342         wait_data->check_completion = is_vf_reset_done;
2343         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2344                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2345         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2346         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2347         wait_data->result = HNS3_WAIT_REQUEST;
2348         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2349         return -EAGAIN;
2350 }
2351
2352 static int
2353 hns3vf_prepare_reset(struct hns3_adapter *hns)
2354 {
2355         struct hns3_hw *hw = &hns->hw;
2356         int ret = 0;
2357
2358         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2359                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2360                                         0, true, NULL, 0);
2361         }
2362         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2363
2364         return ret;
2365 }
2366
2367 static int
2368 hns3vf_stop_service(struct hns3_adapter *hns)
2369 {
2370         struct hns3_hw *hw = &hns->hw;
2371         struct rte_eth_dev *eth_dev;
2372
2373         eth_dev = &rte_eth_devices[hw->data->port_id];
2374         if (hw->adapter_state == HNS3_NIC_STARTED)
2375                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2376         hw->mac.link_status = ETH_LINK_DOWN;
2377
2378         hns3_set_rxtx_function(eth_dev);
2379         rte_wmb();
2380         /* Disable datapath on secondary process. */
2381         hns3_mp_req_stop_rxtx(eth_dev);
2382         rte_delay_ms(hw->tqps_num);
2383
2384         rte_spinlock_lock(&hw->lock);
2385         if (hw->adapter_state == HNS3_NIC_STARTED ||
2386             hw->adapter_state == HNS3_NIC_STOPPING) {
2387                 hns3_enable_all_queues(hw, false);
2388                 hns3vf_do_stop(hns);
2389                 hw->reset.mbuf_deferred_free = true;
2390         } else
2391                 hw->reset.mbuf_deferred_free = false;
2392
2393         /*
2394          * It is cumbersome for hardware to pick-and-choose entries for deletion
2395          * from table space. Hence, for function reset software intervention is
2396          * required to delete the entries.
2397          */
2398         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2399                 hns3vf_configure_all_mc_mac_addr(hns, true);
2400         rte_spinlock_unlock(&hw->lock);
2401
2402         return 0;
2403 }
2404
2405 static int
2406 hns3vf_start_service(struct hns3_adapter *hns)
2407 {
2408         struct hns3_hw *hw = &hns->hw;
2409         struct rte_eth_dev *eth_dev;
2410
2411         eth_dev = &rte_eth_devices[hw->data->port_id];
2412         hns3_set_rxtx_function(eth_dev);
2413         hns3_mp_req_start_rxtx(eth_dev);
2414         if (hw->adapter_state == HNS3_NIC_STARTED) {
2415                 hns3vf_service_handler(eth_dev);
2416
2417                 /* Enable interrupt of all rx queues before enabling queues */
2418                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2419                 /*
2420                  * Enable state of each rxq and txq will be recovered after
2421                  * reset, so we need to restore them before enable all tqps;
2422                  */
2423                 hns3_restore_tqp_enable_state(hw);
2424                 /*
2425                  * When finished the initialization, enable queues to receive
2426                  * and transmit packets.
2427                  */
2428                 hns3_enable_all_queues(hw, true);
2429         }
2430
2431         return 0;
2432 }
2433
2434 static int
2435 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2436 {
2437         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2438         struct rte_ether_addr *hw_mac;
2439         int ret;
2440
2441         /*
2442          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2443          * on the host by "ip link set ..." command. If the hns3 PF kernel
2444          * ethdev driver sets the MAC address for VF device after the
2445          * initialization of the related VF device, the PF driver will notify
2446          * VF driver to reset VF device to make the new MAC address effective
2447          * immediately. The hns3 VF PMD driver should check whether the MAC
2448          * address has been changed by the PF kernel ethdev driver, if changed
2449          * VF driver should configure hardware using the new MAC address in the
2450          * recovering hardware configuration stage of the reset process.
2451          */
2452         ret = hns3vf_get_host_mac_addr(hw);
2453         if (ret)
2454                 return ret;
2455
2456         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2457         ret = rte_is_zero_ether_addr(hw_mac);
2458         if (ret) {
2459                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2460         } else {
2461                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2462                 if (!ret) {
2463                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2464                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2465                                               &hw->data->mac_addrs[0]);
2466                         hns3_warn(hw, "Default MAC address has been changed to:"
2467                                   " %s by the host PF kernel ethdev driver",
2468                                   mac_str);
2469                 }
2470         }
2471
2472         return 0;
2473 }
2474
2475 static int
2476 hns3vf_restore_conf(struct hns3_adapter *hns)
2477 {
2478         struct hns3_hw *hw = &hns->hw;
2479         int ret;
2480
2481         ret = hns3vf_check_default_mac_change(hw);
2482         if (ret)
2483                 return ret;
2484
2485         ret = hns3vf_configure_mac_addr(hns, false);
2486         if (ret)
2487                 return ret;
2488
2489         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2490         if (ret)
2491                 goto err_mc_mac;
2492
2493         ret = hns3vf_restore_promisc(hns);
2494         if (ret)
2495                 goto err_vlan_table;
2496
2497         ret = hns3vf_restore_vlan_conf(hns);
2498         if (ret)
2499                 goto err_vlan_table;
2500
2501         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2502         if (ret)
2503                 goto err_vlan_table;
2504
2505         ret = hns3vf_restore_rx_interrupt(hw);
2506         if (ret)
2507                 goto err_vlan_table;
2508
2509         ret = hns3_restore_gro_conf(hw);
2510         if (ret)
2511                 goto err_vlan_table;
2512
2513         if (hw->adapter_state == HNS3_NIC_STARTED) {
2514                 ret = hns3vf_do_start(hns, false);
2515                 if (ret)
2516                         goto err_vlan_table;
2517                 hns3_info(hw, "hns3vf dev restart successful!");
2518         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2519                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2520         return 0;
2521
2522 err_vlan_table:
2523         hns3vf_configure_all_mc_mac_addr(hns, true);
2524 err_mc_mac:
2525         hns3vf_configure_mac_addr(hns, true);
2526         return ret;
2527 }
2528
2529 static enum hns3_reset_level
2530 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2531 {
2532         enum hns3_reset_level reset_level;
2533
2534         /* return the highest priority reset level amongst all */
2535         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2536                 reset_level = HNS3_VF_RESET;
2537         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2538                 reset_level = HNS3_VF_FULL_RESET;
2539         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2540                 reset_level = HNS3_VF_PF_FUNC_RESET;
2541         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2542                 reset_level = HNS3_VF_FUNC_RESET;
2543         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2544                 reset_level = HNS3_FLR_RESET;
2545         else
2546                 reset_level = HNS3_NONE_RESET;
2547
2548         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2549                 return HNS3_NONE_RESET;
2550
2551         return reset_level;
2552 }
2553
2554 static void
2555 hns3vf_reset_service(void *param)
2556 {
2557         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2558         struct hns3_hw *hw = &hns->hw;
2559         enum hns3_reset_level reset_level;
2560         struct timeval tv_delta;
2561         struct timeval tv_start;
2562         struct timeval tv;
2563         uint64_t msec;
2564
2565         /*
2566          * The interrupt is not triggered within the delay time.
2567          * The interrupt may have been lost. It is necessary to handle
2568          * the interrupt to recover from the error.
2569          */
2570         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2571                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2572                 hns3_err(hw, "Handling interrupts in delayed tasks");
2573                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2574                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2575                 if (reset_level == HNS3_NONE_RESET) {
2576                         hns3_err(hw, "No reset level is set, try global reset");
2577                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2578                 }
2579         }
2580         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2581
2582         /*
2583          * Hardware reset has been notified, we now have to poll & check if
2584          * hardware has actually completed the reset sequence.
2585          */
2586         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2587         if (reset_level != HNS3_NONE_RESET) {
2588                 gettimeofday(&tv_start, NULL);
2589                 hns3_reset_process(hns, reset_level);
2590                 gettimeofday(&tv, NULL);
2591                 timersub(&tv, &tv_start, &tv_delta);
2592                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2593                        tv_delta.tv_usec / USEC_PER_MSEC;
2594                 if (msec > HNS3_RESET_PROCESS_MS)
2595                         hns3_err(hw, "%d handle long time delta %" PRIx64
2596                                  " ms time=%ld.%.6ld",
2597                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2598         }
2599 }
2600
2601 static int
2602 hns3vf_reinit_dev(struct hns3_adapter *hns)
2603 {
2604         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2605         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2606         struct hns3_hw *hw = &hns->hw;
2607         int ret;
2608
2609         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2610                 rte_intr_disable(&pci_dev->intr_handle);
2611                 ret = hns3vf_set_bus_master(pci_dev, true);
2612                 if (ret < 0) {
2613                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2614                         return ret;
2615                 }
2616         }
2617
2618         /* Firmware command initialize */
2619         ret = hns3_cmd_init(hw);
2620         if (ret) {
2621                 hns3_err(hw, "Failed to init cmd: %d", ret);
2622                 return ret;
2623         }
2624
2625         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2626                 /*
2627                  * UIO enables msix by writing the pcie configuration space
2628                  * vfio_pci enables msix in rte_intr_enable.
2629                  */
2630                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2631                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2632                         if (hns3vf_enable_msix(pci_dev, true))
2633                                 hns3_err(hw, "Failed to enable msix");
2634                 }
2635
2636                 rte_intr_enable(&pci_dev->intr_handle);
2637         }
2638
2639         ret = hns3_reset_all_tqps(hns);
2640         if (ret) {
2641                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2642                 return ret;
2643         }
2644
2645         ret = hns3vf_init_hardware(hns);
2646         if (ret) {
2647                 hns3_err(hw, "Failed to init hardware: %d", ret);
2648                 return ret;
2649         }
2650
2651         return 0;
2652 }
2653
2654 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2655         .dev_configure      = hns3vf_dev_configure,
2656         .dev_start          = hns3vf_dev_start,
2657         .dev_stop           = hns3vf_dev_stop,
2658         .dev_close          = hns3vf_dev_close,
2659         .mtu_set            = hns3vf_dev_mtu_set,
2660         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2661         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2662         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2663         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2664         .stats_get          = hns3_stats_get,
2665         .stats_reset        = hns3_stats_reset,
2666         .xstats_get         = hns3_dev_xstats_get,
2667         .xstats_get_names   = hns3_dev_xstats_get_names,
2668         .xstats_reset       = hns3_dev_xstats_reset,
2669         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2670         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2671         .dev_infos_get      = hns3vf_dev_infos_get,
2672         .fw_version_get     = hns3vf_fw_version_get,
2673         .rx_queue_setup     = hns3_rx_queue_setup,
2674         .tx_queue_setup     = hns3_tx_queue_setup,
2675         .rx_queue_release   = hns3_dev_rx_queue_release,
2676         .tx_queue_release   = hns3_dev_tx_queue_release,
2677         .rx_queue_start     = hns3_dev_rx_queue_start,
2678         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2679         .tx_queue_start     = hns3_dev_tx_queue_start,
2680         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2681         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2682         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2683         .rxq_info_get       = hns3_rxq_info_get,
2684         .txq_info_get       = hns3_txq_info_get,
2685         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2686         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2687         .mac_addr_add       = hns3vf_add_mac_addr,
2688         .mac_addr_remove    = hns3vf_remove_mac_addr,
2689         .mac_addr_set       = hns3vf_set_default_mac_addr,
2690         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2691         .link_update        = hns3vf_dev_link_update,
2692         .rss_hash_update    = hns3_dev_rss_hash_update,
2693         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2694         .reta_update        = hns3_dev_rss_reta_update,
2695         .reta_query         = hns3_dev_rss_reta_query,
2696         .filter_ctrl        = hns3_dev_filter_ctrl,
2697         .vlan_filter_set    = hns3vf_vlan_filter_set,
2698         .vlan_offload_set   = hns3vf_vlan_offload_set,
2699         .get_reg            = hns3_get_regs,
2700         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2701 };
2702
2703 static const struct hns3_reset_ops hns3vf_reset_ops = {
2704         .reset_service       = hns3vf_reset_service,
2705         .stop_service        = hns3vf_stop_service,
2706         .prepare_reset       = hns3vf_prepare_reset,
2707         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2708         .reinit_dev          = hns3vf_reinit_dev,
2709         .restore_conf        = hns3vf_restore_conf,
2710         .start_service       = hns3vf_start_service,
2711 };
2712
2713 static int
2714 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2715 {
2716         struct hns3_adapter *hns = eth_dev->data->dev_private;
2717         struct hns3_hw *hw = &hns->hw;
2718         int ret;
2719
2720         PMD_INIT_FUNC_TRACE();
2721
2722         eth_dev->process_private = (struct hns3_process_private *)
2723             rte_zmalloc_socket("hns3_filter_list",
2724                                sizeof(struct hns3_process_private),
2725                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2726         if (eth_dev->process_private == NULL) {
2727                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2728                 return -ENOMEM;
2729         }
2730
2731         /* initialize flow filter lists */
2732         hns3_filterlist_init(eth_dev);
2733
2734         hns3_set_rxtx_function(eth_dev);
2735         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2736         eth_dev->rx_queue_count = hns3_rx_queue_count;
2737         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2738                 ret = hns3_mp_init_secondary();
2739                 if (ret) {
2740                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2741                                           "process, ret = %d", ret);
2742                         goto err_mp_init_secondary;
2743                 }
2744
2745                 hw->secondary_cnt++;
2746                 return 0;
2747         }
2748
2749         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2750
2751         ret = hns3_mp_init_primary();
2752         if (ret) {
2753                 PMD_INIT_LOG(ERR,
2754                              "Failed to init for primary process, ret = %d",
2755                              ret);
2756                 goto err_mp_init_primary;
2757         }
2758
2759         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2760         hns->is_vf = true;
2761         hw->data = eth_dev->data;
2762
2763         ret = hns3_reset_init(hw);
2764         if (ret)
2765                 goto err_init_reset;
2766         hw->reset.ops = &hns3vf_reset_ops;
2767
2768         ret = hns3vf_init_vf(eth_dev);
2769         if (ret) {
2770                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2771                 goto err_init_vf;
2772         }
2773
2774         /* Allocate memory for storing MAC addresses */
2775         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2776                                                sizeof(struct rte_ether_addr) *
2777                                                HNS3_VF_UC_MACADDR_NUM, 0);
2778         if (eth_dev->data->mac_addrs == NULL) {
2779                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2780                              "to store MAC addresses",
2781                              sizeof(struct rte_ether_addr) *
2782                              HNS3_VF_UC_MACADDR_NUM);
2783                 ret = -ENOMEM;
2784                 goto err_rte_zmalloc;
2785         }
2786
2787         /*
2788          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2789          * on the host by "ip link set ..." command. To avoid some incorrect
2790          * scenes, for example, hns3 VF PMD driver fails to receive and send
2791          * packets after user configure the MAC address by using the
2792          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2793          * address strategy as the hns3 kernel ethdev driver in the
2794          * initialization. If user configure a MAC address by the ip command
2795          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2796          * start with a random MAC address in the initialization.
2797          */
2798         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2799                 rte_eth_random_addr(hw->mac.mac_addr);
2800         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2801                             &eth_dev->data->mac_addrs[0]);
2802
2803         hw->adapter_state = HNS3_NIC_INITIALIZED;
2804
2805         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2806                 hns3_err(hw, "Reschedule reset service after dev_init");
2807                 hns3_schedule_reset(hns);
2808         } else {
2809                 /* IMP will wait ready flag before reset */
2810                 hns3_notify_reset_ready(hw, false);
2811         }
2812         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2813                           eth_dev);
2814         return 0;
2815
2816 err_rte_zmalloc:
2817         hns3vf_uninit_vf(eth_dev);
2818
2819 err_init_vf:
2820         rte_free(hw->reset.wait_data);
2821
2822 err_init_reset:
2823         hns3_mp_uninit_primary();
2824
2825 err_mp_init_primary:
2826 err_mp_init_secondary:
2827         eth_dev->dev_ops = NULL;
2828         eth_dev->rx_pkt_burst = NULL;
2829         eth_dev->tx_pkt_burst = NULL;
2830         eth_dev->tx_pkt_prepare = NULL;
2831         rte_free(eth_dev->process_private);
2832         eth_dev->process_private = NULL;
2833
2834         return ret;
2835 }
2836
2837 static int
2838 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2839 {
2840         struct hns3_adapter *hns = eth_dev->data->dev_private;
2841         struct hns3_hw *hw = &hns->hw;
2842
2843         PMD_INIT_FUNC_TRACE();
2844
2845         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2846                 return -EPERM;
2847
2848         if (hw->adapter_state < HNS3_NIC_CLOSING)
2849                 hns3vf_dev_close(eth_dev);
2850
2851         hw->adapter_state = HNS3_NIC_REMOVED;
2852         return 0;
2853 }
2854
2855 static int
2856 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2857                      struct rte_pci_device *pci_dev)
2858 {
2859         return rte_eth_dev_pci_generic_probe(pci_dev,
2860                                              sizeof(struct hns3_adapter),
2861                                              hns3vf_dev_init);
2862 }
2863
2864 static int
2865 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2866 {
2867         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2868 }
2869
2870 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2871         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2872         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2873         { .vendor_id = 0, }, /* sentinel */
2874 };
2875
2876 static struct rte_pci_driver rte_hns3vf_pmd = {
2877         .id_table = pci_id_hns3vf_map,
2878         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2879         .probe = eth_hns3vf_pci_probe,
2880         .remove = eth_hns3vf_pci_remove,
2881 };
2882
2883 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2884 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2885 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");