1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <arpa/inet.h>
12 #include <linux/pci_regs.h>
14 #include <rte_alarm.h>
15 #include <rte_atomic.h>
16 #include <rte_bus_pci.h>
17 #include <rte_byteorder.h>
18 #include <rte_common.h>
19 #include <rte_cycles.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
24 #include <rte_ethdev_pci.h>
25 #include <rte_interrupts.h>
31 #include "hns3_ethdev.h"
32 #include "hns3_logs.h"
33 #include "hns3_rxtx.h"
34 #include "hns3_regs.h"
35 #include "hns3_intr.h"
39 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
40 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
42 #define HNS3VF_RESET_WAIT_MS 20
43 #define HNS3VF_RESET_WAIT_CNT 2000
45 /* Reset related Registers */
46 #define HNS3_GLOBAL_RESET_BIT 0
47 #define HNS3_CORE_RESET_BIT 1
48 #define HNS3_IMP_RESET_BIT 2
49 #define HNS3_FUN_RST_ING_B 0
51 enum hns3vf_evt_cause {
52 HNS3VF_VECTOR0_EVENT_RST,
53 HNS3VF_VECTOR0_EVENT_MBX,
54 HNS3VF_VECTOR0_EVENT_OTHER,
57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
63 struct rte_ether_addr *mac_addr);
64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
65 struct rte_ether_addr *mac_addr);
66 /* set PCI bus mastering */
68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
72 rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
75 /* set the master bit */
76 reg |= PCI_COMMAND_MASTER;
78 reg &= ~(PCI_COMMAND_MASTER);
80 rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
84 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
85 * @cap: the capability
87 * Return the address of the given capability within the PCI capability list.
90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
92 #define MAX_PCIE_CAPABILITY 48
98 rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
99 if (!(status & PCI_STATUS_CAP_LIST))
102 ttl = MAX_PCIE_CAPABILITY;
103 rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
104 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
105 rte_pci_read_config(device, &id, sizeof(id),
106 (pos + PCI_CAP_LIST_ID));
114 rte_pci_read_config(device, &pos, sizeof(pos),
115 (pos + PCI_CAP_LIST_NEXT));
121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
126 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
128 rte_pci_read_config(device, &control, sizeof(control),
129 (pos + PCI_MSIX_FLAGS));
131 control |= PCI_MSIX_FLAGS_ENABLE;
133 control &= ~PCI_MSIX_FLAGS_ENABLE;
134 rte_pci_write_config(device, &control, sizeof(control),
135 (pos + PCI_MSIX_FLAGS));
142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
144 /* mac address was checked by upper level interface */
145 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
148 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
149 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
150 RTE_ETHER_ADDR_LEN, false, NULL, 0);
152 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
154 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
163 /* mac address was checked by upper level interface */
164 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
167 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
168 HNS3_MBX_MAC_VLAN_UC_REMOVE,
169 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
172 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
174 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
183 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
184 struct rte_ether_addr *addr;
188 for (i = 0; i < hw->mc_addrs_num; i++) {
189 addr = &hw->mc_addrs[i];
190 /* Check if there are duplicate addresses */
191 if (rte_is_same_ether_addr(addr, mac_addr)) {
192 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
194 hns3_err(hw, "failed to add mc mac addr, same addrs"
195 "(%s) is added by the set_mc_mac_addr_list "
201 ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
203 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
205 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
213 __rte_unused uint32_t idx,
214 __rte_unused uint32_t pool)
216 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
217 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
220 rte_spinlock_lock(&hw->lock);
223 * In hns3 network engine adding UC and MC mac address with different
224 * commands with firmware. We need to determine whether the input
225 * address is a UC or a MC address to call different commands.
226 * By the way, it is recommended calling the API function named
227 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
228 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
229 * may affect the specifications of UC mac addresses.
231 if (rte_is_multicast_ether_addr(mac_addr))
232 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
234 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
236 rte_spinlock_unlock(&hw->lock);
238 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
240 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
250 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
251 /* index will be checked by upper level rte interface */
252 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
253 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
256 rte_spinlock_lock(&hw->lock);
258 if (rte_is_multicast_ether_addr(mac_addr))
259 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
261 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
263 rte_spinlock_unlock(&hw->lock);
265 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
267 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
274 struct rte_ether_addr *mac_addr)
276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
277 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
278 struct rte_ether_addr *old_addr;
279 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
280 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
284 * It has been guaranteed that input parameter named mac_addr is valid
285 * address in the rte layer of DPDK framework.
287 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
288 rte_spinlock_lock(&hw->lock);
289 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
290 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
293 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
294 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
295 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
298 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
299 * driver. When user has configured a MAC address for VF device
300 * by "ip link set ..." command based on the PF device, the hns3
301 * PF kernel ethdev driver does not allow VF driver to request
302 * reconfiguring a different default MAC address, and return
303 * -EPREM to VF driver through mailbox.
306 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
308 hns3_warn(hw, "Has permanet mac addr(%s) for vf",
311 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
313 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
318 rte_ether_addr_copy(mac_addr,
319 (struct rte_ether_addr *)hw->mac.mac_addr);
320 rte_spinlock_unlock(&hw->lock);
326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
328 struct hns3_hw *hw = &hns->hw;
329 struct rte_ether_addr *addr;
330 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
335 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
336 addr = &hw->data->mac_addrs[i];
337 if (rte_is_zero_ether_addr(addr))
339 if (rte_is_multicast_ether_addr(addr))
340 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
341 hns3vf_add_mc_mac_addr(hw, addr);
343 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
344 hns3vf_add_uc_mac_addr(hw, addr);
348 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
350 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
351 "ret = %d.", del ? "remove" : "restore",
359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
360 struct rte_ether_addr *mac_addr)
362 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
365 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
366 HNS3_MBX_MAC_VLAN_MC_ADD,
367 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
370 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
372 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
381 struct rte_ether_addr *mac_addr)
383 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
386 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
387 HNS3_MBX_MAC_VLAN_MC_REMOVE,
388 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
391 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
393 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
402 struct rte_ether_addr *mc_addr_set,
405 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
406 struct rte_ether_addr *addr;
410 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
411 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
412 "invalid. valid range: 0~%d",
413 nb_mc_addr, HNS3_MC_MACADDR_NUM);
417 /* Check if input mac addresses are valid */
418 for (i = 0; i < nb_mc_addr; i++) {
419 addr = &mc_addr_set[i];
420 if (!rte_is_multicast_ether_addr(addr)) {
421 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
424 "failed to set mc mac addr, addr(%s) invalid.",
429 /* Check if there are duplicate addresses */
430 for (j = i + 1; j < nb_mc_addr; j++) {
431 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
432 rte_ether_format_addr(mac_str,
433 RTE_ETHER_ADDR_FMT_SIZE,
435 hns3_err(hw, "failed to set mc mac addr, "
436 "addrs invalid. two same addrs(%s).",
443 * Check if there are duplicate addresses between mac_addrs
446 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
447 if (rte_is_same_ether_addr(addr,
448 &hw->data->mac_addrs[j])) {
449 rte_ether_format_addr(mac_str,
450 RTE_ETHER_ADDR_FMT_SIZE,
452 hns3_err(hw, "failed to set mc mac addr, "
453 "addrs invalid. addrs(%s) has already "
454 "configured in mac_addr add API",
465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
466 struct rte_ether_addr *mc_addr_set,
469 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
470 struct rte_ether_addr *addr;
477 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
481 rte_spinlock_lock(&hw->lock);
482 cur_addr_num = hw->mc_addrs_num;
483 for (i = 0; i < cur_addr_num; i++) {
484 num = cur_addr_num - i - 1;
485 addr = &hw->mc_addrs[num];
486 ret = hns3vf_remove_mc_mac_addr(hw, addr);
488 rte_spinlock_unlock(&hw->lock);
495 set_addr_num = (int)nb_mc_addr;
496 for (i = 0; i < set_addr_num; i++) {
497 addr = &mc_addr_set[i];
498 ret = hns3vf_add_mc_mac_addr(hw, addr);
500 rte_spinlock_unlock(&hw->lock);
504 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
507 rte_spinlock_unlock(&hw->lock);
513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
515 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
516 struct hns3_hw *hw = &hns->hw;
517 struct rte_ether_addr *addr;
522 for (i = 0; i < hw->mc_addrs_num; i++) {
523 addr = &hw->mc_addrs[i];
524 if (!rte_is_multicast_ether_addr(addr))
527 ret = hns3vf_remove_mc_mac_addr(hw, addr);
529 ret = hns3vf_add_mc_mac_addr(hw, addr);
532 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
534 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
535 del ? "Remove" : "Restore", mac_str, ret);
542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
543 bool en_uc_pmc, bool en_mc_pmc)
545 struct hns3_mbx_vf_to_pf_cmd *req;
546 struct hns3_cmd_desc desc;
549 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
552 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
553 * so there are some features for promiscuous/allmulticast mode in hns3
554 * VF PMD driver as below:
555 * 1. The promiscuous/allmulticast mode can be configured successfully
556 * only based on the trusted VF device. If based on the non trusted
557 * VF device, configuring promiscuous/allmulticast mode will fail.
558 * The hns3 VF device can be confiruged as trusted device by hns3 PF
559 * kernel ethdev driver on the host by the following command:
560 * "ip link set <eth num> vf <vf id> turst on"
561 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
562 * driver can receive the ingress and outgoing traffic. In the words,
563 * all the ingress packets, all the packets sent from the PF and
564 * other VFs on the same physical port.
565 * 3. Note: Because of the hardware constraints, By default vlan filter
566 * is enabled and couldn't be turned off based on VF device, so vlan
567 * filter is still effective even in promiscuous mode. If upper
568 * applications don't call rte_eth_dev_vlan_filter API function to
569 * set vlan based on VF device, hns3 VF PMD driver will can't receive
570 * the packets with vlan tag in promiscuoue mode.
572 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
573 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
574 req->msg[1] = en_bc_pmc ? 1 : 0;
575 req->msg[2] = en_uc_pmc ? 1 : 0;
576 req->msg[3] = en_mc_pmc ? 1 : 0;
578 ret = hns3_cmd_send(hw, &desc, 1);
580 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
588 struct hns3_adapter *hns = dev->data->dev_private;
589 struct hns3_hw *hw = &hns->hw;
592 ret = hns3vf_set_promisc_mode(hw, true, true, true);
594 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
602 bool allmulti = dev->data->all_multicast ? true : false;
603 struct hns3_adapter *hns = dev->data->dev_private;
604 struct hns3_hw *hw = &hns->hw;
607 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
609 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
617 struct hns3_adapter *hns = dev->data->dev_private;
618 struct hns3_hw *hw = &hns->hw;
621 if (dev->data->promiscuous)
624 ret = hns3vf_set_promisc_mode(hw, true, false, true);
626 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
634 struct hns3_adapter *hns = dev->data->dev_private;
635 struct hns3_hw *hw = &hns->hw;
638 if (dev->data->promiscuous)
641 ret = hns3vf_set_promisc_mode(hw, true, false, false);
643 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
649 hns3vf_restore_promisc(struct hns3_adapter *hns)
651 struct hns3_hw *hw = &hns->hw;
652 bool allmulti = hw->data->all_multicast ? true : false;
654 if (hw->data->promiscuous)
655 return hns3vf_set_promisc_mode(hw, true, true, true);
657 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
662 bool mmap, enum hns3_ring_type queue_type,
665 struct hns3_vf_bind_vector_msg bind_msg;
670 memset(&bind_msg, 0, sizeof(bind_msg));
671 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
672 HNS3_MBX_UNMAP_RING_TO_VECTOR;
673 bind_msg.vector_id = vector_id;
675 if (queue_type == HNS3_RING_TYPE_RX)
676 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
678 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
680 bind_msg.param[0].ring_type = queue_type;
681 bind_msg.ring_num = 1;
682 bind_msg.param[0].tqp_index = queue_id;
683 op_str = mmap ? "Map" : "Unmap";
684 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
685 sizeof(bind_msg), false, NULL, 0);
687 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
688 op_str, queue_id, bind_msg.vector_id, ret);
694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
701 * In hns3 network engine, vector 0 is always the misc interrupt of this
702 * function, vector 1~N can be used respectively for the queues of the
703 * function. Tx and Rx queues with the same number share the interrupt
704 * vector. In the initialization clearing the all hardware mapping
705 * relationship configurations between queues and interrupt vectors is
706 * needed, so some error caused by the residual configurations, such as
707 * the unexpected Tx interrupt, can be avoid. Because of the hardware
708 * constraints in hns3 hardware engine, we have to implement clearing
709 * the mapping relationship configurations by binding all queues to the
710 * last interrupt vector and reserving the last interrupt vector. This
711 * method results in a decrease of the maximum queues when upper
712 * applications call the rte_eth_dev_configure API function to enable
715 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
716 hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
717 for (i = 0; i < hw->intr_tqps_num; i++) {
719 * Set gap limiter and rate limiter configuration of queue's
722 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
723 HNS3_TQP_INTR_GL_DEFAULT);
724 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
725 HNS3_TQP_INTR_GL_DEFAULT);
726 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
728 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
729 HNS3_RING_TYPE_TX, i);
731 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
732 "vector: %d, ret=%d", i, vec, ret);
736 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
737 HNS3_RING_TYPE_RX, i);
739 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
740 "vector: %d, ret=%d", i, vec, ret);
749 hns3vf_dev_configure(struct rte_eth_dev *dev)
751 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
752 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
753 struct rte_eth_conf *conf = &dev->data->dev_conf;
754 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
755 uint16_t nb_rx_q = dev->data->nb_rx_queues;
756 uint16_t nb_tx_q = dev->data->nb_tx_queues;
757 struct rte_eth_rss_conf rss_conf;
762 * Hardware does not support individually enable/disable/reset the Tx or
763 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
764 * and Rx queues at the same time. When the numbers of Tx queues
765 * allocated by upper applications are not equal to the numbers of Rx
766 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
767 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
768 * these fake queues are imperceptible, and can not be used by upper
771 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
773 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
777 hw->adapter_state = HNS3_NIC_CONFIGURING;
778 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
779 hns3_err(hw, "setting link speed/duplex not supported");
784 /* When RSS is not configured, redirect the packet queue 0 */
785 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
786 rss_conf = conf->rx_adv_conf.rss_conf;
787 if (rss_conf.rss_key == NULL) {
788 rss_conf.rss_key = rss_cfg->key;
789 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
792 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
798 * If jumbo frames are enabled, MTU needs to be refreshed
799 * according to the maximum RX packet length.
801 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
803 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
804 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
805 * can safely assign to "uint16_t" type variable.
807 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
808 ret = hns3vf_dev_mtu_set(dev, mtu);
811 dev->data->mtu = mtu;
814 ret = hns3vf_dev_configure_vlan(dev);
818 hw->adapter_state = HNS3_NIC_CONFIGURED;
822 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
823 hw->adapter_state = HNS3_NIC_INITIALIZED;
829 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
833 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
834 sizeof(mtu), true, NULL, 0);
836 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
842 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
844 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
845 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
849 * The hns3 PF/VF devices on the same port share the hardware MTU
850 * configuration. Currently, we send mailbox to inform hns3 PF kernel
851 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
852 * driver, there is no need to stop the port for hns3 VF device, and the
853 * MTU value issued by hns3 VF PMD driver must be less than or equal to
856 if (rte_atomic16_read(&hw->reset.resetting)) {
857 hns3_err(hw, "Failed to set mtu during resetting");
861 rte_spinlock_lock(&hw->lock);
862 ret = hns3vf_config_mtu(hw, mtu);
864 rte_spinlock_unlock(&hw->lock);
867 if (frame_size > RTE_ETHER_MAX_LEN)
868 dev->data->dev_conf.rxmode.offloads |=
869 DEV_RX_OFFLOAD_JUMBO_FRAME;
871 dev->data->dev_conf.rxmode.offloads &=
872 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
873 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
874 rte_spinlock_unlock(&hw->lock);
880 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
882 struct hns3_adapter *hns = eth_dev->data->dev_private;
883 struct hns3_hw *hw = &hns->hw;
884 uint16_t q_num = hw->tqps_num;
887 * In interrupt mode, 'max_rx_queues' is set based on the number of
888 * MSI-X interrupt resources of the hardware.
890 if (hw->data->dev_conf.intr_conf.rxq == 1)
891 q_num = hw->intr_tqps_num;
893 info->max_rx_queues = q_num;
894 info->max_tx_queues = hw->tqps_num;
895 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
896 info->min_rx_bufsize = hw->rx_buf_len;
897 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
898 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
900 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
901 DEV_RX_OFFLOAD_UDP_CKSUM |
902 DEV_RX_OFFLOAD_TCP_CKSUM |
903 DEV_RX_OFFLOAD_SCTP_CKSUM |
904 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
905 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
906 DEV_RX_OFFLOAD_KEEP_CRC |
907 DEV_RX_OFFLOAD_SCATTER |
908 DEV_RX_OFFLOAD_VLAN_STRIP |
909 DEV_RX_OFFLOAD_QINQ_STRIP |
910 DEV_RX_OFFLOAD_VLAN_FILTER |
911 DEV_RX_OFFLOAD_JUMBO_FRAME |
912 DEV_RX_OFFLOAD_RSS_HASH);
913 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
914 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
915 DEV_TX_OFFLOAD_IPV4_CKSUM |
916 DEV_TX_OFFLOAD_TCP_CKSUM |
917 DEV_TX_OFFLOAD_UDP_CKSUM |
918 DEV_TX_OFFLOAD_SCTP_CKSUM |
919 DEV_TX_OFFLOAD_VLAN_INSERT |
920 DEV_TX_OFFLOAD_QINQ_INSERT |
921 DEV_TX_OFFLOAD_MULTI_SEGS |
922 DEV_TX_OFFLOAD_TCP_TSO |
923 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
924 DEV_TX_OFFLOAD_GRE_TNL_TSO |
925 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
926 info->tx_queue_offload_capa);
928 info->rx_desc_lim = (struct rte_eth_desc_lim) {
929 .nb_max = HNS3_MAX_RING_DESC,
930 .nb_min = HNS3_MIN_RING_DESC,
931 .nb_align = HNS3_ALIGN_RING_DESC,
934 info->tx_desc_lim = (struct rte_eth_desc_lim) {
935 .nb_max = HNS3_MAX_RING_DESC,
936 .nb_min = HNS3_MIN_RING_DESC,
937 .nb_align = HNS3_ALIGN_RING_DESC,
940 info->vmdq_queue_num = 0;
942 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
943 info->hash_key_size = HNS3_RSS_KEY_SIZE;
944 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
945 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
946 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
952 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
954 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
958 hns3vf_disable_irq0(struct hns3_hw *hw)
960 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
964 hns3vf_enable_irq0(struct hns3_hw *hw)
966 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
969 static enum hns3vf_evt_cause
970 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
972 struct hns3_hw *hw = &hns->hw;
973 enum hns3vf_evt_cause ret;
974 uint32_t cmdq_stat_reg;
975 uint32_t rst_ing_reg;
978 /* Fetch the events from their corresponding regs */
979 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
981 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
982 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
983 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
984 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
985 rte_atomic16_set(&hw->reset.disable_cmd, 1);
986 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
987 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
988 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
990 hw->reset.stats.global_cnt++;
991 hns3_warn(hw, "Global reset detected, clear reset status");
993 hns3_schedule_delayed_reset(hns);
994 hns3_warn(hw, "Global reset detected, don't clear reset status");
997 ret = HNS3VF_VECTOR0_EVENT_RST;
1001 /* Check for vector0 mailbox(=CMDQ RX) event source */
1002 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1003 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1004 ret = HNS3VF_VECTOR0_EVENT_MBX;
1009 ret = HNS3VF_VECTOR0_EVENT_OTHER;
1017 hns3vf_interrupt_handler(void *param)
1019 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1020 struct hns3_adapter *hns = dev->data->dev_private;
1021 struct hns3_hw *hw = &hns->hw;
1022 enum hns3vf_evt_cause event_cause;
1025 if (hw->irq_thread_id == 0)
1026 hw->irq_thread_id = pthread_self();
1028 /* Disable interrupt */
1029 hns3vf_disable_irq0(hw);
1031 /* Read out interrupt causes */
1032 event_cause = hns3vf_check_event_cause(hns, &clearval);
1034 switch (event_cause) {
1035 case HNS3VF_VECTOR0_EVENT_RST:
1036 hns3_schedule_reset(hns);
1038 case HNS3VF_VECTOR0_EVENT_MBX:
1039 hns3_dev_handle_mbx_msg(hw);
1045 /* Clear interrupt causes */
1046 hns3vf_clear_event_cause(hw, clearval);
1048 /* Enable interrupt */
1049 hns3vf_enable_irq0(hw);
1053 hns3vf_check_tqp_info(struct hns3_hw *hw)
1057 tqps_num = hw->tqps_num;
1058 if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1059 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1061 tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1065 if (hw->rx_buf_len == 0)
1066 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
1067 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1073 hns3vf_get_queue_info(struct hns3_hw *hw)
1075 #define HNS3VF_TQPS_RSS_INFO_LEN 6
1076 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1079 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1080 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1082 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1086 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1087 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1088 memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
1090 return hns3vf_check_tqp_info(hw);
1094 hns3vf_get_queue_depth(struct hns3_hw *hw)
1096 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
1097 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1100 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1101 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1103 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1108 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1109 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1115 hns3vf_get_tc_info(struct hns3_hw *hw)
1120 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1121 true, &resp_msg, sizeof(resp_msg));
1123 hns3_err(hw, "VF request to get TC info from PF failed %d",
1128 hw->hw_tc_map = resp_msg;
1134 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1136 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1139 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1140 true, host_mac, RTE_ETHER_ADDR_LEN);
1142 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1146 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1152 hns3vf_get_configuration(struct hns3_hw *hw)
1156 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1157 hw->rss_dis_flag = false;
1159 /* Get queue configuration from PF */
1160 ret = hns3vf_get_queue_info(hw);
1164 /* Get queue depth info from PF */
1165 ret = hns3vf_get_queue_depth(hw);
1169 /* Get user defined VF MAC addr from PF */
1170 ret = hns3vf_get_host_mac_addr(hw);
1174 /* Get tc configuration from PF */
1175 return hns3vf_get_tc_info(hw);
1179 hns3vf_set_tc_info(struct hns3_adapter *hns)
1181 struct hns3_hw *hw = &hns->hw;
1182 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1183 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1187 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1188 if (hw->hw_tc_map & BIT(i))
1191 if (nb_rx_q < hw->num_tc) {
1192 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1193 nb_rx_q, hw->num_tc);
1197 if (nb_tx_q < hw->num_tc) {
1198 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1199 nb_tx_q, hw->num_tc);
1203 hns3_set_rss_size(hw, nb_rx_q);
1204 hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1210 hns3vf_request_link_info(struct hns3_hw *hw)
1215 if (rte_atomic16_read(&hw->reset.resetting))
1217 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1218 &resp_msg, sizeof(resp_msg));
1220 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1224 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1226 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1227 struct hns3_hw *hw = &hns->hw;
1228 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1229 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1230 uint8_t is_kill = on ? 0 : 1;
1232 msg_data[0] = is_kill;
1233 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1234 memcpy(&msg_data[3], &proto, sizeof(proto));
1236 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1237 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1242 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1244 struct hns3_adapter *hns = dev->data->dev_private;
1245 struct hns3_hw *hw = &hns->hw;
1248 if (rte_atomic16_read(&hw->reset.resetting)) {
1250 "vf set vlan id failed during resetting, vlan_id =%u",
1254 rte_spinlock_lock(&hw->lock);
1255 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1256 rte_spinlock_unlock(&hw->lock);
1258 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1265 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1270 msg_data = enable ? 1 : 0;
1271 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1272 &msg_data, sizeof(msg_data), false, NULL, 0);
1274 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1280 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1282 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1284 unsigned int tmp_mask;
1287 if (rte_atomic16_read(&hw->reset.resetting)) {
1288 hns3_err(hw, "vf set vlan offload failed during resetting, "
1289 "mask = 0x%x", mask);
1293 tmp_mask = (unsigned int)mask;
1294 /* Vlan stripping setting */
1295 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1296 rte_spinlock_lock(&hw->lock);
1297 /* Enable or disable VLAN stripping */
1298 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1299 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1301 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1302 rte_spinlock_unlock(&hw->lock);
1309 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1311 struct rte_vlan_filter_conf *vfc;
1312 struct hns3_hw *hw = &hns->hw;
1319 vfc = &hw->data->vlan_filter_conf;
1320 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1321 if (vfc->ids[i] == 0)
1326 * 64 means the num bits of ids, one bit corresponds to
1330 /* count trailing zeroes */
1331 vbit = ~ids & (ids - 1);
1332 /* clear least significant bit set */
1333 ids ^= (ids ^ (ids - 1)) ^ vbit;
1338 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1341 "VF handle vlan table failed, ret =%d, on = %d",
1352 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1354 return hns3vf_handle_all_vlan_table(hns, 0);
1358 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1360 struct hns3_hw *hw = &hns->hw;
1361 struct rte_eth_conf *dev_conf;
1365 dev_conf = &hw->data->dev_conf;
1366 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1368 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1370 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1376 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1378 struct hns3_adapter *hns = dev->data->dev_private;
1379 struct rte_eth_dev_data *data = dev->data;
1380 struct hns3_hw *hw = &hns->hw;
1383 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1384 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1385 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1386 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1387 "or hw_vlan_insert_pvid is not support!");
1390 /* Apply vlan offload setting */
1391 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1393 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1399 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1403 msg_data = alive ? 1 : 0;
1404 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1405 sizeof(msg_data), false, NULL, 0);
1409 hns3vf_keep_alive_handler(void *param)
1411 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1412 struct hns3_adapter *hns = eth_dev->data->dev_private;
1413 struct hns3_hw *hw = &hns->hw;
1417 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1418 false, &respmsg, sizeof(uint8_t));
1420 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1423 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1428 hns3vf_service_handler(void *param)
1430 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1431 struct hns3_adapter *hns = eth_dev->data->dev_private;
1432 struct hns3_hw *hw = &hns->hw;
1435 * The query link status and reset processing are executed in the
1436 * interrupt thread.When the IMP reset occurs, IMP will not respond,
1437 * and the query operation will time out after 30ms. In the case of
1438 * multiple PF/VFs, each query failure timeout causes the IMP reset
1439 * interrupt to fail to respond within 100ms.
1440 * Before querying the link status, check whether there is a reset
1441 * pending, and if so, abandon the query.
1443 if (!hns3vf_is_reset_pending(hns))
1444 hns3vf_request_link_info(hw);
1446 hns3_warn(hw, "Cancel the query when reset is pending");
1448 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1453 hns3_query_vf_resource(struct hns3_hw *hw)
1455 struct hns3_vf_res_cmd *req;
1456 struct hns3_cmd_desc desc;
1460 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1461 ret = hns3_cmd_send(hw, &desc, 1);
1463 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1467 req = (struct hns3_vf_res_cmd *)desc.data;
1468 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1469 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1470 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1471 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1472 num_msi, HNS3_MIN_VECTOR_NUM);
1476 hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
1482 hns3vf_init_hardware(struct hns3_adapter *hns)
1484 struct hns3_hw *hw = &hns->hw;
1485 uint16_t mtu = hw->data->mtu;
1488 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1492 ret = hns3vf_config_mtu(hw, mtu);
1494 goto err_init_hardware;
1496 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1498 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1499 goto err_init_hardware;
1502 ret = hns3_config_gro(hw, false);
1504 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1505 goto err_init_hardware;
1509 * In the initialization clearing the all hardware mapping relationship
1510 * configurations between queues and interrupt vectors is needed, so
1511 * some error caused by the residual configurations, such as the
1512 * unexpected interrupt, can be avoid.
1514 ret = hns3vf_init_ring_with_vector(hw);
1516 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1517 goto err_init_hardware;
1520 ret = hns3vf_set_alive(hw, true);
1522 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1523 goto err_init_hardware;
1526 hns3vf_request_link_info(hw);
1530 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1535 hns3vf_clear_vport_list(struct hns3_hw *hw)
1537 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1538 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1543 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1545 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1546 struct hns3_adapter *hns = eth_dev->data->dev_private;
1547 struct hns3_hw *hw = &hns->hw;
1550 PMD_INIT_FUNC_TRACE();
1552 /* Get hardware io base address from pcie BAR2 IO space */
1553 hw->io_base = pci_dev->mem_resource[2].addr;
1555 /* Firmware command queue initialize */
1556 ret = hns3_cmd_init_queue(hw);
1558 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1559 goto err_cmd_init_queue;
1562 /* Firmware command initialize */
1563 ret = hns3_cmd_init(hw);
1565 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1569 /* Get VF resource */
1570 ret = hns3_query_vf_resource(hw);
1574 rte_spinlock_init(&hw->mbx_resp.lock);
1576 hns3vf_clear_event_cause(hw, 0);
1578 ret = rte_intr_callback_register(&pci_dev->intr_handle,
1579 hns3vf_interrupt_handler, eth_dev);
1581 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1582 goto err_intr_callback_register;
1585 /* Enable interrupt */
1586 rte_intr_enable(&pci_dev->intr_handle);
1587 hns3vf_enable_irq0(hw);
1589 /* Get configuration from PF */
1590 ret = hns3vf_get_configuration(hw);
1592 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1593 goto err_get_config;
1597 * The hns3 PF ethdev driver in kernel support setting VF MAC address
1598 * on the host by "ip link set ..." command. To avoid some incorrect
1599 * scenes, for example, hns3 VF PMD driver fails to receive and send
1600 * packets after user configure the MAC address by using the
1601 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1602 * address strategy as the hns3 kernel ethdev driver in the
1603 * initialization. If user configure a MAC address by the ip command
1604 * for VF device, then hns3 VF PMD driver will start with it, otherwise
1605 * start with a random MAC address in the initialization.
1607 ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1609 rte_eth_random_addr(hw->mac.mac_addr);
1611 ret = hns3vf_clear_vport_list(hw);
1613 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1614 goto err_get_config;
1617 ret = hns3vf_init_hardware(hns);
1619 goto err_get_config;
1621 hns3_set_default_rss_args(hw);
1626 hns3vf_disable_irq0(hw);
1627 rte_intr_disable(&pci_dev->intr_handle);
1628 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1630 err_intr_callback_register:
1632 hns3_cmd_uninit(hw);
1633 hns3_cmd_destroy_queue(hw);
1641 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1643 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1644 struct hns3_adapter *hns = eth_dev->data->dev_private;
1645 struct hns3_hw *hw = &hns->hw;
1647 PMD_INIT_FUNC_TRACE();
1649 hns3_rss_uninit(hns);
1650 (void)hns3vf_set_alive(hw, false);
1651 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1652 hns3vf_disable_irq0(hw);
1653 rte_intr_disable(&pci_dev->intr_handle);
1654 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1656 hns3_cmd_uninit(hw);
1657 hns3_cmd_destroy_queue(hw);
1662 hns3vf_do_stop(struct hns3_adapter *hns)
1664 struct hns3_hw *hw = &hns->hw;
1667 hw->mac.link_status = ETH_LINK_DOWN;
1669 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1670 hns3vf_configure_mac_addr(hns, true);
1673 reset_queue = false;
1674 return hns3_stop_queues(hns, reset_queue);
1678 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1680 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1682 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1683 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1684 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1687 if (dev->data->dev_conf.intr_conf.rxq == 0)
1690 /* unmap the ring with vector */
1691 if (rte_intr_allow_others(intr_handle)) {
1692 vec = RTE_INTR_VEC_RXTX_OFFSET;
1693 base = RTE_INTR_VEC_RXTX_OFFSET;
1695 if (rte_intr_dp_is_en(intr_handle)) {
1696 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1697 (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1700 if (vec < base + intr_handle->nb_efd - 1)
1704 /* Clean datapath event and queue/vec mapping */
1705 rte_intr_efd_disable(intr_handle);
1706 if (intr_handle->intr_vec) {
1707 rte_free(intr_handle->intr_vec);
1708 intr_handle->intr_vec = NULL;
1713 hns3vf_dev_stop(struct rte_eth_dev *dev)
1715 struct hns3_adapter *hns = dev->data->dev_private;
1716 struct hns3_hw *hw = &hns->hw;
1718 PMD_INIT_FUNC_TRACE();
1720 hw->adapter_state = HNS3_NIC_STOPPING;
1721 hns3_set_rxtx_function(dev);
1723 /* Disable datapath on secondary process. */
1724 hns3_mp_req_stop_rxtx(dev);
1725 /* Prevent crashes when queues are still in use. */
1726 rte_delay_ms(hw->tqps_num);
1728 rte_spinlock_lock(&hw->lock);
1729 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1730 hns3vf_do_stop(hns);
1731 hns3vf_unmap_rx_interrupt(dev);
1732 hns3_dev_release_mbufs(hns);
1733 hw->adapter_state = HNS3_NIC_CONFIGURED;
1735 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1736 rte_spinlock_unlock(&hw->lock);
1740 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1742 struct hns3_adapter *hns = eth_dev->data->dev_private;
1743 struct hns3_hw *hw = &hns->hw;
1745 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1748 if (hw->adapter_state == HNS3_NIC_STARTED)
1749 hns3vf_dev_stop(eth_dev);
1751 hw->adapter_state = HNS3_NIC_CLOSING;
1752 hns3_reset_abort(hns);
1753 hw->adapter_state = HNS3_NIC_CLOSED;
1754 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1755 hns3vf_configure_all_mc_mac_addr(hns, true);
1756 hns3vf_remove_all_vlan_table(hns);
1757 hns3vf_uninit_vf(eth_dev);
1758 hns3_free_all_queues(eth_dev);
1759 rte_free(hw->reset.wait_data);
1760 rte_free(eth_dev->process_private);
1761 eth_dev->process_private = NULL;
1762 hns3_mp_uninit_primary();
1763 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1767 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1768 __rte_unused int wait_to_complete)
1770 struct hns3_adapter *hns = eth_dev->data->dev_private;
1771 struct hns3_hw *hw = &hns->hw;
1772 struct hns3_mac *mac = &hw->mac;
1773 struct rte_eth_link new_link;
1775 memset(&new_link, 0, sizeof(new_link));
1776 switch (mac->link_speed) {
1777 case ETH_SPEED_NUM_10M:
1778 case ETH_SPEED_NUM_100M:
1779 case ETH_SPEED_NUM_1G:
1780 case ETH_SPEED_NUM_10G:
1781 case ETH_SPEED_NUM_25G:
1782 case ETH_SPEED_NUM_40G:
1783 case ETH_SPEED_NUM_50G:
1784 case ETH_SPEED_NUM_100G:
1785 new_link.link_speed = mac->link_speed;
1788 new_link.link_speed = ETH_SPEED_NUM_100M;
1792 new_link.link_duplex = mac->link_duplex;
1793 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1794 new_link.link_autoneg =
1795 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1797 return rte_eth_linkstatus_set(eth_dev, &new_link);
1801 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1803 struct hns3_hw *hw = &hns->hw;
1806 ret = hns3vf_set_tc_info(hns);
1810 ret = hns3_start_queues(hns, reset_queue);
1812 hns3_err(hw, "Failed to start queues: %d", ret);
1818 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1820 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1821 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1822 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1824 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1825 uint32_t intr_vector;
1829 if (dev->data->dev_conf.intr_conf.rxq == 0)
1832 /* disable uio/vfio intr/eventfd mapping */
1833 rte_intr_disable(intr_handle);
1835 /* check and configure queue intr-vector mapping */
1836 if (rte_intr_cap_multiple(intr_handle) ||
1837 !RTE_ETH_DEV_SRIOV(dev).active) {
1838 intr_vector = hw->used_rx_queues;
1839 /* It creates event fd for each intr vector when MSIX is used */
1840 if (rte_intr_efd_enable(intr_handle, intr_vector))
1843 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1844 intr_handle->intr_vec =
1845 rte_zmalloc("intr_vec",
1846 hw->used_rx_queues * sizeof(int), 0);
1847 if (intr_handle->intr_vec == NULL) {
1848 hns3_err(hw, "Failed to allocate %d rx_queues"
1849 " intr_vec", hw->used_rx_queues);
1851 goto vf_alloc_intr_vec_error;
1855 if (rte_intr_allow_others(intr_handle)) {
1856 vec = RTE_INTR_VEC_RXTX_OFFSET;
1857 base = RTE_INTR_VEC_RXTX_OFFSET;
1859 if (rte_intr_dp_is_en(intr_handle)) {
1860 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1861 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1865 goto vf_bind_vector_error;
1866 intr_handle->intr_vec[q_id] = vec;
1867 if (vec < base + intr_handle->nb_efd - 1)
1871 rte_intr_enable(intr_handle);
1874 vf_bind_vector_error:
1875 rte_intr_efd_disable(intr_handle);
1876 if (intr_handle->intr_vec) {
1877 free(intr_handle->intr_vec);
1878 intr_handle->intr_vec = NULL;
1881 vf_alloc_intr_vec_error:
1882 rte_intr_efd_disable(intr_handle);
1887 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
1889 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1890 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1891 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1895 if (dev->data->dev_conf.intr_conf.rxq == 0)
1898 if (rte_intr_dp_is_en(intr_handle)) {
1899 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1900 ret = hns3vf_bind_ring_with_vector(hw,
1901 intr_handle->intr_vec[q_id], true,
1902 HNS3_RING_TYPE_RX, q_id);
1912 hns3vf_restore_filter(struct rte_eth_dev *dev)
1914 hns3_restore_rss_filter(dev);
1918 hns3vf_dev_start(struct rte_eth_dev *dev)
1920 struct hns3_adapter *hns = dev->data->dev_private;
1921 struct hns3_hw *hw = &hns->hw;
1924 PMD_INIT_FUNC_TRACE();
1925 if (rte_atomic16_read(&hw->reset.resetting))
1928 rte_spinlock_lock(&hw->lock);
1929 hw->adapter_state = HNS3_NIC_STARTING;
1930 ret = hns3vf_do_start(hns, true);
1932 hw->adapter_state = HNS3_NIC_CONFIGURED;
1933 rte_spinlock_unlock(&hw->lock);
1936 ret = hns3vf_map_rx_interrupt(dev);
1938 hw->adapter_state = HNS3_NIC_CONFIGURED;
1939 rte_spinlock_unlock(&hw->lock);
1942 hw->adapter_state = HNS3_NIC_STARTED;
1943 rte_spinlock_unlock(&hw->lock);
1945 hns3_set_rxtx_function(dev);
1946 hns3_mp_req_start_rxtx(dev);
1947 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
1949 hns3vf_restore_filter(dev);
1951 /* Enable interrupt of all rx queues before enabling queues */
1952 hns3_dev_all_rx_queue_intr_enable(hw, true);
1954 * When finished the initialization, enable queues to receive/transmit
1957 hns3_enable_all_queues(hw, true);
1963 is_vf_reset_done(struct hns3_hw *hw)
1965 #define HNS3_FUN_RST_ING_BITS \
1966 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1967 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1968 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1969 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1973 if (hw->reset.level == HNS3_VF_RESET) {
1974 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1975 if (val & HNS3_VF_RST_ING_BIT)
1978 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1979 if (val & HNS3_FUN_RST_ING_BITS)
1986 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1988 struct hns3_hw *hw = &hns->hw;
1989 enum hns3_reset_level reset;
1991 hns3vf_check_event_cause(hns, NULL);
1992 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1993 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
1994 hns3_warn(hw, "High level reset %d is pending", reset);
2001 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2003 struct hns3_hw *hw = &hns->hw;
2004 struct hns3_wait_data *wait_data = hw->reset.wait_data;
2007 if (wait_data->result == HNS3_WAIT_SUCCESS) {
2009 * After vf reset is ready, the PF may not have completed
2010 * the reset processing. The vf sending mbox to PF may fail
2011 * during the pf reset, so it is better to add extra delay.
2013 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2014 hw->reset.level == HNS3_FLR_RESET)
2016 /* Reset retry process, no need to add extra delay. */
2017 if (hw->reset.attempts)
2019 if (wait_data->check_completion == NULL)
2022 wait_data->check_completion = NULL;
2023 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2024 wait_data->count = 1;
2025 wait_data->result = HNS3_WAIT_REQUEST;
2026 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2028 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2030 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2031 gettimeofday(&tv, NULL);
2032 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2033 tv.tv_sec, tv.tv_usec);
2035 } else if (wait_data->result == HNS3_WAIT_REQUEST)
2038 wait_data->hns = hns;
2039 wait_data->check_completion = is_vf_reset_done;
2040 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2041 HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2042 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2043 wait_data->count = HNS3VF_RESET_WAIT_CNT;
2044 wait_data->result = HNS3_WAIT_REQUEST;
2045 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2050 hns3vf_prepare_reset(struct hns3_adapter *hns)
2052 struct hns3_hw *hw = &hns->hw;
2055 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2056 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2059 rte_atomic16_set(&hw->reset.disable_cmd, 1);
2065 hns3vf_stop_service(struct hns3_adapter *hns)
2067 struct hns3_hw *hw = &hns->hw;
2068 struct rte_eth_dev *eth_dev;
2070 eth_dev = &rte_eth_devices[hw->data->port_id];
2071 if (hw->adapter_state == HNS3_NIC_STARTED)
2072 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2073 hw->mac.link_status = ETH_LINK_DOWN;
2075 hns3_set_rxtx_function(eth_dev);
2077 /* Disable datapath on secondary process. */
2078 hns3_mp_req_stop_rxtx(eth_dev);
2079 rte_delay_ms(hw->tqps_num);
2081 rte_spinlock_lock(&hw->lock);
2082 if (hw->adapter_state == HNS3_NIC_STARTED ||
2083 hw->adapter_state == HNS3_NIC_STOPPING) {
2084 hns3vf_do_stop(hns);
2085 hw->reset.mbuf_deferred_free = true;
2087 hw->reset.mbuf_deferred_free = false;
2090 * It is cumbersome for hardware to pick-and-choose entries for deletion
2091 * from table space. Hence, for function reset software intervention is
2092 * required to delete the entries.
2094 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2095 hns3vf_configure_all_mc_mac_addr(hns, true);
2096 rte_spinlock_unlock(&hw->lock);
2102 hns3vf_start_service(struct hns3_adapter *hns)
2104 struct hns3_hw *hw = &hns->hw;
2105 struct rte_eth_dev *eth_dev;
2107 eth_dev = &rte_eth_devices[hw->data->port_id];
2108 hns3_set_rxtx_function(eth_dev);
2109 hns3_mp_req_start_rxtx(eth_dev);
2110 if (hw->adapter_state == HNS3_NIC_STARTED) {
2111 hns3vf_service_handler(eth_dev);
2113 /* Enable interrupt of all rx queues before enabling queues */
2114 hns3_dev_all_rx_queue_intr_enable(hw, true);
2116 * When finished the initialization, enable queues to receive
2117 * and transmit packets.
2119 hns3_enable_all_queues(hw, true);
2126 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2128 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2129 struct rte_ether_addr *hw_mac;
2133 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2134 * on the host by "ip link set ..." command. If the hns3 PF kernel
2135 * ethdev driver sets the MAC address for VF device after the
2136 * initialization of the related VF device, the PF driver will notify
2137 * VF driver to reset VF device to make the new MAC address effective
2138 * immediately. The hns3 VF PMD driver should check whether the MAC
2139 * address has been changed by the PF kernel ethdev driver, if changed
2140 * VF driver should configure hardware using the new MAC address in the
2141 * recovering hardware configuration stage of the reset process.
2143 ret = hns3vf_get_host_mac_addr(hw);
2147 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2148 ret = rte_is_zero_ether_addr(hw_mac);
2150 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2152 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2154 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2155 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2156 &hw->data->mac_addrs[0]);
2157 hns3_warn(hw, "Default MAC address has been changed to:"
2158 " %s by the host PF kernel ethdev driver",
2167 hns3vf_restore_conf(struct hns3_adapter *hns)
2169 struct hns3_hw *hw = &hns->hw;
2172 ret = hns3vf_check_default_mac_change(hw);
2176 ret = hns3vf_configure_mac_addr(hns, false);
2180 ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2184 ret = hns3vf_restore_promisc(hns);
2186 goto err_vlan_table;
2188 ret = hns3vf_restore_vlan_conf(hns);
2190 goto err_vlan_table;
2192 ret = hns3vf_restore_rx_interrupt(hw);
2194 goto err_vlan_table;
2196 if (hw->adapter_state == HNS3_NIC_STARTED) {
2197 ret = hns3vf_do_start(hns, false);
2199 goto err_vlan_table;
2200 hns3_info(hw, "hns3vf dev restart successful!");
2201 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2202 hw->adapter_state = HNS3_NIC_CONFIGURED;
2206 hns3vf_configure_all_mc_mac_addr(hns, true);
2208 hns3vf_configure_mac_addr(hns, true);
2212 static enum hns3_reset_level
2213 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2215 enum hns3_reset_level reset_level;
2217 /* return the highest priority reset level amongst all */
2218 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2219 reset_level = HNS3_VF_RESET;
2220 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2221 reset_level = HNS3_VF_FULL_RESET;
2222 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2223 reset_level = HNS3_VF_PF_FUNC_RESET;
2224 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2225 reset_level = HNS3_VF_FUNC_RESET;
2226 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2227 reset_level = HNS3_FLR_RESET;
2229 reset_level = HNS3_NONE_RESET;
2231 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2232 return HNS3_NONE_RESET;
2238 hns3vf_reset_service(void *param)
2240 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2241 struct hns3_hw *hw = &hns->hw;
2242 enum hns3_reset_level reset_level;
2243 struct timeval tv_delta;
2244 struct timeval tv_start;
2249 * The interrupt is not triggered within the delay time.
2250 * The interrupt may have been lost. It is necessary to handle
2251 * the interrupt to recover from the error.
2253 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2254 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2255 hns3_err(hw, "Handling interrupts in delayed tasks");
2256 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2257 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2258 if (reset_level == HNS3_NONE_RESET) {
2259 hns3_err(hw, "No reset level is set, try global reset");
2260 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2263 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2266 * Hardware reset has been notified, we now have to poll & check if
2267 * hardware has actually completed the reset sequence.
2269 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2270 if (reset_level != HNS3_NONE_RESET) {
2271 gettimeofday(&tv_start, NULL);
2272 hns3_reset_process(hns, reset_level);
2273 gettimeofday(&tv, NULL);
2274 timersub(&tv, &tv_start, &tv_delta);
2275 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2276 tv_delta.tv_usec / USEC_PER_MSEC;
2277 if (msec > HNS3_RESET_PROCESS_MS)
2278 hns3_err(hw, "%d handle long time delta %" PRIx64
2279 " ms time=%ld.%.6ld",
2280 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2285 hns3vf_reinit_dev(struct hns3_adapter *hns)
2287 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2288 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2289 struct hns3_hw *hw = &hns->hw;
2292 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2293 rte_intr_disable(&pci_dev->intr_handle);
2294 hns3vf_set_bus_master(pci_dev, true);
2297 /* Firmware command initialize */
2298 ret = hns3_cmd_init(hw);
2300 hns3_err(hw, "Failed to init cmd: %d", ret);
2304 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2306 * UIO enables msix by writing the pcie configuration space
2307 * vfio_pci enables msix in rte_intr_enable.
2309 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2310 pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2311 if (hns3vf_enable_msix(pci_dev, true))
2312 hns3_err(hw, "Failed to enable msix");
2315 rte_intr_enable(&pci_dev->intr_handle);
2318 ret = hns3_reset_all_queues(hns);
2320 hns3_err(hw, "Failed to reset all queues: %d", ret);
2324 ret = hns3vf_init_hardware(hns);
2326 hns3_err(hw, "Failed to init hardware: %d", ret);
2333 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2334 .dev_start = hns3vf_dev_start,
2335 .dev_stop = hns3vf_dev_stop,
2336 .dev_close = hns3vf_dev_close,
2337 .mtu_set = hns3vf_dev_mtu_set,
2338 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2339 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2340 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2341 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2342 .stats_get = hns3_stats_get,
2343 .stats_reset = hns3_stats_reset,
2344 .xstats_get = hns3_dev_xstats_get,
2345 .xstats_get_names = hns3_dev_xstats_get_names,
2346 .xstats_reset = hns3_dev_xstats_reset,
2347 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2348 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2349 .dev_infos_get = hns3vf_dev_infos_get,
2350 .rx_queue_setup = hns3_rx_queue_setup,
2351 .tx_queue_setup = hns3_tx_queue_setup,
2352 .rx_queue_release = hns3_dev_rx_queue_release,
2353 .tx_queue_release = hns3_dev_tx_queue_release,
2354 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2355 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2356 .dev_configure = hns3vf_dev_configure,
2357 .mac_addr_add = hns3vf_add_mac_addr,
2358 .mac_addr_remove = hns3vf_remove_mac_addr,
2359 .mac_addr_set = hns3vf_set_default_mac_addr,
2360 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list,
2361 .link_update = hns3vf_dev_link_update,
2362 .rss_hash_update = hns3_dev_rss_hash_update,
2363 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2364 .reta_update = hns3_dev_rss_reta_update,
2365 .reta_query = hns3_dev_rss_reta_query,
2366 .filter_ctrl = hns3_dev_filter_ctrl,
2367 .vlan_filter_set = hns3vf_vlan_filter_set,
2368 .vlan_offload_set = hns3vf_vlan_offload_set,
2369 .get_reg = hns3_get_regs,
2370 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2373 static const struct hns3_reset_ops hns3vf_reset_ops = {
2374 .reset_service = hns3vf_reset_service,
2375 .stop_service = hns3vf_stop_service,
2376 .prepare_reset = hns3vf_prepare_reset,
2377 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2378 .reinit_dev = hns3vf_reinit_dev,
2379 .restore_conf = hns3vf_restore_conf,
2380 .start_service = hns3vf_start_service,
2384 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2386 struct hns3_adapter *hns = eth_dev->data->dev_private;
2387 struct hns3_hw *hw = &hns->hw;
2390 PMD_INIT_FUNC_TRACE();
2392 eth_dev->process_private = (struct hns3_process_private *)
2393 rte_zmalloc_socket("hns3_filter_list",
2394 sizeof(struct hns3_process_private),
2395 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2396 if (eth_dev->process_private == NULL) {
2397 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2401 /* initialize flow filter lists */
2402 hns3_filterlist_init(eth_dev);
2404 hns3_set_rxtx_function(eth_dev);
2405 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2406 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2407 hns3_mp_init_secondary();
2408 hw->secondary_cnt++;
2412 hns3_mp_init_primary();
2414 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2416 hw->data = eth_dev->data;
2418 ret = hns3_reset_init(hw);
2420 goto err_init_reset;
2421 hw->reset.ops = &hns3vf_reset_ops;
2423 ret = hns3vf_init_vf(eth_dev);
2425 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2429 /* Allocate memory for storing MAC addresses */
2430 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2431 sizeof(struct rte_ether_addr) *
2432 HNS3_VF_UC_MACADDR_NUM, 0);
2433 if (eth_dev->data->mac_addrs == NULL) {
2434 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2435 "to store MAC addresses",
2436 sizeof(struct rte_ether_addr) *
2437 HNS3_VF_UC_MACADDR_NUM);
2439 goto err_rte_zmalloc;
2442 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2443 ð_dev->data->mac_addrs[0]);
2444 hw->adapter_state = HNS3_NIC_INITIALIZED;
2446 * Pass the information to the rte_eth_dev_close() that it should also
2447 * release the private port resources.
2449 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2451 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2452 hns3_err(hw, "Reschedule reset service after dev_init");
2453 hns3_schedule_reset(hns);
2455 /* IMP will wait ready flag before reset */
2456 hns3_notify_reset_ready(hw, false);
2458 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2463 hns3vf_uninit_vf(eth_dev);
2466 rte_free(hw->reset.wait_data);
2469 eth_dev->dev_ops = NULL;
2470 eth_dev->rx_pkt_burst = NULL;
2471 eth_dev->tx_pkt_burst = NULL;
2472 eth_dev->tx_pkt_prepare = NULL;
2473 rte_free(eth_dev->process_private);
2474 eth_dev->process_private = NULL;
2480 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2482 struct hns3_adapter *hns = eth_dev->data->dev_private;
2483 struct hns3_hw *hw = &hns->hw;
2485 PMD_INIT_FUNC_TRACE();
2487 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2490 eth_dev->dev_ops = NULL;
2491 eth_dev->rx_pkt_burst = NULL;
2492 eth_dev->tx_pkt_burst = NULL;
2493 eth_dev->tx_pkt_prepare = NULL;
2495 if (hw->adapter_state < HNS3_NIC_CLOSING)
2496 hns3vf_dev_close(eth_dev);
2498 hw->adapter_state = HNS3_NIC_REMOVED;
2503 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2504 struct rte_pci_device *pci_dev)
2506 return rte_eth_dev_pci_generic_probe(pci_dev,
2507 sizeof(struct hns3_adapter),
2512 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2514 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2517 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2518 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2519 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2520 { .vendor_id = 0, /* sentinel */ },
2523 static struct rte_pci_driver rte_hns3vf_pmd = {
2524 .id_table = pci_id_hns3vf_map,
2525 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2526 .probe = eth_hns3vf_pci_probe,
2527 .remove = eth_hns3vf_pci_remove,
2530 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2531 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2532 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");