drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 /* set PCI bus mastering */
  63 static void
  64 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  65 {
  66         uint16_t reg;
  67
  68         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  69
  70         if (op)
  71                 /* set the master bit */
  72                 reg |= PCI_COMMAND_MASTER;
  73         else
  74                 reg &= ~(PCI_COMMAND_MASTER);
  75
  76         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  77 }
  78
  79 /**
  80  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  81  * @cap: the capability
  82  *
  83  * Return the address of the given capability within the PCI capability list.
  84  */
  85 static int
  86 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  87 {
  88 #define MAX_PCIE_CAPABILITY 48
  89         uint16_t status;
  90         uint8_t pos;
  91         uint8_t id;
  92         int ttl;
  93
  94         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 100         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 101                 rte_pci_read_config(device, &id, sizeof(id),
 102                                     (pos + PCI_CAP_LIST_ID));
 103
 104                 if (id == 0xFF)
 105                         break;
 106
 107                 if (id == cap)
 108                         return (int)pos;
 109
 110                 rte_pci_read_config(device, &pos, sizeof(pos),
 111                                     (pos + PCI_CAP_LIST_NEXT));
 112         }
 113         return 0;
 114 }
 115
 116 static int
 117 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 118 {
 119         uint16_t control;
 120         int pos;
 121
 122         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 123         if (pos) {
 124                 rte_pci_read_config(device, &control, sizeof(control),
 125                                     (pos + PCI_MSIX_FLAGS));
 126                 if (op)
 127                         control |= PCI_MSIX_FLAGS_ENABLE;
 128                 else
 129                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 130                 rte_pci_write_config(device, &control, sizeof(control),
 131                                      (pos + PCI_MSIX_FLAGS));
 132                 return 0;
 133         }
 134         return -ENXIO;
 135 }
 136
 137 static int
 138 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 139                     __rte_unused uint32_t idx,
 140                     __rte_unused uint32_t pool)
 141 {
 142         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 143         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 144         int ret;
 145
 146         rte_spinlock_lock(&hw->lock);
 147         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 148                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 149                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 150         rte_spinlock_unlock(&hw->lock);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "Failed to add mac addr(%s) for vf: %d", mac_str,
 155                          ret);
 156         }
 157
 158         return ret;
 159 }
 160
 161 static void
 162 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 163 {
 164         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 165         /* index will be checked by upper level rte interface */
 166         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 167         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 168         int ret;
 169
 170         rte_spinlock_lock(&hw->lock);
 171         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 172                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 173                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 174                                 NULL, 0);
 175         rte_spinlock_unlock(&hw->lock);
 176         if (ret) {
 177                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 178                                       mac_addr);
 179                 hns3_err(hw, "Failed to remove mac addr(%s) for vf: %d",
 180                          mac_str, ret);
 181         }
 182 }
 183
 184 static int
 185 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 186                             struct rte_ether_addr *mac_addr)
 187 {
 188 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 189         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 190         struct rte_ether_addr *old_addr;
 191         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 192         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 193         int ret;
 194
 195         /*
 196          * It has been guaranteed that input parameter named mac_addr is valid
 197          * address in the rte layer of DPDK framework.
 198          */
 199         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 200         rte_spinlock_lock(&hw->lock);
 201         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 202         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 203                RTE_ETHER_ADDR_LEN);
 204
 205         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 206                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 207                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 208         if (ret) {
 209                 /*
 210                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 211                  * driver. When user has configured a MAC address for VF device
 212                  * by "ip link set ..." command based on the PF device, the hns3
 213                  * PF kernel ethdev driver does not allow VF driver to request
 214                  * reconfiguring a different default MAC address, and return
 215                  * -EPREM to VF driver through mailbox.
 216                  */
 217                 if (ret == -EPERM) {
 218                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 219                                               old_addr);
 220                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 221                                   mac_str);
 222                 } else {
 223                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 224                                               mac_addr);
 225                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 226                                  mac_str, ret);
 227                 }
 228         }
 229
 230         rte_ether_addr_copy(mac_addr,
 231                             (struct rte_ether_addr *)hw->mac.mac_addr);
 232         rte_spinlock_unlock(&hw->lock);
 233
 234         return ret;
 235 }
 236
 237 static int
 238 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 239 {
 240         struct hns3_hw *hw = &hns->hw;
 241         struct rte_ether_addr *addr;
 242         enum hns3_mbx_mac_vlan_subcode opcode;
 243         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 244         int ret = 0;
 245         int i;
 246
 247         if (del)
 248                 opcode = HNS3_MBX_MAC_VLAN_UC_REMOVE;
 249         else
 250                 opcode = HNS3_MBX_MAC_VLAN_UC_ADD;
 251         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 252                 addr = &hw->data->mac_addrs[i];
 253                 if (!rte_is_valid_assigned_ether_addr(addr))
 254                         continue;
 255                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 256                 hns3_dbg(hw, "rm mac addr: %s", mac_str);
 257                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, opcode,
 258                                         addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 259                                         false, NULL, 0);
 260                 if (ret) {
 261                         hns3_err(hw, "Failed to remove mac addr for vf: %d",
 262                                  ret);
 263                         break;
 264                 }
 265         }
 266         return ret;
 267 }
 268
 269 static int
 270 hns3vf_add_mc_mac_addr(struct hns3_adapter *hns,
 271                        struct rte_ether_addr *mac_addr)
 272 {
 273         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 274         struct hns3_hw *hw = &hns->hw;
 275         int ret;
 276
 277         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 278                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 279                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 280                                 NULL, 0);
 281         if (ret) {
 282                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 283                                       mac_addr);
 284                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 285                          mac_str, ret);
 286                 return ret;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int
 293 hns3vf_remove_mc_mac_addr(struct hns3_adapter *hns,
 294                           struct rte_ether_addr *mac_addr)
 295 {
 296         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 297         struct hns3_hw *hw = &hns->hw;
 298         int ret;
 299
 300         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 301                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 302                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 303                                 NULL, 0);
 304         if (ret) {
 305                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 306                                       mac_addr);
 307                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 308                          mac_str, ret);
 309                 return ret;
 310         }
 311
 312         return 0;
 313 }
 314
 315 static int
 316 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 317                             struct rte_ether_addr *mc_addr_set,
 318                             uint32_t nb_mc_addr)
 319 {
 320         struct hns3_adapter *hns = dev->data->dev_private;
 321         struct hns3_hw *hw = &hns->hw;
 322         struct rte_ether_addr *addr;
 323         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 324         int cur_addr_num;
 325         int set_addr_num;
 326         int num;
 327         int ret;
 328         int i;
 329
 330         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 331                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 332                          "invalid. valid range: 0~%d",
 333                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 334                 return -EINVAL;
 335         }
 336
 337         set_addr_num = (int)nb_mc_addr;
 338         for (i = 0; i < set_addr_num; i++) {
 339                 addr = &mc_addr_set[i];
 340                 if (!rte_is_multicast_ether_addr(addr)) {
 341                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 342                                               addr);
 343                         hns3_err(hw,
 344                                  "Failed to set mc mac addr, addr(%s) invalid.",
 345                                  mac_str);
 346                         return -EINVAL;
 347                 }
 348         }
 349         rte_spinlock_lock(&hw->lock);
 350         cur_addr_num = hw->mc_addrs_num;
 351         for (i = 0; i < cur_addr_num; i++) {
 352                 num = cur_addr_num - i - 1;
 353                 addr = &hw->mc_addrs[num];
 354                 ret = hns3vf_remove_mc_mac_addr(hns, addr);
 355                 if (ret) {
 356                         rte_spinlock_unlock(&hw->lock);
 357                         return ret;
 358                 }
 359
 360                 hw->mc_addrs_num--;
 361         }
 362
 363         for (i = 0; i < set_addr_num; i++) {
 364                 addr = &mc_addr_set[i];
 365                 ret = hns3vf_add_mc_mac_addr(hns, addr);
 366                 if (ret) {
 367                         rte_spinlock_unlock(&hw->lock);
 368                         return ret;
 369                 }
 370
 371                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 372                 hw->mc_addrs_num++;
 373         }
 374         rte_spinlock_unlock(&hw->lock);
 375
 376         return 0;
 377 }
 378
 379 static int
 380 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 381 {
 382         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 383         struct hns3_hw *hw = &hns->hw;
 384         struct rte_ether_addr *addr;
 385         int err = 0;
 386         int ret;
 387         int i;
 388
 389         for (i = 0; i < hw->mc_addrs_num; i++) {
 390                 addr = &hw->mc_addrs[i];
 391                 if (!rte_is_multicast_ether_addr(addr))
 392                         continue;
 393                 if (del)
 394                         ret = hns3vf_remove_mc_mac_addr(hns, addr);
 395                 else
 396                         ret = hns3vf_add_mc_mac_addr(hns, addr);
 397                 if (ret) {
 398                         err = ret;
 399                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 400                                               addr);
 401                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 402                                  del ? "Remove" : "Restore", mac_str, ret);
 403                 }
 404         }
 405         return err;
 406 }
 407
 408 static int
 409 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 410                         bool en_uc_pmc, bool en_mc_pmc)
 411 {
 412         struct hns3_mbx_vf_to_pf_cmd *req;
 413         struct hns3_cmd_desc desc;
 414         int ret;
 415
 416         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 417
 418         /*
 419          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 420          * so there are some features for promiscuous/allmulticast mode in hns3
 421          * VF PMD driver as below:
 422          * 1. The promiscuous/allmulticast mode can be configured successfully
 423          *    only based on the trusted VF device. If based on the non trusted
 424          *    VF device, configuring promiscuous/allmulticast mode will fail.
 425          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 426          *    kernel ethdev driver on the host by the following command:
 427          *      "ip link set <eth num> vf <vf id> turst on"
 428          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 429          *    driver can receive the ingress and outgoing traffic. In the words,
 430          *    all the ingress packets, all the packets sent from the PF and
 431          *    other VFs on the same physical port.
 432          * 3. Note: Because of the hardware constraints, By default vlan filter
 433          *    is enabled and couldn't be turned off based on VF device, so vlan
 434          *    filter is still effective even in promiscuous mode. If upper
 435          *    applications don't call rte_eth_dev_vlan_filter API function to
 436          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 437          *    the packets with vlan tag in promiscuoue mode.
 438          */
 439         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 440         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 441         req->msg[1] = en_bc_pmc ? 1 : 0;
 442         req->msg[2] = en_uc_pmc ? 1 : 0;
 443         req->msg[3] = en_mc_pmc ? 1 : 0;
 444
 445         ret = hns3_cmd_send(hw, &desc, 1);
 446         if (ret)
 447                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 448
 449         return ret;
 450 }
 451
 452 static int
 453 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 454 {
 455         struct hns3_adapter *hns = dev->data->dev_private;
 456         struct hns3_hw *hw = &hns->hw;
 457         int ret;
 458
 459         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 460         if (ret)
 461                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 462                         ret);
 463         return ret;
 464 }
 465
 466 static int
 467 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 468 {
 469         bool allmulti = dev->data->all_multicast ? true : false;
 470         struct hns3_adapter *hns = dev->data->dev_private;
 471         struct hns3_hw *hw = &hns->hw;
 472         int ret;
 473
 474         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 475         if (ret)
 476                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 477                         ret);
 478         return ret;
 479 }
 480
 481 static int
 482 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 483 {
 484         struct hns3_adapter *hns = dev->data->dev_private;
 485         struct hns3_hw *hw = &hns->hw;
 486         int ret;
 487
 488         if (dev->data->promiscuous)
 489                 return 0;
 490
 491         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 492         if (ret)
 493                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 494                         ret);
 495         return ret;
 496 }
 497
 498 static int
 499 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 500 {
 501         struct hns3_adapter *hns = dev->data->dev_private;
 502         struct hns3_hw *hw = &hns->hw;
 503         int ret;
 504
 505         if (dev->data->promiscuous)
 506                 return 0;
 507
 508         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 509         if (ret)
 510                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 511                         ret);
 512         return ret;
 513 }
 514
 515 static int
 516 hns3vf_restore_promisc(struct hns3_adapter *hns)
 517 {
 518         struct hns3_hw *hw = &hns->hw;
 519         bool allmulti = hw->data->all_multicast ? true : false;
 520
 521         if (hw->data->promiscuous)
 522                 return hns3vf_set_promisc_mode(hw, true, true, true);
 523
 524         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 525 }
 526
 527 static int
 528 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 529                              bool mmap, enum hns3_ring_type queue_type,
 530                              uint16_t queue_id)
 531 {
 532         struct hns3_vf_bind_vector_msg bind_msg;
 533         const char *op_str;
 534         uint16_t code;
 535         int ret;
 536
 537         memset(&bind_msg, 0, sizeof(bind_msg));
 538         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 539                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 540         bind_msg.vector_id = vector_id;
 541
 542         if (queue_type == HNS3_RING_TYPE_RX)
 543                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 544         else
 545                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 546
 547         bind_msg.param[0].ring_type = queue_type;
 548         bind_msg.ring_num = 1;
 549         bind_msg.param[0].tqp_index = queue_id;
 550         op_str = mmap ? "Map" : "Unmap";
 551         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 552                                 sizeof(bind_msg), false, NULL, 0);
 553         if (ret) {
 554                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 555                          op_str, queue_id, bind_msg.vector_id, ret);
 556                 return ret;
 557         }
 558
 559         return 0;
 560 }
 561
 562 static int
 563 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 564 {
 565         uint8_t vec;
 566         int ret;
 567         int i;
 568
 569         /*
 570          * In hns3 network engine, vector 0 is always the misc interrupt of this
 571          * function, vector 1~N can be used respectively for the queues of the
 572          * function. Tx and Rx queues with the same number share the interrupt
 573          * vector. In the initialization clearing the all hardware mapping
 574          * relationship configurations between queues and interrupt vectors is
 575          * needed, so some error caused by the residual configurations, such as
 576          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 577          * constraints in hns3 hardware engine, we have to implement clearing
 578          * the mapping relationship configurations by binding all queues to the
 579          * last interrupt vector and reserving the last interrupt vector. This
 580          * method results in a decrease of the maximum queues when upper
 581          * applications call the rte_eth_dev_configure API function to enable
 582          * Rx interrupt.
 583          */
 584         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 585         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
 586         for (i = 0; i < hw->intr_tqps_num; i++) {
 587                 /*
 588                  * Set gap limiter and rate limiter configuration of queue's
 589                  * interrupt.
 590                  */
 591                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 592                                        HNS3_TQP_INTR_GL_DEFAULT);
 593                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 594                                        HNS3_TQP_INTR_GL_DEFAULT);
 595                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 596
 597                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 598                                                    HNS3_RING_TYPE_TX, i);
 599                 if (ret) {
 600                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 601                                           "vector: %d, ret=%d", i, vec, ret);
 602                         return ret;
 603                 }
 604
 605                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 606                                                    HNS3_RING_TYPE_RX, i);
 607                 if (ret) {
 608                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 609                                           "vector: %d, ret=%d", i, vec, ret);
 610                         return ret;
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 static int
 618 hns3vf_dev_configure(struct rte_eth_dev *dev)
 619 {
 620         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 621         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 622         struct rte_eth_conf *conf = &dev->data->dev_conf;
 623         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 624         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 625         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 626         struct rte_eth_rss_conf rss_conf;
 627         uint16_t mtu;
 628         int ret;
 629
 630         /*
 631          * Hardware does not support individually enable/disable/reset the Tx or
 632          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 633          * and Rx queues at the same time. When the numbers of Tx queues
 634          * allocated by upper applications are not equal to the numbers of Rx
 635          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 636          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 637          * these fake queues are imperceptible, and can not be used by upper
 638          * applications.
 639          */
 640         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 641         if (ret) {
 642                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 643                 return ret;
 644         }
 645
 646         hw->adapter_state = HNS3_NIC_CONFIGURING;
 647         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 648                 hns3_err(hw, "setting link speed/duplex not supported");
 649                 ret = -EINVAL;
 650                 goto cfg_err;
 651         }
 652
 653         /* When RSS is not configured, redirect the packet queue 0 */
 654         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 655                 rss_conf = conf->rx_adv_conf.rss_conf;
 656                 if (rss_conf.rss_key == NULL) {
 657                         rss_conf.rss_key = rss_cfg->key;
 658                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 659                 }
 660
 661                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 662                 if (ret)
 663                         goto cfg_err;
 664         }
 665
 666         /*
 667          * If jumbo frames are enabled, MTU needs to be refreshed
 668          * according to the maximum RX packet length.
 669          */
 670         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 671                 /*
 672                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 673                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 674                  * can safely assign to "uint16_t" type variable.
 675                  */
 676                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 677                 ret = hns3vf_dev_mtu_set(dev, mtu);
 678                 if (ret)
 679                         goto cfg_err;
 680                 dev->data->mtu = mtu;
 681         }
 682
 683         ret = hns3vf_dev_configure_vlan(dev);
 684         if (ret)
 685                 goto cfg_err;
 686
 687         hw->adapter_state = HNS3_NIC_CONFIGURED;
 688         return 0;
 689
 690 cfg_err:
 691         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 692         hw->adapter_state = HNS3_NIC_INITIALIZED;
 693
 694         return ret;
 695 }
 696
 697 static int
 698 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 699 {
 700         int ret;
 701
 702         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 703                                 sizeof(mtu), true, NULL, 0);
 704         if (ret)
 705                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 706
 707         return ret;
 708 }
 709
 710 static int
 711 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 712 {
 713         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 714         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 715         int ret;
 716
 717         /*
 718          * The hns3 PF/VF devices on the same port share the hardware MTU
 719          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 720          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 721          * driver, there is no need to stop the port for hns3 VF device, and the
 722          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 723          * PF's MTU.
 724          */
 725         if (rte_atomic16_read(&hw->reset.resetting)) {
 726                 hns3_err(hw, "Failed to set mtu during resetting");
 727                 return -EIO;
 728         }
 729
 730         rte_spinlock_lock(&hw->lock);
 731         ret = hns3vf_config_mtu(hw, mtu);
 732         if (ret) {
 733                 rte_spinlock_unlock(&hw->lock);
 734                 return ret;
 735         }
 736         if (frame_size > RTE_ETHER_MAX_LEN)
 737                 dev->data->dev_conf.rxmode.offloads |=
 738                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 739         else
 740                 dev->data->dev_conf.rxmode.offloads &=
 741                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 742         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 743         rte_spinlock_unlock(&hw->lock);
 744
 745         return 0;
 746 }
 747
 748 static int
 749 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 750 {
 751         struct hns3_adapter *hns = eth_dev->data->dev_private;
 752         struct hns3_hw *hw = &hns->hw;
 753         uint16_t q_num = hw->tqps_num;
 754
 755         /*
 756          * In interrupt mode, 'max_rx_queues' is set based on the number of
 757          * MSI-X interrupt resources of the hardware.
 758          */
 759         if (hw->data->dev_conf.intr_conf.rxq == 1)
 760                 q_num = hw->intr_tqps_num;
 761
 762         info->max_rx_queues = q_num;
 763         info->max_tx_queues = hw->tqps_num;
 764         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 765         info->min_rx_bufsize = hw->rx_buf_len;
 766         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 767         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 768
 769         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 770                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 771                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 772                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 773                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 774                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 775                                  DEV_RX_OFFLOAD_KEEP_CRC |
 776                                  DEV_RX_OFFLOAD_SCATTER |
 777                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 778                                  DEV_RX_OFFLOAD_QINQ_STRIP |
 779                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 780                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
 781         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 782         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 783                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 784                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 785                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 786                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 787                                  DEV_TX_OFFLOAD_VLAN_INSERT |
 788                                  DEV_TX_OFFLOAD_QINQ_INSERT |
 789                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 790                                  DEV_TX_OFFLOAD_TCP_TSO |
 791                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 792                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 793                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 794                                  info->tx_queue_offload_capa);
 795
 796         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 797                 .nb_max = HNS3_MAX_RING_DESC,
 798                 .nb_min = HNS3_MIN_RING_DESC,
 799                 .nb_align = HNS3_ALIGN_RING_DESC,
 800         };
 801
 802         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 803                 .nb_max = HNS3_MAX_RING_DESC,
 804                 .nb_min = HNS3_MIN_RING_DESC,
 805                 .nb_align = HNS3_ALIGN_RING_DESC,
 806         };
 807
 808         info->vmdq_queue_num = 0;
 809
 810         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 811         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 812         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 813         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 814         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 815
 816         return 0;
 817 }
 818
 819 static void
 820 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 821 {
 822         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 823 }
 824
 825 static void
 826 hns3vf_disable_irq0(struct hns3_hw *hw)
 827 {
 828         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 829 }
 830
 831 static void
 832 hns3vf_enable_irq0(struct hns3_hw *hw)
 833 {
 834         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 835 }
 836
 837 static enum hns3vf_evt_cause
 838 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 839 {
 840         struct hns3_hw *hw = &hns->hw;
 841         enum hns3vf_evt_cause ret;
 842         uint32_t cmdq_stat_reg;
 843         uint32_t rst_ing_reg;
 844         uint32_t val;
 845
 846         /* Fetch the events from their corresponding regs */
 847         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 848
 849         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 850                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 851                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 852                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 853                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 854                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 855                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 856                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 857                 if (clearval) {
 858                         hw->reset.stats.global_cnt++;
 859                         hns3_warn(hw, "Global reset detected, clear reset status");
 860                 } else {
 861                         hns3_schedule_delayed_reset(hns);
 862                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 863                 }
 864
 865                 ret = HNS3VF_VECTOR0_EVENT_RST;
 866                 goto out;
 867         }
 868
 869         /* Check for vector0 mailbox(=CMDQ RX) event source */
 870         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 871                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 872                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 873                 goto out;
 874         }
 875
 876         val = 0;
 877         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 878 out:
 879         if (clearval)
 880                 *clearval = val;
 881         return ret;
 882 }
 883
 884 static void
 885 hns3vf_interrupt_handler(void *param)
 886 {
 887         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 888         struct hns3_adapter *hns = dev->data->dev_private;
 889         struct hns3_hw *hw = &hns->hw;
 890         enum hns3vf_evt_cause event_cause;
 891         uint32_t clearval;
 892
 893         if (hw->irq_thread_id == 0)
 894                 hw->irq_thread_id = pthread_self();
 895
 896         /* Disable interrupt */
 897         hns3vf_disable_irq0(hw);
 898
 899         /* Read out interrupt causes */
 900         event_cause = hns3vf_check_event_cause(hns, &clearval);
 901
 902         switch (event_cause) {
 903         case HNS3VF_VECTOR0_EVENT_RST:
 904                 hns3_schedule_reset(hns);
 905                 break;
 906         case HNS3VF_VECTOR0_EVENT_MBX:
 907                 hns3_dev_handle_mbx_msg(hw);
 908                 break;
 909         default:
 910                 break;
 911         }
 912
 913         /* Clear interrupt causes */
 914         hns3vf_clear_event_cause(hw, clearval);
 915
 916         /* Enable interrupt */
 917         hns3vf_enable_irq0(hw);
 918 }
 919
 920 static int
 921 hns3vf_check_tqp_info(struct hns3_hw *hw)
 922 {
 923         uint16_t tqps_num;
 924
 925         tqps_num = hw->tqps_num;
 926         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
 927                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
 928                                   "range: 1~%d",
 929                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
 930                 return -EINVAL;
 931         }
 932
 933         if (hw->rx_buf_len == 0)
 934                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
 935         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
 936
 937         return 0;
 938 }
 939
 940 static int
 941 hns3vf_get_queue_info(struct hns3_hw *hw)
 942 {
 943 #define HNS3VF_TQPS_RSS_INFO_LEN        6
 944         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
 945         int ret;
 946
 947         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
 948                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
 949         if (ret) {
 950                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
 951                 return ret;
 952         }
 953
 954         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
 955         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
 956         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
 957
 958         return hns3vf_check_tqp_info(hw);
 959 }
 960
 961 static int
 962 hns3vf_get_queue_depth(struct hns3_hw *hw)
 963 {
 964 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
 965         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
 966         int ret;
 967
 968         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
 969                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
 970         if (ret) {
 971                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
 972                              ret);
 973                 return ret;
 974         }
 975
 976         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
 977         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
 978
 979         return 0;
 980 }
 981
 982 static int
 983 hns3vf_get_tc_info(struct hns3_hw *hw)
 984 {
 985         uint8_t resp_msg;
 986         int ret;
 987
 988         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
 989                                 true, &resp_msg, sizeof(resp_msg));
 990         if (ret) {
 991                 hns3_err(hw, "VF request to get TC info from PF failed %d",
 992                          ret);
 993                 return ret;
 994         }
 995
 996         hw->hw_tc_map = resp_msg;
 997
 998         return 0;
 999 }
1000
1001 static int
1002 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1003 {
1004         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1005         int ret;
1006
1007         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1008                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1009         if (ret) {
1010                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1011                 return ret;
1012         }
1013
1014         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1015
1016         return 0;
1017 }
1018
1019 static int
1020 hns3vf_get_configuration(struct hns3_hw *hw)
1021 {
1022         int ret;
1023
1024         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1025         hw->rss_dis_flag = false;
1026
1027         /* Get queue configuration from PF */
1028         ret = hns3vf_get_queue_info(hw);
1029         if (ret)
1030                 return ret;
1031
1032         /* Get queue depth info from PF */
1033         ret = hns3vf_get_queue_depth(hw);
1034         if (ret)
1035                 return ret;
1036
1037         /* Get user defined VF MAC addr from PF */
1038         ret = hns3vf_get_host_mac_addr(hw);
1039         if (ret)
1040                 return ret;
1041
1042         /* Get tc configuration from PF */
1043         return hns3vf_get_tc_info(hw);
1044 }
1045
1046 static int
1047 hns3vf_set_tc_info(struct hns3_adapter *hns)
1048 {
1049         struct hns3_hw *hw = &hns->hw;
1050         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1051         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1052         uint8_t i;
1053
1054         hw->num_tc = 0;
1055         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1056                 if (hw->hw_tc_map & BIT(i))
1057                         hw->num_tc++;
1058
1059         if (nb_rx_q < hw->num_tc) {
1060                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1061                          nb_rx_q, hw->num_tc);
1062                 return -EINVAL;
1063         }
1064
1065         if (nb_tx_q < hw->num_tc) {
1066                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1067                          nb_tx_q, hw->num_tc);
1068                 return -EINVAL;
1069         }
1070
1071         hns3_set_rss_size(hw, nb_rx_q);
1072         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1073
1074         return 0;
1075 }
1076
1077 static void
1078 hns3vf_request_link_info(struct hns3_hw *hw)
1079 {
1080         uint8_t resp_msg;
1081         int ret;
1082
1083         if (rte_atomic16_read(&hw->reset.resetting))
1084                 return;
1085         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1086                                 &resp_msg, sizeof(resp_msg));
1087         if (ret)
1088                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1089 }
1090
1091 static int
1092 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1093 {
1094 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1095         struct hns3_hw *hw = &hns->hw;
1096         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1097         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1098         uint8_t is_kill = on ? 0 : 1;
1099
1100         msg_data[0] = is_kill;
1101         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1102         memcpy(&msg_data[3], &proto, sizeof(proto));
1103
1104         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1105                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1106                                  0);
1107 }
1108
1109 static int
1110 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1111 {
1112         struct hns3_adapter *hns = dev->data->dev_private;
1113         struct hns3_hw *hw = &hns->hw;
1114         int ret;
1115
1116         if (rte_atomic16_read(&hw->reset.resetting)) {
1117                 hns3_err(hw,
1118                          "vf set vlan id failed during resetting, vlan_id =%u",
1119                          vlan_id);
1120                 return -EIO;
1121         }
1122         rte_spinlock_lock(&hw->lock);
1123         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1124         rte_spinlock_unlock(&hw->lock);
1125         if (ret)
1126                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1127                          vlan_id, ret);
1128
1129         return ret;
1130 }
1131
1132 static int
1133 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1134 {
1135         uint8_t msg_data;
1136         int ret;
1137
1138         msg_data = enable ? 1 : 0;
1139         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1140                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1141         if (ret)
1142                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1143
1144         return ret;
1145 }
1146
1147 static int
1148 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1149 {
1150         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1151         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1152         unsigned int tmp_mask;
1153
1154         tmp_mask = (unsigned int)mask;
1155         /* Vlan stripping setting */
1156         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1157                 rte_spinlock_lock(&hw->lock);
1158                 /* Enable or disable VLAN stripping */
1159                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1160                         hns3vf_en_hw_strip_rxvtag(hw, true);
1161                 else
1162                         hns3vf_en_hw_strip_rxvtag(hw, false);
1163                 rte_spinlock_unlock(&hw->lock);
1164         }
1165
1166         return 0;
1167 }
1168
1169 static int
1170 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1171 {
1172         struct rte_vlan_filter_conf *vfc;
1173         struct hns3_hw *hw = &hns->hw;
1174         uint16_t vlan_id;
1175         uint64_t vbit;
1176         uint64_t ids;
1177         int ret = 0;
1178         uint32_t i;
1179
1180         vfc = &hw->data->vlan_filter_conf;
1181         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1182                 if (vfc->ids[i] == 0)
1183                         continue;
1184                 ids = vfc->ids[i];
1185                 while (ids) {
1186                         /*
1187                          * 64 means the num bits of ids, one bit corresponds to
1188                          * one vlan id
1189                          */
1190                         vlan_id = 64 * i;
1191                         /* count trailing zeroes */
1192                         vbit = ~ids & (ids - 1);
1193                         /* clear least significant bit set */
1194                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1195                         for (; vbit;) {
1196                                 vbit >>= 1;
1197                                 vlan_id++;
1198                         }
1199                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1200                         if (ret) {
1201                                 hns3_err(hw,
1202                                          "VF handle vlan table failed, ret =%d, on = %d",
1203                                          ret, on);
1204                                 return ret;
1205                         }
1206                 }
1207         }
1208
1209         return ret;
1210 }
1211
1212 static int
1213 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1214 {
1215         return hns3vf_handle_all_vlan_table(hns, 0);
1216 }
1217
1218 static int
1219 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1220 {
1221         struct hns3_hw *hw = &hns->hw;
1222         struct rte_eth_conf *dev_conf;
1223         bool en;
1224         int ret;
1225
1226         dev_conf = &hw->data->dev_conf;
1227         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1228                                                                    : false;
1229         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1230         if (ret)
1231                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1232                          ret);
1233         return ret;
1234 }
1235
1236 static int
1237 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1238 {
1239         struct hns3_adapter *hns = dev->data->dev_private;
1240         struct rte_eth_dev_data *data = dev->data;
1241         struct hns3_hw *hw = &hns->hw;
1242         int ret;
1243
1244         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1245             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1246             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1247                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1248                               "or hw_vlan_insert_pvid is not support!");
1249         }
1250
1251         /* Apply vlan offload setting */
1252         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1253         if (ret)
1254                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1255
1256         return ret;
1257 }
1258
1259 static int
1260 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1261 {
1262         uint8_t msg_data;
1263
1264         msg_data = alive ? 1 : 0;
1265         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1266                                  sizeof(msg_data), false, NULL, 0);
1267 }
1268
1269 static void
1270 hns3vf_keep_alive_handler(void *param)
1271 {
1272         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1273         struct hns3_adapter *hns = eth_dev->data->dev_private;
1274         struct hns3_hw *hw = &hns->hw;
1275         uint8_t respmsg;
1276         int ret;
1277
1278         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1279                                 false, &respmsg, sizeof(uint8_t));
1280         if (ret)
1281                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1282                          ret);
1283
1284         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1285                           eth_dev);
1286 }
1287
1288 static void
1289 hns3vf_service_handler(void *param)
1290 {
1291         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1292         struct hns3_adapter *hns = eth_dev->data->dev_private;
1293         struct hns3_hw *hw = &hns->hw;
1294
1295         /*
1296          * The query link status and reset processing are executed in the
1297          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1298          * and the query operation will time out after 30ms. In the case of
1299          * multiple PF/VFs, each query failure timeout causes the IMP reset
1300          * interrupt to fail to respond within 100ms.
1301          * Before querying the link status, check whether there is a reset
1302          * pending, and if so, abandon the query.
1303          */
1304         if (!hns3vf_is_reset_pending(hns))
1305                 hns3vf_request_link_info(hw);
1306         else
1307                 hns3_warn(hw, "Cancel the query when reset is pending");
1308
1309         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1310                           eth_dev);
1311 }
1312
1313 static int
1314 hns3_query_vf_resource(struct hns3_hw *hw)
1315 {
1316         struct hns3_vf_res_cmd *req;
1317         struct hns3_cmd_desc desc;
1318         uint16_t num_msi;
1319         int ret;
1320
1321         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1322         ret = hns3_cmd_send(hw, &desc, 1);
1323         if (ret) {
1324                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1325                 return ret;
1326         }
1327
1328         req = (struct hns3_vf_res_cmd *)desc.data;
1329         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1330                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1331         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1332                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1333                          num_msi, HNS3_MIN_VECTOR_NUM);
1334                 return -EINVAL;
1335         }
1336
1337         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
1338
1339         return 0;
1340 }
1341
1342 static int
1343 hns3vf_init_hardware(struct hns3_adapter *hns)
1344 {
1345         struct hns3_hw *hw = &hns->hw;
1346         uint16_t mtu = hw->data->mtu;
1347         int ret;
1348
1349         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1350         if (ret)
1351                 return ret;
1352
1353         ret = hns3vf_config_mtu(hw, mtu);
1354         if (ret)
1355                 goto err_init_hardware;
1356
1357         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1358         if (ret) {
1359                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1360                 goto err_init_hardware;
1361         }
1362
1363         ret = hns3_config_gro(hw, false);
1364         if (ret) {
1365                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1366                 goto err_init_hardware;
1367         }
1368
1369         ret = hns3vf_set_alive(hw, true);
1370         if (ret) {
1371                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1372                 goto err_init_hardware;
1373         }
1374
1375         hns3vf_request_link_info(hw);
1376         return 0;
1377
1378 err_init_hardware:
1379         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1380         return ret;
1381 }
1382
1383 static int
1384 hns3vf_clear_vport_list(struct hns3_hw *hw)
1385 {
1386         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1387                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1388                                  NULL, 0);
1389 }
1390
1391 static int
1392 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1393 {
1394         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1395         struct hns3_adapter *hns = eth_dev->data->dev_private;
1396         struct hns3_hw *hw = &hns->hw;
1397         int ret;
1398
1399         PMD_INIT_FUNC_TRACE();
1400
1401         /* Get hardware io base address from pcie BAR2 IO space */
1402         hw->io_base = pci_dev->mem_resource[2].addr;
1403
1404         /* Firmware command queue initialize */
1405         ret = hns3_cmd_init_queue(hw);
1406         if (ret) {
1407                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1408                 goto err_cmd_init_queue;
1409         }
1410
1411         /* Firmware command initialize */
1412         ret = hns3_cmd_init(hw);
1413         if (ret) {
1414                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1415                 goto err_cmd_init;
1416         }
1417
1418         /* Get VF resource */
1419         ret = hns3_query_vf_resource(hw);
1420         if (ret)
1421                 goto err_cmd_init;
1422
1423         rte_spinlock_init(&hw->mbx_resp.lock);
1424
1425         hns3vf_clear_event_cause(hw, 0);
1426
1427         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1428                                          hns3vf_interrupt_handler, eth_dev);
1429         if (ret) {
1430                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1431                 goto err_intr_callback_register;
1432         }
1433
1434         /* Enable interrupt */
1435         rte_intr_enable(&pci_dev->intr_handle);
1436         hns3vf_enable_irq0(hw);
1437
1438         /* Get configuration from PF */
1439         ret = hns3vf_get_configuration(hw);
1440         if (ret) {
1441                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1442                 goto err_get_config;
1443         }
1444
1445         /*
1446          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1447          * on the host by "ip link set ..." command. To avoid some incorrect
1448          * scenes, for example, hns3 VF PMD driver fails to receive and send
1449          * packets after user configure the MAC address by using the
1450          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1451          * address strategy as the hns3 kernel ethdev driver in the
1452          * initialization. If user configure a MAC address by the ip command
1453          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1454          * start with a random MAC address in the initialization.
1455          */
1456         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1457         if (ret)
1458                 rte_eth_random_addr(hw->mac.mac_addr);
1459
1460         ret = hns3vf_clear_vport_list(hw);
1461         if (ret) {
1462                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1463                 goto err_get_config;
1464         }
1465
1466         ret = hns3vf_init_hardware(hns);
1467         if (ret)
1468                 goto err_get_config;
1469
1470         hns3_set_default_rss_args(hw);
1471
1472         /*
1473          * In the initialization clearing the all hardware mapping relationship
1474          * configurations between queues and interrupt vectors is needed, so
1475          * some error caused by the residual configurations, such as the
1476          * unexpected interrupt, can be avoid.
1477          */
1478         ret = hns3vf_init_ring_with_vector(hw);
1479         if (ret)
1480                 goto err_get_config;
1481
1482         return 0;
1483
1484 err_get_config:
1485         hns3vf_disable_irq0(hw);
1486         rte_intr_disable(&pci_dev->intr_handle);
1487         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1488                              eth_dev);
1489 err_intr_callback_register:
1490 err_cmd_init:
1491         hns3_cmd_uninit(hw);
1492         hns3_cmd_destroy_queue(hw);
1493 err_cmd_init_queue:
1494         hw->io_base = NULL;
1495
1496         return ret;
1497 }
1498
1499 static void
1500 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1501 {
1502         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1503         struct hns3_adapter *hns = eth_dev->data->dev_private;
1504         struct hns3_hw *hw = &hns->hw;
1505
1506         PMD_INIT_FUNC_TRACE();
1507
1508         hns3_rss_uninit(hns);
1509         (void)hns3vf_set_alive(hw, false);
1510         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1511         hns3vf_disable_irq0(hw);
1512         rte_intr_disable(&pci_dev->intr_handle);
1513         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1514                              eth_dev);
1515         hns3_cmd_uninit(hw);
1516         hns3_cmd_destroy_queue(hw);
1517         hw->io_base = NULL;
1518 }
1519
1520 static int
1521 hns3vf_do_stop(struct hns3_adapter *hns)
1522 {
1523         struct hns3_hw *hw = &hns->hw;
1524         bool reset_queue;
1525
1526         hw->mac.link_status = ETH_LINK_DOWN;
1527
1528         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1529                 hns3vf_configure_mac_addr(hns, true);
1530                 reset_queue = true;
1531         } else
1532                 reset_queue = false;
1533         return hns3_stop_queues(hns, reset_queue);
1534 }
1535
1536 static void
1537 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1538 {
1539         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542         uint8_t base = 0;
1543         uint8_t vec = 0;
1544         uint16_t q_id;
1545
1546         if (dev->data->dev_conf.intr_conf.rxq == 0)
1547                 return;
1548
1549         /* unmap the ring with vector */
1550         if (rte_intr_allow_others(intr_handle)) {
1551                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1552                 base = RTE_INTR_VEC_RXTX_OFFSET;
1553         }
1554         if (rte_intr_dp_is_en(intr_handle)) {
1555                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1556                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1557                                                            HNS3_RING_TYPE_RX,
1558                                                            q_id);
1559                         if (vec < base + intr_handle->nb_efd - 1)
1560                                 vec++;
1561                 }
1562         }
1563         /* Clean datapath event and queue/vec mapping */
1564         rte_intr_efd_disable(intr_handle);
1565         if (intr_handle->intr_vec) {
1566                 rte_free(intr_handle->intr_vec);
1567                 intr_handle->intr_vec = NULL;
1568         }
1569 }
1570
1571 static void
1572 hns3vf_dev_stop(struct rte_eth_dev *dev)
1573 {
1574         struct hns3_adapter *hns = dev->data->dev_private;
1575         struct hns3_hw *hw = &hns->hw;
1576
1577         PMD_INIT_FUNC_TRACE();
1578
1579         hw->adapter_state = HNS3_NIC_STOPPING;
1580         hns3_set_rxtx_function(dev);
1581         rte_wmb();
1582         /* Disable datapath on secondary process. */
1583         hns3_mp_req_stop_rxtx(dev);
1584         /* Prevent crashes when queues are still in use. */
1585         rte_delay_ms(hw->tqps_num);
1586
1587         rte_spinlock_lock(&hw->lock);
1588         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1589                 hns3vf_do_stop(hns);
1590                 hns3_dev_release_mbufs(hns);
1591                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1592         }
1593         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1594         rte_spinlock_unlock(&hw->lock);
1595
1596         hns3vf_unmap_rx_interrupt(dev);
1597 }
1598
1599 static void
1600 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1601 {
1602         struct hns3_adapter *hns = eth_dev->data->dev_private;
1603         struct hns3_hw *hw = &hns->hw;
1604
1605         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1606                 return;
1607
1608         if (hw->adapter_state == HNS3_NIC_STARTED)
1609                 hns3vf_dev_stop(eth_dev);
1610
1611         hw->adapter_state = HNS3_NIC_CLOSING;
1612         hns3_reset_abort(hns);
1613         hw->adapter_state = HNS3_NIC_CLOSED;
1614         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1615         hns3vf_configure_all_mc_mac_addr(hns, true);
1616         hns3vf_remove_all_vlan_table(hns);
1617         hns3vf_uninit_vf(eth_dev);
1618         hns3_free_all_queues(eth_dev);
1619         rte_free(hw->reset.wait_data);
1620         rte_free(eth_dev->process_private);
1621         eth_dev->process_private = NULL;
1622         hns3_mp_uninit_primary();
1623         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1624 }
1625
1626 static int
1627 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1628                        __rte_unused int wait_to_complete)
1629 {
1630         struct hns3_adapter *hns = eth_dev->data->dev_private;
1631         struct hns3_hw *hw = &hns->hw;
1632         struct hns3_mac *mac = &hw->mac;
1633         struct rte_eth_link new_link;
1634
1635         memset(&new_link, 0, sizeof(new_link));
1636         switch (mac->link_speed) {
1637         case ETH_SPEED_NUM_10M:
1638         case ETH_SPEED_NUM_100M:
1639         case ETH_SPEED_NUM_1G:
1640         case ETH_SPEED_NUM_10G:
1641         case ETH_SPEED_NUM_25G:
1642         case ETH_SPEED_NUM_40G:
1643         case ETH_SPEED_NUM_50G:
1644         case ETH_SPEED_NUM_100G:
1645                 new_link.link_speed = mac->link_speed;
1646                 break;
1647         default:
1648                 new_link.link_speed = ETH_SPEED_NUM_100M;
1649                 break;
1650         }
1651
1652         new_link.link_duplex = mac->link_duplex;
1653         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1654         new_link.link_autoneg =
1655             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1656
1657         return rte_eth_linkstatus_set(eth_dev, &new_link);
1658 }
1659
1660 static int
1661 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1662 {
1663         struct hns3_hw *hw = &hns->hw;
1664         int ret;
1665
1666         ret = hns3vf_set_tc_info(hns);
1667         if (ret)
1668                 return ret;
1669
1670         ret = hns3_start_queues(hns, reset_queue);
1671         if (ret) {
1672                 hns3_err(hw, "Failed to start queues: %d", ret);
1673                 return ret;
1674         }
1675
1676         return 0;
1677 }
1678
1679 static int
1680 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1681 {
1682         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1683         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1684         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         uint32_t intr_vector;
1686         uint8_t base = 0;
1687         uint8_t vec = 0;
1688         uint16_t q_id;
1689         int ret;
1690
1691         if (dev->data->dev_conf.intr_conf.rxq == 0)
1692                 return 0;
1693
1694         /* disable uio/vfio intr/eventfd mapping */
1695         rte_intr_disable(intr_handle);
1696
1697         /* check and configure queue intr-vector mapping */
1698         if (rte_intr_cap_multiple(intr_handle) ||
1699             !RTE_ETH_DEV_SRIOV(dev).active) {
1700                 intr_vector = hw->used_rx_queues;
1701                 /* It creates event fd for each intr vector when MSIX is used */
1702                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1703                         return -EINVAL;
1704         }
1705         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1706                 intr_handle->intr_vec =
1707                         rte_zmalloc("intr_vec",
1708                                     hw->used_rx_queues * sizeof(int), 0);
1709                 if (intr_handle->intr_vec == NULL) {
1710                         hns3_err(hw, "Failed to allocate %d rx_queues"
1711                                      " intr_vec", hw->used_rx_queues);
1712                         ret = -ENOMEM;
1713                         goto vf_alloc_intr_vec_error;
1714                 }
1715         }
1716
1717         if (rte_intr_allow_others(intr_handle)) {
1718                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1719                 base = RTE_INTR_VEC_RXTX_OFFSET;
1720         }
1721         if (rte_intr_dp_is_en(intr_handle)) {
1722                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1723                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1724                                                            HNS3_RING_TYPE_RX,
1725                                                            q_id);
1726                         if (ret)
1727                                 goto vf_bind_vector_error;
1728                         intr_handle->intr_vec[q_id] = vec;
1729                         if (vec < base + intr_handle->nb_efd - 1)
1730                                 vec++;
1731                 }
1732         }
1733         rte_intr_enable(intr_handle);
1734         return 0;
1735
1736 vf_bind_vector_error:
1737         rte_intr_efd_disable(intr_handle);
1738         if (intr_handle->intr_vec) {
1739                 free(intr_handle->intr_vec);
1740                 intr_handle->intr_vec = NULL;
1741         }
1742         return ret;
1743 vf_alloc_intr_vec_error:
1744         rte_intr_efd_disable(intr_handle);
1745         return ret;
1746 }
1747
1748 static void
1749 hns3vf_restore_filter(struct rte_eth_dev *dev)
1750 {
1751         hns3_restore_rss_filter(dev);
1752 }
1753
1754 static int
1755 hns3vf_dev_start(struct rte_eth_dev *dev)
1756 {
1757         struct hns3_adapter *hns = dev->data->dev_private;
1758         struct hns3_hw *hw = &hns->hw;
1759         int ret;
1760
1761         PMD_INIT_FUNC_TRACE();
1762         if (rte_atomic16_read(&hw->reset.resetting))
1763                 return -EBUSY;
1764
1765         rte_spinlock_lock(&hw->lock);
1766         hw->adapter_state = HNS3_NIC_STARTING;
1767         ret = hns3vf_do_start(hns, true);
1768         if (ret) {
1769                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1770                 rte_spinlock_unlock(&hw->lock);
1771                 return ret;
1772         }
1773         hw->adapter_state = HNS3_NIC_STARTED;
1774         rte_spinlock_unlock(&hw->lock);
1775
1776         ret = hns3vf_map_rx_interrupt(dev);
1777         if (ret)
1778                 return ret;
1779         hns3_set_rxtx_function(dev);
1780         hns3_mp_req_start_rxtx(dev);
1781         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
1782
1783         hns3vf_restore_filter(dev);
1784
1785         return ret;
1786 }
1787
1788 static bool
1789 is_vf_reset_done(struct hns3_hw *hw)
1790 {
1791 #define HNS3_FUN_RST_ING_BITS \
1792         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1793          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1794          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1795          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1796
1797         uint32_t val;
1798
1799         if (hw->reset.level == HNS3_VF_RESET) {
1800                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1801                 if (val & HNS3_VF_RST_ING_BIT)
1802                         return false;
1803         } else {
1804                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1805                 if (val & HNS3_FUN_RST_ING_BITS)
1806                         return false;
1807         }
1808         return true;
1809 }
1810
1811 bool
1812 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1813 {
1814         struct hns3_hw *hw = &hns->hw;
1815         enum hns3_reset_level reset;
1816
1817         hns3vf_check_event_cause(hns, NULL);
1818         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1819         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
1820                 hns3_warn(hw, "High level reset %d is pending", reset);
1821                 return true;
1822         }
1823         return false;
1824 }
1825
1826 static int
1827 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
1828 {
1829         struct hns3_hw *hw = &hns->hw;
1830         struct hns3_wait_data *wait_data = hw->reset.wait_data;
1831         struct timeval tv;
1832
1833         if (wait_data->result == HNS3_WAIT_SUCCESS) {
1834                 /*
1835                  * After vf reset is ready, the PF may not have completed
1836                  * the reset processing. The vf sending mbox to PF may fail
1837                  * during the pf reset, so it is better to add extra delay.
1838                  */
1839                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
1840                     hw->reset.level == HNS3_FLR_RESET)
1841                         return 0;
1842                 /* Reset retry process, no need to add extra delay. */
1843                 if (hw->reset.attempts)
1844                         return 0;
1845                 if (wait_data->check_completion == NULL)
1846                         return 0;
1847
1848                 wait_data->check_completion = NULL;
1849                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
1850                 wait_data->count = 1;
1851                 wait_data->result = HNS3_WAIT_REQUEST;
1852                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
1853                                   wait_data);
1854                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
1855                 return -EAGAIN;
1856         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
1857                 gettimeofday(&tv, NULL);
1858                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
1859                           tv.tv_sec, tv.tv_usec);
1860                 return -ETIME;
1861         } else if (wait_data->result == HNS3_WAIT_REQUEST)
1862                 return -EAGAIN;
1863
1864         wait_data->hns = hns;
1865         wait_data->check_completion = is_vf_reset_done;
1866         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
1867                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
1868         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
1869         wait_data->count = HNS3VF_RESET_WAIT_CNT;
1870         wait_data->result = HNS3_WAIT_REQUEST;
1871         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
1872         return -EAGAIN;
1873 }
1874
1875 static int
1876 hns3vf_prepare_reset(struct hns3_adapter *hns)
1877 {
1878         struct hns3_hw *hw = &hns->hw;
1879         int ret = 0;
1880
1881         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
1882                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
1883                                         0, true, NULL, 0);
1884         }
1885         rte_atomic16_set(&hw->reset.disable_cmd, 1);
1886
1887         return ret;
1888 }
1889
1890 static int
1891 hns3vf_stop_service(struct hns3_adapter *hns)
1892 {
1893         struct hns3_hw *hw = &hns->hw;
1894         struct rte_eth_dev *eth_dev;
1895
1896         eth_dev = &rte_eth_devices[hw->data->port_id];
1897         if (hw->adapter_state == HNS3_NIC_STARTED)
1898                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
1899         hw->mac.link_status = ETH_LINK_DOWN;
1900
1901         hns3_set_rxtx_function(eth_dev);
1902         rte_wmb();
1903         /* Disable datapath on secondary process. */
1904         hns3_mp_req_stop_rxtx(eth_dev);
1905         rte_delay_ms(hw->tqps_num);
1906
1907         rte_spinlock_lock(&hw->lock);
1908         if (hw->adapter_state == HNS3_NIC_STARTED ||
1909             hw->adapter_state == HNS3_NIC_STOPPING) {
1910                 hns3vf_do_stop(hns);
1911                 hw->reset.mbuf_deferred_free = true;
1912         } else
1913                 hw->reset.mbuf_deferred_free = false;
1914
1915         /*
1916          * It is cumbersome for hardware to pick-and-choose entries for deletion
1917          * from table space. Hence, for function reset software intervention is
1918          * required to delete the entries.
1919          */
1920         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
1921                 hns3vf_configure_all_mc_mac_addr(hns, true);
1922         rte_spinlock_unlock(&hw->lock);
1923
1924         return 0;
1925 }
1926
1927 static int
1928 hns3vf_start_service(struct hns3_adapter *hns)
1929 {
1930         struct hns3_hw *hw = &hns->hw;
1931         struct rte_eth_dev *eth_dev;
1932
1933         eth_dev = &rte_eth_devices[hw->data->port_id];
1934         hns3_set_rxtx_function(eth_dev);
1935         hns3_mp_req_start_rxtx(eth_dev);
1936         if (hw->adapter_state == HNS3_NIC_STARTED)
1937                 hns3vf_service_handler(eth_dev);
1938
1939         return 0;
1940 }
1941
1942 static int
1943 hns3vf_check_default_mac_change(struct hns3_hw *hw)
1944 {
1945         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1946         struct rte_ether_addr *hw_mac;
1947         int ret;
1948
1949         /*
1950          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1951          * on the host by "ip link set ..." command. If the hns3 PF kernel
1952          * ethdev driver sets the MAC address for VF device after the
1953          * initialization of the related VF device, the PF driver will notify
1954          * VF driver to reset VF device to make the new MAC address effective
1955          * immediately. The hns3 VF PMD driver should check whether the MAC
1956          * address has been changed by the PF kernel ethdev driver, if changed
1957          * VF driver should configure hardware using the new MAC address in the
1958          * recovering hardware configuration stage of the reset process.
1959          */
1960         ret = hns3vf_get_host_mac_addr(hw);
1961         if (ret)
1962                 return ret;
1963
1964         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
1965         ret = rte_is_zero_ether_addr(hw_mac);
1966         if (ret) {
1967                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
1968         } else {
1969                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
1970                 if (!ret) {
1971                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
1972                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1973                                               &hw->data->mac_addrs[0]);
1974                         hns3_warn(hw, "Default MAC address has been changed to:"
1975                                   " %s by the host PF kernel ethdev driver",
1976                                   mac_str);
1977                 }
1978         }
1979
1980         return 0;
1981 }
1982
1983 static int
1984 hns3vf_restore_conf(struct hns3_adapter *hns)
1985 {
1986         struct hns3_hw *hw = &hns->hw;
1987         int ret;
1988
1989         ret = hns3vf_check_default_mac_change(hw);
1990         if (ret)
1991                 return ret;
1992
1993         ret = hns3vf_configure_mac_addr(hns, false);
1994         if (ret)
1995                 return ret;
1996
1997         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
1998         if (ret)
1999                 goto err_mc_mac;
2000
2001         ret = hns3vf_restore_promisc(hns);
2002         if (ret)
2003                 goto err_vlan_table;
2004
2005         ret = hns3vf_restore_vlan_conf(hns);
2006         if (ret)
2007                 goto err_vlan_table;
2008
2009         if (hw->adapter_state == HNS3_NIC_STARTED) {
2010                 ret = hns3vf_do_start(hns, false);
2011                 if (ret)
2012                         goto err_vlan_table;
2013                 hns3_info(hw, "hns3vf dev restart successful!");
2014         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2015                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2016         return 0;
2017
2018 err_vlan_table:
2019         hns3vf_configure_all_mc_mac_addr(hns, true);
2020 err_mc_mac:
2021         hns3vf_configure_mac_addr(hns, true);
2022         return ret;
2023 }
2024
2025 static enum hns3_reset_level
2026 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2027 {
2028         enum hns3_reset_level reset_level;
2029
2030         /* return the highest priority reset level amongst all */
2031         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2032                 reset_level = HNS3_VF_RESET;
2033         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2034                 reset_level = HNS3_VF_FULL_RESET;
2035         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2036                 reset_level = HNS3_VF_PF_FUNC_RESET;
2037         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2038                 reset_level = HNS3_VF_FUNC_RESET;
2039         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2040                 reset_level = HNS3_FLR_RESET;
2041         else
2042                 reset_level = HNS3_NONE_RESET;
2043
2044         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2045                 return HNS3_NONE_RESET;
2046
2047         return reset_level;
2048 }
2049
2050 static void
2051 hns3vf_reset_service(void *param)
2052 {
2053         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2054         struct hns3_hw *hw = &hns->hw;
2055         enum hns3_reset_level reset_level;
2056         struct timeval tv_delta;
2057         struct timeval tv_start;
2058         struct timeval tv;
2059         uint64_t msec;
2060
2061         /*
2062          * The interrupt is not triggered within the delay time.
2063          * The interrupt may have been lost. It is necessary to handle
2064          * the interrupt to recover from the error.
2065          */
2066         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2067                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2068                 hns3_err(hw, "Handling interrupts in delayed tasks");
2069                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2070                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2071                 if (reset_level == HNS3_NONE_RESET) {
2072                         hns3_err(hw, "No reset level is set, try global reset");
2073                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2074                 }
2075         }
2076         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2077
2078         /*
2079          * Hardware reset has been notified, we now have to poll & check if
2080          * hardware has actually completed the reset sequence.
2081          */
2082         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2083         if (reset_level != HNS3_NONE_RESET) {
2084                 gettimeofday(&tv_start, NULL);
2085                 hns3_reset_process(hns, reset_level);
2086                 gettimeofday(&tv, NULL);
2087                 timersub(&tv, &tv_start, &tv_delta);
2088                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2089                        tv_delta.tv_usec / USEC_PER_MSEC;
2090                 if (msec > HNS3_RESET_PROCESS_MS)
2091                         hns3_err(hw, "%d handle long time delta %" PRIx64
2092                                  " ms time=%ld.%.6ld",
2093                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2094         }
2095 }
2096
2097 static int
2098 hns3vf_reinit_dev(struct hns3_adapter *hns)
2099 {
2100         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2101         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2102         struct hns3_hw *hw = &hns->hw;
2103         int ret;
2104
2105         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2106                 rte_intr_disable(&pci_dev->intr_handle);
2107                 hns3vf_set_bus_master(pci_dev, true);
2108         }
2109
2110         /* Firmware command initialize */
2111         ret = hns3_cmd_init(hw);
2112         if (ret) {
2113                 hns3_err(hw, "Failed to init cmd: %d", ret);
2114                 return ret;
2115         }
2116
2117         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2118                 /*
2119                  * UIO enables msix by writing the pcie configuration space
2120                  * vfio_pci enables msix in rte_intr_enable.
2121                  */
2122                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2123                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2124                         if (hns3vf_enable_msix(pci_dev, true))
2125                                 hns3_err(hw, "Failed to enable msix");
2126                 }
2127
2128                 rte_intr_enable(&pci_dev->intr_handle);
2129         }
2130
2131         ret = hns3_reset_all_queues(hns);
2132         if (ret) {
2133                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2134                 return ret;
2135         }
2136
2137         ret = hns3vf_init_hardware(hns);
2138         if (ret) {
2139                 hns3_err(hw, "Failed to init hardware: %d", ret);
2140                 return ret;
2141         }
2142
2143         return 0;
2144 }
2145
2146 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2147         .dev_start          = hns3vf_dev_start,
2148         .dev_stop           = hns3vf_dev_stop,
2149         .dev_close          = hns3vf_dev_close,
2150         .mtu_set            = hns3vf_dev_mtu_set,
2151         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2152         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2153         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2154         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2155         .stats_get          = hns3_stats_get,
2156         .stats_reset        = hns3_stats_reset,
2157         .xstats_get         = hns3_dev_xstats_get,
2158         .xstats_get_names   = hns3_dev_xstats_get_names,
2159         .xstats_reset       = hns3_dev_xstats_reset,
2160         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2161         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2162         .dev_infos_get      = hns3vf_dev_infos_get,
2163         .rx_queue_setup     = hns3_rx_queue_setup,
2164         .tx_queue_setup     = hns3_tx_queue_setup,
2165         .rx_queue_release   = hns3_dev_rx_queue_release,
2166         .tx_queue_release   = hns3_dev_tx_queue_release,
2167         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2168         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2169         .dev_configure      = hns3vf_dev_configure,
2170         .mac_addr_add       = hns3vf_add_mac_addr,
2171         .mac_addr_remove    = hns3vf_remove_mac_addr,
2172         .mac_addr_set       = hns3vf_set_default_mac_addr,
2173         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2174         .link_update        = hns3vf_dev_link_update,
2175         .rss_hash_update    = hns3_dev_rss_hash_update,
2176         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2177         .reta_update        = hns3_dev_rss_reta_update,
2178         .reta_query         = hns3_dev_rss_reta_query,
2179         .filter_ctrl        = hns3_dev_filter_ctrl,
2180         .vlan_filter_set    = hns3vf_vlan_filter_set,
2181         .vlan_offload_set   = hns3vf_vlan_offload_set,
2182         .get_reg            = hns3_get_regs,
2183         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2184 };
2185
2186 static const struct hns3_reset_ops hns3vf_reset_ops = {
2187         .reset_service       = hns3vf_reset_service,
2188         .stop_service        = hns3vf_stop_service,
2189         .prepare_reset       = hns3vf_prepare_reset,
2190         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2191         .reinit_dev          = hns3vf_reinit_dev,
2192         .restore_conf        = hns3vf_restore_conf,
2193         .start_service       = hns3vf_start_service,
2194 };
2195
2196 static int
2197 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2198 {
2199         struct hns3_adapter *hns = eth_dev->data->dev_private;
2200         struct hns3_hw *hw = &hns->hw;
2201         int ret;
2202
2203         PMD_INIT_FUNC_TRACE();
2204
2205         eth_dev->process_private = (struct hns3_process_private *)
2206             rte_zmalloc_socket("hns3_filter_list",
2207                                sizeof(struct hns3_process_private),
2208                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2209         if (eth_dev->process_private == NULL) {
2210                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2211                 return -ENOMEM;
2212         }
2213
2214         /* initialize flow filter lists */
2215         hns3_filterlist_init(eth_dev);
2216
2217         hns3_set_rxtx_function(eth_dev);
2218         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2219         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2220                 hns3_mp_init_secondary();
2221                 hw->secondary_cnt++;
2222                 return 0;
2223         }
2224
2225         hns3_mp_init_primary();
2226
2227         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2228         hns->is_vf = true;
2229         hw->data = eth_dev->data;
2230
2231         ret = hns3_reset_init(hw);
2232         if (ret)
2233                 goto err_init_reset;
2234         hw->reset.ops = &hns3vf_reset_ops;
2235
2236         ret = hns3vf_init_vf(eth_dev);
2237         if (ret) {
2238                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2239                 goto err_init_vf;
2240         }
2241
2242         /* Allocate memory for storing MAC addresses */
2243         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2244                                                sizeof(struct rte_ether_addr) *
2245                                                HNS3_VF_UC_MACADDR_NUM, 0);
2246         if (eth_dev->data->mac_addrs == NULL) {
2247                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2248                              "to store MAC addresses",
2249                              sizeof(struct rte_ether_addr) *
2250                              HNS3_VF_UC_MACADDR_NUM);
2251                 ret = -ENOMEM;
2252                 goto err_rte_zmalloc;
2253         }
2254
2255         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2256                             &eth_dev->data->mac_addrs[0]);
2257         hw->adapter_state = HNS3_NIC_INITIALIZED;
2258         /*
2259          * Pass the information to the rte_eth_dev_close() that it should also
2260          * release the private port resources.
2261          */
2262         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2263
2264         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2265                 hns3_err(hw, "Reschedule reset service after dev_init");
2266                 hns3_schedule_reset(hns);
2267         } else {
2268                 /* IMP will wait ready flag before reset */
2269                 hns3_notify_reset_ready(hw, false);
2270         }
2271         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2272                           eth_dev);
2273         return 0;
2274
2275 err_rte_zmalloc:
2276         hns3vf_uninit_vf(eth_dev);
2277
2278 err_init_vf:
2279         rte_free(hw->reset.wait_data);
2280
2281 err_init_reset:
2282         eth_dev->dev_ops = NULL;
2283         eth_dev->rx_pkt_burst = NULL;
2284         eth_dev->tx_pkt_burst = NULL;
2285         eth_dev->tx_pkt_prepare = NULL;
2286         rte_free(eth_dev->process_private);
2287         eth_dev->process_private = NULL;
2288
2289         return ret;
2290 }
2291
2292 static int
2293 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2294 {
2295         struct hns3_adapter *hns = eth_dev->data->dev_private;
2296         struct hns3_hw *hw = &hns->hw;
2297
2298         PMD_INIT_FUNC_TRACE();
2299
2300         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2301                 return -EPERM;
2302
2303         eth_dev->dev_ops = NULL;
2304         eth_dev->rx_pkt_burst = NULL;
2305         eth_dev->tx_pkt_burst = NULL;
2306         eth_dev->tx_pkt_prepare = NULL;
2307
2308         if (hw->adapter_state < HNS3_NIC_CLOSING)
2309                 hns3vf_dev_close(eth_dev);
2310
2311         hw->adapter_state = HNS3_NIC_REMOVED;
2312         return 0;
2313 }
2314
2315 static int
2316 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2317                      struct rte_pci_device *pci_dev)
2318 {
2319         return rte_eth_dev_pci_generic_probe(pci_dev,
2320                                              sizeof(struct hns3_adapter),
2321                                              hns3vf_dev_init);
2322 }
2323
2324 static int
2325 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2326 {
2327         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2328 }
2329
2330 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2331         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2332         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2333         { .vendor_id = 0, /* sentinel */ },
2334 };
2335
2336 static struct rte_pci_driver rte_hns3vf_pmd = {
2337         .id_table = pci_id_hns3vf_map,
2338         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2339         .probe = eth_hns3vf_pci_probe,
2340         .remove = eth_hns3vf_pci_remove,
2341 };
2342
2343 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2344 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2345 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");