drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint16_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid.
 708          */
 709         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 710         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 711                 vec = vec - 1; /* the last interrupt is reserved */
 712         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 713         for (i = 0; i < hw->intr_tqps_num; i++) {
 714                 /*
 715                  * Set gap limiter/rate limiter/quanity limiter algorithm
 716                  * configuration for interrupt coalesce of queue's interrupt.
 717                  */
 718                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 719                                        HNS3_TQP_INTR_GL_DEFAULT);
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 723                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 724
 725                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 726                                                    HNS3_RING_TYPE_TX, i);
 727                 if (ret) {
 728                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 729                                           "vector: %d, ret=%d", i, vec, ret);
 730                         return ret;
 731                 }
 732
 733                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 734                                                    HNS3_RING_TYPE_RX, i);
 735                 if (ret) {
 736                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 737                                           "vector: %d, ret=%d", i, vec, ret);
 738                         return ret;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3vf_dev_configure(struct rte_eth_dev *dev)
 747 {
 748         struct hns3_adapter *hns = dev->data->dev_private;
 749         struct hns3_hw *hw = &hns->hw;
 750         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 751         struct rte_eth_conf *conf = &dev->data->dev_conf;
 752         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 753         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 754         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 755         struct rte_eth_rss_conf rss_conf;
 756         uint16_t mtu;
 757         bool gro_en;
 758         int ret;
 759
 760         /*
 761          * Hardware does not support individually enable/disable/reset the Tx or
 762          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 763          * and Rx queues at the same time. When the numbers of Tx queues
 764          * allocated by upper applications are not equal to the numbers of Rx
 765          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 766          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 767          * these fake queues are imperceptible, and can not be used by upper
 768          * applications.
 769          */
 770         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 771         if (ret) {
 772                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 773                 return ret;
 774         }
 775
 776         hw->adapter_state = HNS3_NIC_CONFIGURING;
 777         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 778                 hns3_err(hw, "setting link speed/duplex not supported");
 779                 ret = -EINVAL;
 780                 goto cfg_err;
 781         }
 782
 783         /* When RSS is not configured, redirect the packet queue 0 */
 784         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 785                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 786                 hw->rss_dis_flag = false;
 787                 rss_conf = conf->rx_adv_conf.rss_conf;
 788                 if (rss_conf.rss_key == NULL) {
 789                         rss_conf.rss_key = rss_cfg->key;
 790                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 791                 }
 792
 793                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 794                 if (ret)
 795                         goto cfg_err;
 796         }
 797
 798         /*
 799          * If jumbo frames are enabled, MTU needs to be refreshed
 800          * according to the maximum RX packet length.
 801          */
 802         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 803                 /*
 804                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 805                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 806                  * can safely assign to "uint16_t" type variable.
 807                  */
 808                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 809                 ret = hns3vf_dev_mtu_set(dev, mtu);
 810                 if (ret)
 811                         goto cfg_err;
 812                 dev->data->mtu = mtu;
 813         }
 814
 815         ret = hns3vf_dev_configure_vlan(dev);
 816         if (ret)
 817                 goto cfg_err;
 818
 819         /* config hardware GRO */
 820         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 821         ret = hns3_config_gro(hw, gro_en);
 822         if (ret)
 823                 goto cfg_err;
 824
 825         hns->rx_simple_allowed = true;
 826         hns->rx_vec_allowed = true;
 827         hns->tx_simple_allowed = true;
 828         hns->tx_vec_allowed = true;
 829
 830         hns3_init_rx_ptype_tble(dev);
 831
 832         hw->adapter_state = HNS3_NIC_CONFIGURED;
 833         return 0;
 834
 835 cfg_err:
 836         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 837         hw->adapter_state = HNS3_NIC_INITIALIZED;
 838
 839         return ret;
 840 }
 841
 842 static int
 843 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 844 {
 845         int ret;
 846
 847         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 848                                 sizeof(mtu), true, NULL, 0);
 849         if (ret)
 850                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 851
 852         return ret;
 853 }
 854
 855 static int
 856 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 857 {
 858         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 859         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 860         int ret;
 861
 862         /*
 863          * The hns3 PF/VF devices on the same port share the hardware MTU
 864          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 865          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 866          * driver, there is no need to stop the port for hns3 VF device, and the
 867          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 868          * PF's MTU.
 869          */
 870         if (rte_atomic16_read(&hw->reset.resetting)) {
 871                 hns3_err(hw, "Failed to set mtu during resetting");
 872                 return -EIO;
 873         }
 874
 875         /*
 876          * when Rx of scattered packets is off, we have some possibility of
 877          * using vector Rx process function or simple Rx functions in hns3 PMD
 878          * driver. If the input MTU is increased and the maximum length of
 879          * received packets is greater than the length of a buffer for Rx
 880          * packet, the hardware network engine needs to use multiple BDs and
 881          * buffers to store these packets. This will cause problems when still
 882          * using vector Rx process function or simple Rx function to receiving
 883          * packets. So, when Rx of scattered packets is off and device is
 884          * started, it is not permitted to increase MTU so that the maximum
 885          * length of Rx packets is greater than Rx buffer length.
 886          */
 887         if (dev->data->dev_started && !dev->data->scattered_rx &&
 888             frame_size > hw->rx_buf_len) {
 889                 hns3_err(hw, "failed to set mtu because current is "
 890                         "not scattered rx mode");
 891                 return -EOPNOTSUPP;
 892         }
 893
 894         rte_spinlock_lock(&hw->lock);
 895         ret = hns3vf_config_mtu(hw, mtu);
 896         if (ret) {
 897                 rte_spinlock_unlock(&hw->lock);
 898                 return ret;
 899         }
 900         if (frame_size > RTE_ETHER_MAX_LEN)
 901                 dev->data->dev_conf.rxmode.offloads |=
 902                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 903         else
 904                 dev->data->dev_conf.rxmode.offloads &=
 905                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 906         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 907         rte_spinlock_unlock(&hw->lock);
 908
 909         return 0;
 910 }
 911
 912 static int
 913 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 914 {
 915         struct hns3_adapter *hns = eth_dev->data->dev_private;
 916         struct hns3_hw *hw = &hns->hw;
 917         uint16_t q_num = hw->tqps_num;
 918
 919         /*
 920          * In interrupt mode, 'max_rx_queues' is set based on the number of
 921          * MSI-X interrupt resources of the hardware.
 922          */
 923         if (hw->data->dev_conf.intr_conf.rxq == 1)
 924                 q_num = hw->intr_tqps_num;
 925
 926         info->max_rx_queues = q_num;
 927         info->max_tx_queues = hw->tqps_num;
 928         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 929         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 930         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 931         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 932         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 933
 934         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 935                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 936                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 937                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 938                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 939                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 940                                  DEV_RX_OFFLOAD_SCATTER |
 941                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 942                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 943                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 944                                  DEV_RX_OFFLOAD_RSS_HASH |
 945                                  DEV_RX_OFFLOAD_TCP_LRO);
 946         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 947                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 948                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 949                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 950                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 951                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 952                                  DEV_TX_OFFLOAD_TCP_TSO |
 953                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 954                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 955                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 956                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 957                                  hns3_txvlan_cap_get(hw));
 958
 959         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 960                 .nb_max = HNS3_MAX_RING_DESC,
 961                 .nb_min = HNS3_MIN_RING_DESC,
 962                 .nb_align = HNS3_ALIGN_RING_DESC,
 963         };
 964
 965         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 966                 .nb_max = HNS3_MAX_RING_DESC,
 967                 .nb_min = HNS3_MIN_RING_DESC,
 968                 .nb_align = HNS3_ALIGN_RING_DESC,
 969                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 970                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 971         };
 972
 973         info->default_rxconf = (struct rte_eth_rxconf) {
 974                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 975                 /*
 976                  * If there are no available Rx buffer descriptors, incoming
 977                  * packets are always dropped by hardware based on hns3 network
 978                  * engine.
 979                  */
 980                 .rx_drop_en = 1,
 981                 .offloads = 0,
 982         };
 983         info->default_txconf = (struct rte_eth_txconf) {
 984                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 985                 .offloads = 0,
 986         };
 987
 988         info->vmdq_queue_num = 0;
 989
 990         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 991         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 992         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 993         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 994         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 995
 996         return 0;
 997 }
 998
 999 static void
1000 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1001 {
1002         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1003 }
1004
1005 static void
1006 hns3vf_disable_irq0(struct hns3_hw *hw)
1007 {
1008         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1009 }
1010
1011 static void
1012 hns3vf_enable_irq0(struct hns3_hw *hw)
1013 {
1014         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1015 }
1016
1017 static enum hns3vf_evt_cause
1018 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1019 {
1020         struct hns3_hw *hw = &hns->hw;
1021         enum hns3vf_evt_cause ret;
1022         uint32_t cmdq_stat_reg;
1023         uint32_t rst_ing_reg;
1024         uint32_t val;
1025
1026         /* Fetch the events from their corresponding regs */
1027         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1028
1029         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1030                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1031                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1032                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1033                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1034                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1035                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1036                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1037                 if (clearval) {
1038                         hw->reset.stats.global_cnt++;
1039                         hns3_warn(hw, "Global reset detected, clear reset status");
1040                 } else {
1041                         hns3_schedule_delayed_reset(hns);
1042                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1043                 }
1044
1045                 ret = HNS3VF_VECTOR0_EVENT_RST;
1046                 goto out;
1047         }
1048
1049         /* Check for vector0 mailbox(=CMDQ RX) event source */
1050         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1051                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1052                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1053                 goto out;
1054         }
1055
1056         val = 0;
1057         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1058 out:
1059         if (clearval)
1060                 *clearval = val;
1061         return ret;
1062 }
1063
1064 static void
1065 hns3vf_interrupt_handler(void *param)
1066 {
1067         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1068         struct hns3_adapter *hns = dev->data->dev_private;
1069         struct hns3_hw *hw = &hns->hw;
1070         enum hns3vf_evt_cause event_cause;
1071         uint32_t clearval;
1072
1073         if (hw->irq_thread_id == 0)
1074                 hw->irq_thread_id = pthread_self();
1075
1076         /* Disable interrupt */
1077         hns3vf_disable_irq0(hw);
1078
1079         /* Read out interrupt causes */
1080         event_cause = hns3vf_check_event_cause(hns, &clearval);
1081
1082         switch (event_cause) {
1083         case HNS3VF_VECTOR0_EVENT_RST:
1084                 hns3_schedule_reset(hns);
1085                 break;
1086         case HNS3VF_VECTOR0_EVENT_MBX:
1087                 hns3_dev_handle_mbx_msg(hw);
1088                 break;
1089         default:
1090                 break;
1091         }
1092
1093         /* Clear interrupt causes */
1094         hns3vf_clear_event_cause(hw, clearval);
1095
1096         /* Enable interrupt */
1097         hns3vf_enable_irq0(hw);
1098 }
1099
1100 static void
1101 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1102 {
1103         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1104         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1105         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1106 }
1107
1108 static void
1109 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1110 {
1111         struct hns3_dev_specs_0_cmd *req0;
1112
1113         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1114
1115         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1116         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1117         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1118 }
1119
1120 static int
1121 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1122 {
1123         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1124         int ret;
1125         int i;
1126
1127         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1128                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1129                                           true);
1130                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1131         }
1132         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1133
1134         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1135         if (ret)
1136                 return ret;
1137
1138         hns3vf_parse_dev_specifications(hw, desc);
1139
1140         return 0;
1141 }
1142
1143 static int
1144 hns3vf_get_capability(struct hns3_hw *hw)
1145 {
1146         struct rte_pci_device *pci_dev;
1147         struct rte_eth_dev *eth_dev;
1148         uint8_t revision;
1149         int ret;
1150
1151         eth_dev = &rte_eth_devices[hw->data->port_id];
1152         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1153
1154         /* Get PCI revision id */
1155         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1156                                   HNS3_PCI_REVISION_ID);
1157         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1158                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1159                              ret);
1160                 return -EIO;
1161         }
1162         hw->revision = revision;
1163
1164         if (revision < PCI_REVISION_ID_HIP09_A) {
1165                 hns3vf_set_default_dev_specifications(hw);
1166                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1167                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1168                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1169                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1170                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1171                 return 0;
1172         }
1173
1174         ret = hns3vf_query_dev_specifications(hw);
1175         if (ret) {
1176                 PMD_INIT_LOG(ERR,
1177                              "failed to query dev specifications, ret = %d",
1178                              ret);
1179                 return ret;
1180         }
1181
1182         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1183         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1184         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1185         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1186         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1187
1188         return 0;
1189 }
1190
1191 static int
1192 hns3vf_check_tqp_info(struct hns3_hw *hw)
1193 {
1194         if (hw->tqps_num == 0) {
1195                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1196                 return -EINVAL;
1197         }
1198
1199         if (hw->rss_size_max == 0) {
1200                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1201                 return -EINVAL;
1202         }
1203
1204         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1205
1206         return 0;
1207 }
1208
1209 static int
1210 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1211 {
1212         uint8_t resp_msg;
1213         int ret;
1214
1215         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1216                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1217                                 true, &resp_msg, sizeof(resp_msg));
1218         if (ret) {
1219                 if (ret == -ETIME) {
1220                         /*
1221                          * Getting current port based VLAN state from PF driver
1222                          * will not affect VF driver's basic function. Because
1223                          * the VF driver relies on hns3 PF kernel ether driver,
1224                          * to avoid introducing compatibility issues with older
1225                          * version of PF driver, no failure will be returned
1226                          * when the return value is ETIME. This return value has
1227                          * the following scenarios:
1228                          * 1) Firmware didn't return the results in time
1229                          * 2) the result return by firmware is timeout
1230                          * 3) the older version of kernel side PF driver does
1231                          *    not support this mailbox message.
1232                          * For scenarios 1 and 2, it is most likely that a
1233                          * hardware error has occurred, or a hardware reset has
1234                          * occurred. In this case, these errors will be caught
1235                          * by other functions.
1236                          */
1237                         PMD_INIT_LOG(WARNING,
1238                                 "failed to get PVID state for timeout, maybe "
1239                                 "kernel side PF driver doesn't support this "
1240                                 "mailbox message, or firmware didn't respond.");
1241                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1242                 } else {
1243                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1244                                 " ret = %d", ret);
1245                         return ret;
1246                 }
1247         }
1248         hw->port_base_vlan_cfg.state = resp_msg ?
1249                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1250         return 0;
1251 }
1252
1253 static int
1254 hns3vf_get_queue_info(struct hns3_hw *hw)
1255 {
1256 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1257         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1258         int ret;
1259
1260         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1261                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1262         if (ret) {
1263                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1264                 return ret;
1265         }
1266
1267         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1268         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1269
1270         return hns3vf_check_tqp_info(hw);
1271 }
1272
1273 static int
1274 hns3vf_get_queue_depth(struct hns3_hw *hw)
1275 {
1276 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1277         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1278         int ret;
1279
1280         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1281                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1282         if (ret) {
1283                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1284                              ret);
1285                 return ret;
1286         }
1287
1288         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1289         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1290
1291         return 0;
1292 }
1293
1294 static int
1295 hns3vf_get_tc_info(struct hns3_hw *hw)
1296 {
1297         uint8_t resp_msg;
1298         int ret;
1299         int i;
1300
1301         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1302                                 true, &resp_msg, sizeof(resp_msg));
1303         if (ret) {
1304                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1305                          ret);
1306                 return ret;
1307         }
1308
1309         hw->hw_tc_map = resp_msg;
1310
1311         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1312                 if (hw->hw_tc_map & BIT(i))
1313                         hw->num_tc++;
1314         }
1315
1316         return 0;
1317 }
1318
1319 static int
1320 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1321 {
1322         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1323         int ret;
1324
1325         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1326                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1327         if (ret) {
1328                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1329                 return ret;
1330         }
1331
1332         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1333
1334         return 0;
1335 }
1336
1337 static int
1338 hns3vf_get_configuration(struct hns3_hw *hw)
1339 {
1340         int ret;
1341
1342         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1343         hw->rss_dis_flag = false;
1344
1345         /* Get device capability */
1346         ret = hns3vf_get_capability(hw);
1347         if (ret) {
1348                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1349                 return ret;
1350         }
1351
1352         /* Get queue configuration from PF */
1353         ret = hns3vf_get_queue_info(hw);
1354         if (ret)
1355                 return ret;
1356
1357         /* Get queue depth info from PF */
1358         ret = hns3vf_get_queue_depth(hw);
1359         if (ret)
1360                 return ret;
1361
1362         /* Get user defined VF MAC addr from PF */
1363         ret = hns3vf_get_host_mac_addr(hw);
1364         if (ret)
1365                 return ret;
1366
1367         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1368         if (ret)
1369                 return ret;
1370
1371         /* Get tc configuration from PF */
1372         return hns3vf_get_tc_info(hw);
1373 }
1374
1375 static int
1376 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1377                             uint16_t nb_tx_q)
1378 {
1379         struct hns3_hw *hw = &hns->hw;
1380
1381         if (nb_rx_q < hw->num_tc) {
1382                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1383                          nb_rx_q, hw->num_tc);
1384                 return -EINVAL;
1385         }
1386
1387         if (nb_tx_q < hw->num_tc) {
1388                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1389                          nb_tx_q, hw->num_tc);
1390                 return -EINVAL;
1391         }
1392
1393         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1394 }
1395
1396 static void
1397 hns3vf_request_link_info(struct hns3_hw *hw)
1398 {
1399         uint8_t resp_msg;
1400         int ret;
1401
1402         if (rte_atomic16_read(&hw->reset.resetting))
1403                 return;
1404         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1405                                 &resp_msg, sizeof(resp_msg));
1406         if (ret)
1407                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1408 }
1409
1410 static int
1411 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1412 {
1413 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1414         struct hns3_hw *hw = &hns->hw;
1415         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1416         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1417         uint8_t is_kill = on ? 0 : 1;
1418
1419         msg_data[0] = is_kill;
1420         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1421         memcpy(&msg_data[3], &proto, sizeof(proto));
1422
1423         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1424                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1425                                  0);
1426 }
1427
1428 static int
1429 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1430 {
1431         struct hns3_adapter *hns = dev->data->dev_private;
1432         struct hns3_hw *hw = &hns->hw;
1433         int ret;
1434
1435         if (rte_atomic16_read(&hw->reset.resetting)) {
1436                 hns3_err(hw,
1437                          "vf set vlan id failed during resetting, vlan_id =%u",
1438                          vlan_id);
1439                 return -EIO;
1440         }
1441         rte_spinlock_lock(&hw->lock);
1442         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1443         rte_spinlock_unlock(&hw->lock);
1444         if (ret)
1445                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1446                          vlan_id, ret);
1447
1448         return ret;
1449 }
1450
1451 static int
1452 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1453 {
1454         uint8_t msg_data;
1455         int ret;
1456
1457         msg_data = enable ? 1 : 0;
1458         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1459                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1460         if (ret)
1461                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1462
1463         return ret;
1464 }
1465
1466 static int
1467 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1468 {
1469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1470         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1471         unsigned int tmp_mask;
1472         int ret = 0;
1473
1474         if (rte_atomic16_read(&hw->reset.resetting)) {
1475                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1476                              "mask = 0x%x", mask);
1477                 return -EIO;
1478         }
1479
1480         tmp_mask = (unsigned int)mask;
1481         /* Vlan stripping setting */
1482         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1483                 rte_spinlock_lock(&hw->lock);
1484                 /* Enable or disable VLAN stripping */
1485                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1486                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1487                 else
1488                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1489                 rte_spinlock_unlock(&hw->lock);
1490         }
1491
1492         return ret;
1493 }
1494
1495 static int
1496 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1497 {
1498         struct rte_vlan_filter_conf *vfc;
1499         struct hns3_hw *hw = &hns->hw;
1500         uint16_t vlan_id;
1501         uint64_t vbit;
1502         uint64_t ids;
1503         int ret = 0;
1504         uint32_t i;
1505
1506         vfc = &hw->data->vlan_filter_conf;
1507         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1508                 if (vfc->ids[i] == 0)
1509                         continue;
1510                 ids = vfc->ids[i];
1511                 while (ids) {
1512                         /*
1513                          * 64 means the num bits of ids, one bit corresponds to
1514                          * one vlan id
1515                          */
1516                         vlan_id = 64 * i;
1517                         /* count trailing zeroes */
1518                         vbit = ~ids & (ids - 1);
1519                         /* clear least significant bit set */
1520                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1521                         for (; vbit;) {
1522                                 vbit >>= 1;
1523                                 vlan_id++;
1524                         }
1525                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1526                         if (ret) {
1527                                 hns3_err(hw,
1528                                          "VF handle vlan table failed, ret =%d, on = %d",
1529                                          ret, on);
1530                                 return ret;
1531                         }
1532                 }
1533         }
1534
1535         return ret;
1536 }
1537
1538 static int
1539 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1540 {
1541         return hns3vf_handle_all_vlan_table(hns, 0);
1542 }
1543
1544 static int
1545 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1546 {
1547         struct hns3_hw *hw = &hns->hw;
1548         struct rte_eth_conf *dev_conf;
1549         bool en;
1550         int ret;
1551
1552         dev_conf = &hw->data->dev_conf;
1553         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1554                                                                    : false;
1555         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1556         if (ret)
1557                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1558                          ret);
1559         return ret;
1560 }
1561
1562 static int
1563 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1564 {
1565         struct hns3_adapter *hns = dev->data->dev_private;
1566         struct rte_eth_dev_data *data = dev->data;
1567         struct hns3_hw *hw = &hns->hw;
1568         int ret;
1569
1570         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1571             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1572             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1573                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1574                               "or hw_vlan_insert_pvid is not support!");
1575         }
1576
1577         /* Apply vlan offload setting */
1578         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1579         if (ret)
1580                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1581
1582         return ret;
1583 }
1584
1585 static int
1586 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1587 {
1588         uint8_t msg_data;
1589
1590         msg_data = alive ? 1 : 0;
1591         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1592                                  sizeof(msg_data), false, NULL, 0);
1593 }
1594
1595 static void
1596 hns3vf_keep_alive_handler(void *param)
1597 {
1598         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1599         struct hns3_adapter *hns = eth_dev->data->dev_private;
1600         struct hns3_hw *hw = &hns->hw;
1601         uint8_t respmsg;
1602         int ret;
1603
1604         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1605                                 false, &respmsg, sizeof(uint8_t));
1606         if (ret)
1607                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1608                          ret);
1609
1610         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1611                           eth_dev);
1612 }
1613
1614 static void
1615 hns3vf_service_handler(void *param)
1616 {
1617         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1618         struct hns3_adapter *hns = eth_dev->data->dev_private;
1619         struct hns3_hw *hw = &hns->hw;
1620
1621         /*
1622          * The query link status and reset processing are executed in the
1623          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1624          * and the query operation will time out after 30ms. In the case of
1625          * multiple PF/VFs, each query failure timeout causes the IMP reset
1626          * interrupt to fail to respond within 100ms.
1627          * Before querying the link status, check whether there is a reset
1628          * pending, and if so, abandon the query.
1629          */
1630         if (!hns3vf_is_reset_pending(hns))
1631                 hns3vf_request_link_info(hw);
1632         else
1633                 hns3_warn(hw, "Cancel the query when reset is pending");
1634
1635         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1636                           eth_dev);
1637 }
1638
1639 static int
1640 hns3_query_vf_resource(struct hns3_hw *hw)
1641 {
1642         struct hns3_vf_res_cmd *req;
1643         struct hns3_cmd_desc desc;
1644         uint16_t num_msi;
1645         int ret;
1646
1647         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1648         ret = hns3_cmd_send(hw, &desc, 1);
1649         if (ret) {
1650                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1651                 return ret;
1652         }
1653
1654         req = (struct hns3_vf_res_cmd *)desc.data;
1655         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1656                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1657         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1658                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1659                          num_msi, HNS3_MIN_VECTOR_NUM);
1660                 return -EINVAL;
1661         }
1662
1663         hw->num_msi = num_msi;
1664
1665         return 0;
1666 }
1667
1668 static int
1669 hns3vf_init_hardware(struct hns3_adapter *hns)
1670 {
1671         struct hns3_hw *hw = &hns->hw;
1672         uint16_t mtu = hw->data->mtu;
1673         int ret;
1674
1675         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1676         if (ret)
1677                 return ret;
1678
1679         ret = hns3vf_config_mtu(hw, mtu);
1680         if (ret)
1681                 goto err_init_hardware;
1682
1683         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1684         if (ret) {
1685                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1686                 goto err_init_hardware;
1687         }
1688
1689         ret = hns3_config_gro(hw, false);
1690         if (ret) {
1691                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1692                 goto err_init_hardware;
1693         }
1694
1695         /*
1696          * In the initialization clearing the all hardware mapping relationship
1697          * configurations between queues and interrupt vectors is needed, so
1698          * some error caused by the residual configurations, such as the
1699          * unexpected interrupt, can be avoid.
1700          */
1701         ret = hns3vf_init_ring_with_vector(hw);
1702         if (ret) {
1703                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1704                 goto err_init_hardware;
1705         }
1706
1707         ret = hns3vf_set_alive(hw, true);
1708         if (ret) {
1709                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1710                 goto err_init_hardware;
1711         }
1712
1713         hns3vf_request_link_info(hw);
1714         return 0;
1715
1716 err_init_hardware:
1717         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1718         return ret;
1719 }
1720
1721 static int
1722 hns3vf_clear_vport_list(struct hns3_hw *hw)
1723 {
1724         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1725                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1726                                  NULL, 0);
1727 }
1728
1729 static int
1730 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1731 {
1732         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1733         struct hns3_adapter *hns = eth_dev->data->dev_private;
1734         struct hns3_hw *hw = &hns->hw;
1735         int ret;
1736
1737         PMD_INIT_FUNC_TRACE();
1738
1739         /* Get hardware io base address from pcie BAR2 IO space */
1740         hw->io_base = pci_dev->mem_resource[2].addr;
1741
1742         /* Firmware command queue initialize */
1743         ret = hns3_cmd_init_queue(hw);
1744         if (ret) {
1745                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1746                 goto err_cmd_init_queue;
1747         }
1748
1749         /* Firmware command initialize */
1750         ret = hns3_cmd_init(hw);
1751         if (ret) {
1752                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1753                 goto err_cmd_init;
1754         }
1755
1756         /* Get VF resource */
1757         ret = hns3_query_vf_resource(hw);
1758         if (ret)
1759                 goto err_cmd_init;
1760
1761         rte_spinlock_init(&hw->mbx_resp.lock);
1762
1763         hns3vf_clear_event_cause(hw, 0);
1764
1765         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1766                                          hns3vf_interrupt_handler, eth_dev);
1767         if (ret) {
1768                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1769                 goto err_intr_callback_register;
1770         }
1771
1772         /* Enable interrupt */
1773         rte_intr_enable(&pci_dev->intr_handle);
1774         hns3vf_enable_irq0(hw);
1775
1776         /* Get configuration from PF */
1777         ret = hns3vf_get_configuration(hw);
1778         if (ret) {
1779                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1780                 goto err_get_config;
1781         }
1782
1783         ret = hns3_tqp_stats_init(hw);
1784         if (ret)
1785                 goto err_get_config;
1786
1787         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1788         if (ret) {
1789                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1790                 goto err_set_tc_queue;
1791         }
1792
1793         ret = hns3vf_clear_vport_list(hw);
1794         if (ret) {
1795                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1796                 goto err_set_tc_queue;
1797         }
1798
1799         ret = hns3vf_init_hardware(hns);
1800         if (ret)
1801                 goto err_set_tc_queue;
1802
1803         hns3_set_default_rss_args(hw);
1804
1805         return 0;
1806
1807 err_set_tc_queue:
1808         hns3_tqp_stats_uninit(hw);
1809
1810 err_get_config:
1811         hns3vf_disable_irq0(hw);
1812         rte_intr_disable(&pci_dev->intr_handle);
1813         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1814                              eth_dev);
1815 err_intr_callback_register:
1816 err_cmd_init:
1817         hns3_cmd_uninit(hw);
1818         hns3_cmd_destroy_queue(hw);
1819 err_cmd_init_queue:
1820         hw->io_base = NULL;
1821
1822         return ret;
1823 }
1824
1825 static void
1826 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1827 {
1828         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1829         struct hns3_adapter *hns = eth_dev->data->dev_private;
1830         struct hns3_hw *hw = &hns->hw;
1831
1832         PMD_INIT_FUNC_TRACE();
1833
1834         hns3_rss_uninit(hns);
1835         (void)hns3_config_gro(hw, false);
1836         (void)hns3vf_set_alive(hw, false);
1837         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1838         hns3_tqp_stats_uninit(hw);
1839         hns3vf_disable_irq0(hw);
1840         rte_intr_disable(&pci_dev->intr_handle);
1841         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1842                              eth_dev);
1843         hns3_cmd_uninit(hw);
1844         hns3_cmd_destroy_queue(hw);
1845         hw->io_base = NULL;
1846 }
1847
1848 static int
1849 hns3vf_do_stop(struct hns3_adapter *hns)
1850 {
1851         struct hns3_hw *hw = &hns->hw;
1852         bool reset_queue;
1853
1854         hw->mac.link_status = ETH_LINK_DOWN;
1855
1856         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1857                 hns3vf_configure_mac_addr(hns, true);
1858                 reset_queue = true;
1859         } else
1860                 reset_queue = false;
1861         return hns3_stop_queues(hns, reset_queue);
1862 }
1863
1864 static void
1865 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1866 {
1867         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1868         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1869         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1870         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1871         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1872         uint16_t q_id;
1873
1874         if (dev->data->dev_conf.intr_conf.rxq == 0)
1875                 return;
1876
1877         /* unmap the ring with vector */
1878         if (rte_intr_allow_others(intr_handle)) {
1879                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1880                 base = RTE_INTR_VEC_RXTX_OFFSET;
1881         }
1882         if (rte_intr_dp_is_en(intr_handle)) {
1883                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1884                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1885                                                            HNS3_RING_TYPE_RX,
1886                                                            q_id);
1887                         if (vec < base + intr_handle->nb_efd - 1)
1888                                 vec++;
1889                 }
1890         }
1891         /* Clean datapath event and queue/vec mapping */
1892         rte_intr_efd_disable(intr_handle);
1893         if (intr_handle->intr_vec) {
1894                 rte_free(intr_handle->intr_vec);
1895                 intr_handle->intr_vec = NULL;
1896         }
1897 }
1898
1899 static void
1900 hns3vf_dev_stop(struct rte_eth_dev *dev)
1901 {
1902         struct hns3_adapter *hns = dev->data->dev_private;
1903         struct hns3_hw *hw = &hns->hw;
1904
1905         PMD_INIT_FUNC_TRACE();
1906
1907         hw->adapter_state = HNS3_NIC_STOPPING;
1908         hns3_set_rxtx_function(dev);
1909         rte_wmb();
1910         /* Disable datapath on secondary process. */
1911         hns3_mp_req_stop_rxtx(dev);
1912         /* Prevent crashes when queues are still in use. */
1913         rte_delay_ms(hw->tqps_num);
1914
1915         rte_spinlock_lock(&hw->lock);
1916         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1917                 hns3vf_do_stop(hns);
1918                 hns3vf_unmap_rx_interrupt(dev);
1919                 hns3_dev_release_mbufs(hns);
1920                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1921         }
1922         hns3_rx_scattered_reset(dev);
1923         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1924         rte_spinlock_unlock(&hw->lock);
1925 }
1926
1927 static int
1928 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1929 {
1930         struct hns3_adapter *hns = eth_dev->data->dev_private;
1931         struct hns3_hw *hw = &hns->hw;
1932
1933         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1934                 return 0;
1935
1936         if (hw->adapter_state == HNS3_NIC_STARTED)
1937                 hns3vf_dev_stop(eth_dev);
1938
1939         hw->adapter_state = HNS3_NIC_CLOSING;
1940         hns3_reset_abort(hns);
1941         hw->adapter_state = HNS3_NIC_CLOSED;
1942         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1943         hns3vf_configure_all_mc_mac_addr(hns, true);
1944         hns3vf_remove_all_vlan_table(hns);
1945         hns3vf_uninit_vf(eth_dev);
1946         hns3_free_all_queues(eth_dev);
1947         rte_free(hw->reset.wait_data);
1948         rte_free(eth_dev->process_private);
1949         eth_dev->process_private = NULL;
1950         hns3_mp_uninit_primary();
1951         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1952
1953         return 0;
1954 }
1955
1956 static int
1957 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1958                       size_t fw_size)
1959 {
1960         struct hns3_adapter *hns = eth_dev->data->dev_private;
1961         struct hns3_hw *hw = &hns->hw;
1962         uint32_t version = hw->fw_version;
1963         int ret;
1964
1965         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1966                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1967                                       HNS3_FW_VERSION_BYTE3_S),
1968                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1969                                       HNS3_FW_VERSION_BYTE2_S),
1970                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1971                                       HNS3_FW_VERSION_BYTE1_S),
1972                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1973                                       HNS3_FW_VERSION_BYTE0_S));
1974         ret += 1; /* add the size of '\0' */
1975         if (fw_size < (uint32_t)ret)
1976                 return ret;
1977         else
1978                 return 0;
1979 }
1980
1981 static int
1982 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1983                        __rte_unused int wait_to_complete)
1984 {
1985         struct hns3_adapter *hns = eth_dev->data->dev_private;
1986         struct hns3_hw *hw = &hns->hw;
1987         struct hns3_mac *mac = &hw->mac;
1988         struct rte_eth_link new_link;
1989
1990         memset(&new_link, 0, sizeof(new_link));
1991         switch (mac->link_speed) {
1992         case ETH_SPEED_NUM_10M:
1993         case ETH_SPEED_NUM_100M:
1994         case ETH_SPEED_NUM_1G:
1995         case ETH_SPEED_NUM_10G:
1996         case ETH_SPEED_NUM_25G:
1997         case ETH_SPEED_NUM_40G:
1998         case ETH_SPEED_NUM_50G:
1999         case ETH_SPEED_NUM_100G:
2000         case ETH_SPEED_NUM_200G:
2001                 new_link.link_speed = mac->link_speed;
2002                 break;
2003         default:
2004                 new_link.link_speed = ETH_SPEED_NUM_100M;
2005                 break;
2006         }
2007
2008         new_link.link_duplex = mac->link_duplex;
2009         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2010         new_link.link_autoneg =
2011             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2012
2013         return rte_eth_linkstatus_set(eth_dev, &new_link);
2014 }
2015
2016 static int
2017 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2018 {
2019         struct hns3_hw *hw = &hns->hw;
2020         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2021         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2022         int ret;
2023
2024         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2025         if (ret)
2026                 return ret;
2027
2028         ret = hns3_start_queues(hns, reset_queue);
2029         if (ret)
2030                 hns3_err(hw, "Failed to start queues: %d", ret);
2031
2032         return ret;
2033 }
2034
2035 static int
2036 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2037 {
2038         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2039         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2040         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2042         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2043         uint32_t intr_vector;
2044         uint16_t q_id;
2045         int ret;
2046
2047         if (dev->data->dev_conf.intr_conf.rxq == 0)
2048                 return 0;
2049
2050         /* disable uio/vfio intr/eventfd mapping */
2051         rte_intr_disable(intr_handle);
2052
2053         /* check and configure queue intr-vector mapping */
2054         if (rte_intr_cap_multiple(intr_handle) ||
2055             !RTE_ETH_DEV_SRIOV(dev).active) {
2056                 intr_vector = hw->used_rx_queues;
2057                 /* It creates event fd for each intr vector when MSIX is used */
2058                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2059                         return -EINVAL;
2060         }
2061         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2062                 intr_handle->intr_vec =
2063                         rte_zmalloc("intr_vec",
2064                                     hw->used_rx_queues * sizeof(int), 0);
2065                 if (intr_handle->intr_vec == NULL) {
2066                         hns3_err(hw, "Failed to allocate %d rx_queues"
2067                                      " intr_vec", hw->used_rx_queues);
2068                         ret = -ENOMEM;
2069                         goto vf_alloc_intr_vec_error;
2070                 }
2071         }
2072
2073         if (rte_intr_allow_others(intr_handle)) {
2074                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2075                 base = RTE_INTR_VEC_RXTX_OFFSET;
2076         }
2077         if (rte_intr_dp_is_en(intr_handle)) {
2078                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2079                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2080                                                            HNS3_RING_TYPE_RX,
2081                                                            q_id);
2082                         if (ret)
2083                                 goto vf_bind_vector_error;
2084                         intr_handle->intr_vec[q_id] = vec;
2085                         if (vec < base + intr_handle->nb_efd - 1)
2086                                 vec++;
2087                 }
2088         }
2089         rte_intr_enable(intr_handle);
2090         return 0;
2091
2092 vf_bind_vector_error:
2093         rte_intr_efd_disable(intr_handle);
2094         if (intr_handle->intr_vec) {
2095                 free(intr_handle->intr_vec);
2096                 intr_handle->intr_vec = NULL;
2097         }
2098         return ret;
2099 vf_alloc_intr_vec_error:
2100         rte_intr_efd_disable(intr_handle);
2101         return ret;
2102 }
2103
2104 static int
2105 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2106 {
2107         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2108         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2109         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2110         uint16_t q_id;
2111         int ret;
2112
2113         if (dev->data->dev_conf.intr_conf.rxq == 0)
2114                 return 0;
2115
2116         if (rte_intr_dp_is_en(intr_handle)) {
2117                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2118                         ret = hns3vf_bind_ring_with_vector(hw,
2119                                         intr_handle->intr_vec[q_id], true,
2120                                         HNS3_RING_TYPE_RX, q_id);
2121                         if (ret)
2122                                 return ret;
2123                 }
2124         }
2125
2126         return 0;
2127 }
2128
2129 static void
2130 hns3vf_restore_filter(struct rte_eth_dev *dev)
2131 {
2132         hns3_restore_rss_filter(dev);
2133 }
2134
2135 static int
2136 hns3vf_dev_start(struct rte_eth_dev *dev)
2137 {
2138         struct hns3_adapter *hns = dev->data->dev_private;
2139         struct hns3_hw *hw = &hns->hw;
2140         int ret;
2141
2142         PMD_INIT_FUNC_TRACE();
2143         if (rte_atomic16_read(&hw->reset.resetting))
2144                 return -EBUSY;
2145
2146         rte_spinlock_lock(&hw->lock);
2147         hw->adapter_state = HNS3_NIC_STARTING;
2148         ret = hns3vf_do_start(hns, true);
2149         if (ret) {
2150                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2151                 rte_spinlock_unlock(&hw->lock);
2152                 return ret;
2153         }
2154         ret = hns3vf_map_rx_interrupt(dev);
2155         if (ret) {
2156                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2157                 rte_spinlock_unlock(&hw->lock);
2158                 return ret;
2159         }
2160         hw->adapter_state = HNS3_NIC_STARTED;
2161         rte_spinlock_unlock(&hw->lock);
2162
2163         hns3_rx_scattered_calc(dev);
2164         hns3_set_rxtx_function(dev);
2165         hns3_mp_req_start_rxtx(dev);
2166         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2167
2168         hns3vf_restore_filter(dev);
2169
2170         /* Enable interrupt of all rx queues before enabling queues */
2171         hns3_dev_all_rx_queue_intr_enable(hw, true);
2172         /*
2173          * When finished the initialization, enable queues to receive/transmit
2174          * packets.
2175          */
2176         hns3_enable_all_queues(hw, true);
2177
2178         return ret;
2179 }
2180
2181 static bool
2182 is_vf_reset_done(struct hns3_hw *hw)
2183 {
2184 #define HNS3_FUN_RST_ING_BITS \
2185         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2186          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2187          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2188          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2189
2190         uint32_t val;
2191
2192         if (hw->reset.level == HNS3_VF_RESET) {
2193                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2194                 if (val & HNS3_VF_RST_ING_BIT)
2195                         return false;
2196         } else {
2197                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2198                 if (val & HNS3_FUN_RST_ING_BITS)
2199                         return false;
2200         }
2201         return true;
2202 }
2203
2204 bool
2205 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2206 {
2207         struct hns3_hw *hw = &hns->hw;
2208         enum hns3_reset_level reset;
2209
2210         /*
2211          * According to the protocol of PCIe, FLR to a PF device resets the PF
2212          * state as well as the SR-IOV extended capability including VF Enable
2213          * which means that VFs no longer exist.
2214          *
2215          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2216          * is in FLR stage, the register state of VF device is not reliable,
2217          * so register states detection can not be carried out. In this case,
2218          * we just ignore the register states and return false to indicate that
2219          * there are no other reset states that need to be processed by driver.
2220          */
2221         if (hw->reset.level == HNS3_VF_FULL_RESET)
2222                 return false;
2223
2224         /* Check the registers to confirm whether there is reset pending */
2225         hns3vf_check_event_cause(hns, NULL);
2226         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2227         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2228                 hns3_warn(hw, "High level reset %d is pending", reset);
2229                 return true;
2230         }
2231         return false;
2232 }
2233
2234 static int
2235 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2236 {
2237         struct hns3_hw *hw = &hns->hw;
2238         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2239         struct timeval tv;
2240
2241         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2242                 /*
2243                  * After vf reset is ready, the PF may not have completed
2244                  * the reset processing. The vf sending mbox to PF may fail
2245                  * during the pf reset, so it is better to add extra delay.
2246                  */
2247                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2248                     hw->reset.level == HNS3_FLR_RESET)
2249                         return 0;
2250                 /* Reset retry process, no need to add extra delay. */
2251                 if (hw->reset.attempts)
2252                         return 0;
2253                 if (wait_data->check_completion == NULL)
2254                         return 0;
2255
2256                 wait_data->check_completion = NULL;
2257                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2258                 wait_data->count = 1;
2259                 wait_data->result = HNS3_WAIT_REQUEST;
2260                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2261                                   wait_data);
2262                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2263                 return -EAGAIN;
2264         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2265                 gettimeofday(&tv, NULL);
2266                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2267                           tv.tv_sec, tv.tv_usec);
2268                 return -ETIME;
2269         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2270                 return -EAGAIN;
2271
2272         wait_data->hns = hns;
2273         wait_data->check_completion = is_vf_reset_done;
2274         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2275                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2276         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2277         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2278         wait_data->result = HNS3_WAIT_REQUEST;
2279         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2280         return -EAGAIN;
2281 }
2282
2283 static int
2284 hns3vf_prepare_reset(struct hns3_adapter *hns)
2285 {
2286         struct hns3_hw *hw = &hns->hw;
2287         int ret = 0;
2288
2289         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2290                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2291                                         0, true, NULL, 0);
2292         }
2293         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2294
2295         return ret;
2296 }
2297
2298 static int
2299 hns3vf_stop_service(struct hns3_adapter *hns)
2300 {
2301         struct hns3_hw *hw = &hns->hw;
2302         struct rte_eth_dev *eth_dev;
2303
2304         eth_dev = &rte_eth_devices[hw->data->port_id];
2305         if (hw->adapter_state == HNS3_NIC_STARTED)
2306                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2307         hw->mac.link_status = ETH_LINK_DOWN;
2308
2309         hns3_set_rxtx_function(eth_dev);
2310         rte_wmb();
2311         /* Disable datapath on secondary process. */
2312         hns3_mp_req_stop_rxtx(eth_dev);
2313         rte_delay_ms(hw->tqps_num);
2314
2315         rte_spinlock_lock(&hw->lock);
2316         if (hw->adapter_state == HNS3_NIC_STARTED ||
2317             hw->adapter_state == HNS3_NIC_STOPPING) {
2318                 hns3vf_do_stop(hns);
2319                 hw->reset.mbuf_deferred_free = true;
2320         } else
2321                 hw->reset.mbuf_deferred_free = false;
2322
2323         /*
2324          * It is cumbersome for hardware to pick-and-choose entries for deletion
2325          * from table space. Hence, for function reset software intervention is
2326          * required to delete the entries.
2327          */
2328         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2329                 hns3vf_configure_all_mc_mac_addr(hns, true);
2330         rte_spinlock_unlock(&hw->lock);
2331
2332         return 0;
2333 }
2334
2335 static int
2336 hns3vf_start_service(struct hns3_adapter *hns)
2337 {
2338         struct hns3_hw *hw = &hns->hw;
2339         struct rte_eth_dev *eth_dev;
2340
2341         eth_dev = &rte_eth_devices[hw->data->port_id];
2342         hns3_set_rxtx_function(eth_dev);
2343         hns3_mp_req_start_rxtx(eth_dev);
2344         if (hw->adapter_state == HNS3_NIC_STARTED) {
2345                 hns3vf_service_handler(eth_dev);
2346
2347                 /* Enable interrupt of all rx queues before enabling queues */
2348                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2349                 /*
2350                  * When finished the initialization, enable queues to receive
2351                  * and transmit packets.
2352                  */
2353                 hns3_enable_all_queues(hw, true);
2354         }
2355
2356         return 0;
2357 }
2358
2359 static int
2360 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2361 {
2362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2363         struct rte_ether_addr *hw_mac;
2364         int ret;
2365
2366         /*
2367          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2368          * on the host by "ip link set ..." command. If the hns3 PF kernel
2369          * ethdev driver sets the MAC address for VF device after the
2370          * initialization of the related VF device, the PF driver will notify
2371          * VF driver to reset VF device to make the new MAC address effective
2372          * immediately. The hns3 VF PMD driver should check whether the MAC
2373          * address has been changed by the PF kernel ethdev driver, if changed
2374          * VF driver should configure hardware using the new MAC address in the
2375          * recovering hardware configuration stage of the reset process.
2376          */
2377         ret = hns3vf_get_host_mac_addr(hw);
2378         if (ret)
2379                 return ret;
2380
2381         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2382         ret = rte_is_zero_ether_addr(hw_mac);
2383         if (ret) {
2384                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2385         } else {
2386                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2387                 if (!ret) {
2388                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2389                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2390                                               &hw->data->mac_addrs[0]);
2391                         hns3_warn(hw, "Default MAC address has been changed to:"
2392                                   " %s by the host PF kernel ethdev driver",
2393                                   mac_str);
2394                 }
2395         }
2396
2397         return 0;
2398 }
2399
2400 static int
2401 hns3vf_restore_conf(struct hns3_adapter *hns)
2402 {
2403         struct hns3_hw *hw = &hns->hw;
2404         int ret;
2405
2406         ret = hns3vf_check_default_mac_change(hw);
2407         if (ret)
2408                 return ret;
2409
2410         ret = hns3vf_configure_mac_addr(hns, false);
2411         if (ret)
2412                 return ret;
2413
2414         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2415         if (ret)
2416                 goto err_mc_mac;
2417
2418         ret = hns3vf_restore_promisc(hns);
2419         if (ret)
2420                 goto err_vlan_table;
2421
2422         ret = hns3vf_restore_vlan_conf(hns);
2423         if (ret)
2424                 goto err_vlan_table;
2425
2426         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2427         if (ret)
2428                 goto err_vlan_table;
2429
2430         ret = hns3vf_restore_rx_interrupt(hw);
2431         if (ret)
2432                 goto err_vlan_table;
2433
2434         ret = hns3_restore_gro_conf(hw);
2435         if (ret)
2436                 goto err_vlan_table;
2437
2438         if (hw->adapter_state == HNS3_NIC_STARTED) {
2439                 ret = hns3vf_do_start(hns, false);
2440                 if (ret)
2441                         goto err_vlan_table;
2442                 hns3_info(hw, "hns3vf dev restart successful!");
2443         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2444                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2445         return 0;
2446
2447 err_vlan_table:
2448         hns3vf_configure_all_mc_mac_addr(hns, true);
2449 err_mc_mac:
2450         hns3vf_configure_mac_addr(hns, true);
2451         return ret;
2452 }
2453
2454 static enum hns3_reset_level
2455 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2456 {
2457         enum hns3_reset_level reset_level;
2458
2459         /* return the highest priority reset level amongst all */
2460         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2461                 reset_level = HNS3_VF_RESET;
2462         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2463                 reset_level = HNS3_VF_FULL_RESET;
2464         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2465                 reset_level = HNS3_VF_PF_FUNC_RESET;
2466         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2467                 reset_level = HNS3_VF_FUNC_RESET;
2468         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2469                 reset_level = HNS3_FLR_RESET;
2470         else
2471                 reset_level = HNS3_NONE_RESET;
2472
2473         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2474                 return HNS3_NONE_RESET;
2475
2476         return reset_level;
2477 }
2478
2479 static void
2480 hns3vf_reset_service(void *param)
2481 {
2482         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2483         struct hns3_hw *hw = &hns->hw;
2484         enum hns3_reset_level reset_level;
2485         struct timeval tv_delta;
2486         struct timeval tv_start;
2487         struct timeval tv;
2488         uint64_t msec;
2489
2490         /*
2491          * The interrupt is not triggered within the delay time.
2492          * The interrupt may have been lost. It is necessary to handle
2493          * the interrupt to recover from the error.
2494          */
2495         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2496                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2497                 hns3_err(hw, "Handling interrupts in delayed tasks");
2498                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2499                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2500                 if (reset_level == HNS3_NONE_RESET) {
2501                         hns3_err(hw, "No reset level is set, try global reset");
2502                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2503                 }
2504         }
2505         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2506
2507         /*
2508          * Hardware reset has been notified, we now have to poll & check if
2509          * hardware has actually completed the reset sequence.
2510          */
2511         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2512         if (reset_level != HNS3_NONE_RESET) {
2513                 gettimeofday(&tv_start, NULL);
2514                 hns3_reset_process(hns, reset_level);
2515                 gettimeofday(&tv, NULL);
2516                 timersub(&tv, &tv_start, &tv_delta);
2517                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2518                        tv_delta.tv_usec / USEC_PER_MSEC;
2519                 if (msec > HNS3_RESET_PROCESS_MS)
2520                         hns3_err(hw, "%d handle long time delta %" PRIx64
2521                                  " ms time=%ld.%.6ld",
2522                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2523         }
2524 }
2525
2526 static int
2527 hns3vf_reinit_dev(struct hns3_adapter *hns)
2528 {
2529         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2530         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2531         struct hns3_hw *hw = &hns->hw;
2532         int ret;
2533
2534         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2535                 rte_intr_disable(&pci_dev->intr_handle);
2536                 hns3vf_set_bus_master(pci_dev, true);
2537         }
2538
2539         /* Firmware command initialize */
2540         ret = hns3_cmd_init(hw);
2541         if (ret) {
2542                 hns3_err(hw, "Failed to init cmd: %d", ret);
2543                 return ret;
2544         }
2545
2546         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2547                 /*
2548                  * UIO enables msix by writing the pcie configuration space
2549                  * vfio_pci enables msix in rte_intr_enable.
2550                  */
2551                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2552                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2553                         if (hns3vf_enable_msix(pci_dev, true))
2554                                 hns3_err(hw, "Failed to enable msix");
2555                 }
2556
2557                 rte_intr_enable(&pci_dev->intr_handle);
2558         }
2559
2560         ret = hns3_reset_all_queues(hns);
2561         if (ret) {
2562                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2563                 return ret;
2564         }
2565
2566         ret = hns3vf_init_hardware(hns);
2567         if (ret) {
2568                 hns3_err(hw, "Failed to init hardware: %d", ret);
2569                 return ret;
2570         }
2571
2572         return 0;
2573 }
2574
2575 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2576         .dev_configure      = hns3vf_dev_configure,
2577         .dev_start          = hns3vf_dev_start,
2578         .dev_stop           = hns3vf_dev_stop,
2579         .dev_close          = hns3vf_dev_close,
2580         .mtu_set            = hns3vf_dev_mtu_set,
2581         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2582         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2583         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2584         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2585         .stats_get          = hns3_stats_get,
2586         .stats_reset        = hns3_stats_reset,
2587         .xstats_get         = hns3_dev_xstats_get,
2588         .xstats_get_names   = hns3_dev_xstats_get_names,
2589         .xstats_reset       = hns3_dev_xstats_reset,
2590         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2591         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2592         .dev_infos_get      = hns3vf_dev_infos_get,
2593         .fw_version_get     = hns3vf_fw_version_get,
2594         .rx_queue_setup     = hns3_rx_queue_setup,
2595         .tx_queue_setup     = hns3_tx_queue_setup,
2596         .rx_queue_release   = hns3_dev_rx_queue_release,
2597         .tx_queue_release   = hns3_dev_tx_queue_release,
2598         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2599         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2600         .rxq_info_get       = hns3_rxq_info_get,
2601         .txq_info_get       = hns3_txq_info_get,
2602         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2603         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2604         .mac_addr_add       = hns3vf_add_mac_addr,
2605         .mac_addr_remove    = hns3vf_remove_mac_addr,
2606         .mac_addr_set       = hns3vf_set_default_mac_addr,
2607         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2608         .link_update        = hns3vf_dev_link_update,
2609         .rss_hash_update    = hns3_dev_rss_hash_update,
2610         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2611         .reta_update        = hns3_dev_rss_reta_update,
2612         .reta_query         = hns3_dev_rss_reta_query,
2613         .filter_ctrl        = hns3_dev_filter_ctrl,
2614         .vlan_filter_set    = hns3vf_vlan_filter_set,
2615         .vlan_offload_set   = hns3vf_vlan_offload_set,
2616         .get_reg            = hns3_get_regs,
2617         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2618 };
2619
2620 static const struct hns3_reset_ops hns3vf_reset_ops = {
2621         .reset_service       = hns3vf_reset_service,
2622         .stop_service        = hns3vf_stop_service,
2623         .prepare_reset       = hns3vf_prepare_reset,
2624         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2625         .reinit_dev          = hns3vf_reinit_dev,
2626         .restore_conf        = hns3vf_restore_conf,
2627         .start_service       = hns3vf_start_service,
2628 };
2629
2630 static int
2631 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2632 {
2633         struct hns3_adapter *hns = eth_dev->data->dev_private;
2634         struct hns3_hw *hw = &hns->hw;
2635         int ret;
2636
2637         PMD_INIT_FUNC_TRACE();
2638
2639         eth_dev->process_private = (struct hns3_process_private *)
2640             rte_zmalloc_socket("hns3_filter_list",
2641                                sizeof(struct hns3_process_private),
2642                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2643         if (eth_dev->process_private == NULL) {
2644                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2645                 return -ENOMEM;
2646         }
2647
2648         /* initialize flow filter lists */
2649         hns3_filterlist_init(eth_dev);
2650
2651         hns3_set_rxtx_function(eth_dev);
2652         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2653         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2654                 ret = hns3_mp_init_secondary();
2655                 if (ret) {
2656                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2657                                           "process, ret = %d", ret);
2658                         goto err_mp_init_secondary;
2659                 }
2660
2661                 hw->secondary_cnt++;
2662                 return 0;
2663         }
2664
2665         ret = hns3_mp_init_primary();
2666         if (ret) {
2667                 PMD_INIT_LOG(ERR,
2668                              "Failed to init for primary process, ret = %d",
2669                              ret);
2670                 goto err_mp_init_primary;
2671         }
2672
2673         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2674         hns->is_vf = true;
2675         hw->data = eth_dev->data;
2676
2677         ret = hns3_reset_init(hw);
2678         if (ret)
2679                 goto err_init_reset;
2680         hw->reset.ops = &hns3vf_reset_ops;
2681
2682         ret = hns3vf_init_vf(eth_dev);
2683         if (ret) {
2684                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2685                 goto err_init_vf;
2686         }
2687
2688         /* Allocate memory for storing MAC addresses */
2689         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2690                                                sizeof(struct rte_ether_addr) *
2691                                                HNS3_VF_UC_MACADDR_NUM, 0);
2692         if (eth_dev->data->mac_addrs == NULL) {
2693                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2694                              "to store MAC addresses",
2695                              sizeof(struct rte_ether_addr) *
2696                              HNS3_VF_UC_MACADDR_NUM);
2697                 ret = -ENOMEM;
2698                 goto err_rte_zmalloc;
2699         }
2700
2701         /*
2702          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2703          * on the host by "ip link set ..." command. To avoid some incorrect
2704          * scenes, for example, hns3 VF PMD driver fails to receive and send
2705          * packets after user configure the MAC address by using the
2706          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2707          * address strategy as the hns3 kernel ethdev driver in the
2708          * initialization. If user configure a MAC address by the ip command
2709          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2710          * start with a random MAC address in the initialization.
2711          */
2712         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2713                 rte_eth_random_addr(hw->mac.mac_addr);
2714         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2715                             &eth_dev->data->mac_addrs[0]);
2716
2717         hw->adapter_state = HNS3_NIC_INITIALIZED;
2718
2719         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2720                 hns3_err(hw, "Reschedule reset service after dev_init");
2721                 hns3_schedule_reset(hns);
2722         } else {
2723                 /* IMP will wait ready flag before reset */
2724                 hns3_notify_reset_ready(hw, false);
2725         }
2726         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2727                           eth_dev);
2728         return 0;
2729
2730 err_rte_zmalloc:
2731         hns3vf_uninit_vf(eth_dev);
2732
2733 err_init_vf:
2734         rte_free(hw->reset.wait_data);
2735
2736 err_init_reset:
2737         hns3_mp_uninit_primary();
2738
2739 err_mp_init_primary:
2740 err_mp_init_secondary:
2741         eth_dev->dev_ops = NULL;
2742         eth_dev->rx_pkt_burst = NULL;
2743         eth_dev->tx_pkt_burst = NULL;
2744         eth_dev->tx_pkt_prepare = NULL;
2745         rte_free(eth_dev->process_private);
2746         eth_dev->process_private = NULL;
2747
2748         return ret;
2749 }
2750
2751 static int
2752 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2753 {
2754         struct hns3_adapter *hns = eth_dev->data->dev_private;
2755         struct hns3_hw *hw = &hns->hw;
2756
2757         PMD_INIT_FUNC_TRACE();
2758
2759         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2760                 return -EPERM;
2761
2762         eth_dev->dev_ops = NULL;
2763         eth_dev->rx_pkt_burst = NULL;
2764         eth_dev->tx_pkt_burst = NULL;
2765         eth_dev->tx_pkt_prepare = NULL;
2766
2767         if (hw->adapter_state < HNS3_NIC_CLOSING)
2768                 hns3vf_dev_close(eth_dev);
2769
2770         hw->adapter_state = HNS3_NIC_REMOVED;
2771         return 0;
2772 }
2773
2774 static int
2775 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2776                      struct rte_pci_device *pci_dev)
2777 {
2778         return rte_eth_dev_pci_generic_probe(pci_dev,
2779                                              sizeof(struct hns3_adapter),
2780                                              hns3vf_dev_init);
2781 }
2782
2783 static int
2784 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2785 {
2786         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2787 }
2788
2789 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2790         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2791         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2792         { .vendor_id = 0, /* sentinel */ },
2793 };
2794
2795 static struct rte_pci_driver rte_hns3vf_pmd = {
2796         .id_table = pci_id_hns3vf_map,
2797         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2798         .probe = eth_hns3vf_pci_probe,
2799         .remove = eth_hns3vf_pci_remove,
2800 };
2801
2802 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2803 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2804 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");