drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint16_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid.
 708          */
 709         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 710         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 711                 vec = vec - 1; /* the last interrupt is reserved */
 712         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 713         for (i = 0; i < hw->intr_tqps_num; i++) {
 714                 /*
 715                  * Set gap limiter/rate limiter/quanity limiter algorithm
 716                  * configuration for interrupt coalesce of queue's interrupt.
 717                  */
 718                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 719                                        HNS3_TQP_INTR_GL_DEFAULT);
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 723                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 724
 725                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 726                                                    HNS3_RING_TYPE_TX, i);
 727                 if (ret) {
 728                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 729                                           "vector: %d, ret=%d", i, vec, ret);
 730                         return ret;
 731                 }
 732
 733                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 734                                                    HNS3_RING_TYPE_RX, i);
 735                 if (ret) {
 736                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 737                                           "vector: %d, ret=%d", i, vec, ret);
 738                         return ret;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3vf_dev_configure(struct rte_eth_dev *dev)
 747 {
 748         struct hns3_adapter *hns = dev->data->dev_private;
 749         struct hns3_hw *hw = &hns->hw;
 750         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 751         struct rte_eth_conf *conf = &dev->data->dev_conf;
 752         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 753         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 754         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 755         struct rte_eth_rss_conf rss_conf;
 756         uint16_t mtu;
 757         bool gro_en;
 758         int ret;
 759
 760         /*
 761          * Hardware does not support individually enable/disable/reset the Tx or
 762          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 763          * and Rx queues at the same time. When the numbers of Tx queues
 764          * allocated by upper applications are not equal to the numbers of Rx
 765          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 766          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 767          * these fake queues are imperceptible, and can not be used by upper
 768          * applications.
 769          */
 770         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 771         if (ret) {
 772                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 773                 return ret;
 774         }
 775
 776         hw->adapter_state = HNS3_NIC_CONFIGURING;
 777         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 778                 hns3_err(hw, "setting link speed/duplex not supported");
 779                 ret = -EINVAL;
 780                 goto cfg_err;
 781         }
 782
 783         /* When RSS is not configured, redirect the packet queue 0 */
 784         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 785                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 786                 rss_conf = conf->rx_adv_conf.rss_conf;
 787                 if (rss_conf.rss_key == NULL) {
 788                         rss_conf.rss_key = rss_cfg->key;
 789                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 790                 }
 791
 792                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 793                 if (ret)
 794                         goto cfg_err;
 795         }
 796
 797         /*
 798          * If jumbo frames are enabled, MTU needs to be refreshed
 799          * according to the maximum RX packet length.
 800          */
 801         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 802                 /*
 803                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 804                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 805                  * can safely assign to "uint16_t" type variable.
 806                  */
 807                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 808                 ret = hns3vf_dev_mtu_set(dev, mtu);
 809                 if (ret)
 810                         goto cfg_err;
 811                 dev->data->mtu = mtu;
 812         }
 813
 814         ret = hns3vf_dev_configure_vlan(dev);
 815         if (ret)
 816                 goto cfg_err;
 817
 818         /* config hardware GRO */
 819         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 820         ret = hns3_config_gro(hw, gro_en);
 821         if (ret)
 822                 goto cfg_err;
 823
 824         hns->rx_simple_allowed = true;
 825         hns->tx_simple_allowed = true;
 826         hns3_init_rx_ptype_tble(dev);
 827
 828         hw->adapter_state = HNS3_NIC_CONFIGURED;
 829         return 0;
 830
 831 cfg_err:
 832         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 833         hw->adapter_state = HNS3_NIC_INITIALIZED;
 834
 835         return ret;
 836 }
 837
 838 static int
 839 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 840 {
 841         int ret;
 842
 843         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 844                                 sizeof(mtu), true, NULL, 0);
 845         if (ret)
 846                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 847
 848         return ret;
 849 }
 850
 851 static int
 852 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 853 {
 854         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 855         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 856         int ret;
 857
 858         /*
 859          * The hns3 PF/VF devices on the same port share the hardware MTU
 860          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 861          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 862          * driver, there is no need to stop the port for hns3 VF device, and the
 863          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 864          * PF's MTU.
 865          */
 866         if (rte_atomic16_read(&hw->reset.resetting)) {
 867                 hns3_err(hw, "Failed to set mtu during resetting");
 868                 return -EIO;
 869         }
 870
 871         rte_spinlock_lock(&hw->lock);
 872         ret = hns3vf_config_mtu(hw, mtu);
 873         if (ret) {
 874                 rte_spinlock_unlock(&hw->lock);
 875                 return ret;
 876         }
 877         if (frame_size > RTE_ETHER_MAX_LEN)
 878                 dev->data->dev_conf.rxmode.offloads |=
 879                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 880         else
 881                 dev->data->dev_conf.rxmode.offloads &=
 882                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 883         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 884         rte_spinlock_unlock(&hw->lock);
 885
 886         return 0;
 887 }
 888
 889 static int
 890 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 891 {
 892         struct hns3_adapter *hns = eth_dev->data->dev_private;
 893         struct hns3_hw *hw = &hns->hw;
 894         uint16_t q_num = hw->tqps_num;
 895
 896         /*
 897          * In interrupt mode, 'max_rx_queues' is set based on the number of
 898          * MSI-X interrupt resources of the hardware.
 899          */
 900         if (hw->data->dev_conf.intr_conf.rxq == 1)
 901                 q_num = hw->intr_tqps_num;
 902
 903         info->max_rx_queues = q_num;
 904         info->max_tx_queues = hw->tqps_num;
 905         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 906         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 907         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 908         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 909         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 910
 911         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 912                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 913                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 914                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 915                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 916                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 917                                  DEV_RX_OFFLOAD_SCATTER |
 918                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 919                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 920                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 921                                  DEV_RX_OFFLOAD_RSS_HASH |
 922                                  DEV_RX_OFFLOAD_TCP_LRO);
 923         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 924                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 925                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 926                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 927                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 928                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 929                                  DEV_TX_OFFLOAD_TCP_TSO |
 930                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 931                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 932                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 933                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 934                                  hns3_txvlan_cap_get(hw));
 935
 936         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 937                 .nb_max = HNS3_MAX_RING_DESC,
 938                 .nb_min = HNS3_MIN_RING_DESC,
 939                 .nb_align = HNS3_ALIGN_RING_DESC,
 940         };
 941
 942         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 943                 .nb_max = HNS3_MAX_RING_DESC,
 944                 .nb_min = HNS3_MIN_RING_DESC,
 945                 .nb_align = HNS3_ALIGN_RING_DESC,
 946                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 947                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
 948         };
 949
 950         info->default_rxconf = (struct rte_eth_rxconf) {
 951                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 952                 /*
 953                  * If there are no available Rx buffer descriptors, incoming
 954                  * packets are always dropped by hardware based on hns3 network
 955                  * engine.
 956                  */
 957                 .rx_drop_en = 1,
 958                 .offloads = 0,
 959         };
 960         info->default_txconf = (struct rte_eth_txconf) {
 961                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 962                 .offloads = 0,
 963         };
 964
 965         info->vmdq_queue_num = 0;
 966
 967         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 968         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 969         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 970         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 971         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 972
 973         return 0;
 974 }
 975
 976 static void
 977 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 978 {
 979         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 980 }
 981
 982 static void
 983 hns3vf_disable_irq0(struct hns3_hw *hw)
 984 {
 985         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 986 }
 987
 988 static void
 989 hns3vf_enable_irq0(struct hns3_hw *hw)
 990 {
 991         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 992 }
 993
 994 static enum hns3vf_evt_cause
 995 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 996 {
 997         struct hns3_hw *hw = &hns->hw;
 998         enum hns3vf_evt_cause ret;
 999         uint32_t cmdq_stat_reg;
1000         uint32_t rst_ing_reg;
1001         uint32_t val;
1002
1003         /* Fetch the events from their corresponding regs */
1004         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1005
1006         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1007                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1008                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1009                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1010                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1011                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1012                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1013                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1014                 if (clearval) {
1015                         hw->reset.stats.global_cnt++;
1016                         hns3_warn(hw, "Global reset detected, clear reset status");
1017                 } else {
1018                         hns3_schedule_delayed_reset(hns);
1019                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1020                 }
1021
1022                 ret = HNS3VF_VECTOR0_EVENT_RST;
1023                 goto out;
1024         }
1025
1026         /* Check for vector0 mailbox(=CMDQ RX) event source */
1027         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1028                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1029                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1030                 goto out;
1031         }
1032
1033         val = 0;
1034         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1035 out:
1036         if (clearval)
1037                 *clearval = val;
1038         return ret;
1039 }
1040
1041 static void
1042 hns3vf_interrupt_handler(void *param)
1043 {
1044         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1045         struct hns3_adapter *hns = dev->data->dev_private;
1046         struct hns3_hw *hw = &hns->hw;
1047         enum hns3vf_evt_cause event_cause;
1048         uint32_t clearval;
1049
1050         if (hw->irq_thread_id == 0)
1051                 hw->irq_thread_id = pthread_self();
1052
1053         /* Disable interrupt */
1054         hns3vf_disable_irq0(hw);
1055
1056         /* Read out interrupt causes */
1057         event_cause = hns3vf_check_event_cause(hns, &clearval);
1058
1059         switch (event_cause) {
1060         case HNS3VF_VECTOR0_EVENT_RST:
1061                 hns3_schedule_reset(hns);
1062                 break;
1063         case HNS3VF_VECTOR0_EVENT_MBX:
1064                 hns3_dev_handle_mbx_msg(hw);
1065                 break;
1066         default:
1067                 break;
1068         }
1069
1070         /* Clear interrupt causes */
1071         hns3vf_clear_event_cause(hw, clearval);
1072
1073         /* Enable interrupt */
1074         hns3vf_enable_irq0(hw);
1075 }
1076
1077 static void
1078 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1079 {
1080         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1081         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1082         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1083 }
1084
1085 static void
1086 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1087 {
1088         struct hns3_dev_specs_0_cmd *req0;
1089
1090         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1091
1092         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1093         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1094         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1095 }
1096
1097 static int
1098 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1099 {
1100         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1101         int ret;
1102         int i;
1103
1104         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1105                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1106                                           true);
1107                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1108         }
1109         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1110
1111         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1112         if (ret)
1113                 return ret;
1114
1115         hns3vf_parse_dev_specifications(hw, desc);
1116
1117         return 0;
1118 }
1119
1120 static int
1121 hns3vf_get_capability(struct hns3_hw *hw)
1122 {
1123         struct rte_pci_device *pci_dev;
1124         struct rte_eth_dev *eth_dev;
1125         uint8_t revision;
1126         int ret;
1127
1128         eth_dev = &rte_eth_devices[hw->data->port_id];
1129         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1130
1131         /* Get PCI revision id */
1132         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1133                                   HNS3_PCI_REVISION_ID);
1134         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1135                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1136                              ret);
1137                 return -EIO;
1138         }
1139         hw->revision = revision;
1140
1141         if (revision < PCI_REVISION_ID_HIP09_A) {
1142                 hns3vf_set_default_dev_specifications(hw);
1143                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1144                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1145                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1146                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1147                 return 0;
1148         }
1149
1150         ret = hns3vf_query_dev_specifications(hw);
1151         if (ret) {
1152                 PMD_INIT_LOG(ERR,
1153                              "failed to query dev specifications, ret = %d",
1154                              ret);
1155                 return ret;
1156         }
1157
1158         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1159         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1160         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1161         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1162
1163         return 0;
1164 }
1165
1166 static int
1167 hns3vf_check_tqp_info(struct hns3_hw *hw)
1168 {
1169         uint16_t tqps_num;
1170
1171         tqps_num = hw->tqps_num;
1172         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1173                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1174                                   "range: 1~%d",
1175                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1176                 return -EINVAL;
1177         }
1178
1179         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1180
1181         return 0;
1182 }
1183 static int
1184 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1185 {
1186         uint8_t resp_msg;
1187         int ret;
1188
1189         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1190                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1191                                 true, &resp_msg, sizeof(resp_msg));
1192         if (ret) {
1193                 if (ret == -ETIME) {
1194                         /*
1195                          * Getting current port based VLAN state from PF driver
1196                          * will not affect VF driver's basic function. Because
1197                          * the VF driver relies on hns3 PF kernel ether driver,
1198                          * to avoid introducing compatibility issues with older
1199                          * version of PF driver, no failure will be returned
1200                          * when the return value is ETIME. This return value has
1201                          * the following scenarios:
1202                          * 1) Firmware didn't return the results in time
1203                          * 2) the result return by firmware is timeout
1204                          * 3) the older version of kernel side PF driver does
1205                          *    not support this mailbox message.
1206                          * For scenarios 1 and 2, it is most likely that a
1207                          * hardware error has occurred, or a hardware reset has
1208                          * occurred. In this case, these errors will be caught
1209                          * by other functions.
1210                          */
1211                         PMD_INIT_LOG(WARNING,
1212                                 "failed to get PVID state for timeout, maybe "
1213                                 "kernel side PF driver doesn't support this "
1214                                 "mailbox message, or firmware didn't respond.");
1215                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1216                 } else {
1217                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1218                                 " ret = %d", ret);
1219                         return ret;
1220                 }
1221         }
1222         hw->port_base_vlan_cfg.state = resp_msg ?
1223                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1224         return 0;
1225 }
1226
1227 static int
1228 hns3vf_get_queue_info(struct hns3_hw *hw)
1229 {
1230 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1231         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1232         int ret;
1233
1234         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1235                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1236         if (ret) {
1237                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1238                 return ret;
1239         }
1240
1241         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1242         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1243
1244         return hns3vf_check_tqp_info(hw);
1245 }
1246
1247 static int
1248 hns3vf_get_queue_depth(struct hns3_hw *hw)
1249 {
1250 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1251         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1252         int ret;
1253
1254         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1255                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1256         if (ret) {
1257                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1258                              ret);
1259                 return ret;
1260         }
1261
1262         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1263         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1264
1265         return 0;
1266 }
1267
1268 static int
1269 hns3vf_get_tc_info(struct hns3_hw *hw)
1270 {
1271         uint8_t resp_msg;
1272         int ret;
1273
1274         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1275                                 true, &resp_msg, sizeof(resp_msg));
1276         if (ret) {
1277                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1278                          ret);
1279                 return ret;
1280         }
1281
1282         hw->hw_tc_map = resp_msg;
1283
1284         return 0;
1285 }
1286
1287 static int
1288 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1289 {
1290         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1291         int ret;
1292
1293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1294                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1295         if (ret) {
1296                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1297                 return ret;
1298         }
1299
1300         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1301
1302         return 0;
1303 }
1304
1305 static int
1306 hns3vf_get_configuration(struct hns3_hw *hw)
1307 {
1308         int ret;
1309
1310         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1311         hw->rss_dis_flag = false;
1312
1313         /* Get device capability */
1314         ret = hns3vf_get_capability(hw);
1315         if (ret) {
1316                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1317                 return ret;
1318         }
1319
1320         /* Get queue configuration from PF */
1321         ret = hns3vf_get_queue_info(hw);
1322         if (ret)
1323                 return ret;
1324
1325         /* Get queue depth info from PF */
1326         ret = hns3vf_get_queue_depth(hw);
1327         if (ret)
1328                 return ret;
1329
1330         /* Get user defined VF MAC addr from PF */
1331         ret = hns3vf_get_host_mac_addr(hw);
1332         if (ret)
1333                 return ret;
1334
1335         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1336         if (ret)
1337                 return ret;
1338
1339         /* Get tc configuration from PF */
1340         return hns3vf_get_tc_info(hw);
1341 }
1342
1343 static int
1344 hns3vf_set_tc_info(struct hns3_adapter *hns)
1345 {
1346         struct hns3_hw *hw = &hns->hw;
1347         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1348         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1349         uint8_t i;
1350
1351         hw->num_tc = 0;
1352         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1353                 if (hw->hw_tc_map & BIT(i))
1354                         hw->num_tc++;
1355
1356         if (nb_rx_q < hw->num_tc) {
1357                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1358                          nb_rx_q, hw->num_tc);
1359                 return -EINVAL;
1360         }
1361
1362         if (nb_tx_q < hw->num_tc) {
1363                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1364                          nb_tx_q, hw->num_tc);
1365                 return -EINVAL;
1366         }
1367
1368         hns3_set_rss_size(hw, nb_rx_q);
1369         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1370
1371         return 0;
1372 }
1373
1374 static void
1375 hns3vf_request_link_info(struct hns3_hw *hw)
1376 {
1377         uint8_t resp_msg;
1378         int ret;
1379
1380         if (rte_atomic16_read(&hw->reset.resetting))
1381                 return;
1382         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1383                                 &resp_msg, sizeof(resp_msg));
1384         if (ret)
1385                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1386 }
1387
1388 static int
1389 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1390 {
1391 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1392         struct hns3_hw *hw = &hns->hw;
1393         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1394         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1395         uint8_t is_kill = on ? 0 : 1;
1396
1397         msg_data[0] = is_kill;
1398         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1399         memcpy(&msg_data[3], &proto, sizeof(proto));
1400
1401         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1402                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1403                                  0);
1404 }
1405
1406 static int
1407 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1408 {
1409         struct hns3_adapter *hns = dev->data->dev_private;
1410         struct hns3_hw *hw = &hns->hw;
1411         int ret;
1412
1413         if (rte_atomic16_read(&hw->reset.resetting)) {
1414                 hns3_err(hw,
1415                          "vf set vlan id failed during resetting, vlan_id =%u",
1416                          vlan_id);
1417                 return -EIO;
1418         }
1419         rte_spinlock_lock(&hw->lock);
1420         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1421         rte_spinlock_unlock(&hw->lock);
1422         if (ret)
1423                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1424                          vlan_id, ret);
1425
1426         return ret;
1427 }
1428
1429 static int
1430 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1431 {
1432         uint8_t msg_data;
1433         int ret;
1434
1435         msg_data = enable ? 1 : 0;
1436         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1437                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1438         if (ret)
1439                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1440
1441         return ret;
1442 }
1443
1444 static int
1445 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1446 {
1447         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1448         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1449         unsigned int tmp_mask;
1450         int ret = 0;
1451
1452         if (rte_atomic16_read(&hw->reset.resetting)) {
1453                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1454                              "mask = 0x%x", mask);
1455                 return -EIO;
1456         }
1457
1458         tmp_mask = (unsigned int)mask;
1459         /* Vlan stripping setting */
1460         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1461                 rte_spinlock_lock(&hw->lock);
1462                 /* Enable or disable VLAN stripping */
1463                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1464                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1465                 else
1466                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1467                 rte_spinlock_unlock(&hw->lock);
1468         }
1469
1470         return ret;
1471 }
1472
1473 static int
1474 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1475 {
1476         struct rte_vlan_filter_conf *vfc;
1477         struct hns3_hw *hw = &hns->hw;
1478         uint16_t vlan_id;
1479         uint64_t vbit;
1480         uint64_t ids;
1481         int ret = 0;
1482         uint32_t i;
1483
1484         vfc = &hw->data->vlan_filter_conf;
1485         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1486                 if (vfc->ids[i] == 0)
1487                         continue;
1488                 ids = vfc->ids[i];
1489                 while (ids) {
1490                         /*
1491                          * 64 means the num bits of ids, one bit corresponds to
1492                          * one vlan id
1493                          */
1494                         vlan_id = 64 * i;
1495                         /* count trailing zeroes */
1496                         vbit = ~ids & (ids - 1);
1497                         /* clear least significant bit set */
1498                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1499                         for (; vbit;) {
1500                                 vbit >>= 1;
1501                                 vlan_id++;
1502                         }
1503                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1504                         if (ret) {
1505                                 hns3_err(hw,
1506                                          "VF handle vlan table failed, ret =%d, on = %d",
1507                                          ret, on);
1508                                 return ret;
1509                         }
1510                 }
1511         }
1512
1513         return ret;
1514 }
1515
1516 static int
1517 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1518 {
1519         return hns3vf_handle_all_vlan_table(hns, 0);
1520 }
1521
1522 static int
1523 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1524 {
1525         struct hns3_hw *hw = &hns->hw;
1526         struct rte_eth_conf *dev_conf;
1527         bool en;
1528         int ret;
1529
1530         dev_conf = &hw->data->dev_conf;
1531         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1532                                                                    : false;
1533         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1534         if (ret)
1535                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1536                          ret);
1537         return ret;
1538 }
1539
1540 static int
1541 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1542 {
1543         struct hns3_adapter *hns = dev->data->dev_private;
1544         struct rte_eth_dev_data *data = dev->data;
1545         struct hns3_hw *hw = &hns->hw;
1546         int ret;
1547
1548         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1549             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1550             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1551                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1552                               "or hw_vlan_insert_pvid is not support!");
1553         }
1554
1555         /* Apply vlan offload setting */
1556         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1557         if (ret)
1558                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1559
1560         return ret;
1561 }
1562
1563 static int
1564 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1565 {
1566         uint8_t msg_data;
1567
1568         msg_data = alive ? 1 : 0;
1569         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1570                                  sizeof(msg_data), false, NULL, 0);
1571 }
1572
1573 static void
1574 hns3vf_keep_alive_handler(void *param)
1575 {
1576         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1577         struct hns3_adapter *hns = eth_dev->data->dev_private;
1578         struct hns3_hw *hw = &hns->hw;
1579         uint8_t respmsg;
1580         int ret;
1581
1582         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1583                                 false, &respmsg, sizeof(uint8_t));
1584         if (ret)
1585                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1586                          ret);
1587
1588         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1589                           eth_dev);
1590 }
1591
1592 static void
1593 hns3vf_service_handler(void *param)
1594 {
1595         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1596         struct hns3_adapter *hns = eth_dev->data->dev_private;
1597         struct hns3_hw *hw = &hns->hw;
1598
1599         /*
1600          * The query link status and reset processing are executed in the
1601          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1602          * and the query operation will time out after 30ms. In the case of
1603          * multiple PF/VFs, each query failure timeout causes the IMP reset
1604          * interrupt to fail to respond within 100ms.
1605          * Before querying the link status, check whether there is a reset
1606          * pending, and if so, abandon the query.
1607          */
1608         if (!hns3vf_is_reset_pending(hns))
1609                 hns3vf_request_link_info(hw);
1610         else
1611                 hns3_warn(hw, "Cancel the query when reset is pending");
1612
1613         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1614                           eth_dev);
1615 }
1616
1617 static int
1618 hns3_query_vf_resource(struct hns3_hw *hw)
1619 {
1620         struct hns3_vf_res_cmd *req;
1621         struct hns3_cmd_desc desc;
1622         uint16_t num_msi;
1623         int ret;
1624
1625         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1626         ret = hns3_cmd_send(hw, &desc, 1);
1627         if (ret) {
1628                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1629                 return ret;
1630         }
1631
1632         req = (struct hns3_vf_res_cmd *)desc.data;
1633         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1634                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1635         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1636                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1637                          num_msi, HNS3_MIN_VECTOR_NUM);
1638                 return -EINVAL;
1639         }
1640
1641         hw->num_msi = num_msi;
1642
1643         return 0;
1644 }
1645
1646 static int
1647 hns3vf_init_hardware(struct hns3_adapter *hns)
1648 {
1649         struct hns3_hw *hw = &hns->hw;
1650         uint16_t mtu = hw->data->mtu;
1651         int ret;
1652
1653         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1654         if (ret)
1655                 return ret;
1656
1657         ret = hns3vf_config_mtu(hw, mtu);
1658         if (ret)
1659                 goto err_init_hardware;
1660
1661         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1662         if (ret) {
1663                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1664                 goto err_init_hardware;
1665         }
1666
1667         ret = hns3_config_gro(hw, false);
1668         if (ret) {
1669                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1670                 goto err_init_hardware;
1671         }
1672
1673         /*
1674          * In the initialization clearing the all hardware mapping relationship
1675          * configurations between queues and interrupt vectors is needed, so
1676          * some error caused by the residual configurations, such as the
1677          * unexpected interrupt, can be avoid.
1678          */
1679         ret = hns3vf_init_ring_with_vector(hw);
1680         if (ret) {
1681                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1682                 goto err_init_hardware;
1683         }
1684
1685         ret = hns3vf_set_alive(hw, true);
1686         if (ret) {
1687                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1688                 goto err_init_hardware;
1689         }
1690
1691         hns3vf_request_link_info(hw);
1692         return 0;
1693
1694 err_init_hardware:
1695         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1696         return ret;
1697 }
1698
1699 static int
1700 hns3vf_clear_vport_list(struct hns3_hw *hw)
1701 {
1702         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1703                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1704                                  NULL, 0);
1705 }
1706
1707 static int
1708 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1709 {
1710         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1711         struct hns3_adapter *hns = eth_dev->data->dev_private;
1712         struct hns3_hw *hw = &hns->hw;
1713         int ret;
1714
1715         PMD_INIT_FUNC_TRACE();
1716
1717         /* Get hardware io base address from pcie BAR2 IO space */
1718         hw->io_base = pci_dev->mem_resource[2].addr;
1719
1720         /* Firmware command queue initialize */
1721         ret = hns3_cmd_init_queue(hw);
1722         if (ret) {
1723                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1724                 goto err_cmd_init_queue;
1725         }
1726
1727         /* Firmware command initialize */
1728         ret = hns3_cmd_init(hw);
1729         if (ret) {
1730                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1731                 goto err_cmd_init;
1732         }
1733
1734         /* Get VF resource */
1735         ret = hns3_query_vf_resource(hw);
1736         if (ret)
1737                 goto err_cmd_init;
1738
1739         rte_spinlock_init(&hw->mbx_resp.lock);
1740
1741         hns3vf_clear_event_cause(hw, 0);
1742
1743         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1744                                          hns3vf_interrupt_handler, eth_dev);
1745         if (ret) {
1746                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1747                 goto err_intr_callback_register;
1748         }
1749
1750         /* Enable interrupt */
1751         rte_intr_enable(&pci_dev->intr_handle);
1752         hns3vf_enable_irq0(hw);
1753
1754         /* Get configuration from PF */
1755         ret = hns3vf_get_configuration(hw);
1756         if (ret) {
1757                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1758                 goto err_get_config;
1759         }
1760
1761         ret = hns3vf_clear_vport_list(hw);
1762         if (ret) {
1763                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1764                 goto err_get_config;
1765         }
1766
1767         ret = hns3vf_init_hardware(hns);
1768         if (ret)
1769                 goto err_get_config;
1770
1771         hns3_set_default_rss_args(hw);
1772
1773         return 0;
1774
1775 err_get_config:
1776         hns3vf_disable_irq0(hw);
1777         rte_intr_disable(&pci_dev->intr_handle);
1778         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1779                              eth_dev);
1780 err_intr_callback_register:
1781 err_cmd_init:
1782         hns3_cmd_uninit(hw);
1783         hns3_cmd_destroy_queue(hw);
1784 err_cmd_init_queue:
1785         hw->io_base = NULL;
1786
1787         return ret;
1788 }
1789
1790 static void
1791 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1792 {
1793         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1794         struct hns3_adapter *hns = eth_dev->data->dev_private;
1795         struct hns3_hw *hw = &hns->hw;
1796
1797         PMD_INIT_FUNC_TRACE();
1798
1799         hns3_rss_uninit(hns);
1800         (void)hns3_config_gro(hw, false);
1801         (void)hns3vf_set_alive(hw, false);
1802         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1803         hns3vf_disable_irq0(hw);
1804         rte_intr_disable(&pci_dev->intr_handle);
1805         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1806                              eth_dev);
1807         hns3_cmd_uninit(hw);
1808         hns3_cmd_destroy_queue(hw);
1809         hw->io_base = NULL;
1810 }
1811
1812 static int
1813 hns3vf_do_stop(struct hns3_adapter *hns)
1814 {
1815         struct hns3_hw *hw = &hns->hw;
1816         bool reset_queue;
1817
1818         hw->mac.link_status = ETH_LINK_DOWN;
1819
1820         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1821                 hns3vf_configure_mac_addr(hns, true);
1822                 reset_queue = true;
1823         } else
1824                 reset_queue = false;
1825         return hns3_stop_queues(hns, reset_queue);
1826 }
1827
1828 static void
1829 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1830 {
1831         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1833         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1834         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1835         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1836         uint16_t q_id;
1837
1838         if (dev->data->dev_conf.intr_conf.rxq == 0)
1839                 return;
1840
1841         /* unmap the ring with vector */
1842         if (rte_intr_allow_others(intr_handle)) {
1843                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1844                 base = RTE_INTR_VEC_RXTX_OFFSET;
1845         }
1846         if (rte_intr_dp_is_en(intr_handle)) {
1847                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1848                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1849                                                            HNS3_RING_TYPE_RX,
1850                                                            q_id);
1851                         if (vec < base + intr_handle->nb_efd - 1)
1852                                 vec++;
1853                 }
1854         }
1855         /* Clean datapath event and queue/vec mapping */
1856         rte_intr_efd_disable(intr_handle);
1857         if (intr_handle->intr_vec) {
1858                 rte_free(intr_handle->intr_vec);
1859                 intr_handle->intr_vec = NULL;
1860         }
1861 }
1862
1863 static void
1864 hns3vf_dev_stop(struct rte_eth_dev *dev)
1865 {
1866         struct hns3_adapter *hns = dev->data->dev_private;
1867         struct hns3_hw *hw = &hns->hw;
1868
1869         PMD_INIT_FUNC_TRACE();
1870
1871         hw->adapter_state = HNS3_NIC_STOPPING;
1872         hns3_set_rxtx_function(dev);
1873         rte_wmb();
1874         /* Disable datapath on secondary process. */
1875         hns3_mp_req_stop_rxtx(dev);
1876         /* Prevent crashes when queues are still in use. */
1877         rte_delay_ms(hw->tqps_num);
1878
1879         rte_spinlock_lock(&hw->lock);
1880         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1881                 hns3vf_do_stop(hns);
1882                 hns3vf_unmap_rx_interrupt(dev);
1883                 hns3_dev_release_mbufs(hns);
1884                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1885         }
1886         hns3_rx_scattered_reset(dev);
1887         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1888         rte_spinlock_unlock(&hw->lock);
1889 }
1890
1891 static void
1892 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1893 {
1894         struct hns3_adapter *hns = eth_dev->data->dev_private;
1895         struct hns3_hw *hw = &hns->hw;
1896
1897         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1898                 return;
1899
1900         if (hw->adapter_state == HNS3_NIC_STARTED)
1901                 hns3vf_dev_stop(eth_dev);
1902
1903         hw->adapter_state = HNS3_NIC_CLOSING;
1904         hns3_reset_abort(hns);
1905         hw->adapter_state = HNS3_NIC_CLOSED;
1906         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1907         hns3vf_configure_all_mc_mac_addr(hns, true);
1908         hns3vf_remove_all_vlan_table(hns);
1909         hns3vf_uninit_vf(eth_dev);
1910         hns3_free_all_queues(eth_dev);
1911         rte_free(hw->reset.wait_data);
1912         rte_free(eth_dev->process_private);
1913         eth_dev->process_private = NULL;
1914         hns3_mp_uninit_primary();
1915         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1916 }
1917
1918 static int
1919 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1920                       size_t fw_size)
1921 {
1922         struct hns3_adapter *hns = eth_dev->data->dev_private;
1923         struct hns3_hw *hw = &hns->hw;
1924         uint32_t version = hw->fw_version;
1925         int ret;
1926
1927         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1928                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1929                                       HNS3_FW_VERSION_BYTE3_S),
1930                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1931                                       HNS3_FW_VERSION_BYTE2_S),
1932                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1933                                       HNS3_FW_VERSION_BYTE1_S),
1934                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1935                                       HNS3_FW_VERSION_BYTE0_S));
1936         ret += 1; /* add the size of '\0' */
1937         if (fw_size < (uint32_t)ret)
1938                 return ret;
1939         else
1940                 return 0;
1941 }
1942
1943 static int
1944 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1945                        __rte_unused int wait_to_complete)
1946 {
1947         struct hns3_adapter *hns = eth_dev->data->dev_private;
1948         struct hns3_hw *hw = &hns->hw;
1949         struct hns3_mac *mac = &hw->mac;
1950         struct rte_eth_link new_link;
1951
1952         memset(&new_link, 0, sizeof(new_link));
1953         switch (mac->link_speed) {
1954         case ETH_SPEED_NUM_10M:
1955         case ETH_SPEED_NUM_100M:
1956         case ETH_SPEED_NUM_1G:
1957         case ETH_SPEED_NUM_10G:
1958         case ETH_SPEED_NUM_25G:
1959         case ETH_SPEED_NUM_40G:
1960         case ETH_SPEED_NUM_50G:
1961         case ETH_SPEED_NUM_100G:
1962         case ETH_SPEED_NUM_200G:
1963                 new_link.link_speed = mac->link_speed;
1964                 break;
1965         default:
1966                 new_link.link_speed = ETH_SPEED_NUM_100M;
1967                 break;
1968         }
1969
1970         new_link.link_duplex = mac->link_duplex;
1971         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1972         new_link.link_autoneg =
1973             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1974
1975         return rte_eth_linkstatus_set(eth_dev, &new_link);
1976 }
1977
1978 static int
1979 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1980 {
1981         struct hns3_hw *hw = &hns->hw;
1982         int ret;
1983
1984         ret = hns3vf_set_tc_info(hns);
1985         if (ret)
1986                 return ret;
1987
1988         ret = hns3_start_queues(hns, reset_queue);
1989         if (ret)
1990                 hns3_err(hw, "Failed to start queues: %d", ret);
1991
1992         return ret;
1993 }
1994
1995 static int
1996 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1997 {
1998         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1999         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2000         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2002         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2003         uint32_t intr_vector;
2004         uint16_t q_id;
2005         int ret;
2006
2007         if (dev->data->dev_conf.intr_conf.rxq == 0)
2008                 return 0;
2009
2010         /* disable uio/vfio intr/eventfd mapping */
2011         rte_intr_disable(intr_handle);
2012
2013         /* check and configure queue intr-vector mapping */
2014         if (rte_intr_cap_multiple(intr_handle) ||
2015             !RTE_ETH_DEV_SRIOV(dev).active) {
2016                 intr_vector = hw->used_rx_queues;
2017                 /* It creates event fd for each intr vector when MSIX is used */
2018                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2019                         return -EINVAL;
2020         }
2021         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2022                 intr_handle->intr_vec =
2023                         rte_zmalloc("intr_vec",
2024                                     hw->used_rx_queues * sizeof(int), 0);
2025                 if (intr_handle->intr_vec == NULL) {
2026                         hns3_err(hw, "Failed to allocate %d rx_queues"
2027                                      " intr_vec", hw->used_rx_queues);
2028                         ret = -ENOMEM;
2029                         goto vf_alloc_intr_vec_error;
2030                 }
2031         }
2032
2033         if (rte_intr_allow_others(intr_handle)) {
2034                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2035                 base = RTE_INTR_VEC_RXTX_OFFSET;
2036         }
2037         if (rte_intr_dp_is_en(intr_handle)) {
2038                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2039                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2040                                                            HNS3_RING_TYPE_RX,
2041                                                            q_id);
2042                         if (ret)
2043                                 goto vf_bind_vector_error;
2044                         intr_handle->intr_vec[q_id] = vec;
2045                         if (vec < base + intr_handle->nb_efd - 1)
2046                                 vec++;
2047                 }
2048         }
2049         rte_intr_enable(intr_handle);
2050         return 0;
2051
2052 vf_bind_vector_error:
2053         rte_intr_efd_disable(intr_handle);
2054         if (intr_handle->intr_vec) {
2055                 free(intr_handle->intr_vec);
2056                 intr_handle->intr_vec = NULL;
2057         }
2058         return ret;
2059 vf_alloc_intr_vec_error:
2060         rte_intr_efd_disable(intr_handle);
2061         return ret;
2062 }
2063
2064 static int
2065 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2066 {
2067         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2068         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2069         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2070         uint16_t q_id;
2071         int ret;
2072
2073         if (dev->data->dev_conf.intr_conf.rxq == 0)
2074                 return 0;
2075
2076         if (rte_intr_dp_is_en(intr_handle)) {
2077                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2078                         ret = hns3vf_bind_ring_with_vector(hw,
2079                                         intr_handle->intr_vec[q_id], true,
2080                                         HNS3_RING_TYPE_RX, q_id);
2081                         if (ret)
2082                                 return ret;
2083                 }
2084         }
2085
2086         return 0;
2087 }
2088
2089 static void
2090 hns3vf_restore_filter(struct rte_eth_dev *dev)
2091 {
2092         hns3_restore_rss_filter(dev);
2093 }
2094
2095 static int
2096 hns3vf_dev_start(struct rte_eth_dev *dev)
2097 {
2098         struct hns3_adapter *hns = dev->data->dev_private;
2099         struct hns3_hw *hw = &hns->hw;
2100         int ret;
2101
2102         PMD_INIT_FUNC_TRACE();
2103         if (rte_atomic16_read(&hw->reset.resetting))
2104                 return -EBUSY;
2105
2106         rte_spinlock_lock(&hw->lock);
2107         hw->adapter_state = HNS3_NIC_STARTING;
2108         ret = hns3vf_do_start(hns, true);
2109         if (ret) {
2110                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2111                 rte_spinlock_unlock(&hw->lock);
2112                 return ret;
2113         }
2114         ret = hns3vf_map_rx_interrupt(dev);
2115         if (ret) {
2116                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2117                 rte_spinlock_unlock(&hw->lock);
2118                 return ret;
2119         }
2120         hw->adapter_state = HNS3_NIC_STARTED;
2121         rte_spinlock_unlock(&hw->lock);
2122
2123         hns3_rx_scattered_calc(dev);
2124         hns3_set_rxtx_function(dev);
2125         hns3_mp_req_start_rxtx(dev);
2126         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2127
2128         hns3vf_restore_filter(dev);
2129
2130         /* Enable interrupt of all rx queues before enabling queues */
2131         hns3_dev_all_rx_queue_intr_enable(hw, true);
2132         /*
2133          * When finished the initialization, enable queues to receive/transmit
2134          * packets.
2135          */
2136         hns3_enable_all_queues(hw, true);
2137
2138         return ret;
2139 }
2140
2141 static bool
2142 is_vf_reset_done(struct hns3_hw *hw)
2143 {
2144 #define HNS3_FUN_RST_ING_BITS \
2145         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2146          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2147          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2148          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2149
2150         uint32_t val;
2151
2152         if (hw->reset.level == HNS3_VF_RESET) {
2153                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2154                 if (val & HNS3_VF_RST_ING_BIT)
2155                         return false;
2156         } else {
2157                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2158                 if (val & HNS3_FUN_RST_ING_BITS)
2159                         return false;
2160         }
2161         return true;
2162 }
2163
2164 bool
2165 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2166 {
2167         struct hns3_hw *hw = &hns->hw;
2168         enum hns3_reset_level reset;
2169
2170         hns3vf_check_event_cause(hns, NULL);
2171         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2172         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2173                 hns3_warn(hw, "High level reset %d is pending", reset);
2174                 return true;
2175         }
2176         return false;
2177 }
2178
2179 static int
2180 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2181 {
2182         struct hns3_hw *hw = &hns->hw;
2183         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2184         struct timeval tv;
2185
2186         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2187                 /*
2188                  * After vf reset is ready, the PF may not have completed
2189                  * the reset processing. The vf sending mbox to PF may fail
2190                  * during the pf reset, so it is better to add extra delay.
2191                  */
2192                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2193                     hw->reset.level == HNS3_FLR_RESET)
2194                         return 0;
2195                 /* Reset retry process, no need to add extra delay. */
2196                 if (hw->reset.attempts)
2197                         return 0;
2198                 if (wait_data->check_completion == NULL)
2199                         return 0;
2200
2201                 wait_data->check_completion = NULL;
2202                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2203                 wait_data->count = 1;
2204                 wait_data->result = HNS3_WAIT_REQUEST;
2205                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2206                                   wait_data);
2207                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2208                 return -EAGAIN;
2209         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2210                 gettimeofday(&tv, NULL);
2211                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2212                           tv.tv_sec, tv.tv_usec);
2213                 return -ETIME;
2214         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2215                 return -EAGAIN;
2216
2217         wait_data->hns = hns;
2218         wait_data->check_completion = is_vf_reset_done;
2219         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2220                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2221         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2222         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2223         wait_data->result = HNS3_WAIT_REQUEST;
2224         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2225         return -EAGAIN;
2226 }
2227
2228 static int
2229 hns3vf_prepare_reset(struct hns3_adapter *hns)
2230 {
2231         struct hns3_hw *hw = &hns->hw;
2232         int ret = 0;
2233
2234         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2235                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2236                                         0, true, NULL, 0);
2237         }
2238         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2239
2240         return ret;
2241 }
2242
2243 static int
2244 hns3vf_stop_service(struct hns3_adapter *hns)
2245 {
2246         struct hns3_hw *hw = &hns->hw;
2247         struct rte_eth_dev *eth_dev;
2248
2249         eth_dev = &rte_eth_devices[hw->data->port_id];
2250         if (hw->adapter_state == HNS3_NIC_STARTED)
2251                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2252         hw->mac.link_status = ETH_LINK_DOWN;
2253
2254         hns3_set_rxtx_function(eth_dev);
2255         rte_wmb();
2256         /* Disable datapath on secondary process. */
2257         hns3_mp_req_stop_rxtx(eth_dev);
2258         rte_delay_ms(hw->tqps_num);
2259
2260         rte_spinlock_lock(&hw->lock);
2261         if (hw->adapter_state == HNS3_NIC_STARTED ||
2262             hw->adapter_state == HNS3_NIC_STOPPING) {
2263                 hns3vf_do_stop(hns);
2264                 hw->reset.mbuf_deferred_free = true;
2265         } else
2266                 hw->reset.mbuf_deferred_free = false;
2267
2268         /*
2269          * It is cumbersome for hardware to pick-and-choose entries for deletion
2270          * from table space. Hence, for function reset software intervention is
2271          * required to delete the entries.
2272          */
2273         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2274                 hns3vf_configure_all_mc_mac_addr(hns, true);
2275         rte_spinlock_unlock(&hw->lock);
2276
2277         return 0;
2278 }
2279
2280 static int
2281 hns3vf_start_service(struct hns3_adapter *hns)
2282 {
2283         struct hns3_hw *hw = &hns->hw;
2284         struct rte_eth_dev *eth_dev;
2285
2286         eth_dev = &rte_eth_devices[hw->data->port_id];
2287         hns3_set_rxtx_function(eth_dev);
2288         hns3_mp_req_start_rxtx(eth_dev);
2289         if (hw->adapter_state == HNS3_NIC_STARTED) {
2290                 hns3vf_service_handler(eth_dev);
2291
2292                 /* Enable interrupt of all rx queues before enabling queues */
2293                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2294                 /*
2295                  * When finished the initialization, enable queues to receive
2296                  * and transmit packets.
2297                  */
2298                 hns3_enable_all_queues(hw, true);
2299         }
2300
2301         return 0;
2302 }
2303
2304 static int
2305 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2306 {
2307         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2308         struct rte_ether_addr *hw_mac;
2309         int ret;
2310
2311         /*
2312          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2313          * on the host by "ip link set ..." command. If the hns3 PF kernel
2314          * ethdev driver sets the MAC address for VF device after the
2315          * initialization of the related VF device, the PF driver will notify
2316          * VF driver to reset VF device to make the new MAC address effective
2317          * immediately. The hns3 VF PMD driver should check whether the MAC
2318          * address has been changed by the PF kernel ethdev driver, if changed
2319          * VF driver should configure hardware using the new MAC address in the
2320          * recovering hardware configuration stage of the reset process.
2321          */
2322         ret = hns3vf_get_host_mac_addr(hw);
2323         if (ret)
2324                 return ret;
2325
2326         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2327         ret = rte_is_zero_ether_addr(hw_mac);
2328         if (ret) {
2329                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2330         } else {
2331                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2332                 if (!ret) {
2333                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2334                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2335                                               &hw->data->mac_addrs[0]);
2336                         hns3_warn(hw, "Default MAC address has been changed to:"
2337                                   " %s by the host PF kernel ethdev driver",
2338                                   mac_str);
2339                 }
2340         }
2341
2342         return 0;
2343 }
2344
2345 static int
2346 hns3vf_restore_conf(struct hns3_adapter *hns)
2347 {
2348         struct hns3_hw *hw = &hns->hw;
2349         int ret;
2350
2351         ret = hns3vf_check_default_mac_change(hw);
2352         if (ret)
2353                 return ret;
2354
2355         ret = hns3vf_configure_mac_addr(hns, false);
2356         if (ret)
2357                 return ret;
2358
2359         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2360         if (ret)
2361                 goto err_mc_mac;
2362
2363         ret = hns3vf_restore_promisc(hns);
2364         if (ret)
2365                 goto err_vlan_table;
2366
2367         ret = hns3vf_restore_vlan_conf(hns);
2368         if (ret)
2369                 goto err_vlan_table;
2370
2371         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2372         if (ret)
2373                 goto err_vlan_table;
2374
2375         ret = hns3vf_restore_rx_interrupt(hw);
2376         if (ret)
2377                 goto err_vlan_table;
2378
2379         ret = hns3_restore_gro_conf(hw);
2380         if (ret)
2381                 goto err_vlan_table;
2382
2383         if (hw->adapter_state == HNS3_NIC_STARTED) {
2384                 ret = hns3vf_do_start(hns, false);
2385                 if (ret)
2386                         goto err_vlan_table;
2387                 hns3_info(hw, "hns3vf dev restart successful!");
2388         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2389                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2390         return 0;
2391
2392 err_vlan_table:
2393         hns3vf_configure_all_mc_mac_addr(hns, true);
2394 err_mc_mac:
2395         hns3vf_configure_mac_addr(hns, true);
2396         return ret;
2397 }
2398
2399 static enum hns3_reset_level
2400 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2401 {
2402         enum hns3_reset_level reset_level;
2403
2404         /* return the highest priority reset level amongst all */
2405         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2406                 reset_level = HNS3_VF_RESET;
2407         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2408                 reset_level = HNS3_VF_FULL_RESET;
2409         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2410                 reset_level = HNS3_VF_PF_FUNC_RESET;
2411         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2412                 reset_level = HNS3_VF_FUNC_RESET;
2413         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2414                 reset_level = HNS3_FLR_RESET;
2415         else
2416                 reset_level = HNS3_NONE_RESET;
2417
2418         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2419                 return HNS3_NONE_RESET;
2420
2421         return reset_level;
2422 }
2423
2424 static void
2425 hns3vf_reset_service(void *param)
2426 {
2427         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2428         struct hns3_hw *hw = &hns->hw;
2429         enum hns3_reset_level reset_level;
2430         struct timeval tv_delta;
2431         struct timeval tv_start;
2432         struct timeval tv;
2433         uint64_t msec;
2434
2435         /*
2436          * The interrupt is not triggered within the delay time.
2437          * The interrupt may have been lost. It is necessary to handle
2438          * the interrupt to recover from the error.
2439          */
2440         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2441                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2442                 hns3_err(hw, "Handling interrupts in delayed tasks");
2443                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2444                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2445                 if (reset_level == HNS3_NONE_RESET) {
2446                         hns3_err(hw, "No reset level is set, try global reset");
2447                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2448                 }
2449         }
2450         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2451
2452         /*
2453          * Hardware reset has been notified, we now have to poll & check if
2454          * hardware has actually completed the reset sequence.
2455          */
2456         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2457         if (reset_level != HNS3_NONE_RESET) {
2458                 gettimeofday(&tv_start, NULL);
2459                 hns3_reset_process(hns, reset_level);
2460                 gettimeofday(&tv, NULL);
2461                 timersub(&tv, &tv_start, &tv_delta);
2462                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2463                        tv_delta.tv_usec / USEC_PER_MSEC;
2464                 if (msec > HNS3_RESET_PROCESS_MS)
2465                         hns3_err(hw, "%d handle long time delta %" PRIx64
2466                                  " ms time=%ld.%.6ld",
2467                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2468         }
2469 }
2470
2471 static int
2472 hns3vf_reinit_dev(struct hns3_adapter *hns)
2473 {
2474         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2476         struct hns3_hw *hw = &hns->hw;
2477         int ret;
2478
2479         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2480                 rte_intr_disable(&pci_dev->intr_handle);
2481                 hns3vf_set_bus_master(pci_dev, true);
2482         }
2483
2484         /* Firmware command initialize */
2485         ret = hns3_cmd_init(hw);
2486         if (ret) {
2487                 hns3_err(hw, "Failed to init cmd: %d", ret);
2488                 return ret;
2489         }
2490
2491         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2492                 /*
2493                  * UIO enables msix by writing the pcie configuration space
2494                  * vfio_pci enables msix in rte_intr_enable.
2495                  */
2496                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2497                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2498                         if (hns3vf_enable_msix(pci_dev, true))
2499                                 hns3_err(hw, "Failed to enable msix");
2500                 }
2501
2502                 rte_intr_enable(&pci_dev->intr_handle);
2503         }
2504
2505         ret = hns3_reset_all_queues(hns);
2506         if (ret) {
2507                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2508                 return ret;
2509         }
2510
2511         ret = hns3vf_init_hardware(hns);
2512         if (ret) {
2513                 hns3_err(hw, "Failed to init hardware: %d", ret);
2514                 return ret;
2515         }
2516
2517         return 0;
2518 }
2519
2520 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2521         .dev_configure      = hns3vf_dev_configure,
2522         .dev_start          = hns3vf_dev_start,
2523         .dev_stop           = hns3vf_dev_stop,
2524         .dev_close          = hns3vf_dev_close,
2525         .mtu_set            = hns3vf_dev_mtu_set,
2526         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2527         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2528         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2529         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2530         .stats_get          = hns3_stats_get,
2531         .stats_reset        = hns3_stats_reset,
2532         .xstats_get         = hns3_dev_xstats_get,
2533         .xstats_get_names   = hns3_dev_xstats_get_names,
2534         .xstats_reset       = hns3_dev_xstats_reset,
2535         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2536         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2537         .dev_infos_get      = hns3vf_dev_infos_get,
2538         .fw_version_get     = hns3vf_fw_version_get,
2539         .rx_queue_setup     = hns3_rx_queue_setup,
2540         .tx_queue_setup     = hns3_tx_queue_setup,
2541         .rx_queue_release   = hns3_dev_rx_queue_release,
2542         .tx_queue_release   = hns3_dev_tx_queue_release,
2543         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2544         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2545         .rxq_info_get       = hns3_rxq_info_get,
2546         .txq_info_get       = hns3_txq_info_get,
2547         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2548         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2549         .mac_addr_add       = hns3vf_add_mac_addr,
2550         .mac_addr_remove    = hns3vf_remove_mac_addr,
2551         .mac_addr_set       = hns3vf_set_default_mac_addr,
2552         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2553         .link_update        = hns3vf_dev_link_update,
2554         .rss_hash_update    = hns3_dev_rss_hash_update,
2555         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2556         .reta_update        = hns3_dev_rss_reta_update,
2557         .reta_query         = hns3_dev_rss_reta_query,
2558         .filter_ctrl        = hns3_dev_filter_ctrl,
2559         .vlan_filter_set    = hns3vf_vlan_filter_set,
2560         .vlan_offload_set   = hns3vf_vlan_offload_set,
2561         .get_reg            = hns3_get_regs,
2562         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2563 };
2564
2565 static const struct hns3_reset_ops hns3vf_reset_ops = {
2566         .reset_service       = hns3vf_reset_service,
2567         .stop_service        = hns3vf_stop_service,
2568         .prepare_reset       = hns3vf_prepare_reset,
2569         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2570         .reinit_dev          = hns3vf_reinit_dev,
2571         .restore_conf        = hns3vf_restore_conf,
2572         .start_service       = hns3vf_start_service,
2573 };
2574
2575 static int
2576 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2577 {
2578         struct hns3_adapter *hns = eth_dev->data->dev_private;
2579         struct hns3_hw *hw = &hns->hw;
2580         int ret;
2581
2582         PMD_INIT_FUNC_TRACE();
2583
2584         eth_dev->process_private = (struct hns3_process_private *)
2585             rte_zmalloc_socket("hns3_filter_list",
2586                                sizeof(struct hns3_process_private),
2587                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2588         if (eth_dev->process_private == NULL) {
2589                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2590                 return -ENOMEM;
2591         }
2592
2593         /* initialize flow filter lists */
2594         hns3_filterlist_init(eth_dev);
2595
2596         hns3_set_rxtx_function(eth_dev);
2597         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2598         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2599                 ret = hns3_mp_init_secondary();
2600                 if (ret) {
2601                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2602                                           "process, ret = %d", ret);
2603                         goto err_mp_init_secondary;
2604                 }
2605
2606                 hw->secondary_cnt++;
2607                 return 0;
2608         }
2609
2610         ret = hns3_mp_init_primary();
2611         if (ret) {
2612                 PMD_INIT_LOG(ERR,
2613                              "Failed to init for primary process, ret = %d",
2614                              ret);
2615                 goto err_mp_init_primary;
2616         }
2617
2618         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2619         hns->is_vf = true;
2620         hw->data = eth_dev->data;
2621
2622         ret = hns3_reset_init(hw);
2623         if (ret)
2624                 goto err_init_reset;
2625         hw->reset.ops = &hns3vf_reset_ops;
2626
2627         ret = hns3vf_init_vf(eth_dev);
2628         if (ret) {
2629                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2630                 goto err_init_vf;
2631         }
2632
2633         /* Allocate memory for storing MAC addresses */
2634         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2635                                                sizeof(struct rte_ether_addr) *
2636                                                HNS3_VF_UC_MACADDR_NUM, 0);
2637         if (eth_dev->data->mac_addrs == NULL) {
2638                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2639                              "to store MAC addresses",
2640                              sizeof(struct rte_ether_addr) *
2641                              HNS3_VF_UC_MACADDR_NUM);
2642                 ret = -ENOMEM;
2643                 goto err_rte_zmalloc;
2644         }
2645
2646         /*
2647          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2648          * on the host by "ip link set ..." command. To avoid some incorrect
2649          * scenes, for example, hns3 VF PMD driver fails to receive and send
2650          * packets after user configure the MAC address by using the
2651          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2652          * address strategy as the hns3 kernel ethdev driver in the
2653          * initialization. If user configure a MAC address by the ip command
2654          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2655          * start with a random MAC address in the initialization.
2656          */
2657         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2658                 rte_eth_random_addr(hw->mac.mac_addr);
2659         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2660                             &eth_dev->data->mac_addrs[0]);
2661
2662         hw->adapter_state = HNS3_NIC_INITIALIZED;
2663         /*
2664          * Pass the information to the rte_eth_dev_close() that it should also
2665          * release the private port resources.
2666          */
2667         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2668
2669         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2670                 hns3_err(hw, "Reschedule reset service after dev_init");
2671                 hns3_schedule_reset(hns);
2672         } else {
2673                 /* IMP will wait ready flag before reset */
2674                 hns3_notify_reset_ready(hw, false);
2675         }
2676         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2677                           eth_dev);
2678         return 0;
2679
2680 err_rte_zmalloc:
2681         hns3vf_uninit_vf(eth_dev);
2682
2683 err_init_vf:
2684         rte_free(hw->reset.wait_data);
2685
2686 err_init_reset:
2687         hns3_mp_uninit_primary();
2688
2689 err_mp_init_primary:
2690 err_mp_init_secondary:
2691         eth_dev->dev_ops = NULL;
2692         eth_dev->rx_pkt_burst = NULL;
2693         eth_dev->tx_pkt_burst = NULL;
2694         eth_dev->tx_pkt_prepare = NULL;
2695         rte_free(eth_dev->process_private);
2696         eth_dev->process_private = NULL;
2697
2698         return ret;
2699 }
2700
2701 static int
2702 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2703 {
2704         struct hns3_adapter *hns = eth_dev->data->dev_private;
2705         struct hns3_hw *hw = &hns->hw;
2706
2707         PMD_INIT_FUNC_TRACE();
2708
2709         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2710                 return -EPERM;
2711
2712         eth_dev->dev_ops = NULL;
2713         eth_dev->rx_pkt_burst = NULL;
2714         eth_dev->tx_pkt_burst = NULL;
2715         eth_dev->tx_pkt_prepare = NULL;
2716
2717         if (hw->adapter_state < HNS3_NIC_CLOSING)
2718                 hns3vf_dev_close(eth_dev);
2719
2720         hw->adapter_state = HNS3_NIC_REMOVED;
2721         return 0;
2722 }
2723
2724 static int
2725 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2726                      struct rte_pci_device *pci_dev)
2727 {
2728         return rte_eth_dev_pci_generic_probe(pci_dev,
2729                                              sizeof(struct hns3_adapter),
2730                                              hns3vf_dev_init);
2731 }
2732
2733 static int
2734 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2735 {
2736         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2737 }
2738
2739 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2740         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2741         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2742         { .vendor_id = 0, /* sentinel */ },
2743 };
2744
2745 static struct rte_pci_driver rte_hns3vf_pmd = {
2746         .id_table = pci_id_hns3vf_map,
2747         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2748         .probe = eth_hns3vf_pci_probe,
2749         .remove = eth_hns3vf_pci_remove,
2750 };
2751
2752 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2753 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2754 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");