drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 /* set PCI bus mastering */
  63 static void
  64 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  65 {
  66         uint16_t reg;
  67
  68         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  69
  70         if (op)
  71                 /* set the master bit */
  72                 reg |= PCI_COMMAND_MASTER;
  73         else
  74                 reg &= ~(PCI_COMMAND_MASTER);
  75
  76         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  77 }
  78
  79 /**
  80  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  81  * @cap: the capability
  82  *
  83  * Return the address of the given capability within the PCI capability list.
  84  */
  85 static int
  86 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  87 {
  88 #define MAX_PCIE_CAPABILITY 48
  89         uint16_t status;
  90         uint8_t pos;
  91         uint8_t id;
  92         int ttl;
  93
  94         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 100         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 101                 rte_pci_read_config(device, &id, sizeof(id),
 102                                     (pos + PCI_CAP_LIST_ID));
 103
 104                 if (id == 0xFF)
 105                         break;
 106
 107                 if (id == cap)
 108                         return (int)pos;
 109
 110                 rte_pci_read_config(device, &pos, sizeof(pos),
 111                                     (pos + PCI_CAP_LIST_NEXT));
 112         }
 113         return 0;
 114 }
 115
 116 static int
 117 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 118 {
 119         uint16_t control;
 120         int pos;
 121
 122         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 123         if (pos) {
 124                 rte_pci_read_config(device, &control, sizeof(control),
 125                                     (pos + PCI_MSIX_FLAGS));
 126                 if (op)
 127                         control |= PCI_MSIX_FLAGS_ENABLE;
 128                 else
 129                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 130                 rte_pci_write_config(device, &control, sizeof(control),
 131                                      (pos + PCI_MSIX_FLAGS));
 132                 return 0;
 133         }
 134         return -ENXIO;
 135 }
 136
 137 static int
 138 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 139                     __rte_unused uint32_t idx,
 140                     __rte_unused uint32_t pool)
 141 {
 142         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 143         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 144         int ret;
 145
 146         rte_spinlock_lock(&hw->lock);
 147         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 148                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 149                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 150         rte_spinlock_unlock(&hw->lock);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "Failed to add mac addr(%s) for vf: %d", mac_str,
 155                          ret);
 156         }
 157
 158         return ret;
 159 }
 160
 161 static void
 162 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 163 {
 164         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 165         /* index will be checked by upper level rte interface */
 166         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 167         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 168         int ret;
 169
 170         rte_spinlock_lock(&hw->lock);
 171         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 172                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 173                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 174                                 NULL, 0);
 175         rte_spinlock_unlock(&hw->lock);
 176         if (ret) {
 177                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 178                                       mac_addr);
 179                 hns3_err(hw, "Failed to remove mac addr(%s) for vf: %d",
 180                          mac_str, ret);
 181         }
 182 }
 183
 184 static int
 185 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 186                             struct rte_ether_addr *mac_addr)
 187 {
 188 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 189         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 190         struct rte_ether_addr *old_addr;
 191         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 192         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 193         int ret;
 194
 195         /*
 196          * It has been guaranteed that input parameter named mac_addr is valid
 197          * address in the rte layer of DPDK framework.
 198          */
 199         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 200         rte_spinlock_lock(&hw->lock);
 201         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 202         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 203                RTE_ETHER_ADDR_LEN);
 204
 205         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 206                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 207                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 208         if (ret) {
 209                 /*
 210                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 211                  * driver. When user has configured a MAC address for VF device
 212                  * by "ip link set ..." command based on the PF device, the hns3
 213                  * PF kernel ethdev driver does not allow VF driver to request
 214                  * reconfiguring a different default MAC address, and return
 215                  * -EPREM to VF driver through mailbox.
 216                  */
 217                 if (ret == -EPERM) {
 218                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 219                                               old_addr);
 220                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 221                                   mac_str);
 222                 } else {
 223                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 224                                               mac_addr);
 225                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 226                                  mac_str, ret);
 227                 }
 228         }
 229
 230         rte_ether_addr_copy(mac_addr,
 231                             (struct rte_ether_addr *)hw->mac.mac_addr);
 232         rte_spinlock_unlock(&hw->lock);
 233
 234         return ret;
 235 }
 236
 237 static int
 238 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 239 {
 240         struct hns3_hw *hw = &hns->hw;
 241         struct rte_ether_addr *addr;
 242         enum hns3_mbx_mac_vlan_subcode opcode;
 243         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 244         int ret = 0;
 245         int i;
 246
 247         if (del)
 248                 opcode = HNS3_MBX_MAC_VLAN_UC_REMOVE;
 249         else
 250                 opcode = HNS3_MBX_MAC_VLAN_UC_ADD;
 251         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 252                 addr = &hw->data->mac_addrs[i];
 253                 if (!rte_is_valid_assigned_ether_addr(addr))
 254                         continue;
 255                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 256                 hns3_dbg(hw, "rm mac addr: %s", mac_str);
 257                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, opcode,
 258                                         addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 259                                         false, NULL, 0);
 260                 if (ret) {
 261                         hns3_err(hw, "Failed to remove mac addr for vf: %d",
 262                                  ret);
 263                         break;
 264                 }
 265         }
 266         return ret;
 267 }
 268
 269 static int
 270 hns3vf_add_mc_mac_addr(struct hns3_adapter *hns,
 271                        struct rte_ether_addr *mac_addr)
 272 {
 273         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 274         struct hns3_hw *hw = &hns->hw;
 275         int ret;
 276
 277         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 278                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 279                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 280                                 NULL, 0);
 281         if (ret) {
 282                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 283                                       mac_addr);
 284                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 285                          mac_str, ret);
 286                 return ret;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int
 293 hns3vf_remove_mc_mac_addr(struct hns3_adapter *hns,
 294                           struct rte_ether_addr *mac_addr)
 295 {
 296         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 297         struct hns3_hw *hw = &hns->hw;
 298         int ret;
 299
 300         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 301                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 302                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 303                                 NULL, 0);
 304         if (ret) {
 305                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 306                                       mac_addr);
 307                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 308                          mac_str, ret);
 309                 return ret;
 310         }
 311
 312         return 0;
 313 }
 314
 315 static int
 316 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 317                             struct rte_ether_addr *mc_addr_set,
 318                             uint32_t nb_mc_addr)
 319 {
 320         struct hns3_adapter *hns = dev->data->dev_private;
 321         struct hns3_hw *hw = &hns->hw;
 322         struct rte_ether_addr *addr;
 323         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 324         int cur_addr_num;
 325         int set_addr_num;
 326         int num;
 327         int ret;
 328         int i;
 329
 330         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 331                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 332                          "invalid. valid range: 0~%d",
 333                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 334                 return -EINVAL;
 335         }
 336
 337         set_addr_num = (int)nb_mc_addr;
 338         for (i = 0; i < set_addr_num; i++) {
 339                 addr = &mc_addr_set[i];
 340                 if (!rte_is_multicast_ether_addr(addr)) {
 341                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 342                                               addr);
 343                         hns3_err(hw,
 344                                  "Failed to set mc mac addr, addr(%s) invalid.",
 345                                  mac_str);
 346                         return -EINVAL;
 347                 }
 348         }
 349         rte_spinlock_lock(&hw->lock);
 350         cur_addr_num = hw->mc_addrs_num;
 351         for (i = 0; i < cur_addr_num; i++) {
 352                 num = cur_addr_num - i - 1;
 353                 addr = &hw->mc_addrs[num];
 354                 ret = hns3vf_remove_mc_mac_addr(hns, addr);
 355                 if (ret) {
 356                         rte_spinlock_unlock(&hw->lock);
 357                         return ret;
 358                 }
 359
 360                 hw->mc_addrs_num--;
 361         }
 362
 363         for (i = 0; i < set_addr_num; i++) {
 364                 addr = &mc_addr_set[i];
 365                 ret = hns3vf_add_mc_mac_addr(hns, addr);
 366                 if (ret) {
 367                         rte_spinlock_unlock(&hw->lock);
 368                         return ret;
 369                 }
 370
 371                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 372                 hw->mc_addrs_num++;
 373         }
 374         rte_spinlock_unlock(&hw->lock);
 375
 376         return 0;
 377 }
 378
 379 static int
 380 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 381 {
 382         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 383         struct hns3_hw *hw = &hns->hw;
 384         struct rte_ether_addr *addr;
 385         int err = 0;
 386         int ret;
 387         int i;
 388
 389         for (i = 0; i < hw->mc_addrs_num; i++) {
 390                 addr = &hw->mc_addrs[i];
 391                 if (!rte_is_multicast_ether_addr(addr))
 392                         continue;
 393                 if (del)
 394                         ret = hns3vf_remove_mc_mac_addr(hns, addr);
 395                 else
 396                         ret = hns3vf_add_mc_mac_addr(hns, addr);
 397                 if (ret) {
 398                         err = ret;
 399                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 400                                               addr);
 401                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 402                                  del ? "Remove" : "Restore", mac_str, ret);
 403                 }
 404         }
 405         return err;
 406 }
 407
 408 static int
 409 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 410                         bool en_uc_pmc, bool en_mc_pmc)
 411 {
 412         struct hns3_mbx_vf_to_pf_cmd *req;
 413         struct hns3_cmd_desc desc;
 414         int ret;
 415
 416         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 417
 418         /*
 419          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 420          * so there are some features for promiscuous/allmulticast mode in hns3
 421          * VF PMD driver as below:
 422          * 1. The promiscuous/allmulticast mode can be configured successfully
 423          *    only based on the trusted VF device. If based on the non trusted
 424          *    VF device, configuring promiscuous/allmulticast mode will fail.
 425          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 426          *    kernel ethdev driver on the host by the following command:
 427          *      "ip link set <eth num> vf <vf id> turst on"
 428          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 429          *    driver can receive the ingress and outgoing traffic. In the words,
 430          *    all the ingress packets, all the packets sent from the PF and
 431          *    other VFs on the same physical port.
 432          * 3. Note: Because of the hardware constraints, By default vlan filter
 433          *    is enabled and couldn't be turned off based on VF device, so vlan
 434          *    filter is still effective even in promiscuous mode. If upper
 435          *    applications don't call rte_eth_dev_vlan_filter API function to
 436          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 437          *    the packets with vlan tag in promiscuoue mode.
 438          */
 439         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 440         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 441         req->msg[1] = en_bc_pmc ? 1 : 0;
 442         req->msg[2] = en_uc_pmc ? 1 : 0;
 443         req->msg[3] = en_mc_pmc ? 1 : 0;
 444
 445         ret = hns3_cmd_send(hw, &desc, 1);
 446         if (ret)
 447                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 448
 449         return ret;
 450 }
 451
 452 static int
 453 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 454 {
 455         struct hns3_adapter *hns = dev->data->dev_private;
 456         struct hns3_hw *hw = &hns->hw;
 457         int ret;
 458
 459         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 460         if (ret)
 461                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 462                         ret);
 463         return ret;
 464 }
 465
 466 static int
 467 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 468 {
 469         bool allmulti = dev->data->all_multicast ? true : false;
 470         struct hns3_adapter *hns = dev->data->dev_private;
 471         struct hns3_hw *hw = &hns->hw;
 472         int ret;
 473
 474         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 475         if (ret)
 476                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 477                         ret);
 478         return ret;
 479 }
 480
 481 static int
 482 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 483 {
 484         struct hns3_adapter *hns = dev->data->dev_private;
 485         struct hns3_hw *hw = &hns->hw;
 486         int ret;
 487
 488         if (dev->data->promiscuous)
 489                 return 0;
 490
 491         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 492         if (ret)
 493                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 494                         ret);
 495         return ret;
 496 }
 497
 498 static int
 499 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 500 {
 501         struct hns3_adapter *hns = dev->data->dev_private;
 502         struct hns3_hw *hw = &hns->hw;
 503         int ret;
 504
 505         if (dev->data->promiscuous)
 506                 return 0;
 507
 508         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 509         if (ret)
 510                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 511                         ret);
 512         return ret;
 513 }
 514
 515 static int
 516 hns3vf_restore_promisc(struct hns3_adapter *hns)
 517 {
 518         struct hns3_hw *hw = &hns->hw;
 519         bool allmulti = hw->data->all_multicast ? true : false;
 520
 521         if (hw->data->promiscuous)
 522                 return hns3vf_set_promisc_mode(hw, true, true, true);
 523
 524         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 525 }
 526
 527 static int
 528 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 529                              bool mmap, enum hns3_ring_type queue_type,
 530                              uint16_t queue_id)
 531 {
 532         struct hns3_vf_bind_vector_msg bind_msg;
 533         const char *op_str;
 534         uint16_t code;
 535         int ret;
 536
 537         memset(&bind_msg, 0, sizeof(bind_msg));
 538         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 539                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 540         bind_msg.vector_id = vector_id;
 541
 542         if (queue_type == HNS3_RING_TYPE_RX)
 543                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 544         else
 545                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 546
 547         bind_msg.param[0].ring_type = queue_type;
 548         bind_msg.ring_num = 1;
 549         bind_msg.param[0].tqp_index = queue_id;
 550         op_str = mmap ? "Map" : "Unmap";
 551         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 552                                 sizeof(bind_msg), false, NULL, 0);
 553         if (ret) {
 554                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 555                          op_str, queue_id, bind_msg.vector_id, ret);
 556                 return ret;
 557         }
 558
 559         return 0;
 560 }
 561
 562 static int
 563 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 564 {
 565         uint8_t vec;
 566         int ret;
 567         int i;
 568
 569         /*
 570          * In hns3 network engine, vector 0 is always the misc interrupt of this
 571          * function, vector 1~N can be used respectively for the queues of the
 572          * function. Tx and Rx queues with the same number share the interrupt
 573          * vector. In the initialization clearing the all hardware mapping
 574          * relationship configurations between queues and interrupt vectors is
 575          * needed, so some error caused by the residual configurations, such as
 576          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 577          * constraints in hns3 hardware engine, we have to implement clearing
 578          * the mapping relationship configurations by binding all queues to the
 579          * last interrupt vector and reserving the last interrupt vector. This
 580          * method results in a decrease of the maximum queues when upper
 581          * applications call the rte_eth_dev_configure API function to enable
 582          * Rx interrupt.
 583          */
 584         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 585         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
 586         for (i = 0; i < hw->intr_tqps_num; i++) {
 587                 /*
 588                  * Set gap limiter and rate limiter configuration of queue's
 589                  * interrupt.
 590                  */
 591                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 592                                        HNS3_TQP_INTR_GL_DEFAULT);
 593                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 594                                        HNS3_TQP_INTR_GL_DEFAULT);
 595                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 596
 597                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 598                                                    HNS3_RING_TYPE_TX, i);
 599                 if (ret) {
 600                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 601                                           "vector: %d, ret=%d", i, vec, ret);
 602                         return ret;
 603                 }
 604
 605                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 606                                                    HNS3_RING_TYPE_RX, i);
 607                 if (ret) {
 608                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 609                                           "vector: %d, ret=%d", i, vec, ret);
 610                         return ret;
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 static int
 618 hns3vf_dev_configure(struct rte_eth_dev *dev)
 619 {
 620         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 621         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 622         struct rte_eth_conf *conf = &dev->data->dev_conf;
 623         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 624         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 625         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 626         struct rte_eth_rss_conf rss_conf;
 627         uint16_t mtu;
 628         int ret;
 629
 630         /*
 631          * Hardware does not support individually enable/disable/reset the Tx or
 632          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 633          * and Rx queues at the same time. When the numbers of Tx queues
 634          * allocated by upper applications are not equal to the numbers of Rx
 635          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 636          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 637          * these fake queues are imperceptible, and can not be used by upper
 638          * applications.
 639          */
 640         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 641         if (ret) {
 642                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 643                 return ret;
 644         }
 645
 646         hw->adapter_state = HNS3_NIC_CONFIGURING;
 647         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 648                 hns3_err(hw, "setting link speed/duplex not supported");
 649                 ret = -EINVAL;
 650                 goto cfg_err;
 651         }
 652
 653         /* When RSS is not configured, redirect the packet queue 0 */
 654         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 655                 rss_conf = conf->rx_adv_conf.rss_conf;
 656                 if (rss_conf.rss_key == NULL) {
 657                         rss_conf.rss_key = rss_cfg->key;
 658                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 659                 }
 660
 661                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 662                 if (ret)
 663                         goto cfg_err;
 664         }
 665
 666         /*
 667          * If jumbo frames are enabled, MTU needs to be refreshed
 668          * according to the maximum RX packet length.
 669          */
 670         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 671                 /*
 672                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 673                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 674                  * can safely assign to "uint16_t" type variable.
 675                  */
 676                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 677                 ret = hns3vf_dev_mtu_set(dev, mtu);
 678                 if (ret)
 679                         goto cfg_err;
 680                 dev->data->mtu = mtu;
 681         }
 682
 683         ret = hns3vf_dev_configure_vlan(dev);
 684         if (ret)
 685                 goto cfg_err;
 686
 687         hw->adapter_state = HNS3_NIC_CONFIGURED;
 688         return 0;
 689
 690 cfg_err:
 691         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 692         hw->adapter_state = HNS3_NIC_INITIALIZED;
 693
 694         return ret;
 695 }
 696
 697 static int
 698 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 699 {
 700         int ret;
 701
 702         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 703                                 sizeof(mtu), true, NULL, 0);
 704         if (ret)
 705                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 706
 707         return ret;
 708 }
 709
 710 static int
 711 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 712 {
 713         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 714         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 715         int ret;
 716
 717         /*
 718          * The hns3 PF/VF devices on the same port share the hardware MTU
 719          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 720          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 721          * driver, there is no need to stop the port for hns3 VF device, and the
 722          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 723          * PF's MTU.
 724          */
 725         if (rte_atomic16_read(&hw->reset.resetting)) {
 726                 hns3_err(hw, "Failed to set mtu during resetting");
 727                 return -EIO;
 728         }
 729
 730         rte_spinlock_lock(&hw->lock);
 731         ret = hns3vf_config_mtu(hw, mtu);
 732         if (ret) {
 733                 rte_spinlock_unlock(&hw->lock);
 734                 return ret;
 735         }
 736         if (frame_size > RTE_ETHER_MAX_LEN)
 737                 dev->data->dev_conf.rxmode.offloads |=
 738                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 739         else
 740                 dev->data->dev_conf.rxmode.offloads &=
 741                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 742         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 743         rte_spinlock_unlock(&hw->lock);
 744
 745         return 0;
 746 }
 747
 748 static int
 749 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 750 {
 751         struct hns3_adapter *hns = eth_dev->data->dev_private;
 752         struct hns3_hw *hw = &hns->hw;
 753         uint16_t q_num = hw->tqps_num;
 754
 755         /*
 756          * In interrupt mode, 'max_rx_queues' is set based on the number of
 757          * MSI-X interrupt resources of the hardware.
 758          */
 759         if (hw->data->dev_conf.intr_conf.rxq == 1)
 760                 q_num = hw->intr_tqps_num;
 761
 762         info->max_rx_queues = q_num;
 763         info->max_tx_queues = hw->tqps_num;
 764         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 765         info->min_rx_bufsize = hw->rx_buf_len;
 766         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 767         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 768
 769         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 770                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 771                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 772                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 773                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 774                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 775                                  DEV_RX_OFFLOAD_KEEP_CRC |
 776                                  DEV_RX_OFFLOAD_SCATTER |
 777                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 778                                  DEV_RX_OFFLOAD_QINQ_STRIP |
 779                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 780                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
 781         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 782         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 783                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 784                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 785                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 786                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 787                                  DEV_TX_OFFLOAD_VLAN_INSERT |
 788                                  DEV_TX_OFFLOAD_QINQ_INSERT |
 789                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 790                                  DEV_TX_OFFLOAD_TCP_TSO |
 791                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 792                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 793                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 794                                  info->tx_queue_offload_capa);
 795
 796         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 797                 .nb_max = HNS3_MAX_RING_DESC,
 798                 .nb_min = HNS3_MIN_RING_DESC,
 799                 .nb_align = HNS3_ALIGN_RING_DESC,
 800         };
 801
 802         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 803                 .nb_max = HNS3_MAX_RING_DESC,
 804                 .nb_min = HNS3_MIN_RING_DESC,
 805                 .nb_align = HNS3_ALIGN_RING_DESC,
 806         };
 807
 808         info->vmdq_queue_num = 0;
 809
 810         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 811         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 812         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 813         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 814         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 815
 816         return 0;
 817 }
 818
 819 static void
 820 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 821 {
 822         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 823 }
 824
 825 static void
 826 hns3vf_disable_irq0(struct hns3_hw *hw)
 827 {
 828         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 829 }
 830
 831 static void
 832 hns3vf_enable_irq0(struct hns3_hw *hw)
 833 {
 834         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 835 }
 836
 837 static enum hns3vf_evt_cause
 838 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 839 {
 840         struct hns3_hw *hw = &hns->hw;
 841         enum hns3vf_evt_cause ret;
 842         uint32_t cmdq_stat_reg;
 843         uint32_t rst_ing_reg;
 844         uint32_t val;
 845
 846         /* Fetch the events from their corresponding regs */
 847         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 848
 849         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 850                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 851                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 852                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 853                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 854                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 855                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 856                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 857                 if (clearval) {
 858                         hw->reset.stats.global_cnt++;
 859                         hns3_warn(hw, "Global reset detected, clear reset status");
 860                 } else {
 861                         hns3_schedule_delayed_reset(hns);
 862                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 863                 }
 864
 865                 ret = HNS3VF_VECTOR0_EVENT_RST;
 866                 goto out;
 867         }
 868
 869         /* Check for vector0 mailbox(=CMDQ RX) event source */
 870         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 871                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 872                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 873                 goto out;
 874         }
 875
 876         val = 0;
 877         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 878 out:
 879         if (clearval)
 880                 *clearval = val;
 881         return ret;
 882 }
 883
 884 static void
 885 hns3vf_interrupt_handler(void *param)
 886 {
 887         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 888         struct hns3_adapter *hns = dev->data->dev_private;
 889         struct hns3_hw *hw = &hns->hw;
 890         enum hns3vf_evt_cause event_cause;
 891         uint32_t clearval;
 892
 893         if (hw->irq_thread_id == 0)
 894                 hw->irq_thread_id = pthread_self();
 895
 896         /* Disable interrupt */
 897         hns3vf_disable_irq0(hw);
 898
 899         /* Read out interrupt causes */
 900         event_cause = hns3vf_check_event_cause(hns, &clearval);
 901
 902         switch (event_cause) {
 903         case HNS3VF_VECTOR0_EVENT_RST:
 904                 hns3_schedule_reset(hns);
 905                 break;
 906         case HNS3VF_VECTOR0_EVENT_MBX:
 907                 hns3_dev_handle_mbx_msg(hw);
 908                 break;
 909         default:
 910                 break;
 911         }
 912
 913         /* Clear interrupt causes */
 914         hns3vf_clear_event_cause(hw, clearval);
 915
 916         /* Enable interrupt */
 917         hns3vf_enable_irq0(hw);
 918 }
 919
 920 static int
 921 hns3vf_check_tqp_info(struct hns3_hw *hw)
 922 {
 923         uint16_t tqps_num;
 924
 925         tqps_num = hw->tqps_num;
 926         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
 927                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
 928                                   "range: 1~%d",
 929                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
 930                 return -EINVAL;
 931         }
 932
 933         if (hw->rx_buf_len == 0)
 934                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
 935         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
 936
 937         return 0;
 938 }
 939
 940 static int
 941 hns3vf_get_queue_info(struct hns3_hw *hw)
 942 {
 943 #define HNS3VF_TQPS_RSS_INFO_LEN        6
 944         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
 945         int ret;
 946
 947         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
 948                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
 949         if (ret) {
 950                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
 951                 return ret;
 952         }
 953
 954         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
 955         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
 956         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
 957
 958         return hns3vf_check_tqp_info(hw);
 959 }
 960
 961 static int
 962 hns3vf_get_queue_depth(struct hns3_hw *hw)
 963 {
 964 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
 965         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
 966         int ret;
 967
 968         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
 969                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
 970         if (ret) {
 971                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
 972                              ret);
 973                 return ret;
 974         }
 975
 976         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
 977         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
 978
 979         return 0;
 980 }
 981
 982 static int
 983 hns3vf_get_tc_info(struct hns3_hw *hw)
 984 {
 985         uint8_t resp_msg;
 986         int ret;
 987
 988         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
 989                                 true, &resp_msg, sizeof(resp_msg));
 990         if (ret) {
 991                 hns3_err(hw, "VF request to get TC info from PF failed %d",
 992                          ret);
 993                 return ret;
 994         }
 995
 996         hw->hw_tc_map = resp_msg;
 997
 998         return 0;
 999 }
1000
1001 static int
1002 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1003 {
1004         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1005         int ret;
1006
1007         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1008                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1009         if (ret) {
1010                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1011                 return ret;
1012         }
1013
1014         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1015
1016         return 0;
1017 }
1018
1019 static int
1020 hns3vf_get_configuration(struct hns3_hw *hw)
1021 {
1022         int ret;
1023
1024         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1025
1026         /* Get queue configuration from PF */
1027         ret = hns3vf_get_queue_info(hw);
1028         if (ret)
1029                 return ret;
1030
1031         /* Get queue depth info from PF */
1032         ret = hns3vf_get_queue_depth(hw);
1033         if (ret)
1034                 return ret;
1035
1036         /* Get user defined VF MAC addr from PF */
1037         ret = hns3vf_get_host_mac_addr(hw);
1038         if (ret)
1039                 return ret;
1040
1041         /* Get tc configuration from PF */
1042         return hns3vf_get_tc_info(hw);
1043 }
1044
1045 static int
1046 hns3vf_set_tc_info(struct hns3_adapter *hns)
1047 {
1048         struct hns3_hw *hw = &hns->hw;
1049         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1050         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1051         uint8_t i;
1052
1053         hw->num_tc = 0;
1054         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1055                 if (hw->hw_tc_map & BIT(i))
1056                         hw->num_tc++;
1057
1058         if (nb_rx_q < hw->num_tc) {
1059                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1060                          nb_rx_q, hw->num_tc);
1061                 return -EINVAL;
1062         }
1063
1064         if (nb_tx_q < hw->num_tc) {
1065                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1066                          nb_tx_q, hw->num_tc);
1067                 return -EINVAL;
1068         }
1069
1070         hns3_set_rss_size(hw, nb_rx_q);
1071         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1072
1073         return 0;
1074 }
1075
1076 static void
1077 hns3vf_request_link_info(struct hns3_hw *hw)
1078 {
1079         uint8_t resp_msg;
1080         int ret;
1081
1082         if (rte_atomic16_read(&hw->reset.resetting))
1083                 return;
1084         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1085                                 &resp_msg, sizeof(resp_msg));
1086         if (ret)
1087                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1088 }
1089
1090 static int
1091 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1092 {
1093 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1094         struct hns3_hw *hw = &hns->hw;
1095         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1096         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1097         uint8_t is_kill = on ? 0 : 1;
1098
1099         msg_data[0] = is_kill;
1100         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1101         memcpy(&msg_data[3], &proto, sizeof(proto));
1102
1103         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1104                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1105                                  0);
1106 }
1107
1108 static int
1109 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1110 {
1111         struct hns3_adapter *hns = dev->data->dev_private;
1112         struct hns3_hw *hw = &hns->hw;
1113         int ret;
1114
1115         if (rte_atomic16_read(&hw->reset.resetting)) {
1116                 hns3_err(hw,
1117                          "vf set vlan id failed during resetting, vlan_id =%u",
1118                          vlan_id);
1119                 return -EIO;
1120         }
1121         rte_spinlock_lock(&hw->lock);
1122         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1123         rte_spinlock_unlock(&hw->lock);
1124         if (ret)
1125                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1126                          vlan_id, ret);
1127
1128         return ret;
1129 }
1130
1131 static int
1132 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1133 {
1134         uint8_t msg_data;
1135         int ret;
1136
1137         msg_data = enable ? 1 : 0;
1138         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1139                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1140         if (ret)
1141                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1142
1143         return ret;
1144 }
1145
1146 static int
1147 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1148 {
1149         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1150         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1151         unsigned int tmp_mask;
1152
1153         tmp_mask = (unsigned int)mask;
1154         /* Vlan stripping setting */
1155         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1156                 rte_spinlock_lock(&hw->lock);
1157                 /* Enable or disable VLAN stripping */
1158                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1159                         hns3vf_en_hw_strip_rxvtag(hw, true);
1160                 else
1161                         hns3vf_en_hw_strip_rxvtag(hw, false);
1162                 rte_spinlock_unlock(&hw->lock);
1163         }
1164
1165         return 0;
1166 }
1167
1168 static int
1169 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1170 {
1171         struct rte_vlan_filter_conf *vfc;
1172         struct hns3_hw *hw = &hns->hw;
1173         uint16_t vlan_id;
1174         uint64_t vbit;
1175         uint64_t ids;
1176         int ret = 0;
1177         uint32_t i;
1178
1179         vfc = &hw->data->vlan_filter_conf;
1180         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1181                 if (vfc->ids[i] == 0)
1182                         continue;
1183                 ids = vfc->ids[i];
1184                 while (ids) {
1185                         /*
1186                          * 64 means the num bits of ids, one bit corresponds to
1187                          * one vlan id
1188                          */
1189                         vlan_id = 64 * i;
1190                         /* count trailing zeroes */
1191                         vbit = ~ids & (ids - 1);
1192                         /* clear least significant bit set */
1193                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1194                         for (; vbit;) {
1195                                 vbit >>= 1;
1196                                 vlan_id++;
1197                         }
1198                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1199                         if (ret) {
1200                                 hns3_err(hw,
1201                                          "VF handle vlan table failed, ret =%d, on = %d",
1202                                          ret, on);
1203                                 return ret;
1204                         }
1205                 }
1206         }
1207
1208         return ret;
1209 }
1210
1211 static int
1212 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1213 {
1214         return hns3vf_handle_all_vlan_table(hns, 0);
1215 }
1216
1217 static int
1218 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1219 {
1220         struct hns3_hw *hw = &hns->hw;
1221         struct rte_eth_conf *dev_conf;
1222         bool en;
1223         int ret;
1224
1225         dev_conf = &hw->data->dev_conf;
1226         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1227                                                                    : false;
1228         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1229         if (ret)
1230                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1231                          ret);
1232         return ret;
1233 }
1234
1235 static int
1236 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1237 {
1238         struct hns3_adapter *hns = dev->data->dev_private;
1239         struct rte_eth_dev_data *data = dev->data;
1240         struct hns3_hw *hw = &hns->hw;
1241         int ret;
1242
1243         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1244             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1245             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1246                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1247                               "or hw_vlan_insert_pvid is not support!");
1248         }
1249
1250         /* Apply vlan offload setting */
1251         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1252         if (ret)
1253                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1254
1255         return ret;
1256 }
1257
1258 static int
1259 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1260 {
1261         uint8_t msg_data;
1262
1263         msg_data = alive ? 1 : 0;
1264         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1265                                  sizeof(msg_data), false, NULL, 0);
1266 }
1267
1268 static void
1269 hns3vf_keep_alive_handler(void *param)
1270 {
1271         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1272         struct hns3_adapter *hns = eth_dev->data->dev_private;
1273         struct hns3_hw *hw = &hns->hw;
1274         uint8_t respmsg;
1275         int ret;
1276
1277         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1278                                 false, &respmsg, sizeof(uint8_t));
1279         if (ret)
1280                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1281                          ret);
1282
1283         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1284                           eth_dev);
1285 }
1286
1287 static void
1288 hns3vf_service_handler(void *param)
1289 {
1290         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1291         struct hns3_adapter *hns = eth_dev->data->dev_private;
1292         struct hns3_hw *hw = &hns->hw;
1293
1294         /*
1295          * The query link status and reset processing are executed in the
1296          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1297          * and the query operation will time out after 30ms. In the case of
1298          * multiple PF/VFs, each query failure timeout causes the IMP reset
1299          * interrupt to fail to respond within 100ms.
1300          * Before querying the link status, check whether there is a reset
1301          * pending, and if so, abandon the query.
1302          */
1303         if (!hns3vf_is_reset_pending(hns))
1304                 hns3vf_request_link_info(hw);
1305         else
1306                 hns3_warn(hw, "Cancel the query when reset is pending");
1307
1308         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1309                           eth_dev);
1310 }
1311
1312 static int
1313 hns3_query_vf_resource(struct hns3_hw *hw)
1314 {
1315         struct hns3_vf_res_cmd *req;
1316         struct hns3_cmd_desc desc;
1317         uint16_t num_msi;
1318         int ret;
1319
1320         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1321         ret = hns3_cmd_send(hw, &desc, 1);
1322         if (ret) {
1323                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1324                 return ret;
1325         }
1326
1327         req = (struct hns3_vf_res_cmd *)desc.data;
1328         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1329                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1330         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1331                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1332                          num_msi, HNS3_MIN_VECTOR_NUM);
1333                 return -EINVAL;
1334         }
1335
1336         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
1337
1338         return 0;
1339 }
1340
1341 static int
1342 hns3vf_init_hardware(struct hns3_adapter *hns)
1343 {
1344         struct hns3_hw *hw = &hns->hw;
1345         uint16_t mtu = hw->data->mtu;
1346         int ret;
1347
1348         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1349         if (ret)
1350                 return ret;
1351
1352         ret = hns3vf_config_mtu(hw, mtu);
1353         if (ret)
1354                 goto err_init_hardware;
1355
1356         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1357         if (ret) {
1358                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1359                 goto err_init_hardware;
1360         }
1361
1362         ret = hns3_config_gro(hw, false);
1363         if (ret) {
1364                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1365                 goto err_init_hardware;
1366         }
1367
1368         ret = hns3vf_set_alive(hw, true);
1369         if (ret) {
1370                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1371                 goto err_init_hardware;
1372         }
1373
1374         hns3vf_request_link_info(hw);
1375         return 0;
1376
1377 err_init_hardware:
1378         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1379         return ret;
1380 }
1381
1382 static int
1383 hns3vf_clear_vport_list(struct hns3_hw *hw)
1384 {
1385         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1386                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1387                                  NULL, 0);
1388 }
1389
1390 static int
1391 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1392 {
1393         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1394         struct hns3_adapter *hns = eth_dev->data->dev_private;
1395         struct hns3_hw *hw = &hns->hw;
1396         int ret;
1397
1398         PMD_INIT_FUNC_TRACE();
1399
1400         /* Get hardware io base address from pcie BAR2 IO space */
1401         hw->io_base = pci_dev->mem_resource[2].addr;
1402
1403         /* Firmware command queue initialize */
1404         ret = hns3_cmd_init_queue(hw);
1405         if (ret) {
1406                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1407                 goto err_cmd_init_queue;
1408         }
1409
1410         /* Firmware command initialize */
1411         ret = hns3_cmd_init(hw);
1412         if (ret) {
1413                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1414                 goto err_cmd_init;
1415         }
1416
1417         /* Get VF resource */
1418         ret = hns3_query_vf_resource(hw);
1419         if (ret)
1420                 goto err_cmd_init;
1421
1422         rte_spinlock_init(&hw->mbx_resp.lock);
1423
1424         hns3vf_clear_event_cause(hw, 0);
1425
1426         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1427                                          hns3vf_interrupt_handler, eth_dev);
1428         if (ret) {
1429                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1430                 goto err_intr_callback_register;
1431         }
1432
1433         /* Enable interrupt */
1434         rte_intr_enable(&pci_dev->intr_handle);
1435         hns3vf_enable_irq0(hw);
1436
1437         /* Get configuration from PF */
1438         ret = hns3vf_get_configuration(hw);
1439         if (ret) {
1440                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1441                 goto err_get_config;
1442         }
1443
1444         /*
1445          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1446          * on the host by "ip link set ..." command. To avoid some incorrect
1447          * scenes, for example, hns3 VF PMD driver fails to receive and send
1448          * packets after user configure the MAC address by using the
1449          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1450          * address strategy as the hns3 kernel ethdev driver in the
1451          * initialization. If user configure a MAC address by the ip command
1452          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1453          * start with a random MAC address in the initialization.
1454          */
1455         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1456         if (ret)
1457                 rte_eth_random_addr(hw->mac.mac_addr);
1458
1459         ret = hns3vf_clear_vport_list(hw);
1460         if (ret) {
1461                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1462                 goto err_get_config;
1463         }
1464
1465         ret = hns3vf_init_hardware(hns);
1466         if (ret)
1467                 goto err_get_config;
1468
1469         hns3_set_default_rss_args(hw);
1470
1471         /*
1472          * In the initialization clearing the all hardware mapping relationship
1473          * configurations between queues and interrupt vectors is needed, so
1474          * some error caused by the residual configurations, such as the
1475          * unexpected interrupt, can be avoid.
1476          */
1477         ret = hns3vf_init_ring_with_vector(hw);
1478         if (ret)
1479                 goto err_get_config;
1480
1481         return 0;
1482
1483 err_get_config:
1484         hns3vf_disable_irq0(hw);
1485         rte_intr_disable(&pci_dev->intr_handle);
1486         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1487                              eth_dev);
1488 err_intr_callback_register:
1489 err_cmd_init:
1490         hns3_cmd_uninit(hw);
1491         hns3_cmd_destroy_queue(hw);
1492 err_cmd_init_queue:
1493         hw->io_base = NULL;
1494
1495         return ret;
1496 }
1497
1498 static void
1499 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1500 {
1501         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1502         struct hns3_adapter *hns = eth_dev->data->dev_private;
1503         struct hns3_hw *hw = &hns->hw;
1504
1505         PMD_INIT_FUNC_TRACE();
1506
1507         hns3_rss_uninit(hns);
1508         (void)hns3vf_set_alive(hw, false);
1509         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1510         hns3vf_disable_irq0(hw);
1511         rte_intr_disable(&pci_dev->intr_handle);
1512         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1513                              eth_dev);
1514         hns3_cmd_uninit(hw);
1515         hns3_cmd_destroy_queue(hw);
1516         hw->io_base = NULL;
1517 }
1518
1519 static int
1520 hns3vf_do_stop(struct hns3_adapter *hns)
1521 {
1522         struct hns3_hw *hw = &hns->hw;
1523         bool reset_queue;
1524
1525         hw->mac.link_status = ETH_LINK_DOWN;
1526
1527         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1528                 hns3vf_configure_mac_addr(hns, true);
1529                 reset_queue = true;
1530         } else
1531                 reset_queue = false;
1532         return hns3_stop_queues(hns, reset_queue);
1533 }
1534
1535 static void
1536 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1537 {
1538         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1540         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1541         uint8_t base = 0;
1542         uint8_t vec = 0;
1543         uint16_t q_id;
1544
1545         if (dev->data->dev_conf.intr_conf.rxq == 0)
1546                 return;
1547
1548         /* unmap the ring with vector */
1549         if (rte_intr_allow_others(intr_handle)) {
1550                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1551                 base = RTE_INTR_VEC_RXTX_OFFSET;
1552         }
1553         if (rte_intr_dp_is_en(intr_handle)) {
1554                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1555                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1556                                                            HNS3_RING_TYPE_RX,
1557                                                            q_id);
1558                         if (vec < base + intr_handle->nb_efd - 1)
1559                                 vec++;
1560                 }
1561         }
1562         /* Clean datapath event and queue/vec mapping */
1563         rte_intr_efd_disable(intr_handle);
1564         if (intr_handle->intr_vec) {
1565                 rte_free(intr_handle->intr_vec);
1566                 intr_handle->intr_vec = NULL;
1567         }
1568 }
1569
1570 static void
1571 hns3vf_dev_stop(struct rte_eth_dev *dev)
1572 {
1573         struct hns3_adapter *hns = dev->data->dev_private;
1574         struct hns3_hw *hw = &hns->hw;
1575
1576         PMD_INIT_FUNC_TRACE();
1577
1578         hw->adapter_state = HNS3_NIC_STOPPING;
1579         hns3_set_rxtx_function(dev);
1580         rte_wmb();
1581         /* Disable datapath on secondary process. */
1582         hns3_mp_req_stop_rxtx(dev);
1583         /* Prevent crashes when queues are still in use. */
1584         rte_delay_ms(hw->tqps_num);
1585
1586         rte_spinlock_lock(&hw->lock);
1587         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1588                 hns3vf_do_stop(hns);
1589                 hns3_dev_release_mbufs(hns);
1590                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1591         }
1592         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1593         rte_spinlock_unlock(&hw->lock);
1594
1595         hns3vf_unmap_rx_interrupt(dev);
1596 }
1597
1598 static void
1599 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1600 {
1601         struct hns3_adapter *hns = eth_dev->data->dev_private;
1602         struct hns3_hw *hw = &hns->hw;
1603
1604         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1605                 return;
1606
1607         if (hw->adapter_state == HNS3_NIC_STARTED)
1608                 hns3vf_dev_stop(eth_dev);
1609
1610         hw->adapter_state = HNS3_NIC_CLOSING;
1611         hns3_reset_abort(hns);
1612         hw->adapter_state = HNS3_NIC_CLOSED;
1613         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1614         hns3vf_configure_all_mc_mac_addr(hns, true);
1615         hns3vf_remove_all_vlan_table(hns);
1616         hns3vf_uninit_vf(eth_dev);
1617         hns3_free_all_queues(eth_dev);
1618         rte_free(hw->reset.wait_data);
1619         rte_free(eth_dev->process_private);
1620         eth_dev->process_private = NULL;
1621         hns3_mp_uninit_primary();
1622         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1623 }
1624
1625 static int
1626 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1627                        __rte_unused int wait_to_complete)
1628 {
1629         struct hns3_adapter *hns = eth_dev->data->dev_private;
1630         struct hns3_hw *hw = &hns->hw;
1631         struct hns3_mac *mac = &hw->mac;
1632         struct rte_eth_link new_link;
1633
1634         memset(&new_link, 0, sizeof(new_link));
1635         switch (mac->link_speed) {
1636         case ETH_SPEED_NUM_10M:
1637         case ETH_SPEED_NUM_100M:
1638         case ETH_SPEED_NUM_1G:
1639         case ETH_SPEED_NUM_10G:
1640         case ETH_SPEED_NUM_25G:
1641         case ETH_SPEED_NUM_40G:
1642         case ETH_SPEED_NUM_50G:
1643         case ETH_SPEED_NUM_100G:
1644                 new_link.link_speed = mac->link_speed;
1645                 break;
1646         default:
1647                 new_link.link_speed = ETH_SPEED_NUM_100M;
1648                 break;
1649         }
1650
1651         new_link.link_duplex = mac->link_duplex;
1652         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1653         new_link.link_autoneg =
1654             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1655
1656         return rte_eth_linkstatus_set(eth_dev, &new_link);
1657 }
1658
1659 static int
1660 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1661 {
1662         struct hns3_hw *hw = &hns->hw;
1663         int ret;
1664
1665         ret = hns3vf_set_tc_info(hns);
1666         if (ret)
1667                 return ret;
1668
1669         ret = hns3_start_queues(hns, reset_queue);
1670         if (ret) {
1671                 hns3_err(hw, "Failed to start queues: %d", ret);
1672                 return ret;
1673         }
1674
1675         return 0;
1676 }
1677
1678 static int
1679 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1680 {
1681         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1682         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1683         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684         uint32_t intr_vector;
1685         uint8_t base = 0;
1686         uint8_t vec = 0;
1687         uint16_t q_id;
1688         int ret;
1689
1690         if (dev->data->dev_conf.intr_conf.rxq == 0)
1691                 return 0;
1692
1693         /* disable uio/vfio intr/eventfd mapping */
1694         rte_intr_disable(intr_handle);
1695
1696         /* check and configure queue intr-vector mapping */
1697         if (rte_intr_cap_multiple(intr_handle) ||
1698             !RTE_ETH_DEV_SRIOV(dev).active) {
1699                 intr_vector = hw->used_rx_queues;
1700                 /* It creates event fd for each intr vector when MSIX is used */
1701                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1702                         return -EINVAL;
1703         }
1704         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1705                 intr_handle->intr_vec =
1706                         rte_zmalloc("intr_vec",
1707                                     hw->used_rx_queues * sizeof(int), 0);
1708                 if (intr_handle->intr_vec == NULL) {
1709                         hns3_err(hw, "Failed to allocate %d rx_queues"
1710                                      " intr_vec", hw->used_rx_queues);
1711                         ret = -ENOMEM;
1712                         goto vf_alloc_intr_vec_error;
1713                 }
1714         }
1715
1716         if (rte_intr_allow_others(intr_handle)) {
1717                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1718                 base = RTE_INTR_VEC_RXTX_OFFSET;
1719         }
1720         if (rte_intr_dp_is_en(intr_handle)) {
1721                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1722                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1723                                                            HNS3_RING_TYPE_RX,
1724                                                            q_id);
1725                         if (ret)
1726                                 goto vf_bind_vector_error;
1727                         intr_handle->intr_vec[q_id] = vec;
1728                         if (vec < base + intr_handle->nb_efd - 1)
1729                                 vec++;
1730                 }
1731         }
1732         rte_intr_enable(intr_handle);
1733         return 0;
1734
1735 vf_bind_vector_error:
1736         rte_intr_efd_disable(intr_handle);
1737         if (intr_handle->intr_vec) {
1738                 free(intr_handle->intr_vec);
1739                 intr_handle->intr_vec = NULL;
1740         }
1741         return ret;
1742 vf_alloc_intr_vec_error:
1743         rte_intr_efd_disable(intr_handle);
1744         return ret;
1745 }
1746
1747 static void
1748 hns3vf_restore_filter(struct rte_eth_dev *dev)
1749 {
1750         hns3_restore_rss_filter(dev);
1751 }
1752
1753 static int
1754 hns3vf_dev_start(struct rte_eth_dev *dev)
1755 {
1756         struct hns3_adapter *hns = dev->data->dev_private;
1757         struct hns3_hw *hw = &hns->hw;
1758         int ret;
1759
1760         PMD_INIT_FUNC_TRACE();
1761         if (rte_atomic16_read(&hw->reset.resetting))
1762                 return -EBUSY;
1763
1764         rte_spinlock_lock(&hw->lock);
1765         hw->adapter_state = HNS3_NIC_STARTING;
1766         ret = hns3vf_do_start(hns, true);
1767         if (ret) {
1768                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1769                 rte_spinlock_unlock(&hw->lock);
1770                 return ret;
1771         }
1772         hw->adapter_state = HNS3_NIC_STARTED;
1773         rte_spinlock_unlock(&hw->lock);
1774
1775         ret = hns3vf_map_rx_interrupt(dev);
1776         if (ret)
1777                 return ret;
1778         hns3_set_rxtx_function(dev);
1779         hns3_mp_req_start_rxtx(dev);
1780         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
1781
1782         hns3vf_restore_filter(dev);
1783
1784         return ret;
1785 }
1786
1787 static bool
1788 is_vf_reset_done(struct hns3_hw *hw)
1789 {
1790 #define HNS3_FUN_RST_ING_BITS \
1791         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1792          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1793          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1794          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1795
1796         uint32_t val;
1797
1798         if (hw->reset.level == HNS3_VF_RESET) {
1799                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1800                 if (val & HNS3_VF_RST_ING_BIT)
1801                         return false;
1802         } else {
1803                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1804                 if (val & HNS3_FUN_RST_ING_BITS)
1805                         return false;
1806         }
1807         return true;
1808 }
1809
1810 bool
1811 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1812 {
1813         struct hns3_hw *hw = &hns->hw;
1814         enum hns3_reset_level reset;
1815
1816         hns3vf_check_event_cause(hns, NULL);
1817         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1818         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
1819                 hns3_warn(hw, "High level reset %d is pending", reset);
1820                 return true;
1821         }
1822         return false;
1823 }
1824
1825 static int
1826 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
1827 {
1828         struct hns3_hw *hw = &hns->hw;
1829         struct hns3_wait_data *wait_data = hw->reset.wait_data;
1830         struct timeval tv;
1831
1832         if (wait_data->result == HNS3_WAIT_SUCCESS) {
1833                 /*
1834                  * After vf reset is ready, the PF may not have completed
1835                  * the reset processing. The vf sending mbox to PF may fail
1836                  * during the pf reset, so it is better to add extra delay.
1837                  */
1838                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
1839                     hw->reset.level == HNS3_FLR_RESET)
1840                         return 0;
1841                 /* Reset retry process, no need to add extra delay. */
1842                 if (hw->reset.attempts)
1843                         return 0;
1844                 if (wait_data->check_completion == NULL)
1845                         return 0;
1846
1847                 wait_data->check_completion = NULL;
1848                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
1849                 wait_data->count = 1;
1850                 wait_data->result = HNS3_WAIT_REQUEST;
1851                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
1852                                   wait_data);
1853                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
1854                 return -EAGAIN;
1855         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
1856                 gettimeofday(&tv, NULL);
1857                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
1858                           tv.tv_sec, tv.tv_usec);
1859                 return -ETIME;
1860         } else if (wait_data->result == HNS3_WAIT_REQUEST)
1861                 return -EAGAIN;
1862
1863         wait_data->hns = hns;
1864         wait_data->check_completion = is_vf_reset_done;
1865         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
1866                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
1867         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
1868         wait_data->count = HNS3VF_RESET_WAIT_CNT;
1869         wait_data->result = HNS3_WAIT_REQUEST;
1870         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
1871         return -EAGAIN;
1872 }
1873
1874 static int
1875 hns3vf_prepare_reset(struct hns3_adapter *hns)
1876 {
1877         struct hns3_hw *hw = &hns->hw;
1878         int ret = 0;
1879
1880         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
1881                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
1882                                         0, true, NULL, 0);
1883         }
1884         rte_atomic16_set(&hw->reset.disable_cmd, 1);
1885
1886         return ret;
1887 }
1888
1889 static int
1890 hns3vf_stop_service(struct hns3_adapter *hns)
1891 {
1892         struct hns3_hw *hw = &hns->hw;
1893         struct rte_eth_dev *eth_dev;
1894
1895         eth_dev = &rte_eth_devices[hw->data->port_id];
1896         if (hw->adapter_state == HNS3_NIC_STARTED)
1897                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
1898         hw->mac.link_status = ETH_LINK_DOWN;
1899
1900         hns3_set_rxtx_function(eth_dev);
1901         rte_wmb();
1902         /* Disable datapath on secondary process. */
1903         hns3_mp_req_stop_rxtx(eth_dev);
1904         rte_delay_ms(hw->tqps_num);
1905
1906         rte_spinlock_lock(&hw->lock);
1907         if (hw->adapter_state == HNS3_NIC_STARTED ||
1908             hw->adapter_state == HNS3_NIC_STOPPING) {
1909                 hns3vf_do_stop(hns);
1910                 hw->reset.mbuf_deferred_free = true;
1911         } else
1912                 hw->reset.mbuf_deferred_free = false;
1913
1914         /*
1915          * It is cumbersome for hardware to pick-and-choose entries for deletion
1916          * from table space. Hence, for function reset software intervention is
1917          * required to delete the entries.
1918          */
1919         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
1920                 hns3vf_configure_all_mc_mac_addr(hns, true);
1921         rte_spinlock_unlock(&hw->lock);
1922
1923         return 0;
1924 }
1925
1926 static int
1927 hns3vf_start_service(struct hns3_adapter *hns)
1928 {
1929         struct hns3_hw *hw = &hns->hw;
1930         struct rte_eth_dev *eth_dev;
1931
1932         eth_dev = &rte_eth_devices[hw->data->port_id];
1933         hns3_set_rxtx_function(eth_dev);
1934         hns3_mp_req_start_rxtx(eth_dev);
1935         if (hw->adapter_state == HNS3_NIC_STARTED)
1936                 hns3vf_service_handler(eth_dev);
1937
1938         return 0;
1939 }
1940
1941 static int
1942 hns3vf_check_default_mac_change(struct hns3_hw *hw)
1943 {
1944         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1945         struct rte_ether_addr *hw_mac;
1946         int ret;
1947
1948         /*
1949          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1950          * on the host by "ip link set ..." command. If the hns3 PF kernel
1951          * ethdev driver sets the MAC address for VF device after the
1952          * initialization of the related VF device, the PF driver will notify
1953          * VF driver to reset VF device to make the new MAC address effective
1954          * immediately. The hns3 VF PMD driver should check whether the MAC
1955          * address has been changed by the PF kernel ethdev driver, if changed
1956          * VF driver should configure hardware using the new MAC address in the
1957          * recovering hardware configuration stage of the reset process.
1958          */
1959         ret = hns3vf_get_host_mac_addr(hw);
1960         if (ret)
1961                 return ret;
1962
1963         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
1964         ret = rte_is_zero_ether_addr(hw_mac);
1965         if (ret) {
1966                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
1967         } else {
1968                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
1969                 if (!ret) {
1970                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
1971                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1972                                               &hw->data->mac_addrs[0]);
1973                         hns3_warn(hw, "Default MAC address has been changed to:"
1974                                   " %s by the host PF kernel ethdev driver",
1975                                   mac_str);
1976                 }
1977         }
1978
1979         return 0;
1980 }
1981
1982 static int
1983 hns3vf_restore_conf(struct hns3_adapter *hns)
1984 {
1985         struct hns3_hw *hw = &hns->hw;
1986         int ret;
1987
1988         ret = hns3vf_check_default_mac_change(hw);
1989         if (ret)
1990                 return ret;
1991
1992         ret = hns3vf_configure_mac_addr(hns, false);
1993         if (ret)
1994                 return ret;
1995
1996         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
1997         if (ret)
1998                 goto err_mc_mac;
1999
2000         ret = hns3vf_restore_promisc(hns);
2001         if (ret)
2002                 goto err_vlan_table;
2003
2004         ret = hns3vf_restore_vlan_conf(hns);
2005         if (ret)
2006                 goto err_vlan_table;
2007
2008         if (hw->adapter_state == HNS3_NIC_STARTED) {
2009                 ret = hns3vf_do_start(hns, false);
2010                 if (ret)
2011                         goto err_vlan_table;
2012                 hns3_info(hw, "hns3vf dev restart successful!");
2013         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2014                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2015         return 0;
2016
2017 err_vlan_table:
2018         hns3vf_configure_all_mc_mac_addr(hns, true);
2019 err_mc_mac:
2020         hns3vf_configure_mac_addr(hns, true);
2021         return ret;
2022 }
2023
2024 static enum hns3_reset_level
2025 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2026 {
2027         enum hns3_reset_level reset_level;
2028
2029         /* return the highest priority reset level amongst all */
2030         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2031                 reset_level = HNS3_VF_RESET;
2032         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2033                 reset_level = HNS3_VF_FULL_RESET;
2034         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2035                 reset_level = HNS3_VF_PF_FUNC_RESET;
2036         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2037                 reset_level = HNS3_VF_FUNC_RESET;
2038         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2039                 reset_level = HNS3_FLR_RESET;
2040         else
2041                 reset_level = HNS3_NONE_RESET;
2042
2043         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2044                 return HNS3_NONE_RESET;
2045
2046         return reset_level;
2047 }
2048
2049 static void
2050 hns3vf_reset_service(void *param)
2051 {
2052         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2053         struct hns3_hw *hw = &hns->hw;
2054         enum hns3_reset_level reset_level;
2055         struct timeval tv_delta;
2056         struct timeval tv_start;
2057         struct timeval tv;
2058         uint64_t msec;
2059
2060         /*
2061          * The interrupt is not triggered within the delay time.
2062          * The interrupt may have been lost. It is necessary to handle
2063          * the interrupt to recover from the error.
2064          */
2065         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2066                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2067                 hns3_err(hw, "Handling interrupts in delayed tasks");
2068                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2069                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2070                 if (reset_level == HNS3_NONE_RESET) {
2071                         hns3_err(hw, "No reset level is set, try global reset");
2072                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2073                 }
2074         }
2075         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2076
2077         /*
2078          * Hardware reset has been notified, we now have to poll & check if
2079          * hardware has actually completed the reset sequence.
2080          */
2081         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2082         if (reset_level != HNS3_NONE_RESET) {
2083                 gettimeofday(&tv_start, NULL);
2084                 hns3_reset_process(hns, reset_level);
2085                 gettimeofday(&tv, NULL);
2086                 timersub(&tv, &tv_start, &tv_delta);
2087                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2088                        tv_delta.tv_usec / USEC_PER_MSEC;
2089                 if (msec > HNS3_RESET_PROCESS_MS)
2090                         hns3_err(hw, "%d handle long time delta %" PRIx64
2091                                  " ms time=%ld.%.6ld",
2092                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2093         }
2094 }
2095
2096 static int
2097 hns3vf_reinit_dev(struct hns3_adapter *hns)
2098 {
2099         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2100         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2101         struct hns3_hw *hw = &hns->hw;
2102         int ret;
2103
2104         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2105                 rte_intr_disable(&pci_dev->intr_handle);
2106                 hns3vf_set_bus_master(pci_dev, true);
2107         }
2108
2109         /* Firmware command initialize */
2110         ret = hns3_cmd_init(hw);
2111         if (ret) {
2112                 hns3_err(hw, "Failed to init cmd: %d", ret);
2113                 return ret;
2114         }
2115
2116         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2117                 /*
2118                  * UIO enables msix by writing the pcie configuration space
2119                  * vfio_pci enables msix in rte_intr_enable.
2120                  */
2121                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2122                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2123                         if (hns3vf_enable_msix(pci_dev, true))
2124                                 hns3_err(hw, "Failed to enable msix");
2125                 }
2126
2127                 rte_intr_enable(&pci_dev->intr_handle);
2128         }
2129
2130         ret = hns3_reset_all_queues(hns);
2131         if (ret) {
2132                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2133                 return ret;
2134         }
2135
2136         ret = hns3vf_init_hardware(hns);
2137         if (ret) {
2138                 hns3_err(hw, "Failed to init hardware: %d", ret);
2139                 return ret;
2140         }
2141
2142         return 0;
2143 }
2144
2145 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2146         .dev_start          = hns3vf_dev_start,
2147         .dev_stop           = hns3vf_dev_stop,
2148         .dev_close          = hns3vf_dev_close,
2149         .mtu_set            = hns3vf_dev_mtu_set,
2150         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2151         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2152         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2153         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2154         .stats_get          = hns3_stats_get,
2155         .stats_reset        = hns3_stats_reset,
2156         .xstats_get         = hns3_dev_xstats_get,
2157         .xstats_get_names   = hns3_dev_xstats_get_names,
2158         .xstats_reset       = hns3_dev_xstats_reset,
2159         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2160         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2161         .dev_infos_get      = hns3vf_dev_infos_get,
2162         .rx_queue_setup     = hns3_rx_queue_setup,
2163         .tx_queue_setup     = hns3_tx_queue_setup,
2164         .rx_queue_release   = hns3_dev_rx_queue_release,
2165         .tx_queue_release   = hns3_dev_tx_queue_release,
2166         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2167         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2168         .dev_configure      = hns3vf_dev_configure,
2169         .mac_addr_add       = hns3vf_add_mac_addr,
2170         .mac_addr_remove    = hns3vf_remove_mac_addr,
2171         .mac_addr_set       = hns3vf_set_default_mac_addr,
2172         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2173         .link_update        = hns3vf_dev_link_update,
2174         .rss_hash_update    = hns3_dev_rss_hash_update,
2175         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2176         .reta_update        = hns3_dev_rss_reta_update,
2177         .reta_query         = hns3_dev_rss_reta_query,
2178         .filter_ctrl        = hns3_dev_filter_ctrl,
2179         .vlan_filter_set    = hns3vf_vlan_filter_set,
2180         .vlan_offload_set   = hns3vf_vlan_offload_set,
2181         .get_reg            = hns3_get_regs,
2182         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2183 };
2184
2185 static const struct hns3_reset_ops hns3vf_reset_ops = {
2186         .reset_service       = hns3vf_reset_service,
2187         .stop_service        = hns3vf_stop_service,
2188         .prepare_reset       = hns3vf_prepare_reset,
2189         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2190         .reinit_dev          = hns3vf_reinit_dev,
2191         .restore_conf        = hns3vf_restore_conf,
2192         .start_service       = hns3vf_start_service,
2193 };
2194
2195 static int
2196 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2197 {
2198         struct hns3_adapter *hns = eth_dev->data->dev_private;
2199         struct hns3_hw *hw = &hns->hw;
2200         int ret;
2201
2202         PMD_INIT_FUNC_TRACE();
2203
2204         eth_dev->process_private = (struct hns3_process_private *)
2205             rte_zmalloc_socket("hns3_filter_list",
2206                                sizeof(struct hns3_process_private),
2207                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2208         if (eth_dev->process_private == NULL) {
2209                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2210                 return -ENOMEM;
2211         }
2212
2213         /* initialize flow filter lists */
2214         hns3_filterlist_init(eth_dev);
2215
2216         hns3_set_rxtx_function(eth_dev);
2217         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2218         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2219                 hns3_mp_init_secondary();
2220                 hw->secondary_cnt++;
2221                 return 0;
2222         }
2223
2224         hns3_mp_init_primary();
2225
2226         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2227         hns->is_vf = true;
2228         hw->data = eth_dev->data;
2229
2230         ret = hns3_reset_init(hw);
2231         if (ret)
2232                 goto err_init_reset;
2233         hw->reset.ops = &hns3vf_reset_ops;
2234
2235         ret = hns3vf_init_vf(eth_dev);
2236         if (ret) {
2237                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2238                 goto err_init_vf;
2239         }
2240
2241         /* Allocate memory for storing MAC addresses */
2242         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2243                                                sizeof(struct rte_ether_addr) *
2244                                                HNS3_VF_UC_MACADDR_NUM, 0);
2245         if (eth_dev->data->mac_addrs == NULL) {
2246                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2247                              "to store MAC addresses",
2248                              sizeof(struct rte_ether_addr) *
2249                              HNS3_VF_UC_MACADDR_NUM);
2250                 ret = -ENOMEM;
2251                 goto err_rte_zmalloc;
2252         }
2253
2254         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2255                             &eth_dev->data->mac_addrs[0]);
2256         hw->adapter_state = HNS3_NIC_INITIALIZED;
2257         /*
2258          * Pass the information to the rte_eth_dev_close() that it should also
2259          * release the private port resources.
2260          */
2261         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2262
2263         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2264                 hns3_err(hw, "Reschedule reset service after dev_init");
2265                 hns3_schedule_reset(hns);
2266         } else {
2267                 /* IMP will wait ready flag before reset */
2268                 hns3_notify_reset_ready(hw, false);
2269         }
2270         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2271                           eth_dev);
2272         return 0;
2273
2274 err_rte_zmalloc:
2275         hns3vf_uninit_vf(eth_dev);
2276
2277 err_init_vf:
2278         rte_free(hw->reset.wait_data);
2279
2280 err_init_reset:
2281         eth_dev->dev_ops = NULL;
2282         eth_dev->rx_pkt_burst = NULL;
2283         eth_dev->tx_pkt_burst = NULL;
2284         eth_dev->tx_pkt_prepare = NULL;
2285         rte_free(eth_dev->process_private);
2286         eth_dev->process_private = NULL;
2287
2288         return ret;
2289 }
2290
2291 static int
2292 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2293 {
2294         struct hns3_adapter *hns = eth_dev->data->dev_private;
2295         struct hns3_hw *hw = &hns->hw;
2296
2297         PMD_INIT_FUNC_TRACE();
2298
2299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2300                 return -EPERM;
2301
2302         eth_dev->dev_ops = NULL;
2303         eth_dev->rx_pkt_burst = NULL;
2304         eth_dev->tx_pkt_burst = NULL;
2305         eth_dev->tx_pkt_prepare = NULL;
2306
2307         if (hw->adapter_state < HNS3_NIC_CLOSING)
2308                 hns3vf_dev_close(eth_dev);
2309
2310         hw->adapter_state = HNS3_NIC_REMOVED;
2311         return 0;
2312 }
2313
2314 static int
2315 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2316                      struct rte_pci_device *pci_dev)
2317 {
2318         return rte_eth_dev_pci_generic_probe(pci_dev,
2319                                              sizeof(struct hns3_adapter),
2320                                              hns3vf_dev_init);
2321 }
2322
2323 static int
2324 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2325 {
2326         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2327 }
2328
2329 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2330         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2331         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2332         { .vendor_id = 0, /* sentinel */ },
2333 };
2334
2335 static struct rte_pci_driver rte_hns3vf_pmd = {
2336         .id_table = pci_id_hns3vf_map,
2337         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2338         .probe = eth_hns3vf_pci_probe,
2339         .remove = eth_hns3vf_pci_remove,
2340 };
2341
2342 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2343 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2344 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");