drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint8_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 708          * constraints in hns3 hardware engine, we have to implement clearing
 709          * the mapping relationship configurations by binding all queues to the
 710          * last interrupt vector and reserving the last interrupt vector. This
 711          * method results in a decrease of the maximum queues when upper
 712          * applications call the rte_eth_dev_configure API function to enable
 713          * Rx interrupt.
 714          */
 715         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 716         /* vec - 1: the last interrupt is reserved */
 717         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
 718         for (i = 0; i < hw->intr_tqps_num; i++) {
 719                 /*
 720                  * Set gap limiter and rate limiter configuration of queue's
 721                  * interrupt.
 722                  */
 723                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 724                                        HNS3_TQP_INTR_GL_DEFAULT);
 725                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 726                                        HNS3_TQP_INTR_GL_DEFAULT);
 727                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 728
 729                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 730                                                    HNS3_RING_TYPE_TX, i);
 731                 if (ret) {
 732                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 733                                           "vector: %d, ret=%d", i, vec, ret);
 734                         return ret;
 735                 }
 736
 737                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 738                                                    HNS3_RING_TYPE_RX, i);
 739                 if (ret) {
 740                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 741                                           "vector: %d, ret=%d", i, vec, ret);
 742                         return ret;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 hns3vf_dev_configure(struct rte_eth_dev *dev)
 751 {
 752         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 754         struct rte_eth_conf *conf = &dev->data->dev_conf;
 755         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 756         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 757         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 758         struct rte_eth_rss_conf rss_conf;
 759         uint16_t mtu;
 760         bool gro_en;
 761         int ret;
 762
 763         /*
 764          * Hardware does not support individually enable/disable/reset the Tx or
 765          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 766          * and Rx queues at the same time. When the numbers of Tx queues
 767          * allocated by upper applications are not equal to the numbers of Rx
 768          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 769          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 770          * these fake queues are imperceptible, and can not be used by upper
 771          * applications.
 772          */
 773         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 774         if (ret) {
 775                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 776                 return ret;
 777         }
 778
 779         hw->adapter_state = HNS3_NIC_CONFIGURING;
 780         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 781                 hns3_err(hw, "setting link speed/duplex not supported");
 782                 ret = -EINVAL;
 783                 goto cfg_err;
 784         }
 785
 786         /* When RSS is not configured, redirect the packet queue 0 */
 787         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 788                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 789                 rss_conf = conf->rx_adv_conf.rss_conf;
 790                 if (rss_conf.rss_key == NULL) {
 791                         rss_conf.rss_key = rss_cfg->key;
 792                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 793                 }
 794
 795                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 796                 if (ret)
 797                         goto cfg_err;
 798         }
 799
 800         /*
 801          * If jumbo frames are enabled, MTU needs to be refreshed
 802          * according to the maximum RX packet length.
 803          */
 804         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 805                 /*
 806                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 807                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 808                  * can safely assign to "uint16_t" type variable.
 809                  */
 810                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 811                 ret = hns3vf_dev_mtu_set(dev, mtu);
 812                 if (ret)
 813                         goto cfg_err;
 814                 dev->data->mtu = mtu;
 815         }
 816
 817         ret = hns3vf_dev_configure_vlan(dev);
 818         if (ret)
 819                 goto cfg_err;
 820
 821         /* config hardware GRO */
 822         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 823         ret = hns3_config_gro(hw, gro_en);
 824         if (ret)
 825                 goto cfg_err;
 826
 827         hw->adapter_state = HNS3_NIC_CONFIGURED;
 828         return 0;
 829
 830 cfg_err:
 831         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 832         hw->adapter_state = HNS3_NIC_INITIALIZED;
 833
 834         return ret;
 835 }
 836
 837 static int
 838 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 839 {
 840         int ret;
 841
 842         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 843                                 sizeof(mtu), true, NULL, 0);
 844         if (ret)
 845                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 846
 847         return ret;
 848 }
 849
 850 static int
 851 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 852 {
 853         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 855         int ret;
 856
 857         /*
 858          * The hns3 PF/VF devices on the same port share the hardware MTU
 859          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 860          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 861          * driver, there is no need to stop the port for hns3 VF device, and the
 862          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 863          * PF's MTU.
 864          */
 865         if (rte_atomic16_read(&hw->reset.resetting)) {
 866                 hns3_err(hw, "Failed to set mtu during resetting");
 867                 return -EIO;
 868         }
 869
 870         rte_spinlock_lock(&hw->lock);
 871         ret = hns3vf_config_mtu(hw, mtu);
 872         if (ret) {
 873                 rte_spinlock_unlock(&hw->lock);
 874                 return ret;
 875         }
 876         if (frame_size > RTE_ETHER_MAX_LEN)
 877                 dev->data->dev_conf.rxmode.offloads |=
 878                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 879         else
 880                 dev->data->dev_conf.rxmode.offloads &=
 881                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 882         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 883         rte_spinlock_unlock(&hw->lock);
 884
 885         return 0;
 886 }
 887
 888 static int
 889 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 890 {
 891         struct hns3_adapter *hns = eth_dev->data->dev_private;
 892         struct hns3_hw *hw = &hns->hw;
 893         uint16_t q_num = hw->tqps_num;
 894
 895         /*
 896          * In interrupt mode, 'max_rx_queues' is set based on the number of
 897          * MSI-X interrupt resources of the hardware.
 898          */
 899         if (hw->data->dev_conf.intr_conf.rxq == 1)
 900                 q_num = hw->intr_tqps_num;
 901
 902         info->max_rx_queues = q_num;
 903         info->max_tx_queues = hw->tqps_num;
 904         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 905         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 906         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 907         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 908         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 909
 910         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 911                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 912                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 913                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 914                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 915                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 916                                  DEV_RX_OFFLOAD_KEEP_CRC |
 917                                  DEV_RX_OFFLOAD_SCATTER |
 918                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 919                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 920                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 921                                  DEV_RX_OFFLOAD_RSS_HASH |
 922                                  DEV_RX_OFFLOAD_TCP_LRO);
 923         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 924         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 925                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 926                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 927                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 928                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 929                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 930                                  DEV_TX_OFFLOAD_TCP_TSO |
 931                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 932                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 933                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 934                                  info->tx_queue_offload_capa |
 935                                  hns3_txvlan_cap_get(hw));
 936
 937         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 938                 .nb_max = HNS3_MAX_RING_DESC,
 939                 .nb_min = HNS3_MIN_RING_DESC,
 940                 .nb_align = HNS3_ALIGN_RING_DESC,
 941         };
 942
 943         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 944                 .nb_max = HNS3_MAX_RING_DESC,
 945                 .nb_min = HNS3_MIN_RING_DESC,
 946                 .nb_align = HNS3_ALIGN_RING_DESC,
 947                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 948                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
 949         };
 950
 951         info->vmdq_queue_num = 0;
 952
 953         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 954         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 955         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 956         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 957         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 958
 959         return 0;
 960 }
 961
 962 static void
 963 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 964 {
 965         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 966 }
 967
 968 static void
 969 hns3vf_disable_irq0(struct hns3_hw *hw)
 970 {
 971         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 972 }
 973
 974 static void
 975 hns3vf_enable_irq0(struct hns3_hw *hw)
 976 {
 977         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 978 }
 979
 980 static enum hns3vf_evt_cause
 981 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 982 {
 983         struct hns3_hw *hw = &hns->hw;
 984         enum hns3vf_evt_cause ret;
 985         uint32_t cmdq_stat_reg;
 986         uint32_t rst_ing_reg;
 987         uint32_t val;
 988
 989         /* Fetch the events from their corresponding regs */
 990         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 991
 992         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 993                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 994                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 995                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 996                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 997                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 998                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 999                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1000                 if (clearval) {
1001                         hw->reset.stats.global_cnt++;
1002                         hns3_warn(hw, "Global reset detected, clear reset status");
1003                 } else {
1004                         hns3_schedule_delayed_reset(hns);
1005                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1006                 }
1007
1008                 ret = HNS3VF_VECTOR0_EVENT_RST;
1009                 goto out;
1010         }
1011
1012         /* Check for vector0 mailbox(=CMDQ RX) event source */
1013         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1014                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1015                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1016                 goto out;
1017         }
1018
1019         val = 0;
1020         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1021 out:
1022         if (clearval)
1023                 *clearval = val;
1024         return ret;
1025 }
1026
1027 static void
1028 hns3vf_interrupt_handler(void *param)
1029 {
1030         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1031         struct hns3_adapter *hns = dev->data->dev_private;
1032         struct hns3_hw *hw = &hns->hw;
1033         enum hns3vf_evt_cause event_cause;
1034         uint32_t clearval;
1035
1036         if (hw->irq_thread_id == 0)
1037                 hw->irq_thread_id = pthread_self();
1038
1039         /* Disable interrupt */
1040         hns3vf_disable_irq0(hw);
1041
1042         /* Read out interrupt causes */
1043         event_cause = hns3vf_check_event_cause(hns, &clearval);
1044
1045         switch (event_cause) {
1046         case HNS3VF_VECTOR0_EVENT_RST:
1047                 hns3_schedule_reset(hns);
1048                 break;
1049         case HNS3VF_VECTOR0_EVENT_MBX:
1050                 hns3_dev_handle_mbx_msg(hw);
1051                 break;
1052         default:
1053                 break;
1054         }
1055
1056         /* Clear interrupt causes */
1057         hns3vf_clear_event_cause(hw, clearval);
1058
1059         /* Enable interrupt */
1060         hns3vf_enable_irq0(hw);
1061 }
1062
1063 static int
1064 hns3vf_get_capability(struct hns3_hw *hw)
1065 {
1066         struct rte_pci_device *pci_dev;
1067         struct rte_eth_dev *eth_dev;
1068         uint8_t revision;
1069         int ret;
1070
1071         eth_dev = &rte_eth_devices[hw->data->port_id];
1072         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1073
1074         /* Get PCI revision id */
1075         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1076                                   HNS3_PCI_REVISION_ID);
1077         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1078                 PMD_INIT_LOG(ERR, "failed to read pci revision id: %d", ret);
1079                 return -EIO;
1080         }
1081         hw->revision = revision;
1082
1083         return 0;
1084 }
1085
1086 static int
1087 hns3vf_check_tqp_info(struct hns3_hw *hw)
1088 {
1089         uint16_t tqps_num;
1090
1091         tqps_num = hw->tqps_num;
1092         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1093                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1094                                   "range: 1~%d",
1095                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1096                 return -EINVAL;
1097         }
1098
1099         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1100
1101         return 0;
1102 }
1103 static int
1104 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1105 {
1106         uint8_t resp_msg;
1107         int ret;
1108
1109         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1110                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1111                                 true, &resp_msg, sizeof(resp_msg));
1112         if (ret) {
1113                 if (ret == -ETIME) {
1114                         /*
1115                          * Getting current port based VLAN state from PF driver
1116                          * will not affect VF driver's basic function. Because
1117                          * the VF driver relies on hns3 PF kernel ether driver,
1118                          * to avoid introducing compatibility issues with older
1119                          * version of PF driver, no failure will be returned
1120                          * when the return value is ETIME. This return value has
1121                          * the following scenarios:
1122                          * 1) Firmware didn't return the results in time
1123                          * 2) the result return by firmware is timeout
1124                          * 3) the older version of kernel side PF driver does
1125                          *    not support this mailbox message.
1126                          * For scenarios 1 and 2, it is most likely that a
1127                          * hardware error has occurred, or a hardware reset has
1128                          * occurred. In this case, these errors will be caught
1129                          * by other functions.
1130                          */
1131                         PMD_INIT_LOG(WARNING,
1132                                 "failed to get PVID state for timeout, maybe "
1133                                 "kernel side PF driver doesn't support this "
1134                                 "mailbox message, or firmware didn't respond.");
1135                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1136                 } else {
1137                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1138                                 " ret = %d", ret);
1139                         return ret;
1140                 }
1141         }
1142         hw->port_base_vlan_cfg.state = resp_msg ?
1143                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1144         return 0;
1145 }
1146
1147 static int
1148 hns3vf_get_queue_info(struct hns3_hw *hw)
1149 {
1150 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1151         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1152         int ret;
1153
1154         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1155                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1156         if (ret) {
1157                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1158                 return ret;
1159         }
1160
1161         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1162         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1163
1164         return hns3vf_check_tqp_info(hw);
1165 }
1166
1167 static int
1168 hns3vf_get_queue_depth(struct hns3_hw *hw)
1169 {
1170 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1171         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1172         int ret;
1173
1174         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1175                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1176         if (ret) {
1177                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1178                              ret);
1179                 return ret;
1180         }
1181
1182         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1183         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1184
1185         return 0;
1186 }
1187
1188 static int
1189 hns3vf_get_tc_info(struct hns3_hw *hw)
1190 {
1191         uint8_t resp_msg;
1192         int ret;
1193
1194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1195                                 true, &resp_msg, sizeof(resp_msg));
1196         if (ret) {
1197                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1198                          ret);
1199                 return ret;
1200         }
1201
1202         hw->hw_tc_map = resp_msg;
1203
1204         return 0;
1205 }
1206
1207 static int
1208 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1209 {
1210         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1211         int ret;
1212
1213         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1214                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1215         if (ret) {
1216                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1217                 return ret;
1218         }
1219
1220         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1221
1222         return 0;
1223 }
1224
1225 static int
1226 hns3vf_get_configuration(struct hns3_hw *hw)
1227 {
1228         int ret;
1229
1230         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1231         hw->rss_dis_flag = false;
1232
1233         /* Get device capability */
1234         ret = hns3vf_get_capability(hw);
1235         if (ret) {
1236                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1237                 return ret;
1238         }
1239
1240         /* Get queue configuration from PF */
1241         ret = hns3vf_get_queue_info(hw);
1242         if (ret)
1243                 return ret;
1244
1245         /* Get queue depth info from PF */
1246         ret = hns3vf_get_queue_depth(hw);
1247         if (ret)
1248                 return ret;
1249
1250         /* Get user defined VF MAC addr from PF */
1251         ret = hns3vf_get_host_mac_addr(hw);
1252         if (ret)
1253                 return ret;
1254
1255         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1256         if (ret)
1257                 return ret;
1258
1259         /* Get tc configuration from PF */
1260         return hns3vf_get_tc_info(hw);
1261 }
1262
1263 static int
1264 hns3vf_set_tc_info(struct hns3_adapter *hns)
1265 {
1266         struct hns3_hw *hw = &hns->hw;
1267         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1268         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1269         uint8_t i;
1270
1271         hw->num_tc = 0;
1272         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1273                 if (hw->hw_tc_map & BIT(i))
1274                         hw->num_tc++;
1275
1276         if (nb_rx_q < hw->num_tc) {
1277                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1278                          nb_rx_q, hw->num_tc);
1279                 return -EINVAL;
1280         }
1281
1282         if (nb_tx_q < hw->num_tc) {
1283                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1284                          nb_tx_q, hw->num_tc);
1285                 return -EINVAL;
1286         }
1287
1288         hns3_set_rss_size(hw, nb_rx_q);
1289         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1290
1291         return 0;
1292 }
1293
1294 static void
1295 hns3vf_request_link_info(struct hns3_hw *hw)
1296 {
1297         uint8_t resp_msg;
1298         int ret;
1299
1300         if (rte_atomic16_read(&hw->reset.resetting))
1301                 return;
1302         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1303                                 &resp_msg, sizeof(resp_msg));
1304         if (ret)
1305                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1306 }
1307
1308 static int
1309 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1310 {
1311 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1312         struct hns3_hw *hw = &hns->hw;
1313         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1314         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1315         uint8_t is_kill = on ? 0 : 1;
1316
1317         msg_data[0] = is_kill;
1318         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1319         memcpy(&msg_data[3], &proto, sizeof(proto));
1320
1321         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1322                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1323                                  0);
1324 }
1325
1326 static int
1327 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1328 {
1329         struct hns3_adapter *hns = dev->data->dev_private;
1330         struct hns3_hw *hw = &hns->hw;
1331         int ret;
1332
1333         if (rte_atomic16_read(&hw->reset.resetting)) {
1334                 hns3_err(hw,
1335                          "vf set vlan id failed during resetting, vlan_id =%u",
1336                          vlan_id);
1337                 return -EIO;
1338         }
1339         rte_spinlock_lock(&hw->lock);
1340         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1341         rte_spinlock_unlock(&hw->lock);
1342         if (ret)
1343                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1344                          vlan_id, ret);
1345
1346         return ret;
1347 }
1348
1349 static int
1350 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1351 {
1352         uint8_t msg_data;
1353         int ret;
1354
1355         msg_data = enable ? 1 : 0;
1356         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1357                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1358         if (ret)
1359                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1360
1361         return ret;
1362 }
1363
1364 static int
1365 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1366 {
1367         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1369         unsigned int tmp_mask;
1370         int ret = 0;
1371
1372         if (rte_atomic16_read(&hw->reset.resetting)) {
1373                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1374                              "mask = 0x%x", mask);
1375                 return -EIO;
1376         }
1377
1378         tmp_mask = (unsigned int)mask;
1379         /* Vlan stripping setting */
1380         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1381                 rte_spinlock_lock(&hw->lock);
1382                 /* Enable or disable VLAN stripping */
1383                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1384                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1385                 else
1386                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1387                 rte_spinlock_unlock(&hw->lock);
1388         }
1389
1390         return ret;
1391 }
1392
1393 static int
1394 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1395 {
1396         struct rte_vlan_filter_conf *vfc;
1397         struct hns3_hw *hw = &hns->hw;
1398         uint16_t vlan_id;
1399         uint64_t vbit;
1400         uint64_t ids;
1401         int ret = 0;
1402         uint32_t i;
1403
1404         vfc = &hw->data->vlan_filter_conf;
1405         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1406                 if (vfc->ids[i] == 0)
1407                         continue;
1408                 ids = vfc->ids[i];
1409                 while (ids) {
1410                         /*
1411                          * 64 means the num bits of ids, one bit corresponds to
1412                          * one vlan id
1413                          */
1414                         vlan_id = 64 * i;
1415                         /* count trailing zeroes */
1416                         vbit = ~ids & (ids - 1);
1417                         /* clear least significant bit set */
1418                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1419                         for (; vbit;) {
1420                                 vbit >>= 1;
1421                                 vlan_id++;
1422                         }
1423                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1424                         if (ret) {
1425                                 hns3_err(hw,
1426                                          "VF handle vlan table failed, ret =%d, on = %d",
1427                                          ret, on);
1428                                 return ret;
1429                         }
1430                 }
1431         }
1432
1433         return ret;
1434 }
1435
1436 static int
1437 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1438 {
1439         return hns3vf_handle_all_vlan_table(hns, 0);
1440 }
1441
1442 static int
1443 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1444 {
1445         struct hns3_hw *hw = &hns->hw;
1446         struct rte_eth_conf *dev_conf;
1447         bool en;
1448         int ret;
1449
1450         dev_conf = &hw->data->dev_conf;
1451         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1452                                                                    : false;
1453         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1454         if (ret)
1455                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1456                          ret);
1457         return ret;
1458 }
1459
1460 static int
1461 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1462 {
1463         struct hns3_adapter *hns = dev->data->dev_private;
1464         struct rte_eth_dev_data *data = dev->data;
1465         struct hns3_hw *hw = &hns->hw;
1466         int ret;
1467
1468         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1469             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1470             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1471                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1472                               "or hw_vlan_insert_pvid is not support!");
1473         }
1474
1475         /* Apply vlan offload setting */
1476         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1477         if (ret)
1478                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1479
1480         return ret;
1481 }
1482
1483 static int
1484 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1485 {
1486         uint8_t msg_data;
1487
1488         msg_data = alive ? 1 : 0;
1489         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1490                                  sizeof(msg_data), false, NULL, 0);
1491 }
1492
1493 static void
1494 hns3vf_keep_alive_handler(void *param)
1495 {
1496         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1497         struct hns3_adapter *hns = eth_dev->data->dev_private;
1498         struct hns3_hw *hw = &hns->hw;
1499         uint8_t respmsg;
1500         int ret;
1501
1502         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1503                                 false, &respmsg, sizeof(uint8_t));
1504         if (ret)
1505                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1506                          ret);
1507
1508         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1509                           eth_dev);
1510 }
1511
1512 static void
1513 hns3vf_service_handler(void *param)
1514 {
1515         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1516         struct hns3_adapter *hns = eth_dev->data->dev_private;
1517         struct hns3_hw *hw = &hns->hw;
1518
1519         /*
1520          * The query link status and reset processing are executed in the
1521          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1522          * and the query operation will time out after 30ms. In the case of
1523          * multiple PF/VFs, each query failure timeout causes the IMP reset
1524          * interrupt to fail to respond within 100ms.
1525          * Before querying the link status, check whether there is a reset
1526          * pending, and if so, abandon the query.
1527          */
1528         if (!hns3vf_is_reset_pending(hns))
1529                 hns3vf_request_link_info(hw);
1530         else
1531                 hns3_warn(hw, "Cancel the query when reset is pending");
1532
1533         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1534                           eth_dev);
1535 }
1536
1537 static int
1538 hns3_query_vf_resource(struct hns3_hw *hw)
1539 {
1540         struct hns3_vf_res_cmd *req;
1541         struct hns3_cmd_desc desc;
1542         uint16_t num_msi;
1543         int ret;
1544
1545         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1546         ret = hns3_cmd_send(hw, &desc, 1);
1547         if (ret) {
1548                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1549                 return ret;
1550         }
1551
1552         req = (struct hns3_vf_res_cmd *)desc.data;
1553         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1554                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1555         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1556                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1557                          num_msi, HNS3_MIN_VECTOR_NUM);
1558                 return -EINVAL;
1559         }
1560
1561         hw->num_msi = num_msi;
1562
1563         return 0;
1564 }
1565
1566 static int
1567 hns3vf_init_hardware(struct hns3_adapter *hns)
1568 {
1569         struct hns3_hw *hw = &hns->hw;
1570         uint16_t mtu = hw->data->mtu;
1571         int ret;
1572
1573         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1574         if (ret)
1575                 return ret;
1576
1577         ret = hns3vf_config_mtu(hw, mtu);
1578         if (ret)
1579                 goto err_init_hardware;
1580
1581         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1582         if (ret) {
1583                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1584                 goto err_init_hardware;
1585         }
1586
1587         ret = hns3_config_gro(hw, false);
1588         if (ret) {
1589                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1590                 goto err_init_hardware;
1591         }
1592
1593         /*
1594          * In the initialization clearing the all hardware mapping relationship
1595          * configurations between queues and interrupt vectors is needed, so
1596          * some error caused by the residual configurations, such as the
1597          * unexpected interrupt, can be avoid.
1598          */
1599         ret = hns3vf_init_ring_with_vector(hw);
1600         if (ret) {
1601                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1602                 goto err_init_hardware;
1603         }
1604
1605         ret = hns3vf_set_alive(hw, true);
1606         if (ret) {
1607                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1608                 goto err_init_hardware;
1609         }
1610
1611         hns3vf_request_link_info(hw);
1612         return 0;
1613
1614 err_init_hardware:
1615         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1616         return ret;
1617 }
1618
1619 static int
1620 hns3vf_clear_vport_list(struct hns3_hw *hw)
1621 {
1622         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1623                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1624                                  NULL, 0);
1625 }
1626
1627 static int
1628 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1629 {
1630         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1631         struct hns3_adapter *hns = eth_dev->data->dev_private;
1632         struct hns3_hw *hw = &hns->hw;
1633         int ret;
1634
1635         PMD_INIT_FUNC_TRACE();
1636
1637         /* Get hardware io base address from pcie BAR2 IO space */
1638         hw->io_base = pci_dev->mem_resource[2].addr;
1639
1640         /* Firmware command queue initialize */
1641         ret = hns3_cmd_init_queue(hw);
1642         if (ret) {
1643                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1644                 goto err_cmd_init_queue;
1645         }
1646
1647         /* Firmware command initialize */
1648         ret = hns3_cmd_init(hw);
1649         if (ret) {
1650                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1651                 goto err_cmd_init;
1652         }
1653
1654         /* Get VF resource */
1655         ret = hns3_query_vf_resource(hw);
1656         if (ret)
1657                 goto err_cmd_init;
1658
1659         rte_spinlock_init(&hw->mbx_resp.lock);
1660
1661         hns3vf_clear_event_cause(hw, 0);
1662
1663         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1664                                          hns3vf_interrupt_handler, eth_dev);
1665         if (ret) {
1666                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1667                 goto err_intr_callback_register;
1668         }
1669
1670         /* Enable interrupt */
1671         rte_intr_enable(&pci_dev->intr_handle);
1672         hns3vf_enable_irq0(hw);
1673
1674         /* Get configuration from PF */
1675         ret = hns3vf_get_configuration(hw);
1676         if (ret) {
1677                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1678                 goto err_get_config;
1679         }
1680
1681         /*
1682          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1683          * on the host by "ip link set ..." command. To avoid some incorrect
1684          * scenes, for example, hns3 VF PMD driver fails to receive and send
1685          * packets after user configure the MAC address by using the
1686          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1687          * address strategy as the hns3 kernel ethdev driver in the
1688          * initialization. If user configure a MAC address by the ip command
1689          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1690          * start with a random MAC address in the initialization.
1691          */
1692         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1693         if (ret)
1694                 rte_eth_random_addr(hw->mac.mac_addr);
1695
1696         ret = hns3vf_clear_vport_list(hw);
1697         if (ret) {
1698                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1699                 goto err_get_config;
1700         }
1701
1702         ret = hns3vf_init_hardware(hns);
1703         if (ret)
1704                 goto err_get_config;
1705
1706         hns3_set_default_rss_args(hw);
1707
1708         return 0;
1709
1710 err_get_config:
1711         hns3vf_disable_irq0(hw);
1712         rte_intr_disable(&pci_dev->intr_handle);
1713         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1714                              eth_dev);
1715 err_intr_callback_register:
1716 err_cmd_init:
1717         hns3_cmd_uninit(hw);
1718         hns3_cmd_destroy_queue(hw);
1719 err_cmd_init_queue:
1720         hw->io_base = NULL;
1721
1722         return ret;
1723 }
1724
1725 static void
1726 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1727 {
1728         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1729         struct hns3_adapter *hns = eth_dev->data->dev_private;
1730         struct hns3_hw *hw = &hns->hw;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         hns3_rss_uninit(hns);
1735         (void)hns3_config_gro(hw, false);
1736         (void)hns3vf_set_alive(hw, false);
1737         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1738         hns3vf_disable_irq0(hw);
1739         rte_intr_disable(&pci_dev->intr_handle);
1740         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1741                              eth_dev);
1742         hns3_cmd_uninit(hw);
1743         hns3_cmd_destroy_queue(hw);
1744         hw->io_base = NULL;
1745 }
1746
1747 static int
1748 hns3vf_do_stop(struct hns3_adapter *hns)
1749 {
1750         struct hns3_hw *hw = &hns->hw;
1751         bool reset_queue;
1752
1753         hw->mac.link_status = ETH_LINK_DOWN;
1754
1755         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1756                 hns3vf_configure_mac_addr(hns, true);
1757                 reset_queue = true;
1758         } else
1759                 reset_queue = false;
1760         return hns3_stop_queues(hns, reset_queue);
1761 }
1762
1763 static void
1764 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1765 {
1766         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1768         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1769         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1770         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1771         uint16_t q_id;
1772
1773         if (dev->data->dev_conf.intr_conf.rxq == 0)
1774                 return;
1775
1776         /* unmap the ring with vector */
1777         if (rte_intr_allow_others(intr_handle)) {
1778                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1779                 base = RTE_INTR_VEC_RXTX_OFFSET;
1780         }
1781         if (rte_intr_dp_is_en(intr_handle)) {
1782                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1783                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1784                                                            HNS3_RING_TYPE_RX,
1785                                                            q_id);
1786                         if (vec < base + intr_handle->nb_efd - 1)
1787                                 vec++;
1788                 }
1789         }
1790         /* Clean datapath event and queue/vec mapping */
1791         rte_intr_efd_disable(intr_handle);
1792         if (intr_handle->intr_vec) {
1793                 rte_free(intr_handle->intr_vec);
1794                 intr_handle->intr_vec = NULL;
1795         }
1796 }
1797
1798 static void
1799 hns3vf_dev_stop(struct rte_eth_dev *dev)
1800 {
1801         struct hns3_adapter *hns = dev->data->dev_private;
1802         struct hns3_hw *hw = &hns->hw;
1803
1804         PMD_INIT_FUNC_TRACE();
1805
1806         hw->adapter_state = HNS3_NIC_STOPPING;
1807         hns3_set_rxtx_function(dev);
1808         rte_wmb();
1809         /* Disable datapath on secondary process. */
1810         hns3_mp_req_stop_rxtx(dev);
1811         /* Prevent crashes when queues are still in use. */
1812         rte_delay_ms(hw->tqps_num);
1813
1814         rte_spinlock_lock(&hw->lock);
1815         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1816                 hns3vf_do_stop(hns);
1817                 hns3vf_unmap_rx_interrupt(dev);
1818                 hns3_dev_release_mbufs(hns);
1819                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1820         }
1821         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1822         rte_spinlock_unlock(&hw->lock);
1823 }
1824
1825 static void
1826 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1827 {
1828         struct hns3_adapter *hns = eth_dev->data->dev_private;
1829         struct hns3_hw *hw = &hns->hw;
1830
1831         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1832                 return;
1833
1834         if (hw->adapter_state == HNS3_NIC_STARTED)
1835                 hns3vf_dev_stop(eth_dev);
1836
1837         hw->adapter_state = HNS3_NIC_CLOSING;
1838         hns3_reset_abort(hns);
1839         hw->adapter_state = HNS3_NIC_CLOSED;
1840         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1841         hns3vf_configure_all_mc_mac_addr(hns, true);
1842         hns3vf_remove_all_vlan_table(hns);
1843         hns3vf_uninit_vf(eth_dev);
1844         hns3_free_all_queues(eth_dev);
1845         rte_free(hw->reset.wait_data);
1846         rte_free(eth_dev->process_private);
1847         eth_dev->process_private = NULL;
1848         hns3_mp_uninit_primary();
1849         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1850 }
1851
1852 static int
1853 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1854                       size_t fw_size)
1855 {
1856         struct hns3_adapter *hns = eth_dev->data->dev_private;
1857         struct hns3_hw *hw = &hns->hw;
1858         uint32_t version = hw->fw_version;
1859         int ret;
1860
1861         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1862                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1863                                       HNS3_FW_VERSION_BYTE3_S),
1864                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1865                                       HNS3_FW_VERSION_BYTE2_S),
1866                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1867                                       HNS3_FW_VERSION_BYTE1_S),
1868                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1869                                       HNS3_FW_VERSION_BYTE0_S));
1870         ret += 1; /* add the size of '\0' */
1871         if (fw_size < (uint32_t)ret)
1872                 return ret;
1873         else
1874                 return 0;
1875 }
1876
1877 static int
1878 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1879                        __rte_unused int wait_to_complete)
1880 {
1881         struct hns3_adapter *hns = eth_dev->data->dev_private;
1882         struct hns3_hw *hw = &hns->hw;
1883         struct hns3_mac *mac = &hw->mac;
1884         struct rte_eth_link new_link;
1885
1886         memset(&new_link, 0, sizeof(new_link));
1887         switch (mac->link_speed) {
1888         case ETH_SPEED_NUM_10M:
1889         case ETH_SPEED_NUM_100M:
1890         case ETH_SPEED_NUM_1G:
1891         case ETH_SPEED_NUM_10G:
1892         case ETH_SPEED_NUM_25G:
1893         case ETH_SPEED_NUM_40G:
1894         case ETH_SPEED_NUM_50G:
1895         case ETH_SPEED_NUM_100G:
1896         case ETH_SPEED_NUM_200G:
1897                 new_link.link_speed = mac->link_speed;
1898                 break;
1899         default:
1900                 new_link.link_speed = ETH_SPEED_NUM_100M;
1901                 break;
1902         }
1903
1904         new_link.link_duplex = mac->link_duplex;
1905         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1906         new_link.link_autoneg =
1907             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1908
1909         return rte_eth_linkstatus_set(eth_dev, &new_link);
1910 }
1911
1912 static int
1913 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1914 {
1915         struct hns3_hw *hw = &hns->hw;
1916         int ret;
1917
1918         ret = hns3vf_set_tc_info(hns);
1919         if (ret)
1920                 return ret;
1921
1922         ret = hns3_start_queues(hns, reset_queue);
1923         if (ret)
1924                 hns3_err(hw, "Failed to start queues: %d", ret);
1925
1926         return ret;
1927 }
1928
1929 static int
1930 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1931 {
1932         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1933         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1934         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1936         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1937         uint32_t intr_vector;
1938         uint16_t q_id;
1939         int ret;
1940
1941         if (dev->data->dev_conf.intr_conf.rxq == 0)
1942                 return 0;
1943
1944         /* disable uio/vfio intr/eventfd mapping */
1945         rte_intr_disable(intr_handle);
1946
1947         /* check and configure queue intr-vector mapping */
1948         if (rte_intr_cap_multiple(intr_handle) ||
1949             !RTE_ETH_DEV_SRIOV(dev).active) {
1950                 intr_vector = hw->used_rx_queues;
1951                 /* It creates event fd for each intr vector when MSIX is used */
1952                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1953                         return -EINVAL;
1954         }
1955         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1956                 intr_handle->intr_vec =
1957                         rte_zmalloc("intr_vec",
1958                                     hw->used_rx_queues * sizeof(int), 0);
1959                 if (intr_handle->intr_vec == NULL) {
1960                         hns3_err(hw, "Failed to allocate %d rx_queues"
1961                                      " intr_vec", hw->used_rx_queues);
1962                         ret = -ENOMEM;
1963                         goto vf_alloc_intr_vec_error;
1964                 }
1965         }
1966
1967         if (rte_intr_allow_others(intr_handle)) {
1968                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1969                 base = RTE_INTR_VEC_RXTX_OFFSET;
1970         }
1971         if (rte_intr_dp_is_en(intr_handle)) {
1972                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1973                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1974                                                            HNS3_RING_TYPE_RX,
1975                                                            q_id);
1976                         if (ret)
1977                                 goto vf_bind_vector_error;
1978                         intr_handle->intr_vec[q_id] = vec;
1979                         if (vec < base + intr_handle->nb_efd - 1)
1980                                 vec++;
1981                 }
1982         }
1983         rte_intr_enable(intr_handle);
1984         return 0;
1985
1986 vf_bind_vector_error:
1987         rte_intr_efd_disable(intr_handle);
1988         if (intr_handle->intr_vec) {
1989                 free(intr_handle->intr_vec);
1990                 intr_handle->intr_vec = NULL;
1991         }
1992         return ret;
1993 vf_alloc_intr_vec_error:
1994         rte_intr_efd_disable(intr_handle);
1995         return ret;
1996 }
1997
1998 static int
1999 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2000 {
2001         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2002         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2003         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2004         uint16_t q_id;
2005         int ret;
2006
2007         if (dev->data->dev_conf.intr_conf.rxq == 0)
2008                 return 0;
2009
2010         if (rte_intr_dp_is_en(intr_handle)) {
2011                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2012                         ret = hns3vf_bind_ring_with_vector(hw,
2013                                         intr_handle->intr_vec[q_id], true,
2014                                         HNS3_RING_TYPE_RX, q_id);
2015                         if (ret)
2016                                 return ret;
2017                 }
2018         }
2019
2020         return 0;
2021 }
2022
2023 static void
2024 hns3vf_restore_filter(struct rte_eth_dev *dev)
2025 {
2026         hns3_restore_rss_filter(dev);
2027 }
2028
2029 static int
2030 hns3vf_dev_start(struct rte_eth_dev *dev)
2031 {
2032         struct hns3_adapter *hns = dev->data->dev_private;
2033         struct hns3_hw *hw = &hns->hw;
2034         int ret;
2035
2036         PMD_INIT_FUNC_TRACE();
2037         if (rte_atomic16_read(&hw->reset.resetting))
2038                 return -EBUSY;
2039
2040         rte_spinlock_lock(&hw->lock);
2041         hw->adapter_state = HNS3_NIC_STARTING;
2042         ret = hns3vf_do_start(hns, true);
2043         if (ret) {
2044                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2045                 rte_spinlock_unlock(&hw->lock);
2046                 return ret;
2047         }
2048         ret = hns3vf_map_rx_interrupt(dev);
2049         if (ret) {
2050                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2051                 rte_spinlock_unlock(&hw->lock);
2052                 return ret;
2053         }
2054         hw->adapter_state = HNS3_NIC_STARTED;
2055         rte_spinlock_unlock(&hw->lock);
2056
2057         hns3_set_rxtx_function(dev);
2058         hns3_mp_req_start_rxtx(dev);
2059         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2060
2061         hns3vf_restore_filter(dev);
2062
2063         /* Enable interrupt of all rx queues before enabling queues */
2064         hns3_dev_all_rx_queue_intr_enable(hw, true);
2065         /*
2066          * When finished the initialization, enable queues to receive/transmit
2067          * packets.
2068          */
2069         hns3_enable_all_queues(hw, true);
2070
2071         return ret;
2072 }
2073
2074 static bool
2075 is_vf_reset_done(struct hns3_hw *hw)
2076 {
2077 #define HNS3_FUN_RST_ING_BITS \
2078         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2079          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2080          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2081          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2082
2083         uint32_t val;
2084
2085         if (hw->reset.level == HNS3_VF_RESET) {
2086                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2087                 if (val & HNS3_VF_RST_ING_BIT)
2088                         return false;
2089         } else {
2090                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2091                 if (val & HNS3_FUN_RST_ING_BITS)
2092                         return false;
2093         }
2094         return true;
2095 }
2096
2097 bool
2098 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2099 {
2100         struct hns3_hw *hw = &hns->hw;
2101         enum hns3_reset_level reset;
2102
2103         hns3vf_check_event_cause(hns, NULL);
2104         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2105         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2106                 hns3_warn(hw, "High level reset %d is pending", reset);
2107                 return true;
2108         }
2109         return false;
2110 }
2111
2112 static int
2113 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2114 {
2115         struct hns3_hw *hw = &hns->hw;
2116         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2117         struct timeval tv;
2118
2119         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2120                 /*
2121                  * After vf reset is ready, the PF may not have completed
2122                  * the reset processing. The vf sending mbox to PF may fail
2123                  * during the pf reset, so it is better to add extra delay.
2124                  */
2125                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2126                     hw->reset.level == HNS3_FLR_RESET)
2127                         return 0;
2128                 /* Reset retry process, no need to add extra delay. */
2129                 if (hw->reset.attempts)
2130                         return 0;
2131                 if (wait_data->check_completion == NULL)
2132                         return 0;
2133
2134                 wait_data->check_completion = NULL;
2135                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2136                 wait_data->count = 1;
2137                 wait_data->result = HNS3_WAIT_REQUEST;
2138                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2139                                   wait_data);
2140                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2141                 return -EAGAIN;
2142         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2143                 gettimeofday(&tv, NULL);
2144                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2145                           tv.tv_sec, tv.tv_usec);
2146                 return -ETIME;
2147         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2148                 return -EAGAIN;
2149
2150         wait_data->hns = hns;
2151         wait_data->check_completion = is_vf_reset_done;
2152         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2153                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2154         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2155         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2156         wait_data->result = HNS3_WAIT_REQUEST;
2157         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2158         return -EAGAIN;
2159 }
2160
2161 static int
2162 hns3vf_prepare_reset(struct hns3_adapter *hns)
2163 {
2164         struct hns3_hw *hw = &hns->hw;
2165         int ret = 0;
2166
2167         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2168                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2169                                         0, true, NULL, 0);
2170         }
2171         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2172
2173         return ret;
2174 }
2175
2176 static int
2177 hns3vf_stop_service(struct hns3_adapter *hns)
2178 {
2179         struct hns3_hw *hw = &hns->hw;
2180         struct rte_eth_dev *eth_dev;
2181
2182         eth_dev = &rte_eth_devices[hw->data->port_id];
2183         if (hw->adapter_state == HNS3_NIC_STARTED)
2184                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2185         hw->mac.link_status = ETH_LINK_DOWN;
2186
2187         hns3_set_rxtx_function(eth_dev);
2188         rte_wmb();
2189         /* Disable datapath on secondary process. */
2190         hns3_mp_req_stop_rxtx(eth_dev);
2191         rte_delay_ms(hw->tqps_num);
2192
2193         rte_spinlock_lock(&hw->lock);
2194         if (hw->adapter_state == HNS3_NIC_STARTED ||
2195             hw->adapter_state == HNS3_NIC_STOPPING) {
2196                 hns3vf_do_stop(hns);
2197                 hw->reset.mbuf_deferred_free = true;
2198         } else
2199                 hw->reset.mbuf_deferred_free = false;
2200
2201         /*
2202          * It is cumbersome for hardware to pick-and-choose entries for deletion
2203          * from table space. Hence, for function reset software intervention is
2204          * required to delete the entries.
2205          */
2206         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2207                 hns3vf_configure_all_mc_mac_addr(hns, true);
2208         rte_spinlock_unlock(&hw->lock);
2209
2210         return 0;
2211 }
2212
2213 static int
2214 hns3vf_start_service(struct hns3_adapter *hns)
2215 {
2216         struct hns3_hw *hw = &hns->hw;
2217         struct rte_eth_dev *eth_dev;
2218
2219         eth_dev = &rte_eth_devices[hw->data->port_id];
2220         hns3_set_rxtx_function(eth_dev);
2221         hns3_mp_req_start_rxtx(eth_dev);
2222         if (hw->adapter_state == HNS3_NIC_STARTED) {
2223                 hns3vf_service_handler(eth_dev);
2224
2225                 /* Enable interrupt of all rx queues before enabling queues */
2226                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2227                 /*
2228                  * When finished the initialization, enable queues to receive
2229                  * and transmit packets.
2230                  */
2231                 hns3_enable_all_queues(hw, true);
2232         }
2233
2234         return 0;
2235 }
2236
2237 static int
2238 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2239 {
2240         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2241         struct rte_ether_addr *hw_mac;
2242         int ret;
2243
2244         /*
2245          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2246          * on the host by "ip link set ..." command. If the hns3 PF kernel
2247          * ethdev driver sets the MAC address for VF device after the
2248          * initialization of the related VF device, the PF driver will notify
2249          * VF driver to reset VF device to make the new MAC address effective
2250          * immediately. The hns3 VF PMD driver should check whether the MAC
2251          * address has been changed by the PF kernel ethdev driver, if changed
2252          * VF driver should configure hardware using the new MAC address in the
2253          * recovering hardware configuration stage of the reset process.
2254          */
2255         ret = hns3vf_get_host_mac_addr(hw);
2256         if (ret)
2257                 return ret;
2258
2259         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2260         ret = rte_is_zero_ether_addr(hw_mac);
2261         if (ret) {
2262                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2263         } else {
2264                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2265                 if (!ret) {
2266                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2267                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2268                                               &hw->data->mac_addrs[0]);
2269                         hns3_warn(hw, "Default MAC address has been changed to:"
2270                                   " %s by the host PF kernel ethdev driver",
2271                                   mac_str);
2272                 }
2273         }
2274
2275         return 0;
2276 }
2277
2278 static int
2279 hns3vf_restore_conf(struct hns3_adapter *hns)
2280 {
2281         struct hns3_hw *hw = &hns->hw;
2282         int ret;
2283
2284         ret = hns3vf_check_default_mac_change(hw);
2285         if (ret)
2286                 return ret;
2287
2288         ret = hns3vf_configure_mac_addr(hns, false);
2289         if (ret)
2290                 return ret;
2291
2292         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2293         if (ret)
2294                 goto err_mc_mac;
2295
2296         ret = hns3vf_restore_promisc(hns);
2297         if (ret)
2298                 goto err_vlan_table;
2299
2300         ret = hns3vf_restore_vlan_conf(hns);
2301         if (ret)
2302                 goto err_vlan_table;
2303
2304         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2305         if (ret)
2306                 goto err_vlan_table;
2307
2308         ret = hns3vf_restore_rx_interrupt(hw);
2309         if (ret)
2310                 goto err_vlan_table;
2311
2312         ret = hns3_restore_gro_conf(hw);
2313         if (ret)
2314                 goto err_vlan_table;
2315
2316         if (hw->adapter_state == HNS3_NIC_STARTED) {
2317                 ret = hns3vf_do_start(hns, false);
2318                 if (ret)
2319                         goto err_vlan_table;
2320                 hns3_info(hw, "hns3vf dev restart successful!");
2321         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2322                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2323         return 0;
2324
2325 err_vlan_table:
2326         hns3vf_configure_all_mc_mac_addr(hns, true);
2327 err_mc_mac:
2328         hns3vf_configure_mac_addr(hns, true);
2329         return ret;
2330 }
2331
2332 static enum hns3_reset_level
2333 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2334 {
2335         enum hns3_reset_level reset_level;
2336
2337         /* return the highest priority reset level amongst all */
2338         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2339                 reset_level = HNS3_VF_RESET;
2340         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2341                 reset_level = HNS3_VF_FULL_RESET;
2342         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2343                 reset_level = HNS3_VF_PF_FUNC_RESET;
2344         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2345                 reset_level = HNS3_VF_FUNC_RESET;
2346         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2347                 reset_level = HNS3_FLR_RESET;
2348         else
2349                 reset_level = HNS3_NONE_RESET;
2350
2351         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2352                 return HNS3_NONE_RESET;
2353
2354         return reset_level;
2355 }
2356
2357 static void
2358 hns3vf_reset_service(void *param)
2359 {
2360         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2361         struct hns3_hw *hw = &hns->hw;
2362         enum hns3_reset_level reset_level;
2363         struct timeval tv_delta;
2364         struct timeval tv_start;
2365         struct timeval tv;
2366         uint64_t msec;
2367
2368         /*
2369          * The interrupt is not triggered within the delay time.
2370          * The interrupt may have been lost. It is necessary to handle
2371          * the interrupt to recover from the error.
2372          */
2373         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2374                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2375                 hns3_err(hw, "Handling interrupts in delayed tasks");
2376                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2377                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2378                 if (reset_level == HNS3_NONE_RESET) {
2379                         hns3_err(hw, "No reset level is set, try global reset");
2380                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2381                 }
2382         }
2383         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2384
2385         /*
2386          * Hardware reset has been notified, we now have to poll & check if
2387          * hardware has actually completed the reset sequence.
2388          */
2389         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2390         if (reset_level != HNS3_NONE_RESET) {
2391                 gettimeofday(&tv_start, NULL);
2392                 hns3_reset_process(hns, reset_level);
2393                 gettimeofday(&tv, NULL);
2394                 timersub(&tv, &tv_start, &tv_delta);
2395                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2396                        tv_delta.tv_usec / USEC_PER_MSEC;
2397                 if (msec > HNS3_RESET_PROCESS_MS)
2398                         hns3_err(hw, "%d handle long time delta %" PRIx64
2399                                  " ms time=%ld.%.6ld",
2400                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2401         }
2402 }
2403
2404 static int
2405 hns3vf_reinit_dev(struct hns3_adapter *hns)
2406 {
2407         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2408         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2409         struct hns3_hw *hw = &hns->hw;
2410         int ret;
2411
2412         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2413                 rte_intr_disable(&pci_dev->intr_handle);
2414                 hns3vf_set_bus_master(pci_dev, true);
2415         }
2416
2417         /* Firmware command initialize */
2418         ret = hns3_cmd_init(hw);
2419         if (ret) {
2420                 hns3_err(hw, "Failed to init cmd: %d", ret);
2421                 return ret;
2422         }
2423
2424         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2425                 /*
2426                  * UIO enables msix by writing the pcie configuration space
2427                  * vfio_pci enables msix in rte_intr_enable.
2428                  */
2429                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2430                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2431                         if (hns3vf_enable_msix(pci_dev, true))
2432                                 hns3_err(hw, "Failed to enable msix");
2433                 }
2434
2435                 rte_intr_enable(&pci_dev->intr_handle);
2436         }
2437
2438         ret = hns3_reset_all_queues(hns);
2439         if (ret) {
2440                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2441                 return ret;
2442         }
2443
2444         ret = hns3vf_init_hardware(hns);
2445         if (ret) {
2446                 hns3_err(hw, "Failed to init hardware: %d", ret);
2447                 return ret;
2448         }
2449
2450         return 0;
2451 }
2452
2453 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2454         .dev_start          = hns3vf_dev_start,
2455         .dev_stop           = hns3vf_dev_stop,
2456         .dev_close          = hns3vf_dev_close,
2457         .mtu_set            = hns3vf_dev_mtu_set,
2458         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2459         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2460         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2461         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2462         .stats_get          = hns3_stats_get,
2463         .stats_reset        = hns3_stats_reset,
2464         .xstats_get         = hns3_dev_xstats_get,
2465         .xstats_get_names   = hns3_dev_xstats_get_names,
2466         .xstats_reset       = hns3_dev_xstats_reset,
2467         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2468         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2469         .dev_infos_get      = hns3vf_dev_infos_get,
2470         .fw_version_get     = hns3vf_fw_version_get,
2471         .rx_queue_setup     = hns3_rx_queue_setup,
2472         .tx_queue_setup     = hns3_tx_queue_setup,
2473         .rx_queue_release   = hns3_dev_rx_queue_release,
2474         .tx_queue_release   = hns3_dev_tx_queue_release,
2475         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2476         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2477         .dev_configure      = hns3vf_dev_configure,
2478         .mac_addr_add       = hns3vf_add_mac_addr,
2479         .mac_addr_remove    = hns3vf_remove_mac_addr,
2480         .mac_addr_set       = hns3vf_set_default_mac_addr,
2481         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2482         .link_update        = hns3vf_dev_link_update,
2483         .rss_hash_update    = hns3_dev_rss_hash_update,
2484         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2485         .reta_update        = hns3_dev_rss_reta_update,
2486         .reta_query         = hns3_dev_rss_reta_query,
2487         .filter_ctrl        = hns3_dev_filter_ctrl,
2488         .vlan_filter_set    = hns3vf_vlan_filter_set,
2489         .vlan_offload_set   = hns3vf_vlan_offload_set,
2490         .get_reg            = hns3_get_regs,
2491         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2492 };
2493
2494 static const struct hns3_reset_ops hns3vf_reset_ops = {
2495         .reset_service       = hns3vf_reset_service,
2496         .stop_service        = hns3vf_stop_service,
2497         .prepare_reset       = hns3vf_prepare_reset,
2498         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2499         .reinit_dev          = hns3vf_reinit_dev,
2500         .restore_conf        = hns3vf_restore_conf,
2501         .start_service       = hns3vf_start_service,
2502 };
2503
2504 static int
2505 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2506 {
2507         struct hns3_adapter *hns = eth_dev->data->dev_private;
2508         struct hns3_hw *hw = &hns->hw;
2509         int ret;
2510
2511         PMD_INIT_FUNC_TRACE();
2512
2513         eth_dev->process_private = (struct hns3_process_private *)
2514             rte_zmalloc_socket("hns3_filter_list",
2515                                sizeof(struct hns3_process_private),
2516                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2517         if (eth_dev->process_private == NULL) {
2518                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2519                 return -ENOMEM;
2520         }
2521
2522         /* initialize flow filter lists */
2523         hns3_filterlist_init(eth_dev);
2524
2525         hns3_set_rxtx_function(eth_dev);
2526         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2527         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2528                 ret = hns3_mp_init_secondary();
2529                 if (ret) {
2530                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2531                                           "process, ret = %d", ret);
2532                         goto err_mp_init_secondary;
2533                 }
2534
2535                 hw->secondary_cnt++;
2536                 return 0;
2537         }
2538
2539         ret = hns3_mp_init_primary();
2540         if (ret) {
2541                 PMD_INIT_LOG(ERR,
2542                              "Failed to init for primary process, ret = %d",
2543                              ret);
2544                 goto err_mp_init_primary;
2545         }
2546
2547         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2548         hns->is_vf = true;
2549         hw->data = eth_dev->data;
2550
2551         ret = hns3_reset_init(hw);
2552         if (ret)
2553                 goto err_init_reset;
2554         hw->reset.ops = &hns3vf_reset_ops;
2555
2556         ret = hns3vf_init_vf(eth_dev);
2557         if (ret) {
2558                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2559                 goto err_init_vf;
2560         }
2561
2562         /* Allocate memory for storing MAC addresses */
2563         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2564                                                sizeof(struct rte_ether_addr) *
2565                                                HNS3_VF_UC_MACADDR_NUM, 0);
2566         if (eth_dev->data->mac_addrs == NULL) {
2567                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2568                              "to store MAC addresses",
2569                              sizeof(struct rte_ether_addr) *
2570                              HNS3_VF_UC_MACADDR_NUM);
2571                 ret = -ENOMEM;
2572                 goto err_rte_zmalloc;
2573         }
2574
2575         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2576                             &eth_dev->data->mac_addrs[0]);
2577         hw->adapter_state = HNS3_NIC_INITIALIZED;
2578         /*
2579          * Pass the information to the rte_eth_dev_close() that it should also
2580          * release the private port resources.
2581          */
2582         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2583
2584         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2585                 hns3_err(hw, "Reschedule reset service after dev_init");
2586                 hns3_schedule_reset(hns);
2587         } else {
2588                 /* IMP will wait ready flag before reset */
2589                 hns3_notify_reset_ready(hw, false);
2590         }
2591         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2592                           eth_dev);
2593         return 0;
2594
2595 err_rte_zmalloc:
2596         hns3vf_uninit_vf(eth_dev);
2597
2598 err_init_vf:
2599         rte_free(hw->reset.wait_data);
2600
2601 err_init_reset:
2602         hns3_mp_uninit_primary();
2603
2604 err_mp_init_primary:
2605 err_mp_init_secondary:
2606         eth_dev->dev_ops = NULL;
2607         eth_dev->rx_pkt_burst = NULL;
2608         eth_dev->tx_pkt_burst = NULL;
2609         eth_dev->tx_pkt_prepare = NULL;
2610         rte_free(eth_dev->process_private);
2611         eth_dev->process_private = NULL;
2612
2613         return ret;
2614 }
2615
2616 static int
2617 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2618 {
2619         struct hns3_adapter *hns = eth_dev->data->dev_private;
2620         struct hns3_hw *hw = &hns->hw;
2621
2622         PMD_INIT_FUNC_TRACE();
2623
2624         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2625                 return -EPERM;
2626
2627         eth_dev->dev_ops = NULL;
2628         eth_dev->rx_pkt_burst = NULL;
2629         eth_dev->tx_pkt_burst = NULL;
2630         eth_dev->tx_pkt_prepare = NULL;
2631
2632         if (hw->adapter_state < HNS3_NIC_CLOSING)
2633                 hns3vf_dev_close(eth_dev);
2634
2635         hw->adapter_state = HNS3_NIC_REMOVED;
2636         return 0;
2637 }
2638
2639 static int
2640 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2641                      struct rte_pci_device *pci_dev)
2642 {
2643         return rte_eth_dev_pci_generic_probe(pci_dev,
2644                                              sizeof(struct hns3_adapter),
2645                                              hns3vf_dev_init);
2646 }
2647
2648 static int
2649 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2650 {
2651         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2652 }
2653
2654 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2655         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2656         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2657         { .vendor_id = 0, /* sentinel */ },
2658 };
2659
2660 static struct rte_pci_driver rte_hns3vf_pmd = {
2661         .id_table = pci_id_hns3vf_map,
2662         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2663         .probe = eth_hns3vf_pci_probe,
2664         .remove = eth_hns3vf_pci_remove,
2665 };
2666
2667 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2668 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2669 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");