1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <arpa/inet.h>
12 #include <linux/pci_regs.h>
14 #include <rte_alarm.h>
15 #include <rte_atomic.h>
16 #include <rte_bus_pci.h>
17 #include <rte_byteorder.h>
18 #include <rte_common.h>
19 #include <rte_cycles.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
24 #include <rte_ethdev_pci.h>
25 #include <rte_interrupts.h>
31 #include "hns3_ethdev.h"
32 #include "hns3_logs.h"
33 #include "hns3_rxtx.h"
34 #include "hns3_regs.h"
35 #include "hns3_intr.h"
39 #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
40 #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
42 #define HNS3VF_RESET_WAIT_MS 20
43 #define HNS3VF_RESET_WAIT_CNT 2000
45 /* Reset related Registers */
46 #define HNS3_GLOBAL_RESET_BIT 0
47 #define HNS3_CORE_RESET_BIT 1
48 #define HNS3_IMP_RESET_BIT 2
49 #define HNS3_FUN_RST_ING_B 0
51 enum hns3vf_evt_cause {
52 HNS3VF_VECTOR0_EVENT_RST,
53 HNS3VF_VECTOR0_EVENT_MBX,
54 HNS3VF_VECTOR0_EVENT_OTHER,
57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
63 struct rte_ether_addr *mac_addr);
64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
65 struct rte_ether_addr *mac_addr);
66 /* set PCI bus mastering */
68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
72 rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
75 /* set the master bit */
76 reg |= PCI_COMMAND_MASTER;
78 reg &= ~(PCI_COMMAND_MASTER);
80 rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
84 * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
85 * @cap: the capability
87 * Return the address of the given capability within the PCI capability list.
90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
92 #define MAX_PCIE_CAPABILITY 48
98 rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
99 if (!(status & PCI_STATUS_CAP_LIST))
102 ttl = MAX_PCIE_CAPABILITY;
103 rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
104 while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
105 rte_pci_read_config(device, &id, sizeof(id),
106 (pos + PCI_CAP_LIST_ID));
114 rte_pci_read_config(device, &pos, sizeof(pos),
115 (pos + PCI_CAP_LIST_NEXT));
121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
126 pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
128 rte_pci_read_config(device, &control, sizeof(control),
129 (pos + PCI_MSIX_FLAGS));
131 control |= PCI_MSIX_FLAGS_ENABLE;
133 control &= ~PCI_MSIX_FLAGS_ENABLE;
134 rte_pci_write_config(device, &control, sizeof(control),
135 (pos + PCI_MSIX_FLAGS));
142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
144 /* mac address was checked by upper level interface */
145 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
148 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
149 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
150 RTE_ETHER_ADDR_LEN, false, NULL, 0);
152 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
154 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
163 /* mac address was checked by upper level interface */
164 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
167 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
168 HNS3_MBX_MAC_VLAN_UC_REMOVE,
169 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
172 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
174 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
183 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
184 struct rte_ether_addr *addr;
188 for (i = 0; i < hw->mc_addrs_num; i++) {
189 addr = &hw->mc_addrs[i];
190 /* Check if there are duplicate addresses */
191 if (rte_is_same_ether_addr(addr, mac_addr)) {
192 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
194 hns3_err(hw, "failed to add mc mac addr, same addrs"
195 "(%s) is added by the set_mc_mac_addr_list "
201 ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
203 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
205 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
213 __rte_unused uint32_t idx,
214 __rte_unused uint32_t pool)
216 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
217 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
220 rte_spinlock_lock(&hw->lock);
223 * In hns3 network engine adding UC and MC mac address with different
224 * commands with firmware. We need to determine whether the input
225 * address is a UC or a MC address to call different commands.
226 * By the way, it is recommended calling the API function named
227 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
228 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
229 * may affect the specifications of UC mac addresses.
231 if (rte_is_multicast_ether_addr(mac_addr))
232 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
234 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
236 rte_spinlock_unlock(&hw->lock);
238 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
240 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
250 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
251 /* index will be checked by upper level rte interface */
252 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
253 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
256 rte_spinlock_lock(&hw->lock);
258 if (rte_is_multicast_ether_addr(mac_addr))
259 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
261 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
263 rte_spinlock_unlock(&hw->lock);
265 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
267 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
274 struct rte_ether_addr *mac_addr)
276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
277 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
278 struct rte_ether_addr *old_addr;
279 uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
280 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
284 * It has been guaranteed that input parameter named mac_addr is valid
285 * address in the rte layer of DPDK framework.
287 old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
288 rte_spinlock_lock(&hw->lock);
289 memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
290 memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
293 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
294 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
295 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
298 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
299 * driver. When user has configured a MAC address for VF device
300 * by "ip link set ..." command based on the PF device, the hns3
301 * PF kernel ethdev driver does not allow VF driver to request
302 * reconfiguring a different default MAC address, and return
303 * -EPREM to VF driver through mailbox.
306 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
308 hns3_warn(hw, "Has permanet mac addr(%s) for vf",
311 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
313 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
318 rte_ether_addr_copy(mac_addr,
319 (struct rte_ether_addr *)hw->mac.mac_addr);
320 rte_spinlock_unlock(&hw->lock);
326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
328 struct hns3_hw *hw = &hns->hw;
329 struct rte_ether_addr *addr;
330 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
335 for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
336 addr = &hw->data->mac_addrs[i];
337 if (rte_is_zero_ether_addr(addr))
339 if (rte_is_multicast_ether_addr(addr))
340 ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
341 hns3vf_add_mc_mac_addr(hw, addr);
343 ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
344 hns3vf_add_uc_mac_addr(hw, addr);
348 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
350 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
351 "ret = %d.", del ? "remove" : "restore",
359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
360 struct rte_ether_addr *mac_addr)
362 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
365 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
366 HNS3_MBX_MAC_VLAN_MC_ADD,
367 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
370 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
372 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
381 struct rte_ether_addr *mac_addr)
383 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
386 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
387 HNS3_MBX_MAC_VLAN_MC_REMOVE,
388 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
391 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
393 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
402 struct rte_ether_addr *mc_addr_set,
405 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
406 struct rte_ether_addr *addr;
410 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
411 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
412 "invalid. valid range: 0~%d",
413 nb_mc_addr, HNS3_MC_MACADDR_NUM);
417 /* Check if input mac addresses are valid */
418 for (i = 0; i < nb_mc_addr; i++) {
419 addr = &mc_addr_set[i];
420 if (!rte_is_multicast_ether_addr(addr)) {
421 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
424 "failed to set mc mac addr, addr(%s) invalid.",
429 /* Check if there are duplicate addresses */
430 for (j = i + 1; j < nb_mc_addr; j++) {
431 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
432 rte_ether_format_addr(mac_str,
433 RTE_ETHER_ADDR_FMT_SIZE,
435 hns3_err(hw, "failed to set mc mac addr, "
436 "addrs invalid. two same addrs(%s).",
443 * Check if there are duplicate addresses between mac_addrs
446 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
447 if (rte_is_same_ether_addr(addr,
448 &hw->data->mac_addrs[j])) {
449 rte_ether_format_addr(mac_str,
450 RTE_ETHER_ADDR_FMT_SIZE,
452 hns3_err(hw, "failed to set mc mac addr, "
453 "addrs invalid. addrs(%s) has already "
454 "configured in mac_addr add API",
465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
466 struct rte_ether_addr *mc_addr_set,
469 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
470 struct rte_ether_addr *addr;
477 ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
481 rte_spinlock_lock(&hw->lock);
482 cur_addr_num = hw->mc_addrs_num;
483 for (i = 0; i < cur_addr_num; i++) {
484 num = cur_addr_num - i - 1;
485 addr = &hw->mc_addrs[num];
486 ret = hns3vf_remove_mc_mac_addr(hw, addr);
488 rte_spinlock_unlock(&hw->lock);
495 set_addr_num = (int)nb_mc_addr;
496 for (i = 0; i < set_addr_num; i++) {
497 addr = &mc_addr_set[i];
498 ret = hns3vf_add_mc_mac_addr(hw, addr);
500 rte_spinlock_unlock(&hw->lock);
504 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
507 rte_spinlock_unlock(&hw->lock);
513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
515 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
516 struct hns3_hw *hw = &hns->hw;
517 struct rte_ether_addr *addr;
522 for (i = 0; i < hw->mc_addrs_num; i++) {
523 addr = &hw->mc_addrs[i];
524 if (!rte_is_multicast_ether_addr(addr))
527 ret = hns3vf_remove_mc_mac_addr(hw, addr);
529 ret = hns3vf_add_mc_mac_addr(hw, addr);
532 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
534 hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
535 del ? "Remove" : "Restore", mac_str, ret);
542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
543 bool en_uc_pmc, bool en_mc_pmc)
545 struct hns3_mbx_vf_to_pf_cmd *req;
546 struct hns3_cmd_desc desc;
549 req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
552 * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
553 * so there are some features for promiscuous/allmulticast mode in hns3
554 * VF PMD driver as below:
555 * 1. The promiscuous/allmulticast mode can be configured successfully
556 * only based on the trusted VF device. If based on the non trusted
557 * VF device, configuring promiscuous/allmulticast mode will fail.
558 * The hns3 VF device can be confiruged as trusted device by hns3 PF
559 * kernel ethdev driver on the host by the following command:
560 * "ip link set <eth num> vf <vf id> turst on"
561 * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
562 * driver can receive the ingress and outgoing traffic. In the words,
563 * all the ingress packets, all the packets sent from the PF and
564 * other VFs on the same physical port.
565 * 3. Note: Because of the hardware constraints, By default vlan filter
566 * is enabled and couldn't be turned off based on VF device, so vlan
567 * filter is still effective even in promiscuous mode. If upper
568 * applications don't call rte_eth_dev_vlan_filter API function to
569 * set vlan based on VF device, hns3 VF PMD driver will can't receive
570 * the packets with vlan tag in promiscuoue mode.
572 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
573 req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
574 req->msg[1] = en_bc_pmc ? 1 : 0;
575 req->msg[2] = en_uc_pmc ? 1 : 0;
576 req->msg[3] = en_mc_pmc ? 1 : 0;
578 ret = hns3_cmd_send(hw, &desc, 1);
580 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
588 struct hns3_adapter *hns = dev->data->dev_private;
589 struct hns3_hw *hw = &hns->hw;
592 ret = hns3vf_set_promisc_mode(hw, true, true, true);
594 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
602 bool allmulti = dev->data->all_multicast ? true : false;
603 struct hns3_adapter *hns = dev->data->dev_private;
604 struct hns3_hw *hw = &hns->hw;
607 ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
609 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
617 struct hns3_adapter *hns = dev->data->dev_private;
618 struct hns3_hw *hw = &hns->hw;
621 if (dev->data->promiscuous)
624 ret = hns3vf_set_promisc_mode(hw, true, false, true);
626 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
634 struct hns3_adapter *hns = dev->data->dev_private;
635 struct hns3_hw *hw = &hns->hw;
638 if (dev->data->promiscuous)
641 ret = hns3vf_set_promisc_mode(hw, true, false, false);
643 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
649 hns3vf_restore_promisc(struct hns3_adapter *hns)
651 struct hns3_hw *hw = &hns->hw;
652 bool allmulti = hw->data->all_multicast ? true : false;
654 if (hw->data->promiscuous)
655 return hns3vf_set_promisc_mode(hw, true, true, true);
657 return hns3vf_set_promisc_mode(hw, true, false, allmulti);
661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
662 bool mmap, enum hns3_ring_type queue_type,
665 struct hns3_vf_bind_vector_msg bind_msg;
670 memset(&bind_msg, 0, sizeof(bind_msg));
671 code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
672 HNS3_MBX_UNMAP_RING_TO_VECTOR;
673 bind_msg.vector_id = vector_id;
675 if (queue_type == HNS3_RING_TYPE_RX)
676 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
678 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
680 bind_msg.param[0].ring_type = queue_type;
681 bind_msg.ring_num = 1;
682 bind_msg.param[0].tqp_index = queue_id;
683 op_str = mmap ? "Map" : "Unmap";
684 ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
685 sizeof(bind_msg), false, NULL, 0);
687 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
688 op_str, queue_id, bind_msg.vector_id, ret);
694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
701 * In hns3 network engine, vector 0 is always the misc interrupt of this
702 * function, vector 1~N can be used respectively for the queues of the
703 * function. Tx and Rx queues with the same number share the interrupt
704 * vector. In the initialization clearing the all hardware mapping
705 * relationship configurations between queues and interrupt vectors is
706 * needed, so some error caused by the residual configurations, such as
707 * the unexpected Tx interrupt, can be avoid. Because of the hardware
708 * constraints in hns3 hardware engine, we have to implement clearing
709 * the mapping relationship configurations by binding all queues to the
710 * last interrupt vector and reserving the last interrupt vector. This
711 * method results in a decrease of the maximum queues when upper
712 * applications call the rte_eth_dev_configure API function to enable
715 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
716 /* vec - 1: the last interrupt is reserved */
717 hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
718 for (i = 0; i < hw->intr_tqps_num; i++) {
720 * Set gap limiter and rate limiter configuration of queue's
723 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
724 HNS3_TQP_INTR_GL_DEFAULT);
725 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
726 HNS3_TQP_INTR_GL_DEFAULT);
727 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
729 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
730 HNS3_RING_TYPE_TX, i);
732 PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
733 "vector: %d, ret=%d", i, vec, ret);
737 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
738 HNS3_RING_TYPE_RX, i);
740 PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
741 "vector: %d, ret=%d", i, vec, ret);
750 hns3vf_dev_configure(struct rte_eth_dev *dev)
752 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
753 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
754 struct rte_eth_conf *conf = &dev->data->dev_conf;
755 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
756 uint16_t nb_rx_q = dev->data->nb_rx_queues;
757 uint16_t nb_tx_q = dev->data->nb_tx_queues;
758 struct rte_eth_rss_conf rss_conf;
764 * Hardware does not support individually enable/disable/reset the Tx or
765 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
766 * and Rx queues at the same time. When the numbers of Tx queues
767 * allocated by upper applications are not equal to the numbers of Rx
768 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
769 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
770 * these fake queues are imperceptible, and can not be used by upper
773 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
775 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
779 hw->adapter_state = HNS3_NIC_CONFIGURING;
780 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
781 hns3_err(hw, "setting link speed/duplex not supported");
786 /* When RSS is not configured, redirect the packet queue 0 */
787 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
788 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
789 rss_conf = conf->rx_adv_conf.rss_conf;
790 if (rss_conf.rss_key == NULL) {
791 rss_conf.rss_key = rss_cfg->key;
792 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
795 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
801 * If jumbo frames are enabled, MTU needs to be refreshed
802 * according to the maximum RX packet length.
804 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
806 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
807 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
808 * can safely assign to "uint16_t" type variable.
810 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
811 ret = hns3vf_dev_mtu_set(dev, mtu);
814 dev->data->mtu = mtu;
817 ret = hns3vf_dev_configure_vlan(dev);
821 /* config hardware GRO */
822 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
823 ret = hns3_config_gro(hw, gro_en);
827 hw->adapter_state = HNS3_NIC_CONFIGURED;
831 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
832 hw->adapter_state = HNS3_NIC_INITIALIZED;
838 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
842 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
843 sizeof(mtu), true, NULL, 0);
845 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
851 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
853 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
854 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
858 * The hns3 PF/VF devices on the same port share the hardware MTU
859 * configuration. Currently, we send mailbox to inform hns3 PF kernel
860 * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
861 * driver, there is no need to stop the port for hns3 VF device, and the
862 * MTU value issued by hns3 VF PMD driver must be less than or equal to
865 if (rte_atomic16_read(&hw->reset.resetting)) {
866 hns3_err(hw, "Failed to set mtu during resetting");
870 rte_spinlock_lock(&hw->lock);
871 ret = hns3vf_config_mtu(hw, mtu);
873 rte_spinlock_unlock(&hw->lock);
876 if (frame_size > RTE_ETHER_MAX_LEN)
877 dev->data->dev_conf.rxmode.offloads |=
878 DEV_RX_OFFLOAD_JUMBO_FRAME;
880 dev->data->dev_conf.rxmode.offloads &=
881 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
882 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
883 rte_spinlock_unlock(&hw->lock);
889 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
891 struct hns3_adapter *hns = eth_dev->data->dev_private;
892 struct hns3_hw *hw = &hns->hw;
893 uint16_t q_num = hw->tqps_num;
896 * In interrupt mode, 'max_rx_queues' is set based on the number of
897 * MSI-X interrupt resources of the hardware.
899 if (hw->data->dev_conf.intr_conf.rxq == 1)
900 q_num = hw->intr_tqps_num;
902 info->max_rx_queues = q_num;
903 info->max_tx_queues = hw->tqps_num;
904 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
905 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
906 info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
907 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
908 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
910 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
911 DEV_RX_OFFLOAD_UDP_CKSUM |
912 DEV_RX_OFFLOAD_TCP_CKSUM |
913 DEV_RX_OFFLOAD_SCTP_CKSUM |
914 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
915 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
916 DEV_RX_OFFLOAD_SCATTER |
917 DEV_RX_OFFLOAD_VLAN_STRIP |
918 DEV_RX_OFFLOAD_VLAN_FILTER |
919 DEV_RX_OFFLOAD_JUMBO_FRAME |
920 DEV_RX_OFFLOAD_RSS_HASH |
921 DEV_RX_OFFLOAD_TCP_LRO);
922 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
923 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
924 DEV_TX_OFFLOAD_IPV4_CKSUM |
925 DEV_TX_OFFLOAD_TCP_CKSUM |
926 DEV_TX_OFFLOAD_UDP_CKSUM |
927 DEV_TX_OFFLOAD_SCTP_CKSUM |
928 DEV_TX_OFFLOAD_MULTI_SEGS |
929 DEV_TX_OFFLOAD_TCP_TSO |
930 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
931 DEV_TX_OFFLOAD_GRE_TNL_TSO |
932 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
933 info->tx_queue_offload_capa |
934 hns3_txvlan_cap_get(hw));
936 info->rx_desc_lim = (struct rte_eth_desc_lim) {
937 .nb_max = HNS3_MAX_RING_DESC,
938 .nb_min = HNS3_MIN_RING_DESC,
939 .nb_align = HNS3_ALIGN_RING_DESC,
942 info->tx_desc_lim = (struct rte_eth_desc_lim) {
943 .nb_max = HNS3_MAX_RING_DESC,
944 .nb_min = HNS3_MIN_RING_DESC,
945 .nb_align = HNS3_ALIGN_RING_DESC,
946 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
947 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
950 info->default_rxconf = (struct rte_eth_rxconf) {
952 * If there are no available Rx buffer descriptors, incoming
953 * packets are always dropped by hardware based on hns3 network
959 info->vmdq_queue_num = 0;
961 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
962 info->hash_key_size = HNS3_RSS_KEY_SIZE;
963 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
964 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
965 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
971 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
973 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
977 hns3vf_disable_irq0(struct hns3_hw *hw)
979 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
983 hns3vf_enable_irq0(struct hns3_hw *hw)
985 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
988 static enum hns3vf_evt_cause
989 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
991 struct hns3_hw *hw = &hns->hw;
992 enum hns3vf_evt_cause ret;
993 uint32_t cmdq_stat_reg;
994 uint32_t rst_ing_reg;
997 /* Fetch the events from their corresponding regs */
998 cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1000 if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1001 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1002 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1003 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1004 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1005 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1006 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1007 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1009 hw->reset.stats.global_cnt++;
1010 hns3_warn(hw, "Global reset detected, clear reset status");
1012 hns3_schedule_delayed_reset(hns);
1013 hns3_warn(hw, "Global reset detected, don't clear reset status");
1016 ret = HNS3VF_VECTOR0_EVENT_RST;
1020 /* Check for vector0 mailbox(=CMDQ RX) event source */
1021 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1022 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1023 ret = HNS3VF_VECTOR0_EVENT_MBX;
1028 ret = HNS3VF_VECTOR0_EVENT_OTHER;
1036 hns3vf_interrupt_handler(void *param)
1038 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1039 struct hns3_adapter *hns = dev->data->dev_private;
1040 struct hns3_hw *hw = &hns->hw;
1041 enum hns3vf_evt_cause event_cause;
1044 if (hw->irq_thread_id == 0)
1045 hw->irq_thread_id = pthread_self();
1047 /* Disable interrupt */
1048 hns3vf_disable_irq0(hw);
1050 /* Read out interrupt causes */
1051 event_cause = hns3vf_check_event_cause(hns, &clearval);
1053 switch (event_cause) {
1054 case HNS3VF_VECTOR0_EVENT_RST:
1055 hns3_schedule_reset(hns);
1057 case HNS3VF_VECTOR0_EVENT_MBX:
1058 hns3_dev_handle_mbx_msg(hw);
1064 /* Clear interrupt causes */
1065 hns3vf_clear_event_cause(hw, clearval);
1067 /* Enable interrupt */
1068 hns3vf_enable_irq0(hw);
1072 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1074 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1075 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1076 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1080 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1082 struct hns3_dev_specs_0_cmd *req0;
1084 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1086 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1087 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1088 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1092 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1094 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1098 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1099 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1101 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1103 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1105 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1109 hns3vf_parse_dev_specifications(hw, desc);
1115 hns3vf_get_capability(struct hns3_hw *hw)
1117 struct rte_pci_device *pci_dev;
1118 struct rte_eth_dev *eth_dev;
1122 eth_dev = &rte_eth_devices[hw->data->port_id];
1123 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1125 /* Get PCI revision id */
1126 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1127 HNS3_PCI_REVISION_ID);
1128 if (ret != HNS3_PCI_REVISION_ID_LEN) {
1129 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1133 hw->revision = revision;
1135 if (revision < PCI_REVISION_ID_HIP09_A) {
1136 hns3vf_set_default_dev_specifications(hw);
1140 ret = hns3vf_query_dev_specifications(hw);
1143 "failed to query dev specifications, ret = %d",
1152 hns3vf_check_tqp_info(struct hns3_hw *hw)
1156 tqps_num = hw->tqps_num;
1157 if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1158 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1160 tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1164 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1169 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1174 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1175 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1176 true, &resp_msg, sizeof(resp_msg));
1178 if (ret == -ETIME) {
1180 * Getting current port based VLAN state from PF driver
1181 * will not affect VF driver's basic function. Because
1182 * the VF driver relies on hns3 PF kernel ether driver,
1183 * to avoid introducing compatibility issues with older
1184 * version of PF driver, no failure will be returned
1185 * when the return value is ETIME. This return value has
1186 * the following scenarios:
1187 * 1) Firmware didn't return the results in time
1188 * 2) the result return by firmware is timeout
1189 * 3) the older version of kernel side PF driver does
1190 * not support this mailbox message.
1191 * For scenarios 1 and 2, it is most likely that a
1192 * hardware error has occurred, or a hardware reset has
1193 * occurred. In this case, these errors will be caught
1194 * by other functions.
1196 PMD_INIT_LOG(WARNING,
1197 "failed to get PVID state for timeout, maybe "
1198 "kernel side PF driver doesn't support this "
1199 "mailbox message, or firmware didn't respond.");
1200 resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1202 PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1207 hw->port_base_vlan_cfg.state = resp_msg ?
1208 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1213 hns3vf_get_queue_info(struct hns3_hw *hw)
1215 #define HNS3VF_TQPS_RSS_INFO_LEN 6
1216 uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1219 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1220 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1222 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1226 memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1227 memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1229 return hns3vf_check_tqp_info(hw);
1233 hns3vf_get_queue_depth(struct hns3_hw *hw)
1235 #define HNS3VF_TQPS_DEPTH_INFO_LEN 4
1236 uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1239 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1240 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1242 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1247 memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1248 memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1254 hns3vf_get_tc_info(struct hns3_hw *hw)
1259 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1260 true, &resp_msg, sizeof(resp_msg));
1262 hns3_err(hw, "VF request to get TC info from PF failed %d",
1267 hw->hw_tc_map = resp_msg;
1273 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1275 uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1278 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1279 true, host_mac, RTE_ETHER_ADDR_LEN);
1281 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1285 memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1291 hns3vf_get_configuration(struct hns3_hw *hw)
1295 hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1296 hw->rss_dis_flag = false;
1298 /* Get device capability */
1299 ret = hns3vf_get_capability(hw);
1301 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1305 /* Get queue configuration from PF */
1306 ret = hns3vf_get_queue_info(hw);
1310 /* Get queue depth info from PF */
1311 ret = hns3vf_get_queue_depth(hw);
1315 /* Get user defined VF MAC addr from PF */
1316 ret = hns3vf_get_host_mac_addr(hw);
1320 ret = hns3vf_get_port_base_vlan_filter_state(hw);
1324 /* Get tc configuration from PF */
1325 return hns3vf_get_tc_info(hw);
1329 hns3vf_set_tc_info(struct hns3_adapter *hns)
1331 struct hns3_hw *hw = &hns->hw;
1332 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1333 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1337 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1338 if (hw->hw_tc_map & BIT(i))
1341 if (nb_rx_q < hw->num_tc) {
1342 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1343 nb_rx_q, hw->num_tc);
1347 if (nb_tx_q < hw->num_tc) {
1348 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1349 nb_tx_q, hw->num_tc);
1353 hns3_set_rss_size(hw, nb_rx_q);
1354 hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1360 hns3vf_request_link_info(struct hns3_hw *hw)
1365 if (rte_atomic16_read(&hw->reset.resetting))
1367 ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1368 &resp_msg, sizeof(resp_msg));
1370 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1374 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1376 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1377 struct hns3_hw *hw = &hns->hw;
1378 uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1379 uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1380 uint8_t is_kill = on ? 0 : 1;
1382 msg_data[0] = is_kill;
1383 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1384 memcpy(&msg_data[3], &proto, sizeof(proto));
1386 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1387 msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1392 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1394 struct hns3_adapter *hns = dev->data->dev_private;
1395 struct hns3_hw *hw = &hns->hw;
1398 if (rte_atomic16_read(&hw->reset.resetting)) {
1400 "vf set vlan id failed during resetting, vlan_id =%u",
1404 rte_spinlock_lock(&hw->lock);
1405 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1406 rte_spinlock_unlock(&hw->lock);
1408 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1415 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1420 msg_data = enable ? 1 : 0;
1421 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1422 &msg_data, sizeof(msg_data), false, NULL, 0);
1424 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1430 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1432 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1433 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1434 unsigned int tmp_mask;
1437 if (rte_atomic16_read(&hw->reset.resetting)) {
1438 hns3_err(hw, "vf set vlan offload failed during resetting, "
1439 "mask = 0x%x", mask);
1443 tmp_mask = (unsigned int)mask;
1444 /* Vlan stripping setting */
1445 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1446 rte_spinlock_lock(&hw->lock);
1447 /* Enable or disable VLAN stripping */
1448 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1449 ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1451 ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1452 rte_spinlock_unlock(&hw->lock);
1459 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1461 struct rte_vlan_filter_conf *vfc;
1462 struct hns3_hw *hw = &hns->hw;
1469 vfc = &hw->data->vlan_filter_conf;
1470 for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1471 if (vfc->ids[i] == 0)
1476 * 64 means the num bits of ids, one bit corresponds to
1480 /* count trailing zeroes */
1481 vbit = ~ids & (ids - 1);
1482 /* clear least significant bit set */
1483 ids ^= (ids ^ (ids - 1)) ^ vbit;
1488 ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1491 "VF handle vlan table failed, ret =%d, on = %d",
1502 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1504 return hns3vf_handle_all_vlan_table(hns, 0);
1508 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1510 struct hns3_hw *hw = &hns->hw;
1511 struct rte_eth_conf *dev_conf;
1515 dev_conf = &hw->data->dev_conf;
1516 en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1518 ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1520 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1526 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1528 struct hns3_adapter *hns = dev->data->dev_private;
1529 struct rte_eth_dev_data *data = dev->data;
1530 struct hns3_hw *hw = &hns->hw;
1533 if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1534 data->dev_conf.txmode.hw_vlan_reject_untagged ||
1535 data->dev_conf.txmode.hw_vlan_insert_pvid) {
1536 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1537 "or hw_vlan_insert_pvid is not support!");
1540 /* Apply vlan offload setting */
1541 ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1543 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1549 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1553 msg_data = alive ? 1 : 0;
1554 return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1555 sizeof(msg_data), false, NULL, 0);
1559 hns3vf_keep_alive_handler(void *param)
1561 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1562 struct hns3_adapter *hns = eth_dev->data->dev_private;
1563 struct hns3_hw *hw = &hns->hw;
1567 ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1568 false, &respmsg, sizeof(uint8_t));
1570 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1573 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1578 hns3vf_service_handler(void *param)
1580 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1581 struct hns3_adapter *hns = eth_dev->data->dev_private;
1582 struct hns3_hw *hw = &hns->hw;
1585 * The query link status and reset processing are executed in the
1586 * interrupt thread.When the IMP reset occurs, IMP will not respond,
1587 * and the query operation will time out after 30ms. In the case of
1588 * multiple PF/VFs, each query failure timeout causes the IMP reset
1589 * interrupt to fail to respond within 100ms.
1590 * Before querying the link status, check whether there is a reset
1591 * pending, and if so, abandon the query.
1593 if (!hns3vf_is_reset_pending(hns))
1594 hns3vf_request_link_info(hw);
1596 hns3_warn(hw, "Cancel the query when reset is pending");
1598 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1603 hns3_query_vf_resource(struct hns3_hw *hw)
1605 struct hns3_vf_res_cmd *req;
1606 struct hns3_cmd_desc desc;
1610 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1611 ret = hns3_cmd_send(hw, &desc, 1);
1613 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1617 req = (struct hns3_vf_res_cmd *)desc.data;
1618 num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1619 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1620 if (num_msi < HNS3_MIN_VECTOR_NUM) {
1621 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1622 num_msi, HNS3_MIN_VECTOR_NUM);
1626 hw->num_msi = num_msi;
1632 hns3vf_init_hardware(struct hns3_adapter *hns)
1634 struct hns3_hw *hw = &hns->hw;
1635 uint16_t mtu = hw->data->mtu;
1638 ret = hns3vf_set_promisc_mode(hw, true, false, false);
1642 ret = hns3vf_config_mtu(hw, mtu);
1644 goto err_init_hardware;
1646 ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1648 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1649 goto err_init_hardware;
1652 ret = hns3_config_gro(hw, false);
1654 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1655 goto err_init_hardware;
1659 * In the initialization clearing the all hardware mapping relationship
1660 * configurations between queues and interrupt vectors is needed, so
1661 * some error caused by the residual configurations, such as the
1662 * unexpected interrupt, can be avoid.
1664 ret = hns3vf_init_ring_with_vector(hw);
1666 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1667 goto err_init_hardware;
1670 ret = hns3vf_set_alive(hw, true);
1672 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1673 goto err_init_hardware;
1676 hns3vf_request_link_info(hw);
1680 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1685 hns3vf_clear_vport_list(struct hns3_hw *hw)
1687 return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1688 HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1693 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1695 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1696 struct hns3_adapter *hns = eth_dev->data->dev_private;
1697 struct hns3_hw *hw = &hns->hw;
1700 PMD_INIT_FUNC_TRACE();
1702 /* Get hardware io base address from pcie BAR2 IO space */
1703 hw->io_base = pci_dev->mem_resource[2].addr;
1705 /* Firmware command queue initialize */
1706 ret = hns3_cmd_init_queue(hw);
1708 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1709 goto err_cmd_init_queue;
1712 /* Firmware command initialize */
1713 ret = hns3_cmd_init(hw);
1715 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1719 /* Get VF resource */
1720 ret = hns3_query_vf_resource(hw);
1724 rte_spinlock_init(&hw->mbx_resp.lock);
1726 hns3vf_clear_event_cause(hw, 0);
1728 ret = rte_intr_callback_register(&pci_dev->intr_handle,
1729 hns3vf_interrupt_handler, eth_dev);
1731 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1732 goto err_intr_callback_register;
1735 /* Enable interrupt */
1736 rte_intr_enable(&pci_dev->intr_handle);
1737 hns3vf_enable_irq0(hw);
1739 /* Get configuration from PF */
1740 ret = hns3vf_get_configuration(hw);
1742 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1743 goto err_get_config;
1747 * The hns3 PF ethdev driver in kernel support setting VF MAC address
1748 * on the host by "ip link set ..." command. To avoid some incorrect
1749 * scenes, for example, hns3 VF PMD driver fails to receive and send
1750 * packets after user configure the MAC address by using the
1751 * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1752 * address strategy as the hns3 kernel ethdev driver in the
1753 * initialization. If user configure a MAC address by the ip command
1754 * for VF device, then hns3 VF PMD driver will start with it, otherwise
1755 * start with a random MAC address in the initialization.
1757 ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1759 rte_eth_random_addr(hw->mac.mac_addr);
1761 ret = hns3vf_clear_vport_list(hw);
1763 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1764 goto err_get_config;
1767 ret = hns3vf_init_hardware(hns);
1769 goto err_get_config;
1771 hns3_set_default_rss_args(hw);
1776 hns3vf_disable_irq0(hw);
1777 rte_intr_disable(&pci_dev->intr_handle);
1778 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1780 err_intr_callback_register:
1782 hns3_cmd_uninit(hw);
1783 hns3_cmd_destroy_queue(hw);
1791 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1793 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1794 struct hns3_adapter *hns = eth_dev->data->dev_private;
1795 struct hns3_hw *hw = &hns->hw;
1797 PMD_INIT_FUNC_TRACE();
1799 hns3_rss_uninit(hns);
1800 (void)hns3_config_gro(hw, false);
1801 (void)hns3vf_set_alive(hw, false);
1802 (void)hns3vf_set_promisc_mode(hw, false, false, false);
1803 hns3vf_disable_irq0(hw);
1804 rte_intr_disable(&pci_dev->intr_handle);
1805 hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1807 hns3_cmd_uninit(hw);
1808 hns3_cmd_destroy_queue(hw);
1813 hns3vf_do_stop(struct hns3_adapter *hns)
1815 struct hns3_hw *hw = &hns->hw;
1818 hw->mac.link_status = ETH_LINK_DOWN;
1820 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1821 hns3vf_configure_mac_addr(hns, true);
1824 reset_queue = false;
1825 return hns3_stop_queues(hns, reset_queue);
1829 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1831 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1833 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1834 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1835 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1838 if (dev->data->dev_conf.intr_conf.rxq == 0)
1841 /* unmap the ring with vector */
1842 if (rte_intr_allow_others(intr_handle)) {
1843 vec = RTE_INTR_VEC_RXTX_OFFSET;
1844 base = RTE_INTR_VEC_RXTX_OFFSET;
1846 if (rte_intr_dp_is_en(intr_handle)) {
1847 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1848 (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1851 if (vec < base + intr_handle->nb_efd - 1)
1855 /* Clean datapath event and queue/vec mapping */
1856 rte_intr_efd_disable(intr_handle);
1857 if (intr_handle->intr_vec) {
1858 rte_free(intr_handle->intr_vec);
1859 intr_handle->intr_vec = NULL;
1864 hns3vf_dev_stop(struct rte_eth_dev *dev)
1866 struct hns3_adapter *hns = dev->data->dev_private;
1867 struct hns3_hw *hw = &hns->hw;
1869 PMD_INIT_FUNC_TRACE();
1871 hw->adapter_state = HNS3_NIC_STOPPING;
1872 hns3_set_rxtx_function(dev);
1874 /* Disable datapath on secondary process. */
1875 hns3_mp_req_stop_rxtx(dev);
1876 /* Prevent crashes when queues are still in use. */
1877 rte_delay_ms(hw->tqps_num);
1879 rte_spinlock_lock(&hw->lock);
1880 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1881 hns3vf_do_stop(hns);
1882 hns3vf_unmap_rx_interrupt(dev);
1883 hns3_dev_release_mbufs(hns);
1884 hw->adapter_state = HNS3_NIC_CONFIGURED;
1886 rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1887 rte_spinlock_unlock(&hw->lock);
1891 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1893 struct hns3_adapter *hns = eth_dev->data->dev_private;
1894 struct hns3_hw *hw = &hns->hw;
1896 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1899 if (hw->adapter_state == HNS3_NIC_STARTED)
1900 hns3vf_dev_stop(eth_dev);
1902 hw->adapter_state = HNS3_NIC_CLOSING;
1903 hns3_reset_abort(hns);
1904 hw->adapter_state = HNS3_NIC_CLOSED;
1905 rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1906 hns3vf_configure_all_mc_mac_addr(hns, true);
1907 hns3vf_remove_all_vlan_table(hns);
1908 hns3vf_uninit_vf(eth_dev);
1909 hns3_free_all_queues(eth_dev);
1910 rte_free(hw->reset.wait_data);
1911 rte_free(eth_dev->process_private);
1912 eth_dev->process_private = NULL;
1913 hns3_mp_uninit_primary();
1914 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1918 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1921 struct hns3_adapter *hns = eth_dev->data->dev_private;
1922 struct hns3_hw *hw = &hns->hw;
1923 uint32_t version = hw->fw_version;
1926 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1927 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1928 HNS3_FW_VERSION_BYTE3_S),
1929 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1930 HNS3_FW_VERSION_BYTE2_S),
1931 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1932 HNS3_FW_VERSION_BYTE1_S),
1933 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1934 HNS3_FW_VERSION_BYTE0_S));
1935 ret += 1; /* add the size of '\0' */
1936 if (fw_size < (uint32_t)ret)
1943 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1944 __rte_unused int wait_to_complete)
1946 struct hns3_adapter *hns = eth_dev->data->dev_private;
1947 struct hns3_hw *hw = &hns->hw;
1948 struct hns3_mac *mac = &hw->mac;
1949 struct rte_eth_link new_link;
1951 memset(&new_link, 0, sizeof(new_link));
1952 switch (mac->link_speed) {
1953 case ETH_SPEED_NUM_10M:
1954 case ETH_SPEED_NUM_100M:
1955 case ETH_SPEED_NUM_1G:
1956 case ETH_SPEED_NUM_10G:
1957 case ETH_SPEED_NUM_25G:
1958 case ETH_SPEED_NUM_40G:
1959 case ETH_SPEED_NUM_50G:
1960 case ETH_SPEED_NUM_100G:
1961 case ETH_SPEED_NUM_200G:
1962 new_link.link_speed = mac->link_speed;
1965 new_link.link_speed = ETH_SPEED_NUM_100M;
1969 new_link.link_duplex = mac->link_duplex;
1970 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1971 new_link.link_autoneg =
1972 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1974 return rte_eth_linkstatus_set(eth_dev, &new_link);
1978 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1980 struct hns3_hw *hw = &hns->hw;
1983 ret = hns3vf_set_tc_info(hns);
1987 ret = hns3_start_queues(hns, reset_queue);
1989 hns3_err(hw, "Failed to start queues: %d", ret);
1995 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1997 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1998 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1999 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2000 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2001 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2002 uint32_t intr_vector;
2006 if (dev->data->dev_conf.intr_conf.rxq == 0)
2009 /* disable uio/vfio intr/eventfd mapping */
2010 rte_intr_disable(intr_handle);
2012 /* check and configure queue intr-vector mapping */
2013 if (rte_intr_cap_multiple(intr_handle) ||
2014 !RTE_ETH_DEV_SRIOV(dev).active) {
2015 intr_vector = hw->used_rx_queues;
2016 /* It creates event fd for each intr vector when MSIX is used */
2017 if (rte_intr_efd_enable(intr_handle, intr_vector))
2020 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2021 intr_handle->intr_vec =
2022 rte_zmalloc("intr_vec",
2023 hw->used_rx_queues * sizeof(int), 0);
2024 if (intr_handle->intr_vec == NULL) {
2025 hns3_err(hw, "Failed to allocate %d rx_queues"
2026 " intr_vec", hw->used_rx_queues);
2028 goto vf_alloc_intr_vec_error;
2032 if (rte_intr_allow_others(intr_handle)) {
2033 vec = RTE_INTR_VEC_RXTX_OFFSET;
2034 base = RTE_INTR_VEC_RXTX_OFFSET;
2036 if (rte_intr_dp_is_en(intr_handle)) {
2037 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2038 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2042 goto vf_bind_vector_error;
2043 intr_handle->intr_vec[q_id] = vec;
2044 if (vec < base + intr_handle->nb_efd - 1)
2048 rte_intr_enable(intr_handle);
2051 vf_bind_vector_error:
2052 rte_intr_efd_disable(intr_handle);
2053 if (intr_handle->intr_vec) {
2054 free(intr_handle->intr_vec);
2055 intr_handle->intr_vec = NULL;
2058 vf_alloc_intr_vec_error:
2059 rte_intr_efd_disable(intr_handle);
2064 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2066 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2067 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2068 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2072 if (dev->data->dev_conf.intr_conf.rxq == 0)
2075 if (rte_intr_dp_is_en(intr_handle)) {
2076 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2077 ret = hns3vf_bind_ring_with_vector(hw,
2078 intr_handle->intr_vec[q_id], true,
2079 HNS3_RING_TYPE_RX, q_id);
2089 hns3vf_restore_filter(struct rte_eth_dev *dev)
2091 hns3_restore_rss_filter(dev);
2095 hns3vf_dev_start(struct rte_eth_dev *dev)
2097 struct hns3_adapter *hns = dev->data->dev_private;
2098 struct hns3_hw *hw = &hns->hw;
2101 PMD_INIT_FUNC_TRACE();
2102 if (rte_atomic16_read(&hw->reset.resetting))
2105 rte_spinlock_lock(&hw->lock);
2106 hw->adapter_state = HNS3_NIC_STARTING;
2107 ret = hns3vf_do_start(hns, true);
2109 hw->adapter_state = HNS3_NIC_CONFIGURED;
2110 rte_spinlock_unlock(&hw->lock);
2113 ret = hns3vf_map_rx_interrupt(dev);
2115 hw->adapter_state = HNS3_NIC_CONFIGURED;
2116 rte_spinlock_unlock(&hw->lock);
2119 hw->adapter_state = HNS3_NIC_STARTED;
2120 rte_spinlock_unlock(&hw->lock);
2122 hns3_set_rxtx_function(dev);
2123 hns3_mp_req_start_rxtx(dev);
2124 rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2126 hns3vf_restore_filter(dev);
2128 /* Enable interrupt of all rx queues before enabling queues */
2129 hns3_dev_all_rx_queue_intr_enable(hw, true);
2131 * When finished the initialization, enable queues to receive/transmit
2134 hns3_enable_all_queues(hw, true);
2140 is_vf_reset_done(struct hns3_hw *hw)
2142 #define HNS3_FUN_RST_ING_BITS \
2143 (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2144 BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2145 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2146 BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2150 if (hw->reset.level == HNS3_VF_RESET) {
2151 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2152 if (val & HNS3_VF_RST_ING_BIT)
2155 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2156 if (val & HNS3_FUN_RST_ING_BITS)
2163 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2165 struct hns3_hw *hw = &hns->hw;
2166 enum hns3_reset_level reset;
2168 hns3vf_check_event_cause(hns, NULL);
2169 reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2170 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2171 hns3_warn(hw, "High level reset %d is pending", reset);
2178 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2180 struct hns3_hw *hw = &hns->hw;
2181 struct hns3_wait_data *wait_data = hw->reset.wait_data;
2184 if (wait_data->result == HNS3_WAIT_SUCCESS) {
2186 * After vf reset is ready, the PF may not have completed
2187 * the reset processing. The vf sending mbox to PF may fail
2188 * during the pf reset, so it is better to add extra delay.
2190 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2191 hw->reset.level == HNS3_FLR_RESET)
2193 /* Reset retry process, no need to add extra delay. */
2194 if (hw->reset.attempts)
2196 if (wait_data->check_completion == NULL)
2199 wait_data->check_completion = NULL;
2200 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2201 wait_data->count = 1;
2202 wait_data->result = HNS3_WAIT_REQUEST;
2203 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2205 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2207 } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2208 gettimeofday(&tv, NULL);
2209 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2210 tv.tv_sec, tv.tv_usec);
2212 } else if (wait_data->result == HNS3_WAIT_REQUEST)
2215 wait_data->hns = hns;
2216 wait_data->check_completion = is_vf_reset_done;
2217 wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2218 HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2219 wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2220 wait_data->count = HNS3VF_RESET_WAIT_CNT;
2221 wait_data->result = HNS3_WAIT_REQUEST;
2222 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2227 hns3vf_prepare_reset(struct hns3_adapter *hns)
2229 struct hns3_hw *hw = &hns->hw;
2232 if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2233 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2236 rte_atomic16_set(&hw->reset.disable_cmd, 1);
2242 hns3vf_stop_service(struct hns3_adapter *hns)
2244 struct hns3_hw *hw = &hns->hw;
2245 struct rte_eth_dev *eth_dev;
2247 eth_dev = &rte_eth_devices[hw->data->port_id];
2248 if (hw->adapter_state == HNS3_NIC_STARTED)
2249 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2250 hw->mac.link_status = ETH_LINK_DOWN;
2252 hns3_set_rxtx_function(eth_dev);
2254 /* Disable datapath on secondary process. */
2255 hns3_mp_req_stop_rxtx(eth_dev);
2256 rte_delay_ms(hw->tqps_num);
2258 rte_spinlock_lock(&hw->lock);
2259 if (hw->adapter_state == HNS3_NIC_STARTED ||
2260 hw->adapter_state == HNS3_NIC_STOPPING) {
2261 hns3vf_do_stop(hns);
2262 hw->reset.mbuf_deferred_free = true;
2264 hw->reset.mbuf_deferred_free = false;
2267 * It is cumbersome for hardware to pick-and-choose entries for deletion
2268 * from table space. Hence, for function reset software intervention is
2269 * required to delete the entries.
2271 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2272 hns3vf_configure_all_mc_mac_addr(hns, true);
2273 rte_spinlock_unlock(&hw->lock);
2279 hns3vf_start_service(struct hns3_adapter *hns)
2281 struct hns3_hw *hw = &hns->hw;
2282 struct rte_eth_dev *eth_dev;
2284 eth_dev = &rte_eth_devices[hw->data->port_id];
2285 hns3_set_rxtx_function(eth_dev);
2286 hns3_mp_req_start_rxtx(eth_dev);
2287 if (hw->adapter_state == HNS3_NIC_STARTED) {
2288 hns3vf_service_handler(eth_dev);
2290 /* Enable interrupt of all rx queues before enabling queues */
2291 hns3_dev_all_rx_queue_intr_enable(hw, true);
2293 * When finished the initialization, enable queues to receive
2294 * and transmit packets.
2296 hns3_enable_all_queues(hw, true);
2303 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2305 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2306 struct rte_ether_addr *hw_mac;
2310 * The hns3 PF ethdev driver in kernel support setting VF MAC address
2311 * on the host by "ip link set ..." command. If the hns3 PF kernel
2312 * ethdev driver sets the MAC address for VF device after the
2313 * initialization of the related VF device, the PF driver will notify
2314 * VF driver to reset VF device to make the new MAC address effective
2315 * immediately. The hns3 VF PMD driver should check whether the MAC
2316 * address has been changed by the PF kernel ethdev driver, if changed
2317 * VF driver should configure hardware using the new MAC address in the
2318 * recovering hardware configuration stage of the reset process.
2320 ret = hns3vf_get_host_mac_addr(hw);
2324 hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2325 ret = rte_is_zero_ether_addr(hw_mac);
2327 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2329 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2331 rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2332 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2333 &hw->data->mac_addrs[0]);
2334 hns3_warn(hw, "Default MAC address has been changed to:"
2335 " %s by the host PF kernel ethdev driver",
2344 hns3vf_restore_conf(struct hns3_adapter *hns)
2346 struct hns3_hw *hw = &hns->hw;
2349 ret = hns3vf_check_default_mac_change(hw);
2353 ret = hns3vf_configure_mac_addr(hns, false);
2357 ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2361 ret = hns3vf_restore_promisc(hns);
2363 goto err_vlan_table;
2365 ret = hns3vf_restore_vlan_conf(hns);
2367 goto err_vlan_table;
2369 ret = hns3vf_get_port_base_vlan_filter_state(hw);
2371 goto err_vlan_table;
2373 ret = hns3vf_restore_rx_interrupt(hw);
2375 goto err_vlan_table;
2377 ret = hns3_restore_gro_conf(hw);
2379 goto err_vlan_table;
2381 if (hw->adapter_state == HNS3_NIC_STARTED) {
2382 ret = hns3vf_do_start(hns, false);
2384 goto err_vlan_table;
2385 hns3_info(hw, "hns3vf dev restart successful!");
2386 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2387 hw->adapter_state = HNS3_NIC_CONFIGURED;
2391 hns3vf_configure_all_mc_mac_addr(hns, true);
2393 hns3vf_configure_mac_addr(hns, true);
2397 static enum hns3_reset_level
2398 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2400 enum hns3_reset_level reset_level;
2402 /* return the highest priority reset level amongst all */
2403 if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2404 reset_level = HNS3_VF_RESET;
2405 else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2406 reset_level = HNS3_VF_FULL_RESET;
2407 else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2408 reset_level = HNS3_VF_PF_FUNC_RESET;
2409 else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2410 reset_level = HNS3_VF_FUNC_RESET;
2411 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2412 reset_level = HNS3_FLR_RESET;
2414 reset_level = HNS3_NONE_RESET;
2416 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2417 return HNS3_NONE_RESET;
2423 hns3vf_reset_service(void *param)
2425 struct hns3_adapter *hns = (struct hns3_adapter *)param;
2426 struct hns3_hw *hw = &hns->hw;
2427 enum hns3_reset_level reset_level;
2428 struct timeval tv_delta;
2429 struct timeval tv_start;
2434 * The interrupt is not triggered within the delay time.
2435 * The interrupt may have been lost. It is necessary to handle
2436 * the interrupt to recover from the error.
2438 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2439 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2440 hns3_err(hw, "Handling interrupts in delayed tasks");
2441 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2442 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2443 if (reset_level == HNS3_NONE_RESET) {
2444 hns3_err(hw, "No reset level is set, try global reset");
2445 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2448 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2451 * Hardware reset has been notified, we now have to poll & check if
2452 * hardware has actually completed the reset sequence.
2454 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2455 if (reset_level != HNS3_NONE_RESET) {
2456 gettimeofday(&tv_start, NULL);
2457 hns3_reset_process(hns, reset_level);
2458 gettimeofday(&tv, NULL);
2459 timersub(&tv, &tv_start, &tv_delta);
2460 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2461 tv_delta.tv_usec / USEC_PER_MSEC;
2462 if (msec > HNS3_RESET_PROCESS_MS)
2463 hns3_err(hw, "%d handle long time delta %" PRIx64
2464 " ms time=%ld.%.6ld",
2465 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2470 hns3vf_reinit_dev(struct hns3_adapter *hns)
2472 struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2473 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2474 struct hns3_hw *hw = &hns->hw;
2477 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2478 rte_intr_disable(&pci_dev->intr_handle);
2479 hns3vf_set_bus_master(pci_dev, true);
2482 /* Firmware command initialize */
2483 ret = hns3_cmd_init(hw);
2485 hns3_err(hw, "Failed to init cmd: %d", ret);
2489 if (hw->reset.level == HNS3_VF_FULL_RESET) {
2491 * UIO enables msix by writing the pcie configuration space
2492 * vfio_pci enables msix in rte_intr_enable.
2494 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2495 pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2496 if (hns3vf_enable_msix(pci_dev, true))
2497 hns3_err(hw, "Failed to enable msix");
2500 rte_intr_enable(&pci_dev->intr_handle);
2503 ret = hns3_reset_all_queues(hns);
2505 hns3_err(hw, "Failed to reset all queues: %d", ret);
2509 ret = hns3vf_init_hardware(hns);
2511 hns3_err(hw, "Failed to init hardware: %d", ret);
2518 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2519 .dev_start = hns3vf_dev_start,
2520 .dev_stop = hns3vf_dev_stop,
2521 .dev_close = hns3vf_dev_close,
2522 .mtu_set = hns3vf_dev_mtu_set,
2523 .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2524 .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2525 .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2526 .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2527 .stats_get = hns3_stats_get,
2528 .stats_reset = hns3_stats_reset,
2529 .xstats_get = hns3_dev_xstats_get,
2530 .xstats_get_names = hns3_dev_xstats_get_names,
2531 .xstats_reset = hns3_dev_xstats_reset,
2532 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
2533 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2534 .dev_infos_get = hns3vf_dev_infos_get,
2535 .fw_version_get = hns3vf_fw_version_get,
2536 .rx_queue_setup = hns3_rx_queue_setup,
2537 .tx_queue_setup = hns3_tx_queue_setup,
2538 .rx_queue_release = hns3_dev_rx_queue_release,
2539 .tx_queue_release = hns3_dev_tx_queue_release,
2540 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
2541 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
2542 .rxq_info_get = hns3_rxq_info_get,
2543 .txq_info_get = hns3_txq_info_get,
2544 .dev_configure = hns3vf_dev_configure,
2545 .mac_addr_add = hns3vf_add_mac_addr,
2546 .mac_addr_remove = hns3vf_remove_mac_addr,
2547 .mac_addr_set = hns3vf_set_default_mac_addr,
2548 .set_mc_addr_list = hns3vf_set_mc_mac_addr_list,
2549 .link_update = hns3vf_dev_link_update,
2550 .rss_hash_update = hns3_dev_rss_hash_update,
2551 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
2552 .reta_update = hns3_dev_rss_reta_update,
2553 .reta_query = hns3_dev_rss_reta_query,
2554 .filter_ctrl = hns3_dev_filter_ctrl,
2555 .vlan_filter_set = hns3vf_vlan_filter_set,
2556 .vlan_offload_set = hns3vf_vlan_offload_set,
2557 .get_reg = hns3_get_regs,
2558 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2561 static const struct hns3_reset_ops hns3vf_reset_ops = {
2562 .reset_service = hns3vf_reset_service,
2563 .stop_service = hns3vf_stop_service,
2564 .prepare_reset = hns3vf_prepare_reset,
2565 .wait_hardware_ready = hns3vf_wait_hardware_ready,
2566 .reinit_dev = hns3vf_reinit_dev,
2567 .restore_conf = hns3vf_restore_conf,
2568 .start_service = hns3vf_start_service,
2572 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2574 struct hns3_adapter *hns = eth_dev->data->dev_private;
2575 struct hns3_hw *hw = &hns->hw;
2578 PMD_INIT_FUNC_TRACE();
2580 eth_dev->process_private = (struct hns3_process_private *)
2581 rte_zmalloc_socket("hns3_filter_list",
2582 sizeof(struct hns3_process_private),
2583 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2584 if (eth_dev->process_private == NULL) {
2585 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2589 /* initialize flow filter lists */
2590 hns3_filterlist_init(eth_dev);
2592 hns3_set_rxtx_function(eth_dev);
2593 eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2594 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2595 ret = hns3_mp_init_secondary();
2597 PMD_INIT_LOG(ERR, "Failed to init for secondary "
2598 "process, ret = %d", ret);
2599 goto err_mp_init_secondary;
2602 hw->secondary_cnt++;
2606 ret = hns3_mp_init_primary();
2609 "Failed to init for primary process, ret = %d",
2611 goto err_mp_init_primary;
2614 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2616 hw->data = eth_dev->data;
2618 ret = hns3_reset_init(hw);
2620 goto err_init_reset;
2621 hw->reset.ops = &hns3vf_reset_ops;
2623 ret = hns3vf_init_vf(eth_dev);
2625 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2629 /* Allocate memory for storing MAC addresses */
2630 eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2631 sizeof(struct rte_ether_addr) *
2632 HNS3_VF_UC_MACADDR_NUM, 0);
2633 if (eth_dev->data->mac_addrs == NULL) {
2634 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2635 "to store MAC addresses",
2636 sizeof(struct rte_ether_addr) *
2637 HNS3_VF_UC_MACADDR_NUM);
2639 goto err_rte_zmalloc;
2642 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2643 ð_dev->data->mac_addrs[0]);
2644 hw->adapter_state = HNS3_NIC_INITIALIZED;
2646 * Pass the information to the rte_eth_dev_close() that it should also
2647 * release the private port resources.
2649 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2651 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2652 hns3_err(hw, "Reschedule reset service after dev_init");
2653 hns3_schedule_reset(hns);
2655 /* IMP will wait ready flag before reset */
2656 hns3_notify_reset_ready(hw, false);
2658 rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2663 hns3vf_uninit_vf(eth_dev);
2666 rte_free(hw->reset.wait_data);
2669 hns3_mp_uninit_primary();
2671 err_mp_init_primary:
2672 err_mp_init_secondary:
2673 eth_dev->dev_ops = NULL;
2674 eth_dev->rx_pkt_burst = NULL;
2675 eth_dev->tx_pkt_burst = NULL;
2676 eth_dev->tx_pkt_prepare = NULL;
2677 rte_free(eth_dev->process_private);
2678 eth_dev->process_private = NULL;
2684 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2686 struct hns3_adapter *hns = eth_dev->data->dev_private;
2687 struct hns3_hw *hw = &hns->hw;
2689 PMD_INIT_FUNC_TRACE();
2691 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2694 eth_dev->dev_ops = NULL;
2695 eth_dev->rx_pkt_burst = NULL;
2696 eth_dev->tx_pkt_burst = NULL;
2697 eth_dev->tx_pkt_prepare = NULL;
2699 if (hw->adapter_state < HNS3_NIC_CLOSING)
2700 hns3vf_dev_close(eth_dev);
2702 hw->adapter_state = HNS3_NIC_REMOVED;
2707 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2708 struct rte_pci_device *pci_dev)
2710 return rte_eth_dev_pci_generic_probe(pci_dev,
2711 sizeof(struct hns3_adapter),
2716 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2718 return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2721 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2722 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2723 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2724 { .vendor_id = 0, /* sentinel */ },
2727 static struct rte_pci_driver rte_hns3vf_pmd = {
2728 .id_table = pci_id_hns3vf_map,
2729 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2730 .probe = eth_hns3vf_pci_probe,
2731 .remove = eth_hns3vf_pci_remove,
2734 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2735 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2736 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");