drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 /* set PCI bus mastering */
  48 static int
  49 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  50 {
  51         uint16_t reg;
  52         int ret;
  53
  54         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  55         if (ret < 0) {
  56                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  57                              PCI_COMMAND);
  58                 return ret;
  59         }
  60
  61         if (op)
  62                 /* set the master bit */
  63                 reg |= PCI_COMMAND_MASTER;
  64         else
  65                 reg &= ~(PCI_COMMAND_MASTER);
  66
  67         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  68 }
  69
  70 /**
  71  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  72  * @cap: the capability
  73  *
  74  * Return the address of the given capability within the PCI capability list.
  75  */
  76 static int
  77 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  78 {
  79 #define MAX_PCIE_CAPABILITY 48
  80         uint16_t status;
  81         uint8_t pos;
  82         uint8_t id;
  83         int ttl;
  84         int ret;
  85
  86         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  87         if (ret < 0) {
  88                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  89                 return 0;
  90         }
  91
  92         if (!(status & PCI_STATUS_CAP_LIST))
  93                 return 0;
  94
  95         ttl = MAX_PCIE_CAPABILITY;
  96         ret = rte_pci_read_config(device, &pos, sizeof(pos),
  97                                   PCI_CAPABILITY_LIST);
  98         if (ret < 0) {
  99                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 100                              PCI_CAPABILITY_LIST);
 101                 return 0;
 102         }
 103
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 ret = rte_pci_read_config(device, &id, sizeof(id),
 106                                           (pos + PCI_CAP_LIST_ID));
 107                 if (ret < 0) {
 108                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 109                                      (pos + PCI_CAP_LIST_ID));
 110                         break;
 111                 }
 112
 113                 if (id == 0xFF)
 114                         break;
 115
 116                 if (id == cap)
 117                         return (int)pos;
 118
 119                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 120                                           (pos + PCI_CAP_LIST_NEXT));
 121                 if (ret < 0) {
 122                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 123                                      (pos + PCI_CAP_LIST_NEXT));
 124                         break;
 125                 }
 126         }
 127         return 0;
 128 }
 129
 130 static int
 131 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 132 {
 133         uint16_t control;
 134         int pos;
 135         int ret;
 136
 137         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 138         if (pos) {
 139                 ret = rte_pci_read_config(device, &control, sizeof(control),
 140                                     (pos + PCI_MSIX_FLAGS));
 141                 if (ret < 0) {
 142                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 143                                      (pos + PCI_MSIX_FLAGS));
 144                         return -ENXIO;
 145                 }
 146
 147                 if (op)
 148                         control |= PCI_MSIX_FLAGS_ENABLE;
 149                 else
 150                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 151                 ret = rte_pci_write_config(device, &control, sizeof(control),
 152                                           (pos + PCI_MSIX_FLAGS));
 153                 if (ret < 0) {
 154                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 155                                     (pos + PCI_MSIX_FLAGS));
 156                 }
 157                 return 0;
 158         }
 159         return -ENXIO;
 160 }
 161
 162 static int
 163 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 164 {
 165         /* mac address was checked by upper level interface */
 166         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 167         int ret;
 168
 169         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 170                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 171                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 172         if (ret) {
 173                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 174                                       mac_addr);
 175                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 176                          mac_str, ret);
 177         }
 178         return ret;
 179 }
 180
 181 static int
 182 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 183 {
 184         /* mac address was checked by upper level interface */
 185         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 186         int ret;
 187
 188         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 189                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 190                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 191                                 false, NULL, 0);
 192         if (ret) {
 193                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 194                                       mac_addr);
 195                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 196                          mac_str, ret);
 197         }
 198         return ret;
 199 }
 200
 201 static int
 202 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 203 {
 204         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 205         struct rte_ether_addr *addr;
 206         int ret;
 207         int i;
 208
 209         for (i = 0; i < hw->mc_addrs_num; i++) {
 210                 addr = &hw->mc_addrs[i];
 211                 /* Check if there are duplicate addresses */
 212                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 213                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 214                                               addr);
 215                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 216                                  "(%s) is added by the set_mc_mac_addr_list "
 217                                  "API", mac_str);
 218                         return -EINVAL;
 219                 }
 220         }
 221
 222         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 223         if (ret) {
 224                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 225                                       mac_addr);
 226                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 227                          mac_str, ret);
 228         }
 229         return ret;
 230 }
 231
 232 static int
 233 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 234                     __rte_unused uint32_t idx,
 235                     __rte_unused uint32_t pool)
 236 {
 237         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 238         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 239         int ret;
 240
 241         rte_spinlock_lock(&hw->lock);
 242
 243         /*
 244          * In hns3 network engine adding UC and MC mac address with different
 245          * commands with firmware. We need to determine whether the input
 246          * address is a UC or a MC address to call different commands.
 247          * By the way, it is recommended calling the API function named
 248          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 249          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 250          * may affect the specifications of UC mac addresses.
 251          */
 252         if (rte_is_multicast_ether_addr(mac_addr))
 253                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 254         else
 255                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 256
 257         rte_spinlock_unlock(&hw->lock);
 258         if (ret) {
 259                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 260                                       mac_addr);
 261                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 262                          ret);
 263         }
 264
 265         return ret;
 266 }
 267
 268 static void
 269 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 270 {
 271         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 272         /* index will be checked by upper level rte interface */
 273         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 274         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 275         int ret;
 276
 277         rte_spinlock_lock(&hw->lock);
 278
 279         if (rte_is_multicast_ether_addr(mac_addr))
 280                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 281         else
 282                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 283
 284         rte_spinlock_unlock(&hw->lock);
 285         if (ret) {
 286                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 287                                       mac_addr);
 288                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 289                          mac_str, ret);
 290         }
 291 }
 292
 293 static int
 294 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 295                             struct rte_ether_addr *mac_addr)
 296 {
 297 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 298         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 299         struct rte_ether_addr *old_addr;
 300         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 301         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 302         int ret;
 303
 304         /*
 305          * It has been guaranteed that input parameter named mac_addr is valid
 306          * address in the rte layer of DPDK framework.
 307          */
 308         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 309         rte_spinlock_lock(&hw->lock);
 310         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 311         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 312                RTE_ETHER_ADDR_LEN);
 313
 314         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 315                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 316                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 317         if (ret) {
 318                 /*
 319                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 320                  * driver. When user has configured a MAC address for VF device
 321                  * by "ip link set ..." command based on the PF device, the hns3
 322                  * PF kernel ethdev driver does not allow VF driver to request
 323                  * reconfiguring a different default MAC address, and return
 324                  * -EPREM to VF driver through mailbox.
 325                  */
 326                 if (ret == -EPERM) {
 327                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 328                                               old_addr);
 329                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 330                                   mac_str);
 331                 } else {
 332                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 333                                               mac_addr);
 334                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 335                                  mac_str, ret);
 336                 }
 337         }
 338
 339         rte_ether_addr_copy(mac_addr,
 340                             (struct rte_ether_addr *)hw->mac.mac_addr);
 341         rte_spinlock_unlock(&hw->lock);
 342
 343         return ret;
 344 }
 345
 346 static int
 347 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 348 {
 349         struct hns3_hw *hw = &hns->hw;
 350         struct rte_ether_addr *addr;
 351         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 352         int err = 0;
 353         int ret;
 354         int i;
 355
 356         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 357                 addr = &hw->data->mac_addrs[i];
 358                 if (rte_is_zero_ether_addr(addr))
 359                         continue;
 360                 if (rte_is_multicast_ether_addr(addr))
 361                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 362                               hns3vf_add_mc_mac_addr(hw, addr);
 363                 else
 364                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 365                               hns3vf_add_uc_mac_addr(hw, addr);
 366
 367                 if (ret) {
 368                         err = ret;
 369                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 370                                               addr);
 371                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 372                                  "ret = %d.", del ? "remove" : "restore",
 373                                  mac_str, i, ret);
 374                 }
 375         }
 376         return err;
 377 }
 378
 379 static int
 380 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 381                        struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 402                           struct rte_ether_addr *mac_addr)
 403 {
 404         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 405         int ret;
 406
 407         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 408                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 409                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 410                                 NULL, 0);
 411         if (ret) {
 412                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 413                                       mac_addr);
 414                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 415                          mac_str, ret);
 416         }
 417
 418         return ret;
 419 }
 420
 421 static int
 422 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 423                              struct rte_ether_addr *mc_addr_set,
 424                              uint32_t nb_mc_addr)
 425 {
 426         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 427         struct rte_ether_addr *addr;
 428         uint32_t i;
 429         uint32_t j;
 430
 431         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 432                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 433                          "invalid. valid range: 0~%d",
 434                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 435                 return -EINVAL;
 436         }
 437
 438         /* Check if input mac addresses are valid */
 439         for (i = 0; i < nb_mc_addr; i++) {
 440                 addr = &mc_addr_set[i];
 441                 if (!rte_is_multicast_ether_addr(addr)) {
 442                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 443                                               addr);
 444                         hns3_err(hw,
 445                                  "failed to set mc mac addr, addr(%s) invalid.",
 446                                  mac_str);
 447                         return -EINVAL;
 448                 }
 449
 450                 /* Check if there are duplicate addresses */
 451                 for (j = i + 1; j < nb_mc_addr; j++) {
 452                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 453                                 hns3_ether_format_addr(mac_str,
 454                                                       RTE_ETHER_ADDR_FMT_SIZE,
 455                                                       addr);
 456                                 hns3_err(hw, "failed to set mc mac addr, "
 457                                          "addrs invalid. two same addrs(%s).",
 458                                          mac_str);
 459                                 return -EINVAL;
 460                         }
 461                 }
 462
 463                 /*
 464                  * Check if there are duplicate addresses between mac_addrs
 465                  * and mc_addr_set
 466                  */
 467                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 468                         if (rte_is_same_ether_addr(addr,
 469                                                    &hw->data->mac_addrs[j])) {
 470                                 hns3_ether_format_addr(mac_str,
 471                                                       RTE_ETHER_ADDR_FMT_SIZE,
 472                                                       addr);
 473                                 hns3_err(hw, "failed to set mc mac addr, "
 474                                          "addrs invalid. addrs(%s) has already "
 475                                          "configured in mac_addr add API",
 476                                          mac_str);
 477                                 return -EINVAL;
 478                         }
 479                 }
 480         }
 481
 482         return 0;
 483 }
 484
 485 static int
 486 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 487                             struct rte_ether_addr *mc_addr_set,
 488                             uint32_t nb_mc_addr)
 489 {
 490         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 491         struct rte_ether_addr *addr;
 492         int cur_addr_num;
 493         int set_addr_num;
 494         int num;
 495         int ret;
 496         int i;
 497
 498         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 499         if (ret)
 500                 return ret;
 501
 502         rte_spinlock_lock(&hw->lock);
 503         cur_addr_num = hw->mc_addrs_num;
 504         for (i = 0; i < cur_addr_num; i++) {
 505                 num = cur_addr_num - i - 1;
 506                 addr = &hw->mc_addrs[num];
 507                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 508                 if (ret) {
 509                         rte_spinlock_unlock(&hw->lock);
 510                         return ret;
 511                 }
 512
 513                 hw->mc_addrs_num--;
 514         }
 515
 516         set_addr_num = (int)nb_mc_addr;
 517         for (i = 0; i < set_addr_num; i++) {
 518                 addr = &mc_addr_set[i];
 519                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 520                 if (ret) {
 521                         rte_spinlock_unlock(&hw->lock);
 522                         return ret;
 523                 }
 524
 525                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 526                 hw->mc_addrs_num++;
 527         }
 528         rte_spinlock_unlock(&hw->lock);
 529
 530         return 0;
 531 }
 532
 533 static int
 534 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 535 {
 536         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 537         struct hns3_hw *hw = &hns->hw;
 538         struct rte_ether_addr *addr;
 539         int err = 0;
 540         int ret;
 541         int i;
 542
 543         for (i = 0; i < hw->mc_addrs_num; i++) {
 544                 addr = &hw->mc_addrs[i];
 545                 if (!rte_is_multicast_ether_addr(addr))
 546                         continue;
 547                 if (del)
 548                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 549                 else
 550                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 551                 if (ret) {
 552                         err = ret;
 553                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 554                                               addr);
 555                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 556                                  del ? "Remove" : "Restore", mac_str, ret);
 557                 }
 558         }
 559         return err;
 560 }
 561
 562 static int
 563 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 564                         bool en_uc_pmc, bool en_mc_pmc)
 565 {
 566         struct hns3_mbx_vf_to_pf_cmd *req;
 567         struct hns3_cmd_desc desc;
 568         int ret;
 569
 570         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 571
 572         /*
 573          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 574          * so there are some features for promiscuous/allmulticast mode in hns3
 575          * VF PMD driver as below:
 576          * 1. The promiscuous/allmulticast mode can be configured successfully
 577          *    only based on the trusted VF device. If based on the non trusted
 578          *    VF device, configuring promiscuous/allmulticast mode will fail.
 579          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 580          *    kernel ethdev driver on the host by the following command:
 581          *      "ip link set <eth num> vf <vf id> turst on"
 582          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 583          *    driver can receive the ingress and outgoing traffic. In the words,
 584          *    all the ingress packets, all the packets sent from the PF and
 585          *    other VFs on the same physical port.
 586          * 3. Note: Because of the hardware constraints, By default vlan filter
 587          *    is enabled and couldn't be turned off based on VF device, so vlan
 588          *    filter is still effective even in promiscuous mode. If upper
 589          *    applications don't call rte_eth_dev_vlan_filter API function to
 590          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 591          *    the packets with vlan tag in promiscuoue mode.
 592          */
 593         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 594         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 595         req->msg[1] = en_bc_pmc ? 1 : 0;
 596         req->msg[2] = en_uc_pmc ? 1 : 0;
 597         req->msg[3] = en_mc_pmc ? 1 : 0;
 598         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 599
 600         ret = hns3_cmd_send(hw, &desc, 1);
 601         if (ret)
 602                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 609 {
 610         struct hns3_adapter *hns = dev->data->dev_private;
 611         struct hns3_hw *hw = &hns->hw;
 612         int ret;
 613
 614         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 615         if (ret)
 616                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 617                         ret);
 618         return ret;
 619 }
 620
 621 static int
 622 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 623 {
 624         bool allmulti = dev->data->all_multicast ? true : false;
 625         struct hns3_adapter *hns = dev->data->dev_private;
 626         struct hns3_hw *hw = &hns->hw;
 627         int ret;
 628
 629         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 630         if (ret)
 631                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 632                         ret);
 633         return ret;
 634 }
 635
 636 static int
 637 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 638 {
 639         struct hns3_adapter *hns = dev->data->dev_private;
 640         struct hns3_hw *hw = &hns->hw;
 641         int ret;
 642
 643         if (dev->data->promiscuous)
 644                 return 0;
 645
 646         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 647         if (ret)
 648                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 649                         ret);
 650         return ret;
 651 }
 652
 653 static int
 654 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 655 {
 656         struct hns3_adapter *hns = dev->data->dev_private;
 657         struct hns3_hw *hw = &hns->hw;
 658         int ret;
 659
 660         if (dev->data->promiscuous)
 661                 return 0;
 662
 663         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 664         if (ret)
 665                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 666                         ret);
 667         return ret;
 668 }
 669
 670 static int
 671 hns3vf_restore_promisc(struct hns3_adapter *hns)
 672 {
 673         struct hns3_hw *hw = &hns->hw;
 674         bool allmulti = hw->data->all_multicast ? true : false;
 675
 676         if (hw->data->promiscuous)
 677                 return hns3vf_set_promisc_mode(hw, true, true, true);
 678
 679         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 680 }
 681
 682 static int
 683 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 684                              bool mmap, enum hns3_ring_type queue_type,
 685                              uint16_t queue_id)
 686 {
 687         struct hns3_vf_bind_vector_msg bind_msg;
 688         const char *op_str;
 689         uint16_t code;
 690         int ret;
 691
 692         memset(&bind_msg, 0, sizeof(bind_msg));
 693         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 694                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 695         bind_msg.vector_id = vector_id;
 696
 697         if (queue_type == HNS3_RING_TYPE_RX)
 698                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 699         else
 700                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 701
 702         bind_msg.param[0].ring_type = queue_type;
 703         bind_msg.ring_num = 1;
 704         bind_msg.param[0].tqp_index = queue_id;
 705         op_str = mmap ? "Map" : "Unmap";
 706         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 707                                 sizeof(bind_msg), false, NULL, 0);
 708         if (ret)
 709                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 710                          op_str, queue_id, bind_msg.vector_id, ret);
 711
 712         return ret;
 713 }
 714
 715 static int
 716 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 717 {
 718         uint16_t vec;
 719         int ret;
 720         int i;
 721
 722         /*
 723          * In hns3 network engine, vector 0 is always the misc interrupt of this
 724          * function, vector 1~N can be used respectively for the queues of the
 725          * function. Tx and Rx queues with the same number share the interrupt
 726          * vector. In the initialization clearing the all hardware mapping
 727          * relationship configurations between queues and interrupt vectors is
 728          * needed, so some error caused by the residual configurations, such as
 729          * the unexpected Tx interrupt, can be avoid.
 730          */
 731         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 732         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 733                 vec = vec - 1; /* the last interrupt is reserved */
 734         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 735         for (i = 0; i < hw->intr_tqps_num; i++) {
 736                 /*
 737                  * Set gap limiter/rate limiter/quanity limiter algorithm
 738                  * configuration for interrupt coalesce of queue's interrupt.
 739                  */
 740                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 741                                        HNS3_TQP_INTR_GL_DEFAULT);
 742                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 743                                        HNS3_TQP_INTR_GL_DEFAULT);
 744                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 745                 /*
 746                  * QL(quantity limiter) is not used currently, just set 0 to
 747                  * close it.
 748                  */
 749                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 750
 751                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 752                                                    HNS3_RING_TYPE_TX, i);
 753                 if (ret) {
 754                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 755                                           "vector: %u, ret=%d", i, vec, ret);
 756                         return ret;
 757                 }
 758
 759                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 760                                                    HNS3_RING_TYPE_RX, i);
 761                 if (ret) {
 762                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 763                                           "vector: %u, ret=%d", i, vec, ret);
 764                         return ret;
 765                 }
 766         }
 767
 768         return 0;
 769 }
 770
 771 static int
 772 hns3vf_dev_configure(struct rte_eth_dev *dev)
 773 {
 774         struct hns3_adapter *hns = dev->data->dev_private;
 775         struct hns3_hw *hw = &hns->hw;
 776         struct rte_eth_conf *conf = &dev->data->dev_conf;
 777         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 778         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 779         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 780         struct rte_eth_rss_conf rss_conf;
 781         uint16_t mtu;
 782         bool gro_en;
 783         int ret;
 784
 785         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 786
 787         /*
 788          * Some versions of hardware network engine does not support
 789          * individually enable/disable/reset the Tx or Rx queue. These devices
 790          * must enable/disable/reset Tx and Rx queues at the same time. When the
 791          * numbers of Tx queues allocated by upper applications are not equal to
 792          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 793          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 794          * work as usual. But these fake queues are imperceptible, and can not
 795          * be used by upper applications.
 796          */
 797         if (!hns3_dev_indep_txrx_supported(hw)) {
 798                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 799                 if (ret) {
 800                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
 801                                  ret);
 802                         return ret;
 803                 }
 804         }
 805
 806         hw->adapter_state = HNS3_NIC_CONFIGURING;
 807         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 808                 hns3_err(hw, "setting link speed/duplex not supported");
 809                 ret = -EINVAL;
 810                 goto cfg_err;
 811         }
 812
 813         /* When RSS is not configured, redirect the packet queue 0 */
 814         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 815                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 816                 hw->rss_dis_flag = false;
 817                 rss_conf = conf->rx_adv_conf.rss_conf;
 818                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 819                 if (ret)
 820                         goto cfg_err;
 821         }
 822
 823         /*
 824          * If jumbo frames are enabled, MTU needs to be refreshed
 825          * according to the maximum RX packet length.
 826          */
 827         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 828                 /*
 829                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 830                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 831                  * can safely assign to "uint16_t" type variable.
 832                  */
 833                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 834                 ret = hns3vf_dev_mtu_set(dev, mtu);
 835                 if (ret)
 836                         goto cfg_err;
 837                 dev->data->mtu = mtu;
 838         }
 839
 840         ret = hns3vf_dev_configure_vlan(dev);
 841         if (ret)
 842                 goto cfg_err;
 843
 844         /* config hardware GRO */
 845         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 846         ret = hns3_config_gro(hw, gro_en);
 847         if (ret)
 848                 goto cfg_err;
 849
 850         hns->rx_simple_allowed = true;
 851         hns->rx_vec_allowed = true;
 852         hns->tx_simple_allowed = true;
 853         hns->tx_vec_allowed = true;
 854
 855         hns3_init_rx_ptype_tble(dev);
 856
 857         hw->adapter_state = HNS3_NIC_CONFIGURED;
 858         return 0;
 859
 860 cfg_err:
 861         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 862         hw->adapter_state = HNS3_NIC_INITIALIZED;
 863
 864         return ret;
 865 }
 866
 867 static int
 868 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 869 {
 870         int ret;
 871
 872         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 873                                 sizeof(mtu), true, NULL, 0);
 874         if (ret)
 875                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 876
 877         return ret;
 878 }
 879
 880 static int
 881 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 882 {
 883         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 884         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 885         int ret;
 886
 887         /*
 888          * The hns3 PF/VF devices on the same port share the hardware MTU
 889          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 890          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 891          * driver, there is no need to stop the port for hns3 VF device, and the
 892          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 893          * PF's MTU.
 894          */
 895         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 896                 hns3_err(hw, "Failed to set mtu during resetting");
 897                 return -EIO;
 898         }
 899
 900         /*
 901          * when Rx of scattered packets is off, we have some possibility of
 902          * using vector Rx process function or simple Rx functions in hns3 PMD
 903          * driver. If the input MTU is increased and the maximum length of
 904          * received packets is greater than the length of a buffer for Rx
 905          * packet, the hardware network engine needs to use multiple BDs and
 906          * buffers to store these packets. This will cause problems when still
 907          * using vector Rx process function or simple Rx function to receiving
 908          * packets. So, when Rx of scattered packets is off and device is
 909          * started, it is not permitted to increase MTU so that the maximum
 910          * length of Rx packets is greater than Rx buffer length.
 911          */
 912         if (dev->data->dev_started && !dev->data->scattered_rx &&
 913             frame_size > hw->rx_buf_len) {
 914                 hns3_err(hw, "failed to set mtu because current is "
 915                         "not scattered rx mode");
 916                 return -EOPNOTSUPP;
 917         }
 918
 919         rte_spinlock_lock(&hw->lock);
 920         ret = hns3vf_config_mtu(hw, mtu);
 921         if (ret) {
 922                 rte_spinlock_unlock(&hw->lock);
 923                 return ret;
 924         }
 925         if (mtu > RTE_ETHER_MTU)
 926                 dev->data->dev_conf.rxmode.offloads |=
 927                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 928         else
 929                 dev->data->dev_conf.rxmode.offloads &=
 930                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 931         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 932         rte_spinlock_unlock(&hw->lock);
 933
 934         return 0;
 935 }
 936
 937 static int
 938 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 939 {
 940         struct hns3_adapter *hns = eth_dev->data->dev_private;
 941         struct hns3_hw *hw = &hns->hw;
 942         uint16_t q_num = hw->tqps_num;
 943
 944         /*
 945          * In interrupt mode, 'max_rx_queues' is set based on the number of
 946          * MSI-X interrupt resources of the hardware.
 947          */
 948         if (hw->data->dev_conf.intr_conf.rxq == 1)
 949                 q_num = hw->intr_tqps_num;
 950
 951         info->max_rx_queues = q_num;
 952         info->max_tx_queues = hw->tqps_num;
 953         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 954         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 955         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 956         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 957         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 958
 959         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 960                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 961                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 962                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 963                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 964                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 965                                  DEV_RX_OFFLOAD_SCATTER |
 966                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 967                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 968                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 969                                  DEV_RX_OFFLOAD_RSS_HASH |
 970                                  DEV_RX_OFFLOAD_TCP_LRO);
 971         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 972                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 973                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 974                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 975                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 976                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 977                                  DEV_TX_OFFLOAD_TCP_TSO |
 978                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 979                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 980                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 981                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 982                                  hns3_txvlan_cap_get(hw));
 983
 984         if (hns3_dev_indep_txrx_supported(hw))
 985                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 986                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 987
 988         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 989                 .nb_max = HNS3_MAX_RING_DESC,
 990                 .nb_min = HNS3_MIN_RING_DESC,
 991                 .nb_align = HNS3_ALIGN_RING_DESC,
 992         };
 993
 994         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 995                 .nb_max = HNS3_MAX_RING_DESC,
 996                 .nb_min = HNS3_MIN_RING_DESC,
 997                 .nb_align = HNS3_ALIGN_RING_DESC,
 998                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 999                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1000         };
1001
1002         info->default_rxconf = (struct rte_eth_rxconf) {
1003                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1004                 /*
1005                  * If there are no available Rx buffer descriptors, incoming
1006                  * packets are always dropped by hardware based on hns3 network
1007                  * engine.
1008                  */
1009                 .rx_drop_en = 1,
1010                 .offloads = 0,
1011         };
1012         info->default_txconf = (struct rte_eth_txconf) {
1013                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1014                 .offloads = 0,
1015         };
1016
1017         info->vmdq_queue_num = 0;
1018
1019         info->reta_size = hw->rss_ind_tbl_size;
1020         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1021         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1022         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1023         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1024
1025         return 0;
1026 }
1027
1028 static void
1029 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1030 {
1031         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1032 }
1033
1034 static void
1035 hns3vf_disable_irq0(struct hns3_hw *hw)
1036 {
1037         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1038 }
1039
1040 static void
1041 hns3vf_enable_irq0(struct hns3_hw *hw)
1042 {
1043         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1044 }
1045
1046 static enum hns3vf_evt_cause
1047 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1048 {
1049         struct hns3_hw *hw = &hns->hw;
1050         enum hns3vf_evt_cause ret;
1051         uint32_t cmdq_stat_reg;
1052         uint32_t rst_ing_reg;
1053         uint32_t val;
1054
1055         /* Fetch the events from their corresponding regs */
1056         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1057
1058         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1059                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1060                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1061                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1062                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1063                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1064                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1065                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1066                 if (clearval) {
1067                         hw->reset.stats.global_cnt++;
1068                         hns3_warn(hw, "Global reset detected, clear reset status");
1069                 } else {
1070                         hns3_schedule_delayed_reset(hns);
1071                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1072                 }
1073
1074                 ret = HNS3VF_VECTOR0_EVENT_RST;
1075                 goto out;
1076         }
1077
1078         /* Check for vector0 mailbox(=CMDQ RX) event source */
1079         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1080                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1081                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1082                 goto out;
1083         }
1084
1085         val = 0;
1086         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1087 out:
1088         if (clearval)
1089                 *clearval = val;
1090         return ret;
1091 }
1092
1093 static void
1094 hns3vf_interrupt_handler(void *param)
1095 {
1096         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1097         struct hns3_adapter *hns = dev->data->dev_private;
1098         struct hns3_hw *hw = &hns->hw;
1099         enum hns3vf_evt_cause event_cause;
1100         uint32_t clearval;
1101
1102         if (hw->irq_thread_id == 0)
1103                 hw->irq_thread_id = pthread_self();
1104
1105         /* Disable interrupt */
1106         hns3vf_disable_irq0(hw);
1107
1108         /* Read out interrupt causes */
1109         event_cause = hns3vf_check_event_cause(hns, &clearval);
1110
1111         switch (event_cause) {
1112         case HNS3VF_VECTOR0_EVENT_RST:
1113                 hns3_schedule_reset(hns);
1114                 break;
1115         case HNS3VF_VECTOR0_EVENT_MBX:
1116                 hns3_dev_handle_mbx_msg(hw);
1117                 break;
1118         default:
1119                 break;
1120         }
1121
1122         /* Clear interrupt causes */
1123         hns3vf_clear_event_cause(hw, clearval);
1124
1125         /* Enable interrupt */
1126         hns3vf_enable_irq0(hw);
1127 }
1128
1129 static void
1130 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1131 {
1132         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1133         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1134         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1135         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1136 }
1137
1138 static void
1139 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1140 {
1141         struct hns3_dev_specs_0_cmd *req0;
1142
1143         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1144
1145         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1146         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1147         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1148         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1149 }
1150
1151 static int
1152 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1153 {
1154         if (hw->rss_ind_tbl_size == 0 ||
1155             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1156                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1157                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1158                               HNS3_RSS_IND_TBL_SIZE_MAX);
1159                 return -EINVAL;
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int
1166 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1167 {
1168         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1169         int ret;
1170         int i;
1171
1172         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1173                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1174                                           true);
1175                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1176         }
1177         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1178
1179         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1180         if (ret)
1181                 return ret;
1182
1183         hns3vf_parse_dev_specifications(hw, desc);
1184
1185         return hns3vf_check_dev_specifications(hw);
1186 }
1187
1188 static int
1189 hns3vf_get_capability(struct hns3_hw *hw)
1190 {
1191         struct rte_pci_device *pci_dev;
1192         struct rte_eth_dev *eth_dev;
1193         uint8_t revision;
1194         int ret;
1195
1196         eth_dev = &rte_eth_devices[hw->data->port_id];
1197         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1198
1199         /* Get PCI revision id */
1200         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1201                                   HNS3_PCI_REVISION_ID);
1202         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1203                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1204                              ret);
1205                 return -EIO;
1206         }
1207         hw->revision = revision;
1208
1209         if (revision < PCI_REVISION_ID_HIP09_A) {
1210                 hns3vf_set_default_dev_specifications(hw);
1211                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1212                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1213                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1214                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1215                 hw->rss_info.ipv6_sctp_offload_supported = false;
1216                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1217                 return 0;
1218         }
1219
1220         ret = hns3vf_query_dev_specifications(hw);
1221         if (ret) {
1222                 PMD_INIT_LOG(ERR,
1223                              "failed to query dev specifications, ret = %d",
1224                              ret);
1225                 return ret;
1226         }
1227
1228         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1229         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1230         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1231         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1232         hw->rss_info.ipv6_sctp_offload_supported = true;
1233         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1234
1235         return 0;
1236 }
1237
1238 static int
1239 hns3vf_check_tqp_info(struct hns3_hw *hw)
1240 {
1241         if (hw->tqps_num == 0) {
1242                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1243                 return -EINVAL;
1244         }
1245
1246         if (hw->rss_size_max == 0) {
1247                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1248                 return -EINVAL;
1249         }
1250
1251         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1252
1253         return 0;
1254 }
1255
1256 static int
1257 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1258 {
1259         uint8_t resp_msg;
1260         int ret;
1261
1262         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1263                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1264                                 true, &resp_msg, sizeof(resp_msg));
1265         if (ret) {
1266                 if (ret == -ETIME) {
1267                         /*
1268                          * Getting current port based VLAN state from PF driver
1269                          * will not affect VF driver's basic function. Because
1270                          * the VF driver relies on hns3 PF kernel ether driver,
1271                          * to avoid introducing compatibility issues with older
1272                          * version of PF driver, no failure will be returned
1273                          * when the return value is ETIME. This return value has
1274                          * the following scenarios:
1275                          * 1) Firmware didn't return the results in time
1276                          * 2) the result return by firmware is timeout
1277                          * 3) the older version of kernel side PF driver does
1278                          *    not support this mailbox message.
1279                          * For scenarios 1 and 2, it is most likely that a
1280                          * hardware error has occurred, or a hardware reset has
1281                          * occurred. In this case, these errors will be caught
1282                          * by other functions.
1283                          */
1284                         PMD_INIT_LOG(WARNING,
1285                                 "failed to get PVID state for timeout, maybe "
1286                                 "kernel side PF driver doesn't support this "
1287                                 "mailbox message, or firmware didn't respond.");
1288                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1289                 } else {
1290                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1291                                 " ret = %d", ret);
1292                         return ret;
1293                 }
1294         }
1295         hw->port_base_vlan_cfg.state = resp_msg ?
1296                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1297         return 0;
1298 }
1299
1300 static int
1301 hns3vf_get_queue_info(struct hns3_hw *hw)
1302 {
1303 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1304         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1305         int ret;
1306
1307         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1308                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1309         if (ret) {
1310                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1311                 return ret;
1312         }
1313
1314         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1315         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1316
1317         return hns3vf_check_tqp_info(hw);
1318 }
1319
1320 static int
1321 hns3vf_get_queue_depth(struct hns3_hw *hw)
1322 {
1323 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1324         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1325         int ret;
1326
1327         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1328                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1329         if (ret) {
1330                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1331                              ret);
1332                 return ret;
1333         }
1334
1335         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1336         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1337
1338         return 0;
1339 }
1340
1341 static int
1342 hns3vf_get_tc_info(struct hns3_hw *hw)
1343 {
1344         uint8_t resp_msg;
1345         int ret;
1346         uint32_t i;
1347
1348         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1349                                 true, &resp_msg, sizeof(resp_msg));
1350         if (ret) {
1351                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1352                          ret);
1353                 return ret;
1354         }
1355
1356         hw->hw_tc_map = resp_msg;
1357
1358         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1359                 if (hw->hw_tc_map & BIT(i))
1360                         hw->num_tc++;
1361         }
1362
1363         return 0;
1364 }
1365
1366 static int
1367 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1368 {
1369         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1370         int ret;
1371
1372         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1373                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1374         if (ret) {
1375                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1376                 return ret;
1377         }
1378
1379         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1380
1381         return 0;
1382 }
1383
1384 static int
1385 hns3vf_get_configuration(struct hns3_hw *hw)
1386 {
1387         int ret;
1388
1389         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1390         hw->rss_dis_flag = false;
1391
1392         /* Get device capability */
1393         ret = hns3vf_get_capability(hw);
1394         if (ret) {
1395                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1396                 return ret;
1397         }
1398
1399         /* Get queue configuration from PF */
1400         ret = hns3vf_get_queue_info(hw);
1401         if (ret)
1402                 return ret;
1403
1404         /* Get queue depth info from PF */
1405         ret = hns3vf_get_queue_depth(hw);
1406         if (ret)
1407                 return ret;
1408
1409         /* Get user defined VF MAC addr from PF */
1410         ret = hns3vf_get_host_mac_addr(hw);
1411         if (ret)
1412                 return ret;
1413
1414         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1415         if (ret)
1416                 return ret;
1417
1418         /* Get tc configuration from PF */
1419         return hns3vf_get_tc_info(hw);
1420 }
1421
1422 static int
1423 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1424                             uint16_t nb_tx_q)
1425 {
1426         struct hns3_hw *hw = &hns->hw;
1427
1428         if (nb_rx_q < hw->num_tc) {
1429                 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).",
1430                          nb_rx_q, hw->num_tc);
1431                 return -EINVAL;
1432         }
1433
1434         if (nb_tx_q < hw->num_tc) {
1435                 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).",
1436                          nb_tx_q, hw->num_tc);
1437                 return -EINVAL;
1438         }
1439
1440         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1441 }
1442
1443 static void
1444 hns3vf_request_link_info(struct hns3_hw *hw)
1445 {
1446         uint8_t resp_msg;
1447         int ret;
1448
1449         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1450                 return;
1451         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1452                                 &resp_msg, sizeof(resp_msg));
1453         if (ret)
1454                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1455 }
1456
1457 void
1458 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1459                           uint32_t link_speed, uint8_t link_duplex)
1460 {
1461         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1462         struct hns3_mac *mac = &hw->mac;
1463         bool report_lse;
1464         bool changed;
1465
1466         changed = mac->link_status != link_status ||
1467                   mac->link_speed != link_speed ||
1468                   mac->link_duplex != link_duplex;
1469         if (!changed)
1470                 return;
1471
1472         /*
1473          * VF's link status/speed/duplex were updated by polling from PF driver,
1474          * because the link status/speed/duplex may be changed in the polling
1475          * interval, so driver will report lse (lsc event) once any of the above
1476          * thress variables changed.
1477          * But if the PF's link status is down and driver saved link status is
1478          * also down, there are no need to report lse.
1479          */
1480         report_lse = true;
1481         if (link_status == ETH_LINK_DOWN && link_status == mac->link_status)
1482                 report_lse = false;
1483
1484         mac->link_status = link_status;
1485         mac->link_speed = link_speed;
1486         mac->link_duplex = link_duplex;
1487
1488         if (report_lse)
1489                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1490 }
1491
1492 static int
1493 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1494 {
1495 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1496         struct hns3_hw *hw = &hns->hw;
1497         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1498         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1499         uint8_t is_kill = on ? 0 : 1;
1500
1501         msg_data[0] = is_kill;
1502         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1503         memcpy(&msg_data[3], &proto, sizeof(proto));
1504
1505         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1506                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1507                                  0);
1508 }
1509
1510 static int
1511 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1512 {
1513         struct hns3_adapter *hns = dev->data->dev_private;
1514         struct hns3_hw *hw = &hns->hw;
1515         int ret;
1516
1517         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1518                 hns3_err(hw,
1519                          "vf set vlan id failed during resetting, vlan_id =%u",
1520                          vlan_id);
1521                 return -EIO;
1522         }
1523         rte_spinlock_lock(&hw->lock);
1524         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1525         rte_spinlock_unlock(&hw->lock);
1526         if (ret)
1527                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1528                          vlan_id, ret);
1529
1530         return ret;
1531 }
1532
1533 static int
1534 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1535 {
1536         uint8_t msg_data;
1537         int ret;
1538
1539         msg_data = enable ? 1 : 0;
1540         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1541                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1542         if (ret)
1543                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1544
1545         return ret;
1546 }
1547
1548 static int
1549 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1550 {
1551         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1552         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1553         unsigned int tmp_mask;
1554         int ret = 0;
1555
1556         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1557                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1558                              "mask = 0x%x", mask);
1559                 return -EIO;
1560         }
1561
1562         tmp_mask = (unsigned int)mask;
1563         /* Vlan stripping setting */
1564         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1565                 rte_spinlock_lock(&hw->lock);
1566                 /* Enable or disable VLAN stripping */
1567                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1568                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1569                 else
1570                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1571                 rte_spinlock_unlock(&hw->lock);
1572         }
1573
1574         return ret;
1575 }
1576
1577 static int
1578 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1579 {
1580         struct rte_vlan_filter_conf *vfc;
1581         struct hns3_hw *hw = &hns->hw;
1582         uint16_t vlan_id;
1583         uint64_t vbit;
1584         uint64_t ids;
1585         int ret = 0;
1586         uint32_t i;
1587
1588         vfc = &hw->data->vlan_filter_conf;
1589         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1590                 if (vfc->ids[i] == 0)
1591                         continue;
1592                 ids = vfc->ids[i];
1593                 while (ids) {
1594                         /*
1595                          * 64 means the num bits of ids, one bit corresponds to
1596                          * one vlan id
1597                          */
1598                         vlan_id = 64 * i;
1599                         /* count trailing zeroes */
1600                         vbit = ~ids & (ids - 1);
1601                         /* clear least significant bit set */
1602                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1603                         for (; vbit;) {
1604                                 vbit >>= 1;
1605                                 vlan_id++;
1606                         }
1607                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1608                         if (ret) {
1609                                 hns3_err(hw,
1610                                          "VF handle vlan table failed, ret =%d, on = %d",
1611                                          ret, on);
1612                                 return ret;
1613                         }
1614                 }
1615         }
1616
1617         return ret;
1618 }
1619
1620 static int
1621 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1622 {
1623         return hns3vf_handle_all_vlan_table(hns, 0);
1624 }
1625
1626 static int
1627 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1628 {
1629         struct hns3_hw *hw = &hns->hw;
1630         struct rte_eth_conf *dev_conf;
1631         bool en;
1632         int ret;
1633
1634         dev_conf = &hw->data->dev_conf;
1635         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1636                                                                    : false;
1637         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1638         if (ret)
1639                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1640                          ret);
1641         return ret;
1642 }
1643
1644 static int
1645 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1646 {
1647         struct hns3_adapter *hns = dev->data->dev_private;
1648         struct rte_eth_dev_data *data = dev->data;
1649         struct hns3_hw *hw = &hns->hw;
1650         int ret;
1651
1652         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1653             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1654             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1655                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1656                               "or hw_vlan_insert_pvid is not support!");
1657         }
1658
1659         /* Apply vlan offload setting */
1660         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1661         if (ret)
1662                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1663
1664         return ret;
1665 }
1666
1667 static int
1668 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1669 {
1670         uint8_t msg_data;
1671
1672         msg_data = alive ? 1 : 0;
1673         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1674                                  sizeof(msg_data), false, NULL, 0);
1675 }
1676
1677 static void
1678 hns3vf_keep_alive_handler(void *param)
1679 {
1680         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1681         struct hns3_adapter *hns = eth_dev->data->dev_private;
1682         struct hns3_hw *hw = &hns->hw;
1683         uint8_t respmsg;
1684         int ret;
1685
1686         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1687                                 false, &respmsg, sizeof(uint8_t));
1688         if (ret)
1689                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1690                          ret);
1691
1692         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1693                           eth_dev);
1694 }
1695
1696 static void
1697 hns3vf_service_handler(void *param)
1698 {
1699         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1700         struct hns3_adapter *hns = eth_dev->data->dev_private;
1701         struct hns3_hw *hw = &hns->hw;
1702
1703         /*
1704          * The query link status and reset processing are executed in the
1705          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1706          * and the query operation will time out after 30ms. In the case of
1707          * multiple PF/VFs, each query failure timeout causes the IMP reset
1708          * interrupt to fail to respond within 100ms.
1709          * Before querying the link status, check whether there is a reset
1710          * pending, and if so, abandon the query.
1711          */
1712         if (!hns3vf_is_reset_pending(hns))
1713                 hns3vf_request_link_info(hw);
1714         else
1715                 hns3_warn(hw, "Cancel the query when reset is pending");
1716
1717         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1718                           eth_dev);
1719 }
1720
1721 static int
1722 hns3_query_vf_resource(struct hns3_hw *hw)
1723 {
1724         struct hns3_vf_res_cmd *req;
1725         struct hns3_cmd_desc desc;
1726         uint16_t num_msi;
1727         int ret;
1728
1729         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1730         ret = hns3_cmd_send(hw, &desc, 1);
1731         if (ret) {
1732                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1733                 return ret;
1734         }
1735
1736         req = (struct hns3_vf_res_cmd *)desc.data;
1737         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1738                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1739         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1740                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1741                          num_msi, HNS3_MIN_VECTOR_NUM);
1742                 return -EINVAL;
1743         }
1744
1745         hw->num_msi = num_msi;
1746
1747         return 0;
1748 }
1749
1750 static int
1751 hns3vf_init_hardware(struct hns3_adapter *hns)
1752 {
1753         struct hns3_hw *hw = &hns->hw;
1754         uint16_t mtu = hw->data->mtu;
1755         int ret;
1756
1757         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1758         if (ret)
1759                 return ret;
1760
1761         ret = hns3vf_config_mtu(hw, mtu);
1762         if (ret)
1763                 goto err_init_hardware;
1764
1765         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1766         if (ret) {
1767                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1768                 goto err_init_hardware;
1769         }
1770
1771         ret = hns3_config_gro(hw, false);
1772         if (ret) {
1773                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1774                 goto err_init_hardware;
1775         }
1776
1777         /*
1778          * In the initialization clearing the all hardware mapping relationship
1779          * configurations between queues and interrupt vectors is needed, so
1780          * some error caused by the residual configurations, such as the
1781          * unexpected interrupt, can be avoid.
1782          */
1783         ret = hns3vf_init_ring_with_vector(hw);
1784         if (ret) {
1785                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1786                 goto err_init_hardware;
1787         }
1788
1789         ret = hns3vf_set_alive(hw, true);
1790         if (ret) {
1791                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1792                 goto err_init_hardware;
1793         }
1794
1795         return 0;
1796
1797 err_init_hardware:
1798         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1799         return ret;
1800 }
1801
1802 static int
1803 hns3vf_clear_vport_list(struct hns3_hw *hw)
1804 {
1805         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1806                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1807                                  NULL, 0);
1808 }
1809
1810 static int
1811 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1812 {
1813         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1814         struct hns3_adapter *hns = eth_dev->data->dev_private;
1815         struct hns3_hw *hw = &hns->hw;
1816         int ret;
1817
1818         PMD_INIT_FUNC_TRACE();
1819
1820         /* Get hardware io base address from pcie BAR2 IO space */
1821         hw->io_base = pci_dev->mem_resource[2].addr;
1822
1823         /* Firmware command queue initialize */
1824         ret = hns3_cmd_init_queue(hw);
1825         if (ret) {
1826                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1827                 goto err_cmd_init_queue;
1828         }
1829
1830         /* Firmware command initialize */
1831         ret = hns3_cmd_init(hw);
1832         if (ret) {
1833                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1834                 goto err_cmd_init;
1835         }
1836
1837         /* Get VF resource */
1838         ret = hns3_query_vf_resource(hw);
1839         if (ret)
1840                 goto err_cmd_init;
1841
1842         rte_spinlock_init(&hw->mbx_resp.lock);
1843
1844         hns3vf_clear_event_cause(hw, 0);
1845
1846         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1847                                          hns3vf_interrupt_handler, eth_dev);
1848         if (ret) {
1849                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1850                 goto err_intr_callback_register;
1851         }
1852
1853         /* Enable interrupt */
1854         rte_intr_enable(&pci_dev->intr_handle);
1855         hns3vf_enable_irq0(hw);
1856
1857         /* Get configuration from PF */
1858         ret = hns3vf_get_configuration(hw);
1859         if (ret) {
1860                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1861                 goto err_get_config;
1862         }
1863
1864         ret = hns3_tqp_stats_init(hw);
1865         if (ret)
1866                 goto err_get_config;
1867
1868         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1869         if (ret) {
1870                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1871                 goto err_set_tc_queue;
1872         }
1873
1874         ret = hns3vf_clear_vport_list(hw);
1875         if (ret) {
1876                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1877                 goto err_set_tc_queue;
1878         }
1879
1880         ret = hns3vf_init_hardware(hns);
1881         if (ret)
1882                 goto err_set_tc_queue;
1883
1884         hns3_rss_set_default_args(hw);
1885
1886         return 0;
1887
1888 err_set_tc_queue:
1889         hns3_tqp_stats_uninit(hw);
1890
1891 err_get_config:
1892         hns3vf_disable_irq0(hw);
1893         rte_intr_disable(&pci_dev->intr_handle);
1894         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1895                              eth_dev);
1896 err_intr_callback_register:
1897 err_cmd_init:
1898         hns3_cmd_uninit(hw);
1899         hns3_cmd_destroy_queue(hw);
1900 err_cmd_init_queue:
1901         hw->io_base = NULL;
1902
1903         return ret;
1904 }
1905
1906 static void
1907 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1908 {
1909         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1910         struct hns3_adapter *hns = eth_dev->data->dev_private;
1911         struct hns3_hw *hw = &hns->hw;
1912
1913         PMD_INIT_FUNC_TRACE();
1914
1915         hns3_rss_uninit(hns);
1916         (void)hns3_config_gro(hw, false);
1917         (void)hns3vf_set_alive(hw, false);
1918         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1919         hns3_tqp_stats_uninit(hw);
1920         hns3vf_disable_irq0(hw);
1921         rte_intr_disable(&pci_dev->intr_handle);
1922         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1923                              eth_dev);
1924         hns3_cmd_uninit(hw);
1925         hns3_cmd_destroy_queue(hw);
1926         hw->io_base = NULL;
1927 }
1928
1929 static int
1930 hns3vf_do_stop(struct hns3_adapter *hns)
1931 {
1932         struct hns3_hw *hw = &hns->hw;
1933         int ret;
1934
1935         hw->mac.link_status = ETH_LINK_DOWN;
1936
1937         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1938                 hns3vf_configure_mac_addr(hns, true);
1939                 ret = hns3_reset_all_tqps(hns);
1940                 if (ret) {
1941                         hns3_err(hw, "failed to reset all queues ret = %d",
1942                                  ret);
1943                         return ret;
1944                 }
1945         }
1946         return 0;
1947 }
1948
1949 static void
1950 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1951 {
1952         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1954         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1955         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1956         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1957         uint16_t q_id;
1958
1959         if (dev->data->dev_conf.intr_conf.rxq == 0)
1960                 return;
1961
1962         /* unmap the ring with vector */
1963         if (rte_intr_allow_others(intr_handle)) {
1964                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1965                 base = RTE_INTR_VEC_RXTX_OFFSET;
1966         }
1967         if (rte_intr_dp_is_en(intr_handle)) {
1968                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1969                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1970                                                            HNS3_RING_TYPE_RX,
1971                                                            q_id);
1972                         if (vec < base + intr_handle->nb_efd - 1)
1973                                 vec++;
1974                 }
1975         }
1976         /* Clean datapath event and queue/vec mapping */
1977         rte_intr_efd_disable(intr_handle);
1978         if (intr_handle->intr_vec) {
1979                 rte_free(intr_handle->intr_vec);
1980                 intr_handle->intr_vec = NULL;
1981         }
1982 }
1983
1984 static int
1985 hns3vf_dev_stop(struct rte_eth_dev *dev)
1986 {
1987         struct hns3_adapter *hns = dev->data->dev_private;
1988         struct hns3_hw *hw = &hns->hw;
1989
1990         PMD_INIT_FUNC_TRACE();
1991         dev->data->dev_started = 0;
1992
1993         hw->adapter_state = HNS3_NIC_STOPPING;
1994         hns3_set_rxtx_function(dev);
1995         rte_wmb();
1996         /* Disable datapath on secondary process. */
1997         hns3_mp_req_stop_rxtx(dev);
1998         /* Prevent crashes when queues are still in use. */
1999         rte_delay_ms(hw->tqps_num);
2000
2001         rte_spinlock_lock(&hw->lock);
2002         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2003                 hns3_stop_tqps(hw);
2004                 hns3vf_do_stop(hns);
2005                 hns3vf_unmap_rx_interrupt(dev);
2006                 hns3_dev_release_mbufs(hns);
2007                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2008         }
2009         hns3_rx_scattered_reset(dev);
2010         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
2011         rte_spinlock_unlock(&hw->lock);
2012
2013         return 0;
2014 }
2015
2016 static int
2017 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2018 {
2019         struct hns3_adapter *hns = eth_dev->data->dev_private;
2020         struct hns3_hw *hw = &hns->hw;
2021         int ret = 0;
2022
2023         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2024                 rte_free(eth_dev->process_private);
2025                 eth_dev->process_private = NULL;
2026                 return 0;
2027         }
2028
2029         if (hw->adapter_state == HNS3_NIC_STARTED)
2030                 ret = hns3vf_dev_stop(eth_dev);
2031
2032         hw->adapter_state = HNS3_NIC_CLOSING;
2033         hns3_reset_abort(hns);
2034         hw->adapter_state = HNS3_NIC_CLOSED;
2035         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2036         hns3vf_configure_all_mc_mac_addr(hns, true);
2037         hns3vf_remove_all_vlan_table(hns);
2038         hns3vf_uninit_vf(eth_dev);
2039         hns3_free_all_queues(eth_dev);
2040         rte_free(hw->reset.wait_data);
2041         rte_free(eth_dev->process_private);
2042         eth_dev->process_private = NULL;
2043         hns3_mp_uninit_primary();
2044         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2045
2046         return ret;
2047 }
2048
2049 static int
2050 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2051                       size_t fw_size)
2052 {
2053         struct hns3_adapter *hns = eth_dev->data->dev_private;
2054         struct hns3_hw *hw = &hns->hw;
2055         uint32_t version = hw->fw_version;
2056         int ret;
2057
2058         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2059                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2060                                       HNS3_FW_VERSION_BYTE3_S),
2061                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2062                                       HNS3_FW_VERSION_BYTE2_S),
2063                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2064                                       HNS3_FW_VERSION_BYTE1_S),
2065                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2066                                       HNS3_FW_VERSION_BYTE0_S));
2067         ret += 1; /* add the size of '\0' */
2068         if (fw_size < (uint32_t)ret)
2069                 return ret;
2070         else
2071                 return 0;
2072 }
2073
2074 static int
2075 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2076                        __rte_unused int wait_to_complete)
2077 {
2078         struct hns3_adapter *hns = eth_dev->data->dev_private;
2079         struct hns3_hw *hw = &hns->hw;
2080         struct hns3_mac *mac = &hw->mac;
2081         struct rte_eth_link new_link;
2082
2083         memset(&new_link, 0, sizeof(new_link));
2084         switch (mac->link_speed) {
2085         case ETH_SPEED_NUM_10M:
2086         case ETH_SPEED_NUM_100M:
2087         case ETH_SPEED_NUM_1G:
2088         case ETH_SPEED_NUM_10G:
2089         case ETH_SPEED_NUM_25G:
2090         case ETH_SPEED_NUM_40G:
2091         case ETH_SPEED_NUM_50G:
2092         case ETH_SPEED_NUM_100G:
2093         case ETH_SPEED_NUM_200G:
2094                 new_link.link_speed = mac->link_speed;
2095                 break;
2096         default:
2097                 new_link.link_speed = ETH_SPEED_NUM_100M;
2098                 break;
2099         }
2100
2101         new_link.link_duplex = mac->link_duplex;
2102         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2103         new_link.link_autoneg =
2104             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2105
2106         return rte_eth_linkstatus_set(eth_dev, &new_link);
2107 }
2108
2109 static int
2110 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2111 {
2112         struct hns3_hw *hw = &hns->hw;
2113         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2114         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2115         int ret;
2116
2117         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2118         if (ret)
2119                 return ret;
2120
2121         ret = hns3_init_queues(hns, reset_queue);
2122         if (ret)
2123                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2124
2125         return ret;
2126 }
2127
2128 static int
2129 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2130 {
2131         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2132         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2133         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2135         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2136         uint32_t intr_vector;
2137         uint16_t q_id;
2138         int ret;
2139
2140         /*
2141          * hns3 needs a separate interrupt to be used as event interrupt which
2142          * could not be shared with task queue pair, so KERNEL drivers need
2143          * support multiple interrupt vectors.
2144          */
2145         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2146             !rte_intr_cap_multiple(intr_handle))
2147                 return 0;
2148
2149         rte_intr_disable(intr_handle);
2150         intr_vector = hw->used_rx_queues;
2151         /* It creates event fd for each intr vector when MSIX is used */
2152         if (rte_intr_efd_enable(intr_handle, intr_vector))
2153                 return -EINVAL;
2154
2155         if (intr_handle->intr_vec == NULL) {
2156                 intr_handle->intr_vec =
2157                         rte_zmalloc("intr_vec",
2158                                     hw->used_rx_queues * sizeof(int), 0);
2159                 if (intr_handle->intr_vec == NULL) {
2160                         hns3_err(hw, "Failed to allocate %u rx_queues"
2161                                      " intr_vec", hw->used_rx_queues);
2162                         ret = -ENOMEM;
2163                         goto vf_alloc_intr_vec_error;
2164                 }
2165         }
2166
2167         if (rte_intr_allow_others(intr_handle)) {
2168                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2169                 base = RTE_INTR_VEC_RXTX_OFFSET;
2170         }
2171
2172         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2173                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2174                                                    HNS3_RING_TYPE_RX, q_id);
2175                 if (ret)
2176                         goto vf_bind_vector_error;
2177                 intr_handle->intr_vec[q_id] = vec;
2178                 /*
2179                  * If there are not enough efds (e.g. not enough interrupt),
2180                  * remaining queues will be bond to the last interrupt.
2181                  */
2182                 if (vec < base + intr_handle->nb_efd - 1)
2183                         vec++;
2184         }
2185         rte_intr_enable(intr_handle);
2186         return 0;
2187
2188 vf_bind_vector_error:
2189         free(intr_handle->intr_vec);
2190         intr_handle->intr_vec = NULL;
2191 vf_alloc_intr_vec_error:
2192         rte_intr_efd_disable(intr_handle);
2193         return ret;
2194 }
2195
2196 static int
2197 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2198 {
2199         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2200         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2202         uint16_t q_id;
2203         int ret;
2204
2205         if (dev->data->dev_conf.intr_conf.rxq == 0)
2206                 return 0;
2207
2208         if (rte_intr_dp_is_en(intr_handle)) {
2209                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2210                         ret = hns3vf_bind_ring_with_vector(hw,
2211                                         intr_handle->intr_vec[q_id], true,
2212                                         HNS3_RING_TYPE_RX, q_id);
2213                         if (ret)
2214                                 return ret;
2215                 }
2216         }
2217
2218         return 0;
2219 }
2220
2221 static void
2222 hns3vf_restore_filter(struct rte_eth_dev *dev)
2223 {
2224         hns3_restore_rss_filter(dev);
2225 }
2226
2227 static int
2228 hns3vf_dev_start(struct rte_eth_dev *dev)
2229 {
2230         struct hns3_adapter *hns = dev->data->dev_private;
2231         struct hns3_hw *hw = &hns->hw;
2232         int ret;
2233
2234         PMD_INIT_FUNC_TRACE();
2235         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2236                 return -EBUSY;
2237
2238         rte_spinlock_lock(&hw->lock);
2239         hw->adapter_state = HNS3_NIC_STARTING;
2240         ret = hns3vf_do_start(hns, true);
2241         if (ret) {
2242                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2243                 rte_spinlock_unlock(&hw->lock);
2244                 return ret;
2245         }
2246         ret = hns3vf_map_rx_interrupt(dev);
2247         if (ret) {
2248                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2249                 rte_spinlock_unlock(&hw->lock);
2250                 return ret;
2251         }
2252
2253         /*
2254          * There are three register used to control the status of a TQP
2255          * (contains a pair of Tx queue and Rx queue) in the new version network
2256          * engine. One is used to control the enabling of Tx queue, the other is
2257          * used to control the enabling of Rx queue, and the last is the master
2258          * switch used to control the enabling of the tqp. The Tx register and
2259          * TQP register must be enabled at the same time to enable a Tx queue.
2260          * The same applies to the Rx queue. For the older network enginem, this
2261          * function only refresh the enabled flag, and it is used to update the
2262          * status of queue in the dpdk framework.
2263          */
2264         ret = hns3_start_all_txqs(dev);
2265         if (ret) {
2266                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2267                 rte_spinlock_unlock(&hw->lock);
2268                 return ret;
2269         }
2270
2271         ret = hns3_start_all_rxqs(dev);
2272         if (ret) {
2273                 hns3_stop_all_txqs(dev);
2274                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2275                 rte_spinlock_unlock(&hw->lock);
2276                 return ret;
2277         }
2278
2279         hw->adapter_state = HNS3_NIC_STARTED;
2280         rte_spinlock_unlock(&hw->lock);
2281
2282         hns3_rx_scattered_calc(dev);
2283         hns3_set_rxtx_function(dev);
2284         hns3_mp_req_start_rxtx(dev);
2285         hns3vf_service_handler(dev);
2286
2287         hns3vf_restore_filter(dev);
2288
2289         /* Enable interrupt of all rx queues before enabling queues */
2290         hns3_dev_all_rx_queue_intr_enable(hw, true);
2291
2292         /*
2293          * After finished the initialization, start all tqps to receive/transmit
2294          * packets and refresh all queue status.
2295          */
2296         hns3_start_tqps(hw);
2297
2298         return ret;
2299 }
2300
2301 static bool
2302 is_vf_reset_done(struct hns3_hw *hw)
2303 {
2304 #define HNS3_FUN_RST_ING_BITS \
2305         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2306          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2307          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2308          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2309
2310         uint32_t val;
2311
2312         if (hw->reset.level == HNS3_VF_RESET) {
2313                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2314                 if (val & HNS3_VF_RST_ING_BIT)
2315                         return false;
2316         } else {
2317                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2318                 if (val & HNS3_FUN_RST_ING_BITS)
2319                         return false;
2320         }
2321         return true;
2322 }
2323
2324 bool
2325 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2326 {
2327         struct hns3_hw *hw = &hns->hw;
2328         enum hns3_reset_level reset;
2329
2330         /*
2331          * According to the protocol of PCIe, FLR to a PF device resets the PF
2332          * state as well as the SR-IOV extended capability including VF Enable
2333          * which means that VFs no longer exist.
2334          *
2335          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2336          * is in FLR stage, the register state of VF device is not reliable,
2337          * so register states detection can not be carried out. In this case,
2338          * we just ignore the register states and return false to indicate that
2339          * there are no other reset states that need to be processed by driver.
2340          */
2341         if (hw->reset.level == HNS3_VF_FULL_RESET)
2342                 return false;
2343
2344         /* Check the registers to confirm whether there is reset pending */
2345         hns3vf_check_event_cause(hns, NULL);
2346         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2347         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2348                 hns3_warn(hw, "High level reset %d is pending", reset);
2349                 return true;
2350         }
2351         return false;
2352 }
2353
2354 static int
2355 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2356 {
2357         struct hns3_hw *hw = &hns->hw;
2358         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2359         struct timeval tv;
2360
2361         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2362                 /*
2363                  * After vf reset is ready, the PF may not have completed
2364                  * the reset processing. The vf sending mbox to PF may fail
2365                  * during the pf reset, so it is better to add extra delay.
2366                  */
2367                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2368                     hw->reset.level == HNS3_FLR_RESET)
2369                         return 0;
2370                 /* Reset retry process, no need to add extra delay. */
2371                 if (hw->reset.attempts)
2372                         return 0;
2373                 if (wait_data->check_completion == NULL)
2374                         return 0;
2375
2376                 wait_data->check_completion = NULL;
2377                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2378                 wait_data->count = 1;
2379                 wait_data->result = HNS3_WAIT_REQUEST;
2380                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2381                                   wait_data);
2382                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2383                 return -EAGAIN;
2384         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2385                 gettimeofday(&tv, NULL);
2386                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2387                           tv.tv_sec, tv.tv_usec);
2388                 return -ETIME;
2389         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2390                 return -EAGAIN;
2391
2392         wait_data->hns = hns;
2393         wait_data->check_completion = is_vf_reset_done;
2394         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2395                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2396         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2397         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2398         wait_data->result = HNS3_WAIT_REQUEST;
2399         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2400         return -EAGAIN;
2401 }
2402
2403 static int
2404 hns3vf_prepare_reset(struct hns3_adapter *hns)
2405 {
2406         struct hns3_hw *hw = &hns->hw;
2407         int ret = 0;
2408
2409         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2410                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2411                                         0, true, NULL, 0);
2412         }
2413         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2414
2415         return ret;
2416 }
2417
2418 static int
2419 hns3vf_stop_service(struct hns3_adapter *hns)
2420 {
2421         struct hns3_hw *hw = &hns->hw;
2422         struct rte_eth_dev *eth_dev;
2423
2424         eth_dev = &rte_eth_devices[hw->data->port_id];
2425         if (hw->adapter_state == HNS3_NIC_STARTED) {
2426                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2427                 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed,
2428                         hw->mac.link_duplex);
2429         }
2430         hw->mac.link_status = ETH_LINK_DOWN;
2431
2432         hns3_set_rxtx_function(eth_dev);
2433         rte_wmb();
2434         /* Disable datapath on secondary process. */
2435         hns3_mp_req_stop_rxtx(eth_dev);
2436         rte_delay_ms(hw->tqps_num);
2437
2438         rte_spinlock_lock(&hw->lock);
2439         if (hw->adapter_state == HNS3_NIC_STARTED ||
2440             hw->adapter_state == HNS3_NIC_STOPPING) {
2441                 hns3_enable_all_queues(hw, false);
2442                 hns3vf_do_stop(hns);
2443                 hw->reset.mbuf_deferred_free = true;
2444         } else
2445                 hw->reset.mbuf_deferred_free = false;
2446
2447         /*
2448          * It is cumbersome for hardware to pick-and-choose entries for deletion
2449          * from table space. Hence, for function reset software intervention is
2450          * required to delete the entries.
2451          */
2452         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2453                 hns3vf_configure_all_mc_mac_addr(hns, true);
2454         rte_spinlock_unlock(&hw->lock);
2455
2456         return 0;
2457 }
2458
2459 static int
2460 hns3vf_start_service(struct hns3_adapter *hns)
2461 {
2462         struct hns3_hw *hw = &hns->hw;
2463         struct rte_eth_dev *eth_dev;
2464
2465         eth_dev = &rte_eth_devices[hw->data->port_id];
2466         hns3_set_rxtx_function(eth_dev);
2467         hns3_mp_req_start_rxtx(eth_dev);
2468         if (hw->adapter_state == HNS3_NIC_STARTED) {
2469                 hns3vf_service_handler(eth_dev);
2470
2471                 /* Enable interrupt of all rx queues before enabling queues */
2472                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2473                 /*
2474                  * Enable state of each rxq and txq will be recovered after
2475                  * reset, so we need to restore them before enable all tqps;
2476                  */
2477                 hns3_restore_tqp_enable_state(hw);
2478                 /*
2479                  * When finished the initialization, enable queues to receive
2480                  * and transmit packets.
2481                  */
2482                 hns3_enable_all_queues(hw, true);
2483         }
2484
2485         return 0;
2486 }
2487
2488 static int
2489 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2490 {
2491         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2492         struct rte_ether_addr *hw_mac;
2493         int ret;
2494
2495         /*
2496          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2497          * on the host by "ip link set ..." command. If the hns3 PF kernel
2498          * ethdev driver sets the MAC address for VF device after the
2499          * initialization of the related VF device, the PF driver will notify
2500          * VF driver to reset VF device to make the new MAC address effective
2501          * immediately. The hns3 VF PMD driver should check whether the MAC
2502          * address has been changed by the PF kernel ethdev driver, if changed
2503          * VF driver should configure hardware using the new MAC address in the
2504          * recovering hardware configuration stage of the reset process.
2505          */
2506         ret = hns3vf_get_host_mac_addr(hw);
2507         if (ret)
2508                 return ret;
2509
2510         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2511         ret = rte_is_zero_ether_addr(hw_mac);
2512         if (ret) {
2513                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2514         } else {
2515                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2516                 if (!ret) {
2517                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2518                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2519                                               &hw->data->mac_addrs[0]);
2520                         hns3_warn(hw, "Default MAC address has been changed to:"
2521                                   " %s by the host PF kernel ethdev driver",
2522                                   mac_str);
2523                 }
2524         }
2525
2526         return 0;
2527 }
2528
2529 static int
2530 hns3vf_restore_conf(struct hns3_adapter *hns)
2531 {
2532         struct hns3_hw *hw = &hns->hw;
2533         int ret;
2534
2535         ret = hns3vf_check_default_mac_change(hw);
2536         if (ret)
2537                 return ret;
2538
2539         ret = hns3vf_configure_mac_addr(hns, false);
2540         if (ret)
2541                 return ret;
2542
2543         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2544         if (ret)
2545                 goto err_mc_mac;
2546
2547         ret = hns3vf_restore_promisc(hns);
2548         if (ret)
2549                 goto err_vlan_table;
2550
2551         ret = hns3vf_restore_vlan_conf(hns);
2552         if (ret)
2553                 goto err_vlan_table;
2554
2555         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2556         if (ret)
2557                 goto err_vlan_table;
2558
2559         ret = hns3vf_restore_rx_interrupt(hw);
2560         if (ret)
2561                 goto err_vlan_table;
2562
2563         ret = hns3_restore_gro_conf(hw);
2564         if (ret)
2565                 goto err_vlan_table;
2566
2567         if (hw->adapter_state == HNS3_NIC_STARTED) {
2568                 ret = hns3vf_do_start(hns, false);
2569                 if (ret)
2570                         goto err_vlan_table;
2571                 hns3_info(hw, "hns3vf dev restart successful!");
2572         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2573                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2574         return 0;
2575
2576 err_vlan_table:
2577         hns3vf_configure_all_mc_mac_addr(hns, true);
2578 err_mc_mac:
2579         hns3vf_configure_mac_addr(hns, true);
2580         return ret;
2581 }
2582
2583 static enum hns3_reset_level
2584 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2585 {
2586         enum hns3_reset_level reset_level;
2587
2588         /* return the highest priority reset level amongst all */
2589         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2590                 reset_level = HNS3_VF_RESET;
2591         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2592                 reset_level = HNS3_VF_FULL_RESET;
2593         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2594                 reset_level = HNS3_VF_PF_FUNC_RESET;
2595         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2596                 reset_level = HNS3_VF_FUNC_RESET;
2597         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2598                 reset_level = HNS3_FLR_RESET;
2599         else
2600                 reset_level = HNS3_NONE_RESET;
2601
2602         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2603                 return HNS3_NONE_RESET;
2604
2605         return reset_level;
2606 }
2607
2608 static void
2609 hns3vf_reset_service(void *param)
2610 {
2611         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2612         struct hns3_hw *hw = &hns->hw;
2613         enum hns3_reset_level reset_level;
2614         struct timeval tv_delta;
2615         struct timeval tv_start;
2616         struct timeval tv;
2617         uint64_t msec;
2618
2619         /*
2620          * The interrupt is not triggered within the delay time.
2621          * The interrupt may have been lost. It is necessary to handle
2622          * the interrupt to recover from the error.
2623          */
2624         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2625                             SCHEDULE_DEFERRED) {
2626                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2627                                  __ATOMIC_RELAXED);
2628                 hns3_err(hw, "Handling interrupts in delayed tasks");
2629                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2630                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2631                 if (reset_level == HNS3_NONE_RESET) {
2632                         hns3_err(hw, "No reset level is set, try global reset");
2633                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2634                 }
2635         }
2636         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2637
2638         /*
2639          * Hardware reset has been notified, we now have to poll & check if
2640          * hardware has actually completed the reset sequence.
2641          */
2642         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2643         if (reset_level != HNS3_NONE_RESET) {
2644                 gettimeofday(&tv_start, NULL);
2645                 hns3_reset_process(hns, reset_level);
2646                 gettimeofday(&tv, NULL);
2647                 timersub(&tv, &tv_start, &tv_delta);
2648                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2649                        tv_delta.tv_usec / USEC_PER_MSEC;
2650                 if (msec > HNS3_RESET_PROCESS_MS)
2651                         hns3_err(hw, "%d handle long time delta %" PRIx64
2652                                  " ms time=%ld.%.6ld",
2653                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2654         }
2655 }
2656
2657 static int
2658 hns3vf_reinit_dev(struct hns3_adapter *hns)
2659 {
2660         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2661         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2662         struct hns3_hw *hw = &hns->hw;
2663         int ret;
2664
2665         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2666                 rte_intr_disable(&pci_dev->intr_handle);
2667                 ret = hns3vf_set_bus_master(pci_dev, true);
2668                 if (ret < 0) {
2669                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2670                         return ret;
2671                 }
2672         }
2673
2674         /* Firmware command initialize */
2675         ret = hns3_cmd_init(hw);
2676         if (ret) {
2677                 hns3_err(hw, "Failed to init cmd: %d", ret);
2678                 return ret;
2679         }
2680
2681         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2682                 /*
2683                  * UIO enables msix by writing the pcie configuration space
2684                  * vfio_pci enables msix in rte_intr_enable.
2685                  */
2686                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2687                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2688                         if (hns3vf_enable_msix(pci_dev, true))
2689                                 hns3_err(hw, "Failed to enable msix");
2690                 }
2691
2692                 rte_intr_enable(&pci_dev->intr_handle);
2693         }
2694
2695         ret = hns3_reset_all_tqps(hns);
2696         if (ret) {
2697                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2698                 return ret;
2699         }
2700
2701         ret = hns3vf_init_hardware(hns);
2702         if (ret) {
2703                 hns3_err(hw, "Failed to init hardware: %d", ret);
2704                 return ret;
2705         }
2706
2707         return 0;
2708 }
2709
2710 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2711         .dev_configure      = hns3vf_dev_configure,
2712         .dev_start          = hns3vf_dev_start,
2713         .dev_stop           = hns3vf_dev_stop,
2714         .dev_close          = hns3vf_dev_close,
2715         .mtu_set            = hns3vf_dev_mtu_set,
2716         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2717         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2718         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2719         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2720         .stats_get          = hns3_stats_get,
2721         .stats_reset        = hns3_stats_reset,
2722         .xstats_get         = hns3_dev_xstats_get,
2723         .xstats_get_names   = hns3_dev_xstats_get_names,
2724         .xstats_reset       = hns3_dev_xstats_reset,
2725         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2726         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2727         .dev_infos_get      = hns3vf_dev_infos_get,
2728         .fw_version_get     = hns3vf_fw_version_get,
2729         .rx_queue_setup     = hns3_rx_queue_setup,
2730         .tx_queue_setup     = hns3_tx_queue_setup,
2731         .rx_queue_release   = hns3_dev_rx_queue_release,
2732         .tx_queue_release   = hns3_dev_tx_queue_release,
2733         .rx_queue_start     = hns3_dev_rx_queue_start,
2734         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2735         .tx_queue_start     = hns3_dev_tx_queue_start,
2736         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2737         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2738         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2739         .rxq_info_get       = hns3_rxq_info_get,
2740         .txq_info_get       = hns3_txq_info_get,
2741         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2742         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2743         .mac_addr_add       = hns3vf_add_mac_addr,
2744         .mac_addr_remove    = hns3vf_remove_mac_addr,
2745         .mac_addr_set       = hns3vf_set_default_mac_addr,
2746         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2747         .link_update        = hns3vf_dev_link_update,
2748         .rss_hash_update    = hns3_dev_rss_hash_update,
2749         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2750         .reta_update        = hns3_dev_rss_reta_update,
2751         .reta_query         = hns3_dev_rss_reta_query,
2752         .filter_ctrl        = hns3_dev_filter_ctrl,
2753         .vlan_filter_set    = hns3vf_vlan_filter_set,
2754         .vlan_offload_set   = hns3vf_vlan_offload_set,
2755         .get_reg            = hns3_get_regs,
2756         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2757 };
2758
2759 static const struct hns3_reset_ops hns3vf_reset_ops = {
2760         .reset_service       = hns3vf_reset_service,
2761         .stop_service        = hns3vf_stop_service,
2762         .prepare_reset       = hns3vf_prepare_reset,
2763         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2764         .reinit_dev          = hns3vf_reinit_dev,
2765         .restore_conf        = hns3vf_restore_conf,
2766         .start_service       = hns3vf_start_service,
2767 };
2768
2769 static int
2770 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2771 {
2772         struct hns3_adapter *hns = eth_dev->data->dev_private;
2773         struct hns3_hw *hw = &hns->hw;
2774         int ret;
2775
2776         PMD_INIT_FUNC_TRACE();
2777
2778         eth_dev->process_private = (struct hns3_process_private *)
2779             rte_zmalloc_socket("hns3_filter_list",
2780                                sizeof(struct hns3_process_private),
2781                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2782         if (eth_dev->process_private == NULL) {
2783                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2784                 return -ENOMEM;
2785         }
2786
2787         /* initialize flow filter lists */
2788         hns3_filterlist_init(eth_dev);
2789
2790         hns3_set_rxtx_function(eth_dev);
2791         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2792         eth_dev->rx_queue_count = hns3_rx_queue_count;
2793         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2794                 ret = hns3_mp_init_secondary();
2795                 if (ret) {
2796                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2797                                           "process, ret = %d", ret);
2798                         goto err_mp_init_secondary;
2799                 }
2800
2801                 hw->secondary_cnt++;
2802                 return 0;
2803         }
2804
2805         ret = hns3_mp_init_primary();
2806         if (ret) {
2807                 PMD_INIT_LOG(ERR,
2808                              "Failed to init for primary process, ret = %d",
2809                              ret);
2810                 goto err_mp_init_primary;
2811         }
2812
2813         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2814         hns->is_vf = true;
2815         hw->data = eth_dev->data;
2816
2817         ret = hns3_reset_init(hw);
2818         if (ret)
2819                 goto err_init_reset;
2820         hw->reset.ops = &hns3vf_reset_ops;
2821
2822         ret = hns3vf_init_vf(eth_dev);
2823         if (ret) {
2824                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2825                 goto err_init_vf;
2826         }
2827
2828         /* Allocate memory for storing MAC addresses */
2829         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2830                                                sizeof(struct rte_ether_addr) *
2831                                                HNS3_VF_UC_MACADDR_NUM, 0);
2832         if (eth_dev->data->mac_addrs == NULL) {
2833                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2834                              "to store MAC addresses",
2835                              sizeof(struct rte_ether_addr) *
2836                              HNS3_VF_UC_MACADDR_NUM);
2837                 ret = -ENOMEM;
2838                 goto err_rte_zmalloc;
2839         }
2840
2841         /*
2842          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2843          * on the host by "ip link set ..." command. To avoid some incorrect
2844          * scenes, for example, hns3 VF PMD driver fails to receive and send
2845          * packets after user configure the MAC address by using the
2846          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2847          * address strategy as the hns3 kernel ethdev driver in the
2848          * initialization. If user configure a MAC address by the ip command
2849          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2850          * start with a random MAC address in the initialization.
2851          */
2852         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2853                 rte_eth_random_addr(hw->mac.mac_addr);
2854         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2855                             &eth_dev->data->mac_addrs[0]);
2856
2857         hw->adapter_state = HNS3_NIC_INITIALIZED;
2858
2859         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2860                             SCHEDULE_PENDING) {
2861                 hns3_err(hw, "Reschedule reset service after dev_init");
2862                 hns3_schedule_reset(hns);
2863         } else {
2864                 /* IMP will wait ready flag before reset */
2865                 hns3_notify_reset_ready(hw, false);
2866         }
2867         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2868                           eth_dev);
2869         return 0;
2870
2871 err_rte_zmalloc:
2872         hns3vf_uninit_vf(eth_dev);
2873
2874 err_init_vf:
2875         rte_free(hw->reset.wait_data);
2876
2877 err_init_reset:
2878         hns3_mp_uninit_primary();
2879
2880 err_mp_init_primary:
2881 err_mp_init_secondary:
2882         eth_dev->dev_ops = NULL;
2883         eth_dev->rx_pkt_burst = NULL;
2884         eth_dev->tx_pkt_burst = NULL;
2885         eth_dev->tx_pkt_prepare = NULL;
2886         rte_free(eth_dev->process_private);
2887         eth_dev->process_private = NULL;
2888
2889         return ret;
2890 }
2891
2892 static int
2893 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2894 {
2895         struct hns3_adapter *hns = eth_dev->data->dev_private;
2896         struct hns3_hw *hw = &hns->hw;
2897
2898         PMD_INIT_FUNC_TRACE();
2899
2900         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2901                 rte_free(eth_dev->process_private);
2902                 eth_dev->process_private = NULL;
2903                 return 0;
2904         }
2905
2906         if (hw->adapter_state < HNS3_NIC_CLOSING)
2907                 hns3vf_dev_close(eth_dev);
2908
2909         hw->adapter_state = HNS3_NIC_REMOVED;
2910         return 0;
2911 }
2912
2913 static int
2914 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2915                      struct rte_pci_device *pci_dev)
2916 {
2917         return rte_eth_dev_pci_generic_probe(pci_dev,
2918                                              sizeof(struct hns3_adapter),
2919                                              hns3vf_dev_init);
2920 }
2921
2922 static int
2923 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2924 {
2925         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2926 }
2927
2928 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2929         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2930         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2931         { .vendor_id = 0, }, /* sentinel */
2932 };
2933
2934 static struct rte_pci_driver rte_hns3vf_pmd = {
2935         .id_table = pci_id_hns3vf_map,
2936         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2937         .probe = eth_hns3vf_pci_probe,
2938         .remove = eth_hns3vf_pci_remove,
2939 };
2940
2941 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2942 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2943 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");