drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 209 {
 210         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 211         struct rte_ether_addr *addr;
 212         int ret;
 213         int i;
 214
 215         for (i = 0; i < hw->mc_addrs_num; i++) {
 216                 addr = &hw->mc_addrs[i];
 217                 /* Check if there are duplicate addresses */
 218                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 219                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 220                                               addr);
 221                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 222                                  "(%s) is added by the set_mc_mac_addr_list "
 223                                  "API", mac_str);
 224                         return -EINVAL;
 225                 }
 226         }
 227
 228         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 229         if (ret) {
 230                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 231                                       mac_addr);
 232                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 233                          mac_str, ret);
 234         }
 235         return ret;
 236 }
 237
 238 static int
 239 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 240                     __rte_unused uint32_t idx,
 241                     __rte_unused uint32_t pool)
 242 {
 243         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 244         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 245         int ret;
 246
 247         rte_spinlock_lock(&hw->lock);
 248
 249         /*
 250          * In hns3 network engine adding UC and MC mac address with different
 251          * commands with firmware. We need to determine whether the input
 252          * address is a UC or a MC address to call different commands.
 253          * By the way, it is recommended calling the API function named
 254          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 255          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 256          * may affect the specifications of UC mac addresses.
 257          */
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 260         else
 261                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 268                          ret);
 269         }
 270
 271         return ret;
 272 }
 273
 274 static void
 275 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 276 {
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         /* index will be checked by upper level rte interface */
 279         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         rte_spinlock_lock(&hw->lock);
 284
 285         if (rte_is_multicast_ether_addr(mac_addr))
 286                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 287         else
 288                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 289
 290         rte_spinlock_unlock(&hw->lock);
 291         if (ret) {
 292                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 293                                       mac_addr);
 294                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 295                          mac_str, ret);
 296         }
 297 }
 298
 299 static int
 300 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 301                             struct rte_ether_addr *mac_addr)
 302 {
 303 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 304         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 305         struct rte_ether_addr *old_addr;
 306         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 307         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 308         int ret;
 309
 310         /*
 311          * It has been guaranteed that input parameter named mac_addr is valid
 312          * address in the rte layer of DPDK framework.
 313          */
 314         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 315         rte_spinlock_lock(&hw->lock);
 316         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 317         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 318                RTE_ETHER_ADDR_LEN);
 319
 320         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 321                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 322                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 323         if (ret) {
 324                 /*
 325                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 326                  * driver. When user has configured a MAC address for VF device
 327                  * by "ip link set ..." command based on the PF device, the hns3
 328                  * PF kernel ethdev driver does not allow VF driver to request
 329                  * reconfiguring a different default MAC address, and return
 330                  * -EPREM to VF driver through mailbox.
 331                  */
 332                 if (ret == -EPERM) {
 333                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 334                                               old_addr);
 335                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 336                                   mac_str);
 337                 } else {
 338                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 339                                               mac_addr);
 340                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 341                                  mac_str, ret);
 342                 }
 343         }
 344
 345         rte_ether_addr_copy(mac_addr,
 346                             (struct rte_ether_addr *)hw->mac.mac_addr);
 347         rte_spinlock_unlock(&hw->lock);
 348
 349         return ret;
 350 }
 351
 352 static int
 353 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 354 {
 355         struct hns3_hw *hw = &hns->hw;
 356         struct rte_ether_addr *addr;
 357         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 358         int err = 0;
 359         int ret;
 360         int i;
 361
 362         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 363                 addr = &hw->data->mac_addrs[i];
 364                 if (rte_is_zero_ether_addr(addr))
 365                         continue;
 366                 if (rte_is_multicast_ether_addr(addr))
 367                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 368                               hns3vf_add_mc_mac_addr(hw, addr);
 369                 else
 370                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 371                               hns3vf_add_uc_mac_addr(hw, addr);
 372
 373                 if (ret) {
 374                         err = ret;
 375                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 376                                               addr);
 377                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 378                                  "ret = %d.", del ? "remove" : "restore",
 379                                  mac_str, i, ret);
 380                 }
 381         }
 382         return err;
 383 }
 384
 385 static int
 386 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 387                        struct rte_ether_addr *mac_addr)
 388 {
 389         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 390         int ret;
 391
 392         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 393                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 394                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 395                                 NULL, 0);
 396         if (ret) {
 397                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 398                                       mac_addr);
 399                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 400                          mac_str, ret);
 401         }
 402
 403         return ret;
 404 }
 405
 406 static int
 407 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 408                           struct rte_ether_addr *mac_addr)
 409 {
 410         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 411         int ret;
 412
 413         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 414                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 415                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 416                                 NULL, 0);
 417         if (ret) {
 418                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 419                                       mac_addr);
 420                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 421                          mac_str, ret);
 422         }
 423
 424         return ret;
 425 }
 426
 427 static int
 428 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 429                              struct rte_ether_addr *mc_addr_set,
 430                              uint32_t nb_mc_addr)
 431 {
 432         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 433         struct rte_ether_addr *addr;
 434         uint32_t i;
 435         uint32_t j;
 436
 437         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 438                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 439                          "invalid. valid range: 0~%d",
 440                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 441                 return -EINVAL;
 442         }
 443
 444         /* Check if input mac addresses are valid */
 445         for (i = 0; i < nb_mc_addr; i++) {
 446                 addr = &mc_addr_set[i];
 447                 if (!rte_is_multicast_ether_addr(addr)) {
 448                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 449                                               addr);
 450                         hns3_err(hw,
 451                                  "failed to set mc mac addr, addr(%s) invalid.",
 452                                  mac_str);
 453                         return -EINVAL;
 454                 }
 455
 456                 /* Check if there are duplicate addresses */
 457                 for (j = i + 1; j < nb_mc_addr; j++) {
 458                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 459                                 hns3_ether_format_addr(mac_str,
 460                                                       RTE_ETHER_ADDR_FMT_SIZE,
 461                                                       addr);
 462                                 hns3_err(hw, "failed to set mc mac addr, "
 463                                          "addrs invalid. two same addrs(%s).",
 464                                          mac_str);
 465                                 return -EINVAL;
 466                         }
 467                 }
 468
 469                 /*
 470                  * Check if there are duplicate addresses between mac_addrs
 471                  * and mc_addr_set
 472                  */
 473                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 474                         if (rte_is_same_ether_addr(addr,
 475                                                    &hw->data->mac_addrs[j])) {
 476                                 hns3_ether_format_addr(mac_str,
 477                                                       RTE_ETHER_ADDR_FMT_SIZE,
 478                                                       addr);
 479                                 hns3_err(hw, "failed to set mc mac addr, "
 480                                          "addrs invalid. addrs(%s) has already "
 481                                          "configured in mac_addr add API",
 482                                          mac_str);
 483                                 return -EINVAL;
 484                         }
 485                 }
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int
 492 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 493                             struct rte_ether_addr *mc_addr_set,
 494                             uint32_t nb_mc_addr)
 495 {
 496         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 497         struct rte_ether_addr *addr;
 498         int cur_addr_num;
 499         int set_addr_num;
 500         int num;
 501         int ret;
 502         int i;
 503
 504         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 505         if (ret)
 506                 return ret;
 507
 508         rte_spinlock_lock(&hw->lock);
 509         cur_addr_num = hw->mc_addrs_num;
 510         for (i = 0; i < cur_addr_num; i++) {
 511                 num = cur_addr_num - i - 1;
 512                 addr = &hw->mc_addrs[num];
 513                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 514                 if (ret) {
 515                         rte_spinlock_unlock(&hw->lock);
 516                         return ret;
 517                 }
 518
 519                 hw->mc_addrs_num--;
 520         }
 521
 522         set_addr_num = (int)nb_mc_addr;
 523         for (i = 0; i < set_addr_num; i++) {
 524                 addr = &mc_addr_set[i];
 525                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 526                 if (ret) {
 527                         rte_spinlock_unlock(&hw->lock);
 528                         return ret;
 529                 }
 530
 531                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 532                 hw->mc_addrs_num++;
 533         }
 534         rte_spinlock_unlock(&hw->lock);
 535
 536         return 0;
 537 }
 538
 539 static int
 540 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 541 {
 542         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 543         struct hns3_hw *hw = &hns->hw;
 544         struct rte_ether_addr *addr;
 545         int err = 0;
 546         int ret;
 547         int i;
 548
 549         for (i = 0; i < hw->mc_addrs_num; i++) {
 550                 addr = &hw->mc_addrs[i];
 551                 if (!rte_is_multicast_ether_addr(addr))
 552                         continue;
 553                 if (del)
 554                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 555                 else
 556                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 557                 if (ret) {
 558                         err = ret;
 559                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 560                                               addr);
 561                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 562                                  del ? "Remove" : "Restore", mac_str, ret);
 563                 }
 564         }
 565         return err;
 566 }
 567
 568 static int
 569 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 570                         bool en_uc_pmc, bool en_mc_pmc)
 571 {
 572         struct hns3_mbx_vf_to_pf_cmd *req;
 573         struct hns3_cmd_desc desc;
 574         int ret;
 575
 576         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 577
 578         /*
 579          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 580          * so there are some features for promiscuous/allmulticast mode in hns3
 581          * VF PMD driver as below:
 582          * 1. The promiscuous/allmulticast mode can be configured successfully
 583          *    only based on the trusted VF device. If based on the non trusted
 584          *    VF device, configuring promiscuous/allmulticast mode will fail.
 585          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 586          *    kernel ethdev driver on the host by the following command:
 587          *      "ip link set <eth num> vf <vf id> turst on"
 588          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 589          *    driver can receive the ingress and outgoing traffic. In the words,
 590          *    all the ingress packets, all the packets sent from the PF and
 591          *    other VFs on the same physical port.
 592          * 3. Note: Because of the hardware constraints, By default vlan filter
 593          *    is enabled and couldn't be turned off based on VF device, so vlan
 594          *    filter is still effective even in promiscuous mode. If upper
 595          *    applications don't call rte_eth_dev_vlan_filter API function to
 596          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 597          *    the packets with vlan tag in promiscuoue mode.
 598          */
 599         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 600         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 601         req->msg[1] = en_bc_pmc ? 1 : 0;
 602         req->msg[2] = en_uc_pmc ? 1 : 0;
 603         req->msg[3] = en_mc_pmc ? 1 : 0;
 604         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 605
 606         ret = hns3_cmd_send(hw, &desc, 1);
 607         if (ret)
 608                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 609
 610         return ret;
 611 }
 612
 613 static int
 614 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 615 {
 616         struct hns3_adapter *hns = dev->data->dev_private;
 617         struct hns3_hw *hw = &hns->hw;
 618         int ret;
 619
 620         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 621         if (ret)
 622                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 623                         ret);
 624         return ret;
 625 }
 626
 627 static int
 628 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 629 {
 630         bool allmulti = dev->data->all_multicast ? true : false;
 631         struct hns3_adapter *hns = dev->data->dev_private;
 632         struct hns3_hw *hw = &hns->hw;
 633         int ret;
 634
 635         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 636         if (ret)
 637                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 638                         ret);
 639         return ret;
 640 }
 641
 642 static int
 643 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 644 {
 645         struct hns3_adapter *hns = dev->data->dev_private;
 646         struct hns3_hw *hw = &hns->hw;
 647         int ret;
 648
 649         if (dev->data->promiscuous)
 650                 return 0;
 651
 652         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 653         if (ret)
 654                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 655                         ret);
 656         return ret;
 657 }
 658
 659 static int
 660 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 661 {
 662         struct hns3_adapter *hns = dev->data->dev_private;
 663         struct hns3_hw *hw = &hns->hw;
 664         int ret;
 665
 666         if (dev->data->promiscuous)
 667                 return 0;
 668
 669         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 670         if (ret)
 671                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 672                         ret);
 673         return ret;
 674 }
 675
 676 static int
 677 hns3vf_restore_promisc(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         bool allmulti = hw->data->all_multicast ? true : false;
 681
 682         if (hw->data->promiscuous)
 683                 return hns3vf_set_promisc_mode(hw, true, true, true);
 684
 685         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 686 }
 687
 688 static int
 689 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 690                              bool mmap, enum hns3_ring_type queue_type,
 691                              uint16_t queue_id)
 692 {
 693         struct hns3_vf_bind_vector_msg bind_msg;
 694         const char *op_str;
 695         uint16_t code;
 696         int ret;
 697
 698         memset(&bind_msg, 0, sizeof(bind_msg));
 699         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 700                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 701         bind_msg.vector_id = vector_id;
 702
 703         if (queue_type == HNS3_RING_TYPE_RX)
 704                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 705         else
 706                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 707
 708         bind_msg.param[0].ring_type = queue_type;
 709         bind_msg.ring_num = 1;
 710         bind_msg.param[0].tqp_index = queue_id;
 711         op_str = mmap ? "Map" : "Unmap";
 712         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 713                                 sizeof(bind_msg), false, NULL, 0);
 714         if (ret)
 715                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 716                          op_str, queue_id, bind_msg.vector_id, ret);
 717
 718         return ret;
 719 }
 720
 721 static int
 722 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 723 {
 724         uint16_t vec;
 725         int ret;
 726         int i;
 727
 728         /*
 729          * In hns3 network engine, vector 0 is always the misc interrupt of this
 730          * function, vector 1~N can be used respectively for the queues of the
 731          * function. Tx and Rx queues with the same number share the interrupt
 732          * vector. In the initialization clearing the all hardware mapping
 733          * relationship configurations between queues and interrupt vectors is
 734          * needed, so some error caused by the residual configurations, such as
 735          * the unexpected Tx interrupt, can be avoid.
 736          */
 737         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 738         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 739                 vec = vec - 1; /* the last interrupt is reserved */
 740         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 741         for (i = 0; i < hw->intr_tqps_num; i++) {
 742                 /*
 743                  * Set gap limiter/rate limiter/quanity limiter algorithm
 744                  * configuration for interrupt coalesce of queue's interrupt.
 745                  */
 746                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 747                                        HNS3_TQP_INTR_GL_DEFAULT);
 748                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 749                                        HNS3_TQP_INTR_GL_DEFAULT);
 750                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 751                 /*
 752                  * QL(quantity limiter) is not used currently, just set 0 to
 753                  * close it.
 754                  */
 755                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 756
 757                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 758                                                    HNS3_RING_TYPE_TX, i);
 759                 if (ret) {
 760                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 761                                           "vector: %u, ret=%d", i, vec, ret);
 762                         return ret;
 763                 }
 764
 765                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 766                                                    HNS3_RING_TYPE_RX, i);
 767                 if (ret) {
 768                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 769                                           "vector: %u, ret=%d", i, vec, ret);
 770                         return ret;
 771                 }
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int
 778 hns3vf_dev_configure(struct rte_eth_dev *dev)
 779 {
 780         struct hns3_adapter *hns = dev->data->dev_private;
 781         struct hns3_hw *hw = &hns->hw;
 782         struct rte_eth_conf *conf = &dev->data->dev_conf;
 783         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 784         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 785         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 786         struct rte_eth_rss_conf rss_conf;
 787         uint32_t max_rx_pkt_len;
 788         uint16_t mtu;
 789         bool gro_en;
 790         int ret;
 791
 792         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 793
 794         /*
 795          * Some versions of hardware network engine does not support
 796          * individually enable/disable/reset the Tx or Rx queue. These devices
 797          * must enable/disable/reset Tx and Rx queues at the same time. When the
 798          * numbers of Tx queues allocated by upper applications are not equal to
 799          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 800          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 801          * work as usual. But these fake queues are imperceptible, and can not
 802          * be used by upper applications.
 803          */
 804         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 805         if (ret) {
 806                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 807                 return ret;
 808         }
 809
 810         hw->adapter_state = HNS3_NIC_CONFIGURING;
 811         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 812                 hns3_err(hw, "setting link speed/duplex not supported");
 813                 ret = -EINVAL;
 814                 goto cfg_err;
 815         }
 816
 817         /* When RSS is not configured, redirect the packet queue 0 */
 818         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 819                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 820                 hw->rss_dis_flag = false;
 821                 rss_conf = conf->rx_adv_conf.rss_conf;
 822                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 823                 if (ret)
 824                         goto cfg_err;
 825         }
 826
 827         /*
 828          * If jumbo frames are enabled, MTU needs to be refreshed
 829          * according to the maximum RX packet length.
 830          */
 831         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 832                 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
 833                 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
 834                     max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
 835                         hns3_err(hw, "maximum Rx packet length must be greater "
 836                                  "than %u and less than %u when jumbo frame enabled.",
 837                                  (uint16_t)HNS3_DEFAULT_FRAME_LEN,
 838                                  (uint16_t)HNS3_MAX_FRAME_LEN);
 839                         ret = -EINVAL;
 840                         goto cfg_err;
 841                 }
 842
 843                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
 844                 ret = hns3vf_dev_mtu_set(dev, mtu);
 845                 if (ret)
 846                         goto cfg_err;
 847                 dev->data->mtu = mtu;
 848         }
 849
 850         ret = hns3vf_dev_configure_vlan(dev);
 851         if (ret)
 852                 goto cfg_err;
 853
 854         /* config hardware GRO */
 855         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 856         ret = hns3_config_gro(hw, gro_en);
 857         if (ret)
 858                 goto cfg_err;
 859
 860         hns3_init_rx_ptype_tble(dev);
 861
 862         hw->adapter_state = HNS3_NIC_CONFIGURED;
 863         return 0;
 864
 865 cfg_err:
 866         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 867         hw->adapter_state = HNS3_NIC_INITIALIZED;
 868
 869         return ret;
 870 }
 871
 872 static int
 873 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 874 {
 875         int ret;
 876
 877         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 878                                 sizeof(mtu), true, NULL, 0);
 879         if (ret)
 880                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 881
 882         return ret;
 883 }
 884
 885 static int
 886 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 887 {
 888         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 889         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 890         int ret;
 891
 892         /*
 893          * The hns3 PF/VF devices on the same port share the hardware MTU
 894          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 895          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 896          * driver, there is no need to stop the port for hns3 VF device, and the
 897          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 898          * PF's MTU.
 899          */
 900         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 901                 hns3_err(hw, "Failed to set mtu during resetting");
 902                 return -EIO;
 903         }
 904
 905         /*
 906          * when Rx of scattered packets is off, we have some possibility of
 907          * using vector Rx process function or simple Rx functions in hns3 PMD
 908          * driver. If the input MTU is increased and the maximum length of
 909          * received packets is greater than the length of a buffer for Rx
 910          * packet, the hardware network engine needs to use multiple BDs and
 911          * buffers to store these packets. This will cause problems when still
 912          * using vector Rx process function or simple Rx function to receiving
 913          * packets. So, when Rx of scattered packets is off and device is
 914          * started, it is not permitted to increase MTU so that the maximum
 915          * length of Rx packets is greater than Rx buffer length.
 916          */
 917         if (dev->data->dev_started && !dev->data->scattered_rx &&
 918             frame_size > hw->rx_buf_len) {
 919                 hns3_err(hw, "failed to set mtu because current is "
 920                         "not scattered rx mode");
 921                 return -EOPNOTSUPP;
 922         }
 923
 924         rte_spinlock_lock(&hw->lock);
 925         ret = hns3vf_config_mtu(hw, mtu);
 926         if (ret) {
 927                 rte_spinlock_unlock(&hw->lock);
 928                 return ret;
 929         }
 930         if (mtu > RTE_ETHER_MTU)
 931                 dev->data->dev_conf.rxmode.offloads |=
 932                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 933         else
 934                 dev->data->dev_conf.rxmode.offloads &=
 935                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 936         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 937         rte_spinlock_unlock(&hw->lock);
 938
 939         return 0;
 940 }
 941
 942 static int
 943 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 944 {
 945         struct hns3_adapter *hns = eth_dev->data->dev_private;
 946         struct hns3_hw *hw = &hns->hw;
 947         uint16_t q_num = hw->tqps_num;
 948
 949         /*
 950          * In interrupt mode, 'max_rx_queues' is set based on the number of
 951          * MSI-X interrupt resources of the hardware.
 952          */
 953         if (hw->data->dev_conf.intr_conf.rxq == 1)
 954                 q_num = hw->intr_tqps_num;
 955
 956         info->max_rx_queues = q_num;
 957         info->max_tx_queues = hw->tqps_num;
 958         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 959         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 960         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 961         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 962         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 963
 964         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 965                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 966                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 967                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 968                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 969                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 970                                  DEV_RX_OFFLOAD_SCATTER |
 971                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 972                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 973                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 974                                  DEV_RX_OFFLOAD_RSS_HASH |
 975                                  DEV_RX_OFFLOAD_TCP_LRO);
 976         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 977                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 978                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 979                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 980                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 981                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 982                                  DEV_TX_OFFLOAD_TCP_TSO |
 983                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 984                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 985                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 986                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 987                                  hns3_txvlan_cap_get(hw));
 988
 989         if (hns3_dev_outer_udp_cksum_supported(hw))
 990                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
 991
 992         if (hns3_dev_indep_txrx_supported(hw))
 993                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 994                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 995
 996         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 997                 .nb_max = HNS3_MAX_RING_DESC,
 998                 .nb_min = HNS3_MIN_RING_DESC,
 999                 .nb_align = HNS3_ALIGN_RING_DESC,
1000         };
1001
1002         info->tx_desc_lim = (struct rte_eth_desc_lim) {
1003                 .nb_max = HNS3_MAX_RING_DESC,
1004                 .nb_min = HNS3_MIN_RING_DESC,
1005                 .nb_align = HNS3_ALIGN_RING_DESC,
1006                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
1007                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1008         };
1009
1010         info->default_rxconf = (struct rte_eth_rxconf) {
1011                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1012                 /*
1013                  * If there are no available Rx buffer descriptors, incoming
1014                  * packets are always dropped by hardware based on hns3 network
1015                  * engine.
1016                  */
1017                 .rx_drop_en = 1,
1018                 .offloads = 0,
1019         };
1020         info->default_txconf = (struct rte_eth_txconf) {
1021                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1022                 .offloads = 0,
1023         };
1024
1025         info->reta_size = hw->rss_ind_tbl_size;
1026         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1027         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1028
1029         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1030         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1031         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1032         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1033         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1034         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1035
1036         return 0;
1037 }
1038
1039 static void
1040 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1041 {
1042         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1043 }
1044
1045 static void
1046 hns3vf_disable_irq0(struct hns3_hw *hw)
1047 {
1048         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1049 }
1050
1051 static void
1052 hns3vf_enable_irq0(struct hns3_hw *hw)
1053 {
1054         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1055 }
1056
1057 static enum hns3vf_evt_cause
1058 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1059 {
1060         struct hns3_hw *hw = &hns->hw;
1061         enum hns3vf_evt_cause ret;
1062         uint32_t cmdq_stat_reg;
1063         uint32_t rst_ing_reg;
1064         uint32_t val;
1065
1066         /* Fetch the events from their corresponding regs */
1067         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1068         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1069                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1070                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1071                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1072                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1073                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1074                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1075                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1076                 if (clearval) {
1077                         hw->reset.stats.global_cnt++;
1078                         hns3_warn(hw, "Global reset detected, clear reset status");
1079                 } else {
1080                         hns3_schedule_delayed_reset(hns);
1081                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1082                 }
1083
1084                 ret = HNS3VF_VECTOR0_EVENT_RST;
1085                 goto out;
1086         }
1087
1088         /* Check for vector0 mailbox(=CMDQ RX) event source */
1089         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1090                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1091                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1092                 goto out;
1093         }
1094
1095         val = 0;
1096         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1097 out:
1098         if (clearval)
1099                 *clearval = val;
1100         return ret;
1101 }
1102
1103 static void
1104 hns3vf_interrupt_handler(void *param)
1105 {
1106         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1107         struct hns3_adapter *hns = dev->data->dev_private;
1108         struct hns3_hw *hw = &hns->hw;
1109         enum hns3vf_evt_cause event_cause;
1110         uint32_t clearval;
1111
1112         /* Disable interrupt */
1113         hns3vf_disable_irq0(hw);
1114
1115         /* Read out interrupt causes */
1116         event_cause = hns3vf_check_event_cause(hns, &clearval);
1117
1118         switch (event_cause) {
1119         case HNS3VF_VECTOR0_EVENT_RST:
1120                 hns3_schedule_reset(hns);
1121                 break;
1122         case HNS3VF_VECTOR0_EVENT_MBX:
1123                 hns3_dev_handle_mbx_msg(hw);
1124                 break;
1125         default:
1126                 break;
1127         }
1128
1129         /* Clear interrupt causes */
1130         hns3vf_clear_event_cause(hw, clearval);
1131
1132         /* Enable interrupt */
1133         hns3vf_enable_irq0(hw);
1134 }
1135
1136 static void
1137 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1138 {
1139         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1140         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1141         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1142         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1143 }
1144
1145 static void
1146 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1147 {
1148         struct hns3_dev_specs_0_cmd *req0;
1149
1150         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1151
1152         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1153         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1154         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1155         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1156 }
1157
1158 static int
1159 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1160 {
1161         if (hw->rss_ind_tbl_size == 0 ||
1162             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1163                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1164                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1165                               HNS3_RSS_IND_TBL_SIZE_MAX);
1166                 return -EINVAL;
1167         }
1168
1169         return 0;
1170 }
1171
1172 static int
1173 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1174 {
1175         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1176         int ret;
1177         int i;
1178
1179         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1180                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1181                                           true);
1182                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1183         }
1184         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1185
1186         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1187         if (ret)
1188                 return ret;
1189
1190         hns3vf_parse_dev_specifications(hw, desc);
1191
1192         return hns3vf_check_dev_specifications(hw);
1193 }
1194
1195 void
1196 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1197 {
1198         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1199                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1200         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1201         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1202
1203         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1204                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1205                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1206 }
1207
1208 static void
1209 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1210 {
1211 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1212
1213         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1214         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1215         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1216         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1217         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1218
1219         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1220                          __ATOMIC_RELEASE);
1221
1222         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1223                                 NULL, 0);
1224
1225         while (remain_ms > 0) {
1226                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1227                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1228                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1229                         break;
1230                 remain_ms--;
1231         }
1232
1233         /*
1234          * When exit above loop, the pf_push_lsc_cap could be one of the three
1235          * state: unknown (means pf not ack), not_supported, supported.
1236          * Here config it as 'not_supported' when it's 'unknown' state.
1237          */
1238         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1239                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1240
1241         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1242                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1243                 hns3_info(hw, "detect PF support push link status change!");
1244         } else {
1245                 /*
1246                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1247                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1248                  * the RTE_ETH_DEV_INTR_LSC capability.
1249                  */
1250                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1251         }
1252 }
1253
1254 static int
1255 hns3vf_get_capability(struct hns3_hw *hw)
1256 {
1257         struct rte_pci_device *pci_dev;
1258         struct rte_eth_dev *eth_dev;
1259         uint8_t revision;
1260         int ret;
1261
1262         eth_dev = &rte_eth_devices[hw->data->port_id];
1263         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1264
1265         /* Get PCI revision id */
1266         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1267                                   HNS3_PCI_REVISION_ID);
1268         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1269                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1270                              ret);
1271                 return -EIO;
1272         }
1273         hw->revision = revision;
1274
1275         if (revision < PCI_REVISION_ID_HIP09_A) {
1276                 hns3vf_set_default_dev_specifications(hw);
1277                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1278                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1279                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1280                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1281                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1282                 hw->rss_info.ipv6_sctp_offload_supported = false;
1283                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1284                 return 0;
1285         }
1286
1287         ret = hns3vf_query_dev_specifications(hw);
1288         if (ret) {
1289                 PMD_INIT_LOG(ERR,
1290                              "failed to query dev specifications, ret = %d",
1291                              ret);
1292                 return ret;
1293         }
1294
1295         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1296         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1297         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1298         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1299         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1300         hw->rss_info.ipv6_sctp_offload_supported = true;
1301         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1302
1303         return 0;
1304 }
1305
1306 static int
1307 hns3vf_check_tqp_info(struct hns3_hw *hw)
1308 {
1309         if (hw->tqps_num == 0) {
1310                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1311                 return -EINVAL;
1312         }
1313
1314         if (hw->rss_size_max == 0) {
1315                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1316                 return -EINVAL;
1317         }
1318
1319         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1320
1321         return 0;
1322 }
1323
1324 static int
1325 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1326 {
1327         uint8_t resp_msg;
1328         int ret;
1329
1330         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1331                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1332                                 true, &resp_msg, sizeof(resp_msg));
1333         if (ret) {
1334                 if (ret == -ETIME) {
1335                         /*
1336                          * Getting current port based VLAN state from PF driver
1337                          * will not affect VF driver's basic function. Because
1338                          * the VF driver relies on hns3 PF kernel ether driver,
1339                          * to avoid introducing compatibility issues with older
1340                          * version of PF driver, no failure will be returned
1341                          * when the return value is ETIME. This return value has
1342                          * the following scenarios:
1343                          * 1) Firmware didn't return the results in time
1344                          * 2) the result return by firmware is timeout
1345                          * 3) the older version of kernel side PF driver does
1346                          *    not support this mailbox message.
1347                          * For scenarios 1 and 2, it is most likely that a
1348                          * hardware error has occurred, or a hardware reset has
1349                          * occurred. In this case, these errors will be caught
1350                          * by other functions.
1351                          */
1352                         PMD_INIT_LOG(WARNING,
1353                                 "failed to get PVID state for timeout, maybe "
1354                                 "kernel side PF driver doesn't support this "
1355                                 "mailbox message, or firmware didn't respond.");
1356                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1357                 } else {
1358                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1359                                 " ret = %d", ret);
1360                         return ret;
1361                 }
1362         }
1363         hw->port_base_vlan_cfg.state = resp_msg ?
1364                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1365         return 0;
1366 }
1367
1368 static int
1369 hns3vf_get_queue_info(struct hns3_hw *hw)
1370 {
1371 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1372         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1373         int ret;
1374
1375         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1376                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1377         if (ret) {
1378                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1379                 return ret;
1380         }
1381
1382         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1383         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1384
1385         return hns3vf_check_tqp_info(hw);
1386 }
1387
1388 static int
1389 hns3vf_get_queue_depth(struct hns3_hw *hw)
1390 {
1391 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1392         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1393         int ret;
1394
1395         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1396                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1397         if (ret) {
1398                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1399                              ret);
1400                 return ret;
1401         }
1402
1403         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1404         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1405
1406         return 0;
1407 }
1408
1409 static int
1410 hns3vf_get_tc_info(struct hns3_hw *hw)
1411 {
1412         uint8_t resp_msg;
1413         int ret;
1414         uint32_t i;
1415
1416         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1417                                 true, &resp_msg, sizeof(resp_msg));
1418         if (ret) {
1419                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1420                          ret);
1421                 return ret;
1422         }
1423
1424         hw->hw_tc_map = resp_msg;
1425
1426         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1427                 if (hw->hw_tc_map & BIT(i))
1428                         hw->num_tc++;
1429         }
1430
1431         return 0;
1432 }
1433
1434 static int
1435 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1436 {
1437         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1438         int ret;
1439
1440         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1441                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1442         if (ret) {
1443                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1444                 return ret;
1445         }
1446
1447         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1448
1449         return 0;
1450 }
1451
1452 static int
1453 hns3vf_get_configuration(struct hns3_hw *hw)
1454 {
1455         int ret;
1456
1457         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1458         hw->rss_dis_flag = false;
1459
1460         /* Get device capability */
1461         ret = hns3vf_get_capability(hw);
1462         if (ret) {
1463                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1464                 return ret;
1465         }
1466
1467         hns3vf_get_push_lsc_cap(hw);
1468
1469         /* Get queue configuration from PF */
1470         ret = hns3vf_get_queue_info(hw);
1471         if (ret)
1472                 return ret;
1473
1474         /* Get queue depth info from PF */
1475         ret = hns3vf_get_queue_depth(hw);
1476         if (ret)
1477                 return ret;
1478
1479         /* Get user defined VF MAC addr from PF */
1480         ret = hns3vf_get_host_mac_addr(hw);
1481         if (ret)
1482                 return ret;
1483
1484         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1485         if (ret)
1486                 return ret;
1487
1488         /* Get tc configuration from PF */
1489         return hns3vf_get_tc_info(hw);
1490 }
1491
1492 static int
1493 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1494                             uint16_t nb_tx_q)
1495 {
1496         struct hns3_hw *hw = &hns->hw;
1497
1498         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1499 }
1500
1501 static void
1502 hns3vf_request_link_info(struct hns3_hw *hw)
1503 {
1504         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1505         bool send_req;
1506         int ret;
1507
1508         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1509                 return;
1510
1511         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1512                    vf->req_link_info_cnt > 0;
1513         if (!send_req)
1514                 return;
1515
1516         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1517                                 NULL, 0);
1518         if (ret) {
1519                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1520                 return;
1521         }
1522
1523         if (vf->req_link_info_cnt > 0)
1524                 vf->req_link_info_cnt--;
1525 }
1526
1527 void
1528 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1529                           uint32_t link_speed, uint8_t link_duplex)
1530 {
1531         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1532         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1533         struct hns3_mac *mac = &hw->mac;
1534         int ret;
1535
1536         /*
1537          * PF kernel driver may push link status when VF driver is in resetting,
1538          * driver will stop polling job in this case, after resetting done
1539          * driver will start polling job again.
1540          * When polling job started, driver will get initial link status by
1541          * sending request to PF kernel driver, then could update link status by
1542          * process PF kernel driver's link status mailbox message.
1543          */
1544         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1545                 return;
1546
1547         if (hw->adapter_state != HNS3_NIC_STARTED)
1548                 return;
1549
1550         mac->link_status = link_status;
1551         mac->link_speed = link_speed;
1552         mac->link_duplex = link_duplex;
1553         ret = hns3vf_dev_link_update(dev, 0);
1554         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1555                 hns3_start_report_lse(dev);
1556 }
1557
1558 static int
1559 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1560 {
1561 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1562         struct hns3_hw *hw = &hns->hw;
1563         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1564         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1565         uint8_t is_kill = on ? 0 : 1;
1566
1567         msg_data[0] = is_kill;
1568         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1569         memcpy(&msg_data[3], &proto, sizeof(proto));
1570
1571         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1572                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1573                                  0);
1574 }
1575
1576 static int
1577 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1578 {
1579         struct hns3_adapter *hns = dev->data->dev_private;
1580         struct hns3_hw *hw = &hns->hw;
1581         int ret;
1582
1583         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1584                 hns3_err(hw,
1585                          "vf set vlan id failed during resetting, vlan_id =%u",
1586                          vlan_id);
1587                 return -EIO;
1588         }
1589         rte_spinlock_lock(&hw->lock);
1590         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1591         rte_spinlock_unlock(&hw->lock);
1592         if (ret)
1593                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1594                          vlan_id, ret);
1595
1596         return ret;
1597 }
1598
1599 static int
1600 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1601 {
1602         uint8_t msg_data;
1603         int ret;
1604
1605         msg_data = enable ? 1 : 0;
1606         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1607                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1608         if (ret)
1609                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1610                                 enable ? "enable" : "disable", ret);
1611
1612         return ret;
1613 }
1614
1615 static int
1616 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1617 {
1618         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1620         unsigned int tmp_mask;
1621         int ret = 0;
1622
1623         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1624                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1625                              "mask = 0x%x", mask);
1626                 return -EIO;
1627         }
1628
1629         tmp_mask = (unsigned int)mask;
1630         /* Vlan stripping setting */
1631         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1632                 rte_spinlock_lock(&hw->lock);
1633                 /* Enable or disable VLAN stripping */
1634                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1635                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1636                 else
1637                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1638                 rte_spinlock_unlock(&hw->lock);
1639         }
1640
1641         return ret;
1642 }
1643
1644 static int
1645 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1646 {
1647         struct rte_vlan_filter_conf *vfc;
1648         struct hns3_hw *hw = &hns->hw;
1649         uint16_t vlan_id;
1650         uint64_t vbit;
1651         uint64_t ids;
1652         int ret = 0;
1653         uint32_t i;
1654
1655         vfc = &hw->data->vlan_filter_conf;
1656         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1657                 if (vfc->ids[i] == 0)
1658                         continue;
1659                 ids = vfc->ids[i];
1660                 while (ids) {
1661                         /*
1662                          * 64 means the num bits of ids, one bit corresponds to
1663                          * one vlan id
1664                          */
1665                         vlan_id = 64 * i;
1666                         /* count trailing zeroes */
1667                         vbit = ~ids & (ids - 1);
1668                         /* clear least significant bit set */
1669                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1670                         for (; vbit;) {
1671                                 vbit >>= 1;
1672                                 vlan_id++;
1673                         }
1674                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1675                         if (ret) {
1676                                 hns3_err(hw,
1677                                          "VF handle vlan table failed, ret =%d, on = %d",
1678                                          ret, on);
1679                                 return ret;
1680                         }
1681                 }
1682         }
1683
1684         return ret;
1685 }
1686
1687 static int
1688 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1689 {
1690         return hns3vf_handle_all_vlan_table(hns, 0);
1691 }
1692
1693 static int
1694 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1695 {
1696         struct hns3_hw *hw = &hns->hw;
1697         struct rte_eth_conf *dev_conf;
1698         bool en;
1699         int ret;
1700
1701         dev_conf = &hw->data->dev_conf;
1702         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1703                                                                    : false;
1704         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1705         if (ret)
1706                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1707                          ret);
1708         return ret;
1709 }
1710
1711 static int
1712 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1713 {
1714         struct hns3_adapter *hns = dev->data->dev_private;
1715         struct rte_eth_dev_data *data = dev->data;
1716         struct hns3_hw *hw = &hns->hw;
1717         int ret;
1718
1719         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1720             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1721             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1722                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1723                               "or hw_vlan_insert_pvid is not support!");
1724         }
1725
1726         /* Apply vlan offload setting */
1727         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1728         if (ret)
1729                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1730
1731         return ret;
1732 }
1733
1734 static int
1735 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1736 {
1737         uint8_t msg_data;
1738
1739         msg_data = alive ? 1 : 0;
1740         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1741                                  sizeof(msg_data), false, NULL, 0);
1742 }
1743
1744 static void
1745 hns3vf_keep_alive_handler(void *param)
1746 {
1747         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1748         struct hns3_adapter *hns = eth_dev->data->dev_private;
1749         struct hns3_hw *hw = &hns->hw;
1750         int ret;
1751
1752         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1753                                 false, NULL, 0);
1754         if (ret)
1755                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1756                          ret);
1757
1758         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1759                           eth_dev);
1760 }
1761
1762 static void
1763 hns3vf_service_handler(void *param)
1764 {
1765         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1766         struct hns3_adapter *hns = eth_dev->data->dev_private;
1767         struct hns3_hw *hw = &hns->hw;
1768
1769         /*
1770          * The query link status and reset processing are executed in the
1771          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1772          * and the query operation will timeout after 30ms. In the case of
1773          * multiple PF/VFs, each query failure timeout causes the IMP reset
1774          * interrupt to fail to respond within 100ms.
1775          * Before querying the link status, check whether there is a reset
1776          * pending, and if so, abandon the query.
1777          */
1778         if (!hns3vf_is_reset_pending(hns))
1779                 hns3vf_request_link_info(hw);
1780         else
1781                 hns3_warn(hw, "Cancel the query when reset is pending");
1782
1783         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1784                           eth_dev);
1785 }
1786
1787 static void
1788 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1789 {
1790 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1791
1792         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1793
1794         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1795                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1796
1797         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1798
1799         hns3vf_service_handler(dev);
1800 }
1801
1802 static void
1803 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1804 {
1805         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1806
1807         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1808
1809         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1810 }
1811
1812 static int
1813 hns3_query_vf_resource(struct hns3_hw *hw)
1814 {
1815         struct hns3_vf_res_cmd *req;
1816         struct hns3_cmd_desc desc;
1817         uint16_t num_msi;
1818         int ret;
1819
1820         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1821         ret = hns3_cmd_send(hw, &desc, 1);
1822         if (ret) {
1823                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1824                 return ret;
1825         }
1826
1827         req = (struct hns3_vf_res_cmd *)desc.data;
1828         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1829                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1830         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1831                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1832                          num_msi, HNS3_MIN_VECTOR_NUM);
1833                 return -EINVAL;
1834         }
1835
1836         hw->num_msi = num_msi;
1837
1838         return 0;
1839 }
1840
1841 static int
1842 hns3vf_init_hardware(struct hns3_adapter *hns)
1843 {
1844         struct hns3_hw *hw = &hns->hw;
1845         uint16_t mtu = hw->data->mtu;
1846         int ret;
1847
1848         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1849         if (ret)
1850                 return ret;
1851
1852         ret = hns3vf_config_mtu(hw, mtu);
1853         if (ret)
1854                 goto err_init_hardware;
1855
1856         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1857         if (ret) {
1858                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1859                 goto err_init_hardware;
1860         }
1861
1862         ret = hns3_config_gro(hw, false);
1863         if (ret) {
1864                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1865                 goto err_init_hardware;
1866         }
1867
1868         /*
1869          * In the initialization clearing the all hardware mapping relationship
1870          * configurations between queues and interrupt vectors is needed, so
1871          * some error caused by the residual configurations, such as the
1872          * unexpected interrupt, can be avoid.
1873          */
1874         ret = hns3vf_init_ring_with_vector(hw);
1875         if (ret) {
1876                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1877                 goto err_init_hardware;
1878         }
1879
1880         return 0;
1881
1882 err_init_hardware:
1883         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1884         return ret;
1885 }
1886
1887 static int
1888 hns3vf_clear_vport_list(struct hns3_hw *hw)
1889 {
1890         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1891                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1892                                  NULL, 0);
1893 }
1894
1895 static int
1896 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1897 {
1898         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1899         struct hns3_adapter *hns = eth_dev->data->dev_private;
1900         struct hns3_hw *hw = &hns->hw;
1901         int ret;
1902
1903         PMD_INIT_FUNC_TRACE();
1904
1905         /* Get hardware io base address from pcie BAR2 IO space */
1906         hw->io_base = pci_dev->mem_resource[2].addr;
1907
1908         /* Firmware command queue initialize */
1909         ret = hns3_cmd_init_queue(hw);
1910         if (ret) {
1911                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1912                 goto err_cmd_init_queue;
1913         }
1914
1915         /* Firmware command initialize */
1916         ret = hns3_cmd_init(hw);
1917         if (ret) {
1918                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1919                 goto err_cmd_init;
1920         }
1921
1922         /* Get VF resource */
1923         ret = hns3_query_vf_resource(hw);
1924         if (ret)
1925                 goto err_cmd_init;
1926
1927         rte_spinlock_init(&hw->mbx_resp.lock);
1928
1929         hns3vf_clear_event_cause(hw, 0);
1930
1931         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1932                                          hns3vf_interrupt_handler, eth_dev);
1933         if (ret) {
1934                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1935                 goto err_intr_callback_register;
1936         }
1937
1938         /* Enable interrupt */
1939         rte_intr_enable(&pci_dev->intr_handle);
1940         hns3vf_enable_irq0(hw);
1941
1942         /* Get configuration from PF */
1943         ret = hns3vf_get_configuration(hw);
1944         if (ret) {
1945                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1946                 goto err_get_config;
1947         }
1948
1949         ret = hns3_tqp_stats_init(hw);
1950         if (ret)
1951                 goto err_get_config;
1952
1953         /* Hardware statistics of imissed registers cleared. */
1954         ret = hns3_update_imissed_stats(hw, true);
1955         if (ret) {
1956                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1957                 goto err_set_tc_queue;
1958         }
1959
1960         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1961         if (ret) {
1962                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1963                 goto err_set_tc_queue;
1964         }
1965
1966         ret = hns3vf_clear_vport_list(hw);
1967         if (ret) {
1968                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1969                 goto err_set_tc_queue;
1970         }
1971
1972         ret = hns3vf_init_hardware(hns);
1973         if (ret)
1974                 goto err_set_tc_queue;
1975
1976         hns3_rss_set_default_args(hw);
1977
1978         ret = hns3vf_set_alive(hw, true);
1979         if (ret) {
1980                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1981                 goto err_set_tc_queue;
1982         }
1983
1984         return 0;
1985
1986 err_set_tc_queue:
1987         hns3_tqp_stats_uninit(hw);
1988
1989 err_get_config:
1990         hns3vf_disable_irq0(hw);
1991         rte_intr_disable(&pci_dev->intr_handle);
1992         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1993                              eth_dev);
1994 err_intr_callback_register:
1995 err_cmd_init:
1996         hns3_cmd_uninit(hw);
1997         hns3_cmd_destroy_queue(hw);
1998 err_cmd_init_queue:
1999         hw->io_base = NULL;
2000
2001         return ret;
2002 }
2003
2004 static void
2005 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2006 {
2007         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2008         struct hns3_adapter *hns = eth_dev->data->dev_private;
2009         struct hns3_hw *hw = &hns->hw;
2010
2011         PMD_INIT_FUNC_TRACE();
2012
2013         hns3_rss_uninit(hns);
2014         (void)hns3_config_gro(hw, false);
2015         (void)hns3vf_set_alive(hw, false);
2016         (void)hns3vf_set_promisc_mode(hw, false, false, false);
2017         hns3_tqp_stats_uninit(hw);
2018         hns3vf_disable_irq0(hw);
2019         rte_intr_disable(&pci_dev->intr_handle);
2020         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2021                              eth_dev);
2022         hns3_cmd_uninit(hw);
2023         hns3_cmd_destroy_queue(hw);
2024         hw->io_base = NULL;
2025 }
2026
2027 static int
2028 hns3vf_do_stop(struct hns3_adapter *hns)
2029 {
2030         struct hns3_hw *hw = &hns->hw;
2031         int ret;
2032
2033         hw->mac.link_status = ETH_LINK_DOWN;
2034
2035         /*
2036          * The "hns3vf_do_stop" function will also be called by .stop_service to
2037          * prepare reset. At the time of global or IMP reset, the command cannot
2038          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2039          * accessed during the reset process. So the mbuf can not be released
2040          * during reset and is required to be released after the reset is
2041          * completed.
2042          */
2043         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
2044                 hns3_dev_release_mbufs(hns);
2045
2046         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2047                 hns3vf_configure_mac_addr(hns, true);
2048                 ret = hns3_reset_all_tqps(hns);
2049                 if (ret) {
2050                         hns3_err(hw, "failed to reset all queues ret = %d",
2051                                  ret);
2052                         return ret;
2053                 }
2054         }
2055         return 0;
2056 }
2057
2058 static void
2059 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2060 {
2061         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2063         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2064         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2065         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2066         uint16_t q_id;
2067
2068         if (dev->data->dev_conf.intr_conf.rxq == 0)
2069                 return;
2070
2071         /* unmap the ring with vector */
2072         if (rte_intr_allow_others(intr_handle)) {
2073                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2074                 base = RTE_INTR_VEC_RXTX_OFFSET;
2075         }
2076         if (rte_intr_dp_is_en(intr_handle)) {
2077                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2078                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2079                                                            HNS3_RING_TYPE_RX,
2080                                                            q_id);
2081                         if (vec < base + intr_handle->nb_efd - 1)
2082                                 vec++;
2083                 }
2084         }
2085         /* Clean datapath event and queue/vec mapping */
2086         rte_intr_efd_disable(intr_handle);
2087         if (intr_handle->intr_vec) {
2088                 rte_free(intr_handle->intr_vec);
2089                 intr_handle->intr_vec = NULL;
2090         }
2091 }
2092
2093 static int
2094 hns3vf_dev_stop(struct rte_eth_dev *dev)
2095 {
2096         struct hns3_adapter *hns = dev->data->dev_private;
2097         struct hns3_hw *hw = &hns->hw;
2098
2099         PMD_INIT_FUNC_TRACE();
2100         dev->data->dev_started = 0;
2101
2102         hw->adapter_state = HNS3_NIC_STOPPING;
2103         hns3_set_rxtx_function(dev);
2104         rte_wmb();
2105         /* Disable datapath on secondary process. */
2106         hns3_mp_req_stop_rxtx(dev);
2107         /* Prevent crashes when queues are still in use. */
2108         rte_delay_ms(hw->cfg_max_queues);
2109
2110         rte_spinlock_lock(&hw->lock);
2111         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2112                 hns3_stop_tqps(hw);
2113                 hns3vf_do_stop(hns);
2114                 hns3vf_unmap_rx_interrupt(dev);
2115                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2116         }
2117         hns3_rx_scattered_reset(dev);
2118         hns3vf_stop_poll_job(dev);
2119         hns3_stop_report_lse(dev);
2120         rte_spinlock_unlock(&hw->lock);
2121
2122         return 0;
2123 }
2124
2125 static int
2126 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2127 {
2128         struct hns3_adapter *hns = eth_dev->data->dev_private;
2129         struct hns3_hw *hw = &hns->hw;
2130         int ret = 0;
2131
2132         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2133                 rte_free(eth_dev->process_private);
2134                 eth_dev->process_private = NULL;
2135                 return 0;
2136         }
2137
2138         if (hw->adapter_state == HNS3_NIC_STARTED)
2139                 ret = hns3vf_dev_stop(eth_dev);
2140
2141         hw->adapter_state = HNS3_NIC_CLOSING;
2142         hns3_reset_abort(hns);
2143         hw->adapter_state = HNS3_NIC_CLOSED;
2144         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2145         hns3vf_configure_all_mc_mac_addr(hns, true);
2146         hns3vf_remove_all_vlan_table(hns);
2147         hns3vf_uninit_vf(eth_dev);
2148         hns3_free_all_queues(eth_dev);
2149         rte_free(hw->reset.wait_data);
2150         rte_free(eth_dev->process_private);
2151         eth_dev->process_private = NULL;
2152         hns3_mp_uninit_primary();
2153         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2154
2155         return ret;
2156 }
2157
2158 static int
2159 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2160                       size_t fw_size)
2161 {
2162         struct hns3_adapter *hns = eth_dev->data->dev_private;
2163         struct hns3_hw *hw = &hns->hw;
2164         uint32_t version = hw->fw_version;
2165         int ret;
2166
2167         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2168                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2169                                       HNS3_FW_VERSION_BYTE3_S),
2170                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2171                                       HNS3_FW_VERSION_BYTE2_S),
2172                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2173                                       HNS3_FW_VERSION_BYTE1_S),
2174                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2175                                       HNS3_FW_VERSION_BYTE0_S));
2176         if (ret < 0)
2177                 return -EINVAL;
2178
2179         ret += 1; /* add the size of '\0' */
2180         if (fw_size < (size_t)ret)
2181                 return ret;
2182         else
2183                 return 0;
2184 }
2185
2186 static int
2187 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2188                        __rte_unused int wait_to_complete)
2189 {
2190         struct hns3_adapter *hns = eth_dev->data->dev_private;
2191         struct hns3_hw *hw = &hns->hw;
2192         struct hns3_mac *mac = &hw->mac;
2193         struct rte_eth_link new_link;
2194
2195         memset(&new_link, 0, sizeof(new_link));
2196         switch (mac->link_speed) {
2197         case ETH_SPEED_NUM_10M:
2198         case ETH_SPEED_NUM_100M:
2199         case ETH_SPEED_NUM_1G:
2200         case ETH_SPEED_NUM_10G:
2201         case ETH_SPEED_NUM_25G:
2202         case ETH_SPEED_NUM_40G:
2203         case ETH_SPEED_NUM_50G:
2204         case ETH_SPEED_NUM_100G:
2205         case ETH_SPEED_NUM_200G:
2206                 if (mac->link_status)
2207                         new_link.link_speed = mac->link_speed;
2208                 break;
2209         default:
2210                 if (mac->link_status)
2211                         new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2212                 break;
2213         }
2214
2215         if (!mac->link_status)
2216                 new_link.link_speed = ETH_SPEED_NUM_NONE;
2217
2218         new_link.link_duplex = mac->link_duplex;
2219         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2220         new_link.link_autoneg =
2221             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2222
2223         return rte_eth_linkstatus_set(eth_dev, &new_link);
2224 }
2225
2226 static int
2227 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2228 {
2229         struct hns3_hw *hw = &hns->hw;
2230         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2231         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2232         int ret;
2233
2234         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2235         if (ret)
2236                 return ret;
2237
2238         hns3_enable_rxd_adv_layout(hw);
2239
2240         ret = hns3_init_queues(hns, reset_queue);
2241         if (ret)
2242                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2243
2244         return ret;
2245 }
2246
2247 static int
2248 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2249 {
2250         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2251         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2252         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2254         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2255         uint32_t intr_vector;
2256         uint16_t q_id;
2257         int ret;
2258
2259         /*
2260          * hns3 needs a separate interrupt to be used as event interrupt which
2261          * could not be shared with task queue pair, so KERNEL drivers need
2262          * support multiple interrupt vectors.
2263          */
2264         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2265             !rte_intr_cap_multiple(intr_handle))
2266                 return 0;
2267
2268         rte_intr_disable(intr_handle);
2269         intr_vector = hw->used_rx_queues;
2270         /* It creates event fd for each intr vector when MSIX is used */
2271         if (rte_intr_efd_enable(intr_handle, intr_vector))
2272                 return -EINVAL;
2273
2274         if (intr_handle->intr_vec == NULL) {
2275                 intr_handle->intr_vec =
2276                         rte_zmalloc("intr_vec",
2277                                     hw->used_rx_queues * sizeof(int), 0);
2278                 if (intr_handle->intr_vec == NULL) {
2279                         hns3_err(hw, "Failed to allocate %u rx_queues"
2280                                      " intr_vec", hw->used_rx_queues);
2281                         ret = -ENOMEM;
2282                         goto vf_alloc_intr_vec_error;
2283                 }
2284         }
2285
2286         if (rte_intr_allow_others(intr_handle)) {
2287                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2288                 base = RTE_INTR_VEC_RXTX_OFFSET;
2289         }
2290
2291         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2292                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2293                                                    HNS3_RING_TYPE_RX, q_id);
2294                 if (ret)
2295                         goto vf_bind_vector_error;
2296                 intr_handle->intr_vec[q_id] = vec;
2297                 /*
2298                  * If there are not enough efds (e.g. not enough interrupt),
2299                  * remaining queues will be bond to the last interrupt.
2300                  */
2301                 if (vec < base + intr_handle->nb_efd - 1)
2302                         vec++;
2303         }
2304         rte_intr_enable(intr_handle);
2305         return 0;
2306
2307 vf_bind_vector_error:
2308         free(intr_handle->intr_vec);
2309         intr_handle->intr_vec = NULL;
2310 vf_alloc_intr_vec_error:
2311         rte_intr_efd_disable(intr_handle);
2312         return ret;
2313 }
2314
2315 static int
2316 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2317 {
2318         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2319         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2320         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2321         uint16_t q_id;
2322         int ret;
2323
2324         if (dev->data->dev_conf.intr_conf.rxq == 0)
2325                 return 0;
2326
2327         if (rte_intr_dp_is_en(intr_handle)) {
2328                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2329                         ret = hns3vf_bind_ring_with_vector(hw,
2330                                         intr_handle->intr_vec[q_id], true,
2331                                         HNS3_RING_TYPE_RX, q_id);
2332                         if (ret)
2333                                 return ret;
2334                 }
2335         }
2336
2337         return 0;
2338 }
2339
2340 static void
2341 hns3vf_restore_filter(struct rte_eth_dev *dev)
2342 {
2343         hns3_restore_rss_filter(dev);
2344 }
2345
2346 static int
2347 hns3vf_dev_start(struct rte_eth_dev *dev)
2348 {
2349         struct hns3_adapter *hns = dev->data->dev_private;
2350         struct hns3_hw *hw = &hns->hw;
2351         int ret;
2352
2353         PMD_INIT_FUNC_TRACE();
2354         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2355                 return -EBUSY;
2356
2357         rte_spinlock_lock(&hw->lock);
2358         hw->adapter_state = HNS3_NIC_STARTING;
2359         ret = hns3vf_do_start(hns, true);
2360         if (ret) {
2361                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2362                 rte_spinlock_unlock(&hw->lock);
2363                 return ret;
2364         }
2365         ret = hns3vf_map_rx_interrupt(dev);
2366         if (ret)
2367                 goto map_rx_inter_err;
2368
2369         /*
2370          * There are three register used to control the status of a TQP
2371          * (contains a pair of Tx queue and Rx queue) in the new version network
2372          * engine. One is used to control the enabling of Tx queue, the other is
2373          * used to control the enabling of Rx queue, and the last is the master
2374          * switch used to control the enabling of the tqp. The Tx register and
2375          * TQP register must be enabled at the same time to enable a Tx queue.
2376          * The same applies to the Rx queue. For the older network enginem, this
2377          * function only refresh the enabled flag, and it is used to update the
2378          * status of queue in the dpdk framework.
2379          */
2380         ret = hns3_start_all_txqs(dev);
2381         if (ret)
2382                 goto map_rx_inter_err;
2383
2384         ret = hns3_start_all_rxqs(dev);
2385         if (ret)
2386                 goto start_all_rxqs_fail;
2387
2388         hw->adapter_state = HNS3_NIC_STARTED;
2389         rte_spinlock_unlock(&hw->lock);
2390
2391         hns3_rx_scattered_calc(dev);
2392         hns3_set_rxtx_function(dev);
2393         hns3_mp_req_start_rxtx(dev);
2394
2395         hns3vf_restore_filter(dev);
2396
2397         /* Enable interrupt of all rx queues before enabling queues */
2398         hns3_dev_all_rx_queue_intr_enable(hw, true);
2399         hns3_start_tqps(hw);
2400
2401         if (dev->data->dev_conf.intr_conf.lsc != 0)
2402                 hns3vf_dev_link_update(dev, 0);
2403         hns3vf_start_poll_job(dev);
2404
2405         return ret;
2406
2407 start_all_rxqs_fail:
2408         hns3_stop_all_txqs(dev);
2409 map_rx_inter_err:
2410         (void)hns3vf_do_stop(hns);
2411         hw->adapter_state = HNS3_NIC_CONFIGURED;
2412         rte_spinlock_unlock(&hw->lock);
2413
2414         return ret;
2415 }
2416
2417 static bool
2418 is_vf_reset_done(struct hns3_hw *hw)
2419 {
2420 #define HNS3_FUN_RST_ING_BITS \
2421         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2422          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2423          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2424          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2425
2426         uint32_t val;
2427
2428         if (hw->reset.level == HNS3_VF_RESET) {
2429                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2430                 if (val & HNS3_VF_RST_ING_BIT)
2431                         return false;
2432         } else {
2433                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2434                 if (val & HNS3_FUN_RST_ING_BITS)
2435                         return false;
2436         }
2437         return true;
2438 }
2439
2440 bool
2441 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2442 {
2443         struct hns3_hw *hw = &hns->hw;
2444         enum hns3_reset_level reset;
2445
2446         /*
2447          * According to the protocol of PCIe, FLR to a PF device resets the PF
2448          * state as well as the SR-IOV extended capability including VF Enable
2449          * which means that VFs no longer exist.
2450          *
2451          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2452          * is in FLR stage, the register state of VF device is not reliable,
2453          * so register states detection can not be carried out. In this case,
2454          * we just ignore the register states and return false to indicate that
2455          * there are no other reset states that need to be processed by driver.
2456          */
2457         if (hw->reset.level == HNS3_VF_FULL_RESET)
2458                 return false;
2459
2460         /* Check the registers to confirm whether there is reset pending */
2461         hns3vf_check_event_cause(hns, NULL);
2462         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2463         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2464             hw->reset.level < reset) {
2465                 hns3_warn(hw, "High level reset %d is pending", reset);
2466                 return true;
2467         }
2468         return false;
2469 }
2470
2471 static int
2472 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2473 {
2474         struct hns3_hw *hw = &hns->hw;
2475         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2476         struct timeval tv;
2477
2478         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2479                 /*
2480                  * After vf reset is ready, the PF may not have completed
2481                  * the reset processing. The vf sending mbox to PF may fail
2482                  * during the pf reset, so it is better to add extra delay.
2483                  */
2484                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2485                     hw->reset.level == HNS3_FLR_RESET)
2486                         return 0;
2487                 /* Reset retry process, no need to add extra delay. */
2488                 if (hw->reset.attempts)
2489                         return 0;
2490                 if (wait_data->check_completion == NULL)
2491                         return 0;
2492
2493                 wait_data->check_completion = NULL;
2494                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2495                 wait_data->count = 1;
2496                 wait_data->result = HNS3_WAIT_REQUEST;
2497                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2498                                   wait_data);
2499                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2500                 return -EAGAIN;
2501         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2502                 hns3_clock_gettime(&tv);
2503                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2504                           tv.tv_sec, tv.tv_usec);
2505                 return -ETIME;
2506         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2507                 return -EAGAIN;
2508
2509         wait_data->hns = hns;
2510         wait_data->check_completion = is_vf_reset_done;
2511         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2512                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2513         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2514         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2515         wait_data->result = HNS3_WAIT_REQUEST;
2516         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2517         return -EAGAIN;
2518 }
2519
2520 static int
2521 hns3vf_prepare_reset(struct hns3_adapter *hns)
2522 {
2523         struct hns3_hw *hw = &hns->hw;
2524         int ret;
2525
2526         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2527                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2528                                         0, true, NULL, 0);
2529                 if (ret)
2530                         return ret;
2531         }
2532         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2533
2534         return 0;
2535 }
2536
2537 static int
2538 hns3vf_stop_service(struct hns3_adapter *hns)
2539 {
2540         struct hns3_hw *hw = &hns->hw;
2541         struct rte_eth_dev *eth_dev;
2542
2543         eth_dev = &rte_eth_devices[hw->data->port_id];
2544         if (hw->adapter_state == HNS3_NIC_STARTED) {
2545                 /*
2546                  * Make sure call update link status before hns3vf_stop_poll_job
2547                  * because update link status depend on polling job exist.
2548                  */
2549                 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed,
2550                                           hw->mac.link_duplex);
2551                 hns3vf_stop_poll_job(eth_dev);
2552         }
2553         hw->mac.link_status = ETH_LINK_DOWN;
2554
2555         hns3_set_rxtx_function(eth_dev);
2556         rte_wmb();
2557         /* Disable datapath on secondary process. */
2558         hns3_mp_req_stop_rxtx(eth_dev);
2559         rte_delay_ms(hw->cfg_max_queues);
2560
2561         rte_spinlock_lock(&hw->lock);
2562         if (hw->adapter_state == HNS3_NIC_STARTED ||
2563             hw->adapter_state == HNS3_NIC_STOPPING) {
2564                 hns3_enable_all_queues(hw, false);
2565                 hns3vf_do_stop(hns);
2566                 hw->reset.mbuf_deferred_free = true;
2567         } else
2568                 hw->reset.mbuf_deferred_free = false;
2569
2570         /*
2571          * It is cumbersome for hardware to pick-and-choose entries for deletion
2572          * from table space. Hence, for function reset software intervention is
2573          * required to delete the entries.
2574          */
2575         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2576                 hns3vf_configure_all_mc_mac_addr(hns, true);
2577         rte_spinlock_unlock(&hw->lock);
2578
2579         return 0;
2580 }
2581
2582 static int
2583 hns3vf_start_service(struct hns3_adapter *hns)
2584 {
2585         struct hns3_hw *hw = &hns->hw;
2586         struct rte_eth_dev *eth_dev;
2587
2588         eth_dev = &rte_eth_devices[hw->data->port_id];
2589         hns3_set_rxtx_function(eth_dev);
2590         hns3_mp_req_start_rxtx(eth_dev);
2591         if (hw->adapter_state == HNS3_NIC_STARTED) {
2592                 hns3vf_start_poll_job(eth_dev);
2593
2594                 /* Enable interrupt of all rx queues before enabling queues */
2595                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2596                 /*
2597                  * Enable state of each rxq and txq will be recovered after
2598                  * reset, so we need to restore them before enable all tqps;
2599                  */
2600                 hns3_restore_tqp_enable_state(hw);
2601                 /*
2602                  * When finished the initialization, enable queues to receive
2603                  * and transmit packets.
2604                  */
2605                 hns3_enable_all_queues(hw, true);
2606         }
2607
2608         return 0;
2609 }
2610
2611 static int
2612 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2613 {
2614         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2615         struct rte_ether_addr *hw_mac;
2616         int ret;
2617
2618         /*
2619          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2620          * on the host by "ip link set ..." command. If the hns3 PF kernel
2621          * ethdev driver sets the MAC address for VF device after the
2622          * initialization of the related VF device, the PF driver will notify
2623          * VF driver to reset VF device to make the new MAC address effective
2624          * immediately. The hns3 VF PMD driver should check whether the MAC
2625          * address has been changed by the PF kernel ethdev driver, if changed
2626          * VF driver should configure hardware using the new MAC address in the
2627          * recovering hardware configuration stage of the reset process.
2628          */
2629         ret = hns3vf_get_host_mac_addr(hw);
2630         if (ret)
2631                 return ret;
2632
2633         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2634         ret = rte_is_zero_ether_addr(hw_mac);
2635         if (ret) {
2636                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2637         } else {
2638                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2639                 if (!ret) {
2640                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2641                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2642                                               &hw->data->mac_addrs[0]);
2643                         hns3_warn(hw, "Default MAC address has been changed to:"
2644                                   " %s by the host PF kernel ethdev driver",
2645                                   mac_str);
2646                 }
2647         }
2648
2649         return 0;
2650 }
2651
2652 static int
2653 hns3vf_restore_conf(struct hns3_adapter *hns)
2654 {
2655         struct hns3_hw *hw = &hns->hw;
2656         int ret;
2657
2658         ret = hns3vf_check_default_mac_change(hw);
2659         if (ret)
2660                 return ret;
2661
2662         ret = hns3vf_configure_mac_addr(hns, false);
2663         if (ret)
2664                 return ret;
2665
2666         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2667         if (ret)
2668                 goto err_mc_mac;
2669
2670         ret = hns3vf_restore_promisc(hns);
2671         if (ret)
2672                 goto err_vlan_table;
2673
2674         ret = hns3vf_restore_vlan_conf(hns);
2675         if (ret)
2676                 goto err_vlan_table;
2677
2678         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2679         if (ret)
2680                 goto err_vlan_table;
2681
2682         ret = hns3vf_restore_rx_interrupt(hw);
2683         if (ret)
2684                 goto err_vlan_table;
2685
2686         ret = hns3_restore_gro_conf(hw);
2687         if (ret)
2688                 goto err_vlan_table;
2689
2690         if (hw->adapter_state == HNS3_NIC_STARTED) {
2691                 ret = hns3vf_do_start(hns, false);
2692                 if (ret)
2693                         goto err_vlan_table;
2694                 hns3_info(hw, "hns3vf dev restart successful!");
2695         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2696                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2697
2698         ret = hns3vf_set_alive(hw, true);
2699         if (ret) {
2700                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2701                 goto err_vlan_table;
2702         }
2703
2704         return 0;
2705
2706 err_vlan_table:
2707         hns3vf_configure_all_mc_mac_addr(hns, true);
2708 err_mc_mac:
2709         hns3vf_configure_mac_addr(hns, true);
2710         return ret;
2711 }
2712
2713 static enum hns3_reset_level
2714 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2715 {
2716         enum hns3_reset_level reset_level;
2717
2718         /* return the highest priority reset level amongst all */
2719         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2720                 reset_level = HNS3_VF_RESET;
2721         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2722                 reset_level = HNS3_VF_FULL_RESET;
2723         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2724                 reset_level = HNS3_VF_PF_FUNC_RESET;
2725         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2726                 reset_level = HNS3_VF_FUNC_RESET;
2727         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2728                 reset_level = HNS3_FLR_RESET;
2729         else
2730                 reset_level = HNS3_NONE_RESET;
2731
2732         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2733                 return HNS3_NONE_RESET;
2734
2735         return reset_level;
2736 }
2737
2738 static void
2739 hns3vf_reset_service(void *param)
2740 {
2741         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2742         struct hns3_hw *hw = &hns->hw;
2743         enum hns3_reset_level reset_level;
2744         struct timeval tv_delta;
2745         struct timeval tv_start;
2746         struct timeval tv;
2747         uint64_t msec;
2748
2749         /*
2750          * The interrupt is not triggered within the delay time.
2751          * The interrupt may have been lost. It is necessary to handle
2752          * the interrupt to recover from the error.
2753          */
2754         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2755                             SCHEDULE_DEFERRED) {
2756                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2757                                  __ATOMIC_RELAXED);
2758                 hns3_err(hw, "Handling interrupts in delayed tasks");
2759                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2760                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2761                 if (reset_level == HNS3_NONE_RESET) {
2762                         hns3_err(hw, "No reset level is set, try global reset");
2763                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2764                 }
2765         }
2766         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2767
2768         /*
2769          * Hardware reset has been notified, we now have to poll & check if
2770          * hardware has actually completed the reset sequence.
2771          */
2772         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2773         if (reset_level != HNS3_NONE_RESET) {
2774                 hns3_clock_gettime(&tv_start);
2775                 hns3_reset_process(hns, reset_level);
2776                 hns3_clock_gettime(&tv);
2777                 timersub(&tv, &tv_start, &tv_delta);
2778                 msec = hns3_clock_calctime_ms(&tv_delta);
2779                 if (msec > HNS3_RESET_PROCESS_MS)
2780                         hns3_err(hw, "%d handle long time delta %" PRIu64
2781                                  " ms time=%ld.%.6ld",
2782                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2783         }
2784 }
2785
2786 static int
2787 hns3vf_reinit_dev(struct hns3_adapter *hns)
2788 {
2789         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2790         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2791         struct hns3_hw *hw = &hns->hw;
2792         int ret;
2793
2794         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2795                 rte_intr_disable(&pci_dev->intr_handle);
2796                 ret = hns3vf_set_bus_master(pci_dev, true);
2797                 if (ret < 0) {
2798                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2799                         return ret;
2800                 }
2801         }
2802
2803         /* Firmware command initialize */
2804         ret = hns3_cmd_init(hw);
2805         if (ret) {
2806                 hns3_err(hw, "Failed to init cmd: %d", ret);
2807                 return ret;
2808         }
2809
2810         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2811                 /*
2812                  * UIO enables msix by writing the pcie configuration space
2813                  * vfio_pci enables msix in rte_intr_enable.
2814                  */
2815                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2816                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2817                         if (hns3vf_enable_msix(pci_dev, true))
2818                                 hns3_err(hw, "Failed to enable msix");
2819                 }
2820
2821                 rte_intr_enable(&pci_dev->intr_handle);
2822         }
2823
2824         ret = hns3_reset_all_tqps(hns);
2825         if (ret) {
2826                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2827                 return ret;
2828         }
2829
2830         ret = hns3vf_init_hardware(hns);
2831         if (ret) {
2832                 hns3_err(hw, "Failed to init hardware: %d", ret);
2833                 return ret;
2834         }
2835
2836         return 0;
2837 }
2838
2839 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2840         .dev_configure      = hns3vf_dev_configure,
2841         .dev_start          = hns3vf_dev_start,
2842         .dev_stop           = hns3vf_dev_stop,
2843         .dev_close          = hns3vf_dev_close,
2844         .mtu_set            = hns3vf_dev_mtu_set,
2845         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2846         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2847         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2848         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2849         .stats_get          = hns3_stats_get,
2850         .stats_reset        = hns3_stats_reset,
2851         .xstats_get         = hns3_dev_xstats_get,
2852         .xstats_get_names   = hns3_dev_xstats_get_names,
2853         .xstats_reset       = hns3_dev_xstats_reset,
2854         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2855         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2856         .dev_infos_get      = hns3vf_dev_infos_get,
2857         .fw_version_get     = hns3vf_fw_version_get,
2858         .rx_queue_setup     = hns3_rx_queue_setup,
2859         .tx_queue_setup     = hns3_tx_queue_setup,
2860         .rx_queue_release   = hns3_dev_rx_queue_release,
2861         .tx_queue_release   = hns3_dev_tx_queue_release,
2862         .rx_queue_start     = hns3_dev_rx_queue_start,
2863         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2864         .tx_queue_start     = hns3_dev_tx_queue_start,
2865         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2866         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2867         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2868         .rxq_info_get       = hns3_rxq_info_get,
2869         .txq_info_get       = hns3_txq_info_get,
2870         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2871         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2872         .mac_addr_add       = hns3vf_add_mac_addr,
2873         .mac_addr_remove    = hns3vf_remove_mac_addr,
2874         .mac_addr_set       = hns3vf_set_default_mac_addr,
2875         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2876         .link_update        = hns3vf_dev_link_update,
2877         .rss_hash_update    = hns3_dev_rss_hash_update,
2878         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2879         .reta_update        = hns3_dev_rss_reta_update,
2880         .reta_query         = hns3_dev_rss_reta_query,
2881         .flow_ops_get       = hns3_dev_flow_ops_get,
2882         .vlan_filter_set    = hns3vf_vlan_filter_set,
2883         .vlan_offload_set   = hns3vf_vlan_offload_set,
2884         .get_reg            = hns3_get_regs,
2885         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2886         .tx_done_cleanup    = hns3_tx_done_cleanup,
2887 };
2888
2889 static const struct hns3_reset_ops hns3vf_reset_ops = {
2890         .reset_service       = hns3vf_reset_service,
2891         .stop_service        = hns3vf_stop_service,
2892         .prepare_reset       = hns3vf_prepare_reset,
2893         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2894         .reinit_dev          = hns3vf_reinit_dev,
2895         .restore_conf        = hns3vf_restore_conf,
2896         .start_service       = hns3vf_start_service,
2897 };
2898
2899 static int
2900 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2901 {
2902         struct hns3_adapter *hns = eth_dev->data->dev_private;
2903         struct hns3_hw *hw = &hns->hw;
2904         int ret;
2905
2906         PMD_INIT_FUNC_TRACE();
2907
2908         eth_dev->process_private = (struct hns3_process_private *)
2909             rte_zmalloc_socket("hns3_filter_list",
2910                                sizeof(struct hns3_process_private),
2911                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2912         if (eth_dev->process_private == NULL) {
2913                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2914                 return -ENOMEM;
2915         }
2916
2917         hns3_flow_init(eth_dev);
2918
2919         hns3_set_rxtx_function(eth_dev);
2920         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2921         eth_dev->rx_queue_count = hns3_rx_queue_count;
2922         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2923                 ret = hns3_mp_init_secondary();
2924                 if (ret) {
2925                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2926                                           "process, ret = %d", ret);
2927                         goto err_mp_init_secondary;
2928                 }
2929
2930                 hw->secondary_cnt++;
2931                 return 0;
2932         }
2933
2934         ret = hns3_mp_init_primary();
2935         if (ret) {
2936                 PMD_INIT_LOG(ERR,
2937                              "Failed to init for primary process, ret = %d",
2938                              ret);
2939                 goto err_mp_init_primary;
2940         }
2941
2942         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2943         hns->is_vf = true;
2944         hw->data = eth_dev->data;
2945         hns3_parse_devargs(eth_dev);
2946
2947         ret = hns3_reset_init(hw);
2948         if (ret)
2949                 goto err_init_reset;
2950         hw->reset.ops = &hns3vf_reset_ops;
2951
2952         ret = hns3vf_init_vf(eth_dev);
2953         if (ret) {
2954                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2955                 goto err_init_vf;
2956         }
2957
2958         /* Allocate memory for storing MAC addresses */
2959         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2960                                                sizeof(struct rte_ether_addr) *
2961                                                HNS3_VF_UC_MACADDR_NUM, 0);
2962         if (eth_dev->data->mac_addrs == NULL) {
2963                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2964                              "to store MAC addresses",
2965                              sizeof(struct rte_ether_addr) *
2966                              HNS3_VF_UC_MACADDR_NUM);
2967                 ret = -ENOMEM;
2968                 goto err_rte_zmalloc;
2969         }
2970
2971         /*
2972          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2973          * on the host by "ip link set ..." command. To avoid some incorrect
2974          * scenes, for example, hns3 VF PMD driver fails to receive and send
2975          * packets after user configure the MAC address by using the
2976          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2977          * address strategy as the hns3 kernel ethdev driver in the
2978          * initialization. If user configure a MAC address by the ip command
2979          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2980          * start with a random MAC address in the initialization.
2981          */
2982         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2983                 rte_eth_random_addr(hw->mac.mac_addr);
2984         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2985                             &eth_dev->data->mac_addrs[0]);
2986
2987         hw->adapter_state = HNS3_NIC_INITIALIZED;
2988
2989         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2990                             SCHEDULE_PENDING) {
2991                 hns3_err(hw, "Reschedule reset service after dev_init");
2992                 hns3_schedule_reset(hns);
2993         } else {
2994                 /* IMP will wait ready flag before reset */
2995                 hns3_notify_reset_ready(hw, false);
2996         }
2997         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2998                           eth_dev);
2999         return 0;
3000
3001 err_rte_zmalloc:
3002         hns3vf_uninit_vf(eth_dev);
3003
3004 err_init_vf:
3005         rte_free(hw->reset.wait_data);
3006
3007 err_init_reset:
3008         hns3_mp_uninit_primary();
3009
3010 err_mp_init_primary:
3011 err_mp_init_secondary:
3012         eth_dev->dev_ops = NULL;
3013         eth_dev->rx_pkt_burst = NULL;
3014         eth_dev->rx_descriptor_status = NULL;
3015         eth_dev->tx_pkt_burst = NULL;
3016         eth_dev->tx_pkt_prepare = NULL;
3017         eth_dev->tx_descriptor_status = NULL;
3018         rte_free(eth_dev->process_private);
3019         eth_dev->process_private = NULL;
3020
3021         return ret;
3022 }
3023
3024 static int
3025 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3026 {
3027         struct hns3_adapter *hns = eth_dev->data->dev_private;
3028         struct hns3_hw *hw = &hns->hw;
3029
3030         PMD_INIT_FUNC_TRACE();
3031
3032         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3033                 rte_free(eth_dev->process_private);
3034                 eth_dev->process_private = NULL;
3035                 return 0;
3036         }
3037
3038         if (hw->adapter_state < HNS3_NIC_CLOSING)
3039                 hns3vf_dev_close(eth_dev);
3040
3041         hw->adapter_state = HNS3_NIC_REMOVED;
3042         return 0;
3043 }
3044
3045 static int
3046 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3047                      struct rte_pci_device *pci_dev)
3048 {
3049         return rte_eth_dev_pci_generic_probe(pci_dev,
3050                                              sizeof(struct hns3_adapter),
3051                                              hns3vf_dev_init);
3052 }
3053
3054 static int
3055 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3056 {
3057         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3058 }
3059
3060 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3061         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3062         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3063         { .vendor_id = 0, }, /* sentinel */
3064 };
3065
3066 static struct rte_pci_driver rte_hns3vf_pmd = {
3067         .id_table = pci_id_hns3vf_map,
3068         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3069         .probe = eth_hns3vf_pci_probe,
3070         .remove = eth_hns3vf_pci_remove,
3071 };
3072
3073 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3074 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3075 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3076 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3077                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3078                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3079                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");