drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <rte_ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 /* set PCI bus mastering */
  48 static int
  49 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  50 {
  51         uint16_t reg;
  52         int ret;
  53
  54         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  55         if (ret < 0) {
  56                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  57                              PCI_COMMAND);
  58                 return ret;
  59         }
  60
  61         if (op)
  62                 /* set the master bit */
  63                 reg |= PCI_COMMAND_MASTER;
  64         else
  65                 reg &= ~(PCI_COMMAND_MASTER);
  66
  67         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  68 }
  69
  70 /**
  71  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  72  * @cap: the capability
  73  *
  74  * Return the address of the given capability within the PCI capability list.
  75  */
  76 static int
  77 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  78 {
  79 #define MAX_PCIE_CAPABILITY 48
  80         uint16_t status;
  81         uint8_t pos;
  82         uint8_t id;
  83         int ttl;
  84         int ret;
  85
  86         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  87         if (ret < 0) {
  88                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  89                 return 0;
  90         }
  91
  92         if (!(status & PCI_STATUS_CAP_LIST))
  93                 return 0;
  94
  95         ttl = MAX_PCIE_CAPABILITY;
  96         ret = rte_pci_read_config(device, &pos, sizeof(pos),
  97                                   PCI_CAPABILITY_LIST);
  98         if (ret < 0) {
  99                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 100                              PCI_CAPABILITY_LIST);
 101                 return 0;
 102         }
 103
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 ret = rte_pci_read_config(device, &id, sizeof(id),
 106                                           (pos + PCI_CAP_LIST_ID));
 107                 if (ret < 0) {
 108                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 109                                      (pos + PCI_CAP_LIST_ID));
 110                         break;
 111                 }
 112
 113                 if (id == 0xFF)
 114                         break;
 115
 116                 if (id == cap)
 117                         return (int)pos;
 118
 119                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 120                                           (pos + PCI_CAP_LIST_NEXT));
 121                 if (ret < 0) {
 122                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 123                                      (pos + PCI_CAP_LIST_NEXT));
 124                         break;
 125                 }
 126         }
 127         return 0;
 128 }
 129
 130 static int
 131 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 132 {
 133         uint16_t control;
 134         int pos;
 135         int ret;
 136
 137         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 138         if (pos) {
 139                 ret = rte_pci_read_config(device, &control, sizeof(control),
 140                                     (pos + PCI_MSIX_FLAGS));
 141                 if (ret < 0) {
 142                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 143                                      (pos + PCI_MSIX_FLAGS));
 144                         return -ENXIO;
 145                 }
 146
 147                 if (op)
 148                         control |= PCI_MSIX_FLAGS_ENABLE;
 149                 else
 150                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 151                 ret = rte_pci_write_config(device, &control, sizeof(control),
 152                                           (pos + PCI_MSIX_FLAGS));
 153                 if (ret < 0) {
 154                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 155                                     (pos + PCI_MSIX_FLAGS));
 156                 }
 157                 return 0;
 158         }
 159         return -ENXIO;
 160 }
 161
 162 static int
 163 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 164 {
 165         /* mac address was checked by upper level interface */
 166         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 167         int ret;
 168
 169         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 170                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 171                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 172         if (ret) {
 173                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 174                                       mac_addr);
 175                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 176                          mac_str, ret);
 177         }
 178         return ret;
 179 }
 180
 181 static int
 182 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 183 {
 184         /* mac address was checked by upper level interface */
 185         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 186         int ret;
 187
 188         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 189                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 190                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 191                                 false, NULL, 0);
 192         if (ret) {
 193                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 194                                       mac_addr);
 195                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 196                          mac_str, ret);
 197         }
 198         return ret;
 199 }
 200
 201 static int
 202 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 203 {
 204         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 205         struct rte_ether_addr *addr;
 206         int ret;
 207         int i;
 208
 209         for (i = 0; i < hw->mc_addrs_num; i++) {
 210                 addr = &hw->mc_addrs[i];
 211                 /* Check if there are duplicate addresses */
 212                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 213                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 214                                               addr);
 215                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 216                                  "(%s) is added by the set_mc_mac_addr_list "
 217                                  "API", mac_str);
 218                         return -EINVAL;
 219                 }
 220         }
 221
 222         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 223         if (ret) {
 224                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 225                                       mac_addr);
 226                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 227                          mac_str, ret);
 228         }
 229         return ret;
 230 }
 231
 232 static int
 233 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 234                     __rte_unused uint32_t idx,
 235                     __rte_unused uint32_t pool)
 236 {
 237         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 238         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 239         int ret;
 240
 241         rte_spinlock_lock(&hw->lock);
 242
 243         /*
 244          * In hns3 network engine adding UC and MC mac address with different
 245          * commands with firmware. We need to determine whether the input
 246          * address is a UC or a MC address to call different commands.
 247          * By the way, it is recommended calling the API function named
 248          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 249          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 250          * may affect the specifications of UC mac addresses.
 251          */
 252         if (rte_is_multicast_ether_addr(mac_addr))
 253                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 254         else
 255                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 256
 257         rte_spinlock_unlock(&hw->lock);
 258         if (ret) {
 259                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 260                                       mac_addr);
 261                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 262                          ret);
 263         }
 264
 265         return ret;
 266 }
 267
 268 static void
 269 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 270 {
 271         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 272         /* index will be checked by upper level rte interface */
 273         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 274         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 275         int ret;
 276
 277         rte_spinlock_lock(&hw->lock);
 278
 279         if (rte_is_multicast_ether_addr(mac_addr))
 280                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 281         else
 282                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 283
 284         rte_spinlock_unlock(&hw->lock);
 285         if (ret) {
 286                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 287                                       mac_addr);
 288                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 289                          mac_str, ret);
 290         }
 291 }
 292
 293 static int
 294 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 295                             struct rte_ether_addr *mac_addr)
 296 {
 297 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 298         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 299         struct rte_ether_addr *old_addr;
 300         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 301         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 302         int ret;
 303
 304         /*
 305          * It has been guaranteed that input parameter named mac_addr is valid
 306          * address in the rte layer of DPDK framework.
 307          */
 308         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 309         rte_spinlock_lock(&hw->lock);
 310         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 311         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 312                RTE_ETHER_ADDR_LEN);
 313
 314         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 315                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 316                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 317         if (ret) {
 318                 /*
 319                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 320                  * driver. When user has configured a MAC address for VF device
 321                  * by "ip link set ..." command based on the PF device, the hns3
 322                  * PF kernel ethdev driver does not allow VF driver to request
 323                  * reconfiguring a different default MAC address, and return
 324                  * -EPREM to VF driver through mailbox.
 325                  */
 326                 if (ret == -EPERM) {
 327                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 328                                               old_addr);
 329                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 330                                   mac_str);
 331                 } else {
 332                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 333                                               mac_addr);
 334                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 335                                  mac_str, ret);
 336                 }
 337         }
 338
 339         rte_ether_addr_copy(mac_addr,
 340                             (struct rte_ether_addr *)hw->mac.mac_addr);
 341         rte_spinlock_unlock(&hw->lock);
 342
 343         return ret;
 344 }
 345
 346 static int
 347 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 348 {
 349         struct hns3_hw *hw = &hns->hw;
 350         struct rte_ether_addr *addr;
 351         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 352         int err = 0;
 353         int ret;
 354         int i;
 355
 356         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 357                 addr = &hw->data->mac_addrs[i];
 358                 if (rte_is_zero_ether_addr(addr))
 359                         continue;
 360                 if (rte_is_multicast_ether_addr(addr))
 361                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 362                               hns3vf_add_mc_mac_addr(hw, addr);
 363                 else
 364                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 365                               hns3vf_add_uc_mac_addr(hw, addr);
 366
 367                 if (ret) {
 368                         err = ret;
 369                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 370                                               addr);
 371                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 372                                  "ret = %d.", del ? "remove" : "restore",
 373                                  mac_str, i, ret);
 374                 }
 375         }
 376         return err;
 377 }
 378
 379 static int
 380 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 381                        struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 402                           struct rte_ether_addr *mac_addr)
 403 {
 404         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 405         int ret;
 406
 407         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 408                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 409                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 410                                 NULL, 0);
 411         if (ret) {
 412                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 413                                       mac_addr);
 414                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 415                          mac_str, ret);
 416         }
 417
 418         return ret;
 419 }
 420
 421 static int
 422 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 423                              struct rte_ether_addr *mc_addr_set,
 424                              uint32_t nb_mc_addr)
 425 {
 426         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 427         struct rte_ether_addr *addr;
 428         uint32_t i;
 429         uint32_t j;
 430
 431         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 432                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 433                          "invalid. valid range: 0~%d",
 434                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 435                 return -EINVAL;
 436         }
 437
 438         /* Check if input mac addresses are valid */
 439         for (i = 0; i < nb_mc_addr; i++) {
 440                 addr = &mc_addr_set[i];
 441                 if (!rte_is_multicast_ether_addr(addr)) {
 442                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 443                                               addr);
 444                         hns3_err(hw,
 445                                  "failed to set mc mac addr, addr(%s) invalid.",
 446                                  mac_str);
 447                         return -EINVAL;
 448                 }
 449
 450                 /* Check if there are duplicate addresses */
 451                 for (j = i + 1; j < nb_mc_addr; j++) {
 452                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 453                                 hns3_ether_format_addr(mac_str,
 454                                                       RTE_ETHER_ADDR_FMT_SIZE,
 455                                                       addr);
 456                                 hns3_err(hw, "failed to set mc mac addr, "
 457                                          "addrs invalid. two same addrs(%s).",
 458                                          mac_str);
 459                                 return -EINVAL;
 460                         }
 461                 }
 462
 463                 /*
 464                  * Check if there are duplicate addresses between mac_addrs
 465                  * and mc_addr_set
 466                  */
 467                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 468                         if (rte_is_same_ether_addr(addr,
 469                                                    &hw->data->mac_addrs[j])) {
 470                                 hns3_ether_format_addr(mac_str,
 471                                                       RTE_ETHER_ADDR_FMT_SIZE,
 472                                                       addr);
 473                                 hns3_err(hw, "failed to set mc mac addr, "
 474                                          "addrs invalid. addrs(%s) has already "
 475                                          "configured in mac_addr add API",
 476                                          mac_str);
 477                                 return -EINVAL;
 478                         }
 479                 }
 480         }
 481
 482         return 0;
 483 }
 484
 485 static int
 486 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 487                             struct rte_ether_addr *mc_addr_set,
 488                             uint32_t nb_mc_addr)
 489 {
 490         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 491         struct rte_ether_addr *addr;
 492         int cur_addr_num;
 493         int set_addr_num;
 494         int num;
 495         int ret;
 496         int i;
 497
 498         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 499         if (ret)
 500                 return ret;
 501
 502         rte_spinlock_lock(&hw->lock);
 503         cur_addr_num = hw->mc_addrs_num;
 504         for (i = 0; i < cur_addr_num; i++) {
 505                 num = cur_addr_num - i - 1;
 506                 addr = &hw->mc_addrs[num];
 507                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 508                 if (ret) {
 509                         rte_spinlock_unlock(&hw->lock);
 510                         return ret;
 511                 }
 512
 513                 hw->mc_addrs_num--;
 514         }
 515
 516         set_addr_num = (int)nb_mc_addr;
 517         for (i = 0; i < set_addr_num; i++) {
 518                 addr = &mc_addr_set[i];
 519                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 520                 if (ret) {
 521                         rte_spinlock_unlock(&hw->lock);
 522                         return ret;
 523                 }
 524
 525                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 526                 hw->mc_addrs_num++;
 527         }
 528         rte_spinlock_unlock(&hw->lock);
 529
 530         return 0;
 531 }
 532
 533 static int
 534 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 535 {
 536         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 537         struct hns3_hw *hw = &hns->hw;
 538         struct rte_ether_addr *addr;
 539         int err = 0;
 540         int ret;
 541         int i;
 542
 543         for (i = 0; i < hw->mc_addrs_num; i++) {
 544                 addr = &hw->mc_addrs[i];
 545                 if (!rte_is_multicast_ether_addr(addr))
 546                         continue;
 547                 if (del)
 548                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 549                 else
 550                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 551                 if (ret) {
 552                         err = ret;
 553                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 554                                               addr);
 555                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 556                                  del ? "Remove" : "Restore", mac_str, ret);
 557                 }
 558         }
 559         return err;
 560 }
 561
 562 static int
 563 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 564                         bool en_uc_pmc, bool en_mc_pmc)
 565 {
 566         struct hns3_mbx_vf_to_pf_cmd *req;
 567         struct hns3_cmd_desc desc;
 568         int ret;
 569
 570         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 571
 572         /*
 573          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 574          * so there are some features for promiscuous/allmulticast mode in hns3
 575          * VF PMD driver as below:
 576          * 1. The promiscuous/allmulticast mode can be configured successfully
 577          *    only based on the trusted VF device. If based on the non trusted
 578          *    VF device, configuring promiscuous/allmulticast mode will fail.
 579          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 580          *    kernel ethdev driver on the host by the following command:
 581          *      "ip link set <eth num> vf <vf id> turst on"
 582          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 583          *    driver can receive the ingress and outgoing traffic. In the words,
 584          *    all the ingress packets, all the packets sent from the PF and
 585          *    other VFs on the same physical port.
 586          * 3. Note: Because of the hardware constraints, By default vlan filter
 587          *    is enabled and couldn't be turned off based on VF device, so vlan
 588          *    filter is still effective even in promiscuous mode. If upper
 589          *    applications don't call rte_eth_dev_vlan_filter API function to
 590          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 591          *    the packets with vlan tag in promiscuoue mode.
 592          */
 593         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 594         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 595         req->msg[1] = en_bc_pmc ? 1 : 0;
 596         req->msg[2] = en_uc_pmc ? 1 : 0;
 597         req->msg[3] = en_mc_pmc ? 1 : 0;
 598         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 599
 600         ret = hns3_cmd_send(hw, &desc, 1);
 601         if (ret)
 602                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 609 {
 610         struct hns3_adapter *hns = dev->data->dev_private;
 611         struct hns3_hw *hw = &hns->hw;
 612         int ret;
 613
 614         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 615         if (ret)
 616                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 617                         ret);
 618         return ret;
 619 }
 620
 621 static int
 622 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 623 {
 624         bool allmulti = dev->data->all_multicast ? true : false;
 625         struct hns3_adapter *hns = dev->data->dev_private;
 626         struct hns3_hw *hw = &hns->hw;
 627         int ret;
 628
 629         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 630         if (ret)
 631                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 632                         ret);
 633         return ret;
 634 }
 635
 636 static int
 637 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 638 {
 639         struct hns3_adapter *hns = dev->data->dev_private;
 640         struct hns3_hw *hw = &hns->hw;
 641         int ret;
 642
 643         if (dev->data->promiscuous)
 644                 return 0;
 645
 646         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 647         if (ret)
 648                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 649                         ret);
 650         return ret;
 651 }
 652
 653 static int
 654 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 655 {
 656         struct hns3_adapter *hns = dev->data->dev_private;
 657         struct hns3_hw *hw = &hns->hw;
 658         int ret;
 659
 660         if (dev->data->promiscuous)
 661                 return 0;
 662
 663         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 664         if (ret)
 665                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 666                         ret);
 667         return ret;
 668 }
 669
 670 static int
 671 hns3vf_restore_promisc(struct hns3_adapter *hns)
 672 {
 673         struct hns3_hw *hw = &hns->hw;
 674         bool allmulti = hw->data->all_multicast ? true : false;
 675
 676         if (hw->data->promiscuous)
 677                 return hns3vf_set_promisc_mode(hw, true, true, true);
 678
 679         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 680 }
 681
 682 static int
 683 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 684                              bool mmap, enum hns3_ring_type queue_type,
 685                              uint16_t queue_id)
 686 {
 687         struct hns3_vf_bind_vector_msg bind_msg;
 688         const char *op_str;
 689         uint16_t code;
 690         int ret;
 691
 692         memset(&bind_msg, 0, sizeof(bind_msg));
 693         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 694                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 695         bind_msg.vector_id = vector_id;
 696
 697         if (queue_type == HNS3_RING_TYPE_RX)
 698                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 699         else
 700                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 701
 702         bind_msg.param[0].ring_type = queue_type;
 703         bind_msg.ring_num = 1;
 704         bind_msg.param[0].tqp_index = queue_id;
 705         op_str = mmap ? "Map" : "Unmap";
 706         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 707                                 sizeof(bind_msg), false, NULL, 0);
 708         if (ret)
 709                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 710                          op_str, queue_id, bind_msg.vector_id, ret);
 711
 712         return ret;
 713 }
 714
 715 static int
 716 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 717 {
 718         uint16_t vec;
 719         int ret;
 720         int i;
 721
 722         /*
 723          * In hns3 network engine, vector 0 is always the misc interrupt of this
 724          * function, vector 1~N can be used respectively for the queues of the
 725          * function. Tx and Rx queues with the same number share the interrupt
 726          * vector. In the initialization clearing the all hardware mapping
 727          * relationship configurations between queues and interrupt vectors is
 728          * needed, so some error caused by the residual configurations, such as
 729          * the unexpected Tx interrupt, can be avoid.
 730          */
 731         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 732         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 733                 vec = vec - 1; /* the last interrupt is reserved */
 734         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 735         for (i = 0; i < hw->intr_tqps_num; i++) {
 736                 /*
 737                  * Set gap limiter/rate limiter/quanity limiter algorithm
 738                  * configuration for interrupt coalesce of queue's interrupt.
 739                  */
 740                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 741                                        HNS3_TQP_INTR_GL_DEFAULT);
 742                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 743                                        HNS3_TQP_INTR_GL_DEFAULT);
 744                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 745                 /*
 746                  * QL(quantity limiter) is not used currently, just set 0 to
 747                  * close it.
 748                  */
 749                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 750
 751                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 752                                                    HNS3_RING_TYPE_TX, i);
 753                 if (ret) {
 754                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 755                                           "vector: %u, ret=%d", i, vec, ret);
 756                         return ret;
 757                 }
 758
 759                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 760                                                    HNS3_RING_TYPE_RX, i);
 761                 if (ret) {
 762                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 763                                           "vector: %u, ret=%d", i, vec, ret);
 764                         return ret;
 765                 }
 766         }
 767
 768         return 0;
 769 }
 770
 771 static int
 772 hns3vf_dev_configure(struct rte_eth_dev *dev)
 773 {
 774         struct hns3_adapter *hns = dev->data->dev_private;
 775         struct hns3_hw *hw = &hns->hw;
 776         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 777         struct rte_eth_conf *conf = &dev->data->dev_conf;
 778         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 779         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 780         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 781         struct rte_eth_rss_conf rss_conf;
 782         uint16_t mtu;
 783         bool gro_en;
 784         int ret;
 785
 786         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 787
 788         /*
 789          * Some versions of hardware network engine does not support
 790          * individually enable/disable/reset the Tx or Rx queue. These devices
 791          * must enable/disable/reset Tx and Rx queues at the same time. When the
 792          * numbers of Tx queues allocated by upper applications are not equal to
 793          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 794          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 795          * work as usual. But these fake queues are imperceptible, and can not
 796          * be used by upper applications.
 797          */
 798         if (!hns3_dev_indep_txrx_supported(hw)) {
 799                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 800                 if (ret) {
 801                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
 802                                  ret);
 803                         return ret;
 804                 }
 805         }
 806
 807         hw->adapter_state = HNS3_NIC_CONFIGURING;
 808         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 809                 hns3_err(hw, "setting link speed/duplex not supported");
 810                 ret = -EINVAL;
 811                 goto cfg_err;
 812         }
 813
 814         /* When RSS is not configured, redirect the packet queue 0 */
 815         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 816                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 817                 hw->rss_dis_flag = false;
 818                 rss_conf = conf->rx_adv_conf.rss_conf;
 819                 if (rss_conf.rss_key == NULL) {
 820                         rss_conf.rss_key = rss_cfg->key;
 821                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 822                 }
 823
 824                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 825                 if (ret)
 826                         goto cfg_err;
 827         }
 828
 829         /*
 830          * If jumbo frames are enabled, MTU needs to be refreshed
 831          * according to the maximum RX packet length.
 832          */
 833         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 834                 /*
 835                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 836                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 837                  * can safely assign to "uint16_t" type variable.
 838                  */
 839                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 840                 ret = hns3vf_dev_mtu_set(dev, mtu);
 841                 if (ret)
 842                         goto cfg_err;
 843                 dev->data->mtu = mtu;
 844         }
 845
 846         ret = hns3vf_dev_configure_vlan(dev);
 847         if (ret)
 848                 goto cfg_err;
 849
 850         /* config hardware GRO */
 851         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 852         ret = hns3_config_gro(hw, gro_en);
 853         if (ret)
 854                 goto cfg_err;
 855
 856         hns->rx_simple_allowed = true;
 857         hns->rx_vec_allowed = true;
 858         hns->tx_simple_allowed = true;
 859         hns->tx_vec_allowed = true;
 860
 861         hns3_init_rx_ptype_tble(dev);
 862
 863         hw->adapter_state = HNS3_NIC_CONFIGURED;
 864         return 0;
 865
 866 cfg_err:
 867         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 868         hw->adapter_state = HNS3_NIC_INITIALIZED;
 869
 870         return ret;
 871 }
 872
 873 static int
 874 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 875 {
 876         int ret;
 877
 878         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 879                                 sizeof(mtu), true, NULL, 0);
 880         if (ret)
 881                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 882
 883         return ret;
 884 }
 885
 886 static int
 887 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 888 {
 889         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 890         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 891         int ret;
 892
 893         /*
 894          * The hns3 PF/VF devices on the same port share the hardware MTU
 895          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 896          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 897          * driver, there is no need to stop the port for hns3 VF device, and the
 898          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 899          * PF's MTU.
 900          */
 901         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 902                 hns3_err(hw, "Failed to set mtu during resetting");
 903                 return -EIO;
 904         }
 905
 906         /*
 907          * when Rx of scattered packets is off, we have some possibility of
 908          * using vector Rx process function or simple Rx functions in hns3 PMD
 909          * driver. If the input MTU is increased and the maximum length of
 910          * received packets is greater than the length of a buffer for Rx
 911          * packet, the hardware network engine needs to use multiple BDs and
 912          * buffers to store these packets. This will cause problems when still
 913          * using vector Rx process function or simple Rx function to receiving
 914          * packets. So, when Rx of scattered packets is off and device is
 915          * started, it is not permitted to increase MTU so that the maximum
 916          * length of Rx packets is greater than Rx buffer length.
 917          */
 918         if (dev->data->dev_started && !dev->data->scattered_rx &&
 919             frame_size > hw->rx_buf_len) {
 920                 hns3_err(hw, "failed to set mtu because current is "
 921                         "not scattered rx mode");
 922                 return -EOPNOTSUPP;
 923         }
 924
 925         rte_spinlock_lock(&hw->lock);
 926         ret = hns3vf_config_mtu(hw, mtu);
 927         if (ret) {
 928                 rte_spinlock_unlock(&hw->lock);
 929                 return ret;
 930         }
 931         if (mtu > RTE_ETHER_MTU)
 932                 dev->data->dev_conf.rxmode.offloads |=
 933                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 934         else
 935                 dev->data->dev_conf.rxmode.offloads &=
 936                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 937         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 938         rte_spinlock_unlock(&hw->lock);
 939
 940         return 0;
 941 }
 942
 943 static int
 944 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 945 {
 946         struct hns3_adapter *hns = eth_dev->data->dev_private;
 947         struct hns3_hw *hw = &hns->hw;
 948         uint16_t q_num = hw->tqps_num;
 949
 950         /*
 951          * In interrupt mode, 'max_rx_queues' is set based on the number of
 952          * MSI-X interrupt resources of the hardware.
 953          */
 954         if (hw->data->dev_conf.intr_conf.rxq == 1)
 955                 q_num = hw->intr_tqps_num;
 956
 957         info->max_rx_queues = q_num;
 958         info->max_tx_queues = hw->tqps_num;
 959         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 960         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 961         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 962         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 963         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 964
 965         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 966                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 967                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 968                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 969                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 970                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 971                                  DEV_RX_OFFLOAD_SCATTER |
 972                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 973                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 974                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 975                                  DEV_RX_OFFLOAD_RSS_HASH |
 976                                  DEV_RX_OFFLOAD_TCP_LRO);
 977         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 978                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 979                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 980                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 981                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 982                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 983                                  DEV_TX_OFFLOAD_TCP_TSO |
 984                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 985                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 986                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 987                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 988                                  hns3_txvlan_cap_get(hw));
 989
 990         if (hns3_dev_indep_txrx_supported(hw))
 991                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 992                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 993
 994         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 995                 .nb_max = HNS3_MAX_RING_DESC,
 996                 .nb_min = HNS3_MIN_RING_DESC,
 997                 .nb_align = HNS3_ALIGN_RING_DESC,
 998         };
 999
1000         info->tx_desc_lim = (struct rte_eth_desc_lim) {
1001                 .nb_max = HNS3_MAX_RING_DESC,
1002                 .nb_min = HNS3_MIN_RING_DESC,
1003                 .nb_align = HNS3_ALIGN_RING_DESC,
1004                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
1005                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1006         };
1007
1008         info->default_rxconf = (struct rte_eth_rxconf) {
1009                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1010                 /*
1011                  * If there are no available Rx buffer descriptors, incoming
1012                  * packets are always dropped by hardware based on hns3 network
1013                  * engine.
1014                  */
1015                 .rx_drop_en = 1,
1016                 .offloads = 0,
1017         };
1018         info->default_txconf = (struct rte_eth_txconf) {
1019                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1020                 .offloads = 0,
1021         };
1022
1023         info->vmdq_queue_num = 0;
1024
1025         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1026         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1027         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1028         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1029         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1030
1031         return 0;
1032 }
1033
1034 static void
1035 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1036 {
1037         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1038 }
1039
1040 static void
1041 hns3vf_disable_irq0(struct hns3_hw *hw)
1042 {
1043         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1044 }
1045
1046 static void
1047 hns3vf_enable_irq0(struct hns3_hw *hw)
1048 {
1049         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1050 }
1051
1052 static enum hns3vf_evt_cause
1053 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1054 {
1055         struct hns3_hw *hw = &hns->hw;
1056         enum hns3vf_evt_cause ret;
1057         uint32_t cmdq_stat_reg;
1058         uint32_t rst_ing_reg;
1059         uint32_t val;
1060
1061         /* Fetch the events from their corresponding regs */
1062         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1063
1064         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1065                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1066                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1067                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1068                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1069                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1070                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1071                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1072                 if (clearval) {
1073                         hw->reset.stats.global_cnt++;
1074                         hns3_warn(hw, "Global reset detected, clear reset status");
1075                 } else {
1076                         hns3_schedule_delayed_reset(hns);
1077                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1078                 }
1079
1080                 ret = HNS3VF_VECTOR0_EVENT_RST;
1081                 goto out;
1082         }
1083
1084         /* Check for vector0 mailbox(=CMDQ RX) event source */
1085         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1086                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1087                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1088                 goto out;
1089         }
1090
1091         val = 0;
1092         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1093 out:
1094         if (clearval)
1095                 *clearval = val;
1096         return ret;
1097 }
1098
1099 static void
1100 hns3vf_interrupt_handler(void *param)
1101 {
1102         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1103         struct hns3_adapter *hns = dev->data->dev_private;
1104         struct hns3_hw *hw = &hns->hw;
1105         enum hns3vf_evt_cause event_cause;
1106         uint32_t clearval;
1107
1108         if (hw->irq_thread_id == 0)
1109                 hw->irq_thread_id = pthread_self();
1110
1111         /* Disable interrupt */
1112         hns3vf_disable_irq0(hw);
1113
1114         /* Read out interrupt causes */
1115         event_cause = hns3vf_check_event_cause(hns, &clearval);
1116
1117         switch (event_cause) {
1118         case HNS3VF_VECTOR0_EVENT_RST:
1119                 hns3_schedule_reset(hns);
1120                 break;
1121         case HNS3VF_VECTOR0_EVENT_MBX:
1122                 hns3_dev_handle_mbx_msg(hw);
1123                 break;
1124         default:
1125                 break;
1126         }
1127
1128         /* Clear interrupt causes */
1129         hns3vf_clear_event_cause(hw, clearval);
1130
1131         /* Enable interrupt */
1132         hns3vf_enable_irq0(hw);
1133 }
1134
1135 static void
1136 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1137 {
1138         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1139         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1140         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1141         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1142 }
1143
1144 static void
1145 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1146 {
1147         struct hns3_dev_specs_0_cmd *req0;
1148
1149         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1150
1151         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1152         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1153         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1154         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1155 }
1156
1157 static int
1158 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1159 {
1160         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1161         int ret;
1162         int i;
1163
1164         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1165                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1166                                           true);
1167                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1168         }
1169         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1170
1171         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1172         if (ret)
1173                 return ret;
1174
1175         hns3vf_parse_dev_specifications(hw, desc);
1176
1177         return 0;
1178 }
1179
1180 static int
1181 hns3vf_get_capability(struct hns3_hw *hw)
1182 {
1183         struct rte_pci_device *pci_dev;
1184         struct rte_eth_dev *eth_dev;
1185         uint8_t revision;
1186         int ret;
1187
1188         eth_dev = &rte_eth_devices[hw->data->port_id];
1189         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1190
1191         /* Get PCI revision id */
1192         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1193                                   HNS3_PCI_REVISION_ID);
1194         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1195                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1196                              ret);
1197                 return -EIO;
1198         }
1199         hw->revision = revision;
1200
1201         if (revision < PCI_REVISION_ID_HIP09_A) {
1202                 hns3vf_set_default_dev_specifications(hw);
1203                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1204                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1205                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1206                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1207                 hw->rss_info.ipv6_sctp_offload_supported = false;
1208                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1209                 return 0;
1210         }
1211
1212         ret = hns3vf_query_dev_specifications(hw);
1213         if (ret) {
1214                 PMD_INIT_LOG(ERR,
1215                              "failed to query dev specifications, ret = %d",
1216                              ret);
1217                 return ret;
1218         }
1219
1220         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1221         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1222         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1223         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1224         hw->rss_info.ipv6_sctp_offload_supported = true;
1225         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1226
1227         return 0;
1228 }
1229
1230 static int
1231 hns3vf_check_tqp_info(struct hns3_hw *hw)
1232 {
1233         if (hw->tqps_num == 0) {
1234                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1235                 return -EINVAL;
1236         }
1237
1238         if (hw->rss_size_max == 0) {
1239                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1240                 return -EINVAL;
1241         }
1242
1243         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1244
1245         return 0;
1246 }
1247
1248 static int
1249 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1250 {
1251         uint8_t resp_msg;
1252         int ret;
1253
1254         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1255                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1256                                 true, &resp_msg, sizeof(resp_msg));
1257         if (ret) {
1258                 if (ret == -ETIME) {
1259                         /*
1260                          * Getting current port based VLAN state from PF driver
1261                          * will not affect VF driver's basic function. Because
1262                          * the VF driver relies on hns3 PF kernel ether driver,
1263                          * to avoid introducing compatibility issues with older
1264                          * version of PF driver, no failure will be returned
1265                          * when the return value is ETIME. This return value has
1266                          * the following scenarios:
1267                          * 1) Firmware didn't return the results in time
1268                          * 2) the result return by firmware is timeout
1269                          * 3) the older version of kernel side PF driver does
1270                          *    not support this mailbox message.
1271                          * For scenarios 1 and 2, it is most likely that a
1272                          * hardware error has occurred, or a hardware reset has
1273                          * occurred. In this case, these errors will be caught
1274                          * by other functions.
1275                          */
1276                         PMD_INIT_LOG(WARNING,
1277                                 "failed to get PVID state for timeout, maybe "
1278                                 "kernel side PF driver doesn't support this "
1279                                 "mailbox message, or firmware didn't respond.");
1280                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1281                 } else {
1282                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1283                                 " ret = %d", ret);
1284                         return ret;
1285                 }
1286         }
1287         hw->port_base_vlan_cfg.state = resp_msg ?
1288                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1289         return 0;
1290 }
1291
1292 static int
1293 hns3vf_get_queue_info(struct hns3_hw *hw)
1294 {
1295 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1296         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1297         int ret;
1298
1299         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1300                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1301         if (ret) {
1302                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1303                 return ret;
1304         }
1305
1306         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1307         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1308
1309         return hns3vf_check_tqp_info(hw);
1310 }
1311
1312 static int
1313 hns3vf_get_queue_depth(struct hns3_hw *hw)
1314 {
1315 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1316         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1317         int ret;
1318
1319         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1320                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1321         if (ret) {
1322                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1323                              ret);
1324                 return ret;
1325         }
1326
1327         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1328         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1329
1330         return 0;
1331 }
1332
1333 static int
1334 hns3vf_get_tc_info(struct hns3_hw *hw)
1335 {
1336         uint8_t resp_msg;
1337         int ret;
1338         uint32_t i;
1339
1340         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1341                                 true, &resp_msg, sizeof(resp_msg));
1342         if (ret) {
1343                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1344                          ret);
1345                 return ret;
1346         }
1347
1348         hw->hw_tc_map = resp_msg;
1349
1350         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1351                 if (hw->hw_tc_map & BIT(i))
1352                         hw->num_tc++;
1353         }
1354
1355         return 0;
1356 }
1357
1358 static int
1359 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1360 {
1361         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1362         int ret;
1363
1364         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1365                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1366         if (ret) {
1367                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1368                 return ret;
1369         }
1370
1371         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1372
1373         return 0;
1374 }
1375
1376 static int
1377 hns3vf_get_configuration(struct hns3_hw *hw)
1378 {
1379         int ret;
1380
1381         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1382         hw->rss_dis_flag = false;
1383
1384         /* Get device capability */
1385         ret = hns3vf_get_capability(hw);
1386         if (ret) {
1387                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1388                 return ret;
1389         }
1390
1391         /* Get queue configuration from PF */
1392         ret = hns3vf_get_queue_info(hw);
1393         if (ret)
1394                 return ret;
1395
1396         /* Get queue depth info from PF */
1397         ret = hns3vf_get_queue_depth(hw);
1398         if (ret)
1399                 return ret;
1400
1401         /* Get user defined VF MAC addr from PF */
1402         ret = hns3vf_get_host_mac_addr(hw);
1403         if (ret)
1404                 return ret;
1405
1406         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1407         if (ret)
1408                 return ret;
1409
1410         /* Get tc configuration from PF */
1411         return hns3vf_get_tc_info(hw);
1412 }
1413
1414 static int
1415 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1416                             uint16_t nb_tx_q)
1417 {
1418         struct hns3_hw *hw = &hns->hw;
1419
1420         if (nb_rx_q < hw->num_tc) {
1421                 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).",
1422                          nb_rx_q, hw->num_tc);
1423                 return -EINVAL;
1424         }
1425
1426         if (nb_tx_q < hw->num_tc) {
1427                 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).",
1428                          nb_tx_q, hw->num_tc);
1429                 return -EINVAL;
1430         }
1431
1432         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1433 }
1434
1435 static void
1436 hns3vf_request_link_info(struct hns3_hw *hw)
1437 {
1438         uint8_t resp_msg;
1439         int ret;
1440
1441         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1442                 return;
1443         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1444                                 &resp_msg, sizeof(resp_msg));
1445         if (ret)
1446                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1447 }
1448
1449 static int
1450 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1451 {
1452 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1453         struct hns3_hw *hw = &hns->hw;
1454         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1455         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1456         uint8_t is_kill = on ? 0 : 1;
1457
1458         msg_data[0] = is_kill;
1459         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1460         memcpy(&msg_data[3], &proto, sizeof(proto));
1461
1462         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1463                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1464                                  0);
1465 }
1466
1467 static int
1468 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1469 {
1470         struct hns3_adapter *hns = dev->data->dev_private;
1471         struct hns3_hw *hw = &hns->hw;
1472         int ret;
1473
1474         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1475                 hns3_err(hw,
1476                          "vf set vlan id failed during resetting, vlan_id =%u",
1477                          vlan_id);
1478                 return -EIO;
1479         }
1480         rte_spinlock_lock(&hw->lock);
1481         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1482         rte_spinlock_unlock(&hw->lock);
1483         if (ret)
1484                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1485                          vlan_id, ret);
1486
1487         return ret;
1488 }
1489
1490 static int
1491 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1492 {
1493         uint8_t msg_data;
1494         int ret;
1495
1496         msg_data = enable ? 1 : 0;
1497         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1498                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1499         if (ret)
1500                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1501
1502         return ret;
1503 }
1504
1505 static int
1506 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1507 {
1508         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1510         unsigned int tmp_mask;
1511         int ret = 0;
1512
1513         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1514                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1515                              "mask = 0x%x", mask);
1516                 return -EIO;
1517         }
1518
1519         tmp_mask = (unsigned int)mask;
1520         /* Vlan stripping setting */
1521         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1522                 rte_spinlock_lock(&hw->lock);
1523                 /* Enable or disable VLAN stripping */
1524                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1525                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1526                 else
1527                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1528                 rte_spinlock_unlock(&hw->lock);
1529         }
1530
1531         return ret;
1532 }
1533
1534 static int
1535 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1536 {
1537         struct rte_vlan_filter_conf *vfc;
1538         struct hns3_hw *hw = &hns->hw;
1539         uint16_t vlan_id;
1540         uint64_t vbit;
1541         uint64_t ids;
1542         int ret = 0;
1543         uint32_t i;
1544
1545         vfc = &hw->data->vlan_filter_conf;
1546         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1547                 if (vfc->ids[i] == 0)
1548                         continue;
1549                 ids = vfc->ids[i];
1550                 while (ids) {
1551                         /*
1552                          * 64 means the num bits of ids, one bit corresponds to
1553                          * one vlan id
1554                          */
1555                         vlan_id = 64 * i;
1556                         /* count trailing zeroes */
1557                         vbit = ~ids & (ids - 1);
1558                         /* clear least significant bit set */
1559                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1560                         for (; vbit;) {
1561                                 vbit >>= 1;
1562                                 vlan_id++;
1563                         }
1564                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1565                         if (ret) {
1566                                 hns3_err(hw,
1567                                          "VF handle vlan table failed, ret =%d, on = %d",
1568                                          ret, on);
1569                                 return ret;
1570                         }
1571                 }
1572         }
1573
1574         return ret;
1575 }
1576
1577 static int
1578 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1579 {
1580         return hns3vf_handle_all_vlan_table(hns, 0);
1581 }
1582
1583 static int
1584 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1585 {
1586         struct hns3_hw *hw = &hns->hw;
1587         struct rte_eth_conf *dev_conf;
1588         bool en;
1589         int ret;
1590
1591         dev_conf = &hw->data->dev_conf;
1592         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1593                                                                    : false;
1594         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1595         if (ret)
1596                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1597                          ret);
1598         return ret;
1599 }
1600
1601 static int
1602 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1603 {
1604         struct hns3_adapter *hns = dev->data->dev_private;
1605         struct rte_eth_dev_data *data = dev->data;
1606         struct hns3_hw *hw = &hns->hw;
1607         int ret;
1608
1609         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1610             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1611             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1612                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1613                               "or hw_vlan_insert_pvid is not support!");
1614         }
1615
1616         /* Apply vlan offload setting */
1617         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1618         if (ret)
1619                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1620
1621         return ret;
1622 }
1623
1624 static int
1625 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1626 {
1627         uint8_t msg_data;
1628
1629         msg_data = alive ? 1 : 0;
1630         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1631                                  sizeof(msg_data), false, NULL, 0);
1632 }
1633
1634 static void
1635 hns3vf_keep_alive_handler(void *param)
1636 {
1637         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1638         struct hns3_adapter *hns = eth_dev->data->dev_private;
1639         struct hns3_hw *hw = &hns->hw;
1640         uint8_t respmsg;
1641         int ret;
1642
1643         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1644                                 false, &respmsg, sizeof(uint8_t));
1645         if (ret)
1646                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1647                          ret);
1648
1649         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1650                           eth_dev);
1651 }
1652
1653 static void
1654 hns3vf_service_handler(void *param)
1655 {
1656         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1657         struct hns3_adapter *hns = eth_dev->data->dev_private;
1658         struct hns3_hw *hw = &hns->hw;
1659
1660         /*
1661          * The query link status and reset processing are executed in the
1662          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1663          * and the query operation will time out after 30ms. In the case of
1664          * multiple PF/VFs, each query failure timeout causes the IMP reset
1665          * interrupt to fail to respond within 100ms.
1666          * Before querying the link status, check whether there is a reset
1667          * pending, and if so, abandon the query.
1668          */
1669         if (!hns3vf_is_reset_pending(hns))
1670                 hns3vf_request_link_info(hw);
1671         else
1672                 hns3_warn(hw, "Cancel the query when reset is pending");
1673
1674         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1675                           eth_dev);
1676 }
1677
1678 static int
1679 hns3_query_vf_resource(struct hns3_hw *hw)
1680 {
1681         struct hns3_vf_res_cmd *req;
1682         struct hns3_cmd_desc desc;
1683         uint16_t num_msi;
1684         int ret;
1685
1686         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1687         ret = hns3_cmd_send(hw, &desc, 1);
1688         if (ret) {
1689                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1690                 return ret;
1691         }
1692
1693         req = (struct hns3_vf_res_cmd *)desc.data;
1694         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1695                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1696         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1697                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1698                          num_msi, HNS3_MIN_VECTOR_NUM);
1699                 return -EINVAL;
1700         }
1701
1702         hw->num_msi = num_msi;
1703
1704         return 0;
1705 }
1706
1707 static int
1708 hns3vf_init_hardware(struct hns3_adapter *hns)
1709 {
1710         struct hns3_hw *hw = &hns->hw;
1711         uint16_t mtu = hw->data->mtu;
1712         int ret;
1713
1714         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1715         if (ret)
1716                 return ret;
1717
1718         ret = hns3vf_config_mtu(hw, mtu);
1719         if (ret)
1720                 goto err_init_hardware;
1721
1722         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1723         if (ret) {
1724                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1725                 goto err_init_hardware;
1726         }
1727
1728         ret = hns3_config_gro(hw, false);
1729         if (ret) {
1730                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1731                 goto err_init_hardware;
1732         }
1733
1734         /*
1735          * In the initialization clearing the all hardware mapping relationship
1736          * configurations between queues and interrupt vectors is needed, so
1737          * some error caused by the residual configurations, such as the
1738          * unexpected interrupt, can be avoid.
1739          */
1740         ret = hns3vf_init_ring_with_vector(hw);
1741         if (ret) {
1742                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1743                 goto err_init_hardware;
1744         }
1745
1746         ret = hns3vf_set_alive(hw, true);
1747         if (ret) {
1748                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1749                 goto err_init_hardware;
1750         }
1751
1752         return 0;
1753
1754 err_init_hardware:
1755         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1756         return ret;
1757 }
1758
1759 static int
1760 hns3vf_clear_vport_list(struct hns3_hw *hw)
1761 {
1762         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1763                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1764                                  NULL, 0);
1765 }
1766
1767 static int
1768 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1769 {
1770         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1771         struct hns3_adapter *hns = eth_dev->data->dev_private;
1772         struct hns3_hw *hw = &hns->hw;
1773         int ret;
1774
1775         PMD_INIT_FUNC_TRACE();
1776
1777         /* Get hardware io base address from pcie BAR2 IO space */
1778         hw->io_base = pci_dev->mem_resource[2].addr;
1779
1780         /* Firmware command queue initialize */
1781         ret = hns3_cmd_init_queue(hw);
1782         if (ret) {
1783                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1784                 goto err_cmd_init_queue;
1785         }
1786
1787         /* Firmware command initialize */
1788         ret = hns3_cmd_init(hw);
1789         if (ret) {
1790                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1791                 goto err_cmd_init;
1792         }
1793
1794         /* Get VF resource */
1795         ret = hns3_query_vf_resource(hw);
1796         if (ret)
1797                 goto err_cmd_init;
1798
1799         rte_spinlock_init(&hw->mbx_resp.lock);
1800
1801         hns3vf_clear_event_cause(hw, 0);
1802
1803         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1804                                          hns3vf_interrupt_handler, eth_dev);
1805         if (ret) {
1806                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1807                 goto err_intr_callback_register;
1808         }
1809
1810         /* Enable interrupt */
1811         rte_intr_enable(&pci_dev->intr_handle);
1812         hns3vf_enable_irq0(hw);
1813
1814         /* Get configuration from PF */
1815         ret = hns3vf_get_configuration(hw);
1816         if (ret) {
1817                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1818                 goto err_get_config;
1819         }
1820
1821         ret = hns3_tqp_stats_init(hw);
1822         if (ret)
1823                 goto err_get_config;
1824
1825         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1826         if (ret) {
1827                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1828                 goto err_set_tc_queue;
1829         }
1830
1831         ret = hns3vf_clear_vport_list(hw);
1832         if (ret) {
1833                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1834                 goto err_set_tc_queue;
1835         }
1836
1837         ret = hns3vf_init_hardware(hns);
1838         if (ret)
1839                 goto err_set_tc_queue;
1840
1841         hns3_set_default_rss_args(hw);
1842
1843         return 0;
1844
1845 err_set_tc_queue:
1846         hns3_tqp_stats_uninit(hw);
1847
1848 err_get_config:
1849         hns3vf_disable_irq0(hw);
1850         rte_intr_disable(&pci_dev->intr_handle);
1851         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1852                              eth_dev);
1853 err_intr_callback_register:
1854 err_cmd_init:
1855         hns3_cmd_uninit(hw);
1856         hns3_cmd_destroy_queue(hw);
1857 err_cmd_init_queue:
1858         hw->io_base = NULL;
1859
1860         return ret;
1861 }
1862
1863 static void
1864 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1865 {
1866         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1867         struct hns3_adapter *hns = eth_dev->data->dev_private;
1868         struct hns3_hw *hw = &hns->hw;
1869
1870         PMD_INIT_FUNC_TRACE();
1871
1872         hns3_rss_uninit(hns);
1873         (void)hns3_config_gro(hw, false);
1874         (void)hns3vf_set_alive(hw, false);
1875         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1876         hns3_tqp_stats_uninit(hw);
1877         hns3vf_disable_irq0(hw);
1878         rte_intr_disable(&pci_dev->intr_handle);
1879         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1880                              eth_dev);
1881         hns3_cmd_uninit(hw);
1882         hns3_cmd_destroy_queue(hw);
1883         hw->io_base = NULL;
1884 }
1885
1886 static int
1887 hns3vf_do_stop(struct hns3_adapter *hns)
1888 {
1889         struct hns3_hw *hw = &hns->hw;
1890         int ret;
1891
1892         hw->mac.link_status = ETH_LINK_DOWN;
1893
1894         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1895                 hns3vf_configure_mac_addr(hns, true);
1896                 ret = hns3_reset_all_tqps(hns);
1897                 if (ret) {
1898                         hns3_err(hw, "failed to reset all queues ret = %d",
1899                                  ret);
1900                         return ret;
1901                 }
1902         }
1903         return 0;
1904 }
1905
1906 static void
1907 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1908 {
1909         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1911         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1912         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1913         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1914         uint16_t q_id;
1915
1916         if (dev->data->dev_conf.intr_conf.rxq == 0)
1917                 return;
1918
1919         /* unmap the ring with vector */
1920         if (rte_intr_allow_others(intr_handle)) {
1921                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1922                 base = RTE_INTR_VEC_RXTX_OFFSET;
1923         }
1924         if (rte_intr_dp_is_en(intr_handle)) {
1925                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1926                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1927                                                            HNS3_RING_TYPE_RX,
1928                                                            q_id);
1929                         if (vec < base + intr_handle->nb_efd - 1)
1930                                 vec++;
1931                 }
1932         }
1933         /* Clean datapath event and queue/vec mapping */
1934         rte_intr_efd_disable(intr_handle);
1935         if (intr_handle->intr_vec) {
1936                 rte_free(intr_handle->intr_vec);
1937                 intr_handle->intr_vec = NULL;
1938         }
1939 }
1940
1941 static int
1942 hns3vf_dev_stop(struct rte_eth_dev *dev)
1943 {
1944         struct hns3_adapter *hns = dev->data->dev_private;
1945         struct hns3_hw *hw = &hns->hw;
1946
1947         PMD_INIT_FUNC_TRACE();
1948         dev->data->dev_started = 0;
1949
1950         hw->adapter_state = HNS3_NIC_STOPPING;
1951         hns3_set_rxtx_function(dev);
1952         rte_wmb();
1953         /* Disable datapath on secondary process. */
1954         hns3_mp_req_stop_rxtx(dev);
1955         /* Prevent crashes when queues are still in use. */
1956         rte_delay_ms(hw->tqps_num);
1957
1958         rte_spinlock_lock(&hw->lock);
1959         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1960                 hns3_stop_tqps(hw);
1961                 hns3vf_do_stop(hns);
1962                 hns3vf_unmap_rx_interrupt(dev);
1963                 hns3_dev_release_mbufs(hns);
1964                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1965         }
1966         hns3_rx_scattered_reset(dev);
1967         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1968         rte_spinlock_unlock(&hw->lock);
1969
1970         return 0;
1971 }
1972
1973 static int
1974 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1975 {
1976         struct hns3_adapter *hns = eth_dev->data->dev_private;
1977         struct hns3_hw *hw = &hns->hw;
1978         int ret = 0;
1979
1980         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1981                 return 0;
1982
1983         if (hw->adapter_state == HNS3_NIC_STARTED)
1984                 ret = hns3vf_dev_stop(eth_dev);
1985
1986         hw->adapter_state = HNS3_NIC_CLOSING;
1987         hns3_reset_abort(hns);
1988         hw->adapter_state = HNS3_NIC_CLOSED;
1989         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1990         hns3vf_configure_all_mc_mac_addr(hns, true);
1991         hns3vf_remove_all_vlan_table(hns);
1992         hns3vf_uninit_vf(eth_dev);
1993         hns3_free_all_queues(eth_dev);
1994         rte_free(hw->reset.wait_data);
1995         rte_free(eth_dev->process_private);
1996         eth_dev->process_private = NULL;
1997         hns3_mp_uninit_primary();
1998         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1999
2000         return ret;
2001 }
2002
2003 static int
2004 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2005                       size_t fw_size)
2006 {
2007         struct hns3_adapter *hns = eth_dev->data->dev_private;
2008         struct hns3_hw *hw = &hns->hw;
2009         uint32_t version = hw->fw_version;
2010         int ret;
2011
2012         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2013                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2014                                       HNS3_FW_VERSION_BYTE3_S),
2015                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2016                                       HNS3_FW_VERSION_BYTE2_S),
2017                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2018                                       HNS3_FW_VERSION_BYTE1_S),
2019                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2020                                       HNS3_FW_VERSION_BYTE0_S));
2021         ret += 1; /* add the size of '\0' */
2022         if (fw_size < (uint32_t)ret)
2023                 return ret;
2024         else
2025                 return 0;
2026 }
2027
2028 static int
2029 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2030                        __rte_unused int wait_to_complete)
2031 {
2032         struct hns3_adapter *hns = eth_dev->data->dev_private;
2033         struct hns3_hw *hw = &hns->hw;
2034         struct hns3_mac *mac = &hw->mac;
2035         struct rte_eth_link new_link;
2036
2037         memset(&new_link, 0, sizeof(new_link));
2038         switch (mac->link_speed) {
2039         case ETH_SPEED_NUM_10M:
2040         case ETH_SPEED_NUM_100M:
2041         case ETH_SPEED_NUM_1G:
2042         case ETH_SPEED_NUM_10G:
2043         case ETH_SPEED_NUM_25G:
2044         case ETH_SPEED_NUM_40G:
2045         case ETH_SPEED_NUM_50G:
2046         case ETH_SPEED_NUM_100G:
2047         case ETH_SPEED_NUM_200G:
2048                 new_link.link_speed = mac->link_speed;
2049                 break;
2050         default:
2051                 new_link.link_speed = ETH_SPEED_NUM_100M;
2052                 break;
2053         }
2054
2055         new_link.link_duplex = mac->link_duplex;
2056         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2057         new_link.link_autoneg =
2058             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2059
2060         return rte_eth_linkstatus_set(eth_dev, &new_link);
2061 }
2062
2063 static int
2064 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2065 {
2066         struct hns3_hw *hw = &hns->hw;
2067         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2068         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2069         int ret;
2070
2071         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2072         if (ret)
2073                 return ret;
2074
2075         ret = hns3_init_queues(hns, reset_queue);
2076         if (ret)
2077                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2078
2079         return ret;
2080 }
2081
2082 static int
2083 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2084 {
2085         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2086         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2087         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2089         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2090         uint32_t intr_vector;
2091         uint16_t q_id;
2092         int ret;
2093
2094         if (dev->data->dev_conf.intr_conf.rxq == 0)
2095                 return 0;
2096
2097         /* disable uio/vfio intr/eventfd mapping */
2098         rte_intr_disable(intr_handle);
2099
2100         /* check and configure queue intr-vector mapping */
2101         if (rte_intr_cap_multiple(intr_handle) ||
2102             !RTE_ETH_DEV_SRIOV(dev).active) {
2103                 intr_vector = hw->used_rx_queues;
2104                 /* It creates event fd for each intr vector when MSIX is used */
2105                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2106                         return -EINVAL;
2107         }
2108         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2109                 intr_handle->intr_vec =
2110                         rte_zmalloc("intr_vec",
2111                                     hw->used_rx_queues * sizeof(int), 0);
2112                 if (intr_handle->intr_vec == NULL) {
2113                         hns3_err(hw, "Failed to allocate %u rx_queues"
2114                                      " intr_vec", hw->used_rx_queues);
2115                         ret = -ENOMEM;
2116                         goto vf_alloc_intr_vec_error;
2117                 }
2118         }
2119
2120         if (rte_intr_allow_others(intr_handle)) {
2121                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2122                 base = RTE_INTR_VEC_RXTX_OFFSET;
2123         }
2124         if (rte_intr_dp_is_en(intr_handle)) {
2125                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2126                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2127                                                            HNS3_RING_TYPE_RX,
2128                                                            q_id);
2129                         if (ret)
2130                                 goto vf_bind_vector_error;
2131                         intr_handle->intr_vec[q_id] = vec;
2132                         if (vec < base + intr_handle->nb_efd - 1)
2133                                 vec++;
2134                 }
2135         }
2136         rte_intr_enable(intr_handle);
2137         return 0;
2138
2139 vf_bind_vector_error:
2140         rte_intr_efd_disable(intr_handle);
2141         if (intr_handle->intr_vec) {
2142                 free(intr_handle->intr_vec);
2143                 intr_handle->intr_vec = NULL;
2144         }
2145         return ret;
2146 vf_alloc_intr_vec_error:
2147         rte_intr_efd_disable(intr_handle);
2148         return ret;
2149 }
2150
2151 static int
2152 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2153 {
2154         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2155         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2156         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2157         uint16_t q_id;
2158         int ret;
2159
2160         if (dev->data->dev_conf.intr_conf.rxq == 0)
2161                 return 0;
2162
2163         if (rte_intr_dp_is_en(intr_handle)) {
2164                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2165                         ret = hns3vf_bind_ring_with_vector(hw,
2166                                         intr_handle->intr_vec[q_id], true,
2167                                         HNS3_RING_TYPE_RX, q_id);
2168                         if (ret)
2169                                 return ret;
2170                 }
2171         }
2172
2173         return 0;
2174 }
2175
2176 static void
2177 hns3vf_restore_filter(struct rte_eth_dev *dev)
2178 {
2179         hns3_restore_rss_filter(dev);
2180 }
2181
2182 static int
2183 hns3vf_dev_start(struct rte_eth_dev *dev)
2184 {
2185         struct hns3_adapter *hns = dev->data->dev_private;
2186         struct hns3_hw *hw = &hns->hw;
2187         int ret;
2188
2189         PMD_INIT_FUNC_TRACE();
2190         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2191                 return -EBUSY;
2192
2193         rte_spinlock_lock(&hw->lock);
2194         hw->adapter_state = HNS3_NIC_STARTING;
2195         ret = hns3vf_do_start(hns, true);
2196         if (ret) {
2197                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2198                 rte_spinlock_unlock(&hw->lock);
2199                 return ret;
2200         }
2201         ret = hns3vf_map_rx_interrupt(dev);
2202         if (ret) {
2203                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2204                 rte_spinlock_unlock(&hw->lock);
2205                 return ret;
2206         }
2207
2208         /*
2209          * There are three register used to control the status of a TQP
2210          * (contains a pair of Tx queue and Rx queue) in the new version network
2211          * engine. One is used to control the enabling of Tx queue, the other is
2212          * used to control the enabling of Rx queue, and the last is the master
2213          * switch used to control the enabling of the tqp. The Tx register and
2214          * TQP register must be enabled at the same time to enable a Tx queue.
2215          * The same applies to the Rx queue. For the older network enginem, this
2216          * function only refresh the enabled flag, and it is used to update the
2217          * status of queue in the dpdk framework.
2218          */
2219         ret = hns3_start_all_txqs(dev);
2220         if (ret) {
2221                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2222                 rte_spinlock_unlock(&hw->lock);
2223                 return ret;
2224         }
2225
2226         ret = hns3_start_all_rxqs(dev);
2227         if (ret) {
2228                 hns3_stop_all_txqs(dev);
2229                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2230                 rte_spinlock_unlock(&hw->lock);
2231                 return ret;
2232         }
2233
2234         hw->adapter_state = HNS3_NIC_STARTED;
2235         rte_spinlock_unlock(&hw->lock);
2236
2237         hns3_rx_scattered_calc(dev);
2238         hns3_set_rxtx_function(dev);
2239         hns3_mp_req_start_rxtx(dev);
2240         hns3vf_service_handler(dev);
2241
2242         hns3vf_restore_filter(dev);
2243
2244         /* Enable interrupt of all rx queues before enabling queues */
2245         hns3_dev_all_rx_queue_intr_enable(hw, true);
2246
2247         /*
2248          * After finished the initialization, start all tqps to receive/transmit
2249          * packets and refresh all queue status.
2250          */
2251         hns3_start_tqps(hw);
2252
2253         return ret;
2254 }
2255
2256 static bool
2257 is_vf_reset_done(struct hns3_hw *hw)
2258 {
2259 #define HNS3_FUN_RST_ING_BITS \
2260         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2261          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2262          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2263          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2264
2265         uint32_t val;
2266
2267         if (hw->reset.level == HNS3_VF_RESET) {
2268                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2269                 if (val & HNS3_VF_RST_ING_BIT)
2270                         return false;
2271         } else {
2272                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2273                 if (val & HNS3_FUN_RST_ING_BITS)
2274                         return false;
2275         }
2276         return true;
2277 }
2278
2279 bool
2280 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2281 {
2282         struct hns3_hw *hw = &hns->hw;
2283         enum hns3_reset_level reset;
2284
2285         /*
2286          * According to the protocol of PCIe, FLR to a PF device resets the PF
2287          * state as well as the SR-IOV extended capability including VF Enable
2288          * which means that VFs no longer exist.
2289          *
2290          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2291          * is in FLR stage, the register state of VF device is not reliable,
2292          * so register states detection can not be carried out. In this case,
2293          * we just ignore the register states and return false to indicate that
2294          * there are no other reset states that need to be processed by driver.
2295          */
2296         if (hw->reset.level == HNS3_VF_FULL_RESET)
2297                 return false;
2298
2299         /* Check the registers to confirm whether there is reset pending */
2300         hns3vf_check_event_cause(hns, NULL);
2301         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2302         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2303                 hns3_warn(hw, "High level reset %d is pending", reset);
2304                 return true;
2305         }
2306         return false;
2307 }
2308
2309 static int
2310 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2311 {
2312         struct hns3_hw *hw = &hns->hw;
2313         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2314         struct timeval tv;
2315
2316         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2317                 /*
2318                  * After vf reset is ready, the PF may not have completed
2319                  * the reset processing. The vf sending mbox to PF may fail
2320                  * during the pf reset, so it is better to add extra delay.
2321                  */
2322                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2323                     hw->reset.level == HNS3_FLR_RESET)
2324                         return 0;
2325                 /* Reset retry process, no need to add extra delay. */
2326                 if (hw->reset.attempts)
2327                         return 0;
2328                 if (wait_data->check_completion == NULL)
2329                         return 0;
2330
2331                 wait_data->check_completion = NULL;
2332                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2333                 wait_data->count = 1;
2334                 wait_data->result = HNS3_WAIT_REQUEST;
2335                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2336                                   wait_data);
2337                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2338                 return -EAGAIN;
2339         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2340                 gettimeofday(&tv, NULL);
2341                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2342                           tv.tv_sec, tv.tv_usec);
2343                 return -ETIME;
2344         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2345                 return -EAGAIN;
2346
2347         wait_data->hns = hns;
2348         wait_data->check_completion = is_vf_reset_done;
2349         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2350                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2351         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2352         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2353         wait_data->result = HNS3_WAIT_REQUEST;
2354         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2355         return -EAGAIN;
2356 }
2357
2358 static int
2359 hns3vf_prepare_reset(struct hns3_adapter *hns)
2360 {
2361         struct hns3_hw *hw = &hns->hw;
2362         int ret = 0;
2363
2364         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2365                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2366                                         0, true, NULL, 0);
2367         }
2368         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2369
2370         return ret;
2371 }
2372
2373 static int
2374 hns3vf_stop_service(struct hns3_adapter *hns)
2375 {
2376         struct hns3_hw *hw = &hns->hw;
2377         struct rte_eth_dev *eth_dev;
2378
2379         eth_dev = &rte_eth_devices[hw->data->port_id];
2380         if (hw->adapter_state == HNS3_NIC_STARTED)
2381                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2382         hw->mac.link_status = ETH_LINK_DOWN;
2383
2384         hns3_set_rxtx_function(eth_dev);
2385         rte_wmb();
2386         /* Disable datapath on secondary process. */
2387         hns3_mp_req_stop_rxtx(eth_dev);
2388         rte_delay_ms(hw->tqps_num);
2389
2390         rte_spinlock_lock(&hw->lock);
2391         if (hw->adapter_state == HNS3_NIC_STARTED ||
2392             hw->adapter_state == HNS3_NIC_STOPPING) {
2393                 hns3_enable_all_queues(hw, false);
2394                 hns3vf_do_stop(hns);
2395                 hw->reset.mbuf_deferred_free = true;
2396         } else
2397                 hw->reset.mbuf_deferred_free = false;
2398
2399         /*
2400          * It is cumbersome for hardware to pick-and-choose entries for deletion
2401          * from table space. Hence, for function reset software intervention is
2402          * required to delete the entries.
2403          */
2404         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2405                 hns3vf_configure_all_mc_mac_addr(hns, true);
2406         rte_spinlock_unlock(&hw->lock);
2407
2408         return 0;
2409 }
2410
2411 static int
2412 hns3vf_start_service(struct hns3_adapter *hns)
2413 {
2414         struct hns3_hw *hw = &hns->hw;
2415         struct rte_eth_dev *eth_dev;
2416
2417         eth_dev = &rte_eth_devices[hw->data->port_id];
2418         hns3_set_rxtx_function(eth_dev);
2419         hns3_mp_req_start_rxtx(eth_dev);
2420         if (hw->adapter_state == HNS3_NIC_STARTED) {
2421                 hns3vf_service_handler(eth_dev);
2422
2423                 /* Enable interrupt of all rx queues before enabling queues */
2424                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2425                 /*
2426                  * Enable state of each rxq and txq will be recovered after
2427                  * reset, so we need to restore them before enable all tqps;
2428                  */
2429                 hns3_restore_tqp_enable_state(hw);
2430                 /*
2431                  * When finished the initialization, enable queues to receive
2432                  * and transmit packets.
2433                  */
2434                 hns3_enable_all_queues(hw, true);
2435         }
2436
2437         return 0;
2438 }
2439
2440 static int
2441 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2442 {
2443         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2444         struct rte_ether_addr *hw_mac;
2445         int ret;
2446
2447         /*
2448          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2449          * on the host by "ip link set ..." command. If the hns3 PF kernel
2450          * ethdev driver sets the MAC address for VF device after the
2451          * initialization of the related VF device, the PF driver will notify
2452          * VF driver to reset VF device to make the new MAC address effective
2453          * immediately. The hns3 VF PMD driver should check whether the MAC
2454          * address has been changed by the PF kernel ethdev driver, if changed
2455          * VF driver should configure hardware using the new MAC address in the
2456          * recovering hardware configuration stage of the reset process.
2457          */
2458         ret = hns3vf_get_host_mac_addr(hw);
2459         if (ret)
2460                 return ret;
2461
2462         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2463         ret = rte_is_zero_ether_addr(hw_mac);
2464         if (ret) {
2465                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2466         } else {
2467                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2468                 if (!ret) {
2469                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2470                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2471                                               &hw->data->mac_addrs[0]);
2472                         hns3_warn(hw, "Default MAC address has been changed to:"
2473                                   " %s by the host PF kernel ethdev driver",
2474                                   mac_str);
2475                 }
2476         }
2477
2478         return 0;
2479 }
2480
2481 static int
2482 hns3vf_restore_conf(struct hns3_adapter *hns)
2483 {
2484         struct hns3_hw *hw = &hns->hw;
2485         int ret;
2486
2487         ret = hns3vf_check_default_mac_change(hw);
2488         if (ret)
2489                 return ret;
2490
2491         ret = hns3vf_configure_mac_addr(hns, false);
2492         if (ret)
2493                 return ret;
2494
2495         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2496         if (ret)
2497                 goto err_mc_mac;
2498
2499         ret = hns3vf_restore_promisc(hns);
2500         if (ret)
2501                 goto err_vlan_table;
2502
2503         ret = hns3vf_restore_vlan_conf(hns);
2504         if (ret)
2505                 goto err_vlan_table;
2506
2507         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2508         if (ret)
2509                 goto err_vlan_table;
2510
2511         ret = hns3vf_restore_rx_interrupt(hw);
2512         if (ret)
2513                 goto err_vlan_table;
2514
2515         ret = hns3_restore_gro_conf(hw);
2516         if (ret)
2517                 goto err_vlan_table;
2518
2519         if (hw->adapter_state == HNS3_NIC_STARTED) {
2520                 ret = hns3vf_do_start(hns, false);
2521                 if (ret)
2522                         goto err_vlan_table;
2523                 hns3_info(hw, "hns3vf dev restart successful!");
2524         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2525                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2526         return 0;
2527
2528 err_vlan_table:
2529         hns3vf_configure_all_mc_mac_addr(hns, true);
2530 err_mc_mac:
2531         hns3vf_configure_mac_addr(hns, true);
2532         return ret;
2533 }
2534
2535 static enum hns3_reset_level
2536 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2537 {
2538         enum hns3_reset_level reset_level;
2539
2540         /* return the highest priority reset level amongst all */
2541         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2542                 reset_level = HNS3_VF_RESET;
2543         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2544                 reset_level = HNS3_VF_FULL_RESET;
2545         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2546                 reset_level = HNS3_VF_PF_FUNC_RESET;
2547         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2548                 reset_level = HNS3_VF_FUNC_RESET;
2549         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2550                 reset_level = HNS3_FLR_RESET;
2551         else
2552                 reset_level = HNS3_NONE_RESET;
2553
2554         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2555                 return HNS3_NONE_RESET;
2556
2557         return reset_level;
2558 }
2559
2560 static void
2561 hns3vf_reset_service(void *param)
2562 {
2563         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2564         struct hns3_hw *hw = &hns->hw;
2565         enum hns3_reset_level reset_level;
2566         struct timeval tv_delta;
2567         struct timeval tv_start;
2568         struct timeval tv;
2569         uint64_t msec;
2570
2571         /*
2572          * The interrupt is not triggered within the delay time.
2573          * The interrupt may have been lost. It is necessary to handle
2574          * the interrupt to recover from the error.
2575          */
2576         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2577                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2578                 hns3_err(hw, "Handling interrupts in delayed tasks");
2579                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2580                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2581                 if (reset_level == HNS3_NONE_RESET) {
2582                         hns3_err(hw, "No reset level is set, try global reset");
2583                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2584                 }
2585         }
2586         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2587
2588         /*
2589          * Hardware reset has been notified, we now have to poll & check if
2590          * hardware has actually completed the reset sequence.
2591          */
2592         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2593         if (reset_level != HNS3_NONE_RESET) {
2594                 gettimeofday(&tv_start, NULL);
2595                 hns3_reset_process(hns, reset_level);
2596                 gettimeofday(&tv, NULL);
2597                 timersub(&tv, &tv_start, &tv_delta);
2598                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2599                        tv_delta.tv_usec / USEC_PER_MSEC;
2600                 if (msec > HNS3_RESET_PROCESS_MS)
2601                         hns3_err(hw, "%d handle long time delta %" PRIx64
2602                                  " ms time=%ld.%.6ld",
2603                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2604         }
2605 }
2606
2607 static int
2608 hns3vf_reinit_dev(struct hns3_adapter *hns)
2609 {
2610         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2611         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2612         struct hns3_hw *hw = &hns->hw;
2613         int ret;
2614
2615         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2616                 rte_intr_disable(&pci_dev->intr_handle);
2617                 ret = hns3vf_set_bus_master(pci_dev, true);
2618                 if (ret < 0) {
2619                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2620                         return ret;
2621                 }
2622         }
2623
2624         /* Firmware command initialize */
2625         ret = hns3_cmd_init(hw);
2626         if (ret) {
2627                 hns3_err(hw, "Failed to init cmd: %d", ret);
2628                 return ret;
2629         }
2630
2631         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2632                 /*
2633                  * UIO enables msix by writing the pcie configuration space
2634                  * vfio_pci enables msix in rte_intr_enable.
2635                  */
2636                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2637                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2638                         if (hns3vf_enable_msix(pci_dev, true))
2639                                 hns3_err(hw, "Failed to enable msix");
2640                 }
2641
2642                 rte_intr_enable(&pci_dev->intr_handle);
2643         }
2644
2645         ret = hns3_reset_all_tqps(hns);
2646         if (ret) {
2647                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2648                 return ret;
2649         }
2650
2651         ret = hns3vf_init_hardware(hns);
2652         if (ret) {
2653                 hns3_err(hw, "Failed to init hardware: %d", ret);
2654                 return ret;
2655         }
2656
2657         return 0;
2658 }
2659
2660 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2661         .dev_configure      = hns3vf_dev_configure,
2662         .dev_start          = hns3vf_dev_start,
2663         .dev_stop           = hns3vf_dev_stop,
2664         .dev_close          = hns3vf_dev_close,
2665         .mtu_set            = hns3vf_dev_mtu_set,
2666         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2667         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2668         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2669         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2670         .stats_get          = hns3_stats_get,
2671         .stats_reset        = hns3_stats_reset,
2672         .xstats_get         = hns3_dev_xstats_get,
2673         .xstats_get_names   = hns3_dev_xstats_get_names,
2674         .xstats_reset       = hns3_dev_xstats_reset,
2675         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2676         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2677         .dev_infos_get      = hns3vf_dev_infos_get,
2678         .fw_version_get     = hns3vf_fw_version_get,
2679         .rx_queue_setup     = hns3_rx_queue_setup,
2680         .tx_queue_setup     = hns3_tx_queue_setup,
2681         .rx_queue_release   = hns3_dev_rx_queue_release,
2682         .tx_queue_release   = hns3_dev_tx_queue_release,
2683         .rx_queue_start     = hns3_dev_rx_queue_start,
2684         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2685         .tx_queue_start     = hns3_dev_tx_queue_start,
2686         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2687         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2688         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2689         .rxq_info_get       = hns3_rxq_info_get,
2690         .txq_info_get       = hns3_txq_info_get,
2691         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2692         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2693         .mac_addr_add       = hns3vf_add_mac_addr,
2694         .mac_addr_remove    = hns3vf_remove_mac_addr,
2695         .mac_addr_set       = hns3vf_set_default_mac_addr,
2696         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2697         .link_update        = hns3vf_dev_link_update,
2698         .rss_hash_update    = hns3_dev_rss_hash_update,
2699         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2700         .reta_update        = hns3_dev_rss_reta_update,
2701         .reta_query         = hns3_dev_rss_reta_query,
2702         .filter_ctrl        = hns3_dev_filter_ctrl,
2703         .vlan_filter_set    = hns3vf_vlan_filter_set,
2704         .vlan_offload_set   = hns3vf_vlan_offload_set,
2705         .get_reg            = hns3_get_regs,
2706         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2707 };
2708
2709 static const struct hns3_reset_ops hns3vf_reset_ops = {
2710         .reset_service       = hns3vf_reset_service,
2711         .stop_service        = hns3vf_stop_service,
2712         .prepare_reset       = hns3vf_prepare_reset,
2713         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2714         .reinit_dev          = hns3vf_reinit_dev,
2715         .restore_conf        = hns3vf_restore_conf,
2716         .start_service       = hns3vf_start_service,
2717 };
2718
2719 static int
2720 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2721 {
2722         struct hns3_adapter *hns = eth_dev->data->dev_private;
2723         struct hns3_hw *hw = &hns->hw;
2724         int ret;
2725
2726         PMD_INIT_FUNC_TRACE();
2727
2728         eth_dev->process_private = (struct hns3_process_private *)
2729             rte_zmalloc_socket("hns3_filter_list",
2730                                sizeof(struct hns3_process_private),
2731                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2732         if (eth_dev->process_private == NULL) {
2733                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2734                 return -ENOMEM;
2735         }
2736
2737         /* initialize flow filter lists */
2738         hns3_filterlist_init(eth_dev);
2739
2740         hns3_set_rxtx_function(eth_dev);
2741         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2742         eth_dev->rx_queue_count = hns3_rx_queue_count;
2743         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2744                 ret = hns3_mp_init_secondary();
2745                 if (ret) {
2746                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2747                                           "process, ret = %d", ret);
2748                         goto err_mp_init_secondary;
2749                 }
2750
2751                 hw->secondary_cnt++;
2752                 return 0;
2753         }
2754
2755         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2756
2757         ret = hns3_mp_init_primary();
2758         if (ret) {
2759                 PMD_INIT_LOG(ERR,
2760                              "Failed to init for primary process, ret = %d",
2761                              ret);
2762                 goto err_mp_init_primary;
2763         }
2764
2765         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2766         hns->is_vf = true;
2767         hw->data = eth_dev->data;
2768
2769         ret = hns3_reset_init(hw);
2770         if (ret)
2771                 goto err_init_reset;
2772         hw->reset.ops = &hns3vf_reset_ops;
2773
2774         ret = hns3vf_init_vf(eth_dev);
2775         if (ret) {
2776                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2777                 goto err_init_vf;
2778         }
2779
2780         /* Allocate memory for storing MAC addresses */
2781         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2782                                                sizeof(struct rte_ether_addr) *
2783                                                HNS3_VF_UC_MACADDR_NUM, 0);
2784         if (eth_dev->data->mac_addrs == NULL) {
2785                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2786                              "to store MAC addresses",
2787                              sizeof(struct rte_ether_addr) *
2788                              HNS3_VF_UC_MACADDR_NUM);
2789                 ret = -ENOMEM;
2790                 goto err_rte_zmalloc;
2791         }
2792
2793         /*
2794          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2795          * on the host by "ip link set ..." command. To avoid some incorrect
2796          * scenes, for example, hns3 VF PMD driver fails to receive and send
2797          * packets after user configure the MAC address by using the
2798          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2799          * address strategy as the hns3 kernel ethdev driver in the
2800          * initialization. If user configure a MAC address by the ip command
2801          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2802          * start with a random MAC address in the initialization.
2803          */
2804         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2805                 rte_eth_random_addr(hw->mac.mac_addr);
2806         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2807                             &eth_dev->data->mac_addrs[0]);
2808
2809         hw->adapter_state = HNS3_NIC_INITIALIZED;
2810
2811         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2812                 hns3_err(hw, "Reschedule reset service after dev_init");
2813                 hns3_schedule_reset(hns);
2814         } else {
2815                 /* IMP will wait ready flag before reset */
2816                 hns3_notify_reset_ready(hw, false);
2817         }
2818         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2819                           eth_dev);
2820         return 0;
2821
2822 err_rte_zmalloc:
2823         hns3vf_uninit_vf(eth_dev);
2824
2825 err_init_vf:
2826         rte_free(hw->reset.wait_data);
2827
2828 err_init_reset:
2829         hns3_mp_uninit_primary();
2830
2831 err_mp_init_primary:
2832 err_mp_init_secondary:
2833         eth_dev->dev_ops = NULL;
2834         eth_dev->rx_pkt_burst = NULL;
2835         eth_dev->tx_pkt_burst = NULL;
2836         eth_dev->tx_pkt_prepare = NULL;
2837         rte_free(eth_dev->process_private);
2838         eth_dev->process_private = NULL;
2839
2840         return ret;
2841 }
2842
2843 static int
2844 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2845 {
2846         struct hns3_adapter *hns = eth_dev->data->dev_private;
2847         struct hns3_hw *hw = &hns->hw;
2848
2849         PMD_INIT_FUNC_TRACE();
2850
2851         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2852                 return -EPERM;
2853
2854         if (hw->adapter_state < HNS3_NIC_CLOSING)
2855                 hns3vf_dev_close(eth_dev);
2856
2857         hw->adapter_state = HNS3_NIC_REMOVED;
2858         return 0;
2859 }
2860
2861 static int
2862 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2863                      struct rte_pci_device *pci_dev)
2864 {
2865         return rte_eth_dev_pci_generic_probe(pci_dev,
2866                                              sizeof(struct hns3_adapter),
2867                                              hns3vf_dev_init);
2868 }
2869
2870 static int
2871 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2872 {
2873         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2874 }
2875
2876 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2877         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2878         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2879         { .vendor_id = 0, }, /* sentinel */
2880 };
2881
2882 static struct rte_pci_driver rte_hns3vf_pmd = {
2883         .id_table = pci_id_hns3vf_map,
2884         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2885         .probe = eth_hns3vf_pci_probe,
2886         .remove = eth_hns3vf_pci_remove,
2887 };
2888
2889 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2890 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2891 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");