drivers/net/hns3/hns3_intr.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <stdbool.h>
   6 #include <rte_atomic.h>
   7 #include <rte_alarm.h>
   8 #include <rte_cycles.h>
   9 #include <rte_ethdev.h>
  10 #include <rte_io.h>
  11 #include <rte_malloc.h>
  12 #include <rte_pci.h>
  13 #include <rte_bus_pci.h>
  14
  15 #include "hns3_ethdev.h"
  16 #include "hns3_logs.h"
  17 #include "hns3_intr.h"
  18 #include "hns3_regs.h"
  19 #include "hns3_rxtx.h"
  20
  21 #define SWITCH_CONTEXT_US       10
  22
  23 /* offset in MSIX bd */
  24 #define MAC_ERROR_OFFSET        1
  25 #define PPP_PF_ERROR_OFFSET     2
  26 #define PPU_PF_ERROR_OFFSET     3
  27 #define RCB_ERROR_OFFSET        5
  28 #define RCB_ERROR_STATUS_OFFSET 2
  29
  30 #define HNS3_CHECK_MERGE_CNT(val)                       \
  31         do {                                            \
  32                 if (val)                                \
  33                         hw->reset.stats.merge_cnt++;    \
  34         } while (0)
  35
  36 static const char *reset_string[HNS3_MAX_RESET] = {
  37         "none", "vf_func", "vf_pf_func", "vf_full", "flr",
  38         "vf_global", "pf_func", "global", "IMP",
  39 };
  40
  41 const struct hns3_hw_error mac_afifo_tnl_int[] = {
  42         { .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err",
  43           .reset_level = HNS3_NONE_RESET },
  44         { .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err",
  45           .reset_level = HNS3_GLOBAL_RESET },
  46         { .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err",
  47           .reset_level = HNS3_NONE_RESET },
  48         { .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err",
  49           .reset_level = HNS3_GLOBAL_RESET },
  50         { .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err",
  51           .reset_level = HNS3_NONE_RESET },
  52         { .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err",
  53           .reset_level = HNS3_GLOBAL_RESET },
  54         { .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err",
  55           .reset_level = HNS3_NONE_RESET },
  56         { .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err",
  57           .reset_level = HNS3_GLOBAL_RESET },
  58         { .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err",
  59           .reset_level = HNS3_GLOBAL_RESET },
  60         { .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err",
  61           .reset_level = HNS3_GLOBAL_RESET },
  62         { .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err",
  63           .reset_level = HNS3_GLOBAL_RESET },
  64         { .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err",
  65           .reset_level = HNS3_GLOBAL_RESET },
  66         { .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err",
  67           .reset_level = HNS3_GLOBAL_RESET },
  68         { .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err",
  69           .reset_level = HNS3_GLOBAL_RESET },
  70         { .int_msk = 0, .msg = NULL,
  71           .reset_level = HNS3_NONE_RESET}
  72 };
  73
  74 const struct hns3_hw_error ppu_mpf_abnormal_int_st2[] = {
  75         { .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
  76           .reset_level = HNS3_GLOBAL_RESET },
  77         { .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
  78           .reset_level = HNS3_GLOBAL_RESET },
  79         { .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
  80           .reset_level = HNS3_GLOBAL_RESET },
  81         { .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
  82           .reset_level = HNS3_GLOBAL_RESET },
  83         { .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err",
  84           .reset_level = HNS3_GLOBAL_RESET },
  85         { .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err",
  86           .reset_level = HNS3_GLOBAL_RESET },
  87         { .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err",
  88           .reset_level = HNS3_GLOBAL_RESET },
  89         { .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err",
  90           .reset_level = HNS3_GLOBAL_RESET },
  91         { .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err",
  92           .reset_level = HNS3_GLOBAL_RESET },
  93         { .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err",
  94           .reset_level = HNS3_GLOBAL_RESET },
  95         { .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err",
  96           .reset_level = HNS3_GLOBAL_RESET },
  97         { .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err",
  98           .reset_level = HNS3_GLOBAL_RESET },
  99         { .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err",
 100           .reset_level = HNS3_GLOBAL_RESET },
 101         { .int_msk = BIT(26), .msg = "rd_bus_err",
 102           .reset_level = HNS3_GLOBAL_RESET },
 103         { .int_msk = BIT(27), .msg = "wr_bus_err",
 104           .reset_level = HNS3_GLOBAL_RESET },
 105         { .int_msk = BIT(28), .msg = "reg_search_miss",
 106           .reset_level = HNS3_GLOBAL_RESET },
 107         { .int_msk = BIT(29), .msg = "rx_q_search_miss",
 108           .reset_level = HNS3_NONE_RESET },
 109         { .int_msk = BIT(30), .msg = "ooo_ecc_err_detect",
 110           .reset_level = HNS3_NONE_RESET },
 111         { .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl",
 112           .reset_level = HNS3_GLOBAL_RESET },
 113         { .int_msk = 0, .msg = NULL,
 114           .reset_level = HNS3_NONE_RESET}
 115 };
 116
 117 const struct hns3_hw_error ssu_port_based_pf_int[] = {
 118         { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
 119           .reset_level = HNS3_GLOBAL_RESET },
 120         { .int_msk = BIT(9), .msg = "low_water_line_err_port",
 121           .reset_level = HNS3_NONE_RESET },
 122         { .int_msk = BIT(10), .msg = "hi_water_line_err_port",
 123           .reset_level = HNS3_GLOBAL_RESET },
 124         { .int_msk = 0, .msg = NULL,
 125           .reset_level = HNS3_NONE_RESET}
 126 };
 127
 128 const struct hns3_hw_error ppp_pf_abnormal_int[] = {
 129         { .int_msk = BIT(0), .msg = "tx_vlan_tag_err",
 130           .reset_level = HNS3_NONE_RESET },
 131         { .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err",
 132           .reset_level = HNS3_NONE_RESET },
 133         { .int_msk = 0, .msg = NULL,
 134           .reset_level = HNS3_NONE_RESET}
 135 };
 136
 137 const struct hns3_hw_error ppu_pf_abnormal_int[] = {
 138         { .int_msk = BIT(0), .msg = "over_8bd_no_fe",
 139           .reset_level = HNS3_FUNC_RESET },
 140         { .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err",
 141           .reset_level = HNS3_NONE_RESET },
 142         { .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err",
 143           .reset_level = HNS3_NONE_RESET },
 144         { .int_msk = BIT(3), .msg = "tx_rd_fbd_poison",
 145           .reset_level = HNS3_FUNC_RESET },
 146         { .int_msk = BIT(4), .msg = "rx_rd_ebd_poison",
 147           .reset_level = HNS3_FUNC_RESET },
 148         { .int_msk = BIT(5), .msg = "buf_wait_timeout",
 149           .reset_level = HNS3_NONE_RESET },
 150         { .int_msk = 0, .msg = NULL,
 151           .reset_level = HNS3_NONE_RESET}
 152 };
 153
 154 static int
 155 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)
 156 {
 157         struct hns3_hw *hw = &hns->hw;
 158         struct hns3_cmd_desc desc[2];
 159         int ret;
 160
 161         /* configure PPP error interrupts */
 162         hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
 163         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 164         hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
 165
 166         if (cmd == HNS3_PPP_CMD0_INT_CMD) {
 167                 if (en) {
 168                         desc[0].data[0] =
 169                                 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);
 170                         desc[0].data[1] =
 171                                 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);
 172                         desc[0].data[4] =
 173                                 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);
 174                 }
 175
 176                 desc[1].data[0] =
 177                         rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);
 178                 desc[1].data[1] =
 179                         rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);
 180                 desc[1].data[2] =
 181                         rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);
 182         } else if (cmd == HNS3_PPP_CMD1_INT_CMD) {
 183                 if (en) {
 184                         desc[0].data[0] =
 185                                 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);
 186                         desc[0].data[1] =
 187                                 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);
 188                 }
 189
 190                 desc[1].data[0] =
 191                         rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);
 192                 desc[1].data[1] =
 193                         rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);
 194         }
 195
 196         ret = hns3_cmd_send(hw, &desc[0], 2);
 197         if (ret)
 198                 hns3_err(hw, "fail to configure PPP error int: %d", ret);
 199
 200         return ret;
 201 }
 202
 203 static int
 204 enable_ppp_err_intr(struct hns3_adapter *hns, bool en)
 205 {
 206         int ret;
 207
 208         ret = config_ppp_err_intr(hns, HNS3_PPP_CMD0_INT_CMD, en);
 209         if (ret)
 210                 return ret;
 211
 212         return config_ppp_err_intr(hns, HNS3_PPP_CMD1_INT_CMD, en);
 213 }
 214
 215 static int
 216 enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
 217 {
 218         struct hns3_hw *hw = &hns->hw;
 219         struct hns3_cmd_desc desc[2];
 220         int ret;
 221
 222         /* configure SSU ecc error interrupts */
 223         hns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_ECC_INT_CMD, false);
 224         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 225         hns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_ECC_INT_CMD, false);
 226         if (en) {
 227                 desc[0].data[0] =
 228                         rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);
 229                 desc[0].data[1] =
 230                         rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);
 231                 desc[0].data[4] =
 232                         rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);
 233         }
 234
 235         desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);
 236         desc[1].data[1] =
 237                 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
 238         desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);
 239
 240         ret = hns3_cmd_send(hw, &desc[0], 2);
 241         if (ret) {
 242                 hns3_err(hw, "fail to configure SSU ECC error interrupt: %d",
 243                          ret);
 244                 return ret;
 245         }
 246
 247         /* configure SSU common error interrupts */
 248         hns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_COMMON_INT_CMD, false);
 249         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 250         hns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_COMMON_INT_CMD, false);
 251
 252         if (en) {
 253                 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);
 254                 desc[0].data[1] =
 255                         rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN);
 256                 desc[0].data[2] =
 257                         rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN);
 258         }
 259
 260         desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK |
 261                                            HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK);
 262         desc[1].data[1] =
 263                 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
 264
 265         ret = hns3_cmd_send(hw, &desc[0], 2);
 266         if (ret)
 267                 hns3_err(hw, "fail to configure SSU COMMON error intr: %d",
 268                          ret);
 269
 270         return ret;
 271 }
 272
 273 static int
 274 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)
 275 {
 276         struct hns3_hw *hw = &hns->hw;
 277         struct hns3_cmd_desc desc[2];
 278         int num = 1;
 279
 280         /* configure PPU error interrupts */
 281         switch (cmd) {
 282         case HNS3_PPU_MPF_ECC_INT_CMD:
 283                 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
 284                 desc[0].flag |= HNS3_CMD_FLAG_NEXT;
 285                 hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
 286                 if (en) {
 287                         desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN;
 288                         desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN;
 289                         desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN;
 290                         desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN;
 291                 }
 292
 293                 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK;
 294                 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK;
 295                 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK;
 296                 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK;
 297                 num = 2;
 298                 break;
 299         case HNS3_PPU_MPF_OTHER_INT_CMD:
 300                 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
 301                 if (en)
 302                         desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2;
 303
 304                 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK;
 305                 break;
 306         case HNS3_PPU_PF_OTHER_INT_CMD:
 307                 hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
 308                 if (en)
 309                         desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN;
 310
 311                 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK;
 312                 break;
 313         default:
 314                 hns3_err(hw,
 315                          "Invalid cmd(%u) to configure PPU error interrupts.",
 316                          cmd);
 317                 return -EINVAL;
 318         }
 319
 320         return hns3_cmd_send(hw, &desc[0], num);
 321 }
 322
 323 static int
 324 enable_ppu_err_intr(struct hns3_adapter *hns, bool en)
 325 {
 326         struct hns3_hw *hw = &hns->hw;
 327         int ret;
 328
 329         ret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_ECC_INT_CMD, en);
 330         if (ret) {
 331                 hns3_err(hw, "fail to configure PPU MPF ECC error intr: %d",
 332                          ret);
 333                 return ret;
 334         }
 335
 336         ret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_OTHER_INT_CMD, en);
 337         if (ret) {
 338                 hns3_err(hw, "fail to configure PPU MPF other intr: %d",
 339                          ret);
 340                 return ret;
 341         }
 342
 343         ret = config_ppu_err_intrs(hns, HNS3_PPU_PF_OTHER_INT_CMD, en);
 344         if (ret)
 345                 hns3_err(hw, "fail to configure PPU PF error interrupts: %d",
 346                          ret);
 347         return ret;
 348 }
 349
 350 static int
 351 enable_mac_err_intr(struct hns3_adapter *hns, bool en)
 352 {
 353         struct hns3_hw *hw = &hns->hw;
 354         struct hns3_cmd_desc desc;
 355         int ret;
 356
 357         /* configure MAC common error interrupts */
 358         hns3_cmd_setup_basic_desc(&desc, HNS3_MAC_COMMON_INT_EN, false);
 359         if (en)
 360                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN);
 361
 362         desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK);
 363
 364         ret = hns3_cmd_send(hw, &desc, 1);
 365         if (ret)
 366                 hns3_err(hw, "fail to configure MAC COMMON error intr: %d",
 367                          ret);
 368
 369         return ret;
 370 }
 371
 372 static const struct hns3_hw_blk hw_blk[] = {
 373         {
 374                 .name = "PPP",
 375                 .enable_err_intr = enable_ppp_err_intr,
 376         },
 377         {
 378                 .name = "SSU",
 379                 .enable_err_intr = enable_ssu_err_intr,
 380         },
 381         {
 382                 .name = "PPU",
 383                 .enable_err_intr = enable_ppu_err_intr,
 384         },
 385         {
 386                 .name = "MAC",
 387                 .enable_err_intr = enable_mac_err_intr,
 388         },
 389         {
 390                 .name = NULL,
 391                 .enable_err_intr = NULL,
 392         }
 393 };
 394
 395 int
 396 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en)
 397 {
 398         const struct hns3_hw_blk *module = hw_blk;
 399         int ret = 0;
 400
 401         while (module->enable_err_intr) {
 402                 ret = module->enable_err_intr(hns, en);
 403                 if (ret)
 404                         return ret;
 405
 406                 module++;
 407         }
 408
 409         return ret;
 410 }
 411
 412 static enum hns3_reset_level
 413 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg,
 414                         const struct hns3_hw_error *err, uint32_t err_sts)
 415 {
 416         enum hns3_reset_level reset_level = HNS3_FUNC_RESET;
 417         struct hns3_hw *hw = &hns->hw;
 418         bool need_reset = false;
 419
 420         while (err->msg) {
 421                 if (err->int_msk & err_sts) {
 422                         hns3_warn(hw, "%s %s found [error status=0x%x]",
 423                                   reg, err->msg, err_sts);
 424                         if (err->reset_level != HNS3_NONE_RESET &&
 425                             err->reset_level >= reset_level) {
 426                                 reset_level = err->reset_level;
 427                                 need_reset = true;
 428                         }
 429                 }
 430                 err++;
 431         }
 432         if (need_reset)
 433                 return reset_level;
 434         else
 435                 return HNS3_NONE_RESET;
 436 }
 437
 438 static int
 439 query_num_bds_in_msix(struct hns3_hw *hw, struct hns3_cmd_desc *desc_bd)
 440 {
 441         int ret;
 442
 443         hns3_cmd_setup_basic_desc(desc_bd, HNS3_QUERY_MSIX_INT_STS_BD_NUM,
 444                                   true);
 445         ret = hns3_cmd_send(hw, desc_bd, 1);
 446         if (ret)
 447                 hns3_err(hw, "query num bds in msix failed: %d", ret);
 448
 449         return ret;
 450 }
 451
 452 static int
 453 query_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
 454                        uint32_t mpf_bd_num)
 455 {
 456         int ret;
 457
 458         hns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT,
 459                                   true);
 460         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 461
 462         ret = hns3_cmd_send(hw, &desc[0], mpf_bd_num);
 463         if (ret)
 464                 hns3_err(hw, "query all mpf msix err failed: %d", ret);
 465
 466         return ret;
 467 }
 468
 469 static int
 470 clear_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
 471                        uint32_t mpf_bd_num)
 472 {
 473         int ret;
 474
 475         hns3_cmd_reuse_desc(desc, false);
 476         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 477
 478         ret = hns3_cmd_send(hw, desc, mpf_bd_num);
 479         if (ret)
 480                 hns3_err(hw, "clear all mpf msix err failed: %d", ret);
 481
 482         return ret;
 483 }
 484
 485 static int
 486 query_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
 487                       uint32_t pf_bd_num)
 488 {
 489         int ret;
 490
 491         hns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_PF_MSIX_INT, true);
 492         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 493
 494         ret = hns3_cmd_send(hw, desc, pf_bd_num);
 495         if (ret)
 496                 hns3_err(hw, "query all pf msix int cmd failed: %d", ret);
 497
 498         return ret;
 499 }
 500
 501 static int
 502 clear_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
 503                       uint32_t pf_bd_num)
 504 {
 505         int ret;
 506
 507         hns3_cmd_reuse_desc(desc, false);
 508         desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 509
 510         ret = hns3_cmd_send(hw, desc, pf_bd_num);
 511         if (ret)
 512                 hns3_err(hw, "clear all pf msix err failed: %d", ret);
 513
 514         return ret;
 515 }
 516
 517 void
 518 hns3_intr_unregister(const struct rte_intr_handle *hdl,
 519                      rte_intr_callback_fn cb_fn, void *cb_arg)
 520 {
 521         int retry_cnt = 0;
 522         int ret;
 523
 524         do {
 525                 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg);
 526                 if (ret >= 0) {
 527                         break;
 528                 } else if (ret != -EAGAIN) {
 529                         PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret);
 530                         break;
 531                 }
 532                 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS);
 533         } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT);
 534 }
 535
 536 void
 537 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)
 538 {
 539         uint32_t mpf_bd_num, pf_bd_num, bd_num;
 540         enum hns3_reset_level req_level;
 541         struct hns3_hw *hw = &hns->hw;
 542         struct hns3_pf *pf = &hns->pf;
 543         struct hns3_cmd_desc desc_bd;
 544         struct hns3_cmd_desc *desc;
 545         uint32_t *desc_data;
 546         uint32_t status;
 547         int ret;
 548
 549         /* query the number of bds for the MSIx int status */
 550         ret = query_num_bds_in_msix(hw, &desc_bd);
 551         if (ret) {
 552                 hns3_err(hw, "fail to query msix int status bd num: %d", ret);
 553                 return;
 554         }
 555
 556         mpf_bd_num = rte_le_to_cpu_32(desc_bd.data[0]);
 557         pf_bd_num = rte_le_to_cpu_32(desc_bd.data[1]);
 558         bd_num = max_t(uint32_t, mpf_bd_num, pf_bd_num);
 559         if (bd_num < RCB_ERROR_OFFSET) {
 560                 hns3_err(hw, "bd_num is less than RCB_ERROR_OFFSET: %u",
 561                          bd_num);
 562                 return;
 563         }
 564
 565         desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);
 566         if (desc == NULL) {
 567                 hns3_err(hw, "fail to zmalloc desc");
 568                 return;
 569         }
 570
 571         /* query all main PF MSIx errors */
 572         ret = query_all_mpf_msix_err(hw, &desc[0], mpf_bd_num);
 573         if (ret) {
 574                 hns3_err(hw, "query all mpf msix int cmd failed: %d", ret);
 575                 goto out;
 576         }
 577
 578         /* log MAC errors */
 579         desc_data = (uint32_t *)&desc[MAC_ERROR_OFFSET];
 580         status = rte_le_to_cpu_32(*desc_data);
 581         if (status) {
 582                 req_level = hns3_find_highest_level(hns, "MAC_AFIFO_TNL_INT_R",
 583                                                     mac_afifo_tnl_int,
 584                                                     status);
 585                 hns3_atomic_set_bit(req_level, levels);
 586                 pf->abn_int_stats.mac_afifo_tnl_intr_cnt++;
 587         }
 588
 589         /* log PPU(RCB) errors */
 590         desc_data = (uint32_t *)&desc[RCB_ERROR_OFFSET];
 591         status = rte_le_to_cpu_32(*(desc_data + RCB_ERROR_STATUS_OFFSET)) &
 592                         HNS3_PPU_MPF_INT_ST2_MSIX_MASK;
 593         if (status) {
 594                 req_level = hns3_find_highest_level(hns,
 595                                                     "PPU_MPF_ABNORMAL_INT_ST2",
 596                                                     ppu_mpf_abnormal_int_st2,
 597                                                     status);
 598                 hns3_atomic_set_bit(req_level, levels);
 599                 pf->abn_int_stats.ppu_mpf_abnormal_intr_st2_cnt++;
 600         }
 601
 602         /* clear all main PF MSIx errors */
 603         ret = clear_all_mpf_msix_err(hw, desc, mpf_bd_num);
 604         if (ret) {
 605                 hns3_err(hw, "clear all mpf msix int cmd failed: %d", ret);
 606                 goto out;
 607         }
 608
 609         /* query all PF MSIx errors */
 610         memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));
 611         ret = query_all_pf_msix_err(hw, &desc[0], pf_bd_num);
 612         if (ret) {
 613                 hns3_err(hw, "query all pf msix int cmd failed (%d)", ret);
 614                 goto out;
 615         }
 616
 617         /* log SSU PF errors */
 618         status = rte_le_to_cpu_32(desc[0].data[0]) &
 619                  HNS3_SSU_PORT_INT_MSIX_MASK;
 620         if (status) {
 621                 req_level = hns3_find_highest_level(hns,
 622                                                     "SSU_PORT_BASED_ERR_INT",
 623                                                     ssu_port_based_pf_int,
 624                                                     status);
 625                 hns3_atomic_set_bit(req_level, levels);
 626                 pf->abn_int_stats.ssu_port_based_pf_intr_cnt++;
 627         }
 628
 629         /* log PPP PF errors */
 630         desc_data = (uint32_t *)&desc[PPP_PF_ERROR_OFFSET];
 631         status = rte_le_to_cpu_32(*desc_data);
 632         if (status) {
 633                 req_level = hns3_find_highest_level(hns,
 634                                                     "PPP_PF_ABNORMAL_INT_ST0",
 635                                                     ppp_pf_abnormal_int,
 636                                                     status);
 637                 hns3_atomic_set_bit(req_level, levels);
 638                 pf->abn_int_stats.ppp_pf_abnormal_intr_cnt++;
 639         }
 640
 641         /* log PPU(RCB) PF errors */
 642         desc_data = (uint32_t *)&desc[PPU_PF_ERROR_OFFSET];
 643         status = rte_le_to_cpu_32(*desc_data) & HNS3_PPU_PF_INT_MSIX_MASK;
 644         if (status) {
 645                 req_level = hns3_find_highest_level(hns,
 646                                                     "PPU_PF_ABNORMAL_INT_ST",
 647                                                     ppu_pf_abnormal_int,
 648                                                     status);
 649                 hns3_atomic_set_bit(req_level, levels);
 650                 pf->abn_int_stats.ppu_pf_abnormal_intr_cnt++;
 651         }
 652
 653         /* clear all PF MSIx errors */
 654         ret = clear_all_pf_msix_err(hw, desc, pf_bd_num);
 655         if (ret)
 656                 hns3_err(hw, "clear all pf msix int cmd failed: %d", ret);
 657 out:
 658         rte_free(desc);
 659 }
 660
 661 int
 662 hns3_reset_init(struct hns3_hw *hw)
 663 {
 664         rte_spinlock_init(&hw->lock);
 665         hw->reset.level = HNS3_NONE_RESET;
 666         hw->reset.stage = RESET_STAGE_NONE;
 667         hw->reset.request = 0;
 668         hw->reset.pending = 0;
 669         rte_atomic16_init(&hw->reset.resetting);
 670         rte_atomic16_init(&hw->reset.disable_cmd);
 671         hw->reset.wait_data = rte_zmalloc("wait_data",
 672                                           sizeof(struct hns3_wait_data), 0);
 673         if (!hw->reset.wait_data) {
 674                 PMD_INIT_LOG(ERR, "Failed to allocate memory for wait_data");
 675                 return -ENOMEM;
 676         }
 677         return 0;
 678 }
 679
 680 void
 681 hns3_schedule_reset(struct hns3_adapter *hns)
 682 {
 683         struct hns3_hw *hw = &hns->hw;
 684
 685         /* Reschedule the reset process after successful initialization */
 686         if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
 687                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_PENDING);
 688                 return;
 689         }
 690
 691         if (hw->adapter_state >= HNS3_NIC_CLOSED)
 692                 return;
 693
 694         /* Schedule restart alarm if it is not scheduled yet */
 695         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_REQUESTED)
 696                 return;
 697         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED)
 698                 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
 699         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
 700
 701         rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);
 702 }
 703
 704 void
 705 hns3_schedule_delayed_reset(struct hns3_adapter *hns)
 706 {
 707 #define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC)
 708         struct hns3_hw *hw = &hns->hw;
 709
 710         /* Do nothing if it is uninited or closed */
 711         if (hw->adapter_state == HNS3_NIC_UNINITIALIZED ||
 712             hw->adapter_state >= HNS3_NIC_CLOSED) {
 713                 return;
 714         }
 715
 716         if (rte_atomic16_read(&hns->hw.reset.schedule) != SCHEDULE_NONE)
 717                 return;
 718         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_DEFERRED);
 719         rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);
 720 }
 721
 722 void
 723 hns3_wait_callback(void *param)
 724 {
 725         struct hns3_wait_data *data = (struct hns3_wait_data *)param;
 726         struct hns3_adapter *hns = data->hns;
 727         struct hns3_hw *hw = &hns->hw;
 728         uint64_t msec;
 729         bool done;
 730
 731         data->count--;
 732         if (data->check_completion) {
 733                 /*
 734                  * Check if the current time exceeds the deadline
 735                  * or a pending reset coming, or reset during close.
 736                  */
 737                 msec = get_timeofday_ms();
 738                 if (msec > data->end_ms || is_reset_pending(hns) ||
 739                     hw->adapter_state == HNS3_NIC_CLOSING) {
 740                         done = false;
 741                         data->count = 0;
 742                 } else
 743                         done = data->check_completion(hw);
 744         } else
 745                 done = true;
 746
 747         if (!done && data->count > 0) {
 748                 rte_eal_alarm_set(data->interval, hns3_wait_callback, data);
 749                 return;
 750         }
 751         if (done)
 752                 data->result = HNS3_WAIT_SUCCESS;
 753         else {
 754                 hns3_err(hw, "%s wait timeout at stage %d",
 755                          reset_string[hw->reset.level], hw->reset.stage);
 756                 data->result = HNS3_WAIT_TIMEOUT;
 757         }
 758         hns3_schedule_reset(hns);
 759 }
 760
 761 void
 762 hns3_notify_reset_ready(struct hns3_hw *hw, bool enable)
 763 {
 764         uint32_t reg_val;
 765
 766         reg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG);
 767         if (enable)
 768                 reg_val |= HNS3_NIC_SW_RST_RDY;
 769         else
 770                 reg_val &= ~HNS3_NIC_SW_RST_RDY;
 771
 772         hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val);
 773 }
 774
 775 int
 776 hns3_reset_req_hw_reset(struct hns3_adapter *hns)
 777 {
 778         struct hns3_hw *hw = &hns->hw;
 779
 780         if (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) {
 781                 hw->reset.wait_data->hns = hns;
 782                 hw->reset.wait_data->check_completion = NULL;
 783                 hw->reset.wait_data->interval = HNS3_RESET_SYNC_US;
 784                 hw->reset.wait_data->count = 1;
 785                 hw->reset.wait_data->result = HNS3_WAIT_REQUEST;
 786                 rte_eal_alarm_set(hw->reset.wait_data->interval,
 787                                   hns3_wait_callback, hw->reset.wait_data);
 788                 return -EAGAIN;
 789         } else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
 790                 return -EAGAIN;
 791
 792         /* inform hardware that preparatory work is done */
 793         hns3_notify_reset_ready(hw, true);
 794         return 0;
 795 }
 796
 797 static void
 798 hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)
 799 {
 800         uint64_t merge_cnt = hw->reset.stats.merge_cnt;
 801         int64_t tmp;
 802
 803         switch (hw->reset.level) {
 804         case HNS3_IMP_RESET:
 805                 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels);
 806                 tmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels);
 807                 HNS3_CHECK_MERGE_CNT(tmp);
 808                 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
 809                 HNS3_CHECK_MERGE_CNT(tmp);
 810                 break;
 811         case HNS3_GLOBAL_RESET:
 812                 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels);
 813                 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);
 814                 HNS3_CHECK_MERGE_CNT(tmp);
 815                 break;
 816         case HNS3_FUNC_RESET:
 817                 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels);
 818                 break;
 819         case HNS3_VF_RESET:
 820                 hns3_atomic_clear_bit(HNS3_VF_RESET, levels);
 821                 tmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
 822                 HNS3_CHECK_MERGE_CNT(tmp);
 823                 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
 824                 HNS3_CHECK_MERGE_CNT(tmp);
 825                 break;
 826         case HNS3_VF_FULL_RESET:
 827                 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels);
 828                 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
 829                 HNS3_CHECK_MERGE_CNT(tmp);
 830                 break;
 831         case HNS3_VF_PF_FUNC_RESET:
 832                 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);
 833                 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);
 834                 HNS3_CHECK_MERGE_CNT(tmp);
 835                 break;
 836         case HNS3_VF_FUNC_RESET:
 837                 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels);
 838                 break;
 839         case HNS3_FLR_RESET:
 840                 hns3_atomic_clear_bit(HNS3_FLR_RESET, levels);
 841                 break;
 842         case HNS3_NONE_RESET:
 843         default:
 844                 return;
 845         };
 846         if (merge_cnt != hw->reset.stats.merge_cnt)
 847                 hns3_warn(hw,
 848                           "No need to do low-level reset after %s reset. "
 849                           "merge cnt: %" PRIx64 " total merge cnt: %" PRIx64,
 850                           reset_string[hw->reset.level],
 851                           hw->reset.stats.merge_cnt - merge_cnt,
 852                           hw->reset.stats.merge_cnt);
 853 }
 854
 855 static bool
 856 hns3_reset_err_handle(struct hns3_adapter *hns)
 857 {
 858 #define MAX_RESET_FAIL_CNT 5
 859
 860         struct hns3_hw *hw = &hns->hw;
 861
 862         if (hw->adapter_state == HNS3_NIC_CLOSING)
 863                 goto reset_fail;
 864
 865         if (is_reset_pending(hns)) {
 866                 hw->reset.attempts = 0;
 867                 hw->reset.stats.fail_cnt++;
 868                 hns3_warn(hw, "%s reset fail because new Reset is pending "
 869                               "attempts:%" PRIx64,
 870                           reset_string[hw->reset.level],
 871                           hw->reset.stats.fail_cnt);
 872                 hw->reset.level = HNS3_NONE_RESET;
 873                 return true;
 874         }
 875
 876         hw->reset.attempts++;
 877         if (hw->reset.attempts < MAX_RESET_FAIL_CNT) {
 878                 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending);
 879                 hns3_warn(hw, "%s retry to reset attempts: %d",
 880                           reset_string[hw->reset.level],
 881                           hw->reset.attempts);
 882                 return true;
 883         }
 884
 885         if (rte_atomic16_read(&hw->reset.disable_cmd))
 886                 hns3_cmd_init(hw);
 887 reset_fail:
 888         hw->reset.attempts = 0;
 889         hw->reset.stats.fail_cnt++;
 890         hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64
 891                   " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64
 892                   " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64
 893                   " merge_cnt:%" PRIx64,
 894                   reset_string[hw->reset.level], hw->reset.stats.fail_cnt,
 895                   hw->reset.stats.success_cnt, hw->reset.stats.global_cnt,
 896                   hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt,
 897                   hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt);
 898
 899         /* IMP no longer waiting the ready flag */
 900         hns3_notify_reset_ready(hw, true);
 901         return false;
 902 }
 903
 904 static int
 905 hns3_reset_pre(struct hns3_adapter *hns)
 906 {
 907         struct hns3_hw *hw = &hns->hw;
 908         struct timeval tv;
 909         int ret;
 910
 911         if (hw->reset.stage == RESET_STAGE_NONE) {
 912                 rte_atomic16_set(&hns->hw.reset.resetting, 1);
 913                 hw->reset.stage = RESET_STAGE_DOWN;
 914                 ret = hw->reset.ops->stop_service(hns);
 915                 gettimeofday(&tv, NULL);
 916                 if (ret) {
 917                         hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld",
 918                                   ret, tv.tv_sec, tv.tv_usec);
 919                         return ret;
 920                 }
 921                 hns3_warn(hw, "Reset step1 down success time=%ld.%.6ld",
 922                           tv.tv_sec, tv.tv_usec);
 923                 hw->reset.stage = RESET_STAGE_PREWAIT;
 924         }
 925         if (hw->reset.stage == RESET_STAGE_PREWAIT) {
 926                 ret = hw->reset.ops->prepare_reset(hns);
 927                 gettimeofday(&tv, NULL);
 928                 if (ret) {
 929                         hns3_warn(hw,
 930                                   "Reset step2 prepare wait fail=%d time=%ld.%.6ld",
 931                                   ret, tv.tv_sec, tv.tv_usec);
 932                         return ret;
 933                 }
 934                 hns3_warn(hw, "Reset step2 prepare wait success time=%ld.%.6ld",
 935                           tv.tv_sec, tv.tv_usec);
 936                 hw->reset.stage = RESET_STAGE_REQ_HW_RESET;
 937                 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
 938         }
 939         return 0;
 940 }
 941
 942 static int
 943 hns3_reset_post(struct hns3_adapter *hns)
 944 {
 945 #define TIMEOUT_RETRIES_CNT     5
 946         struct hns3_hw *hw = &hns->hw;
 947         struct timeval tv_delta;
 948         struct timeval tv;
 949         int ret = 0;
 950
 951         if (hw->adapter_state == HNS3_NIC_CLOSING) {
 952                 hns3_warn(hw, "Don't do reset_post during closing, just uninit cmd");
 953                 hns3_cmd_uninit(hw);
 954                 return -EPERM;
 955         }
 956
 957         if (hw->reset.stage == RESET_STAGE_DEV_INIT) {
 958                 rte_spinlock_lock(&hw->lock);
 959                 if (hw->reset.mbuf_deferred_free) {
 960                         hns3_dev_release_mbufs(hns);
 961                         hw->reset.mbuf_deferred_free = false;
 962                 }
 963                 ret = hw->reset.ops->reinit_dev(hns);
 964                 rte_spinlock_unlock(&hw->lock);
 965                 gettimeofday(&tv, NULL);
 966                 if (ret) {
 967                         hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d",
 968                                   ret, hw->reset.retries);
 969                         goto err;
 970                 }
 971                 hns3_warn(hw, "Reset step5 devinit success time=%ld.%.6ld",
 972                           tv.tv_sec, tv.tv_usec);
 973                 hw->reset.retries = 0;
 974                 hw->reset.stage = RESET_STAGE_RESTORE;
 975                 rte_eal_alarm_set(SWITCH_CONTEXT_US,
 976                                   hw->reset.ops->reset_service, hns);
 977                 return -EAGAIN;
 978         }
 979         if (hw->reset.stage == RESET_STAGE_RESTORE) {
 980                 rte_spinlock_lock(&hw->lock);
 981                 ret = hw->reset.ops->restore_conf(hns);
 982                 rte_spinlock_unlock(&hw->lock);
 983                 gettimeofday(&tv, NULL);
 984                 if (ret) {
 985                         hns3_warn(hw,
 986                                   "Reset step6 restore fail=%d retries=%d",
 987                                   ret, hw->reset.retries);
 988                         goto err;
 989                 }
 990                 hns3_warn(hw, "Reset step6 restore success time=%ld.%.6ld",
 991                           tv.tv_sec, tv.tv_usec);
 992                 hw->reset.retries = 0;
 993                 hw->reset.stage = RESET_STAGE_DONE;
 994         }
 995         if (hw->reset.stage == RESET_STAGE_DONE) {
 996                 /* IMP will wait ready flag before reset */
 997                 hns3_notify_reset_ready(hw, false);
 998                 hns3_clear_reset_level(hw, &hw->reset.pending);
 999                 rte_atomic16_clear(&hns->hw.reset.resetting);
1000                 hw->reset.attempts = 0;
1001                 hw->reset.stats.success_cnt++;
1002                 hw->reset.stage = RESET_STAGE_NONE;
1003                 hw->reset.ops->start_service(hns);
1004                 gettimeofday(&tv, NULL);
1005                 timersub(&tv, &hw->reset.start_time, &tv_delta);
1006                 hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64
1007                           " success_cnt:%" PRIx64 " global_cnt:%" PRIx64
1008                           " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64
1009                           " exec_cnt:%" PRIx64 " merge_cnt:%" PRIx64,
1010                           reset_string[hw->reset.level],
1011                           hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt,
1012                           hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt,
1013                           hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt,
1014                           hw->reset.stats.merge_cnt);
1015                 hns3_warn(hw,
1016                           "%s reset done delta %ld ms time=%ld.%.6ld",
1017                           reset_string[hw->reset.level],
1018                           tv_delta.tv_sec * MSEC_PER_SEC +
1019                           tv_delta.tv_usec / USEC_PER_MSEC,
1020                           tv.tv_sec, tv.tv_usec);
1021                 hw->reset.level = HNS3_NONE_RESET;
1022         }
1023         return 0;
1024
1025 err:
1026         if (ret == -ETIME) {
1027                 hw->reset.retries++;
1028                 if (hw->reset.retries < TIMEOUT_RETRIES_CNT) {
1029                         rte_eal_alarm_set(HNS3_RESET_SYNC_US,
1030                                           hw->reset.ops->reset_service, hns);
1031                         return -EAGAIN;
1032                 }
1033         }
1034         hw->reset.retries = 0;
1035         return -EIO;
1036 }
1037
1038 /*
1039  * There are three scenarios as follows:
1040  * When the reset is not in progress, the reset process starts.
1041  * During the reset process, if the reset level has not changed,
1042  * the reset process continues; otherwise, the reset process is aborted.
1043  *      hw->reset.level   new_level          action
1044  *      HNS3_NONE_RESET  HNS3_XXXX_RESET    start reset
1045  *      HNS3_XXXX_RESET  HNS3_XXXX_RESET    continue reset
1046  *      HNS3_LOW_RESET   HNS3_HIGH_RESET    abort
1047  */
1048 int
1049 hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level)
1050 {
1051         struct hns3_hw *hw = &hns->hw;
1052         struct timeval tv_delta;
1053         struct timeval tv;
1054         int ret;
1055
1056         if (hw->reset.level == HNS3_NONE_RESET) {
1057                 hw->reset.level = new_level;
1058                 hw->reset.stats.exec_cnt++;
1059                 gettimeofday(&hw->reset.start_time, NULL);
1060                 hns3_warn(hw, "Start %s reset time=%ld.%.6ld",
1061                           reset_string[hw->reset.level],
1062                           hw->reset.start_time.tv_sec,
1063                           hw->reset.start_time.tv_usec);
1064         }
1065
1066         if (is_reset_pending(hns)) {
1067                 gettimeofday(&tv, NULL);
1068                 hns3_warn(hw,
1069                           "%s reset is aborted by high level time=%ld.%.6ld",
1070                           reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
1071                 if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)
1072                         rte_eal_alarm_cancel(hns3_wait_callback,
1073                                              hw->reset.wait_data);
1074                 ret = -EBUSY;
1075                 goto err;
1076         }
1077
1078         ret = hns3_reset_pre(hns);
1079         if (ret)
1080                 goto err;
1081
1082         if (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) {
1083                 ret = hns3_reset_req_hw_reset(hns);
1084                 if (ret == -EAGAIN)
1085                         return ret;
1086                 gettimeofday(&tv, NULL);
1087                 hns3_warn(hw,
1088                           "Reset step3 request IMP reset success time=%ld.%.6ld",
1089                           tv.tv_sec, tv.tv_usec);
1090                 hw->reset.stage = RESET_STAGE_WAIT;
1091                 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;
1092         }
1093         if (hw->reset.stage == RESET_STAGE_WAIT) {
1094                 ret = hw->reset.ops->wait_hardware_ready(hns);
1095                 if (ret)
1096                         goto retry;
1097                 gettimeofday(&tv, NULL);
1098                 hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld",
1099                           tv.tv_sec, tv.tv_usec);
1100                 hw->reset.stage = RESET_STAGE_DEV_INIT;
1101         }
1102
1103         ret = hns3_reset_post(hns);
1104         if (ret)
1105                 goto retry;
1106
1107         return 0;
1108 retry:
1109         if (ret == -EAGAIN)
1110                 return ret;
1111 err:
1112         hns3_clear_reset_level(hw, &hw->reset.pending);
1113         if (hns3_reset_err_handle(hns)) {
1114                 hw->reset.stage = RESET_STAGE_PREWAIT;
1115                 hns3_schedule_reset(hns);
1116         } else {
1117                 rte_spinlock_lock(&hw->lock);
1118                 if (hw->reset.mbuf_deferred_free) {
1119                         hns3_dev_release_mbufs(hns);
1120                         hw->reset.mbuf_deferred_free = false;
1121                 }
1122                 rte_spinlock_unlock(&hw->lock);
1123                 rte_atomic16_clear(&hns->hw.reset.resetting);
1124                 hw->reset.stage = RESET_STAGE_NONE;
1125                 gettimeofday(&tv, NULL);
1126                 timersub(&tv, &hw->reset.start_time, &tv_delta);
1127                 hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld",
1128                           reset_string[hw->reset.level],
1129                           tv_delta.tv_sec * MSEC_PER_SEC +
1130                           tv_delta.tv_usec / USEC_PER_MSEC,
1131                           tv.tv_sec, tv.tv_usec);
1132                 hw->reset.level = HNS3_NONE_RESET;
1133         }
1134
1135         return -EIO;
1136 }
1137
1138 /*
1139  * The reset process can only be terminated after handshake with IMP(step3),
1140  * so that IMP can complete the reset process normally.
1141  */
1142 void
1143 hns3_reset_abort(struct hns3_adapter *hns)
1144 {
1145         struct hns3_hw *hw = &hns->hw;
1146         struct timeval tv;
1147         int i;
1148
1149         for (i = 0; i < HNS3_QUIT_RESET_CNT; i++) {
1150                 if (hw->reset.level == HNS3_NONE_RESET)
1151                         break;
1152                 rte_delay_ms(HNS3_QUIT_RESET_DELAY_MS);
1153         }
1154
1155         /* IMP no longer waiting the ready flag */
1156         hns3_notify_reset_ready(hw, true);
1157
1158         rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
1159         rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data);
1160
1161         if (hw->reset.level != HNS3_NONE_RESET) {
1162                 gettimeofday(&tv, NULL);
1163                 hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld",
1164                          reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);
1165         }
1166 }