drivers/net/hns3/hns3_regs.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdio.h>
  11 #include <inttypes.h>
  12 #include <unistd.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_io.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_rxtx.h"
  27 #include "hns3_regs.h"
  28
  29 #define MAX_SEPARATE_NUM        4
  30 #define SEPARATOR_VALUE         0xFFFFFFFF
  31 #define REG_NUM_PER_LINE        4
  32 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(uint32_t))
  33
  34 static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,
  35                                           HNS3_CMDQ_TX_ADDR_H_REG,
  36                                           HNS3_CMDQ_TX_DEPTH_REG,
  37                                           HNS3_CMDQ_TX_TAIL_REG,
  38                                           HNS3_CMDQ_TX_HEAD_REG,
  39                                           HNS3_CMDQ_RX_ADDR_L_REG,
  40                                           HNS3_CMDQ_RX_ADDR_H_REG,
  41                                           HNS3_CMDQ_RX_DEPTH_REG,
  42                                           HNS3_CMDQ_RX_TAIL_REG,
  43                                           HNS3_CMDQ_RX_HEAD_REG,
  44                                           HNS3_VECTOR0_CMDQ_SRC_REG,
  45                                           HNS3_CMDQ_INTR_STS_REG,
  46                                           HNS3_CMDQ_INTR_EN_REG,
  47                                           HNS3_CMDQ_INTR_GEN_REG};
  48
  49 static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  50                                             HNS3_VECTOR0_OTER_EN_REG,
  51                                             HNS3_MISC_RESET_STS_REG,
  52                                             HNS3_VECTOR0_OTHER_INT_STS_REG,
  53                                             HNS3_GLOBAL_RESET_REG,
  54                                             HNS3_FUN_RST_ING,
  55                                             HNS3_GRO_EN_REG};
  56
  57 static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  58                                                HNS3_FUN_RST_ING,
  59                                                HNS3_GRO_EN_REG};
  60
  61 static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,
  62                                           HNS3_RING_RX_BASEADDR_H_REG,
  63                                           HNS3_RING_RX_BD_NUM_REG,
  64                                           HNS3_RING_RX_BD_LEN_REG,
  65                                           HNS3_RING_RX_MERGE_EN_REG,
  66                                           HNS3_RING_RX_TAIL_REG,
  67                                           HNS3_RING_RX_HEAD_REG,
  68                                           HNS3_RING_RX_FBDNUM_REG,
  69                                           HNS3_RING_RX_OFFSET_REG,
  70                                           HNS3_RING_RX_FBD_OFFSET_REG,
  71                                           HNS3_RING_RX_STASH_REG,
  72                                           HNS3_RING_RX_BD_ERR_REG,
  73                                           HNS3_RING_TX_BASEADDR_L_REG,
  74                                           HNS3_RING_TX_BASEADDR_H_REG,
  75                                           HNS3_RING_TX_BD_NUM_REG,
  76                                           HNS3_RING_TX_PRIORITY_REG,
  77                                           HNS3_RING_TX_TC_REG,
  78                                           HNS3_RING_TX_MERGE_EN_REG,
  79                                           HNS3_RING_TX_TAIL_REG,
  80                                           HNS3_RING_TX_HEAD_REG,
  81                                           HNS3_RING_TX_FBDNUM_REG,
  82                                           HNS3_RING_TX_OFFSET_REG,
  83                                           HNS3_RING_TX_EBD_NUM_REG,
  84                                           HNS3_RING_TX_EBD_OFFSET_REG,
  85                                           HNS3_RING_TX_BD_ERR_REG,
  86                                           HNS3_RING_EN_REG};
  87
  88 static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,
  89                                               HNS3_TQP_INTR_GL0_REG,
  90                                               HNS3_TQP_INTR_GL1_REG,
  91                                               HNS3_TQP_INTR_GL2_REG,
  92                                               HNS3_TQP_INTR_RL_REG};
  93
  94 static int
  95 hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
  96                   uint32_t *regs_num_64_bit)
  97 {
  98         struct hns3_cmd_desc desc;
  99         int ret;
 100
 101         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_REG_NUM, true);
 102         ret = hns3_cmd_send(hw, &desc, 1);
 103         if (ret) {
 104                 hns3_err(hw, "Query register number cmd failed, ret = %d",
 105                          ret);
 106                 return ret;
 107         }
 108
 109         *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);
 110         *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);
 111
 112         return 0;
 113 }
 114
 115 static int
 116 hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
 117 {
 118         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 119         int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
 120         uint32_t regs_num_32_bit, regs_num_64_bit;
 121         int ret;
 122
 123         ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 124         if (ret) {
 125                 hns3_err(hw, "Get register number failed, ret = %d.",
 126                          ret);
 127                 return -ENOTSUP;
 128         }
 129
 130         cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1;
 131         if (hns->is_vf)
 132                 common_lines =
 133                         sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1;
 134         else
 135                 common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1;
 136         ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1;
 137         tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1;
 138
 139         *length = (cmdq_lines + common_lines + ring_lines * hw->tqps_num +
 140                    tqp_intr_lines * hw->num_msi) * REG_LEN_PER_LINE +
 141                   regs_num_32_bit * sizeof(uint32_t) +
 142                   regs_num_64_bit * sizeof(uint64_t);
 143
 144         return 0;
 145 }
 146
 147 static int
 148 hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 149 {
 150 #define HNS3_32_BIT_REG_RTN_DATANUM 8
 151 #define HNS3_32_BIT_DESC_NODATA_LEN 2
 152         struct hns3_cmd_desc *desc;
 153         uint32_t *reg_val = data;
 154         uint32_t *desc_data;
 155         int cmd_num;
 156         int i, k, n;
 157         int ret;
 158
 159         if (regs_num == 0)
 160                 return 0;
 161
 162         cmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN,
 163                                HNS3_32_BIT_REG_RTN_DATANUM);
 164         desc = rte_zmalloc("hns3-32bit-regs",
 165                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 166         if (desc == NULL) {
 167                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 168                          "store 32bit regs",
 169                          sizeof(struct hns3_cmd_desc) * cmd_num);
 170                 return -ENOMEM;
 171         }
 172
 173         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_32_BIT_REG, true);
 174         ret = hns3_cmd_send(hw, desc, cmd_num);
 175         if (ret) {
 176                 hns3_err(hw, "Query 32 bit register cmd failed, ret = %d",
 177                          ret);
 178                 rte_free(desc);
 179                 return ret;
 180         }
 181
 182         for (i = 0; i < cmd_num; i++) {
 183                 if (i == 0) {
 184                         desc_data = &desc[i].data[0];
 185                         n = HNS3_32_BIT_REG_RTN_DATANUM -
 186                             HNS3_32_BIT_DESC_NODATA_LEN;
 187                 } else {
 188                         desc_data = (uint32_t *)(&desc[i]);
 189                         n = HNS3_32_BIT_REG_RTN_DATANUM;
 190                 }
 191                 for (k = 0; k < n; k++) {
 192                         *reg_val++ = rte_le_to_cpu_32(*desc_data++);
 193
 194                         regs_num--;
 195                         if (regs_num == 0)
 196                                 break;
 197                 }
 198         }
 199
 200         rte_free(desc);
 201         return 0;
 202 }
 203
 204 static int
 205 hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 206 {
 207 #define HNS3_64_BIT_REG_RTN_DATANUM 4
 208 #define HNS3_64_BIT_DESC_NODATA_LEN 1
 209         struct hns3_cmd_desc *desc;
 210         uint64_t *reg_val = data;
 211         uint64_t *desc_data;
 212         int cmd_num;
 213         int i, k, n;
 214         int ret;
 215
 216         if (regs_num == 0)
 217                 return 0;
 218
 219         cmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN,
 220                                HNS3_64_BIT_REG_RTN_DATANUM);
 221         desc = rte_zmalloc("hns3-64bit-regs",
 222                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 223         if (desc == NULL) {
 224                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 225                          "store 64bit regs",
 226                          sizeof(struct hns3_cmd_desc) * cmd_num);
 227                 return -ENOMEM;
 228         }
 229
 230         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_64_BIT_REG, true);
 231         ret = hns3_cmd_send(hw, desc, cmd_num);
 232         if (ret) {
 233                 hns3_err(hw, "Query 64 bit register cmd failed, ret = %d",
 234                          ret);
 235                 rte_free(desc);
 236                 return ret;
 237         }
 238
 239         for (i = 0; i < cmd_num; i++) {
 240                 if (i == 0) {
 241                         desc_data = (uint64_t *)(&desc[i].data[0]);
 242                         n = HNS3_64_BIT_REG_RTN_DATANUM -
 243                             HNS3_64_BIT_DESC_NODATA_LEN;
 244                 } else {
 245                         desc_data = (uint64_t *)(&desc[i]);
 246                         n = HNS3_64_BIT_REG_RTN_DATANUM;
 247                 }
 248                 for (k = 0; k < n; k++) {
 249                         *reg_val++ = rte_le_to_cpu_64(*desc_data++);
 250
 251                         regs_num--;
 252                         if (!regs_num)
 253                                 break;
 254                 }
 255         }
 256
 257         rte_free(desc);
 258         return 0;
 259 }
 260
 261 static void
 262 hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)
 263 {
 264         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 265         uint32_t reg_offset;
 266         int separator_num;
 267         int reg_um;
 268         int i, j;
 269
 270         /* fetching per-PF registers values from PF PCIe register space */
 271         reg_um = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);
 272         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 273         for (i = 0; i < reg_um; i++)
 274                 *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);
 275         for (i = 0; i < separator_num; i++)
 276                 *data++ = SEPARATOR_VALUE;
 277
 278         if (hns->is_vf)
 279                 reg_um = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);
 280         else
 281                 reg_um = sizeof(common_reg_addrs) / sizeof(uint32_t);
 282         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 283         for (i = 0; i < reg_um; i++)
 284                 if (hns->is_vf)
 285                         *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);
 286                 else
 287                         *data++ = hns3_read_dev(hw, common_reg_addrs[i]);
 288         for (i = 0; i < separator_num; i++)
 289                 *data++ = SEPARATOR_VALUE;
 290
 291         reg_um = sizeof(ring_reg_addrs) / sizeof(uint32_t);
 292         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 293         for (j = 0; j < hw->tqps_num; j++) {
 294                 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_REG_SIZE * j;
 295                 for (i = 0; i < reg_um; i++)
 296                         *data++ = hns3_read_dev(hw,
 297                                                 ring_reg_addrs[i] + reg_offset);
 298                 for (i = 0; i < separator_num; i++)
 299                         *data++ = SEPARATOR_VALUE;
 300         }
 301
 302         reg_um = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);
 303         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 304         for (j = 0; j < hw->num_msi; j++) {
 305                 reg_offset = HNS3_TQP_INTR_REG_SIZE * j;
 306                 for (i = 0; i < reg_um; i++)
 307                         *data++ = hns3_read_dev(hw,
 308                                                 tqp_intr_reg_addrs[i] +
 309                                                 reg_offset);
 310                 for (i = 0; i < separator_num; i++)
 311                         *data++ = SEPARATOR_VALUE;
 312         }
 313 }
 314
 315 int
 316 hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
 317 {
 318         struct hns3_adapter *hns = eth_dev->data->dev_private;
 319         struct hns3_hw *hw = &hns->hw;
 320         uint32_t regs_num_32_bit;
 321         uint32_t regs_num_64_bit;
 322         uint32_t length;
 323         uint32_t *data;
 324         int ret;
 325
 326         if (regs == NULL) {
 327                 hns3_err(hw, "the input parameter regs is NULL!");
 328                 return -EINVAL;
 329         }
 330
 331         ret = hns3_get_regs_length(hw, &length);
 332         if (ret)
 333                 return ret;
 334
 335         data = regs->data;
 336         if (data == NULL) {
 337                 regs->length = length;
 338                 regs->width = sizeof(uint32_t);
 339                 return 0;
 340         }
 341
 342         /* Only full register dump is supported */
 343         if (regs->length && regs->length != length)
 344                 return -ENOTSUP;
 345
 346         /* fetching per-PF registers values from PF PCIe register space */
 347         hns3_direct_access_regs(hw, data);
 348
 349         ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 350         if (ret) {
 351                 hns3_err(hw, "Get register number failed, ret = %d", ret);
 352                 return ret;
 353         }
 354
 355         /* fetching PF common registers values from firmware */
 356         ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);
 357         if (ret) {
 358                 hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
 359                 return ret;
 360         }
 361
 362         data += regs_num_32_bit;
 363         ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);
 364         if (ret)
 365                 hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
 366
 367         return ret;
 368 }