drivers/net/hns3/hns3_regs.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdio.h>
  11 #include <inttypes.h>
  12 #include <unistd.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_io.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_rxtx.h"
  27 #include "hns3_regs.h"
  28
  29 #define MAX_SEPARATE_NUM        4
  30 #define SEPARATOR_VALUE         0xFFFFFFFF
  31 #define REG_NUM_PER_LINE        4
  32 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(uint32_t))
  33
  34 static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,
  35                                           HNS3_CMDQ_TX_ADDR_H_REG,
  36                                           HNS3_CMDQ_TX_DEPTH_REG,
  37                                           HNS3_CMDQ_TX_TAIL_REG,
  38                                           HNS3_CMDQ_TX_HEAD_REG,
  39                                           HNS3_CMDQ_RX_ADDR_L_REG,
  40                                           HNS3_CMDQ_RX_ADDR_H_REG,
  41                                           HNS3_CMDQ_RX_DEPTH_REG,
  42                                           HNS3_CMDQ_RX_TAIL_REG,
  43                                           HNS3_CMDQ_RX_HEAD_REG,
  44                                           HNS3_VECTOR0_CMDQ_SRC_REG,
  45                                           HNS3_CMDQ_INTR_STS_REG,
  46                                           HNS3_CMDQ_INTR_EN_REG,
  47                                           HNS3_CMDQ_INTR_GEN_REG};
  48
  49 static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  50                                             HNS3_VECTOR0_OTER_EN_REG,
  51                                             HNS3_MISC_RESET_STS_REG,
  52                                             HNS3_VECTOR0_OTHER_INT_STS_REG,
  53                                             HNS3_GLOBAL_RESET_REG,
  54                                             HNS3_FUN_RST_ING,
  55                                             HNS3_GRO_EN_REG};
  56
  57 static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  58                                                HNS3_FUN_RST_ING,
  59                                                HNS3_GRO_EN_REG};
  60
  61 static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,
  62                                           HNS3_RING_RX_BASEADDR_H_REG,
  63                                           HNS3_RING_RX_BD_NUM_REG,
  64                                           HNS3_RING_RX_BD_LEN_REG,
  65                                           HNS3_RING_RX_MERGE_EN_REG,
  66                                           HNS3_RING_RX_TAIL_REG,
  67                                           HNS3_RING_RX_HEAD_REG,
  68                                           HNS3_RING_RX_FBDNUM_REG,
  69                                           HNS3_RING_RX_OFFSET_REG,
  70                                           HNS3_RING_RX_FBD_OFFSET_REG,
  71                                           HNS3_RING_RX_STASH_REG,
  72                                           HNS3_RING_RX_BD_ERR_REG,
  73                                           HNS3_RING_TX_BASEADDR_L_REG,
  74                                           HNS3_RING_TX_BASEADDR_H_REG,
  75                                           HNS3_RING_TX_BD_NUM_REG,
  76                                           HNS3_RING_TX_PRIORITY_REG,
  77                                           HNS3_RING_TX_TC_REG,
  78                                           HNS3_RING_TX_MERGE_EN_REG,
  79                                           HNS3_RING_TX_TAIL_REG,
  80                                           HNS3_RING_TX_HEAD_REG,
  81                                           HNS3_RING_TX_FBDNUM_REG,
  82                                           HNS3_RING_TX_OFFSET_REG,
  83                                           HNS3_RING_TX_EBD_NUM_REG,
  84                                           HNS3_RING_TX_EBD_OFFSET_REG,
  85                                           HNS3_RING_TX_BD_ERR_REG,
  86                                           HNS3_RING_EN_REG};
  87
  88 static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,
  89                                               HNS3_TQP_INTR_GL0_REG,
  90                                               HNS3_TQP_INTR_GL1_REG,
  91                                               HNS3_TQP_INTR_GL2_REG,
  92                                               HNS3_TQP_INTR_RL_REG};
  93
  94 static int
  95 hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
  96                   uint32_t *regs_num_64_bit)
  97 {
  98         struct hns3_cmd_desc desc;
  99         int ret;
 100
 101         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_REG_NUM, true);
 102         ret = hns3_cmd_send(hw, &desc, 1);
 103         if (ret) {
 104                 hns3_err(hw, "Query register number cmd failed, ret = %d",
 105                          ret);
 106                 return ret;
 107         }
 108
 109         *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);
 110         *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);
 111
 112         return 0;
 113 }
 114
 115 static int
 116 hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
 117 {
 118         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 119         uint32_t cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
 120         uint32_t regs_num_32_bit, regs_num_64_bit;
 121         uint32_t len;
 122         int ret;
 123
 124         cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1;
 125         if (hns->is_vf)
 126                 common_lines =
 127                         sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1;
 128         else
 129                 common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1;
 130         ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1;
 131         tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1;
 132
 133         len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num +
 134               tqp_intr_lines * hw->num_msi) * REG_LEN_PER_LINE;
 135
 136         if (!hns->is_vf) {
 137                 ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 138                 if (ret) {
 139                         hns3_err(hw, "Get register number failed, ret = %d.",
 140                                  ret);
 141                         return -ENOTSUP;
 142                 }
 143                 len += regs_num_32_bit * sizeof(uint32_t) +
 144                        regs_num_64_bit * sizeof(uint64_t);
 145         }
 146
 147         *length = len;
 148         return 0;
 149 }
 150
 151 static int
 152 hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 153 {
 154 #define HNS3_32_BIT_REG_RTN_DATANUM 8
 155 #define HNS3_32_BIT_DESC_NODATA_LEN 2
 156         struct hns3_cmd_desc *desc;
 157         uint32_t *reg_val = data;
 158         uint32_t *desc_data;
 159         int cmd_num;
 160         int i, k, n;
 161         int ret;
 162
 163         if (regs_num == 0)
 164                 return 0;
 165
 166         cmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN,
 167                                HNS3_32_BIT_REG_RTN_DATANUM);
 168         desc = rte_zmalloc("hns3-32bit-regs",
 169                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 170         if (desc == NULL) {
 171                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 172                          "store 32bit regs",
 173                          sizeof(struct hns3_cmd_desc) * cmd_num);
 174                 return -ENOMEM;
 175         }
 176
 177         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_32_BIT_REG, true);
 178         ret = hns3_cmd_send(hw, desc, cmd_num);
 179         if (ret) {
 180                 hns3_err(hw, "Query 32 bit register cmd failed, ret = %d",
 181                          ret);
 182                 rte_free(desc);
 183                 return ret;
 184         }
 185
 186         for (i = 0; i < cmd_num; i++) {
 187                 if (i == 0) {
 188                         desc_data = &desc[i].data[0];
 189                         n = HNS3_32_BIT_REG_RTN_DATANUM -
 190                             HNS3_32_BIT_DESC_NODATA_LEN;
 191                 } else {
 192                         desc_data = (uint32_t *)(&desc[i]);
 193                         n = HNS3_32_BIT_REG_RTN_DATANUM;
 194                 }
 195                 for (k = 0; k < n; k++) {
 196                         *reg_val++ = rte_le_to_cpu_32(*desc_data++);
 197
 198                         regs_num--;
 199                         if (regs_num == 0)
 200                                 break;
 201                 }
 202         }
 203
 204         rte_free(desc);
 205         return 0;
 206 }
 207
 208 static int
 209 hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 210 {
 211 #define HNS3_64_BIT_REG_RTN_DATANUM 4
 212 #define HNS3_64_BIT_DESC_NODATA_LEN 1
 213         struct hns3_cmd_desc *desc;
 214         uint64_t *reg_val = data;
 215         uint64_t *desc_data;
 216         int cmd_num;
 217         int i, k, n;
 218         int ret;
 219
 220         if (regs_num == 0)
 221                 return 0;
 222
 223         cmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN,
 224                                HNS3_64_BIT_REG_RTN_DATANUM);
 225         desc = rte_zmalloc("hns3-64bit-regs",
 226                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 227         if (desc == NULL) {
 228                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 229                          "store 64bit regs",
 230                          sizeof(struct hns3_cmd_desc) * cmd_num);
 231                 return -ENOMEM;
 232         }
 233
 234         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_64_BIT_REG, true);
 235         ret = hns3_cmd_send(hw, desc, cmd_num);
 236         if (ret) {
 237                 hns3_err(hw, "Query 64 bit register cmd failed, ret = %d",
 238                          ret);
 239                 rte_free(desc);
 240                 return ret;
 241         }
 242
 243         for (i = 0; i < cmd_num; i++) {
 244                 if (i == 0) {
 245                         desc_data = (uint64_t *)(&desc[i].data[0]);
 246                         n = HNS3_64_BIT_REG_RTN_DATANUM -
 247                             HNS3_64_BIT_DESC_NODATA_LEN;
 248                 } else {
 249                         desc_data = (uint64_t *)(&desc[i]);
 250                         n = HNS3_64_BIT_REG_RTN_DATANUM;
 251                 }
 252                 for (k = 0; k < n; k++) {
 253                         *reg_val++ = rte_le_to_cpu_64(*desc_data++);
 254
 255                         regs_num--;
 256                         if (!regs_num)
 257                                 break;
 258                 }
 259         }
 260
 261         rte_free(desc);
 262         return 0;
 263 }
 264
 265 static void
 266 hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)
 267 {
 268         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 269         uint32_t reg_offset;
 270         int separator_num;
 271         int reg_um;
 272         int i, j;
 273
 274         /* fetching per-PF registers values from PF PCIe register space */
 275         reg_um = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);
 276         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 277         for (i = 0; i < reg_um; i++)
 278                 *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);
 279         for (i = 0; i < separator_num; i++)
 280                 *data++ = SEPARATOR_VALUE;
 281
 282         if (hns->is_vf)
 283                 reg_um = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);
 284         else
 285                 reg_um = sizeof(common_reg_addrs) / sizeof(uint32_t);
 286         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 287         for (i = 0; i < reg_um; i++)
 288                 if (hns->is_vf)
 289                         *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);
 290                 else
 291                         *data++ = hns3_read_dev(hw, common_reg_addrs[i]);
 292         for (i = 0; i < separator_num; i++)
 293                 *data++ = SEPARATOR_VALUE;
 294
 295         reg_um = sizeof(ring_reg_addrs) / sizeof(uint32_t);
 296         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 297         for (j = 0; j < hw->tqps_num; j++) {
 298                 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_REG_SIZE * j;
 299                 for (i = 0; i < reg_um; i++)
 300                         *data++ = hns3_read_dev(hw,
 301                                                 ring_reg_addrs[i] + reg_offset);
 302                 for (i = 0; i < separator_num; i++)
 303                         *data++ = SEPARATOR_VALUE;
 304         }
 305
 306         reg_um = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);
 307         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 308         for (j = 0; j < hw->num_msi; j++) {
 309                 reg_offset = HNS3_TQP_INTR_REG_SIZE * j;
 310                 for (i = 0; i < reg_um; i++)
 311                         *data++ = hns3_read_dev(hw,
 312                                                 tqp_intr_reg_addrs[i] +
 313                                                 reg_offset);
 314                 for (i = 0; i < separator_num; i++)
 315                         *data++ = SEPARATOR_VALUE;
 316         }
 317 }
 318
 319 int
 320 hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
 321 {
 322         struct hns3_adapter *hns = eth_dev->data->dev_private;
 323         struct hns3_hw *hw = &hns->hw;
 324         uint32_t regs_num_32_bit;
 325         uint32_t regs_num_64_bit;
 326         uint32_t length;
 327         uint32_t *data;
 328         int ret;
 329
 330         if (regs == NULL) {
 331                 hns3_err(hw, "the input parameter regs is NULL!");
 332                 return -EINVAL;
 333         }
 334
 335         ret = hns3_get_regs_length(hw, &length);
 336         if (ret)
 337                 return ret;
 338
 339         data = regs->data;
 340         if (data == NULL) {
 341                 regs->length = length;
 342                 regs->width = sizeof(uint32_t);
 343                 return 0;
 344         }
 345
 346         /* Only full register dump is supported */
 347         if (regs->length && regs->length != length)
 348                 return -ENOTSUP;
 349
 350         /* fetching per-PF registers values from PF PCIe register space */
 351         hns3_direct_access_regs(hw, data);
 352
 353         if (hns->is_vf)
 354                 return 0;
 355
 356         ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 357         if (ret) {
 358                 hns3_err(hw, "Get register number failed, ret = %d", ret);
 359                 return ret;
 360         }
 361
 362         /* fetching PF common registers values from firmware */
 363         ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);
 364         if (ret) {
 365                 hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
 366                 return ret;
 367         }
 368
 369         data += regs_num_32_bit;
 370         ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);
 371         if (ret)
 372                 hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
 373
 374         return ret;
 375 }