drivers/net/hns3/hns3_regs.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <ethdev_pci.h>
   6 #include <rte_io.h>
   7
   8 #include "hns3_ethdev.h"
   9 #include "hns3_logs.h"
  10 #include "hns3_rxtx.h"
  11 #include "hns3_regs.h"
  12
  13 #define MAX_SEPARATE_NUM        4
  14 #define SEPARATOR_VALUE         0xFFFFFFFF
  15 #define REG_NUM_PER_LINE        4
  16 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(uint32_t))
  17
  18 static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,
  19                                           HNS3_CMDQ_TX_ADDR_H_REG,
  20                                           HNS3_CMDQ_TX_DEPTH_REG,
  21                                           HNS3_CMDQ_TX_TAIL_REG,
  22                                           HNS3_CMDQ_TX_HEAD_REG,
  23                                           HNS3_CMDQ_RX_ADDR_L_REG,
  24                                           HNS3_CMDQ_RX_ADDR_H_REG,
  25                                           HNS3_CMDQ_RX_DEPTH_REG,
  26                                           HNS3_CMDQ_RX_TAIL_REG,
  27                                           HNS3_CMDQ_RX_HEAD_REG,
  28                                           HNS3_VECTOR0_CMDQ_SRC_REG,
  29                                           HNS3_CMDQ_INTR_STS_REG,
  30                                           HNS3_CMDQ_INTR_EN_REG,
  31                                           HNS3_CMDQ_INTR_GEN_REG};
  32
  33 static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  34                                             HNS3_VECTOR0_OTER_EN_REG,
  35                                             HNS3_MISC_RESET_STS_REG,
  36                                             HNS3_VECTOR0_OTHER_INT_STS_REG,
  37                                             HNS3_GLOBAL_RESET_REG,
  38                                             HNS3_FUN_RST_ING,
  39                                             HNS3_GRO_EN_REG};
  40
  41 static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  42                                                HNS3_FUN_RST_ING,
  43                                                HNS3_GRO_EN_REG};
  44
  45 static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,
  46                                           HNS3_RING_RX_BASEADDR_H_REG,
  47                                           HNS3_RING_RX_BD_NUM_REG,
  48                                           HNS3_RING_RX_BD_LEN_REG,
  49                                           HNS3_RING_RX_EN_REG,
  50                                           HNS3_RING_RX_MERGE_EN_REG,
  51                                           HNS3_RING_RX_TAIL_REG,
  52                                           HNS3_RING_RX_HEAD_REG,
  53                                           HNS3_RING_RX_FBDNUM_REG,
  54                                           HNS3_RING_RX_OFFSET_REG,
  55                                           HNS3_RING_RX_FBD_OFFSET_REG,
  56                                           HNS3_RING_RX_STASH_REG,
  57                                           HNS3_RING_RX_BD_ERR_REG,
  58                                           HNS3_RING_TX_BASEADDR_L_REG,
  59                                           HNS3_RING_TX_BASEADDR_H_REG,
  60                                           HNS3_RING_TX_BD_NUM_REG,
  61                                           HNS3_RING_TX_EN_REG,
  62                                           HNS3_RING_TX_PRIORITY_REG,
  63                                           HNS3_RING_TX_TC_REG,
  64                                           HNS3_RING_TX_MERGE_EN_REG,
  65                                           HNS3_RING_TX_TAIL_REG,
  66                                           HNS3_RING_TX_HEAD_REG,
  67                                           HNS3_RING_TX_FBDNUM_REG,
  68                                           HNS3_RING_TX_OFFSET_REG,
  69                                           HNS3_RING_TX_EBD_NUM_REG,
  70                                           HNS3_RING_TX_EBD_OFFSET_REG,
  71                                           HNS3_RING_TX_BD_ERR_REG,
  72                                           HNS3_RING_EN_REG};
  73
  74 static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,
  75                                               HNS3_TQP_INTR_GL0_REG,
  76                                               HNS3_TQP_INTR_GL1_REG,
  77                                               HNS3_TQP_INTR_GL2_REG,
  78                                               HNS3_TQP_INTR_RL_REG};
  79
  80 static int
  81 hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
  82                   uint32_t *regs_num_64_bit)
  83 {
  84         struct hns3_cmd_desc desc;
  85         int ret;
  86
  87         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_REG_NUM, true);
  88         ret = hns3_cmd_send(hw, &desc, 1);
  89         if (ret) {
  90                 hns3_err(hw, "Query register number cmd failed, ret = %d",
  91                          ret);
  92                 return ret;
  93         }
  94
  95         *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);
  96         *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);
  97
  98         return 0;
  99 }
 100
 101 static int
 102 hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
 103 {
 104         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 105         uint32_t cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
 106         uint32_t regs_num_32_bit, regs_num_64_bit;
 107         uint32_t dfx_reg_lines;
 108         uint32_t len;
 109         int ret;
 110
 111         cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1;
 112         if (hns->is_vf)
 113                 common_lines =
 114                         sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1;
 115         else
 116                 common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1;
 117         ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1;
 118         tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1;
 119
 120         len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num +
 121               tqp_intr_lines * hw->num_msi) * REG_NUM_PER_LINE;
 122
 123         if (!hns->is_vf) {
 124                 ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 125                 if (ret) {
 126                         hns3_err(hw, "Get register number failed, ret = %d.",
 127                                  ret);
 128                         return -ENOTSUP;
 129                 }
 130                 dfx_reg_lines = regs_num_32_bit * sizeof(uint32_t) /
 131                                         REG_LEN_PER_LINE + 1;
 132                 dfx_reg_lines += regs_num_64_bit * sizeof(uint64_t) /
 133                                         REG_LEN_PER_LINE + 1;
 134                 len += dfx_reg_lines * REG_NUM_PER_LINE;
 135         }
 136
 137         *length = len;
 138         return 0;
 139 }
 140
 141 static int
 142 hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 143 {
 144 #define HNS3_32_BIT_REG_RTN_DATANUM 8
 145 #define HNS3_32_BIT_DESC_NODATA_LEN 2
 146         struct hns3_cmd_desc *desc;
 147         uint32_t *reg_val = data;
 148         uint32_t *desc_data;
 149         int cmd_num;
 150         int i, k, n;
 151         int ret;
 152
 153         if (regs_num == 0)
 154                 return 0;
 155
 156         cmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN,
 157                                HNS3_32_BIT_REG_RTN_DATANUM);
 158         desc = rte_zmalloc("hns3-32bit-regs",
 159                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 160         if (desc == NULL) {
 161                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 162                          "store 32bit regs",
 163                          sizeof(struct hns3_cmd_desc) * cmd_num);
 164                 return -ENOMEM;
 165         }
 166
 167         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_32_BIT_REG, true);
 168         ret = hns3_cmd_send(hw, desc, cmd_num);
 169         if (ret) {
 170                 hns3_err(hw, "Query 32 bit register cmd failed, ret = %d",
 171                          ret);
 172                 rte_free(desc);
 173                 return ret;
 174         }
 175
 176         for (i = 0; i < cmd_num; i++) {
 177                 if (i == 0) {
 178                         desc_data = &desc[i].data[0];
 179                         n = HNS3_32_BIT_REG_RTN_DATANUM -
 180                             HNS3_32_BIT_DESC_NODATA_LEN;
 181                 } else {
 182                         desc_data = (uint32_t *)(&desc[i]);
 183                         n = HNS3_32_BIT_REG_RTN_DATANUM;
 184                 }
 185                 for (k = 0; k < n; k++) {
 186                         *reg_val++ = rte_le_to_cpu_32(*desc_data++);
 187
 188                         regs_num--;
 189                         if (regs_num == 0)
 190                                 break;
 191                 }
 192         }
 193
 194         rte_free(desc);
 195         return 0;
 196 }
 197
 198 static int
 199 hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 200 {
 201 #define HNS3_64_BIT_REG_RTN_DATANUM 4
 202 #define HNS3_64_BIT_DESC_NODATA_LEN 1
 203         struct hns3_cmd_desc *desc;
 204         uint64_t *reg_val = data;
 205         uint64_t *desc_data;
 206         int cmd_num;
 207         int i, k, n;
 208         int ret;
 209
 210         if (regs_num == 0)
 211                 return 0;
 212
 213         cmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN,
 214                                HNS3_64_BIT_REG_RTN_DATANUM);
 215         desc = rte_zmalloc("hns3-64bit-regs",
 216                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 217         if (desc == NULL) {
 218                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 219                          "store 64bit regs",
 220                          sizeof(struct hns3_cmd_desc) * cmd_num);
 221                 return -ENOMEM;
 222         }
 223
 224         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_64_BIT_REG, true);
 225         ret = hns3_cmd_send(hw, desc, cmd_num);
 226         if (ret) {
 227                 hns3_err(hw, "Query 64 bit register cmd failed, ret = %d",
 228                          ret);
 229                 rte_free(desc);
 230                 return ret;
 231         }
 232
 233         for (i = 0; i < cmd_num; i++) {
 234                 if (i == 0) {
 235                         desc_data = (uint64_t *)(&desc[i].data[0]);
 236                         n = HNS3_64_BIT_REG_RTN_DATANUM -
 237                             HNS3_64_BIT_DESC_NODATA_LEN;
 238                 } else {
 239                         desc_data = (uint64_t *)(&desc[i]);
 240                         n = HNS3_64_BIT_REG_RTN_DATANUM;
 241                 }
 242                 for (k = 0; k < n; k++) {
 243                         *reg_val++ = rte_le_to_cpu_64(*desc_data++);
 244
 245                         regs_num--;
 246                         if (!regs_num)
 247                                 break;
 248                 }
 249         }
 250
 251         rte_free(desc);
 252         return 0;
 253 }
 254
 255 static int
 256 hns3_insert_reg_separator(int reg_num, uint32_t *data)
 257 {
 258         int separator_num;
 259         int i;
 260
 261         separator_num = MAX_SEPARATE_NUM - reg_num % REG_NUM_PER_LINE;
 262         for (i = 0; i < separator_num; i++)
 263                 *data++ = SEPARATOR_VALUE;
 264         return separator_num;
 265 }
 266
 267 static int
 268 hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)
 269 {
 270         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 271         uint32_t *origin_data_ptr = data;
 272         uint32_t reg_offset;
 273         int reg_num;
 274         int i, j;
 275
 276         /* fetching per-PF registers values from PF PCIe register space */
 277         reg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);
 278         for (i = 0; i < reg_num; i++)
 279                 *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);
 280         data += hns3_insert_reg_separator(reg_num, data);
 281
 282         if (hns->is_vf)
 283                 reg_num = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);
 284         else
 285                 reg_num = sizeof(common_reg_addrs) / sizeof(uint32_t);
 286         for (i = 0; i < reg_num; i++)
 287                 if (hns->is_vf)
 288                         *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);
 289                 else
 290                         *data++ = hns3_read_dev(hw, common_reg_addrs[i]);
 291         data += hns3_insert_reg_separator(reg_num, data);
 292
 293         reg_num = sizeof(ring_reg_addrs) / sizeof(uint32_t);
 294         for (j = 0; j < hw->tqps_num; j++) {
 295                 reg_offset = hns3_get_tqp_reg_offset(j);
 296                 for (i = 0; i < reg_num; i++)
 297                         *data++ = hns3_read_dev(hw,
 298                                                 ring_reg_addrs[i] + reg_offset);
 299                 data += hns3_insert_reg_separator(reg_num, data);
 300         }
 301
 302         reg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);
 303         for (j = 0; j < hw->intr_tqps_num; j++) {
 304                 reg_offset = hns3_get_tqp_intr_reg_offset(j);
 305                 for (i = 0; i < reg_num; i++)
 306                         *data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] +
 307                                                 reg_offset);
 308                 data += hns3_insert_reg_separator(reg_num, data);
 309         }
 310         return data - origin_data_ptr;
 311 }
 312
 313 int
 314 hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
 315 {
 316 #define HNS3_64_BIT_REG_SIZE (sizeof(uint64_t) / sizeof(uint32_t))
 317         struct hns3_adapter *hns = eth_dev->data->dev_private;
 318         struct hns3_hw *hw = &hns->hw;
 319         uint32_t regs_num_32_bit;
 320         uint32_t regs_num_64_bit;
 321         uint32_t length;
 322         uint32_t *data;
 323         int ret;
 324
 325         if (regs == NULL) {
 326                 hns3_err(hw, "the input parameter regs is NULL!");
 327                 return -EINVAL;
 328         }
 329
 330         ret = hns3_get_regs_length(hw, &length);
 331         if (ret)
 332                 return ret;
 333
 334         data = regs->data;
 335         if (data == NULL) {
 336                 regs->length = length;
 337                 regs->width = sizeof(uint32_t);
 338                 return 0;
 339         }
 340
 341         /* Only full register dump is supported */
 342         if (regs->length && regs->length != length)
 343                 return -ENOTSUP;
 344
 345         /* fetching per-PF registers values from PF PCIe register space */
 346         data += hns3_direct_access_regs(hw, data);
 347
 348         if (hns->is_vf)
 349                 return 0;
 350
 351         ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 352         if (ret) {
 353                 hns3_err(hw, "Get register number failed, ret = %d", ret);
 354                 return ret;
 355         }
 356
 357         /* fetching PF common registers values from firmware */
 358         ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);
 359         if (ret) {
 360                 hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
 361                 return ret;
 362         }
 363         data += regs_num_32_bit;
 364         data += hns3_insert_reg_separator(regs_num_32_bit, data);
 365
 366         ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);
 367         if (ret) {
 368                 hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
 369                 return ret;
 370         }
 371         data += regs_num_64_bit * HNS3_64_BIT_REG_SIZE;
 372         data += hns3_insert_reg_separator(regs_num_64_bit *
 373                                           HNS3_64_BIT_REG_SIZE, data);
 374         return ret;
 375 }