1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
5 #include <rte_bus_pci.h>
6 #include <rte_common.h>
7 #include <rte_cycles.h>
8 #include <rte_geneve.h>
10 #include <ethdev_driver.h>
13 #include <rte_malloc.h>
14 #if defined(RTE_ARCH_ARM64)
15 #include <rte_cpuflags.h>
18 #include "hns3_ethdev.h"
19 #include "hns3_rxtx.h"
20 #include "hns3_regs.h"
21 #include "hns3_logs.h"
23 #define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
24 #define HNS3_RX_RING_PREFETCTH_MASK 3
27 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
31 /* Note: Fake rx queue will not enter here */
32 if (rxq->sw_ring == NULL)
35 if (rxq->rx_rearm_nb == 0) {
36 for (i = 0; i < rxq->nb_rx_desc; i++) {
37 if (rxq->sw_ring[i].mbuf != NULL) {
38 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
39 rxq->sw_ring[i].mbuf = NULL;
43 for (i = rxq->next_to_use;
44 i != rxq->rx_rearm_start;
45 i = (i + 1) % rxq->nb_rx_desc) {
46 if (rxq->sw_ring[i].mbuf != NULL) {
47 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
48 rxq->sw_ring[i].mbuf = NULL;
53 for (i = 0; i < rxq->bulk_mbuf_num; i++)
54 rte_pktmbuf_free_seg(rxq->bulk_mbuf[i]);
55 rxq->bulk_mbuf_num = 0;
57 if (rxq->pkt_first_seg) {
58 rte_pktmbuf_free(rxq->pkt_first_seg);
59 rxq->pkt_first_seg = NULL;
64 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
68 /* Note: Fake tx queue will not enter here */
70 for (i = 0; i < txq->nb_tx_desc; i++) {
71 if (txq->sw_ring[i].mbuf) {
72 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
73 txq->sw_ring[i].mbuf = NULL;
80 hns3_rx_queue_release(void *queue)
82 struct hns3_rx_queue *rxq = queue;
84 hns3_rx_queue_release_mbufs(rxq);
86 rte_memzone_free(rxq->mz);
88 rte_free(rxq->sw_ring);
94 hns3_tx_queue_release(void *queue)
96 struct hns3_tx_queue *txq = queue;
98 hns3_tx_queue_release_mbufs(txq);
100 rte_memzone_free(txq->mz);
102 rte_free(txq->sw_ring);
110 hns3_dev_rx_queue_release(void *queue)
112 struct hns3_rx_queue *rxq = queue;
113 struct hns3_adapter *hns;
119 rte_spinlock_lock(&hns->hw.lock);
120 hns3_rx_queue_release(queue);
121 rte_spinlock_unlock(&hns->hw.lock);
125 hns3_dev_tx_queue_release(void *queue)
127 struct hns3_tx_queue *txq = queue;
128 struct hns3_adapter *hns;
134 rte_spinlock_lock(&hns->hw.lock);
135 hns3_tx_queue_release(queue);
136 rte_spinlock_unlock(&hns->hw.lock);
140 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
142 struct hns3_rx_queue *rxq = queue;
143 struct hns3_adapter *hns;
153 if (hw->fkq_data.rx_queues[idx]) {
154 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
155 hw->fkq_data.rx_queues[idx] = NULL;
158 /* free fake rx queue arrays */
159 if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
160 hw->fkq_data.nb_fake_rx_queues = 0;
161 rte_free(hw->fkq_data.rx_queues);
162 hw->fkq_data.rx_queues = NULL;
167 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
169 struct hns3_tx_queue *txq = queue;
170 struct hns3_adapter *hns;
180 if (hw->fkq_data.tx_queues[idx]) {
181 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
182 hw->fkq_data.tx_queues[idx] = NULL;
185 /* free fake tx queue arrays */
186 if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
187 hw->fkq_data.nb_fake_tx_queues = 0;
188 rte_free(hw->fkq_data.tx_queues);
189 hw->fkq_data.tx_queues = NULL;
194 hns3_free_rx_queues(struct rte_eth_dev *dev)
196 struct hns3_adapter *hns = dev->data->dev_private;
197 struct hns3_fake_queue_data *fkq_data;
198 struct hns3_hw *hw = &hns->hw;
202 nb_rx_q = hw->data->nb_rx_queues;
203 for (i = 0; i < nb_rx_q; i++) {
204 if (dev->data->rx_queues[i]) {
205 hns3_rx_queue_release(dev->data->rx_queues[i]);
206 dev->data->rx_queues[i] = NULL;
210 /* Free fake Rx queues */
211 fkq_data = &hw->fkq_data;
212 for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
213 if (fkq_data->rx_queues[i])
214 hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
219 hns3_free_tx_queues(struct rte_eth_dev *dev)
221 struct hns3_adapter *hns = dev->data->dev_private;
222 struct hns3_fake_queue_data *fkq_data;
223 struct hns3_hw *hw = &hns->hw;
227 nb_tx_q = hw->data->nb_tx_queues;
228 for (i = 0; i < nb_tx_q; i++) {
229 if (dev->data->tx_queues[i]) {
230 hns3_tx_queue_release(dev->data->tx_queues[i]);
231 dev->data->tx_queues[i] = NULL;
235 /* Free fake Tx queues */
236 fkq_data = &hw->fkq_data;
237 for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
238 if (fkq_data->tx_queues[i])
239 hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
244 hns3_free_all_queues(struct rte_eth_dev *dev)
246 hns3_free_rx_queues(dev);
247 hns3_free_tx_queues(dev);
251 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
253 struct rte_mbuf *mbuf;
257 for (i = 0; i < rxq->nb_rx_desc; i++) {
258 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
259 if (unlikely(mbuf == NULL)) {
260 hns3_err(hw, "Failed to allocate RXD[%u] for rx queue!",
262 hns3_rx_queue_release_mbufs(rxq);
266 rte_mbuf_refcnt_set(mbuf, 1);
268 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
270 mbuf->port = rxq->port_id;
272 rxq->sw_ring[i].mbuf = mbuf;
273 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
274 rxq->rx_ring[i].addr = dma_addr;
275 rxq->rx_ring[i].rx.bd_base_info = 0;
282 hns3_buf_size2type(uint32_t buf_size)
288 bd_size_type = HNS3_BD_SIZE_512_TYPE;
291 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
294 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
297 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
304 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
306 uint32_t rx_buf_len = rxq->rx_buf_len;
307 uint64_t dma_addr = rxq->rx_ring_phys_addr;
309 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
310 hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
311 (uint32_t)((dma_addr >> 31) >> 1));
313 hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
314 hns3_buf_size2type(rx_buf_len));
315 hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
316 HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
320 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
322 uint64_t dma_addr = txq->tx_ring_phys_addr;
324 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
325 hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
326 (uint32_t)((dma_addr >> 31) >> 1));
328 hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
329 HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
333 hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw)
335 uint16_t nb_rx_q = hw->data->nb_rx_queues;
336 uint16_t nb_tx_q = hw->data->nb_tx_queues;
337 struct hns3_rx_queue *rxq;
338 struct hns3_tx_queue *txq;
342 pvid_en = hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE;
343 for (i = 0; i < hw->cfg_max_queues; i++) {
345 rxq = hw->data->rx_queues[i];
347 rxq->pvid_sw_discard_en = pvid_en;
350 txq = hw->data->tx_queues[i];
352 txq->pvid_sw_shift_en = pvid_en;
358 hns3_stop_unused_queue(void *tqp_base, enum hns3_ring_type queue_type)
363 reg_offset = queue_type == HNS3_RING_TYPE_TX ?
364 HNS3_RING_TX_EN_REG : HNS3_RING_RX_EN_REG;
365 reg = hns3_read_reg(tqp_base, reg_offset);
366 reg &= ~BIT(HNS3_RING_EN_B);
367 hns3_write_reg(tqp_base, reg_offset, reg);
371 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
373 uint16_t nb_rx_q = hw->data->nb_rx_queues;
374 uint16_t nb_tx_q = hw->data->nb_tx_queues;
375 struct hns3_rx_queue *rxq;
376 struct hns3_tx_queue *txq;
381 for (i = 0; i < hw->cfg_max_queues; i++) {
382 if (hns3_dev_indep_txrx_supported(hw)) {
383 rxq = i < nb_rx_q ? hw->data->rx_queues[i] : NULL;
384 txq = i < nb_tx_q ? hw->data->tx_queues[i] : NULL;
386 tqp_base = (void *)((char *)hw->io_base +
387 hns3_get_tqp_reg_offset(i));
389 * If queue struct is not initialized, it means the
390 * related HW ring has not been initialized yet.
391 * So, these queues should be disabled before enable
392 * the tqps to avoid a HW exception since the queues
393 * are enabled by default.
396 hns3_stop_unused_queue(tqp_base,
399 hns3_stop_unused_queue(tqp_base,
402 rxq = i < nb_rx_q ? hw->data->rx_queues[i] :
403 hw->fkq_data.rx_queues[i - nb_rx_q];
405 tqp_base = rxq->io_base;
408 * This is the master switch that used to control the enabling
409 * of a pair of Tx and Rx queues. Both the Rx and Tx point to
412 rcb_reg = hns3_read_reg(tqp_base, HNS3_RING_EN_REG);
414 rcb_reg |= BIT(HNS3_RING_EN_B);
416 rcb_reg &= ~BIT(HNS3_RING_EN_B);
417 hns3_write_reg(tqp_base, HNS3_RING_EN_REG, rcb_reg);
422 hns3_enable_txq(struct hns3_tx_queue *txq, bool en)
424 struct hns3_hw *hw = &txq->hns->hw;
427 if (hns3_dev_indep_txrx_supported(hw)) {
428 reg = hns3_read_dev(txq, HNS3_RING_TX_EN_REG);
430 reg |= BIT(HNS3_RING_EN_B);
432 reg &= ~BIT(HNS3_RING_EN_B);
433 hns3_write_dev(txq, HNS3_RING_TX_EN_REG, reg);
439 hns3_enable_rxq(struct hns3_rx_queue *rxq, bool en)
441 struct hns3_hw *hw = &rxq->hns->hw;
444 if (hns3_dev_indep_txrx_supported(hw)) {
445 reg = hns3_read_dev(rxq, HNS3_RING_RX_EN_REG);
447 reg |= BIT(HNS3_RING_EN_B);
449 reg &= ~BIT(HNS3_RING_EN_B);
450 hns3_write_dev(rxq, HNS3_RING_RX_EN_REG, reg);
456 hns3_start_all_txqs(struct rte_eth_dev *dev)
458 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
459 struct hns3_tx_queue *txq;
462 for (i = 0; i < dev->data->nb_tx_queues; i++) {
463 txq = hw->data->tx_queues[i];
465 hns3_err(hw, "Tx queue %u not available or setup.", i);
466 goto start_txqs_fail;
469 * Tx queue is enabled by default. Therefore, the Tx queues
470 * needs to be disabled when deferred_start is set. There is
471 * another master switch used to control the enabling of a pair
472 * of Tx and Rx queues. And the master switch is disabled by
475 if (txq->tx_deferred_start)
476 hns3_enable_txq(txq, false);
478 hns3_enable_txq(txq, true);
483 for (j = 0; j < i; j++) {
484 txq = hw->data->tx_queues[j];
485 hns3_enable_txq(txq, false);
491 hns3_start_all_rxqs(struct rte_eth_dev *dev)
493 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
494 struct hns3_rx_queue *rxq;
497 for (i = 0; i < dev->data->nb_rx_queues; i++) {
498 rxq = hw->data->rx_queues[i];
500 hns3_err(hw, "Rx queue %u not available or setup.", i);
501 goto start_rxqs_fail;
504 * Rx queue is enabled by default. Therefore, the Rx queues
505 * needs to be disabled when deferred_start is set. There is
506 * another master switch used to control the enabling of a pair
507 * of Tx and Rx queues. And the master switch is disabled by
510 if (rxq->rx_deferred_start)
511 hns3_enable_rxq(rxq, false);
513 hns3_enable_rxq(rxq, true);
518 for (j = 0; j < i; j++) {
519 rxq = hw->data->rx_queues[j];
520 hns3_enable_rxq(rxq, false);
526 hns3_restore_tqp_enable_state(struct hns3_hw *hw)
528 struct hns3_rx_queue *rxq;
529 struct hns3_tx_queue *txq;
532 for (i = 0; i < hw->data->nb_rx_queues; i++) {
533 rxq = hw->data->rx_queues[i];
535 hns3_enable_rxq(rxq, rxq->enabled);
538 for (i = 0; i < hw->data->nb_tx_queues; i++) {
539 txq = hw->data->tx_queues[i];
541 hns3_enable_txq(txq, txq->enabled);
546 hns3_stop_all_txqs(struct rte_eth_dev *dev)
548 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
549 struct hns3_tx_queue *txq;
552 for (i = 0; i < dev->data->nb_tx_queues; i++) {
553 txq = hw->data->tx_queues[i];
556 hns3_enable_txq(txq, false);
561 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
563 struct hns3_cfg_com_tqp_queue_cmd *req;
564 struct hns3_cmd_desc desc;
567 req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
569 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
570 req->tqp_id = rte_cpu_to_le_16(queue_id);
572 hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
574 ret = hns3_cmd_send(hw, &desc, 1);
576 hns3_err(hw, "TQP enable fail, ret = %d", ret);
582 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
584 struct hns3_reset_tqp_queue_cmd *req;
585 struct hns3_cmd_desc desc;
588 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
590 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
591 req->tqp_id = rte_cpu_to_le_16(queue_id);
592 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
593 ret = hns3_cmd_send(hw, &desc, 1);
595 hns3_err(hw, "send tqp reset cmd error, queue_id = %u, "
596 "ret = %d", queue_id, ret);
602 hns3_get_tqp_reset_status(struct hns3_hw *hw, uint16_t queue_id,
603 uint8_t *reset_status)
605 struct hns3_reset_tqp_queue_cmd *req;
606 struct hns3_cmd_desc desc;
609 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
611 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
612 req->tqp_id = rte_cpu_to_le_16(queue_id);
614 ret = hns3_cmd_send(hw, &desc, 1);
616 hns3_err(hw, "get tqp reset status error, queue_id = %u, "
617 "ret = %d.", queue_id, ret);
620 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
625 hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
627 #define HNS3_TQP_RESET_TRY_MS 200
628 uint16_t wait_time = 0;
629 uint8_t reset_status;
633 * In current version VF is not supported when PF is driven by DPDK
634 * driver, all task queue pairs are mapped to PF function, so PF's queue
635 * id is equals to the global queue id in PF range.
637 ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
639 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
644 /* Wait for tqp hw reset */
645 rte_delay_ms(HNS3_POLL_RESPONE_MS);
646 wait_time += HNS3_POLL_RESPONE_MS;
647 ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status);
653 } while (wait_time < HNS3_TQP_RESET_TRY_MS);
657 hns3_err(hw, "reset tqp timeout, queue_id = %u, ret = %d",
662 ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
664 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
669 hns3_send_reset_tqp_cmd(hw, queue_id, false);
674 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
679 memcpy(msg_data, &queue_id, sizeof(uint16_t));
681 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
682 sizeof(msg_data), true, NULL, 0);
684 hns3_err(hw, "fail to reset tqp, queue_id = %u, ret = %d.",
690 hns3_reset_rcb_cmd(struct hns3_hw *hw, uint8_t *reset_status)
692 struct hns3_reset_cmd *req;
693 struct hns3_cmd_desc desc;
696 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
697 req = (struct hns3_reset_cmd *)desc.data;
698 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_RCB_B, 1);
701 * The start qid should be the global qid of the first tqp of the
702 * function which should be reset in this port. Since our PF not
703 * support take over of VFs, so we only need to reset function 0,
704 * and its start qid is always 0.
706 req->fun_reset_rcb_vqid_start = rte_cpu_to_le_16(0);
707 req->fun_reset_rcb_vqid_num = rte_cpu_to_le_16(hw->cfg_max_queues);
709 ret = hns3_cmd_send(hw, &desc, 1);
711 hns3_err(hw, "fail to send rcb reset cmd, ret = %d.", ret);
715 *reset_status = req->fun_reset_rcb_return_status;
720 hns3pf_reset_all_tqps(struct hns3_hw *hw)
722 #define HNS3_RESET_RCB_NOT_SUPPORT 0U
723 #define HNS3_RESET_ALL_TQP_SUCCESS 1U
724 uint8_t reset_status;
728 ret = hns3_reset_rcb_cmd(hw, &reset_status);
733 * If the firmware version is low, it may not support the rcb reset
734 * which means reset all the tqps at a time. In this case, we should
735 * reset tqps one by one.
737 if (reset_status == HNS3_RESET_RCB_NOT_SUPPORT) {
738 for (i = 0; i < hw->cfg_max_queues; i++) {
739 ret = hns3pf_reset_tqp(hw, i);
742 "fail to reset tqp, queue_id = %d, ret = %d.",
747 } else if (reset_status != HNS3_RESET_ALL_TQP_SUCCESS) {
748 hns3_err(hw, "fail to reset all tqps, reset_status = %u.",
757 hns3vf_reset_all_tqps(struct hns3_hw *hw)
759 #define HNS3VF_RESET_ALL_TQP_DONE 1U
760 uint8_t reset_status;
765 memset(msg_data, 0, sizeof(uint16_t));
766 ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
767 sizeof(msg_data), true, &reset_status,
768 sizeof(reset_status));
770 hns3_err(hw, "fail to send rcb reset mbx, ret = %d.", ret);
774 if (reset_status == HNS3VF_RESET_ALL_TQP_DONE)
778 * If the firmware version or kernel PF version is low, it may not
779 * support the rcb reset which means reset all the tqps at a time.
780 * In this case, we should reset tqps one by one.
782 for (i = 1; i < hw->cfg_max_queues; i++) {
783 ret = hns3vf_reset_tqp(hw, i);
792 hns3_reset_all_tqps(struct hns3_adapter *hns)
794 struct hns3_hw *hw = &hns->hw;
797 /* Disable all queues before reset all queues */
798 for (i = 0; i < hw->cfg_max_queues; i++) {
799 ret = hns3_tqp_enable(hw, i, false);
802 "fail to disable tqps before tqps reset, ret = %d.",
809 return hns3vf_reset_all_tqps(hw);
811 return hns3pf_reset_all_tqps(hw);
815 hns3_send_reset_queue_cmd(struct hns3_hw *hw, uint16_t queue_id,
816 enum hns3_ring_type queue_type, bool enable)
818 struct hns3_reset_tqp_queue_cmd *req;
819 struct hns3_cmd_desc desc;
823 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, false);
825 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
826 req->tqp_id = rte_cpu_to_le_16(queue_id);
827 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
828 req->queue_direction = rte_cpu_to_le_16(queue_direction);
829 hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
831 ret = hns3_cmd_send(hw, &desc, 1);
833 hns3_err(hw, "send queue reset cmd error, queue_id = %u, "
834 "queue_type = %s, ret = %d.", queue_id,
835 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
840 hns3_get_queue_reset_status(struct hns3_hw *hw, uint16_t queue_id,
841 enum hns3_ring_type queue_type,
842 uint8_t *reset_status)
844 struct hns3_reset_tqp_queue_cmd *req;
845 struct hns3_cmd_desc desc;
849 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE_INDEP, true);
851 req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
852 req->tqp_id = rte_cpu_to_le_16(queue_id);
853 queue_direction = queue_type == HNS3_RING_TYPE_TX ? 0 : 1;
854 req->queue_direction = rte_cpu_to_le_16(queue_direction);
856 ret = hns3_cmd_send(hw, &desc, 1);
858 hns3_err(hw, "get queue reset status error, queue_id = %u "
859 "queue_type = %s, ret = %d.", queue_id,
860 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx", ret);
864 *reset_status = hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
869 hns3_reset_queue(struct hns3_hw *hw, uint16_t queue_id,
870 enum hns3_ring_type queue_type)
872 #define HNS3_QUEUE_RESET_TRY_MS 200
873 struct hns3_tx_queue *txq;
874 struct hns3_rx_queue *rxq;
875 uint32_t reset_wait_times;
876 uint32_t max_wait_times;
877 uint8_t reset_status;
880 if (queue_type == HNS3_RING_TYPE_TX) {
881 txq = hw->data->tx_queues[queue_id];
882 hns3_enable_txq(txq, false);
884 rxq = hw->data->rx_queues[queue_id];
885 hns3_enable_rxq(rxq, false);
888 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, true);
890 hns3_err(hw, "send reset queue cmd fail, ret = %d.", ret);
894 reset_wait_times = 0;
895 max_wait_times = HNS3_QUEUE_RESET_TRY_MS / HNS3_POLL_RESPONE_MS;
896 while (reset_wait_times < max_wait_times) {
897 /* Wait for queue hw reset */
898 rte_delay_ms(HNS3_POLL_RESPONE_MS);
899 ret = hns3_get_queue_reset_status(hw, queue_id,
900 queue_type, &reset_status);
902 goto queue_reset_fail;
910 hns3_err(hw, "reset queue timeout, queue_id = %u, "
911 "queue_type = %s", queue_id,
912 queue_type == HNS3_RING_TYPE_TX ? "Tx" : "Rx");
914 goto queue_reset_fail;
917 ret = hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
919 hns3_err(hw, "deassert queue reset fail, ret = %d.", ret);
924 hns3_send_reset_queue_cmd(hw, queue_id, queue_type, false);
929 hns3_get_tqp_intr_reg_offset(uint16_t tqp_intr_id)
933 /* Need an extend offset to config queues > 64 */
934 if (tqp_intr_id < HNS3_MIN_EXT_TQP_INTR_ID)
935 reg_offset = HNS3_TQP_INTR_REG_BASE +
936 tqp_intr_id * HNS3_TQP_INTR_LOW_ORDER_OFFSET;
938 reg_offset = HNS3_TQP_INTR_EXT_REG_BASE +
939 tqp_intr_id / HNS3_MIN_EXT_TQP_INTR_ID *
940 HNS3_TQP_INTR_HIGH_ORDER_OFFSET +
941 tqp_intr_id % HNS3_MIN_EXT_TQP_INTR_ID *
942 HNS3_TQP_INTR_LOW_ORDER_OFFSET;
948 hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
949 uint8_t gl_idx, uint16_t gl_value)
951 uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
952 HNS3_TQP_INTR_GL1_REG,
953 HNS3_TQP_INTR_GL2_REG};
954 uint32_t addr, value;
956 if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
959 addr = offset[gl_idx] + hns3_get_tqp_intr_reg_offset(queue_id);
960 if (hw->intr.gl_unit == HNS3_INTR_COALESCE_GL_UINT_1US)
961 value = gl_value | HNS3_TQP_INTR_GL_UNIT_1US;
963 value = HNS3_GL_USEC_TO_REG(gl_value);
965 hns3_write_dev(hw, addr, value);
969 hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
971 uint32_t addr, value;
973 if (rl_value > HNS3_TQP_INTR_RL_MAX)
976 addr = HNS3_TQP_INTR_RL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
977 value = HNS3_RL_USEC_TO_REG(rl_value);
979 value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
981 hns3_write_dev(hw, addr, value);
985 hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)
990 * int_ql_max == 0 means the hardware does not support QL,
991 * QL regs config is not permitted if QL is not supported,
994 if (hw->intr.int_ql_max == HNS3_INTR_QL_NONE)
997 addr = HNS3_TQP_INTR_TX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
998 hns3_write_dev(hw, addr, ql_value);
1000 addr = HNS3_TQP_INTR_RX_QL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
1001 hns3_write_dev(hw, addr, ql_value);
1005 hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
1007 uint32_t addr, value;
1009 addr = HNS3_TQP_INTR_CTRL_REG + hns3_get_tqp_intr_reg_offset(queue_id);
1012 hns3_write_dev(hw, addr, value);
1016 * Enable all rx queue interrupt when in interrupt rx mode.
1017 * This api was called before enable queue rx&tx (in normal start or reset
1018 * recover scenes), used to fix hardware rx queue interrupt enable was clear
1022 hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
1024 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1025 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1028 if (dev->data->dev_conf.intr_conf.rxq == 0)
1031 for (i = 0; i < nb_rx_q; i++)
1032 hns3_queue_intr_enable(hw, i, en);
1036 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1038 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1039 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1040 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042 if (dev->data->dev_conf.intr_conf.rxq == 0)
1045 hns3_queue_intr_enable(hw, queue_id, true);
1047 return rte_intr_ack(intr_handle);
1051 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1053 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055 if (dev->data->dev_conf.intr_conf.rxq == 0)
1058 hns3_queue_intr_enable(hw, queue_id, false);
1064 hns3_init_rxq(struct hns3_adapter *hns, uint16_t idx)
1066 struct hns3_hw *hw = &hns->hw;
1067 struct hns3_rx_queue *rxq;
1070 PMD_INIT_FUNC_TRACE();
1072 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
1073 ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
1075 hns3_err(hw, "fail to alloc mbuf for Rx queue %u, ret = %d.",
1080 rxq->next_to_use = 0;
1081 rxq->rx_rearm_start = 0;
1082 rxq->rx_free_hold = 0;
1083 rxq->rx_rearm_nb = 0;
1084 rxq->pkt_first_seg = NULL;
1085 rxq->pkt_last_seg = NULL;
1086 hns3_init_rx_queue_hw(rxq);
1087 hns3_rxq_vec_setup(rxq);
1093 hns3_init_fake_rxq(struct hns3_adapter *hns, uint16_t idx)
1095 struct hns3_hw *hw = &hns->hw;
1096 struct hns3_rx_queue *rxq;
1098 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
1099 rxq->next_to_use = 0;
1100 rxq->rx_free_hold = 0;
1101 rxq->rx_rearm_start = 0;
1102 rxq->rx_rearm_nb = 0;
1103 hns3_init_rx_queue_hw(rxq);
1107 hns3_init_txq(struct hns3_tx_queue *txq)
1109 struct hns3_desc *desc;
1113 desc = txq->tx_ring;
1114 for (i = 0; i < txq->nb_tx_desc; i++) {
1115 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1119 txq->next_to_use = 0;
1120 txq->next_to_clean = 0;
1121 txq->tx_bd_ready = txq->nb_tx_desc - 1;
1122 hns3_init_tx_queue_hw(txq);
1126 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
1128 struct hns3_hw *hw = &hns->hw;
1129 struct hns3_tx_queue *txq;
1132 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1133 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
1136 if (!tc_queue->enable)
1139 for (j = 0; j < tc_queue->tqp_count; j++) {
1140 num = tc_queue->tqp_offset + j;
1141 txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
1145 hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
1151 hns3_init_rx_queues(struct hns3_adapter *hns)
1153 struct hns3_hw *hw = &hns->hw;
1154 struct hns3_rx_queue *rxq;
1158 /* Initialize RSS for queues */
1159 ret = hns3_config_rss(hns);
1161 hns3_err(hw, "failed to configure rss, ret = %d.", ret);
1165 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1166 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
1168 hns3_err(hw, "Rx queue %u not available or setup.", i);
1172 if (rxq->rx_deferred_start)
1175 ret = hns3_init_rxq(hns, i);
1177 hns3_err(hw, "failed to init Rx queue %u, ret = %d.", i,
1183 for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++)
1184 hns3_init_fake_rxq(hns, i);
1189 for (j = 0; j < i; j++) {
1190 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
1191 hns3_rx_queue_release_mbufs(rxq);
1198 hns3_init_tx_queues(struct hns3_adapter *hns)
1200 struct hns3_hw *hw = &hns->hw;
1201 struct hns3_tx_queue *txq;
1204 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1205 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
1207 hns3_err(hw, "Tx queue %u not available or setup.", i);
1211 if (txq->tx_deferred_start)
1216 for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
1217 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
1220 hns3_init_tx_ring_tc(hns);
1227 * Note: just init and setup queues, and don't enable tqps.
1230 hns3_init_queues(struct hns3_adapter *hns, bool reset_queue)
1232 struct hns3_hw *hw = &hns->hw;
1236 ret = hns3_reset_all_tqps(hns);
1238 hns3_err(hw, "failed to reset all queues, ret = %d.",
1244 ret = hns3_init_rx_queues(hns);
1246 hns3_err(hw, "failed to init rx queues, ret = %d.", ret);
1250 ret = hns3_init_tx_queues(hns);
1252 hns3_dev_release_mbufs(hns);
1253 hns3_err(hw, "failed to init tx queues, ret = %d.", ret);
1260 hns3_start_tqps(struct hns3_hw *hw)
1262 struct hns3_tx_queue *txq;
1263 struct hns3_rx_queue *rxq;
1266 hns3_enable_all_queues(hw, true);
1268 for (i = 0; i < hw->data->nb_tx_queues; i++) {
1269 txq = hw->data->tx_queues[i];
1271 hw->data->tx_queue_state[i] =
1272 RTE_ETH_QUEUE_STATE_STARTED;
1275 for (i = 0; i < hw->data->nb_rx_queues; i++) {
1276 rxq = hw->data->rx_queues[i];
1278 hw->data->rx_queue_state[i] =
1279 RTE_ETH_QUEUE_STATE_STARTED;
1284 hns3_stop_tqps(struct hns3_hw *hw)
1288 hns3_enable_all_queues(hw, false);
1290 for (i = 0; i < hw->data->nb_tx_queues; i++)
1291 hw->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1293 for (i = 0; i < hw->data->nb_rx_queues; i++)
1294 hw->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
1298 * Iterate over all Rx Queue, and call the callback() function for each Rx
1302 * The target eth dev.
1303 * @param[in] callback
1304 * The function to call for each queue.
1305 * if callback function return nonzero will stop iterate and return it's value
1307 * The arguments to provide the callback function with.
1310 * 0 on success, otherwise with errno set.
1313 hns3_rxq_iterate(struct rte_eth_dev *dev,
1314 int (*callback)(struct hns3_rx_queue *, void *), void *arg)
1319 if (dev->data->rx_queues == NULL)
1322 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1323 ret = callback(dev->data->rx_queues[i], arg);
1332 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
1333 struct hns3_queue_info *q_info)
1335 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1336 const struct rte_memzone *rx_mz;
1337 struct hns3_rx_queue *rxq;
1338 unsigned int rx_desc;
1340 rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
1341 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1343 hns3_err(hw, "Failed to allocate memory for No.%u rx ring!",
1348 /* Allocate rx ring hardware descriptors. */
1349 rxq->queue_id = q_info->idx;
1350 rxq->nb_rx_desc = q_info->nb_desc;
1353 * Allocate a litter more memory because rx vector functions
1354 * don't check boundaries each time.
1356 rx_desc = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1357 sizeof(struct hns3_desc);
1358 rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1359 rx_desc, HNS3_RING_BASE_ALIGN,
1361 if (rx_mz == NULL) {
1362 hns3_err(hw, "Failed to reserve DMA memory for No.%u rx ring!",
1364 hns3_rx_queue_release(rxq);
1368 rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
1369 rxq->rx_ring_phys_addr = rx_mz->iova;
1371 hns3_dbg(hw, "No.%u rx descriptors iova 0x%" PRIx64, q_info->idx,
1372 rxq->rx_ring_phys_addr);
1378 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1379 uint16_t nb_desc, unsigned int socket_id)
1381 struct hns3_adapter *hns = dev->data->dev_private;
1382 struct hns3_hw *hw = &hns->hw;
1383 struct hns3_queue_info q_info;
1384 struct hns3_rx_queue *rxq;
1387 if (hw->fkq_data.rx_queues[idx]) {
1388 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
1389 hw->fkq_data.rx_queues[idx] = NULL;
1393 q_info.socket_id = socket_id;
1394 q_info.nb_desc = nb_desc;
1395 q_info.type = "hns3 fake RX queue";
1396 q_info.ring_name = "rx_fake_ring";
1397 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1399 hns3_err(hw, "Failed to setup No.%u fake rx ring.", idx);
1403 /* Don't need alloc sw_ring, because upper applications don't use it */
1404 rxq->sw_ring = NULL;
1407 rxq->rx_deferred_start = false;
1408 rxq->port_id = dev->data->port_id;
1409 rxq->configured = true;
1410 nb_rx_q = dev->data->nb_rx_queues;
1411 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1412 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
1413 rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
1415 rte_spinlock_lock(&hw->lock);
1416 hw->fkq_data.rx_queues[idx] = rxq;
1417 rte_spinlock_unlock(&hw->lock);
1423 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
1424 struct hns3_queue_info *q_info)
1426 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1427 const struct rte_memzone *tx_mz;
1428 struct hns3_tx_queue *txq;
1429 struct hns3_desc *desc;
1430 unsigned int tx_desc;
1433 txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
1434 RTE_CACHE_LINE_SIZE, q_info->socket_id);
1436 hns3_err(hw, "Failed to allocate memory for No.%u tx ring!",
1441 /* Allocate tx ring hardware descriptors. */
1442 txq->queue_id = q_info->idx;
1443 txq->nb_tx_desc = q_info->nb_desc;
1444 tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
1445 tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
1446 tx_desc, HNS3_RING_BASE_ALIGN,
1448 if (tx_mz == NULL) {
1449 hns3_err(hw, "Failed to reserve DMA memory for No.%u tx ring!",
1451 hns3_tx_queue_release(txq);
1455 txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
1456 txq->tx_ring_phys_addr = tx_mz->iova;
1458 hns3_dbg(hw, "No.%u tx descriptors iova 0x%" PRIx64, q_info->idx,
1459 txq->tx_ring_phys_addr);
1462 desc = txq->tx_ring;
1463 for (i = 0; i < txq->nb_tx_desc; i++) {
1464 desc->tx.tp_fe_sc_vld_ra_ri = 0;
1472 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
1473 uint16_t nb_desc, unsigned int socket_id)
1475 struct hns3_adapter *hns = dev->data->dev_private;
1476 struct hns3_hw *hw = &hns->hw;
1477 struct hns3_queue_info q_info;
1478 struct hns3_tx_queue *txq;
1481 if (hw->fkq_data.tx_queues[idx] != NULL) {
1482 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
1483 hw->fkq_data.tx_queues[idx] = NULL;
1487 q_info.socket_id = socket_id;
1488 q_info.nb_desc = nb_desc;
1489 q_info.type = "hns3 fake TX queue";
1490 q_info.ring_name = "tx_fake_ring";
1491 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1493 hns3_err(hw, "Failed to setup No.%u fake tx ring.", idx);
1497 /* Don't need alloc sw_ring, because upper applications don't use it */
1498 txq->sw_ring = NULL;
1502 txq->tx_deferred_start = false;
1503 txq->port_id = dev->data->port_id;
1504 txq->configured = true;
1505 nb_tx_q = dev->data->nb_tx_queues;
1506 txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1507 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
1509 rte_spinlock_lock(&hw->lock);
1510 hw->fkq_data.tx_queues[idx] = txq;
1511 rte_spinlock_unlock(&hw->lock);
1517 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1519 uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
1523 if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
1524 /* first time configuration */
1526 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
1527 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
1528 RTE_CACHE_LINE_SIZE);
1529 if (hw->fkq_data.rx_queues == NULL) {
1530 hw->fkq_data.nb_fake_rx_queues = 0;
1533 } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
1535 rxq = hw->fkq_data.rx_queues;
1536 for (i = nb_queues; i < old_nb_queues; i++)
1537 hns3_dev_rx_queue_release(rxq[i]);
1539 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
1540 RTE_CACHE_LINE_SIZE);
1543 if (nb_queues > old_nb_queues) {
1544 uint16_t new_qs = nb_queues - old_nb_queues;
1545 memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
1548 hw->fkq_data.rx_queues = rxq;
1549 } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
1550 rxq = hw->fkq_data.rx_queues;
1551 for (i = nb_queues; i < old_nb_queues; i++)
1552 hns3_dev_rx_queue_release(rxq[i]);
1554 rte_free(hw->fkq_data.rx_queues);
1555 hw->fkq_data.rx_queues = NULL;
1558 hw->fkq_data.nb_fake_rx_queues = nb_queues;
1564 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
1566 uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
1570 if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
1571 /* first time configuration */
1573 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
1574 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
1575 RTE_CACHE_LINE_SIZE);
1576 if (hw->fkq_data.tx_queues == NULL) {
1577 hw->fkq_data.nb_fake_tx_queues = 0;
1580 } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1582 txq = hw->fkq_data.tx_queues;
1583 for (i = nb_queues; i < old_nb_queues; i++)
1584 hns3_dev_tx_queue_release(txq[i]);
1585 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1586 RTE_CACHE_LINE_SIZE);
1589 if (nb_queues > old_nb_queues) {
1590 uint16_t new_qs = nb_queues - old_nb_queues;
1591 memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1594 hw->fkq_data.tx_queues = txq;
1595 } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1596 txq = hw->fkq_data.tx_queues;
1597 for (i = nb_queues; i < old_nb_queues; i++)
1598 hns3_dev_tx_queue_release(txq[i]);
1600 rte_free(hw->fkq_data.tx_queues);
1601 hw->fkq_data.tx_queues = NULL;
1603 hw->fkq_data.nb_fake_tx_queues = nb_queues;
1609 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1612 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613 uint16_t rx_need_add_nb_q;
1614 uint16_t tx_need_add_nb_q;
1619 /* Setup new number of fake RX/TX queues and reconfigure device. */
1620 rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1621 tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1622 ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1624 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1628 ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1630 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1631 goto cfg_fake_tx_q_fail;
1634 /* Allocate and set up fake RX queue per Ethernet port. */
1635 port_id = hw->data->port_id;
1636 for (q = 0; q < rx_need_add_nb_q; q++) {
1637 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1638 rte_eth_dev_socket_id(port_id));
1640 goto setup_fake_rx_q_fail;
1643 /* Allocate and set up fake TX queue per Ethernet port. */
1644 for (q = 0; q < tx_need_add_nb_q; q++) {
1645 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1646 rte_eth_dev_socket_id(port_id));
1648 goto setup_fake_tx_q_fail;
1653 setup_fake_tx_q_fail:
1654 setup_fake_rx_q_fail:
1655 (void)hns3_fake_tx_queue_config(hw, 0);
1657 (void)hns3_fake_rx_queue_config(hw, 0);
1663 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1665 struct rte_eth_dev_data *dev_data = hns->hw.data;
1666 struct hns3_rx_queue *rxq;
1667 struct hns3_tx_queue *txq;
1670 if (dev_data->rx_queues)
1671 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1672 rxq = dev_data->rx_queues[i];
1675 hns3_rx_queue_release_mbufs(rxq);
1678 if (dev_data->tx_queues)
1679 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1680 txq = dev_data->tx_queues[i];
1683 hns3_tx_queue_release_mbufs(txq);
1688 hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len)
1690 uint16_t vld_buf_size;
1691 uint16_t num_hw_specs;
1695 * hns3 network engine only support to set 4 typical specification, and
1696 * different buffer size will affect the max packet_len and the max
1697 * number of segmentation when hw gro is turned on in receive side. The
1698 * relationship between them is as follows:
1699 * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg
1700 * ---------------------|-------------------|----------------
1701 * HNS3_4K_BD_BUF_SIZE | 60KB | 15
1702 * HNS3_2K_BD_BUF_SIZE | 62KB | 31
1703 * HNS3_1K_BD_BUF_SIZE | 63KB | 63
1704 * HNS3_512_BD_BUF_SIZE | 31.5KB | 63
1706 static const uint16_t hw_rx_buf_size[] = {
1707 HNS3_4K_BD_BUF_SIZE,
1708 HNS3_2K_BD_BUF_SIZE,
1709 HNS3_1K_BD_BUF_SIZE,
1710 HNS3_512_BD_BUF_SIZE
1713 vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) -
1714 RTE_PKTMBUF_HEADROOM);
1715 if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE)
1718 num_hw_specs = RTE_DIM(hw_rx_buf_size);
1719 for (i = 0; i < num_hw_specs; i++) {
1720 if (vld_buf_size >= hw_rx_buf_size[i]) {
1721 *rx_buf_len = hw_rx_buf_size[i];
1729 hns3_rxq_conf_runtime_check(struct hns3_hw *hw, uint16_t buf_size,
1732 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1733 struct rte_eth_rxmode *rxmode = &hw->data->dev_conf.rxmode;
1734 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
1735 uint16_t min_vec_bds;
1738 * HNS3 hardware network engine set scattered as default. If the driver
1739 * is not work in scattered mode and the pkts greater than buf_size
1740 * but smaller than max_rx_pkt_len will be distributed to multiple BDs.
1741 * Driver cannot handle this situation.
1743 if (!hw->data->scattered_rx && rxmode->max_rx_pkt_len > buf_size) {
1744 hns3_err(hw, "max_rx_pkt_len is not allowed to be set greater "
1745 "than rx_buf_len if scattered is off.");
1749 if (pkt_burst == hns3_recv_pkts_vec) {
1750 min_vec_bds = HNS3_DEFAULT_RXQ_REARM_THRESH +
1751 HNS3_DEFAULT_RX_BURST;
1752 if (nb_desc < min_vec_bds ||
1753 nb_desc % HNS3_DEFAULT_RXQ_REARM_THRESH) {
1754 hns3_err(hw, "if Rx burst mode is vector, "
1755 "number of descriptor is required to be "
1756 "bigger than min vector bds:%u, and could be "
1757 "divided by rxq rearm thresh:%u.",
1758 min_vec_bds, HNS3_DEFAULT_RXQ_REARM_THRESH);
1766 hns3_rx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_rxconf *conf,
1767 struct rte_mempool *mp, uint16_t nb_desc,
1772 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1773 nb_desc % HNS3_ALIGN_RING_DESC) {
1774 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1779 if (conf->rx_drop_en == 0)
1780 hns3_warn(hw, "if no descriptors available, packets are always "
1781 "dropped and rx_drop_en (1) is fixed on");
1783 if (hns3_rx_buf_len_calc(mp, buf_size)) {
1784 hns3_err(hw, "rxq mbufs' data room size (%u) is not enough! "
1785 "minimal data room size (%u).",
1786 rte_pktmbuf_data_room_size(mp),
1787 HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM);
1791 if (hw->data->dev_started) {
1792 ret = hns3_rxq_conf_runtime_check(hw, *buf_size, nb_desc);
1794 hns3_err(hw, "Rx queue runtime setup fail.");
1803 hns3_get_tqp_reg_offset(uint16_t queue_id)
1805 uint32_t reg_offset;
1807 /* Need an extend offset to config queue > 1024 */
1808 if (queue_id < HNS3_MIN_EXTEND_QUEUE_ID)
1809 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE;
1811 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET +
1812 (queue_id - HNS3_MIN_EXTEND_QUEUE_ID) *
1819 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1820 unsigned int socket_id, const struct rte_eth_rxconf *conf,
1821 struct rte_mempool *mp)
1823 struct hns3_adapter *hns = dev->data->dev_private;
1824 struct hns3_hw *hw = &hns->hw;
1825 struct hns3_queue_info q_info;
1826 struct hns3_rx_queue *rxq;
1827 uint16_t rx_buf_size;
1831 ret = hns3_rx_queue_conf_check(hw, conf, mp, nb_desc, &rx_buf_size);
1835 if (dev->data->rx_queues[idx]) {
1836 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1837 dev->data->rx_queues[idx] = NULL;
1841 q_info.socket_id = socket_id;
1842 q_info.nb_desc = nb_desc;
1843 q_info.type = "hns3 RX queue";
1844 q_info.ring_name = "rx_ring";
1846 rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1849 "Failed to alloc mem and reserve DMA mem for rx ring!");
1854 rxq->ptype_tbl = &hns->ptype_tbl;
1856 rxq->rx_free_thresh = (conf->rx_free_thresh > 0) ?
1857 conf->rx_free_thresh : HNS3_DEFAULT_RX_FREE_THRESH;
1859 rxq->rx_deferred_start = conf->rx_deferred_start;
1860 if (rxq->rx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
1861 hns3_warn(hw, "deferred start is not supported.");
1862 rxq->rx_deferred_start = false;
1865 rx_entry_len = (rxq->nb_rx_desc + HNS3_DEFAULT_RX_BURST) *
1866 sizeof(struct hns3_entry);
1867 rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1868 RTE_CACHE_LINE_SIZE, socket_id);
1869 if (rxq->sw_ring == NULL) {
1870 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1871 hns3_rx_queue_release(rxq);
1875 rxq->next_to_use = 0;
1876 rxq->rx_free_hold = 0;
1877 rxq->rx_rearm_start = 0;
1878 rxq->rx_rearm_nb = 0;
1879 rxq->pkt_first_seg = NULL;
1880 rxq->pkt_last_seg = NULL;
1881 rxq->port_id = dev->data->port_id;
1883 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
1884 * the pvid_sw_discard_en in the queue struct should not be changed,
1885 * because PVID-related operations do not need to be processed by PMD
1886 * driver. For hns3 VF device, whether it needs to process PVID depends
1887 * on the configuration of PF kernel mode netdevice driver. And the
1888 * related PF configuration is delivered through the mailbox and finally
1889 * reflectd in port_base_vlan_cfg.
1891 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1892 rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
1893 HNS3_PORT_BASE_VLAN_ENABLE;
1895 rxq->pvid_sw_discard_en = false;
1896 rxq->ptype_en = hns3_dev_rxd_adv_layout_supported(hw) ? true : false;
1897 rxq->configured = true;
1898 rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1899 idx * HNS3_TQP_REG_SIZE);
1900 rxq->io_base = (void *)((char *)hw->io_base +
1901 hns3_get_tqp_reg_offset(idx));
1902 rxq->io_head_reg = (volatile void *)((char *)rxq->io_base +
1903 HNS3_RING_RX_HEAD_REG);
1904 rxq->rx_buf_len = rx_buf_size;
1905 memset(&rxq->basic_stats, 0, sizeof(struct hns3_rx_basic_stats));
1906 memset(&rxq->err_stats, 0, sizeof(struct hns3_rx_bd_errors_stats));
1907 memset(&rxq->dfx_stats, 0, sizeof(struct hns3_rx_dfx_stats));
1909 /* CRC len set here is used for amending packet length */
1910 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1911 rxq->crc_len = RTE_ETHER_CRC_LEN;
1915 rxq->bulk_mbuf_num = 0;
1917 rte_spinlock_lock(&hw->lock);
1918 dev->data->rx_queues[idx] = rxq;
1919 rte_spinlock_unlock(&hw->lock);
1925 hns3_rx_scattered_reset(struct rte_eth_dev *dev)
1927 struct hns3_adapter *hns = dev->data->dev_private;
1928 struct hns3_hw *hw = &hns->hw;
1931 dev->data->scattered_rx = false;
1935 hns3_rx_scattered_calc(struct rte_eth_dev *dev)
1937 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1938 struct hns3_adapter *hns = dev->data->dev_private;
1939 struct hns3_hw *hw = &hns->hw;
1940 struct hns3_rx_queue *rxq;
1943 if (dev->data->rx_queues == NULL)
1946 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
1947 rxq = dev->data->rx_queues[queue_id];
1948 if (hw->rx_buf_len == 0)
1949 hw->rx_buf_len = rxq->rx_buf_len;
1951 hw->rx_buf_len = RTE_MIN(hw->rx_buf_len,
1955 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SCATTER ||
1956 dev_conf->rxmode.max_rx_pkt_len > hw->rx_buf_len)
1957 dev->data->scattered_rx = true;
1961 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1963 static const uint32_t ptypes[] = {
1965 RTE_PTYPE_L2_ETHER_LLDP,
1966 RTE_PTYPE_L2_ETHER_ARP,
1968 RTE_PTYPE_L3_IPV4_EXT,
1970 RTE_PTYPE_L3_IPV6_EXT,
1976 RTE_PTYPE_TUNNEL_GRE,
1977 RTE_PTYPE_INNER_L2_ETHER,
1978 RTE_PTYPE_INNER_L3_IPV4,
1979 RTE_PTYPE_INNER_L3_IPV6,
1980 RTE_PTYPE_INNER_L3_IPV4_EXT,
1981 RTE_PTYPE_INNER_L3_IPV6_EXT,
1982 RTE_PTYPE_INNER_L4_UDP,
1983 RTE_PTYPE_INNER_L4_TCP,
1984 RTE_PTYPE_INNER_L4_SCTP,
1985 RTE_PTYPE_INNER_L4_ICMP,
1986 RTE_PTYPE_TUNNEL_VXLAN,
1987 RTE_PTYPE_TUNNEL_NVGRE,
1990 static const uint32_t adv_layout_ptypes[] = {
1992 RTE_PTYPE_L2_ETHER_TIMESYNC,
1993 RTE_PTYPE_L2_ETHER_LLDP,
1994 RTE_PTYPE_L2_ETHER_ARP,
1995 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1996 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1998 RTE_PTYPE_L4_NONFRAG,
2004 RTE_PTYPE_TUNNEL_GRE,
2005 RTE_PTYPE_TUNNEL_GRENAT,
2006 RTE_PTYPE_INNER_L2_ETHER,
2007 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2008 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2009 RTE_PTYPE_INNER_L4_FRAG,
2010 RTE_PTYPE_INNER_L4_ICMP,
2011 RTE_PTYPE_INNER_L4_NONFRAG,
2012 RTE_PTYPE_INNER_L4_UDP,
2013 RTE_PTYPE_INNER_L4_TCP,
2014 RTE_PTYPE_INNER_L4_SCTP,
2015 RTE_PTYPE_INNER_L4_ICMP,
2018 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020 if (dev->rx_pkt_burst == hns3_recv_pkts ||
2021 dev->rx_pkt_burst == hns3_recv_scattered_pkts ||
2022 dev->rx_pkt_burst == hns3_recv_pkts_vec ||
2023 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) {
2024 if (hns3_dev_rxd_adv_layout_supported(hw))
2025 return adv_layout_ptypes;
2034 hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
2036 tbl->l3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
2037 tbl->l3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
2038 tbl->l3table[2] = RTE_PTYPE_L2_ETHER_ARP;
2039 tbl->l3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
2040 tbl->l3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
2041 tbl->l3table[6] = RTE_PTYPE_L2_ETHER_LLDP;
2043 tbl->l4table[0] = RTE_PTYPE_L4_UDP;
2044 tbl->l4table[1] = RTE_PTYPE_L4_TCP;
2045 tbl->l4table[2] = RTE_PTYPE_TUNNEL_GRE;
2046 tbl->l4table[3] = RTE_PTYPE_L4_SCTP;
2047 tbl->l4table[4] = RTE_PTYPE_L4_IGMP;
2048 tbl->l4table[5] = RTE_PTYPE_L4_ICMP;
2052 hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)
2054 tbl->inner_l3table[0] = RTE_PTYPE_INNER_L2_ETHER |
2055 RTE_PTYPE_INNER_L3_IPV4;
2056 tbl->inner_l3table[1] = RTE_PTYPE_INNER_L2_ETHER |
2057 RTE_PTYPE_INNER_L3_IPV6;
2058 /* There is not a ptype for inner ARP/RARP */
2059 tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN;
2060 tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN;
2061 tbl->inner_l3table[4] = RTE_PTYPE_INNER_L2_ETHER |
2062 RTE_PTYPE_INNER_L3_IPV4_EXT;
2063 tbl->inner_l3table[5] = RTE_PTYPE_INNER_L2_ETHER |
2064 RTE_PTYPE_INNER_L3_IPV6_EXT;
2066 tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP;
2067 tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP;
2068 /* There is not a ptype for inner GRE */
2069 tbl->inner_l4table[2] = RTE_PTYPE_UNKNOWN;
2070 tbl->inner_l4table[3] = RTE_PTYPE_INNER_L4_SCTP;
2071 /* There is not a ptype for inner IGMP */
2072 tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN;
2073 tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP;
2075 tbl->ol3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
2076 tbl->ol3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
2077 tbl->ol3table[2] = RTE_PTYPE_UNKNOWN;
2078 tbl->ol3table[3] = RTE_PTYPE_UNKNOWN;
2079 tbl->ol3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT;
2080 tbl->ol3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT;
2082 tbl->ol4table[0] = RTE_PTYPE_UNKNOWN;
2083 tbl->ol4table[1] = RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN;
2084 tbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;
2088 hns3_init_adv_layout_ptype(struct hns3_ptype_table *tbl)
2090 uint32_t *ptype = tbl->ptype;
2093 ptype[1] = RTE_PTYPE_L2_ETHER_ARP;
2094 ptype[3] = RTE_PTYPE_L2_ETHER_LLDP;
2095 ptype[8] = RTE_PTYPE_L2_ETHER_TIMESYNC;
2097 /* Non-tunnel IPv4 */
2098 ptype[17] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2100 ptype[18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2101 RTE_PTYPE_L4_NONFRAG;
2102 ptype[19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2104 ptype[20] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2106 ptype[21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2107 RTE_PTYPE_TUNNEL_GRE;
2108 ptype[22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2110 ptype[23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2112 ptype[24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2114 /* The next ptype is PTP over IPv4 + UDP */
2115 ptype[25] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2118 /* IPv4 --> GRE/Teredo/VXLAN */
2119 ptype[29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2120 RTE_PTYPE_TUNNEL_GRENAT;
2121 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2122 ptype[30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2123 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;
2125 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2126 ptype[31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2127 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2128 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2129 RTE_PTYPE_INNER_L4_FRAG;
2130 ptype[32] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2131 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2132 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2133 RTE_PTYPE_INNER_L4_NONFRAG;
2134 ptype[33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2135 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2136 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2137 RTE_PTYPE_INNER_L4_UDP;
2138 ptype[34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2139 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2140 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2141 RTE_PTYPE_INNER_L4_TCP;
2142 ptype[35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2143 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2145 RTE_PTYPE_INNER_L4_SCTP;
2146 /* The next ptype's inner L4 is IGMP */
2147 ptype[36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2148 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2149 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
2150 ptype[37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2151 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2152 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2153 RTE_PTYPE_INNER_L4_ICMP;
2155 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2156 ptype[39] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2157 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2158 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2159 RTE_PTYPE_INNER_L4_FRAG;
2160 ptype[40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2161 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2162 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2163 RTE_PTYPE_INNER_L4_NONFRAG;
2164 ptype[41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2165 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2166 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2167 RTE_PTYPE_INNER_L4_UDP;
2168 ptype[42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2169 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2170 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2171 RTE_PTYPE_INNER_L4_TCP;
2172 ptype[43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2173 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2174 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2175 RTE_PTYPE_INNER_L4_SCTP;
2176 /* The next ptype's inner L4 is IGMP */
2177 ptype[44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2178 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
2180 ptype[45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2181 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2182 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2183 RTE_PTYPE_INNER_L4_ICMP;
2185 /* Non-tunnel IPv6 */
2186 ptype[111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2188 ptype[112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2189 RTE_PTYPE_L4_NONFRAG;
2190 ptype[113] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2192 ptype[114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2194 ptype[115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2195 RTE_PTYPE_TUNNEL_GRE;
2196 ptype[116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2198 ptype[117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2200 ptype[118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2202 /* Special for PTP over IPv6 + UDP */
2203 ptype[119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2206 /* IPv6 --> GRE/Teredo/VXLAN */
2207 ptype[123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2208 RTE_PTYPE_TUNNEL_GRENAT;
2209 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2210 ptype[124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2211 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;
2213 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2214 ptype[125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2215 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2216 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2217 RTE_PTYPE_INNER_L4_FRAG;
2218 ptype[126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2219 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2220 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2221 RTE_PTYPE_INNER_L4_NONFRAG;
2222 ptype[127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2223 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2224 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2225 RTE_PTYPE_INNER_L4_UDP;
2226 ptype[128] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2227 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2228 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2229 RTE_PTYPE_INNER_L4_TCP;
2230 ptype[129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2231 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2232 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2233 RTE_PTYPE_INNER_L4_SCTP;
2234 /* The next ptype's inner L4 is IGMP */
2235 ptype[130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2236 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2237 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
2238 ptype[131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2239 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2240 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2241 RTE_PTYPE_INNER_L4_ICMP;
2243 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2244 ptype[133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2245 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2246 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2247 RTE_PTYPE_INNER_L4_FRAG;
2248 ptype[134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2249 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2250 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2251 RTE_PTYPE_INNER_L4_NONFRAG;
2252 ptype[135] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2253 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2255 RTE_PTYPE_INNER_L4_UDP;
2256 ptype[136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2257 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2258 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2259 RTE_PTYPE_INNER_L4_TCP;
2260 ptype[137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2261 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2262 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2263 RTE_PTYPE_INNER_L4_SCTP;
2264 /* The next ptype's inner L4 is IGMP */
2265 ptype[138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2266 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
2268 ptype[139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2269 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2270 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2271 RTE_PTYPE_INNER_L4_ICMP;
2275 hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)
2277 struct hns3_adapter *hns = dev->data->dev_private;
2278 struct hns3_ptype_table *tbl = &hns->ptype_tbl;
2280 memset(tbl, 0, sizeof(*tbl));
2282 hns3_init_non_tunnel_ptype_tbl(tbl);
2283 hns3_init_tunnel_ptype_tbl(tbl);
2284 hns3_init_adv_layout_ptype(tbl);
2288 hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb,
2289 uint32_t l234_info, const struct hns3_desc *rxd)
2291 #define HNS3_STRP_STATUS_NUM 0x4
2293 #define HNS3_NO_STRP_VLAN_VLD 0x0
2294 #define HNS3_INNER_STRP_VLAN_VLD 0x1
2295 #define HNS3_OUTER_STRP_VLAN_VLD 0x2
2296 uint32_t strip_status;
2297 uint32_t report_mode;
2300 * Since HW limitation, the vlan tag will always be inserted into RX
2301 * descriptor when strip the tag from packet, driver needs to determine
2302 * reporting which tag to mbuf according to the PVID configuration
2303 * and vlan striped status.
2305 static const uint32_t report_type[][HNS3_STRP_STATUS_NUM] = {
2307 HNS3_NO_STRP_VLAN_VLD,
2308 HNS3_OUTER_STRP_VLAN_VLD,
2309 HNS3_INNER_STRP_VLAN_VLD,
2310 HNS3_OUTER_STRP_VLAN_VLD
2313 HNS3_NO_STRP_VLAN_VLD,
2314 HNS3_NO_STRP_VLAN_VLD,
2315 HNS3_NO_STRP_VLAN_VLD,
2316 HNS3_INNER_STRP_VLAN_VLD
2319 strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
2320 HNS3_RXD_STRP_TAGP_S);
2321 report_mode = report_type[rxq->pvid_sw_discard_en][strip_status];
2322 switch (report_mode) {
2323 case HNS3_NO_STRP_VLAN_VLD:
2326 case HNS3_INNER_STRP_VLAN_VLD:
2327 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2328 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.vlan_tag);
2330 case HNS3_OUTER_STRP_VLAN_VLD:
2331 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2332 mb->vlan_tci = rte_le_to_cpu_16(rxd->rx.ot_vlan_tag);
2341 recalculate_data_len(struct rte_mbuf *first_seg, struct rte_mbuf *last_seg,
2342 struct rte_mbuf *rxm, struct hns3_rx_queue *rxq,
2345 uint8_t crc_len = rxq->crc_len;
2347 if (data_len <= crc_len) {
2348 rte_pktmbuf_free_seg(rxm);
2349 first_seg->nb_segs--;
2350 last_seg->data_len = (uint16_t)(last_seg->data_len -
2351 (crc_len - data_len));
2352 last_seg->next = NULL;
2354 rxm->data_len = (uint16_t)(data_len - crc_len);
2357 static inline struct rte_mbuf *
2358 hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)
2362 if (likely(rxq->bulk_mbuf_num > 0))
2363 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2365 ret = rte_mempool_get_bulk(rxq->mb_pool, (void **)rxq->bulk_mbuf,
2366 HNS3_BULK_ALLOC_MBUF_NUM);
2367 if (likely(ret == 0)) {
2368 rxq->bulk_mbuf_num = HNS3_BULK_ALLOC_MBUF_NUM;
2369 return rxq->bulk_mbuf[--rxq->bulk_mbuf_num];
2371 return rte_mbuf_raw_alloc(rxq->mb_pool);
2375 hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf,
2376 volatile struct hns3_desc *rxd)
2378 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns);
2379 uint64_t timestamp = rte_le_to_cpu_64(rxd->timestamp);
2381 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;
2382 if (hns3_timestamp_rx_dynflag > 0) {
2383 *RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset,
2384 rte_mbuf_timestamp_t *) = timestamp;
2385 mbuf->ol_flags |= hns3_timestamp_rx_dynflag;
2388 pf->rx_timestamp = timestamp;
2392 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2394 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2395 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2396 struct hns3_rx_queue *rxq; /* RX queue */
2397 struct hns3_entry *sw_ring;
2398 struct hns3_entry *rxe;
2399 struct hns3_desc rxd;
2400 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2401 struct rte_mbuf *rxm;
2402 uint32_t bd_base_info;
2415 rx_ring = rxq->rx_ring;
2416 sw_ring = rxq->sw_ring;
2417 rx_id = rxq->next_to_use;
2419 while (nb_rx < nb_pkts) {
2420 rxdp = &rx_ring[rx_id];
2421 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2422 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2425 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2426 (1u << HNS3_RXD_VLD_B)];
2428 nmb = hns3_rx_alloc_buffer(rxq);
2429 if (unlikely(nmb == NULL)) {
2432 port_id = rxq->port_id;
2433 rte_eth_devices[port_id].data->rx_mbuf_alloc_failed++;
2438 rxe = &sw_ring[rx_id];
2440 if (unlikely(rx_id == rxq->nb_rx_desc))
2443 rte_prefetch0(sw_ring[rx_id].mbuf);
2444 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2445 rte_prefetch0(&rx_ring[rx_id]);
2446 rte_prefetch0(&sw_ring[rx_id]);
2453 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
2454 hns3_rx_ptp_timestamp_handle(rxq, rxm, rxdp);
2456 dma_addr = rte_mbuf_data_iova_default(nmb);
2457 rxdp->addr = rte_cpu_to_le_64(dma_addr);
2458 rxdp->rx.bd_base_info = 0;
2460 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2461 rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
2463 rxm->data_len = rxm->pkt_len;
2464 rxm->port = rxq->port_id;
2465 rxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2466 rxm->ol_flags |= PKT_RX_RSS_HASH;
2467 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2469 rte_le_to_cpu_16(rxd.rx.fd_id);
2470 rxm->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2475 /* Load remained descriptor data and extract necessary fields */
2476 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2477 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2478 ret = hns3_handle_bdinfo(rxq, rxm, bd_base_info,
2479 l234_info, &cksum_err);
2483 rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);
2485 if (rxm->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)
2486 rxm->ol_flags |= PKT_RX_IEEE1588_PTP;
2488 if (likely(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2489 hns3_rx_set_cksum_flag(rxm, rxm->packet_type,
2491 hns3_rxd_to_vlan_tci(rxq, rxm, l234_info, &rxd);
2493 /* Increment bytes counter */
2494 rxq->basic_stats.bytes += rxm->pkt_len;
2496 rx_pkts[nb_rx++] = rxm;
2499 rte_pktmbuf_free(rxm);
2502 rxq->next_to_use = rx_id;
2503 rxq->rx_free_hold += nb_rx_bd;
2504 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2505 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2506 rxq->rx_free_hold = 0;
2513 hns3_recv_scattered_pkts(void *rx_queue,
2514 struct rte_mbuf **rx_pkts,
2517 volatile struct hns3_desc *rx_ring; /* RX ring (desc) */
2518 volatile struct hns3_desc *rxdp; /* pointer of the current desc */
2519 struct hns3_rx_queue *rxq; /* RX queue */
2520 struct hns3_entry *sw_ring;
2521 struct hns3_entry *rxe;
2522 struct rte_mbuf *first_seg;
2523 struct rte_mbuf *last_seg;
2524 struct hns3_desc rxd;
2525 struct rte_mbuf *nmb; /* pointer of the new mbuf */
2526 struct rte_mbuf *rxm;
2527 struct rte_eth_dev *dev;
2528 uint32_t bd_base_info;
2543 rx_id = rxq->next_to_use;
2544 rx_ring = rxq->rx_ring;
2545 sw_ring = rxq->sw_ring;
2546 first_seg = rxq->pkt_first_seg;
2547 last_seg = rxq->pkt_last_seg;
2549 while (nb_rx < nb_pkts) {
2550 rxdp = &rx_ring[rx_id];
2551 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
2552 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
2556 * The interactive process between software and hardware of
2557 * receiving a new packet in hns3 network engine:
2558 * 1. Hardware network engine firstly writes the packet content
2559 * to the memory pointed by the 'addr' field of the Rx Buffer
2560 * Descriptor, secondly fills the result of parsing the
2561 * packet include the valid field into the Rx Buffer
2562 * Descriptor in one write operation.
2563 * 2. Driver reads the Rx BD's valid field in the loop to check
2564 * whether it's valid, if valid then assign a new address to
2565 * the addr field, clear the valid field, get the other
2566 * information of the packet by parsing Rx BD's other fields,
2567 * finally write back the number of Rx BDs processed by the
2568 * driver to the HNS3_RING_RX_HEAD_REG register to inform
2570 * In the above process, the ordering is very important. We must
2571 * make sure that CPU read Rx BD's other fields only after the
2574 * There are two type of re-ordering: compiler re-ordering and
2575 * CPU re-ordering under the ARMv8 architecture.
2576 * 1. we use volatile to deal with compiler re-ordering, so you
2577 * can see that rx_ring/rxdp defined with volatile.
2578 * 2. we commonly use memory barrier to deal with CPU
2579 * re-ordering, but the cost is high.
2581 * In order to solve the high cost of using memory barrier, we
2582 * use the data dependency order under the ARMv8 architecture,
2585 * instr02: load B <- A
2586 * the instr02 will always execute after instr01.
2588 * To construct the data dependency ordering, we use the
2589 * following assignment:
2590 * rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2591 * (1u<<HNS3_RXD_VLD_B)]
2592 * Using gcc compiler under the ARMv8 architecture, the related
2593 * assembly code example as follows:
2594 * note: (1u << HNS3_RXD_VLD_B) equal 0x10
2595 * instr01: ldr w26, [x22, #28] --read bd_base_info
2596 * instr02: and w0, w26, #0x10 --calc bd_base_info & 0x10
2597 * instr03: sub w0, w0, #0x10 --calc (bd_base_info &
2599 * instr04: add x0, x22, x0, lsl #5 --calc copy source addr
2600 * instr05: ldp x2, x3, [x0]
2601 * instr06: stp x2, x3, [x29, #256] --copy BD's [0 ~ 15]B
2602 * instr07: ldp x4, x5, [x0, #16]
2603 * instr08: stp x4, x5, [x29, #272] --copy BD's [16 ~ 31]B
2604 * the instr05~08 depend on x0's value, x0 depent on w26's
2605 * value, the w26 is the bd_base_info, this form the data
2606 * dependency ordering.
2607 * note: if BD is valid, (bd_base_info & (1u<<HNS3_RXD_VLD_B)) -
2608 * (1u<<HNS3_RXD_VLD_B) will always zero, so the
2609 * assignment is correct.
2611 * So we use the data dependency ordering instead of memory
2612 * barrier to improve receive performance.
2614 rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) -
2615 (1u << HNS3_RXD_VLD_B)];
2617 nmb = hns3_rx_alloc_buffer(rxq);
2618 if (unlikely(nmb == NULL)) {
2619 dev = &rte_eth_devices[rxq->port_id];
2620 dev->data->rx_mbuf_alloc_failed++;
2625 rxe = &sw_ring[rx_id];
2627 if (unlikely(rx_id == rxq->nb_rx_desc))
2630 rte_prefetch0(sw_ring[rx_id].mbuf);
2631 if ((rx_id & HNS3_RX_RING_PREFETCTH_MASK) == 0) {
2632 rte_prefetch0(&rx_ring[rx_id]);
2633 rte_prefetch0(&sw_ring[rx_id]);
2639 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2640 rxdp->rx.bd_base_info = 0;
2641 rxdp->addr = dma_addr;
2643 if (first_seg == NULL) {
2645 first_seg->nb_segs = 1;
2647 first_seg->nb_segs++;
2648 last_seg->next = rxm;
2651 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2652 rxm->data_len = rte_le_to_cpu_16(rxd.rx.size);
2654 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
2661 * The last buffer of the received packet. packet len from
2662 * buffer description may contains CRC len, packet len should
2663 * subtract it, same as data len.
2665 first_seg->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);
2668 * This is the last buffer of the received packet. If the CRC
2669 * is not stripped by the hardware:
2670 * - Subtract the CRC length from the total packet length.
2671 * - If the last buffer only contains the whole CRC or a part
2672 * of it, free the mbuf associated to the last buffer. If part
2673 * of the CRC is also contained in the previous mbuf, subtract
2674 * the length of that CRC part from the data length of the
2678 if (unlikely(rxq->crc_len > 0)) {
2679 first_seg->pkt_len -= rxq->crc_len;
2680 recalculate_data_len(first_seg, last_seg, rxm, rxq,
2684 first_seg->port = rxq->port_id;
2685 first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);
2686 first_seg->ol_flags = PKT_RX_RSS_HASH;
2687 if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {
2688 first_seg->hash.fdir.hi =
2689 rte_le_to_cpu_16(rxd.rx.fd_id);
2690 first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
2693 gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M,
2694 HNS3_RXD_GRO_SIZE_S);
2695 if (gro_size != 0) {
2696 first_seg->ol_flags |= PKT_RX_LRO;
2697 first_seg->tso_segsz = gro_size;
2700 l234_info = rte_le_to_cpu_32(rxd.rx.l234_info);
2701 ol_info = rte_le_to_cpu_32(rxd.rx.ol_info);
2702 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
2703 l234_info, &cksum_err);
2707 first_seg->packet_type = hns3_rx_calc_ptype(rxq,
2708 l234_info, ol_info);
2710 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
2711 hns3_rx_set_cksum_flag(first_seg,
2712 first_seg->packet_type,
2714 hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd);
2716 /* Increment bytes counter */
2717 rxq->basic_stats.bytes += first_seg->pkt_len;
2719 rx_pkts[nb_rx++] = first_seg;
2723 rte_pktmbuf_free(first_seg);
2727 rxq->next_to_use = rx_id;
2728 rxq->pkt_first_seg = first_seg;
2729 rxq->pkt_last_seg = last_seg;
2731 rxq->rx_free_hold += nb_rx_bd;
2732 if (rxq->rx_free_hold > rxq->rx_free_thresh) {
2733 hns3_write_reg_opt(rxq->io_head_reg, rxq->rx_free_hold);
2734 rxq->rx_free_hold = 0;
2741 hns3_rxq_vec_setup(__rte_unused struct hns3_rx_queue *rxq)
2746 hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
2752 hns3_recv_pkts_vec(__rte_unused void *tx_queue,
2753 __rte_unused struct rte_mbuf **rx_pkts,
2754 __rte_unused uint16_t nb_pkts)
2760 hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue,
2761 __rte_unused struct rte_mbuf **rx_pkts,
2762 __rte_unused uint16_t nb_pkts)
2768 hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2769 struct rte_eth_burst_mode *mode)
2771 static const struct {
2772 eth_rx_burst_t pkt_burst;
2775 { hns3_recv_pkts, "Scalar" },
2776 { hns3_recv_scattered_pkts, "Scalar Scattered" },
2777 { hns3_recv_pkts_vec, "Vector Neon" },
2778 { hns3_recv_pkts_vec_sve, "Vector Sve" },
2781 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2785 for (i = 0; i < RTE_DIM(burst_infos); i++) {
2786 if (pkt_burst == burst_infos[i].pkt_burst) {
2787 snprintf(mode->info, sizeof(mode->info), "%s",
2788 burst_infos[i].info);
2798 hns3_get_default_vec_support(void)
2800 #if defined(RTE_ARCH_ARM64)
2801 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
2808 hns3_get_sve_support(void)
2810 #if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE)
2811 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
2817 static eth_rx_burst_t
2818 hns3_get_rx_function(struct rte_eth_dev *dev)
2820 struct hns3_adapter *hns = dev->data->dev_private;
2821 uint64_t offloads = dev->data->dev_conf.rxmode.offloads;
2822 bool vec_allowed, sve_allowed, simple_allowed;
2825 vec_support = hns3_rx_check_vec_support(dev) == 0;
2826 vec_allowed = vec_support && hns3_get_default_vec_support();
2827 sve_allowed = vec_support && hns3_get_sve_support();
2828 simple_allowed = !dev->data->scattered_rx &&
2829 (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0;
2831 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed)
2832 return hns3_recv_pkts_vec;
2833 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed)
2834 return hns3_recv_pkts_vec_sve;
2835 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed)
2836 return hns3_recv_pkts;
2837 if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON)
2838 return hns3_recv_scattered_pkts;
2841 return hns3_recv_pkts_vec;
2843 return hns3_recv_pkts;
2845 return hns3_recv_scattered_pkts;
2849 hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
2850 uint16_t nb_desc, uint16_t *tx_rs_thresh,
2851 uint16_t *tx_free_thresh, uint16_t idx)
2853 #define HNS3_TX_RS_FREE_THRESH_GAP 8
2854 uint16_t rs_thresh, free_thresh, fast_free_thresh;
2856 if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
2857 nb_desc % HNS3_ALIGN_RING_DESC) {
2858 hns3_err(hw, "number (%u) of tx descriptors is invalid",
2863 rs_thresh = (conf->tx_rs_thresh > 0) ?
2864 conf->tx_rs_thresh : HNS3_DEFAULT_TX_RS_THRESH;
2865 free_thresh = (conf->tx_free_thresh > 0) ?
2866 conf->tx_free_thresh : HNS3_DEFAULT_TX_FREE_THRESH;
2867 if (rs_thresh + free_thresh > nb_desc || nb_desc % rs_thresh ||
2868 rs_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP ||
2869 free_thresh >= nb_desc - HNS3_TX_RS_FREE_THRESH_GAP) {
2870 hns3_err(hw, "tx_rs_thresh (%u) tx_free_thresh (%u) nb_desc "
2871 "(%u) of tx descriptors for port=%u queue=%u check "
2873 rs_thresh, free_thresh, nb_desc, hw->data->port_id,
2878 if (conf->tx_free_thresh == 0) {
2879 /* Fast free Tx memory buffer to improve cache hit rate */
2880 fast_free_thresh = nb_desc - rs_thresh;
2881 if (fast_free_thresh >=
2882 HNS3_TX_FAST_FREE_AHEAD + HNS3_DEFAULT_TX_FREE_THRESH)
2883 free_thresh = fast_free_thresh -
2884 HNS3_TX_FAST_FREE_AHEAD;
2887 *tx_rs_thresh = rs_thresh;
2888 *tx_free_thresh = free_thresh;
2893 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
2894 unsigned int socket_id, const struct rte_eth_txconf *conf)
2896 struct hns3_adapter *hns = dev->data->dev_private;
2897 uint16_t tx_rs_thresh, tx_free_thresh;
2898 struct hns3_hw *hw = &hns->hw;
2899 struct hns3_queue_info q_info;
2900 struct hns3_tx_queue *txq;
2904 ret = hns3_tx_queue_conf_check(hw, conf, nb_desc,
2905 &tx_rs_thresh, &tx_free_thresh, idx);
2909 if (dev->data->tx_queues[idx] != NULL) {
2910 hns3_tx_queue_release(dev->data->tx_queues[idx]);
2911 dev->data->tx_queues[idx] = NULL;
2915 q_info.socket_id = socket_id;
2916 q_info.nb_desc = nb_desc;
2917 q_info.type = "hns3 TX queue";
2918 q_info.ring_name = "tx_ring";
2919 txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
2922 "Failed to alloc mem and reserve DMA mem for tx ring!");
2926 txq->tx_deferred_start = conf->tx_deferred_start;
2927 if (txq->tx_deferred_start && !hns3_dev_indep_txrx_supported(hw)) {
2928 hns3_warn(hw, "deferred start is not supported.");
2929 txq->tx_deferred_start = false;
2932 tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
2933 txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
2934 RTE_CACHE_LINE_SIZE, socket_id);
2935 if (txq->sw_ring == NULL) {
2936 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
2937 hns3_tx_queue_release(txq);
2942 txq->next_to_use = 0;
2943 txq->next_to_clean = 0;
2944 txq->tx_bd_ready = txq->nb_tx_desc - 1;
2945 txq->tx_free_thresh = tx_free_thresh;
2946 txq->tx_rs_thresh = tx_rs_thresh;
2947 txq->free = rte_zmalloc_socket("hns3 TX mbuf free array",
2948 sizeof(struct rte_mbuf *) * txq->tx_rs_thresh,
2949 RTE_CACHE_LINE_SIZE, socket_id);
2951 hns3_err(hw, "failed to allocate tx mbuf free array!");
2952 hns3_tx_queue_release(txq);
2956 txq->port_id = dev->data->port_id;
2958 * For hns3 PF device, if the VLAN mode is HW_SHIFT_AND_DISCARD_MODE,
2959 * the pvid_sw_shift_en in the queue struct should not be changed,
2960 * because PVID-related operations do not need to be processed by PMD
2961 * driver. For hns3 VF device, whether it needs to process PVID depends
2962 * on the configuration of PF kernel mode netdev driver. And the
2963 * related PF configuration is delivered through the mailbox and finally
2964 * reflectd in port_base_vlan_cfg.
2966 if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
2967 txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==
2968 HNS3_PORT_BASE_VLAN_ENABLE;
2970 txq->pvid_sw_shift_en = false;
2971 txq->max_non_tso_bd_num = hw->max_non_tso_bd_num;
2972 txq->configured = true;
2973 txq->io_base = (void *)((char *)hw->io_base +
2974 hns3_get_tqp_reg_offset(idx));
2975 txq->io_tail_reg = (volatile void *)((char *)txq->io_base +
2976 HNS3_RING_TX_TAIL_REG);
2977 txq->min_tx_pkt_len = hw->min_tx_pkt_len;
2978 txq->tso_mode = hw->tso_mode;
2979 txq->udp_cksum_mode = hw->udp_cksum_mode;
2980 memset(&txq->basic_stats, 0, sizeof(struct hns3_tx_basic_stats));
2981 memset(&txq->dfx_stats, 0, sizeof(struct hns3_tx_dfx_stats));
2983 rte_spinlock_lock(&hw->lock);
2984 dev->data->tx_queues[idx] = txq;
2985 rte_spinlock_unlock(&hw->lock);
2991 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
2993 uint16_t tx_next_clean = txq->next_to_clean;
2994 uint16_t tx_next_use = txq->next_to_use;
2995 uint16_t tx_bd_ready = txq->tx_bd_ready;
2996 uint16_t tx_bd_max = txq->nb_tx_desc;
2997 struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
2998 struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
2999 struct rte_mbuf *mbuf;
3001 while ((!(desc->tx.tp_fe_sc_vld_ra_ri &
3002 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))) &&
3003 tx_next_use != tx_next_clean) {
3004 mbuf = tx_bak_pkt->mbuf;
3006 rte_pktmbuf_free_seg(mbuf);
3007 tx_bak_pkt->mbuf = NULL;
3015 if (tx_next_clean >= tx_bd_max) {
3017 desc = txq->tx_ring;
3018 tx_bak_pkt = txq->sw_ring;
3022 txq->next_to_clean = tx_next_clean;
3023 txq->tx_bd_ready = tx_bd_ready;
3027 hns3_config_gro(struct hns3_hw *hw, bool en)
3029 struct hns3_cfg_gro_status_cmd *req;
3030 struct hns3_cmd_desc desc;
3033 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
3034 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
3036 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
3038 ret = hns3_cmd_send(hw, &desc, 1);
3040 hns3_err(hw, "%s hardware GRO failed, ret = %d",
3041 en ? "enable" : "disable", ret);
3047 hns3_restore_gro_conf(struct hns3_hw *hw)
3053 offloads = hw->data->dev_conf.rxmode.offloads;
3054 gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
3055 ret = hns3_config_gro(hw, gro_en);
3057 hns3_err(hw, "restore hardware GRO to %s failed, ret = %d",
3058 gro_en ? "enabled" : "disabled", ret);
3064 hns3_pkt_is_tso(struct rte_mbuf *m)
3066 return (m->tso_segsz != 0 && m->ol_flags & PKT_TX_TCP_SEG);
3070 hns3_set_tso(struct hns3_desc *desc, uint32_t paylen, struct rte_mbuf *rxm)
3072 if (!hns3_pkt_is_tso(rxm))
3075 if (paylen <= rxm->tso_segsz)
3078 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B));
3079 desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
3083 hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)
3085 desc->addr = rte_mbuf_data_iova(rxm);
3086 desc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));
3087 desc->tx.tp_fe_sc_vld_ra_ri |= rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));
3091 hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,
3092 struct rte_mbuf *rxm)
3094 uint64_t ol_flags = rxm->ol_flags;
3098 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
3099 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
3100 rxm->outer_l2_len + rxm->outer_l3_len : 0;
3101 paylen = rxm->pkt_len - hdr_len;
3102 desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen);
3103 hns3_set_tso(desc, paylen, rxm);
3106 * Currently, hardware doesn't support more than two layers VLAN offload
3107 * in Tx direction based on hns3 network engine. So when the number of
3108 * VLANs in the packets represented by rxm plus the number of VLAN
3109 * offload by hardware such as PVID etc, exceeds two, the packets will
3110 * be discarded or the original VLAN of the packets will be overwitted
3111 * by hardware. When the PF PVID is enabled by calling the API function
3112 * named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
3113 * PF kernel ether driver, the outer VLAN tag will always be the PVID.
3114 * To avoid the VLAN of Tx descriptor is overwritten by PVID, it should
3115 * be added to the position close to the IP header when PVID is enabled.
3117 if (!txq->pvid_sw_shift_en && ol_flags & (PKT_TX_VLAN_PKT |
3119 desc->tx.ol_type_vlan_len_msec |=
3120 rte_cpu_to_le_32(BIT(HNS3_TXD_OVLAN_B));
3121 if (ol_flags & PKT_TX_QINQ_PKT)
3122 desc->tx.outer_vlan_tag =
3123 rte_cpu_to_le_16(rxm->vlan_tci_outer);
3125 desc->tx.outer_vlan_tag =
3126 rte_cpu_to_le_16(rxm->vlan_tci);
3129 if (ol_flags & PKT_TX_QINQ_PKT ||
3130 ((ol_flags & PKT_TX_VLAN_PKT) && txq->pvid_sw_shift_en)) {
3131 desc->tx.type_cs_vlan_tso_len |=
3132 rte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));
3133 desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
3136 if (ol_flags & PKT_TX_IEEE1588_TMST)
3137 desc->tx.tp_fe_sc_vld_ra_ri |=
3138 rte_cpu_to_le_16(BIT(HNS3_TXD_TSYN_B));
3142 hns3_tx_alloc_mbufs(struct rte_mempool *mb_pool, uint16_t nb_new_buf,
3143 struct rte_mbuf **alloc_mbuf)
3145 #define MAX_NON_TSO_BD_PER_PKT 18
3146 struct rte_mbuf *pkt_segs[MAX_NON_TSO_BD_PER_PKT];
3149 /* Allocate enough mbufs */
3150 if (rte_mempool_get_bulk(mb_pool, (void **)pkt_segs, nb_new_buf))
3153 for (i = 0; i < nb_new_buf - 1; i++)
3154 pkt_segs[i]->next = pkt_segs[i + 1];
3156 pkt_segs[nb_new_buf - 1]->next = NULL;
3157 pkt_segs[0]->nb_segs = nb_new_buf;
3158 *alloc_mbuf = pkt_segs[0];
3164 hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt)
3166 new_pkt->ol_flags = old_pkt->ol_flags;
3167 new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt);
3168 new_pkt->outer_l2_len = old_pkt->outer_l2_len;
3169 new_pkt->outer_l3_len = old_pkt->outer_l3_len;
3170 new_pkt->l2_len = old_pkt->l2_len;
3171 new_pkt->l3_len = old_pkt->l3_len;
3172 new_pkt->l4_len = old_pkt->l4_len;
3173 new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer;
3174 new_pkt->vlan_tci = old_pkt->vlan_tci;
3178 hns3_reassemble_tx_pkts(struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt,
3179 uint8_t max_non_tso_bd_num)
3181 struct rte_mempool *mb_pool;
3182 struct rte_mbuf *new_mbuf;
3183 struct rte_mbuf *temp_new;
3184 struct rte_mbuf *temp;
3185 uint16_t last_buf_len;
3186 uint16_t nb_new_buf;
3196 mb_pool = tx_pkt->pool;
3197 buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
3198 nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1;
3199 if (nb_new_buf > max_non_tso_bd_num)
3202 last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size;
3203 if (last_buf_len == 0)
3204 last_buf_len = buf_size;
3206 /* Allocate enough mbufs */
3207 ret = hns3_tx_alloc_mbufs(mb_pool, nb_new_buf, &new_mbuf);
3211 /* Copy the original packet content to the new mbufs */
3213 s = rte_pktmbuf_mtod(temp, char *);
3214 len_s = rte_pktmbuf_data_len(temp);
3215 temp_new = new_mbuf;
3216 while (temp != NULL && temp_new != NULL) {
3217 d = rte_pktmbuf_mtod(temp_new, char *);
3218 buf_len = temp_new->next == NULL ? last_buf_len : buf_size;
3222 len = RTE_MIN(len_s, len_d);
3226 len_d = len_d - len;
3227 len_s = len_s - len;
3233 s = rte_pktmbuf_mtod(temp, char *);
3234 len_s = rte_pktmbuf_data_len(temp);
3238 temp_new->data_len = buf_len;
3239 temp_new = temp_new->next;
3241 hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt);
3243 /* free original mbufs */
3244 rte_pktmbuf_free(tx_pkt);
3246 *new_pkt = new_mbuf;
3252 hns3_parse_outer_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec)
3254 uint32_t tmp = *ol_type_vlan_len_msec;
3255 uint64_t ol_flags = m->ol_flags;
3257 /* (outer) IP header type */
3258 if (ol_flags & PKT_TX_OUTER_IPV4) {
3259 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
3260 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
3261 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
3263 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M,
3264 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_NO_CSUM);
3265 } else if (ol_flags & PKT_TX_OUTER_IPV6) {
3266 tmp |= hns3_gen_field_val(HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
3269 /* OL3 header size, defined in 4 bytes */
3270 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
3271 m->outer_l3_len >> HNS3_L3_LEN_UNIT);
3272 *ol_type_vlan_len_msec = tmp;
3276 hns3_parse_inner_params(struct rte_mbuf *m, uint32_t *ol_type_vlan_len_msec,
3277 uint32_t *type_cs_vlan_tso_len)
3279 #define HNS3_NVGRE_HLEN 8
3280 uint32_t tmp_outer = *ol_type_vlan_len_msec;
3281 uint32_t tmp_inner = *type_cs_vlan_tso_len;
3282 uint64_t ol_flags = m->ol_flags;
3283 uint16_t inner_l2_len;
3285 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
3286 case PKT_TX_TUNNEL_VXLAN_GPE:
3287 case PKT_TX_TUNNEL_GENEVE:
3288 case PKT_TX_TUNNEL_VXLAN:
3289 /* MAC in UDP tunnelling packet, include VxLAN and GENEVE */
3290 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
3291 HNS3_TXD_TUNTYPE_S, HNS3_TUN_MAC_IN_UDP);
3293 * The inner l2 length of mbuf is the sum of outer l4 length,
3294 * tunneling header length and inner l2 length for a tunnel
3295 * packect. But in hns3 tx descriptor, the tunneling header
3296 * length is contained in the field of outer L4 length.
3297 * Therefore, driver need to calculate the outer L4 length and
3300 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
3302 (uint8_t)RTE_ETHER_VXLAN_HLEN >>
3305 inner_l2_len = m->l2_len - RTE_ETHER_VXLAN_HLEN;
3307 case PKT_TX_TUNNEL_GRE:
3308 tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
3309 HNS3_TXD_TUNTYPE_S, HNS3_TUN_NVGRE);
3311 * For NVGRE tunnel packect, the outer L4 is empty. So only
3312 * fill the NVGRE header length to the outer L4 field.
3314 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
3316 (uint8_t)HNS3_NVGRE_HLEN >> HNS3_L4_LEN_UNIT);
3318 inner_l2_len = m->l2_len - HNS3_NVGRE_HLEN;
3321 /* For non UDP / GRE tunneling, drop the tunnel packet */
3325 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
3326 inner_l2_len >> HNS3_L2_LEN_UNIT);
3327 /* OL2 header size, defined in 2 bytes */
3328 tmp_outer |= hns3_gen_field_val(HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
3329 m->outer_l2_len >> HNS3_L2_LEN_UNIT);
3331 *type_cs_vlan_tso_len = tmp_inner;
3332 *ol_type_vlan_len_msec = tmp_outer;
3338 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m,
3339 uint16_t tx_desc_id)
3341 struct hns3_desc *tx_ring = txq->tx_ring;
3342 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3343 uint64_t ol_flags = m->ol_flags;
3344 uint32_t tmp_outer = 0;
3345 uint32_t tmp_inner = 0;
3350 * The tunnel header is contained in the inner L2 header field of the
3351 * mbuf, but for hns3 descriptor, it is contained in the outer L4. So,
3352 * there is a need that switching between them. To avoid multiple
3353 * calculations, the length of the L2 header include the outer and
3354 * inner, will be filled during the parsing of tunnel packects.
3356 if (!(ol_flags & PKT_TX_TUNNEL_MASK)) {
3358 * For non tunnel type the tunnel type id is 0, so no need to
3359 * assign a value to it. Only the inner(normal) L2 header length
3362 tmp_inner |= hns3_gen_field_val(HNS3_TXD_L2LEN_M,
3363 HNS3_TXD_L2LEN_S, m->l2_len >> HNS3_L2_LEN_UNIT);
3366 * If outer csum is not offload, the outer length may be filled
3367 * with 0. And the length of the outer header is added to the
3368 * inner l2_len. It would lead a cksum error. So driver has to
3369 * calculate the header length.
3371 if (unlikely(!(ol_flags &
3372 (PKT_TX_OUTER_IP_CKSUM | PKT_TX_OUTER_UDP_CKSUM)) &&
3373 m->outer_l2_len == 0)) {
3374 struct rte_net_hdr_lens hdr_len;
3375 (void)rte_net_get_ptype(m, &hdr_len,
3376 RTE_PTYPE_L2_MASK | RTE_PTYPE_L3_MASK);
3377 m->outer_l3_len = hdr_len.l3_len;
3378 m->outer_l2_len = hdr_len.l2_len;
3379 m->l2_len = m->l2_len - hdr_len.l2_len - hdr_len.l3_len;
3381 hns3_parse_outer_params(m, &tmp_outer);
3382 ret = hns3_parse_inner_params(m, &tmp_outer, &tmp_inner);
3387 desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer);
3388 desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner);
3389 tmp_ol4cs = ol_flags & PKT_TX_OUTER_UDP_CKSUM ?
3390 BIT(HNS3_TXD_OL4CS_B) : 0;
3391 desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs);
3397 hns3_parse_l3_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3399 uint64_t ol_flags = m->ol_flags;
3403 tmp = *type_cs_vlan_tso_len;
3404 if (ol_flags & PKT_TX_IPV4)
3405 l3_type = HNS3_L3T_IPV4;
3406 else if (ol_flags & PKT_TX_IPV6)
3407 l3_type = HNS3_L3T_IPV6;
3409 l3_type = HNS3_L3T_NONE;
3411 /* inner(/normal) L3 header size, defined in 4 bytes */
3412 tmp |= hns3_gen_field_val(HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
3413 m->l3_len >> HNS3_L3_LEN_UNIT);
3415 tmp |= hns3_gen_field_val(HNS3_TXD_L3T_M, HNS3_TXD_L3T_S, l3_type);
3417 /* Enable L3 checksum offloads */
3418 if (ol_flags & PKT_TX_IP_CKSUM)
3419 tmp |= BIT(HNS3_TXD_L3CS_B);
3420 *type_cs_vlan_tso_len = tmp;
3424 hns3_parse_l4_cksum_params(struct rte_mbuf *m, uint32_t *type_cs_vlan_tso_len)
3426 uint64_t ol_flags = m->ol_flags;
3428 /* Enable L4 checksum offloads */
3429 switch (ol_flags & (PKT_TX_L4_MASK | PKT_TX_TCP_SEG)) {
3430 case PKT_TX_TCP_CKSUM | PKT_TX_TCP_SEG:
3431 case PKT_TX_TCP_CKSUM:
3432 case PKT_TX_TCP_SEG:
3433 tmp = *type_cs_vlan_tso_len;
3434 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3437 case PKT_TX_UDP_CKSUM:
3438 tmp = *type_cs_vlan_tso_len;
3439 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3442 case PKT_TX_SCTP_CKSUM:
3443 tmp = *type_cs_vlan_tso_len;
3444 tmp |= hns3_gen_field_val(HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
3450 tmp |= BIT(HNS3_TXD_L4CS_B);
3451 tmp |= hns3_gen_field_val(HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
3452 m->l4_len >> HNS3_L4_LEN_UNIT);
3453 *type_cs_vlan_tso_len = tmp;
3457 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, struct rte_mbuf *m,
3458 uint16_t tx_desc_id)
3460 struct hns3_desc *tx_ring = txq->tx_ring;
3461 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3464 hns3_parse_l3_cksum_params(m, &value);
3465 hns3_parse_l4_cksum_params(m, &value);
3467 desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
3471 hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num,
3472 uint32_t max_non_tso_bd_num)
3474 struct rte_mbuf *m_first = tx_pkts;
3475 struct rte_mbuf *m_last = tx_pkts;
3476 uint32_t tot_len = 0;
3481 * Hardware requires that the sum of the data length of every 8
3482 * consecutive buffers is greater than MSS in hns3 network engine.
3483 * We simplify it by ensuring pkt_headlen + the first 8 consecutive
3484 * frags greater than gso header len + mss, and the remaining 7
3485 * consecutive frags greater than MSS except the last 7 frags.
3487 if (bd_num <= max_non_tso_bd_num)
3490 for (i = 0; m_last && i < max_non_tso_bd_num - 1;
3491 i++, m_last = m_last->next)
3492 tot_len += m_last->data_len;
3497 /* ensure the first 8 frags is greater than mss + header */
3498 hdr_len = tx_pkts->l2_len + tx_pkts->l3_len + tx_pkts->l4_len;
3499 hdr_len += (tx_pkts->ol_flags & PKT_TX_TUNNEL_MASK) ?
3500 tx_pkts->outer_l2_len + tx_pkts->outer_l3_len : 0;
3501 if (tot_len + m_last->data_len < tx_pkts->tso_segsz + hdr_len)
3505 * ensure the sum of the data length of every 7 consecutive buffer
3506 * is greater than mss except the last one.
3508 for (i = 0; m_last && i < bd_num - max_non_tso_bd_num; i++) {
3509 tot_len -= m_first->data_len;
3510 tot_len += m_last->data_len;
3512 if (tot_len < tx_pkts->tso_segsz)
3515 m_first = m_first->next;
3516 m_last = m_last->next;
3523 hns3_outer_ipv4_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags,
3526 struct rte_ipv4_hdr *ipv4_hdr;
3527 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
3529 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
3530 ipv4_hdr->hdr_checksum = 0;
3531 if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) {
3532 struct rte_udp_hdr *udp_hdr;
3534 * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo
3535 * header for TSO packets
3537 if (ol_flags & PKT_TX_TCP_SEG)
3539 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3540 m->outer_l2_len + m->outer_l3_len);
3541 udp_hdr->dgram_cksum = rte_ipv4_phdr_cksum(ipv4_hdr, ol_flags);
3545 *l4_proto = ipv4_hdr->next_proto_id;
3550 hns3_outer_ipv6_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags,
3553 struct rte_ipv6_hdr *ipv6_hdr;
3554 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
3556 if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) {
3557 struct rte_udp_hdr *udp_hdr;
3559 * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo
3560 * header for TSO packets
3562 if (ol_flags & PKT_TX_TCP_SEG)
3564 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3565 m->outer_l2_len + m->outer_l3_len);
3566 udp_hdr->dgram_cksum = rte_ipv6_phdr_cksum(ipv6_hdr, ol_flags);
3570 *l4_proto = ipv6_hdr->proto;
3575 hns3_outer_header_cksum_prepare(struct rte_mbuf *m)
3577 uint64_t ol_flags = m->ol_flags;
3578 uint32_t paylen, hdr_len, l4_proto;
3579 struct rte_udp_hdr *udp_hdr;
3581 if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6)))
3584 if (ol_flags & PKT_TX_OUTER_IPV4) {
3585 if (hns3_outer_ipv4_cksum_prepared(m, ol_flags, &l4_proto))
3588 if (hns3_outer_ipv6_cksum_prepared(m, ol_flags, &l4_proto))
3592 /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */
3593 if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) {
3594 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3595 hdr_len += m->outer_l2_len + m->outer_l3_len;
3596 paylen = m->pkt_len - hdr_len;
3597 if (paylen <= m->tso_segsz)
3599 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3602 udp_hdr->dgram_cksum = 0;
3607 hns3_check_tso_pkt_valid(struct rte_mbuf *m)
3609 uint32_t tmp_data_len_sum = 0;
3610 uint16_t nb_buf = m->nb_segs;
3611 uint32_t paylen, hdr_len;
3612 struct rte_mbuf *m_seg;
3615 if (nb_buf > HNS3_MAX_TSO_BD_PER_PKT)
3618 hdr_len = m->l2_len + m->l3_len + m->l4_len;
3619 hdr_len += (m->ol_flags & PKT_TX_TUNNEL_MASK) ?
3620 m->outer_l2_len + m->outer_l3_len : 0;
3621 if (hdr_len > HNS3_MAX_TSO_HDR_SIZE)
3624 paylen = m->pkt_len - hdr_len;
3625 if (paylen > HNS3_MAX_BD_PAYLEN)
3629 * The TSO header (include outer and inner L2, L3 and L4 header)
3630 * should be provided by three descriptors in maximum in hns3 network
3634 for (i = 0; m_seg != NULL && i < HNS3_MAX_TSO_HDR_BD_NUM && i < nb_buf;
3635 i++, m_seg = m_seg->next) {
3636 tmp_data_len_sum += m_seg->data_len;
3639 if (hdr_len > tmp_data_len_sum)
3645 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3647 hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m)
3649 struct rte_ether_hdr *eh;
3650 struct rte_vlan_hdr *vh;
3652 if (!txq->pvid_sw_shift_en)
3656 * Due to hardware limitations, we only support two-layer VLAN hardware
3657 * offload in Tx direction based on hns3 network engine, so when PVID is
3658 * enabled, QinQ insert is no longer supported.
3659 * And when PVID is enabled, in the following two cases:
3660 * i) packets with more than two VLAN tags.
3661 * ii) packets with one VLAN tag while the hardware VLAN insert is
3663 * The packets will be regarded as abnormal packets and discarded by
3664 * hardware in Tx direction. For debugging purposes, a validation check
3665 * for these types of packets is added to the '.tx_pkt_prepare' ops
3666 * implementation function named hns3_prep_pkts to inform users that
3667 * these packets will be discarded.
3669 if (m->ol_flags & PKT_TX_QINQ_PKT)
3672 eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
3673 if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
3674 if (m->ol_flags & PKT_TX_VLAN_PKT)
3677 /* Ensure the incoming packet is not a QinQ packet */
3678 vh = (struct rte_vlan_hdr *)(eh + 1);
3679 if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN))
3688 hns3_udp_cksum_help(struct rte_mbuf *m)
3690 uint64_t ol_flags = m->ol_flags;
3694 if (ol_flags & PKT_TX_IPV4) {
3695 struct rte_ipv4_hdr *ipv4_hdr = rte_pktmbuf_mtod_offset(m,
3696 struct rte_ipv4_hdr *, m->l2_len);
3697 l4_len = rte_be_to_cpu_16(ipv4_hdr->total_length) - m->l3_len;
3699 struct rte_ipv6_hdr *ipv6_hdr = rte_pktmbuf_mtod_offset(m,
3700 struct rte_ipv6_hdr *, m->l2_len);
3701 l4_len = rte_be_to_cpu_16(ipv6_hdr->payload_len);
3704 rte_raw_cksum_mbuf(m, m->l2_len + m->l3_len, l4_len, &cksum);
3708 * RFC 768:If the computed checksum is zero for UDP, it is transmitted
3714 return (uint16_t)cksum;
3718 hns3_validate_tunnel_cksum(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3720 uint64_t ol_flags = m->ol_flags;
3721 struct rte_udp_hdr *udp_hdr;
3724 if (tx_queue->udp_cksum_mode == HNS3_SPECIAL_PORT_HW_CKSUM_MODE ||
3725 ol_flags & PKT_TX_TUNNEL_MASK ||
3726 (ol_flags & PKT_TX_L4_MASK) != PKT_TX_UDP_CKSUM)
3729 * A UDP packet with the same dst_port as VXLAN\VXLAN_GPE\GENEVE will
3730 * be recognized as a tunnel packet in HW. In this case, if UDP CKSUM
3731 * offload is set and the tunnel mask has not been set, the CKSUM will
3732 * be wrong since the header length is wrong and driver should complete
3733 * the CKSUM to avoid CKSUM error.
3735 udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
3736 m->l2_len + m->l3_len);
3737 dst_port = rte_be_to_cpu_16(udp_hdr->dst_port);
3739 case RTE_VXLAN_DEFAULT_PORT:
3740 case RTE_VXLAN_GPE_DEFAULT_PORT:
3741 case RTE_GENEVE_DEFAULT_PORT:
3742 udp_hdr->dgram_cksum = hns3_udp_cksum_help(m);
3743 m->ol_flags = ol_flags & ~PKT_TX_L4_MASK;
3751 hns3_prep_pkt_proc(struct hns3_tx_queue *tx_queue, struct rte_mbuf *m)
3755 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3756 ret = rte_validate_tx_offload(m);
3762 ret = hns3_vld_vlan_chk(tx_queue, m);
3768 if (hns3_pkt_is_tso(m)) {
3769 if (hns3_pkt_need_linearized(m, m->nb_segs,
3770 tx_queue->max_non_tso_bd_num) ||
3771 hns3_check_tso_pkt_valid(m)) {
3776 if (tx_queue->tso_mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) {
3778 * (tso mode != HNS3_TSO_SW_CAL_PSEUDO_H_CSUM) means
3779 * hardware support recalculate the TCP pseudo header
3780 * checksum of packets that need TSO, so network driver
3781 * software not need to recalculate it.
3783 hns3_outer_header_cksum_prepare(m);
3788 ret = rte_net_intel_cksum_prepare(m);
3794 if (!hns3_validate_tunnel_cksum(tx_queue, m))
3797 hns3_outer_header_cksum_prepare(m);
3803 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3809 for (i = 0; i < nb_pkts; i++) {
3811 if (hns3_prep_pkt_proc(tx_queue, m))
3819 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
3822 struct hns3_desc *tx_ring = txq->tx_ring;
3823 struct hns3_desc *desc = &tx_ring[tx_desc_id];
3825 /* Enable checksum offloading */
3826 if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) {
3827 /* Fill in tunneling parameters if necessary */
3828 if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) {
3829 txq->dfx_stats.unsupported_tunnel_pkt_cnt++;
3833 hns3_txd_enable_checksum(txq, m, tx_desc_id);
3835 /* clear the control bit */
3836 desc->tx.type_cs_vlan_tso_len = 0;
3837 desc->tx.ol_type_vlan_len_msec = 0;
3844 hns3_check_non_tso_pkt(uint16_t nb_buf, struct rte_mbuf **m_seg,
3845 struct rte_mbuf *tx_pkt, struct hns3_tx_queue *txq)
3847 uint8_t max_non_tso_bd_num;
3848 struct rte_mbuf *new_pkt;
3851 if (hns3_pkt_is_tso(*m_seg))
3855 * If packet length is greater than HNS3_MAX_FRAME_LEN
3856 * driver support, the packet will be ignored.
3858 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN)) {
3859 txq->dfx_stats.over_length_pkt_cnt++;
3863 max_non_tso_bd_num = txq->max_non_tso_bd_num;
3864 if (unlikely(nb_buf > max_non_tso_bd_num)) {
3865 txq->dfx_stats.exceed_limit_bd_pkt_cnt++;
3866 ret = hns3_reassemble_tx_pkts(tx_pkt, &new_pkt,
3867 max_non_tso_bd_num);
3869 txq->dfx_stats.exceed_limit_bd_reassem_fail++;
3879 hns3_tx_free_buffer_simple(struct hns3_tx_queue *txq)
3881 struct hns3_entry *tx_entry;
3882 struct hns3_desc *desc;
3883 uint16_t tx_next_clean;
3887 if (HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) < txq->tx_rs_thresh)
3891 * All mbufs can be released only when the VLD bits of all
3892 * descriptors in a batch are cleared.
3894 tx_next_clean = (txq->next_to_clean + txq->tx_rs_thresh - 1) %
3896 desc = &txq->tx_ring[tx_next_clean];
3897 for (i = 0; i < txq->tx_rs_thresh; i++) {
3898 if (rte_le_to_cpu_16(desc->tx.tp_fe_sc_vld_ra_ri) &
3899 BIT(HNS3_TXD_VLD_B))
3904 tx_entry = &txq->sw_ring[txq->next_to_clean];
3906 for (i = 0; i < txq->tx_rs_thresh; i++)
3907 rte_prefetch0((tx_entry + i)->mbuf);
3908 for (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {
3909 rte_mempool_put(tx_entry->mbuf->pool, tx_entry->mbuf);
3910 tx_entry->mbuf = NULL;
3913 txq->next_to_clean = (tx_next_clean + 1) % txq->nb_tx_desc;
3914 txq->tx_bd_ready += txq->tx_rs_thresh;
3919 hns3_tx_backup_1mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3921 tx_entry->mbuf = pkts[0];
3925 hns3_tx_backup_4mbuf(struct hns3_entry *tx_entry, struct rte_mbuf **pkts)
3927 hns3_tx_backup_1mbuf(&tx_entry[0], &pkts[0]);
3928 hns3_tx_backup_1mbuf(&tx_entry[1], &pkts[1]);
3929 hns3_tx_backup_1mbuf(&tx_entry[2], &pkts[2]);
3930 hns3_tx_backup_1mbuf(&tx_entry[3], &pkts[3]);
3934 hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3936 #define PER_LOOP_NUM 4
3937 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3941 for (i = 0; i < PER_LOOP_NUM; i++, txdp++, pkts++) {
3942 dma_addr = rte_mbuf_data_iova(*pkts);
3943 txdp->addr = rte_cpu_to_le_64(dma_addr);
3944 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3945 txdp->tx.paylen_fd_dop_ol4cs = 0;
3946 txdp->tx.type_cs_vlan_tso_len = 0;
3947 txdp->tx.ol_type_vlan_len_msec = 0;
3948 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3953 hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
3955 const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
3958 dma_addr = rte_mbuf_data_iova(*pkts);
3959 txdp->addr = rte_cpu_to_le_64(dma_addr);
3960 txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len);
3961 txdp->tx.paylen_fd_dop_ol4cs = 0;
3962 txdp->tx.type_cs_vlan_tso_len = 0;
3963 txdp->tx.ol_type_vlan_len_msec = 0;
3964 txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
3968 hns3_tx_fill_hw_ring(struct hns3_tx_queue *txq,
3969 struct rte_mbuf **pkts,
3972 #define PER_LOOP_NUM 4
3973 #define PER_LOOP_MASK (PER_LOOP_NUM - 1)
3974 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
3975 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
3976 const uint32_t mainpart = (nb_pkts & ((uint32_t)~PER_LOOP_MASK));
3977 const uint32_t leftover = (nb_pkts & ((uint32_t)PER_LOOP_MASK));
3980 for (i = 0; i < mainpart; i += PER_LOOP_NUM) {
3981 hns3_tx_backup_4mbuf(tx_entry + i, pkts + i);
3982 hns3_tx_setup_4bd(txdp + i, pkts + i);
3984 /* Increment bytes counter */
3986 for (j = 0; j < PER_LOOP_NUM; j++)
3987 txq->basic_stats.bytes += pkts[i + j]->pkt_len;
3989 if (unlikely(leftover > 0)) {
3990 for (i = 0; i < leftover; i++) {
3991 hns3_tx_backup_1mbuf(tx_entry + mainpart + i,
3992 pkts + mainpart + i);
3993 hns3_tx_setup_1bd(txdp + mainpart + i,
3994 pkts + mainpart + i);
3996 /* Increment bytes counter */
3997 txq->basic_stats.bytes += pkts[mainpart + i]->pkt_len;
4003 hns3_xmit_pkts_simple(void *tx_queue,
4004 struct rte_mbuf **tx_pkts,
4007 struct hns3_tx_queue *txq = tx_queue;
4010 hns3_tx_free_buffer_simple(txq);
4012 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
4013 if (unlikely(nb_pkts == 0)) {
4014 if (txq->tx_bd_ready == 0)
4015 txq->dfx_stats.queue_full_cnt++;
4019 txq->tx_bd_ready -= nb_pkts;
4020 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
4021 nb_tx = txq->nb_tx_desc - txq->next_to_use;
4022 hns3_tx_fill_hw_ring(txq, tx_pkts, nb_tx);
4023 txq->next_to_use = 0;
4026 hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
4027 txq->next_to_use += nb_pkts - nb_tx;
4029 hns3_write_reg_opt(txq->io_tail_reg, nb_pkts);
4035 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
4037 struct hns3_tx_queue *txq = tx_queue;
4038 struct hns3_entry *tx_bak_pkt;
4039 struct hns3_desc *tx_ring;
4040 struct rte_mbuf *tx_pkt;
4041 struct rte_mbuf *m_seg;
4042 struct hns3_desc *desc;
4043 uint32_t nb_hold = 0;
4044 uint16_t tx_next_use;
4045 uint16_t tx_pkt_num;
4051 /* free useless buffer */
4052 hns3_tx_free_useless_buffer(txq);
4054 tx_next_use = txq->next_to_use;
4055 tx_bd_max = txq->nb_tx_desc;
4056 tx_pkt_num = nb_pkts;
4057 tx_ring = txq->tx_ring;
4060 tx_bak_pkt = &txq->sw_ring[tx_next_use];
4061 for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
4062 tx_pkt = *tx_pkts++;
4064 nb_buf = tx_pkt->nb_segs;
4066 if (nb_buf > txq->tx_bd_ready) {
4067 txq->dfx_stats.queue_full_cnt++;
4075 * If packet length is less than minimum packet length supported
4076 * by hardware in Tx direction, driver need to pad it to avoid
4079 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) <
4080 txq->min_tx_pkt_len)) {
4084 add_len = txq->min_tx_pkt_len -
4085 rte_pktmbuf_pkt_len(tx_pkt);
4086 appended = rte_pktmbuf_append(tx_pkt, add_len);
4087 if (appended == NULL) {
4088 txq->dfx_stats.pkt_padding_fail_cnt++;
4092 memset(appended, 0, add_len);
4097 if (hns3_check_non_tso_pkt(nb_buf, &m_seg, tx_pkt, txq))
4100 if (hns3_parse_cksum(txq, tx_next_use, m_seg))
4104 desc = &tx_ring[tx_next_use];
4107 * If the packet is divided into multiple Tx Buffer Descriptors,
4108 * only need to fill vlan, paylen and tso into the first Tx
4109 * Buffer Descriptor.
4111 hns3_fill_first_desc(txq, desc, m_seg);
4114 desc = &tx_ring[tx_next_use];
4116 * Fill valid bits, DMA address and data length for each
4117 * Tx Buffer Descriptor.
4119 hns3_fill_per_desc(desc, m_seg);
4120 tx_bak_pkt->mbuf = m_seg;
4121 m_seg = m_seg->next;
4124 if (tx_next_use >= tx_bd_max) {
4126 tx_bak_pkt = txq->sw_ring;
4130 } while (m_seg != NULL);
4132 /* Add end flag for the last Tx Buffer Descriptor */
4133 desc->tx.tp_fe_sc_vld_ra_ri |=
4134 rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B));
4136 /* Increment bytes counter */
4137 txq->basic_stats.bytes += tx_pkt->pkt_len;
4139 txq->next_to_use = tx_next_use;
4140 txq->tx_bd_ready -= i;
4146 hns3_write_reg_opt(txq->io_tail_reg, nb_hold);
4152 hns3_tx_check_vec_support(__rte_unused struct rte_eth_dev *dev)
4158 hns3_xmit_pkts_vec(__rte_unused void *tx_queue,
4159 __rte_unused struct rte_mbuf **tx_pkts,
4160 __rte_unused uint16_t nb_pkts)
4166 hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue,
4167 struct rte_mbuf __rte_unused **tx_pkts,
4168 uint16_t __rte_unused nb_pkts)
4174 hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
4175 struct rte_eth_burst_mode *mode)
4177 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
4178 const char *info = NULL;
4180 if (pkt_burst == hns3_xmit_pkts_simple)
4181 info = "Scalar Simple";
4182 else if (pkt_burst == hns3_xmit_pkts)
4184 else if (pkt_burst == hns3_xmit_pkts_vec)
4185 info = "Vector Neon";
4186 else if (pkt_burst == hns3_xmit_pkts_vec_sve)
4187 info = "Vector Sve";
4192 snprintf(mode->info, sizeof(mode->info), "%s", info);
4198 hns3_tx_check_simple_support(struct rte_eth_dev *dev)
4200 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
4202 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4203 if (hns3_dev_ptp_supported(hw))
4206 return (offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE));
4209 static eth_tx_burst_t
4210 hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)
4212 struct hns3_adapter *hns = dev->data->dev_private;
4213 bool vec_allowed, sve_allowed, simple_allowed;
4216 vec_support = hns3_tx_check_vec_support(dev) == 0;
4217 vec_allowed = vec_support && hns3_get_default_vec_support();
4218 sve_allowed = vec_support && hns3_get_sve_support();
4219 simple_allowed = hns3_tx_check_simple_support(dev);
4223 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed)
4224 return hns3_xmit_pkts_vec;
4225 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed)
4226 return hns3_xmit_pkts_vec_sve;
4227 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed)
4228 return hns3_xmit_pkts_simple;
4229 if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) {
4230 *prep = hns3_prep_pkts;
4231 return hns3_xmit_pkts;
4235 return hns3_xmit_pkts_vec;
4237 return hns3_xmit_pkts_simple;
4239 *prep = hns3_prep_pkts;
4240 return hns3_xmit_pkts;
4244 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
4245 struct rte_mbuf **pkts __rte_unused,
4246 uint16_t pkts_n __rte_unused)
4252 hns3_trace_rxtx_function(struct rte_eth_dev *dev)
4254 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4255 struct rte_eth_burst_mode rx_mode;
4256 struct rte_eth_burst_mode tx_mode;
4258 memset(&rx_mode, 0, sizeof(rx_mode));
4259 memset(&tx_mode, 0, sizeof(tx_mode));
4260 (void)hns3_rx_burst_mode_get(dev, 0, &rx_mode);
4261 (void)hns3_tx_burst_mode_get(dev, 0, &tx_mode);
4263 hns3_dbg(hw, "using rx_pkt_burst: %s, tx_pkt_burst: %s.",
4264 rx_mode.info, tx_mode.info);
4267 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
4269 struct hns3_adapter *hns = eth_dev->data->dev_private;
4270 eth_tx_prep_t prep = NULL;
4272 if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
4273 __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) {
4274 eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
4275 eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status;
4276 eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep);
4277 eth_dev->tx_pkt_prepare = prep;
4278 eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status;
4279 hns3_trace_rxtx_function(eth_dev);
4281 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
4282 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
4283 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;
4288 hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
4289 struct rte_eth_rxq_info *qinfo)
4291 struct hns3_rx_queue *rxq = dev->data->rx_queues[queue_id];
4293 qinfo->mp = rxq->mb_pool;
4294 qinfo->nb_desc = rxq->nb_rx_desc;
4295 qinfo->scattered_rx = dev->data->scattered_rx;
4296 /* Report the HW Rx buffer length to user */
4297 qinfo->rx_buf_size = rxq->rx_buf_len;
4300 * If there are no available Rx buffer descriptors, incoming packets
4301 * are always dropped by hardware based on hns3 network engine.
4303 qinfo->conf.rx_drop_en = 1;
4304 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
4305 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
4306 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
4310 hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
4311 struct rte_eth_txq_info *qinfo)
4313 struct hns3_tx_queue *txq = dev->data->tx_queues[queue_id];
4315 qinfo->nb_desc = txq->nb_tx_desc;
4316 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
4317 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
4318 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
4319 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
4323 hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4325 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4326 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
4327 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4330 if (!hns3_dev_indep_txrx_supported(hw))
4333 rte_spinlock_lock(&hw->lock);
4334 ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX);
4336 hns3_err(hw, "fail to reset Rx queue %u, ret = %d.",
4338 rte_spinlock_unlock(&hw->lock);
4342 ret = hns3_init_rxq(hns, rx_queue_id);
4344 hns3_err(hw, "fail to init Rx queue %u, ret = %d.",
4346 rte_spinlock_unlock(&hw->lock);
4350 hns3_enable_rxq(rxq, true);
4351 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
4352 rte_spinlock_unlock(&hw->lock);
4358 hns3_reset_sw_rxq(struct hns3_rx_queue *rxq)
4360 rxq->next_to_use = 0;
4361 rxq->rx_rearm_start = 0;
4362 rxq->rx_free_hold = 0;
4363 rxq->rx_rearm_nb = 0;
4364 rxq->pkt_first_seg = NULL;
4365 rxq->pkt_last_seg = NULL;
4366 memset(&rxq->rx_ring[0], 0, rxq->nb_rx_desc * sizeof(struct hns3_desc));
4367 hns3_rxq_vec_setup(rxq);
4371 hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4373 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4374 struct hns3_rx_queue *rxq = dev->data->rx_queues[rx_queue_id];
4376 if (!hns3_dev_indep_txrx_supported(hw))
4379 rte_spinlock_lock(&hw->lock);
4380 hns3_enable_rxq(rxq, false);
4382 hns3_rx_queue_release_mbufs(rxq);
4384 hns3_reset_sw_rxq(rxq);
4385 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
4386 rte_spinlock_unlock(&hw->lock);
4392 hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4394 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4395 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
4398 if (!hns3_dev_indep_txrx_supported(hw))
4401 rte_spinlock_lock(&hw->lock);
4402 ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX);
4404 hns3_err(hw, "fail to reset Tx queue %u, ret = %d.",
4406 rte_spinlock_unlock(&hw->lock);
4411 hns3_enable_txq(txq, true);
4412 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
4413 rte_spinlock_unlock(&hw->lock);
4419 hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4421 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4422 struct hns3_tx_queue *txq = dev->data->tx_queues[tx_queue_id];
4424 if (!hns3_dev_indep_txrx_supported(hw))
4427 rte_spinlock_lock(&hw->lock);
4428 hns3_enable_txq(txq, false);
4429 hns3_tx_queue_release_mbufs(txq);
4431 * All the mbufs in sw_ring are released and all the pointers in sw_ring
4432 * are set to NULL. If this queue is still called by upper layer,
4433 * residual SW status of this txq may cause these pointers in sw_ring
4434 * which have been set to NULL to be released again. To avoid it,
4438 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
4439 rte_spinlock_unlock(&hw->lock);
4445 hns3_tx_done_cleanup_full(struct hns3_tx_queue *txq, uint32_t free_cnt)
4447 uint16_t next_to_clean = txq->next_to_clean;
4448 uint16_t next_to_use = txq->next_to_use;
4449 uint16_t tx_bd_ready = txq->tx_bd_ready;
4450 struct hns3_entry *tx_pkt = &txq->sw_ring[next_to_clean];
4451 struct hns3_desc *desc = &txq->tx_ring[next_to_clean];
4454 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
4455 free_cnt = txq->nb_tx_desc;
4457 for (idx = 0; idx < free_cnt; idx++) {
4458 if (next_to_clean == next_to_use)
4461 if (desc->tx.tp_fe_sc_vld_ra_ri &
4462 rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))
4465 if (tx_pkt->mbuf != NULL) {
4466 rte_pktmbuf_free_seg(tx_pkt->mbuf);
4467 tx_pkt->mbuf = NULL;
4474 if (next_to_clean == txq->nb_tx_desc) {
4475 tx_pkt = txq->sw_ring;
4476 desc = txq->tx_ring;
4482 txq->next_to_clean = next_to_clean;
4483 txq->tx_bd_ready = tx_bd_ready;
4490 hns3_tx_done_cleanup(void *txq, uint32_t free_cnt)
4492 struct hns3_tx_queue *q = (struct hns3_tx_queue *)txq;
4493 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
4495 if (dev->tx_pkt_burst == hns3_xmit_pkts)
4496 return hns3_tx_done_cleanup_full(q, free_cnt);
4497 else if (dev->tx_pkt_burst == hns3_dummy_rxtx_burst)
4504 hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
4506 volatile struct hns3_desc *rxdp;
4507 struct hns3_rx_queue *rxq;
4508 struct rte_eth_dev *dev;
4509 uint32_t bd_base_info;
4512 rxq = (struct hns3_rx_queue *)rx_queue;
4513 if (offset >= rxq->nb_rx_desc)
4516 desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc;
4517 rxdp = &rxq->rx_ring[desc_id];
4518 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
4519 dev = &rte_eth_devices[rxq->port_id];
4520 if (dev->rx_pkt_burst == hns3_recv_pkts ||
4521 dev->rx_pkt_burst == hns3_recv_scattered_pkts) {
4522 if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold)
4523 return RTE_ETH_RX_DESC_UNAVAIL;
4524 } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec ||
4525 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) {
4526 if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb)
4527 return RTE_ETH_RX_DESC_UNAVAIL;
4529 return RTE_ETH_RX_DESC_UNAVAIL;
4532 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4533 return RTE_ETH_RX_DESC_AVAIL;
4535 return RTE_ETH_RX_DESC_DONE;
4539 hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
4541 volatile struct hns3_desc *txdp;
4542 struct hns3_tx_queue *txq;
4543 struct rte_eth_dev *dev;
4546 txq = (struct hns3_tx_queue *)tx_queue;
4547 if (offset >= txq->nb_tx_desc)
4550 dev = &rte_eth_devices[txq->port_id];
4551 if (dev->tx_pkt_burst != hns3_xmit_pkts_simple &&
4552 dev->tx_pkt_burst != hns3_xmit_pkts &&
4553 dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve &&
4554 dev->tx_pkt_burst != hns3_xmit_pkts_vec)
4555 return RTE_ETH_TX_DESC_UNAVAIL;
4557 desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc;
4558 txdp = &txq->tx_ring[desc_id];
4559 if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B)))
4560 return RTE_ETH_TX_DESC_FULL;
4562 return RTE_ETH_TX_DESC_DONE;
4566 hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4569 * Number of BDs that have been processed by the driver
4570 * but have not been notified to the hardware.
4572 uint32_t driver_hold_bd_num;
4573 struct hns3_rx_queue *rxq;
4576 rxq = dev->data->rx_queues[rx_queue_id];
4577 fbd_num = hns3_read_dev(rxq, HNS3_RING_RX_FBDNUM_REG);
4578 if (dev->rx_pkt_burst == hns3_recv_pkts_vec ||
4579 dev->rx_pkt_burst == hns3_recv_pkts_vec_sve)
4580 driver_hold_bd_num = rxq->rx_rearm_nb;
4582 driver_hold_bd_num = rxq->rx_free_hold;
4584 if (fbd_num <= driver_hold_bd_num)
4587 return fbd_num - driver_hold_bd_num;
4591 hns3_enable_rxd_adv_layout(struct hns3_hw *hw)
4594 * If the hardware support rxd advanced layout, then driver enable it
4597 if (hns3_dev_rxd_adv_layout_supported(hw))
4598 hns3_write_dev(hw, HNS3_RXD_ADV_LAYOUT_EN_REG, 1);