1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_MIN_RING_DESC 64
9 #define HNS3_MAX_RING_DESC 32768
10 #define HNS3_DEFAULT_RING_DESC 1024
11 #define HNS3_ALIGN_RING_DESC 32
12 #define HNS3_RING_BASE_ALIGN 128
13 #define HNS3_BULK_ALLOC_MBUF_NUM 32
15 #define HNS3_DEFAULT_RX_FREE_THRESH 32
16 #define HNS3_DEFAULT_TX_FREE_THRESH 32
17 #define HNS3_DEFAULT_TX_RS_THRESH 32
18 #define HNS3_TX_FAST_FREE_AHEAD 64
20 #define HNS3_DEFAULT_RX_BURST 32
21 #if (HNS3_DEFAULT_RX_BURST > 64)
22 #error "PMD HNS3: HNS3_DEFAULT_RX_BURST must <= 64\n"
24 #define HNS3_DEFAULT_DESCS_PER_LOOP 4
25 #define HNS3_SVE_DEFAULT_DESCS_PER_LOOP 8
26 #if (HNS3_DEFAULT_DESCS_PER_LOOP > HNS3_SVE_DEFAULT_DESCS_PER_LOOP)
27 #define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_DEFAULT_DESCS_PER_LOOP
29 #define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_SVE_DEFAULT_DESCS_PER_LOOP
31 #define HNS3_DEFAULT_RXQ_REARM_THRESH 64
32 #define HNS3_UINT8_BIT 8
33 #define HNS3_UINT16_BIT 16
34 #define HNS3_UINT32_BIT 32
36 #define HNS3_512_BD_BUF_SIZE 512
37 #define HNS3_1K_BD_BUF_SIZE 1024
38 #define HNS3_2K_BD_BUF_SIZE 2048
39 #define HNS3_4K_BD_BUF_SIZE 4096
41 #define HNS3_MIN_BD_BUF_SIZE HNS3_512_BD_BUF_SIZE
42 #define HNS3_MAX_BD_BUF_SIZE HNS3_4K_BD_BUF_SIZE
44 #define HNS3_BD_SIZE_512_TYPE 0
45 #define HNS3_BD_SIZE_1024_TYPE 1
46 #define HNS3_BD_SIZE_2048_TYPE 2
47 #define HNS3_BD_SIZE_4096_TYPE 3
49 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
50 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
51 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
52 #define HNS3_RX_FLAG_L4ID_UDP 0x0
53 #define HNS3_RX_FLAG_L4ID_TCP 0x1
55 #define HNS3_RXD_DMAC_S 0
56 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
57 #define HNS3_RXD_VLAN_S 2
58 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
59 #define HNS3_RXD_L3ID_S 4
60 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
61 #define HNS3_RXD_L4ID_S 8
62 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
63 #define HNS3_RXD_FRAG_B 12
64 #define HNS3_RXD_STRP_TAGP_S 13
65 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
67 #define HNS3_RXD_L2E_B 16
68 #define HNS3_RXD_L3E_B 17
69 #define HNS3_RXD_L4E_B 18
70 #define HNS3_RXD_TRUNCATE_B 19
71 #define HNS3_RXD_HOI_B 20
72 #define HNS3_RXD_DOI_B 21
73 #define HNS3_RXD_OL3E_B 22
74 #define HNS3_RXD_OL4E_B 23
75 #define HNS3_RXD_GRO_COUNT_S 24
76 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
77 #define HNS3_RXD_GRO_FIXID_B 30
78 #define HNS3_RXD_GRO_ECN_B 31
80 #define HNS3_RXD_ODMAC_S 0
81 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
82 #define HNS3_RXD_OVLAN_S 2
83 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
84 #define HNS3_RXD_OL3ID_S 4
85 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
86 #define HNS3_RXD_OL4ID_S 8
87 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
88 #define HNS3_RXD_FBHI_S 12
89 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
90 #define HNS3_RXD_FBLI_S 14
91 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
93 #define HNS3_RXD_BDTYPE_S 0
94 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
95 #define HNS3_RXD_VLD_B 4
96 #define HNS3_RXD_UDP0_B 5
97 #define HNS3_RXD_EXTEND_B 7
98 #define HNS3_RXD_FE_B 8
99 #define HNS3_RXD_LUM_B 9
100 #define HNS3_RXD_CRCP_B 10
101 #define HNS3_RXD_L3L4P_B 11
102 #define HNS3_RXD_TSIND_S 12
103 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
104 #define HNS3_RXD_LKBK_B 15
105 #define HNS3_RXD_GRO_SIZE_S 16
106 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
108 #define HNS3_TXD_L3T_S 0
109 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
110 #define HNS3_TXD_L4T_S 2
111 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
112 #define HNS3_TXD_L3CS_B 4
113 #define HNS3_TXD_L4CS_B 5
114 #define HNS3_TXD_VLAN_B 6
115 #define HNS3_TXD_TSO_B 7
117 #define HNS3_TXD_L2LEN_S 8
118 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
119 #define HNS3_TXD_L3LEN_S 16
120 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
121 #define HNS3_TXD_L4LEN_S 24
122 #define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
124 #define HNS3_TXD_OL3T_S 0
125 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
126 #define HNS3_TXD_OVLAN_B 2
127 #define HNS3_TXD_MACSEC_B 3
128 #define HNS3_TXD_TUNTYPE_S 4
129 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
131 #define HNS3_TXD_BDTYPE_S 0
132 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
133 #define HNS3_TXD_FE_B 4
134 #define HNS3_TXD_SC_S 5
135 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
136 #define HNS3_TXD_EXTEND_B 7
137 #define HNS3_TXD_VLD_B 8
138 #define HNS3_TXD_RI_B 9
139 #define HNS3_TXD_RA_B 10
140 #define HNS3_TXD_TSYN_B 11
141 #define HNS3_TXD_DECTTL_S 12
142 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
144 #define HNS3_TXD_MSS_S 0
145 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
147 #define HNS3_L2_LEN_UNIT 1UL
148 #define HNS3_L3_LEN_UNIT 2UL
149 #define HNS3_L4_LEN_UNIT 2UL
151 #define HNS3_TXD_DEFAULT_BDTYPE 0
152 #define HNS3_TXD_VLD_CMD (0x1 << HNS3_TXD_VLD_B)
153 #define HNS3_TXD_FE_CMD (0x1 << HNS3_TXD_FE_B)
154 #define HNS3_TXD_DEFAULT_VLD_FE_BDTYPE \
155 (HNS3_TXD_VLD_CMD | HNS3_TXD_FE_CMD | HNS3_TXD_DEFAULT_BDTYPE)
156 #define HNS3_TXD_SEND_SIZE_SHIFT 16
158 enum hns3_pkt_l2t_type {
159 HNS3_L2_TYPE_UNICAST,
160 HNS3_L2_TYPE_MULTICAST,
161 HNS3_L2_TYPE_BROADCAST,
162 HNS3_L2_TYPE_INVALID,
165 enum hns3_pkt_l3t_type {
172 enum hns3_pkt_l4t_type {
179 enum hns3_pkt_ol3t_type {
182 HNS3_OL3T_IPV4_NO_CSUM,
186 enum hns3_pkt_tun_type {
193 /* hardware spec ring buffer format */
208 * L3T | L4T | L3CS | L4CS | VLAN | TSO |
211 uint32_t type_cs_vlan_tso_len;
213 uint8_t type_cs_vlan_tso;
219 uint16_t outer_vlan_tag;
222 /* OL3T | OVALAN | MACSEC */
223 uint32_t ol_type_vlan_len_msec;
225 uint8_t ol_type_vlan_msec;
233 uint16_t tp_fe_sc_vld_ra_ri;
247 uint16_t o_dm_vlan_id_fb;
248 uint16_t ot_vlan_tag;
252 uint32_t bd_base_info;
254 uint16_t bdtype_vld_udp0;
255 uint16_t fe_lum_crcp_l3l4p;
263 struct rte_mbuf *mbuf;
266 struct hns3_rx_queue {
268 volatile void *io_head_reg;
269 struct hns3_adapter *hns;
270 struct hns3_ptype_table *ptype_tbl;
271 struct rte_mempool *mb_pool;
272 struct hns3_desc *rx_ring;
273 uint64_t rx_ring_phys_addr; /* RX ring DMA address */
274 const struct rte_memzone *mz;
275 struct hns3_entry *sw_ring;
277 struct rte_mbuf *pkt_first_seg;
278 struct rte_mbuf *pkt_last_seg;
285 * threshold for the number of BDs waited to passed to hardware. If the
286 * number exceeds the threshold, driver will pass these BDs to hardware.
288 uint16_t rx_free_thresh;
289 uint16_t next_to_use; /* index of next BD to be polled */
290 uint16_t rx_free_hold; /* num of BDs waited to passed to hardware */
291 uint16_t rx_rearm_start; /* index of BD that driver re-arming from */
292 uint16_t rx_rearm_nb; /* number of remaining BDs to be re-armed */
294 * port based vlan configuration state.
295 * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
299 /* 4 if DEV_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */
302 bool rx_deferred_start; /* don't start this queue in dev start */
303 bool configured; /* indicate if rx queue has been configured */
306 uint64_t pkt_len_errors;
307 uint64_t l3_csum_errors;
308 uint64_t l4_csum_errors;
309 uint64_t ol3_csum_errors;
310 uint64_t ol4_csum_errors;
312 struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM];
313 uint16_t bulk_mbuf_num;
315 /* offset_table: used for vector, to solve execute re-order problem */
316 uint8_t offset_table[HNS3_VECTOR_RX_OFFSET_TABLE_LEN + 1];
317 uint64_t mbuf_initializer; /* value to init mbufs used with vector rx */
318 struct rte_mbuf fake_mbuf; /* fake mbuf used with vector rx */
321 struct hns3_tx_queue {
323 volatile void *io_tail_reg;
324 struct hns3_adapter *hns;
325 struct hns3_desc *tx_ring;
326 uint64_t tx_ring_phys_addr; /* TX ring DMA address */
327 const struct rte_memzone *mz;
328 struct hns3_entry *sw_ring;
334 * index of next BD whose corresponding rte_mbuf can be released by
337 uint16_t next_to_clean;
338 /* index of next BD to be filled by driver to send packet */
339 uint16_t next_to_use;
340 /* num of remaining BDs ready to be filled by driver to send packet */
341 uint16_t tx_bd_ready;
343 /* threshold for free tx buffer if available BDs less than this value */
344 uint16_t tx_free_thresh;
347 * For better performance in tx datapath, releasing mbuf in batches is
349 * Only checking the VLD bit of the last descriptor in a batch of the
350 * thresh descriptors does not mean that these descriptors are all sent
351 * by hardware successfully. So we need to check that the VLD bits of
352 * all descriptors are cleared. and then free all mbufs in the batch.
354 * Number of mbufs released at a time.
357 * Tx mbuf free array used for preserving temporarily address of mbuf
358 * released back to mempool, when releasing mbuf in batches.
360 uint16_t tx_rs_thresh;
361 struct rte_mbuf **free;
364 * port based vlan configuration state.
365 * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
370 * The minimum length of the packet supported by hardware in the Tx
373 uint32_t min_tx_pkt_len;
375 bool tx_deferred_start; /* don't start this queue in dev start */
376 bool configured; /* indicate if tx queue has been configured */
379 * The following items are used for the abnormal errors statistics in
380 * the Tx datapath. When upper level application calls the
381 * rte_eth_tx_burst API function to send multiple packets at a time with
382 * burst mode based on hns3 network engine, there are some abnormal
383 * conditions that cause the driver to fail to operate the hardware to
384 * send packets correctly.
385 * Note: When using burst mode to call the rte_eth_tx_burst API function
386 * to send multiple packets at a time. When the first abnormal error is
387 * detected, add one to the relevant error statistics item, and then
388 * exit the loop of sending multiple packets of the function. That is to
389 * say, even if there are multiple packets in which abnormal errors may
390 * be detected in the burst, the relevant error statistics in the driver
391 * will only be increased by one.
392 * The detail description of the Tx abnormal errors statistic items as
394 * - over_length_pkt_cnt
395 * Total number of greater than HNS3_MAX_FRAME_LEN the driver
398 * - exceed_limit_bd_pkt_cnt
399 * Total number of exceeding the hardware limited bd which process
400 * a packet needed bd numbers.
402 * - exceed_limit_bd_reassem_fail
403 * Total number of exceeding the hardware limited bd fail which
404 * process a packet needed bd numbers and reassemble fail.
406 * - unsupported_tunnel_pkt_cnt
407 * Total number of unsupported tunnel packet. The unsupported tunnel
408 * type: vxlan_gpe, gtp, ipip and MPLSINUDP, MPLSINUDP is a packet
409 * with MPLS-in-UDP RFC 7510 header.
412 * Total count which the available bd numbers in current bd queue is
413 * less than the bd numbers with the pkt process needed.
415 * - pkt_padding_fail_cnt
416 * Total count which the packet length is less than minimum packet
417 * length(struct hns3_tx_queue::min_tx_pkt_len) supported by
418 * hardware in Tx direction and fail to be appended with 0.
420 uint64_t over_length_pkt_cnt;
421 uint64_t exceed_limit_bd_pkt_cnt;
422 uint64_t exceed_limit_bd_reassem_fail;
423 uint64_t unsupported_tunnel_pkt_cnt;
424 uint64_t queue_full_cnt;
425 uint64_t pkt_padding_fail_cnt;
428 #define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
429 ((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)
431 struct hns3_queue_info {
432 const char *type; /* point to queue memory name */
433 const char *ring_name; /* point to hardware ring name */
436 unsigned int socket_id;
439 #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \
440 PKT_TX_OUTER_IPV6 | \
441 PKT_TX_OUTER_IPV4 | \
442 PKT_TX_OUTER_IP_CKSUM | \
449 enum hns3_cksum_status {
451 HNS3_L3_CKSUM_ERR = 1,
452 HNS3_L4_CKSUM_ERR = 2,
453 HNS3_OUTER_L3_CKSUM_ERR = 4,
454 HNS3_OUTER_L4_CKSUM_ERR = 8
458 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
459 uint32_t bd_base_info, uint32_t l234_info,
462 #define L2E_TRUNC_ERR_FLAG (BIT(HNS3_RXD_L2E_B) | \
463 BIT(HNS3_RXD_TRUNCATE_B))
464 #define CHECKSUM_ERR_FLAG (BIT(HNS3_RXD_L3E_B) | \
465 BIT(HNS3_RXD_L4E_B) | \
466 BIT(HNS3_RXD_OL3E_B) | \
467 BIT(HNS3_RXD_OL4E_B))
472 * If packet len bigger than mtu when recv with no-scattered algorithm,
473 * the first n bd will without FE bit, we need process this sisution.
474 * Note: we don't need add statistic counter because latest BD which
475 * with FE bit will mark HNS3_RXD_L2E_B bit.
477 if (unlikely((bd_base_info & BIT(HNS3_RXD_FE_B)) == 0))
480 if (unlikely((l234_info & L2E_TRUNC_ERR_FLAG) || rxm->pkt_len == 0)) {
481 if (l234_info & BIT(HNS3_RXD_L2E_B))
484 rxq->pkt_len_errors++;
488 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
489 if (likely((l234_info & CHECKSUM_ERR_FLAG) == 0)) {
494 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
495 rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
496 rxq->l3_csum_errors++;
497 tmp |= HNS3_L3_CKSUM_ERR;
500 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
501 rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
502 rxq->l4_csum_errors++;
503 tmp |= HNS3_L4_CKSUM_ERR;
506 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
507 rxq->ol3_csum_errors++;
508 tmp |= HNS3_OUTER_L3_CKSUM_ERR;
511 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
512 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
513 rxq->ol4_csum_errors++;
514 tmp |= HNS3_OUTER_L4_CKSUM_ERR;
523 hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, const uint64_t packet_type,
524 const uint32_t cksum_err)
526 if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
527 if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
528 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
529 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
530 if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
531 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
532 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
533 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
534 (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
535 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
537 if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
538 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
539 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
540 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
541 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
542 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
546 static inline uint32_t
547 hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info,
548 const uint32_t ol_info)
550 const struct hns3_ptype_table *const ptype_tbl = rxq->ptype_tbl;
551 uint32_t l2id, l3id, l4id;
552 uint32_t ol3id, ol4id;
554 ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
555 ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
556 l2id = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
557 HNS3_RXD_STRP_TAGP_S);
558 l3id = hns3_get_field(l234_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
559 l4id = hns3_get_field(l234_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
561 if (unlikely(ptype_tbl->ol4table[ol4id]))
562 return ptype_tbl->inner_l2table[l2id] |
563 ptype_tbl->inner_l3table[l3id] |
564 ptype_tbl->inner_l4table[l4id] |
565 ptype_tbl->ol3table[ol3id] | ptype_tbl->ol4table[ol4id];
567 return ptype_tbl->l2table[l2id] | ptype_tbl->l3table[l3id] |
568 ptype_tbl->l4table[l4id];
571 void hns3_dev_rx_queue_release(void *queue);
572 void hns3_dev_tx_queue_release(void *queue);
573 void hns3_free_all_queues(struct rte_eth_dev *dev);
574 int hns3_reset_all_queues(struct hns3_adapter *hns);
575 void hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en);
576 int hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
577 int hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
578 void hns3_enable_all_queues(struct hns3_hw *hw, bool en);
579 int hns3_start_queues(struct hns3_adapter *hns, bool reset_queue);
580 int hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue);
581 int hns3_rxq_iterate(struct rte_eth_dev *dev,
582 int (*callback)(struct hns3_rx_queue *, void *), void *arg);
583 void hns3_dev_release_mbufs(struct hns3_adapter *hns);
584 int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
585 unsigned int socket, const struct rte_eth_rxconf *conf,
586 struct rte_mempool *mp);
587 int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
588 unsigned int socket, const struct rte_eth_txconf *conf);
589 uint16_t hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
591 uint16_t hns3_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
593 uint16_t hns3_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
595 int hns3_rx_burst_mode_get(struct rte_eth_dev *dev,
596 __rte_unused uint16_t queue_id,
597 struct rte_eth_burst_mode *mode);
598 int hns3_rx_check_vec_support(struct rte_eth_dev *dev);
599 uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
601 uint16_t hns3_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
603 uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
605 uint16_t hns3_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
607 int hns3_tx_burst_mode_get(struct rte_eth_dev *dev,
608 __rte_unused uint16_t queue_id,
609 struct rte_eth_burst_mode *mode);
610 const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
611 void hns3_init_rx_ptype_tble(struct rte_eth_dev *dev);
612 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
613 void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
614 uint8_t gl_idx, uint16_t gl_value);
615 void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,
617 void hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id,
619 int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
621 int hns3_config_gro(struct hns3_hw *hw, bool en);
622 int hns3_restore_gro_conf(struct hns3_hw *hw);
623 void hns3_update_all_queues_pvid_state(struct hns3_hw *hw);
624 void hns3_rx_scattered_reset(struct rte_eth_dev *dev);
625 void hns3_rx_scattered_calc(struct rte_eth_dev *dev);
626 int hns3_rx_check_vec_support(struct rte_eth_dev *dev);
627 int hns3_tx_check_vec_support(struct rte_eth_dev *dev);
628 void hns3_rxq_vec_setup(struct hns3_rx_queue *rxq);
629 void hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
630 struct rte_eth_rxq_info *qinfo);
631 void hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
632 struct rte_eth_txq_info *qinfo);
633 #endif /* _HNS3_RXTX_H_ */