1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_MIN_RING_DESC 64
9 #define HNS3_MAX_RING_DESC 32768
10 #define HNS3_DEFAULT_RING_DESC 1024
11 #define HNS3_ALIGN_RING_DESC 32
12 #define HNS3_RING_BASE_ALIGN 128
13 #define HNS3_BULK_ALLOC_MBUF_NUM 32
15 #define HNS3_DEFAULT_RX_FREE_THRESH 32
16 #define HNS3_DEFAULT_TX_FREE_THRESH 32
17 #define HNS3_DEFAULT_TX_RS_THRESH 32
18 #define HNS3_TX_FAST_FREE_AHEAD 64
20 #define HNS3_UINT8_BIT 8
21 #define HNS3_UINT16_BIT 16
22 #define HNS3_UINT32_BIT 32
24 #define HNS3_512_BD_BUF_SIZE 512
25 #define HNS3_1K_BD_BUF_SIZE 1024
26 #define HNS3_2K_BD_BUF_SIZE 2048
27 #define HNS3_4K_BD_BUF_SIZE 4096
29 #define HNS3_MIN_BD_BUF_SIZE HNS3_512_BD_BUF_SIZE
30 #define HNS3_MAX_BD_BUF_SIZE HNS3_4K_BD_BUF_SIZE
32 #define HNS3_BD_SIZE_512_TYPE 0
33 #define HNS3_BD_SIZE_1024_TYPE 1
34 #define HNS3_BD_SIZE_2048_TYPE 2
35 #define HNS3_BD_SIZE_4096_TYPE 3
37 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
38 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
39 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
40 #define HNS3_RX_FLAG_L4ID_UDP 0x0
41 #define HNS3_RX_FLAG_L4ID_TCP 0x1
43 #define HNS3_RXD_DMAC_S 0
44 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
45 #define HNS3_RXD_VLAN_S 2
46 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
47 #define HNS3_RXD_L3ID_S 4
48 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
49 #define HNS3_RXD_L4ID_S 8
50 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
51 #define HNS3_RXD_FRAG_B 12
52 #define HNS3_RXD_STRP_TAGP_S 13
53 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
55 #define HNS3_RXD_L2E_B 16
56 #define HNS3_RXD_L3E_B 17
57 #define HNS3_RXD_L4E_B 18
58 #define HNS3_RXD_TRUNCATE_B 19
59 #define HNS3_RXD_HOI_B 20
60 #define HNS3_RXD_DOI_B 21
61 #define HNS3_RXD_OL3E_B 22
62 #define HNS3_RXD_OL4E_B 23
63 #define HNS3_RXD_GRO_COUNT_S 24
64 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
65 #define HNS3_RXD_GRO_FIXID_B 30
66 #define HNS3_RXD_GRO_ECN_B 31
68 #define HNS3_RXD_ODMAC_S 0
69 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
70 #define HNS3_RXD_OVLAN_S 2
71 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
72 #define HNS3_RXD_OL3ID_S 4
73 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
74 #define HNS3_RXD_OL4ID_S 8
75 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
76 #define HNS3_RXD_FBHI_S 12
77 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
78 #define HNS3_RXD_FBLI_S 14
79 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
81 #define HNS3_RXD_BDTYPE_S 0
82 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
83 #define HNS3_RXD_VLD_B 4
84 #define HNS3_RXD_UDP0_B 5
85 #define HNS3_RXD_EXTEND_B 7
86 #define HNS3_RXD_FE_B 8
87 #define HNS3_RXD_LUM_B 9
88 #define HNS3_RXD_CRCP_B 10
89 #define HNS3_RXD_L3L4P_B 11
90 #define HNS3_RXD_TSIND_S 12
91 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
92 #define HNS3_RXD_LKBK_B 15
93 #define HNS3_RXD_GRO_SIZE_S 16
94 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
96 #define HNS3_TXD_L3T_S 0
97 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
98 #define HNS3_TXD_L4T_S 2
99 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
100 #define HNS3_TXD_L3CS_B 4
101 #define HNS3_TXD_L4CS_B 5
102 #define HNS3_TXD_VLAN_B 6
103 #define HNS3_TXD_TSO_B 7
105 #define HNS3_TXD_L2LEN_S 8
106 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
107 #define HNS3_TXD_L3LEN_S 16
108 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
109 #define HNS3_TXD_L4LEN_S 24
110 #define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
112 #define HNS3_TXD_OL3T_S 0
113 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
114 #define HNS3_TXD_OVLAN_B 2
115 #define HNS3_TXD_MACSEC_B 3
116 #define HNS3_TXD_TUNTYPE_S 4
117 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
119 #define HNS3_TXD_BDTYPE_S 0
120 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
121 #define HNS3_TXD_FE_B 4
122 #define HNS3_TXD_SC_S 5
123 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
124 #define HNS3_TXD_EXTEND_B 7
125 #define HNS3_TXD_VLD_B 8
126 #define HNS3_TXD_RI_B 9
127 #define HNS3_TXD_RA_B 10
128 #define HNS3_TXD_TSYN_B 11
129 #define HNS3_TXD_DECTTL_S 12
130 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
132 #define HNS3_TXD_MSS_S 0
133 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
135 #define HNS3_L2_LEN_UNIT 1UL
136 #define HNS3_L3_LEN_UNIT 2UL
137 #define HNS3_L4_LEN_UNIT 2UL
139 #define HNS3_TXD_DEFAULT_BDTYPE 0
140 #define HNS3_TXD_VLD_CMD (0x1 << HNS3_TXD_VLD_B)
141 #define HNS3_TXD_FE_CMD (0x1 << HNS3_TXD_FE_B)
142 #define HNS3_TXD_DEFAULT_VLD_FE_BDTYPE \
143 (HNS3_TXD_VLD_CMD | HNS3_TXD_FE_CMD | HNS3_TXD_DEFAULT_BDTYPE)
144 #define HNS3_TXD_SEND_SIZE_SHIFT 16
146 enum hns3_pkt_l2t_type {
147 HNS3_L2_TYPE_UNICAST,
148 HNS3_L2_TYPE_MULTICAST,
149 HNS3_L2_TYPE_BROADCAST,
150 HNS3_L2_TYPE_INVALID,
153 enum hns3_pkt_l3t_type {
160 enum hns3_pkt_l4t_type {
167 enum hns3_pkt_ol3t_type {
170 HNS3_OL3T_IPV4_NO_CSUM,
174 enum hns3_pkt_tun_type {
181 /* hardware spec ring buffer format */
196 * L3T | L4T | L3CS | L4CS | VLAN | TSO |
199 uint32_t type_cs_vlan_tso_len;
201 uint8_t type_cs_vlan_tso;
207 uint16_t outer_vlan_tag;
210 /* OL3T | OVALAN | MACSEC */
211 uint32_t ol_type_vlan_len_msec;
213 uint8_t ol_type_vlan_msec;
221 uint16_t tp_fe_sc_vld_ra_ri;
235 uint16_t o_dm_vlan_id_fb;
236 uint16_t ot_vlan_tag;
239 uint32_t bd_base_info;
245 struct rte_mbuf *mbuf;
248 struct hns3_rx_queue {
250 volatile void *io_head_reg;
251 struct hns3_adapter *hns;
252 struct hns3_ptype_table *ptype_tbl;
253 struct rte_mempool *mb_pool;
254 struct hns3_desc *rx_ring;
255 uint64_t rx_ring_phys_addr; /* RX ring DMA address */
256 const struct rte_memzone *mz;
257 struct hns3_entry *sw_ring;
259 struct rte_mbuf *pkt_first_seg;
260 struct rte_mbuf *pkt_last_seg;
267 * threshold for the number of BDs waited to passed to hardware. If the
268 * number exceeds the threshold, driver will pass these BDs to hardware.
270 uint16_t rx_free_thresh;
271 uint16_t next_to_use; /* index of next BD to be polled */
272 uint16_t rx_free_hold; /* num of BDs waited to passed to hardware */
275 * port based vlan configuration state.
276 * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
280 /* 4 if DEV_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */
283 bool rx_deferred_start; /* don't start this queue in dev start */
284 bool configured; /* indicate if rx queue has been configured */
287 uint64_t pkt_len_errors;
288 uint64_t l3_csum_errors;
289 uint64_t l4_csum_errors;
290 uint64_t ol3_csum_errors;
291 uint64_t ol4_csum_errors;
293 struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM];
294 uint16_t bulk_mbuf_num;
297 struct hns3_tx_queue {
299 volatile void *io_tail_reg;
300 struct hns3_adapter *hns;
301 struct hns3_desc *tx_ring;
302 uint64_t tx_ring_phys_addr; /* TX ring DMA address */
303 const struct rte_memzone *mz;
304 struct hns3_entry *sw_ring;
310 * index of next BD whose corresponding rte_mbuf can be released by
313 uint16_t next_to_clean;
314 /* index of next BD to be filled by driver to send packet */
315 uint16_t next_to_use;
316 /* num of remaining BDs ready to be filled by driver to send packet */
317 uint16_t tx_bd_ready;
319 /* threshold for free tx buffer if available BDs less than this value */
320 uint16_t tx_free_thresh;
323 * For better performance in tx datapath, releasing mbuf in batches is
325 * Only checking the VLD bit of the last descriptor in a batch of the
326 * thresh descriptors does not mean that these descriptors are all sent
327 * by hardware successfully. So we need to check that the VLD bits of
328 * all descriptors are cleared. and then free all mbufs in the batch.
330 * Number of mbufs released at a time.
333 * Tx mbuf free array used for preserving temporarily address of mbuf
334 * released back to mempool, when releasing mbuf in batches.
336 uint16_t tx_rs_thresh;
337 struct rte_mbuf **free;
340 * port based vlan configuration state.
341 * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
346 * The minimum length of the packet supported by hardware in the Tx
349 uint32_t min_tx_pkt_len;
351 bool tx_deferred_start; /* don't start this queue in dev start */
352 bool configured; /* indicate if tx queue has been configured */
355 * The following items are used for the abnormal errors statistics in
356 * the Tx datapath. When upper level application calls the
357 * rte_eth_tx_burst API function to send multiple packets at a time with
358 * burst mode based on hns3 network engine, there are some abnormal
359 * conditions that cause the driver to fail to operate the hardware to
360 * send packets correctly.
361 * Note: When using burst mode to call the rte_eth_tx_burst API function
362 * to send multiple packets at a time. When the first abnormal error is
363 * detected, add one to the relevant error statistics item, and then
364 * exit the loop of sending multiple packets of the function. That is to
365 * say, even if there are multiple packets in which abnormal errors may
366 * be detected in the burst, the relevant error statistics in the driver
367 * will only be increased by one.
368 * The detail description of the Tx abnormal errors statistic items as
370 * - over_length_pkt_cnt
371 * Total number of greater than HNS3_MAX_FRAME_LEN the driver
374 * - exceed_limit_bd_pkt_cnt
375 * Total number of exceeding the hardware limited bd which process
376 * a packet needed bd numbers.
378 * - exceed_limit_bd_reassem_fail
379 * Total number of exceeding the hardware limited bd fail which
380 * process a packet needed bd numbers and reassemble fail.
382 * - unsupported_tunnel_pkt_cnt
383 * Total number of unsupported tunnel packet. The unsupported tunnel
384 * type: vxlan_gpe, gtp, ipip and MPLSINUDP, MPLSINUDP is a packet
385 * with MPLS-in-UDP RFC 7510 header.
388 * Total count which the available bd numbers in current bd queue is
389 * less than the bd numbers with the pkt process needed.
391 * - pkt_padding_fail_cnt
392 * Total count which the packet length is less than minimum packet
393 * length(struct hns3_tx_queue::min_tx_pkt_len) supported by
394 * hardware in Tx direction and fail to be appended with 0.
396 uint64_t over_length_pkt_cnt;
397 uint64_t exceed_limit_bd_pkt_cnt;
398 uint64_t exceed_limit_bd_reassem_fail;
399 uint64_t unsupported_tunnel_pkt_cnt;
400 uint64_t queue_full_cnt;
401 uint64_t pkt_padding_fail_cnt;
404 #define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
405 ((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)
407 struct hns3_queue_info {
408 const char *type; /* point to queue memory name */
409 const char *ring_name; /* point to hardware ring name */
412 unsigned int socket_id;
415 #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \
416 PKT_TX_OUTER_IPV6 | \
417 PKT_TX_OUTER_IPV4 | \
418 PKT_TX_OUTER_IP_CKSUM | \
425 enum hns3_cksum_status {
427 HNS3_L3_CKSUM_ERR = 1,
428 HNS3_L4_CKSUM_ERR = 2,
429 HNS3_OUTER_L3_CKSUM_ERR = 4,
430 HNS3_OUTER_L4_CKSUM_ERR = 8
434 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
435 uint32_t bd_base_info, uint32_t l234_info,
438 #define L2E_TRUNC_ERR_FLAG (BIT(HNS3_RXD_L2E_B) | \
439 BIT(HNS3_RXD_TRUNCATE_B))
440 #define CHECKSUM_ERR_FLAG (BIT(HNS3_RXD_L3E_B) | \
441 BIT(HNS3_RXD_L4E_B) | \
442 BIT(HNS3_RXD_OL3E_B) | \
443 BIT(HNS3_RXD_OL4E_B))
448 * If packet len bigger than mtu when recv with no-scattered algorithm,
449 * the first n bd will without FE bit, we need process this sisution.
450 * Note: we don't need add statistic counter because latest BD which
451 * with FE bit will mark HNS3_RXD_L2E_B bit.
453 if (unlikely((bd_base_info & BIT(HNS3_RXD_FE_B)) == 0))
456 if (unlikely((l234_info & L2E_TRUNC_ERR_FLAG) || rxm->pkt_len == 0)) {
457 if (l234_info & BIT(HNS3_RXD_L2E_B))
460 rxq->pkt_len_errors++;
464 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
465 if (likely((l234_info & CHECKSUM_ERR_FLAG) == 0)) {
470 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
471 rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
472 rxq->l3_csum_errors++;
473 tmp |= HNS3_L3_CKSUM_ERR;
476 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
477 rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
478 rxq->l4_csum_errors++;
479 tmp |= HNS3_L4_CKSUM_ERR;
482 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
483 rxq->ol3_csum_errors++;
484 tmp |= HNS3_OUTER_L3_CKSUM_ERR;
487 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
488 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
489 rxq->ol4_csum_errors++;
490 tmp |= HNS3_OUTER_L4_CKSUM_ERR;
499 hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, const uint64_t packet_type,
500 const uint32_t cksum_err)
502 if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
503 if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
504 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
505 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
506 if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
507 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
508 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
509 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
510 (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
511 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
513 if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
514 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
515 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
516 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
517 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
518 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
522 static inline uint32_t
523 hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info,
524 const uint32_t ol_info)
526 const struct hns3_ptype_table *const ptype_tbl = rxq->ptype_tbl;
527 uint32_t l2id, l3id, l4id;
528 uint32_t ol3id, ol4id;
530 ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
531 ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
532 l2id = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
533 HNS3_RXD_STRP_TAGP_S);
534 l3id = hns3_get_field(l234_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
535 l4id = hns3_get_field(l234_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
537 if (unlikely(ptype_tbl->ol4table[ol4id]))
538 return ptype_tbl->inner_l2table[l2id] |
539 ptype_tbl->inner_l3table[l3id] |
540 ptype_tbl->inner_l4table[l4id] |
541 ptype_tbl->ol3table[ol3id] | ptype_tbl->ol4table[ol4id];
543 return ptype_tbl->l2table[l2id] | ptype_tbl->l3table[l3id] |
544 ptype_tbl->l4table[l4id];
547 void hns3_dev_rx_queue_release(void *queue);
548 void hns3_dev_tx_queue_release(void *queue);
549 void hns3_free_all_queues(struct rte_eth_dev *dev);
550 int hns3_reset_all_queues(struct hns3_adapter *hns);
551 void hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en);
552 int hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
553 int hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
554 void hns3_enable_all_queues(struct hns3_hw *hw, bool en);
555 int hns3_start_queues(struct hns3_adapter *hns, bool reset_queue);
556 int hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue);
557 void hns3_dev_release_mbufs(struct hns3_adapter *hns);
558 int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
559 unsigned int socket, const struct rte_eth_rxconf *conf,
560 struct rte_mempool *mp);
561 int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
562 unsigned int socket, const struct rte_eth_txconf *conf);
563 uint16_t hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
565 uint16_t hns3_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
567 int hns3_rx_burst_mode_get(struct rte_eth_dev *dev,
568 __rte_unused uint16_t queue_id,
569 struct rte_eth_burst_mode *mode);
570 uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
572 uint16_t hns3_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
574 uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
576 uint16_t hns3_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
578 int hns3_tx_burst_mode_get(struct rte_eth_dev *dev,
579 __rte_unused uint16_t queue_id,
580 struct rte_eth_burst_mode *mode);
581 const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
582 void hns3_init_rx_ptype_tble(struct rte_eth_dev *dev);
583 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
584 void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
585 uint8_t gl_idx, uint16_t gl_value);
586 void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,
588 void hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id,
590 int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
592 int hns3_config_gro(struct hns3_hw *hw, bool en);
593 int hns3_restore_gro_conf(struct hns3_hw *hw);
594 void hns3_update_all_queues_pvid_state(struct hns3_hw *hw);
595 void hns3_rx_scattered_reset(struct rte_eth_dev *dev);
596 void hns3_rx_scattered_calc(struct rte_eth_dev *dev);
597 int hns3_tx_check_vec_support(struct rte_eth_dev *dev);
598 void hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
599 struct rte_eth_rxq_info *qinfo);
600 void hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
601 struct rte_eth_txq_info *qinfo);
602 #endif /* _HNS3_RXTX_H_ */