1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_MIN_RING_DESC 64
9 #define HNS3_MAX_RING_DESC 32768
10 #define HNS3_DEFAULT_RING_DESC 1024
11 #define HNS3_ALIGN_RING_DESC 32
12 #define HNS3_RING_BASE_ALIGN 128
14 #define HNS3_BD_SIZE_512_TYPE 0
15 #define HNS3_BD_SIZE_1024_TYPE 1
16 #define HNS3_BD_SIZE_2048_TYPE 2
17 #define HNS3_BD_SIZE_4096_TYPE 3
19 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
20 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
21 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
22 #define HNS3_RX_FLAG_L4ID_UDP 0x0
23 #define HNS3_RX_FLAG_L4ID_TCP 0x1
25 #define HNS3_RXD_DMAC_S 0
26 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
27 #define HNS3_RXD_VLAN_S 2
28 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
29 #define HNS3_RXD_L3ID_S 4
30 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
31 #define HNS3_RXD_L4ID_S 8
32 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
33 #define HNS3_RXD_FRAG_B 12
34 #define HNS3_RXD_STRP_TAGP_S 13
35 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
37 #define HNS3_RXD_L2E_B 16
38 #define HNS3_RXD_L3E_B 17
39 #define HNS3_RXD_L4E_B 18
40 #define HNS3_RXD_TRUNCAT_B 19
41 #define HNS3_RXD_HOI_B 20
42 #define HNS3_RXD_DOI_B 21
43 #define HNS3_RXD_OL3E_B 22
44 #define HNS3_RXD_OL4E_B 23
45 #define HNS3_RXD_GRO_COUNT_S 24
46 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
47 #define HNS3_RXD_GRO_FIXID_B 30
48 #define HNS3_RXD_GRO_ECN_B 31
50 #define HNS3_RXD_ODMAC_S 0
51 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
52 #define HNS3_RXD_OVLAN_S 2
53 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
54 #define HNS3_RXD_OL3ID_S 4
55 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
56 #define HNS3_RXD_OL4ID_S 8
57 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
58 #define HNS3_RXD_FBHI_S 12
59 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
60 #define HNS3_RXD_FBLI_S 14
61 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
63 #define HNS3_RXD_BDTYPE_S 0
64 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
65 #define HNS3_RXD_VLD_B 4
66 #define HNS3_RXD_UDP0_B 5
67 #define HNS3_RXD_EXTEND_B 7
68 #define HNS3_RXD_FE_B 8
69 #define HNS3_RXD_LUM_B 9
70 #define HNS3_RXD_CRCP_B 10
71 #define HNS3_RXD_L3L4P_B 11
72 #define HNS3_RXD_TSIND_S 12
73 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
74 #define HNS3_RXD_LKBK_B 15
75 #define HNS3_RXD_GRO_SIZE_S 16
76 #define HNS3_RXD_GRO_SIZE_M (0x3ff << HNS3_RXD_GRO_SIZE_S)
78 #define HNS3_TXD_L3T_S 0
79 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
80 #define HNS3_TXD_L4T_S 2
81 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
82 #define HNS3_TXD_L3CS_B 4
83 #define HNS3_TXD_L4CS_B 5
84 #define HNS3_TXD_VLAN_B 6
85 #define HNS3_TXD_TSO_B 7
87 #define HNS3_TXD_L2LEN_S 8
88 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
89 #define HNS3_TXD_L3LEN_S 16
90 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
91 #define HNS3_TXD_L4LEN_S 24
92 #define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
94 #define HNS3_TXD_OL3T_S 0
95 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
96 #define HNS3_TXD_OVLAN_B 2
97 #define HNS3_TXD_MACSEC_B 3
98 #define HNS3_TXD_TUNTYPE_S 4
99 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
101 #define HNS3_TXD_BDTYPE_S 0
102 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
103 #define HNS3_TXD_FE_B 4
104 #define HNS3_TXD_SC_S 5
105 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
106 #define HNS3_TXD_EXTEND_B 7
107 #define HNS3_TXD_VLD_B 8
108 #define HNS3_TXD_RI_B 9
109 #define HNS3_TXD_RA_B 10
110 #define HNS3_TXD_TSYN_B 11
111 #define HNS3_TXD_DECTTL_S 12
112 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
114 #define HNS3_TXD_MSS_S 0
115 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
117 #define HNS3_L2_LEN_UNIT 1UL
118 #define HNS3_L3_LEN_UNIT 2UL
119 #define HNS3_L4_LEN_UNIT 2UL
121 enum hns3_pkt_l2t_type {
122 HNS3_L2_TYPE_UNICAST,
123 HNS3_L2_TYPE_MULTICAST,
124 HNS3_L2_TYPE_BROADCAST,
125 HNS3_L2_TYPE_INVALID,
128 enum hns3_pkt_l3t_type {
135 enum hns3_pkt_l4t_type {
142 enum hns3_pkt_ol3t_type {
145 HNS3_OL3T_IPV4_NO_CSUM,
149 enum hns3_pkt_tun_type {
156 /* hardware spec ring buffer format */
171 * L3T | L4T | L3CS | L4CS | VLAN | TSO |
174 uint32_t type_cs_vlan_tso_len;
176 uint8_t type_cs_vlan_tso;
182 uint16_t outer_vlan_tag;
185 /* OL3T | OVALAN | MACSEC */
186 uint32_t ol_type_vlan_len_msec;
188 uint8_t ol_type_vlan_msec;
196 uint16_t tp_fe_sc_vld_ra_ri;
210 uint16_t o_dm_vlan_id_fb;
211 uint16_t ot_vlan_tag;
214 uint32_t bd_base_info;
220 struct rte_mbuf *mbuf;
223 struct hns3_rx_queue {
225 struct hns3_adapter *hns;
226 struct rte_mempool *mb_pool;
227 struct hns3_desc *rx_ring;
228 uint64_t rx_ring_phys_addr; /* RX ring DMA address */
229 const struct rte_memzone *mz;
230 struct hns3_entry *sw_ring;
232 struct rte_mbuf *pkt_first_seg;
233 struct rte_mbuf *pkt_last_seg;
240 uint16_t next_to_clean;
241 uint16_t next_to_use;
243 uint16_t rx_free_thresh;
245 bool rx_deferred_start; /* don't start this queue in dev start */
246 bool configured; /* indicate if rx queue has been configured */
249 uint64_t pkt_len_errors;
250 uint64_t l3_csum_erros;
251 uint64_t l4_csum_erros;
252 uint64_t ol3_csum_erros;
253 uint64_t ol4_csum_erros;
256 struct hns3_tx_queue {
258 struct hns3_adapter *hns;
259 struct hns3_desc *tx_ring;
260 uint64_t tx_ring_phys_addr; /* TX ring DMA address */
261 const struct rte_memzone *mz;
262 struct hns3_entry *sw_ring;
267 uint16_t next_to_clean;
268 uint16_t next_to_use;
269 uint16_t tx_bd_ready;
271 bool tx_deferred_start; /* don't start this queue in dev start */
272 bool configured; /* indicate if tx queue has been configured */
275 struct hns3_queue_info {
276 const char *type; /* point to queue memory name */
277 const char *ring_name; /* point to hardware ring name */
280 unsigned int socket_id;
283 #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \
284 PKT_TX_OUTER_IPV6 | \
285 PKT_TX_OUTER_IPV4 | \
286 PKT_TX_OUTER_IP_CKSUM | \
293 enum hns3_cksum_status {
295 HNS3_L3_CKSUM_ERR = 1,
296 HNS3_L4_CKSUM_ERR = 2,
297 HNS3_OUTER_L3_CKSUM_ERR = 4,
298 HNS3_OUTER_L4_CKSUM_ERR = 8
301 void hns3_dev_rx_queue_release(void *queue);
302 void hns3_dev_tx_queue_release(void *queue);
303 void hns3_free_all_queues(struct rte_eth_dev *dev);
304 int hns3_reset_all_queues(struct hns3_adapter *hns);
305 int hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
306 int hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
307 int hns3_start_queues(struct hns3_adapter *hns, bool reset_queue);
308 int hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue);
309 void hns3_dev_release_mbufs(struct hns3_adapter *hns);
310 int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
311 unsigned int socket, const struct rte_eth_rxconf *conf,
312 struct rte_mempool *mp);
313 int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
314 unsigned int socket, const struct rte_eth_txconf *conf);
315 uint16_t hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
317 uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
319 uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
321 const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
322 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
323 void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
324 uint8_t gl_idx, uint16_t gl_value);
325 void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,
327 int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
330 #endif /* _HNS3_RXTX_H_ */