1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_MIN_RING_DESC 64
9 #define HNS3_MAX_RING_DESC 32768
10 #define HNS3_DEFAULT_RING_DESC 1024
11 #define HNS3_ALIGN_RING_DESC 32
12 #define HNS3_RING_BASE_ALIGN 128
13 #define HNS3_BULK_ALLOC_MBUF_NUM 32
15 #define HNS3_DEFAULT_RX_FREE_THRESH 32
16 #define HNS3_DEFAULT_TX_FREE_THRESH 32
17 #define HNS3_DEFAULT_TX_RS_THRESH 32
18 #define HNS3_TX_FAST_FREE_AHEAD 64
20 #define HNS3_DEFAULT_RX_BURST 32
21 #if (HNS3_DEFAULT_RX_BURST > 64)
22 #error "PMD HNS3: HNS3_DEFAULT_RX_BURST must <= 64\n"
24 #define HNS3_DEFAULT_DESCS_PER_LOOP 4
25 #define HNS3_SVE_DEFAULT_DESCS_PER_LOOP 8
26 #if (HNS3_DEFAULT_DESCS_PER_LOOP > HNS3_SVE_DEFAULT_DESCS_PER_LOOP)
27 #define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_DEFAULT_DESCS_PER_LOOP
29 #define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_SVE_DEFAULT_DESCS_PER_LOOP
31 #define HNS3_DEFAULT_RXQ_REARM_THRESH 64
32 #define HNS3_UINT8_BIT 8
33 #define HNS3_UINT16_BIT 16
34 #define HNS3_UINT32_BIT 32
36 #define HNS3_512_BD_BUF_SIZE 512
37 #define HNS3_1K_BD_BUF_SIZE 1024
38 #define HNS3_2K_BD_BUF_SIZE 2048
39 #define HNS3_4K_BD_BUF_SIZE 4096
41 #define HNS3_MIN_BD_BUF_SIZE HNS3_512_BD_BUF_SIZE
42 #define HNS3_MAX_BD_BUF_SIZE HNS3_4K_BD_BUF_SIZE
44 #define HNS3_BD_SIZE_512_TYPE 0
45 #define HNS3_BD_SIZE_1024_TYPE 1
46 #define HNS3_BD_SIZE_2048_TYPE 2
47 #define HNS3_BD_SIZE_4096_TYPE 3
49 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
50 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
51 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
52 #define HNS3_RX_FLAG_L4ID_UDP 0x0
53 #define HNS3_RX_FLAG_L4ID_TCP 0x1
55 #define HNS3_RXD_DMAC_S 0
56 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
57 #define HNS3_RXD_VLAN_S 2
58 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
59 #define HNS3_RXD_L3ID_S 4
60 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
61 #define HNS3_RXD_L4ID_S 8
62 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
63 #define HNS3_RXD_FRAG_B 12
64 #define HNS3_RXD_STRP_TAGP_S 13
65 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
67 #define HNS3_RXD_L2E_B 16
68 #define HNS3_RXD_L3E_B 17
69 #define HNS3_RXD_L4E_B 18
70 #define HNS3_RXD_TRUNCATE_B 19
71 #define HNS3_RXD_HOI_B 20
72 #define HNS3_RXD_DOI_B 21
73 #define HNS3_RXD_OL3E_B 22
74 #define HNS3_RXD_OL4E_B 23
75 #define HNS3_RXD_GRO_COUNT_S 24
76 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
77 #define HNS3_RXD_GRO_FIXID_B 30
78 #define HNS3_RXD_GRO_ECN_B 31
80 #define HNS3_RXD_ODMAC_S 0
81 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
82 #define HNS3_RXD_OVLAN_S 2
83 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
84 #define HNS3_RXD_OL3ID_S 4
85 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
86 #define HNS3_RXD_OL4ID_S 8
87 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
88 #define HNS3_RXD_FBHI_S 12
89 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
90 #define HNS3_RXD_FBLI_S 14
91 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
93 #define HNS3_RXD_BDTYPE_S 0
94 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
95 #define HNS3_RXD_VLD_B 4
96 #define HNS3_RXD_UDP0_B 5
97 #define HNS3_RXD_EXTEND_B 7
98 #define HNS3_RXD_FE_B 8
99 #define HNS3_RXD_LUM_B 9
100 #define HNS3_RXD_CRCP_B 10
101 #define HNS3_RXD_L3L4P_B 11
102 #define HNS3_RXD_TSIND_S 12
103 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
104 #define HNS3_RXD_LKBK_B 15
105 #define HNS3_RXD_GRO_SIZE_S 16
106 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
108 #define HNS3_TXD_L3T_S 0
109 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
110 #define HNS3_TXD_L4T_S 2
111 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
112 #define HNS3_TXD_L3CS_B 4
113 #define HNS3_TXD_L4CS_B 5
114 #define HNS3_TXD_VLAN_B 6
115 #define HNS3_TXD_TSO_B 7
117 #define HNS3_TXD_L2LEN_S 8
118 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
119 #define HNS3_TXD_L3LEN_S 16
120 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
121 #define HNS3_TXD_L4LEN_S 24
122 #define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
124 #define HNS3_TXD_OL3T_S 0
125 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
126 #define HNS3_TXD_OVLAN_B 2
127 #define HNS3_TXD_MACSEC_B 3
128 #define HNS3_TXD_TUNTYPE_S 4
129 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
131 #define HNS3_TXD_BDTYPE_S 0
132 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
133 #define HNS3_TXD_FE_B 4
134 #define HNS3_TXD_SC_S 5
135 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
136 #define HNS3_TXD_EXTEND_B 7
137 #define HNS3_TXD_VLD_B 8
138 #define HNS3_TXD_RI_B 9
139 #define HNS3_TXD_RA_B 10
140 #define HNS3_TXD_TSYN_B 11
141 #define HNS3_TXD_DECTTL_S 12
142 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
144 #define HNS3_TXD_MSS_S 0
145 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
147 #define HNS3_L2_LEN_UNIT 1UL
148 #define HNS3_L3_LEN_UNIT 2UL
149 #define HNS3_L4_LEN_UNIT 2UL
151 #define HNS3_TXD_DEFAULT_BDTYPE 0
152 #define HNS3_TXD_VLD_CMD (0x1 << HNS3_TXD_VLD_B)
153 #define HNS3_TXD_FE_CMD (0x1 << HNS3_TXD_FE_B)
154 #define HNS3_TXD_DEFAULT_VLD_FE_BDTYPE \
155 (HNS3_TXD_VLD_CMD | HNS3_TXD_FE_CMD | HNS3_TXD_DEFAULT_BDTYPE)
156 #define HNS3_TXD_SEND_SIZE_SHIFT 16
158 enum hns3_pkt_l2t_type {
159 HNS3_L2_TYPE_UNICAST,
160 HNS3_L2_TYPE_MULTICAST,
161 HNS3_L2_TYPE_BROADCAST,
162 HNS3_L2_TYPE_INVALID,
165 enum hns3_pkt_l3t_type {
172 enum hns3_pkt_l4t_type {
179 enum hns3_pkt_ol3t_type {
182 HNS3_OL3T_IPV4_NO_CSUM,
186 enum hns3_pkt_tun_type {
193 /* hardware spec ring buffer format */
208 * L3T | L4T | L3CS | L4CS | VLAN | TSO |
211 uint32_t type_cs_vlan_tso_len;
213 uint8_t type_cs_vlan_tso;
219 uint16_t outer_vlan_tag;
222 /* OL3T | OVALAN | MACSEC */
223 uint32_t ol_type_vlan_len_msec;
225 uint8_t ol_type_vlan_msec;
233 uint16_t tp_fe_sc_vld_ra_ri;
247 uint16_t o_dm_vlan_id_fb;
248 uint16_t ot_vlan_tag;
252 uint32_t bd_base_info;
254 uint16_t bdtype_vld_udp0;
255 uint16_t fe_lum_crcp_l3l4p;
263 struct rte_mbuf *mbuf;
266 struct hns3_rx_queue {
268 volatile void *io_head_reg;
269 struct hns3_adapter *hns;
270 struct hns3_ptype_table *ptype_tbl;
271 struct rte_mempool *mb_pool;
272 struct hns3_desc *rx_ring;
273 uint64_t rx_ring_phys_addr; /* RX ring DMA address */
274 const struct rte_memzone *mz;
275 struct hns3_entry *sw_ring;
276 struct rte_mbuf *pkt_first_seg;
277 struct rte_mbuf *pkt_last_seg;
284 * threshold for the number of BDs waited to passed to hardware. If the
285 * number exceeds the threshold, driver will pass these BDs to hardware.
287 uint16_t rx_free_thresh;
288 uint16_t next_to_use; /* index of next BD to be polled */
289 uint16_t rx_free_hold; /* num of BDs waited to passed to hardware */
290 uint16_t rx_rearm_start; /* index of BD that driver re-arming from */
291 uint16_t rx_rearm_nb; /* number of remaining BDs to be re-armed */
293 /* 4 if DEV_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */
296 bool rx_deferred_start; /* don't start this queue in dev start */
297 bool configured; /* indicate if rx queue has been configured */
299 * Indicate whether ignore the outer VLAN field in the Rx BD reported
300 * by the Hardware. Because the outer VLAN is the PVID if the PVID is
301 * set for some version of hardware network engine whose vlan mode is
302 * HNS3_SW_SHIFT_AND_DISCARD_MODE, such as kunpeng 920. And this VLAN
303 * should not be transitted to the upper-layer application. For hardware
304 * network engine whose vlan mode is HNS3_HW_SHIFT_AND_DISCARD_MODE,
305 * such as kunpeng 930, PVID will not be reported to the BDs. So, PMD
306 * driver does not need to perform PVID-related operation in Rx. At this
307 * point, the pvid_sw_discard_en will be false.
309 bool pvid_sw_discard_en;
310 bool enabled; /* indicate if Rx queue has been enabled */
313 uint64_t pkt_len_errors;
314 uint64_t l3_csum_errors;
315 uint64_t l4_csum_errors;
316 uint64_t ol3_csum_errors;
317 uint64_t ol4_csum_errors;
319 struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM];
320 uint16_t bulk_mbuf_num;
322 /* offset_table: used for vector, to solve execute re-order problem */
323 uint8_t offset_table[HNS3_VECTOR_RX_OFFSET_TABLE_LEN + 1];
324 uint64_t mbuf_initializer; /* value to init mbufs used with vector rx */
325 struct rte_mbuf fake_mbuf; /* fake mbuf used with vector rx */
328 struct hns3_tx_queue {
330 volatile void *io_tail_reg;
331 struct hns3_adapter *hns;
332 struct hns3_desc *tx_ring;
333 uint64_t tx_ring_phys_addr; /* TX ring DMA address */
334 const struct rte_memzone *mz;
335 struct hns3_entry *sw_ring;
341 * index of next BD whose corresponding rte_mbuf can be released by
344 uint16_t next_to_clean;
345 /* index of next BD to be filled by driver to send packet */
346 uint16_t next_to_use;
347 /* num of remaining BDs ready to be filled by driver to send packet */
348 uint16_t tx_bd_ready;
350 /* threshold for free tx buffer if available BDs less than this value */
351 uint16_t tx_free_thresh;
354 * For better performance in tx datapath, releasing mbuf in batches is
356 * Only checking the VLD bit of the last descriptor in a batch of the
357 * thresh descriptors does not mean that these descriptors are all sent
358 * by hardware successfully. So we need to check that the VLD bits of
359 * all descriptors are cleared. and then free all mbufs in the batch.
361 * Number of mbufs released at a time.
364 * Tx mbuf free array used for preserving temporarily address of mbuf
365 * released back to mempool, when releasing mbuf in batches.
367 uint16_t tx_rs_thresh;
368 struct rte_mbuf **free;
373 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
375 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
376 * In this mode, because of the hardware constraint, network driver
377 * software need erase the L4 len value of the TCP pseudo header
378 * and recalculate the TCP pseudo header checksum of packets that
381 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
382 * In this mode, hardware support recalculate the TCP pseudo header
383 * checksum of packets that need TSO, so network driver software
384 * not need to recalculate it.
388 * The minimum length of the packet supported by hardware in the Tx
391 uint32_t min_tx_pkt_len;
393 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
394 bool tx_deferred_start; /* don't start this queue in dev start */
395 bool configured; /* indicate if tx queue has been configured */
397 * Indicate whether add the vlan_tci of the mbuf to the inner VLAN field
398 * of Tx BD. Because the outer VLAN will always be the PVID when the
399 * PVID is set and for some version of hardware network engine whose
400 * vlan mode is HNS3_SW_SHIFT_AND_DISCARD_MODE, such as kunpeng 920, the
401 * PVID will overwrite the outer VLAN field of Tx BD. For the hardware
402 * network engine whose vlan mode is HNS3_HW_SHIFT_AND_DISCARD_MODE,
403 * such as kunpeng 930, if the PVID is set, the hardware will shift the
404 * VLAN field automatically. So, PMD driver does not need to do
405 * PVID-related operations in Tx. And pvid_sw_shift_en will be false at
408 bool pvid_sw_shift_en;
409 bool enabled; /* indicate if Tx queue has been enabled */
412 * The following items are used for the abnormal errors statistics in
413 * the Tx datapath. When upper level application calls the
414 * rte_eth_tx_burst API function to send multiple packets at a time with
415 * burst mode based on hns3 network engine, there are some abnormal
416 * conditions that cause the driver to fail to operate the hardware to
417 * send packets correctly.
418 * Note: When using burst mode to call the rte_eth_tx_burst API function
419 * to send multiple packets at a time. When the first abnormal error is
420 * detected, add one to the relevant error statistics item, and then
421 * exit the loop of sending multiple packets of the function. That is to
422 * say, even if there are multiple packets in which abnormal errors may
423 * be detected in the burst, the relevant error statistics in the driver
424 * will only be increased by one.
425 * The detail description of the Tx abnormal errors statistic items as
427 * - over_length_pkt_cnt
428 * Total number of greater than HNS3_MAX_FRAME_LEN the driver
431 * - exceed_limit_bd_pkt_cnt
432 * Total number of exceeding the hardware limited bd which process
433 * a packet needed bd numbers.
435 * - exceed_limit_bd_reassem_fail
436 * Total number of exceeding the hardware limited bd fail which
437 * process a packet needed bd numbers and reassemble fail.
439 * - unsupported_tunnel_pkt_cnt
440 * Total number of unsupported tunnel packet. The unsupported tunnel
441 * type: vxlan_gpe, gtp, ipip and MPLSINUDP, MPLSINUDP is a packet
442 * with MPLS-in-UDP RFC 7510 header.
445 * Total count which the available bd numbers in current bd queue is
446 * less than the bd numbers with the pkt process needed.
448 * - pkt_padding_fail_cnt
449 * Total count which the packet length is less than minimum packet
450 * length(struct hns3_tx_queue::min_tx_pkt_len) supported by
451 * hardware in Tx direction and fail to be appended with 0.
453 uint64_t over_length_pkt_cnt;
454 uint64_t exceed_limit_bd_pkt_cnt;
455 uint64_t exceed_limit_bd_reassem_fail;
456 uint64_t unsupported_tunnel_pkt_cnt;
457 uint64_t queue_full_cnt;
458 uint64_t pkt_padding_fail_cnt;
461 #define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
462 ((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)
464 struct hns3_queue_info {
465 const char *type; /* point to queue memory name */
466 const char *ring_name; /* point to hardware ring name */
469 unsigned int socket_id;
472 #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \
473 PKT_TX_OUTER_IPV6 | \
474 PKT_TX_OUTER_IPV4 | \
475 PKT_TX_OUTER_IP_CKSUM | \
482 enum hns3_cksum_status {
484 HNS3_L3_CKSUM_ERR = 1,
485 HNS3_L4_CKSUM_ERR = 2,
486 HNS3_OUTER_L3_CKSUM_ERR = 4,
487 HNS3_OUTER_L4_CKSUM_ERR = 8
491 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
492 uint32_t bd_base_info, uint32_t l234_info,
495 #define L2E_TRUNC_ERR_FLAG (BIT(HNS3_RXD_L2E_B) | \
496 BIT(HNS3_RXD_TRUNCATE_B))
497 #define CHECKSUM_ERR_FLAG (BIT(HNS3_RXD_L3E_B) | \
498 BIT(HNS3_RXD_L4E_B) | \
499 BIT(HNS3_RXD_OL3E_B) | \
500 BIT(HNS3_RXD_OL4E_B))
505 * If packet len bigger than mtu when recv with no-scattered algorithm,
506 * the first n bd will without FE bit, we need process this sisution.
507 * Note: we don't need add statistic counter because latest BD which
508 * with FE bit will mark HNS3_RXD_L2E_B bit.
510 if (unlikely((bd_base_info & BIT(HNS3_RXD_FE_B)) == 0))
513 if (unlikely((l234_info & L2E_TRUNC_ERR_FLAG) || rxm->pkt_len == 0)) {
514 if (l234_info & BIT(HNS3_RXD_L2E_B))
517 rxq->pkt_len_errors++;
521 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
522 if (likely((l234_info & CHECKSUM_ERR_FLAG) == 0)) {
527 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
528 rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
529 rxq->l3_csum_errors++;
530 tmp |= HNS3_L3_CKSUM_ERR;
533 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
534 rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
535 rxq->l4_csum_errors++;
536 tmp |= HNS3_L4_CKSUM_ERR;
539 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
540 rxq->ol3_csum_errors++;
541 tmp |= HNS3_OUTER_L3_CKSUM_ERR;
544 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
545 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
546 rxq->ol4_csum_errors++;
547 tmp |= HNS3_OUTER_L4_CKSUM_ERR;
556 hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, const uint64_t packet_type,
557 const uint32_t cksum_err)
559 if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
560 if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
561 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
562 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
563 if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
564 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
565 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
566 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
567 (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
568 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
570 if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
571 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
572 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
573 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
574 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
575 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
579 static inline uint32_t
580 hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info,
581 const uint32_t ol_info)
583 const struct hns3_ptype_table *const ptype_tbl = rxq->ptype_tbl;
584 uint32_t l2id, l3id, l4id;
585 uint32_t ol3id, ol4id;
587 ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
588 ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
589 l2id = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M,
590 HNS3_RXD_STRP_TAGP_S);
591 l3id = hns3_get_field(l234_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
592 l4id = hns3_get_field(l234_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
594 if (unlikely(ptype_tbl->ol4table[ol4id]))
595 return ptype_tbl->inner_l2table[l2id] |
596 ptype_tbl->inner_l3table[l3id] |
597 ptype_tbl->inner_l4table[l4id] |
598 ptype_tbl->ol3table[ol3id] | ptype_tbl->ol4table[ol4id];
600 return ptype_tbl->l2table[l2id] | ptype_tbl->l3table[l3id] |
601 ptype_tbl->l4table[l4id];
604 void hns3_dev_rx_queue_release(void *queue);
605 void hns3_dev_tx_queue_release(void *queue);
606 void hns3_free_all_queues(struct rte_eth_dev *dev);
607 int hns3_reset_all_tqps(struct hns3_adapter *hns);
608 void hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en);
609 int hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
610 int hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
611 void hns3_enable_all_queues(struct hns3_hw *hw, bool en);
612 int hns3_init_queues(struct hns3_adapter *hns, bool reset_queue);
613 void hns3_start_tqps(struct hns3_hw *hw);
614 void hns3_stop_tqps(struct hns3_hw *hw);
615 int hns3_rxq_iterate(struct rte_eth_dev *dev,
616 int (*callback)(struct hns3_rx_queue *, void *), void *arg);
617 void hns3_dev_release_mbufs(struct hns3_adapter *hns);
618 int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
619 unsigned int socket, const struct rte_eth_rxconf *conf,
620 struct rte_mempool *mp);
621 int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
622 unsigned int socket, const struct rte_eth_txconf *conf);
623 int hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
624 int hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
625 int hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
626 int hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
627 uint16_t hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
629 uint16_t hns3_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
631 uint16_t hns3_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
633 int hns3_rx_burst_mode_get(struct rte_eth_dev *dev,
634 __rte_unused uint16_t queue_id,
635 struct rte_eth_burst_mode *mode);
636 int hns3_rx_check_vec_support(struct rte_eth_dev *dev);
637 uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
639 uint16_t hns3_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
641 uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
643 uint16_t hns3_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
645 int hns3_tx_burst_mode_get(struct rte_eth_dev *dev,
646 __rte_unused uint16_t queue_id,
647 struct rte_eth_burst_mode *mode);
648 const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
649 void hns3_init_rx_ptype_tble(struct rte_eth_dev *dev);
650 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
651 void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
652 uint8_t gl_idx, uint16_t gl_value);
653 void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,
655 void hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id,
657 int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
659 int hns3_config_gro(struct hns3_hw *hw, bool en);
660 int hns3_restore_gro_conf(struct hns3_hw *hw);
661 void hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw);
662 void hns3_rx_scattered_reset(struct rte_eth_dev *dev);
663 void hns3_rx_scattered_calc(struct rte_eth_dev *dev);
664 int hns3_rx_check_vec_support(struct rte_eth_dev *dev);
665 int hns3_tx_check_vec_support(struct rte_eth_dev *dev);
666 void hns3_rxq_vec_setup(struct hns3_rx_queue *rxq);
667 void hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
668 struct rte_eth_rxq_info *qinfo);
669 void hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
670 struct rte_eth_txq_info *qinfo);
671 uint32_t hns3_get_tqp_reg_offset(uint16_t idx);
672 int hns3_start_all_txqs(struct rte_eth_dev *dev);
673 int hns3_start_all_rxqs(struct rte_eth_dev *dev);
674 void hns3_stop_all_txqs(struct rte_eth_dev *dev);
676 #endif /* _HNS3_RXTX_H_ */