drivers/net/i40e/base/i40e_adminq.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_status.h"
  35 #include "i40e_type.h"
  36 #include "i40e_register.h"
  37 #include "i40e_adminq.h"
  38 #include "i40e_prototype.h"
  39
  40 #ifdef PF_DRIVER
  41 /**
  42  * i40e_is_nvm_update_op - return true if this is an NVM update operation
  43  * @desc: API request descriptor
  44  **/
  45 STATIC INLINE bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
  46 {
  47         return (desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_erase) ||
  48                 desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_update));
  49 }
  50
  51 #endif /* PF_DRIVER */
  52 /**
  53  *  i40e_adminq_init_regs - Initialize AdminQ registers
  54  *  @hw: pointer to the hardware structure
  55  *
  56  *  This assumes the alloc_asq and alloc_arq functions have already been called
  57  **/
  58 STATIC void i40e_adminq_init_regs(struct i40e_hw *hw)
  59 {
  60         /* set head and tail registers in our local struct */
  61         if (i40e_is_vf(hw)) {
  62                 hw->aq.asq.tail = I40E_VF_ATQT1;
  63                 hw->aq.asq.head = I40E_VF_ATQH1;
  64                 hw->aq.asq.len  = I40E_VF_ATQLEN1;
  65                 hw->aq.asq.bal  = I40E_VF_ATQBAL1;
  66                 hw->aq.asq.bah  = I40E_VF_ATQBAH1;
  67                 hw->aq.arq.tail = I40E_VF_ARQT1;
  68                 hw->aq.arq.head = I40E_VF_ARQH1;
  69                 hw->aq.arq.len  = I40E_VF_ARQLEN1;
  70                 hw->aq.arq.bal  = I40E_VF_ARQBAL1;
  71                 hw->aq.arq.bah  = I40E_VF_ARQBAH1;
  72         } else {
  73                 hw->aq.asq.tail = I40E_PF_ATQT;
  74                 hw->aq.asq.head = I40E_PF_ATQH;
  75                 hw->aq.asq.len  = I40E_PF_ATQLEN;
  76                 hw->aq.asq.bal  = I40E_PF_ATQBAL;
  77                 hw->aq.asq.bah  = I40E_PF_ATQBAH;
  78                 hw->aq.arq.tail = I40E_PF_ARQT;
  79                 hw->aq.arq.head = I40E_PF_ARQH;
  80                 hw->aq.arq.len  = I40E_PF_ARQLEN;
  81                 hw->aq.arq.bal  = I40E_PF_ARQBAL;
  82                 hw->aq.arq.bah  = I40E_PF_ARQBAH;
  83         }
  84 }
  85
  86 /**
  87  *  i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
  88  *  @hw: pointer to the hardware structure
  89  **/
  90 enum i40e_status_code i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
  91 {
  92         enum i40e_status_code ret_code;
  93
  94         ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
  95                                          i40e_mem_atq_ring,
  96                                          (hw->aq.num_asq_entries *
  97                                          sizeof(struct i40e_aq_desc)),
  98                                          I40E_ADMINQ_DESC_ALIGNMENT);
  99         if (ret_code)
 100                 return ret_code;
 101
 102         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
 103                                           (hw->aq.num_asq_entries *
 104                                           sizeof(struct i40e_asq_cmd_details)));
 105         if (ret_code) {
 106                 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
 107                 return ret_code;
 108         }
 109
 110         return ret_code;
 111 }
 112
 113 /**
 114  *  i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
 115  *  @hw: pointer to the hardware structure
 116  **/
 117 enum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
 118 {
 119         enum i40e_status_code ret_code;
 120
 121         ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
 122                                          i40e_mem_arq_ring,
 123                                          (hw->aq.num_arq_entries *
 124                                          sizeof(struct i40e_aq_desc)),
 125                                          I40E_ADMINQ_DESC_ALIGNMENT);
 126
 127         return ret_code;
 128 }
 129
 130 /**
 131  *  i40e_free_adminq_asq - Free Admin Queue send rings
 132  *  @hw: pointer to the hardware structure
 133  *
 134  *  This assumes the posted send buffers have already been cleaned
 135  *  and de-allocated
 136  **/
 137 void i40e_free_adminq_asq(struct i40e_hw *hw)
 138 {
 139         i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
 140 }
 141
 142 /**
 143  *  i40e_free_adminq_arq - Free Admin Queue receive rings
 144  *  @hw: pointer to the hardware structure
 145  *
 146  *  This assumes the posted receive buffers have already been cleaned
 147  *  and de-allocated
 148  **/
 149 void i40e_free_adminq_arq(struct i40e_hw *hw)
 150 {
 151         i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
 152 }
 153
 154 /**
 155  *  i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
 156  *  @hw: pointer to the hardware structure
 157  **/
 158 STATIC enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw)
 159 {
 160         enum i40e_status_code ret_code;
 161         struct i40e_aq_desc *desc;
 162         struct i40e_dma_mem *bi;
 163         int i;
 164
 165         /* We'll be allocating the buffer info memory first, then we can
 166          * allocate the mapped buffers for the event processing
 167          */
 168
 169         /* buffer_info structures do not need alignment */
 170         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
 171                 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
 172         if (ret_code)
 173                 goto alloc_arq_bufs;
 174         hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
 175
 176         /* allocate the mapped buffers */
 177         for (i = 0; i < hw->aq.num_arq_entries; i++) {
 178                 bi = &hw->aq.arq.r.arq_bi[i];
 179                 ret_code = i40e_allocate_dma_mem(hw, bi,
 180                                                  i40e_mem_arq_buf,
 181                                                  hw->aq.arq_buf_size,
 182                                                  I40E_ADMINQ_DESC_ALIGNMENT);
 183                 if (ret_code)
 184                         goto unwind_alloc_arq_bufs;
 185
 186                 /* now configure the descriptors for use */
 187                 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
 188
 189                 desc->flags = CPU_TO_LE16(I40E_AQ_FLAG_BUF);
 190                 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
 191                         desc->flags |= CPU_TO_LE16(I40E_AQ_FLAG_LB);
 192                 desc->opcode = 0;
 193                 /* This is in accordance with Admin queue design, there is no
 194                  * register for buffer size configuration
 195                  */
 196                 desc->datalen = CPU_TO_LE16((u16)bi->size);
 197                 desc->retval = 0;
 198                 desc->cookie_high = 0;
 199                 desc->cookie_low = 0;
 200                 desc->params.external.addr_high =
 201                         CPU_TO_LE32(I40E_HI_DWORD(bi->pa));
 202                 desc->params.external.addr_low =
 203                         CPU_TO_LE32(I40E_LO_DWORD(bi->pa));
 204                 desc->params.external.param0 = 0;
 205                 desc->params.external.param1 = 0;
 206         }
 207
 208 alloc_arq_bufs:
 209         return ret_code;
 210
 211 unwind_alloc_arq_bufs:
 212         /* don't try to free the one that failed... */
 213         i--;
 214         for (; i >= 0; i--)
 215                 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
 216         i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
 217
 218         return ret_code;
 219 }
 220
 221 /**
 222  *  i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
 223  *  @hw: pointer to the hardware structure
 224  **/
 225 STATIC enum i40e_status_code i40e_alloc_asq_bufs(struct i40e_hw *hw)
 226 {
 227         enum i40e_status_code ret_code;
 228         struct i40e_dma_mem *bi;
 229         int i;
 230
 231         /* No mapped memory needed yet, just the buffer info structures */
 232         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
 233                 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
 234         if (ret_code)
 235                 goto alloc_asq_bufs;
 236         hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
 237
 238         /* allocate the mapped buffers */
 239         for (i = 0; i < hw->aq.num_asq_entries; i++) {
 240                 bi = &hw->aq.asq.r.asq_bi[i];
 241                 ret_code = i40e_allocate_dma_mem(hw, bi,
 242                                                  i40e_mem_asq_buf,
 243                                                  hw->aq.asq_buf_size,
 244                                                  I40E_ADMINQ_DESC_ALIGNMENT);
 245                 if (ret_code)
 246                         goto unwind_alloc_asq_bufs;
 247         }
 248 alloc_asq_bufs:
 249         return ret_code;
 250
 251 unwind_alloc_asq_bufs:
 252         /* don't try to free the one that failed... */
 253         i--;
 254         for (; i >= 0; i--)
 255                 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
 256         i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
 257
 258         return ret_code;
 259 }
 260
 261 /**
 262  *  i40e_free_arq_bufs - Free receive queue buffer info elements
 263  *  @hw: pointer to the hardware structure
 264  **/
 265 STATIC void i40e_free_arq_bufs(struct i40e_hw *hw)
 266 {
 267         int i;
 268
 269         /* free descriptors */
 270         for (i = 0; i < hw->aq.num_arq_entries; i++)
 271                 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
 272
 273         /* free the descriptor memory */
 274         i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
 275
 276         /* free the dma header */
 277         i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
 278 }
 279
 280 /**
 281  *  i40e_free_asq_bufs - Free send queue buffer info elements
 282  *  @hw: pointer to the hardware structure
 283  **/
 284 STATIC void i40e_free_asq_bufs(struct i40e_hw *hw)
 285 {
 286         int i;
 287
 288         /* only unmap if the address is non-NULL */
 289         for (i = 0; i < hw->aq.num_asq_entries; i++)
 290                 if (hw->aq.asq.r.asq_bi[i].pa)
 291                         i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
 292
 293         /* free the buffer info list */
 294         i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
 295
 296         /* free the descriptor memory */
 297         i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
 298
 299         /* free the dma header */
 300         i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
 301 }
 302
 303 /**
 304  *  i40e_config_asq_regs - configure ASQ registers
 305  *  @hw: pointer to the hardware structure
 306  *
 307  *  Configure base address and length registers for the transmit queue
 308  **/
 309 STATIC enum i40e_status_code i40e_config_asq_regs(struct i40e_hw *hw)
 310 {
 311         enum i40e_status_code ret_code = I40E_SUCCESS;
 312         u32 reg = 0;
 313
 314         /* Clear Head and Tail */
 315         wr32(hw, hw->aq.asq.head, 0);
 316         wr32(hw, hw->aq.asq.tail, 0);
 317
 318         /* set starting point */
 319         wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
 320                                   I40E_PF_ATQLEN_ATQENABLE_MASK));
 321         wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
 322         wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
 323
 324         /* Check one register to verify that config was applied */
 325         reg = rd32(hw, hw->aq.asq.bal);
 326         if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
 327                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 328
 329         return ret_code;
 330 }
 331
 332 /**
 333  *  i40e_config_arq_regs - ARQ register configuration
 334  *  @hw: pointer to the hardware structure
 335  *
 336  * Configure base address and length registers for the receive (event queue)
 337  **/
 338 STATIC enum i40e_status_code i40e_config_arq_regs(struct i40e_hw *hw)
 339 {
 340         enum i40e_status_code ret_code = I40E_SUCCESS;
 341         u32 reg = 0;
 342
 343         /* Clear Head and Tail */
 344         wr32(hw, hw->aq.arq.head, 0);
 345         wr32(hw, hw->aq.arq.tail, 0);
 346
 347         /* set starting point */
 348         wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
 349                                   I40E_PF_ARQLEN_ARQENABLE_MASK));
 350         wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
 351         wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
 352
 353         /* Update tail in the HW to post pre-allocated buffers */
 354         wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
 355
 356         /* Check one register to verify that config was applied */
 357         reg = rd32(hw, hw->aq.arq.bal);
 358         if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa))
 359                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 360
 361         return ret_code;
 362 }
 363
 364 /**
 365  *  i40e_init_asq - main initialization routine for ASQ
 366  *  @hw: pointer to the hardware structure
 367  *
 368  *  This is the main initialization routine for the Admin Send Queue
 369  *  Prior to calling this function, drivers *MUST* set the following fields
 370  *  in the hw->aq structure:
 371  *     - hw->aq.num_asq_entries
 372  *     - hw->aq.arq_buf_size
 373  *
 374  *  Do *NOT* hold the lock when calling this as the memory allocation routines
 375  *  called are not going to be atomic context safe
 376  **/
 377 enum i40e_status_code i40e_init_asq(struct i40e_hw *hw)
 378 {
 379         enum i40e_status_code ret_code = I40E_SUCCESS;
 380
 381         if (hw->aq.asq.count > 0) {
 382                 /* queue already initialized */
 383                 ret_code = I40E_ERR_NOT_READY;
 384                 goto init_adminq_exit;
 385         }
 386
 387         /* verify input for valid configuration */
 388         if ((hw->aq.num_asq_entries == 0) ||
 389             (hw->aq.asq_buf_size == 0)) {
 390                 ret_code = I40E_ERR_CONFIG;
 391                 goto init_adminq_exit;
 392         }
 393
 394         hw->aq.asq.next_to_use = 0;
 395         hw->aq.asq.next_to_clean = 0;
 396         hw->aq.asq.count = hw->aq.num_asq_entries;
 397
 398         /* allocate the ring memory */
 399         ret_code = i40e_alloc_adminq_asq_ring(hw);
 400         if (ret_code != I40E_SUCCESS)
 401                 goto init_adminq_exit;
 402
 403         /* allocate buffers in the rings */
 404         ret_code = i40e_alloc_asq_bufs(hw);
 405         if (ret_code != I40E_SUCCESS)
 406                 goto init_adminq_free_rings;
 407
 408         /* initialize base registers */
 409         ret_code = i40e_config_asq_regs(hw);
 410         if (ret_code != I40E_SUCCESS)
 411                 goto init_adminq_free_rings;
 412
 413         /* success! */
 414         goto init_adminq_exit;
 415
 416 init_adminq_free_rings:
 417         i40e_free_adminq_asq(hw);
 418
 419 init_adminq_exit:
 420         return ret_code;
 421 }
 422
 423 /**
 424  *  i40e_init_arq - initialize ARQ
 425  *  @hw: pointer to the hardware structure
 426  *
 427  *  The main initialization routine for the Admin Receive (Event) Queue.
 428  *  Prior to calling this function, drivers *MUST* set the following fields
 429  *  in the hw->aq structure:
 430  *     - hw->aq.num_asq_entries
 431  *     - hw->aq.arq_buf_size
 432  *
 433  *  Do *NOT* hold the lock when calling this as the memory allocation routines
 434  *  called are not going to be atomic context safe
 435  **/
 436 enum i40e_status_code i40e_init_arq(struct i40e_hw *hw)
 437 {
 438         enum i40e_status_code ret_code = I40E_SUCCESS;
 439
 440         if (hw->aq.arq.count > 0) {
 441                 /* queue already initialized */
 442                 ret_code = I40E_ERR_NOT_READY;
 443                 goto init_adminq_exit;
 444         }
 445
 446         /* verify input for valid configuration */
 447         if ((hw->aq.num_arq_entries == 0) ||
 448             (hw->aq.arq_buf_size == 0)) {
 449                 ret_code = I40E_ERR_CONFIG;
 450                 goto init_adminq_exit;
 451         }
 452
 453         hw->aq.arq.next_to_use = 0;
 454         hw->aq.arq.next_to_clean = 0;
 455         hw->aq.arq.count = hw->aq.num_arq_entries;
 456
 457         /* allocate the ring memory */
 458         ret_code = i40e_alloc_adminq_arq_ring(hw);
 459         if (ret_code != I40E_SUCCESS)
 460                 goto init_adminq_exit;
 461
 462         /* allocate buffers in the rings */
 463         ret_code = i40e_alloc_arq_bufs(hw);
 464         if (ret_code != I40E_SUCCESS)
 465                 goto init_adminq_free_rings;
 466
 467         /* initialize base registers */
 468         ret_code = i40e_config_arq_regs(hw);
 469         if (ret_code != I40E_SUCCESS)
 470                 goto init_adminq_free_rings;
 471
 472         /* success! */
 473         goto init_adminq_exit;
 474
 475 init_adminq_free_rings:
 476         i40e_free_adminq_arq(hw);
 477
 478 init_adminq_exit:
 479         return ret_code;
 480 }
 481
 482 /**
 483  *  i40e_shutdown_asq - shutdown the ASQ
 484  *  @hw: pointer to the hardware structure
 485  *
 486  *  The main shutdown routine for the Admin Send Queue
 487  **/
 488 enum i40e_status_code i40e_shutdown_asq(struct i40e_hw *hw)
 489 {
 490         enum i40e_status_code ret_code = I40E_SUCCESS;
 491
 492         i40e_acquire_spinlock(&hw->aq.asq_spinlock);
 493
 494         if (hw->aq.asq.count == 0) {
 495                 ret_code = I40E_ERR_NOT_READY;
 496                 goto shutdown_asq_out;
 497         }
 498
 499         /* Stop firmware AdminQ processing */
 500         wr32(hw, hw->aq.asq.head, 0);
 501         wr32(hw, hw->aq.asq.tail, 0);
 502         wr32(hw, hw->aq.asq.len, 0);
 503         wr32(hw, hw->aq.asq.bal, 0);
 504         wr32(hw, hw->aq.asq.bah, 0);
 505
 506         hw->aq.asq.count = 0; /* to indicate uninitialized queue */
 507
 508         /* free ring buffers */
 509         i40e_free_asq_bufs(hw);
 510
 511 shutdown_asq_out:
 512         i40e_release_spinlock(&hw->aq.asq_spinlock);
 513         return ret_code;
 514 }
 515
 516 /**
 517  *  i40e_shutdown_arq - shutdown ARQ
 518  *  @hw: pointer to the hardware structure
 519  *
 520  *  The main shutdown routine for the Admin Receive Queue
 521  **/
 522 enum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw)
 523 {
 524         enum i40e_status_code ret_code = I40E_SUCCESS;
 525
 526         i40e_acquire_spinlock(&hw->aq.arq_spinlock);
 527
 528         if (hw->aq.arq.count == 0) {
 529                 ret_code = I40E_ERR_NOT_READY;
 530                 goto shutdown_arq_out;
 531         }
 532
 533         /* Stop firmware AdminQ processing */
 534         wr32(hw, hw->aq.arq.head, 0);
 535         wr32(hw, hw->aq.arq.tail, 0);
 536         wr32(hw, hw->aq.arq.len, 0);
 537         wr32(hw, hw->aq.arq.bal, 0);
 538         wr32(hw, hw->aq.arq.bah, 0);
 539
 540         hw->aq.arq.count = 0; /* to indicate uninitialized queue */
 541
 542         /* free ring buffers */
 543         i40e_free_arq_bufs(hw);
 544
 545 shutdown_arq_out:
 546         i40e_release_spinlock(&hw->aq.arq_spinlock);
 547         return ret_code;
 548 }
 549
 550 /**
 551  *  i40e_init_adminq - main initialization routine for Admin Queue
 552  *  @hw: pointer to the hardware structure
 553  *
 554  *  Prior to calling this function, drivers *MUST* set the following fields
 555  *  in the hw->aq structure:
 556  *     - hw->aq.num_asq_entries
 557  *     - hw->aq.num_arq_entries
 558  *     - hw->aq.arq_buf_size
 559  *     - hw->aq.asq_buf_size
 560  **/
 561 enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
 562 {
 563         enum i40e_status_code ret_code;
 564 #ifdef PF_DRIVER
 565         u16 eetrack_lo, eetrack_hi;
 566         int retry = 0;
 567 #endif
 568         /* verify input for valid configuration */
 569         if ((hw->aq.num_arq_entries == 0) ||
 570             (hw->aq.num_asq_entries == 0) ||
 571             (hw->aq.arq_buf_size == 0) ||
 572             (hw->aq.asq_buf_size == 0)) {
 573                 ret_code = I40E_ERR_CONFIG;
 574                 goto init_adminq_exit;
 575         }
 576
 577         /* initialize spin locks */
 578         i40e_init_spinlock(&hw->aq.asq_spinlock);
 579         i40e_init_spinlock(&hw->aq.arq_spinlock);
 580
 581         /* Set up register offsets */
 582         i40e_adminq_init_regs(hw);
 583
 584         /* setup ASQ command write back timeout */
 585         hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
 586
 587         /* allocate the ASQ */
 588         ret_code = i40e_init_asq(hw);
 589         if (ret_code != I40E_SUCCESS)
 590                 goto init_adminq_destroy_spinlocks;
 591
 592         /* allocate the ARQ */
 593         ret_code = i40e_init_arq(hw);
 594         if (ret_code != I40E_SUCCESS)
 595                 goto init_adminq_free_asq;
 596
 597 #ifdef PF_DRIVER
 598 #ifdef INTEGRATED_VF
 599         /* VF has no need of firmware */
 600         if (i40e_is_vf(hw))
 601                 goto init_adminq_exit;
 602 #endif
 603         /* There are some cases where the firmware may not be quite ready
 604          * for AdminQ operations, so we retry the AdminQ setup a few times
 605          * if we see timeouts in this first AQ call.
 606          */
 607         do {
 608                 ret_code = i40e_aq_get_firmware_version(hw,
 609                                                         &hw->aq.fw_maj_ver,
 610                                                         &hw->aq.fw_min_ver,
 611                                                         &hw->aq.fw_build,
 612                                                         &hw->aq.api_maj_ver,
 613                                                         &hw->aq.api_min_ver,
 614                                                         NULL);
 615                 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
 616                         break;
 617                 retry++;
 618                 i40e_msec_delay(100);
 619                 i40e_resume_aq(hw);
 620         } while (retry < 10);
 621         if (ret_code != I40E_SUCCESS)
 622                 goto init_adminq_free_arq;
 623
 624         /* get the NVM version info */
 625         i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,
 626                            &hw->nvm.version);
 627         i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
 628         i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
 629         hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
 630
 631         if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
 632                 ret_code = I40E_ERR_FIRMWARE_API_VERSION;
 633                 goto init_adminq_free_arq;
 634         }
 635
 636         /* pre-emptive resource lock release */
 637         i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
 638         hw->aq.nvm_release_on_done = false;
 639         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 640
 641         ret_code = i40e_aq_set_hmc_resource_profile(hw,
 642                                                     I40E_HMC_PROFILE_DEFAULT,
 643                                                     0,
 644                                                     NULL);
 645 #endif /* PF_DRIVER */
 646         ret_code = I40E_SUCCESS;
 647
 648         /* success! */
 649         goto init_adminq_exit;
 650
 651 #ifdef PF_DRIVER
 652 init_adminq_free_arq:
 653         i40e_shutdown_arq(hw);
 654 #endif
 655 init_adminq_free_asq:
 656         i40e_shutdown_asq(hw);
 657 init_adminq_destroy_spinlocks:
 658         i40e_destroy_spinlock(&hw->aq.asq_spinlock);
 659         i40e_destroy_spinlock(&hw->aq.arq_spinlock);
 660
 661 init_adminq_exit:
 662         return ret_code;
 663 }
 664
 665 /**
 666  *  i40e_shutdown_adminq - shutdown routine for the Admin Queue
 667  *  @hw: pointer to the hardware structure
 668  **/
 669 enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw)
 670 {
 671         enum i40e_status_code ret_code = I40E_SUCCESS;
 672
 673         if (i40e_check_asq_alive(hw))
 674                 i40e_aq_queue_shutdown(hw, true);
 675
 676         i40e_shutdown_asq(hw);
 677         i40e_shutdown_arq(hw);
 678
 679         /* destroy the spinlocks */
 680         i40e_destroy_spinlock(&hw->aq.asq_spinlock);
 681         i40e_destroy_spinlock(&hw->aq.arq_spinlock);
 682
 683         if (hw->nvm_buff.va)
 684                 i40e_free_virt_mem(hw, &hw->nvm_buff);
 685
 686         return ret_code;
 687 }
 688
 689 /**
 690  *  i40e_clean_asq - cleans Admin send queue
 691  *  @hw: pointer to the hardware structure
 692  *
 693  *  returns the number of free desc
 694  **/
 695 u16 i40e_clean_asq(struct i40e_hw *hw)
 696 {
 697         struct i40e_adminq_ring *asq = &(hw->aq.asq);
 698         struct i40e_asq_cmd_details *details;
 699         u16 ntc = asq->next_to_clean;
 700         struct i40e_aq_desc desc_cb;
 701         struct i40e_aq_desc *desc;
 702
 703         desc = I40E_ADMINQ_DESC(*asq, ntc);
 704         details = I40E_ADMINQ_DETAILS(*asq, ntc);
 705         while (rd32(hw, hw->aq.asq.head) != ntc) {
 706                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 707                            "%s: ntc %d head %d.\n", __FUNCTION__, ntc,
 708                            rd32(hw, hw->aq.asq.head));
 709
 710                 if (details->callback) {
 711                         I40E_ADMINQ_CALLBACK cb_func =
 712                                         (I40E_ADMINQ_CALLBACK)details->callback;
 713                         i40e_memcpy(&desc_cb, desc,
 714                                     sizeof(struct i40e_aq_desc), I40E_DMA_TO_DMA);
 715                         cb_func(hw, &desc_cb);
 716                 }
 717                 i40e_memset(desc, 0, sizeof(*desc), I40E_DMA_MEM);
 718                 i40e_memset(details, 0, sizeof(*details), I40E_NONDMA_MEM);
 719                 ntc++;
 720                 if (ntc == asq->count)
 721                         ntc = 0;
 722                 desc = I40E_ADMINQ_DESC(*asq, ntc);
 723                 details = I40E_ADMINQ_DETAILS(*asq, ntc);
 724         }
 725
 726         asq->next_to_clean = ntc;
 727
 728         return I40E_DESC_UNUSED(asq);
 729 }
 730
 731 /**
 732  *  i40e_asq_done - check if FW has processed the Admin Send Queue
 733  *  @hw: pointer to the hw struct
 734  *
 735  *  Returns true if the firmware has processed all descriptors on the
 736  *  admin send queue. Returns false if there are still requests pending.
 737  **/
 738 bool i40e_asq_done(struct i40e_hw *hw)
 739 {
 740         /* AQ designers suggest use of head for better
 741          * timing reliability than DD bit
 742          */
 743         return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
 744
 745 }
 746
 747 /**
 748  *  i40e_asq_send_command - send command to Admin Queue
 749  *  @hw: pointer to the hw struct
 750  *  @desc: prefilled descriptor describing the command (non DMA mem)
 751  *  @buff: buffer to use for indirect commands
 752  *  @buff_size: size of buffer for indirect commands
 753  *  @cmd_details: pointer to command details structure
 754  *
 755  *  This is the main send command driver routine for the Admin Queue send
 756  *  queue.  It runs the queue, cleans the queue, etc
 757  **/
 758 enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
 759                                 struct i40e_aq_desc *desc,
 760                                 void *buff, /* can be NULL */
 761                                 u16  buff_size,
 762                                 struct i40e_asq_cmd_details *cmd_details)
 763 {
 764         enum i40e_status_code status = I40E_SUCCESS;
 765         struct i40e_dma_mem *dma_buff = NULL;
 766         struct i40e_asq_cmd_details *details;
 767         struct i40e_aq_desc *desc_on_ring;
 768         bool cmd_completed = false;
 769         u16  retval = 0;
 770         u32  val = 0;
 771
 772         i40e_acquire_spinlock(&hw->aq.asq_spinlock);
 773
 774         hw->aq.asq_last_status = I40E_AQ_RC_OK;
 775
 776         if (hw->aq.asq.count == 0) {
 777                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 778                            "AQTX: Admin queue not initialized.\n");
 779                 status = I40E_ERR_QUEUE_EMPTY;
 780                 goto asq_send_command_error;
 781         }
 782
 783         val = rd32(hw, hw->aq.asq.head);
 784         if (val >= hw->aq.num_asq_entries) {
 785                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 786                            "AQTX: head overrun at %d\n", val);
 787                 status = I40E_ERR_QUEUE_EMPTY;
 788                 goto asq_send_command_error;
 789         }
 790
 791         details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
 792         if (cmd_details) {
 793                 i40e_memcpy(details,
 794                             cmd_details,
 795                             sizeof(struct i40e_asq_cmd_details),
 796                             I40E_NONDMA_TO_NONDMA);
 797
 798                 /* If the cmd_details are defined copy the cookie.  The
 799                  * CPU_TO_LE32 is not needed here because the data is ignored
 800                  * by the FW, only used by the driver
 801                  */
 802                 if (details->cookie) {
 803                         desc->cookie_high =
 804                                 CPU_TO_LE32(I40E_HI_DWORD(details->cookie));
 805                         desc->cookie_low =
 806                                 CPU_TO_LE32(I40E_LO_DWORD(details->cookie));
 807                 }
 808         } else {
 809                 i40e_memset(details, 0,
 810                             sizeof(struct i40e_asq_cmd_details),
 811                             I40E_NONDMA_MEM);
 812         }
 813
 814         /* clear requested flags and then set additional flags if defined */
 815         desc->flags &= ~CPU_TO_LE16(details->flags_dis);
 816         desc->flags |= CPU_TO_LE16(details->flags_ena);
 817
 818         if (buff_size > hw->aq.asq_buf_size) {
 819                 i40e_debug(hw,
 820                            I40E_DEBUG_AQ_MESSAGE,
 821                            "AQTX: Invalid buffer size: %d.\n",
 822                            buff_size);
 823                 status = I40E_ERR_INVALID_SIZE;
 824                 goto asq_send_command_error;
 825         }
 826
 827         if (details->postpone && !details->async) {
 828                 i40e_debug(hw,
 829                            I40E_DEBUG_AQ_MESSAGE,
 830                            "AQTX: Async flag not set along with postpone flag");
 831                 status = I40E_ERR_PARAM;
 832                 goto asq_send_command_error;
 833         }
 834
 835         /* call clean and check queue available function to reclaim the
 836          * descriptors that were processed by FW, the function returns the
 837          * number of desc available
 838          */
 839         /* the clean function called here could be called in a separate thread
 840          * in case of asynchronous completions
 841          */
 842         if (i40e_clean_asq(hw) == 0) {
 843                 i40e_debug(hw,
 844                            I40E_DEBUG_AQ_MESSAGE,
 845                            "AQTX: Error queue is full.\n");
 846                 status = I40E_ERR_ADMIN_QUEUE_FULL;
 847                 goto asq_send_command_error;
 848         }
 849
 850         /* initialize the temp desc pointer with the right desc */
 851         desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
 852
 853         /* if the desc is available copy the temp desc to the right place */
 854         i40e_memcpy(desc_on_ring, desc, sizeof(struct i40e_aq_desc),
 855                     I40E_NONDMA_TO_DMA);
 856
 857         /* if buff is not NULL assume indirect command */
 858         if (buff != NULL) {
 859                 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
 860                 /* copy the user buff into the respective DMA buff */
 861                 i40e_memcpy(dma_buff->va, buff, buff_size,
 862                             I40E_NONDMA_TO_DMA);
 863                 desc_on_ring->datalen = CPU_TO_LE16(buff_size);
 864
 865                 /* Update the address values in the desc with the pa value
 866                  * for respective buffer
 867                  */
 868                 desc_on_ring->params.external.addr_high =
 869                                 CPU_TO_LE32(I40E_HI_DWORD(dma_buff->pa));
 870                 desc_on_ring->params.external.addr_low =
 871                                 CPU_TO_LE32(I40E_LO_DWORD(dma_buff->pa));
 872         }
 873
 874         /* bump the tail */
 875         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
 876         i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
 877                       buff, buff_size);
 878         (hw->aq.asq.next_to_use)++;
 879         if (hw->aq.asq.next_to_use == hw->aq.asq.count)
 880                 hw->aq.asq.next_to_use = 0;
 881         if (!details->postpone)
 882                 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
 883
 884         /* if cmd_details are not defined or async flag is not set,
 885          * we need to wait for desc write back
 886          */
 887         if (!details->async && !details->postpone) {
 888                 u32 total_delay = 0;
 889
 890                 do {
 891                         /* AQ designers suggest use of head for better
 892                          * timing reliability than DD bit
 893                          */
 894                         if (i40e_asq_done(hw))
 895                                 break;
 896                         /* ugh! delay while spin_lock */
 897                         i40e_msec_delay(1);
 898                         total_delay++;
 899                 } while (total_delay < hw->aq.asq_cmd_timeout);
 900         }
 901
 902         /* if ready, copy the desc back to temp */
 903         if (i40e_asq_done(hw)) {
 904                 i40e_memcpy(desc, desc_on_ring, sizeof(struct i40e_aq_desc),
 905                             I40E_DMA_TO_NONDMA);
 906                 if (buff != NULL)
 907                         i40e_memcpy(buff, dma_buff->va, buff_size,
 908                                     I40E_DMA_TO_NONDMA);
 909                 retval = LE16_TO_CPU(desc->retval);
 910                 if (retval != 0) {
 911                         i40e_debug(hw,
 912                                    I40E_DEBUG_AQ_MESSAGE,
 913                                    "AQTX: Command completed with error 0x%X.\n",
 914                                    retval);
 915
 916                         /* strip off FW internal code */
 917                         retval &= 0xff;
 918                 }
 919                 cmd_completed = true;
 920                 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
 921                         status = I40E_SUCCESS;
 922                 else
 923                         status = I40E_ERR_ADMIN_QUEUE_ERROR;
 924                 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
 925         }
 926
 927         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 928                    "AQTX: desc and buffer writeback:\n");
 929         i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
 930
 931         /* save writeback aq if requested */
 932         if (details->wb_desc)
 933                 i40e_memcpy(details->wb_desc, desc_on_ring,
 934                             sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA);
 935
 936         /* update the error if time out occurred */
 937         if ((!cmd_completed) &&
 938             (!details->async && !details->postpone)) {
 939                 i40e_debug(hw,
 940                            I40E_DEBUG_AQ_MESSAGE,
 941                            "AQTX: Writeback timeout.\n");
 942                 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
 943         }
 944
 945 asq_send_command_error:
 946         i40e_release_spinlock(&hw->aq.asq_spinlock);
 947         return status;
 948 }
 949
 950 /**
 951  *  i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
 952  *  @desc:     pointer to the temp descriptor (non DMA mem)
 953  *  @opcode:   the opcode can be used to decide which flags to turn off or on
 954  *
 955  *  Fill the desc with default values
 956  **/
 957 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
 958                                        u16 opcode)
 959 {
 960         /* zero out the desc */
 961         i40e_memset((void *)desc, 0, sizeof(struct i40e_aq_desc),
 962                     I40E_NONDMA_MEM);
 963         desc->opcode = CPU_TO_LE16(opcode);
 964         desc->flags = CPU_TO_LE16(I40E_AQ_FLAG_SI);
 965 }
 966
 967 /**
 968  *  i40e_clean_arq_element
 969  *  @hw: pointer to the hw struct
 970  *  @e: event info from the receive descriptor, includes any buffers
 971  *  @pending: number of events that could be left to process
 972  *
 973  *  This function cleans one Admin Receive Queue element and returns
 974  *  the contents through e.  It can also return how many events are
 975  *  left to process through 'pending'
 976  **/
 977 enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
 978                                              struct i40e_arq_event_info *e,
 979                                              u16 *pending)
 980 {
 981         enum i40e_status_code ret_code = I40E_SUCCESS;
 982         u16 ntc = hw->aq.arq.next_to_clean;
 983         struct i40e_aq_desc *desc;
 984         struct i40e_dma_mem *bi;
 985         u16 desc_idx;
 986         u16 datalen;
 987         u16 flags;
 988         u16 ntu;
 989
 990         /* take the lock before we start messing with the ring */
 991         i40e_acquire_spinlock(&hw->aq.arq_spinlock);
 992
 993         /* set next_to_use to head */
 994         ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
 995         if (ntu == ntc) {
 996                 /* nothing to do - shouldn't need to update ring's values */
 997                 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
 998                 goto clean_arq_element_out;
 999         }
1000
1001         /* now clean the next descriptor */
1002         desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
1003         desc_idx = ntc;
1004
1005         flags = LE16_TO_CPU(desc->flags);
1006         if (flags & I40E_AQ_FLAG_ERR) {
1007                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
1008                 hw->aq.arq_last_status =
1009                         (enum i40e_admin_queue_err)LE16_TO_CPU(desc->retval);
1010                 i40e_debug(hw,
1011                            I40E_DEBUG_AQ_MESSAGE,
1012                            "AQRX: Event received with error 0x%X.\n",
1013                            hw->aq.arq_last_status);
1014         }
1015
1016         i40e_memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc),
1017                     I40E_DMA_TO_NONDMA);
1018         datalen = LE16_TO_CPU(desc->datalen);
1019         e->msg_len = min(datalen, e->buf_len);
1020         if (e->msg_buf != NULL && (e->msg_len != 0))
1021                 i40e_memcpy(e->msg_buf,
1022                             hw->aq.arq.r.arq_bi[desc_idx].va,
1023                             e->msg_len, I40E_DMA_TO_NONDMA);
1024
1025         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
1026         i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
1027                       hw->aq.arq_buf_size);
1028
1029         /* Restore the original datalen and buffer address in the desc,
1030          * FW updates datalen to indicate the event message
1031          * size
1032          */
1033         bi = &hw->aq.arq.r.arq_bi[ntc];
1034         i40e_memset((void *)desc, 0, sizeof(struct i40e_aq_desc), I40E_DMA_MEM);
1035
1036         desc->flags = CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1037         if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
1038                 desc->flags |= CPU_TO_LE16(I40E_AQ_FLAG_LB);
1039         desc->datalen = CPU_TO_LE16((u16)bi->size);
1040         desc->params.external.addr_high = CPU_TO_LE32(I40E_HI_DWORD(bi->pa));
1041         desc->params.external.addr_low = CPU_TO_LE32(I40E_LO_DWORD(bi->pa));
1042
1043         /* set tail = the last cleaned desc index. */
1044         wr32(hw, hw->aq.arq.tail, ntc);
1045         /* ntc is updated to tail + 1 */
1046         ntc++;
1047         if (ntc == hw->aq.num_arq_entries)
1048                 ntc = 0;
1049         hw->aq.arq.next_to_clean = ntc;
1050         hw->aq.arq.next_to_use = ntu;
1051
1052 clean_arq_element_out:
1053         /* Set pending if needed, unlock and return */
1054         if (pending != NULL)
1055                 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
1056         i40e_release_spinlock(&hw->aq.arq_spinlock);
1057
1058 #ifdef PF_DRIVER
1059         if (i40e_is_nvm_update_op(&e->desc)) {
1060                 if (hw->aq.nvm_release_on_done) {
1061                         i40e_release_nvm(hw);
1062                         hw->aq.nvm_release_on_done = false;
1063                 }
1064
1065                 switch (hw->nvmupd_state) {
1066                 case I40E_NVMUPD_STATE_INIT_WAIT:
1067                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1068                         break;
1069
1070                 case I40E_NVMUPD_STATE_WRITE_WAIT:
1071                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1072                         break;
1073
1074                 default:
1075                         break;
1076                 }
1077         }
1078
1079 #endif
1080         return ret_code;
1081 }
1082
1083 void i40e_resume_aq(struct i40e_hw *hw)
1084 {
1085         /* Registers are reset after PF reset */
1086         hw->aq.asq.next_to_use = 0;
1087         hw->aq.asq.next_to_clean = 0;
1088
1089 #if (I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK)
1090 #error I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK
1091 #endif
1092         i40e_config_asq_regs(hw);
1093
1094         hw->aq.arq.next_to_use = 0;
1095         hw->aq.arq.next_to_clean = 0;
1096
1097         i40e_config_arq_regs(hw);
1098 }