drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  19 #else
  20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  21 #endif
  22 {
  23         enum i40e_status_code status = I40E_SUCCESS;
  24
  25         DEBUGFUNC("i40e_set_mac_type\n");
  26
  27         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  28                 switch (hw->device_id) {
  29                 case I40E_DEV_ID_SFP_XL710:
  30                 case I40E_DEV_ID_QEMU:
  31                 case I40E_DEV_ID_KX_B:
  32                 case I40E_DEV_ID_KX_C:
  33                 case I40E_DEV_ID_QSFP_A:
  34                 case I40E_DEV_ID_QSFP_B:
  35                 case I40E_DEV_ID_QSFP_C:
  36                 case I40E_DEV_ID_10G_BASE_T:
  37                 case I40E_DEV_ID_10G_BASE_T4:
  38                 case I40E_DEV_ID_20G_KR2:
  39                 case I40E_DEV_ID_20G_KR2_A:
  40                 case I40E_DEV_ID_25G_B:
  41                 case I40E_DEV_ID_25G_SFP28:
  42                         hw->mac.type = I40E_MAC_XL710;
  43                         break;
  44 #ifdef X722_A0_SUPPORT
  45                 case I40E_DEV_ID_X722_A0:
  46 #endif
  47                 case I40E_DEV_ID_KX_X722:
  48                 case I40E_DEV_ID_QSFP_X722:
  49                 case I40E_DEV_ID_SFP_X722:
  50                 case I40E_DEV_ID_1G_BASE_T_X722:
  51                 case I40E_DEV_ID_10G_BASE_T_X722:
  52                 case I40E_DEV_ID_SFP_I_X722:
  53                         hw->mac.type = I40E_MAC_X722;
  54                         break;
  55 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  56                 case I40E_DEV_ID_X722_VF:
  57 #ifdef X722_A0_SUPPORT
  58                 case I40E_DEV_ID_X722_A0_VF:
  59 #endif
  60                         hw->mac.type = I40E_MAC_X722_VF;
  61                         break;
  62 #endif /* INTEGRATED_VF || VF_DRIVER */
  63 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  64                 case I40E_DEV_ID_VF:
  65                 case I40E_DEV_ID_VF_HV:
  66                 case I40E_DEV_ID_ADAPTIVE_VF:
  67                         hw->mac.type = I40E_MAC_VF;
  68                         break;
  69 #endif
  70                 default:
  71                         hw->mac.type = I40E_MAC_GENERIC;
  72                         break;
  73                 }
  74         } else {
  75                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  76         }
  77
  78         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  79                   hw->mac.type, status);
  80         return status;
  81 }
  82
  83 /**
  84  * i40e_aq_str - convert AQ err code to a string
  85  * @hw: pointer to the HW structure
  86  * @aq_err: the AQ error code to convert
  87  **/
  88 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  89 {
  90         switch (aq_err) {
  91         case I40E_AQ_RC_OK:
  92                 return "OK";
  93         case I40E_AQ_RC_EPERM:
  94                 return "I40E_AQ_RC_EPERM";
  95         case I40E_AQ_RC_ENOENT:
  96                 return "I40E_AQ_RC_ENOENT";
  97         case I40E_AQ_RC_ESRCH:
  98                 return "I40E_AQ_RC_ESRCH";
  99         case I40E_AQ_RC_EINTR:
 100                 return "I40E_AQ_RC_EINTR";
 101         case I40E_AQ_RC_EIO:
 102                 return "I40E_AQ_RC_EIO";
 103         case I40E_AQ_RC_ENXIO:
 104                 return "I40E_AQ_RC_ENXIO";
 105         case I40E_AQ_RC_E2BIG:
 106                 return "I40E_AQ_RC_E2BIG";
 107         case I40E_AQ_RC_EAGAIN:
 108                 return "I40E_AQ_RC_EAGAIN";
 109         case I40E_AQ_RC_ENOMEM:
 110                 return "I40E_AQ_RC_ENOMEM";
 111         case I40E_AQ_RC_EACCES:
 112                 return "I40E_AQ_RC_EACCES";
 113         case I40E_AQ_RC_EFAULT:
 114                 return "I40E_AQ_RC_EFAULT";
 115         case I40E_AQ_RC_EBUSY:
 116                 return "I40E_AQ_RC_EBUSY";
 117         case I40E_AQ_RC_EEXIST:
 118                 return "I40E_AQ_RC_EEXIST";
 119         case I40E_AQ_RC_EINVAL:
 120                 return "I40E_AQ_RC_EINVAL";
 121         case I40E_AQ_RC_ENOTTY:
 122                 return "I40E_AQ_RC_ENOTTY";
 123         case I40E_AQ_RC_ENOSPC:
 124                 return "I40E_AQ_RC_ENOSPC";
 125         case I40E_AQ_RC_ENOSYS:
 126                 return "I40E_AQ_RC_ENOSYS";
 127         case I40E_AQ_RC_ERANGE:
 128                 return "I40E_AQ_RC_ERANGE";
 129         case I40E_AQ_RC_EFLUSHED:
 130                 return "I40E_AQ_RC_EFLUSHED";
 131         case I40E_AQ_RC_BAD_ADDR:
 132                 return "I40E_AQ_RC_BAD_ADDR";
 133         case I40E_AQ_RC_EMODE:
 134                 return "I40E_AQ_RC_EMODE";
 135         case I40E_AQ_RC_EFBIG:
 136                 return "I40E_AQ_RC_EFBIG";
 137         }
 138
 139         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 140         return hw->err_str;
 141 }
 142
 143 /**
 144  * i40e_stat_str - convert status err code to a string
 145  * @hw: pointer to the HW structure
 146  * @stat_err: the status error code to convert
 147  **/
 148 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 149 {
 150         switch (stat_err) {
 151         case I40E_SUCCESS:
 152                 return "OK";
 153         case I40E_ERR_NVM:
 154                 return "I40E_ERR_NVM";
 155         case I40E_ERR_NVM_CHECKSUM:
 156                 return "I40E_ERR_NVM_CHECKSUM";
 157         case I40E_ERR_PHY:
 158                 return "I40E_ERR_PHY";
 159         case I40E_ERR_CONFIG:
 160                 return "I40E_ERR_CONFIG";
 161         case I40E_ERR_PARAM:
 162                 return "I40E_ERR_PARAM";
 163         case I40E_ERR_MAC_TYPE:
 164                 return "I40E_ERR_MAC_TYPE";
 165         case I40E_ERR_UNKNOWN_PHY:
 166                 return "I40E_ERR_UNKNOWN_PHY";
 167         case I40E_ERR_LINK_SETUP:
 168                 return "I40E_ERR_LINK_SETUP";
 169         case I40E_ERR_ADAPTER_STOPPED:
 170                 return "I40E_ERR_ADAPTER_STOPPED";
 171         case I40E_ERR_INVALID_MAC_ADDR:
 172                 return "I40E_ERR_INVALID_MAC_ADDR";
 173         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 174                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 175         case I40E_ERR_MASTER_REQUESTS_PENDING:
 176                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 177         case I40E_ERR_INVALID_LINK_SETTINGS:
 178                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 179         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 180                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 181         case I40E_ERR_RESET_FAILED:
 182                 return "I40E_ERR_RESET_FAILED";
 183         case I40E_ERR_SWFW_SYNC:
 184                 return "I40E_ERR_SWFW_SYNC";
 185         case I40E_ERR_NO_AVAILABLE_VSI:
 186                 return "I40E_ERR_NO_AVAILABLE_VSI";
 187         case I40E_ERR_NO_MEMORY:
 188                 return "I40E_ERR_NO_MEMORY";
 189         case I40E_ERR_BAD_PTR:
 190                 return "I40E_ERR_BAD_PTR";
 191         case I40E_ERR_RING_FULL:
 192                 return "I40E_ERR_RING_FULL";
 193         case I40E_ERR_INVALID_PD_ID:
 194                 return "I40E_ERR_INVALID_PD_ID";
 195         case I40E_ERR_INVALID_QP_ID:
 196                 return "I40E_ERR_INVALID_QP_ID";
 197         case I40E_ERR_INVALID_CQ_ID:
 198                 return "I40E_ERR_INVALID_CQ_ID";
 199         case I40E_ERR_INVALID_CEQ_ID:
 200                 return "I40E_ERR_INVALID_CEQ_ID";
 201         case I40E_ERR_INVALID_AEQ_ID:
 202                 return "I40E_ERR_INVALID_AEQ_ID";
 203         case I40E_ERR_INVALID_SIZE:
 204                 return "I40E_ERR_INVALID_SIZE";
 205         case I40E_ERR_INVALID_ARP_INDEX:
 206                 return "I40E_ERR_INVALID_ARP_INDEX";
 207         case I40E_ERR_INVALID_FPM_FUNC_ID:
 208                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 209         case I40E_ERR_QP_INVALID_MSG_SIZE:
 210                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 211         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 212                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 213         case I40E_ERR_INVALID_FRAG_COUNT:
 214                 return "I40E_ERR_INVALID_FRAG_COUNT";
 215         case I40E_ERR_QUEUE_EMPTY:
 216                 return "I40E_ERR_QUEUE_EMPTY";
 217         case I40E_ERR_INVALID_ALIGNMENT:
 218                 return "I40E_ERR_INVALID_ALIGNMENT";
 219         case I40E_ERR_FLUSHED_QUEUE:
 220                 return "I40E_ERR_FLUSHED_QUEUE";
 221         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 222                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 223         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 224                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 225         case I40E_ERR_TIMEOUT:
 226                 return "I40E_ERR_TIMEOUT";
 227         case I40E_ERR_OPCODE_MISMATCH:
 228                 return "I40E_ERR_OPCODE_MISMATCH";
 229         case I40E_ERR_CQP_COMPL_ERROR:
 230                 return "I40E_ERR_CQP_COMPL_ERROR";
 231         case I40E_ERR_INVALID_VF_ID:
 232                 return "I40E_ERR_INVALID_VF_ID";
 233         case I40E_ERR_INVALID_HMCFN_ID:
 234                 return "I40E_ERR_INVALID_HMCFN_ID";
 235         case I40E_ERR_BACKING_PAGE_ERROR:
 236                 return "I40E_ERR_BACKING_PAGE_ERROR";
 237         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 238                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 239         case I40E_ERR_INVALID_PBLE_INDEX:
 240                 return "I40E_ERR_INVALID_PBLE_INDEX";
 241         case I40E_ERR_INVALID_SD_INDEX:
 242                 return "I40E_ERR_INVALID_SD_INDEX";
 243         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 244                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 245         case I40E_ERR_INVALID_SD_TYPE:
 246                 return "I40E_ERR_INVALID_SD_TYPE";
 247         case I40E_ERR_MEMCPY_FAILED:
 248                 return "I40E_ERR_MEMCPY_FAILED";
 249         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 250                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 251         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 252                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 253         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 254                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 255         case I40E_ERR_SRQ_ENABLED:
 256                 return "I40E_ERR_SRQ_ENABLED";
 257         case I40E_ERR_ADMIN_QUEUE_ERROR:
 258                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 259         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 260                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 261         case I40E_ERR_BUF_TOO_SHORT:
 262                 return "I40E_ERR_BUF_TOO_SHORT";
 263         case I40E_ERR_ADMIN_QUEUE_FULL:
 264                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 265         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 266                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 267         case I40E_ERR_BAD_IWARP_CQE:
 268                 return "I40E_ERR_BAD_IWARP_CQE";
 269         case I40E_ERR_NVM_BLANK_MODE:
 270                 return "I40E_ERR_NVM_BLANK_MODE";
 271         case I40E_ERR_NOT_IMPLEMENTED:
 272                 return "I40E_ERR_NOT_IMPLEMENTED";
 273         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 274                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 275         case I40E_ERR_DIAG_TEST_FAILED:
 276                 return "I40E_ERR_DIAG_TEST_FAILED";
 277         case I40E_ERR_NOT_READY:
 278                 return "I40E_ERR_NOT_READY";
 279         case I40E_NOT_SUPPORTED:
 280                 return "I40E_NOT_SUPPORTED";
 281         case I40E_ERR_FIRMWARE_API_VERSION:
 282                 return "I40E_ERR_FIRMWARE_API_VERSION";
 283         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 284                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 285         }
 286
 287         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 288         return hw->err_str;
 289 }
 290
 291 /**
 292  * i40e_debug_aq
 293  * @hw: debug mask related to admin queue
 294  * @mask: debug mask
 295  * @desc: pointer to admin queue descriptor
 296  * @buffer: pointer to command buffer
 297  * @buf_len: max length of buffer
 298  *
 299  * Dumps debug log about adminq command with descriptor contents.
 300  **/
 301 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 302                    void *buffer, u16 buf_len)
 303 {
 304         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 305         u8 *buf = (u8 *)buffer;
 306         u16 len;
 307         u16 i = 0;
 308
 309         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 310                 return;
 311
 312         len = LE16_TO_CPU(aq_desc->datalen);
 313
 314         i40e_debug(hw, mask,
 315                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 316                    LE16_TO_CPU(aq_desc->opcode),
 317                    LE16_TO_CPU(aq_desc->flags),
 318                    LE16_TO_CPU(aq_desc->datalen),
 319                    LE16_TO_CPU(aq_desc->retval));
 320         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 321                    LE32_TO_CPU(aq_desc->cookie_high),
 322                    LE32_TO_CPU(aq_desc->cookie_low));
 323         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 324                    LE32_TO_CPU(aq_desc->params.internal.param0),
 325                    LE32_TO_CPU(aq_desc->params.internal.param1));
 326         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 327                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 328                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 329
 330         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 331                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 332                 if (buf_len < len)
 333                         len = buf_len;
 334                 /* write the full 16-byte chunks */
 335                 for (i = 0; i < (len - 16); i += 16)
 336                         i40e_debug(hw, mask,
 337                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 338                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 339                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 340                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 341                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 342                 /* the most we could have left is 16 bytes, pad with zeros */
 343                 if (i < len) {
 344                         char d_buf[16];
 345                         int j, i_sav;
 346
 347                         i_sav = i;
 348                         memset(d_buf, 0, sizeof(d_buf));
 349                         for (j = 0; i < len; j++, i++)
 350                                 d_buf[j] = buf[i];
 351                         i40e_debug(hw, mask,
 352                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 353                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 354                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 355                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 356                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 357                 }
 358         }
 359 }
 360
 361 /**
 362  * i40e_check_asq_alive
 363  * @hw: pointer to the hw struct
 364  *
 365  * Returns true if Queue is enabled else false.
 366  **/
 367 bool i40e_check_asq_alive(struct i40e_hw *hw)
 368 {
 369         if (hw->aq.asq.len)
 370 #ifdef PF_DRIVER
 371 #ifdef INTEGRATED_VF
 372                 if (!i40e_is_vf(hw))
 373                         return !!(rd32(hw, hw->aq.asq.len) &
 374                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 375 #else
 376                 return !!(rd32(hw, hw->aq.asq.len) &
 377                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 378 #endif /* INTEGRATED_VF */
 379 #endif /* PF_DRIVER */
 380 #ifdef VF_DRIVER
 381 #ifdef INTEGRATED_VF
 382                 if (i40e_is_vf(hw))
 383                         return !!(rd32(hw, hw->aq.asq.len) &
 384                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 385 #else
 386                 return !!(rd32(hw, hw->aq.asq.len) &
 387                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 388 #endif /* INTEGRATED_VF */
 389 #endif /* VF_DRIVER */
 390         return false;
 391 }
 392
 393 /**
 394  * i40e_aq_queue_shutdown
 395  * @hw: pointer to the hw struct
 396  * @unloading: is the driver unloading itself
 397  *
 398  * Tell the Firmware that we're shutting down the AdminQ and whether
 399  * or not the driver is unloading as well.
 400  **/
 401 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 402                                              bool unloading)
 403 {
 404         struct i40e_aq_desc desc;
 405         struct i40e_aqc_queue_shutdown *cmd =
 406                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 407         enum i40e_status_code status;
 408
 409         i40e_fill_default_direct_cmd_desc(&desc,
 410                                           i40e_aqc_opc_queue_shutdown);
 411
 412         if (unloading)
 413                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 414         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 415
 416         return status;
 417 }
 418
 419 /**
 420  * i40e_aq_get_set_rss_lut
 421  * @hw: pointer to the hardware structure
 422  * @vsi_id: vsi fw index
 423  * @pf_lut: for PF table set true, for VSI table set false
 424  * @lut: pointer to the lut buffer provided by the caller
 425  * @lut_size: size of the lut buffer
 426  * @set: set true to set the table, false to get the table
 427  *
 428  * Internal function to get or set RSS look up table
 429  **/
 430 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 431                                                      u16 vsi_id, bool pf_lut,
 432                                                      u8 *lut, u16 lut_size,
 433                                                      bool set)
 434 {
 435         enum i40e_status_code status;
 436         struct i40e_aq_desc desc;
 437         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 438                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 439
 440         if (set)
 441                 i40e_fill_default_direct_cmd_desc(&desc,
 442                                                   i40e_aqc_opc_set_rss_lut);
 443         else
 444                 i40e_fill_default_direct_cmd_desc(&desc,
 445                                                   i40e_aqc_opc_get_rss_lut);
 446
 447         /* Indirect command */
 448         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 449         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 450
 451         cmd_resp->vsi_id =
 452                         CPU_TO_LE16((u16)((vsi_id <<
 453                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 454                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 455         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 456
 457         if (pf_lut)
 458                 cmd_resp->flags |= CPU_TO_LE16((u16)
 459                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 460                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 461                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 462         else
 463                 cmd_resp->flags |= CPU_TO_LE16((u16)
 464                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 465                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 466                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 467
 468         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 469
 470         return status;
 471 }
 472
 473 /**
 474  * i40e_aq_get_rss_lut
 475  * @hw: pointer to the hardware structure
 476  * @vsi_id: vsi fw index
 477  * @pf_lut: for PF table set true, for VSI table set false
 478  * @lut: pointer to the lut buffer provided by the caller
 479  * @lut_size: size of the lut buffer
 480  *
 481  * get the RSS lookup table, PF or VSI type
 482  **/
 483 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 484                                           bool pf_lut, u8 *lut, u16 lut_size)
 485 {
 486         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 487                                        false);
 488 }
 489
 490 /**
 491  * i40e_aq_set_rss_lut
 492  * @hw: pointer to the hardware structure
 493  * @vsi_id: vsi fw index
 494  * @pf_lut: for PF table set true, for VSI table set false
 495  * @lut: pointer to the lut buffer provided by the caller
 496  * @lut_size: size of the lut buffer
 497  *
 498  * set the RSS lookup table, PF or VSI type
 499  **/
 500 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 501                                           bool pf_lut, u8 *lut, u16 lut_size)
 502 {
 503         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 504 }
 505
 506 /**
 507  * i40e_aq_get_set_rss_key
 508  * @hw: pointer to the hw struct
 509  * @vsi_id: vsi fw index
 510  * @key: pointer to key info struct
 511  * @set: set true to set the key, false to get the key
 512  *
 513  * get the RSS key per VSI
 514  **/
 515 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 516                                       u16 vsi_id,
 517                                       struct i40e_aqc_get_set_rss_key_data *key,
 518                                       bool set)
 519 {
 520         enum i40e_status_code status;
 521         struct i40e_aq_desc desc;
 522         struct i40e_aqc_get_set_rss_key *cmd_resp =
 523                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 524         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 525
 526         if (set)
 527                 i40e_fill_default_direct_cmd_desc(&desc,
 528                                                   i40e_aqc_opc_set_rss_key);
 529         else
 530                 i40e_fill_default_direct_cmd_desc(&desc,
 531                                                   i40e_aqc_opc_get_rss_key);
 532
 533         /* Indirect command */
 534         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 535         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 536
 537         cmd_resp->vsi_id =
 538                         CPU_TO_LE16((u16)((vsi_id <<
 539                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 540                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 541         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 542
 543         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 544
 545         return status;
 546 }
 547
 548 /**
 549  * i40e_aq_get_rss_key
 550  * @hw: pointer to the hw struct
 551  * @vsi_id: vsi fw index
 552  * @key: pointer to key info struct
 553  *
 554  **/
 555 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 556                                       u16 vsi_id,
 557                                       struct i40e_aqc_get_set_rss_key_data *key)
 558 {
 559         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 560 }
 561
 562 /**
 563  * i40e_aq_set_rss_key
 564  * @hw: pointer to the hw struct
 565  * @vsi_id: vsi fw index
 566  * @key: pointer to key info struct
 567  *
 568  * set the RSS key per VSI
 569  **/
 570 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 571                                       u16 vsi_id,
 572                                       struct i40e_aqc_get_set_rss_key_data *key)
 573 {
 574         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 575 }
 576
 577 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 578  * hardware to a bit-field that can be used by SW to more easily determine the
 579  * packet type.
 580  *
 581  * Macros are used to shorten the table lines and make this table human
 582  * readable.
 583  *
 584  * We store the PTYPE in the top byte of the bit field - this is just so that
 585  * we can check that the table doesn't have a row missing, as the index into
 586  * the table should be the PTYPE.
 587  *
 588  * Typical work flow:
 589  *
 590  * IF NOT i40e_ptype_lookup[ptype].known
 591  * THEN
 592  *      Packet is unknown
 593  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 594  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 595  * ELSE
 596  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 597  * ENDIF
 598  */
 599
 600 /* macro to make the table lines short */
 601 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 602         {       PTYPE, \
 603                 1, \
 604                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 605                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 606                 I40E_RX_PTYPE_##OUTER_FRAG, \
 607                 I40E_RX_PTYPE_TUNNEL_##T, \
 608                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 609                 I40E_RX_PTYPE_##TEF, \
 610                 I40E_RX_PTYPE_INNER_PROT_##I, \
 611                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 612
 613 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 614                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 615
 616 /* shorter macros makes the table fit but are terse */
 617 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 618 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 619 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 620
 621 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 622 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 623         /* L2 Packet types */
 624         I40E_PTT_UNUSED_ENTRY(0),
 625         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 626         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 627         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 628         I40E_PTT_UNUSED_ENTRY(4),
 629         I40E_PTT_UNUSED_ENTRY(5),
 630         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 631         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 632         I40E_PTT_UNUSED_ENTRY(8),
 633         I40E_PTT_UNUSED_ENTRY(9),
 634         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 635         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 636         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 637         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 638         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 639         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 640         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 641         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 642         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646
 647         /* Non Tunneled IPv4 */
 648         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 651         I40E_PTT_UNUSED_ENTRY(25),
 652         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 653         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 654         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 655
 656         /* IPv4 --> IPv4 */
 657         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 658         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 659         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 660         I40E_PTT_UNUSED_ENTRY(32),
 661         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 662         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 663         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 664
 665         /* IPv4 --> IPv6 */
 666         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 667         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 668         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 669         I40E_PTT_UNUSED_ENTRY(39),
 670         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 671         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 672         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 673
 674         /* IPv4 --> GRE/NAT */
 675         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 676
 677         /* IPv4 --> GRE/NAT --> IPv4 */
 678         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 679         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 680         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(47),
 682         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 683         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 684         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> GRE/NAT --> IPv6 */
 687         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 688         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 689         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(54),
 691         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 692         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 693         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> GRE/NAT --> MAC */
 696         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 697
 698         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 699         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 700         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 701         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 702         I40E_PTT_UNUSED_ENTRY(62),
 703         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 704         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 705         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 706
 707         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 708         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 709         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 710         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(69),
 712         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 713         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 714         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 717         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 718
 719         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 720         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 721         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 722         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 723         I40E_PTT_UNUSED_ENTRY(77),
 724         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 725         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 726         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 727
 728         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 729         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 730         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 731         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(84),
 733         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 734         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 735         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 736
 737         /* Non Tunneled IPv6 */
 738         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 739         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 740         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(91),
 742         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 743         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 744         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 745
 746         /* IPv6 --> IPv4 */
 747         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 748         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 749         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 750         I40E_PTT_UNUSED_ENTRY(98),
 751         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 752         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 753         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 754
 755         /* IPv6 --> IPv6 */
 756         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 757         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 758         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 759         I40E_PTT_UNUSED_ENTRY(105),
 760         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 761         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 762         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 763
 764         /* IPv6 --> GRE/NAT */
 765         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 766
 767         /* IPv6 --> GRE/NAT -> IPv4 */
 768         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 769         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 770         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 771         I40E_PTT_UNUSED_ENTRY(113),
 772         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 773         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 774         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> GRE/NAT -> IPv6 */
 777         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 778         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 779         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(120),
 781         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 782         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 783         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> GRE/NAT -> MAC */
 786         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 787
 788         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 789         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 790         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 791         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 792         I40E_PTT_UNUSED_ENTRY(128),
 793         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 794         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 795         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 796
 797         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 798         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 799         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 800         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(135),
 802         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 803         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 804         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 807         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 808
 809         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 810         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 811         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 812         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 813         I40E_PTT_UNUSED_ENTRY(143),
 814         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 815         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 816         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 817
 818         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 819         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 820         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 821         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(150),
 823         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 824         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 825         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 826
 827         /* unused entries */
 828         I40E_PTT_UNUSED_ENTRY(154),
 829         I40E_PTT_UNUSED_ENTRY(155),
 830         I40E_PTT_UNUSED_ENTRY(156),
 831         I40E_PTT_UNUSED_ENTRY(157),
 832         I40E_PTT_UNUSED_ENTRY(158),
 833         I40E_PTT_UNUSED_ENTRY(159),
 834
 835         I40E_PTT_UNUSED_ENTRY(160),
 836         I40E_PTT_UNUSED_ENTRY(161),
 837         I40E_PTT_UNUSED_ENTRY(162),
 838         I40E_PTT_UNUSED_ENTRY(163),
 839         I40E_PTT_UNUSED_ENTRY(164),
 840         I40E_PTT_UNUSED_ENTRY(165),
 841         I40E_PTT_UNUSED_ENTRY(166),
 842         I40E_PTT_UNUSED_ENTRY(167),
 843         I40E_PTT_UNUSED_ENTRY(168),
 844         I40E_PTT_UNUSED_ENTRY(169),
 845
 846         I40E_PTT_UNUSED_ENTRY(170),
 847         I40E_PTT_UNUSED_ENTRY(171),
 848         I40E_PTT_UNUSED_ENTRY(172),
 849         I40E_PTT_UNUSED_ENTRY(173),
 850         I40E_PTT_UNUSED_ENTRY(174),
 851         I40E_PTT_UNUSED_ENTRY(175),
 852         I40E_PTT_UNUSED_ENTRY(176),
 853         I40E_PTT_UNUSED_ENTRY(177),
 854         I40E_PTT_UNUSED_ENTRY(178),
 855         I40E_PTT_UNUSED_ENTRY(179),
 856
 857         I40E_PTT_UNUSED_ENTRY(180),
 858         I40E_PTT_UNUSED_ENTRY(181),
 859         I40E_PTT_UNUSED_ENTRY(182),
 860         I40E_PTT_UNUSED_ENTRY(183),
 861         I40E_PTT_UNUSED_ENTRY(184),
 862         I40E_PTT_UNUSED_ENTRY(185),
 863         I40E_PTT_UNUSED_ENTRY(186),
 864         I40E_PTT_UNUSED_ENTRY(187),
 865         I40E_PTT_UNUSED_ENTRY(188),
 866         I40E_PTT_UNUSED_ENTRY(189),
 867
 868         I40E_PTT_UNUSED_ENTRY(190),
 869         I40E_PTT_UNUSED_ENTRY(191),
 870         I40E_PTT_UNUSED_ENTRY(192),
 871         I40E_PTT_UNUSED_ENTRY(193),
 872         I40E_PTT_UNUSED_ENTRY(194),
 873         I40E_PTT_UNUSED_ENTRY(195),
 874         I40E_PTT_UNUSED_ENTRY(196),
 875         I40E_PTT_UNUSED_ENTRY(197),
 876         I40E_PTT_UNUSED_ENTRY(198),
 877         I40E_PTT_UNUSED_ENTRY(199),
 878
 879         I40E_PTT_UNUSED_ENTRY(200),
 880         I40E_PTT_UNUSED_ENTRY(201),
 881         I40E_PTT_UNUSED_ENTRY(202),
 882         I40E_PTT_UNUSED_ENTRY(203),
 883         I40E_PTT_UNUSED_ENTRY(204),
 884         I40E_PTT_UNUSED_ENTRY(205),
 885         I40E_PTT_UNUSED_ENTRY(206),
 886         I40E_PTT_UNUSED_ENTRY(207),
 887         I40E_PTT_UNUSED_ENTRY(208),
 888         I40E_PTT_UNUSED_ENTRY(209),
 889
 890         I40E_PTT_UNUSED_ENTRY(210),
 891         I40E_PTT_UNUSED_ENTRY(211),
 892         I40E_PTT_UNUSED_ENTRY(212),
 893         I40E_PTT_UNUSED_ENTRY(213),
 894         I40E_PTT_UNUSED_ENTRY(214),
 895         I40E_PTT_UNUSED_ENTRY(215),
 896         I40E_PTT_UNUSED_ENTRY(216),
 897         I40E_PTT_UNUSED_ENTRY(217),
 898         I40E_PTT_UNUSED_ENTRY(218),
 899         I40E_PTT_UNUSED_ENTRY(219),
 900
 901         I40E_PTT_UNUSED_ENTRY(220),
 902         I40E_PTT_UNUSED_ENTRY(221),
 903         I40E_PTT_UNUSED_ENTRY(222),
 904         I40E_PTT_UNUSED_ENTRY(223),
 905         I40E_PTT_UNUSED_ENTRY(224),
 906         I40E_PTT_UNUSED_ENTRY(225),
 907         I40E_PTT_UNUSED_ENTRY(226),
 908         I40E_PTT_UNUSED_ENTRY(227),
 909         I40E_PTT_UNUSED_ENTRY(228),
 910         I40E_PTT_UNUSED_ENTRY(229),
 911
 912         I40E_PTT_UNUSED_ENTRY(230),
 913         I40E_PTT_UNUSED_ENTRY(231),
 914         I40E_PTT_UNUSED_ENTRY(232),
 915         I40E_PTT_UNUSED_ENTRY(233),
 916         I40E_PTT_UNUSED_ENTRY(234),
 917         I40E_PTT_UNUSED_ENTRY(235),
 918         I40E_PTT_UNUSED_ENTRY(236),
 919         I40E_PTT_UNUSED_ENTRY(237),
 920         I40E_PTT_UNUSED_ENTRY(238),
 921         I40E_PTT_UNUSED_ENTRY(239),
 922
 923         I40E_PTT_UNUSED_ENTRY(240),
 924         I40E_PTT_UNUSED_ENTRY(241),
 925         I40E_PTT_UNUSED_ENTRY(242),
 926         I40E_PTT_UNUSED_ENTRY(243),
 927         I40E_PTT_UNUSED_ENTRY(244),
 928         I40E_PTT_UNUSED_ENTRY(245),
 929         I40E_PTT_UNUSED_ENTRY(246),
 930         I40E_PTT_UNUSED_ENTRY(247),
 931         I40E_PTT_UNUSED_ENTRY(248),
 932         I40E_PTT_UNUSED_ENTRY(249),
 933
 934         I40E_PTT_UNUSED_ENTRY(250),
 935         I40E_PTT_UNUSED_ENTRY(251),
 936         I40E_PTT_UNUSED_ENTRY(252),
 937         I40E_PTT_UNUSED_ENTRY(253),
 938         I40E_PTT_UNUSED_ENTRY(254),
 939         I40E_PTT_UNUSED_ENTRY(255)
 940 };
 941
 942
 943 /**
 944  * i40e_validate_mac_addr - Validate unicast MAC address
 945  * @mac_addr: pointer to MAC address
 946  *
 947  * Tests a MAC address to ensure it is a valid Individual Address
 948  **/
 949 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 950 {
 951         enum i40e_status_code status = I40E_SUCCESS;
 952
 953         DEBUGFUNC("i40e_validate_mac_addr");
 954
 955         /* Broadcast addresses ARE multicast addresses
 956          * Make sure it is not a multicast address
 957          * Reject the zero address
 958          */
 959         if (I40E_IS_MULTICAST(mac_addr) ||
 960             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 961               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 962                 status = I40E_ERR_INVALID_MAC_ADDR;
 963
 964         return status;
 965 }
 966 #ifdef PF_DRIVER
 967
 968 /**
 969  * i40e_init_shared_code - Initialize the shared code
 970  * @hw: pointer to hardware structure
 971  *
 972  * This assigns the MAC type and PHY code and inits the NVM.
 973  * Does not touch the hardware. This function must be called prior to any
 974  * other function in the shared code. The i40e_hw structure should be
 975  * memset to 0 prior to calling this function.  The following fields in
 976  * hw structure should be filled in prior to calling this function:
 977  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 978  * subsystem_vendor_id, and revision_id
 979  **/
 980 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 981 {
 982         enum i40e_status_code status = I40E_SUCCESS;
 983         u32 port, ari, func_rid;
 984
 985         DEBUGFUNC("i40e_init_shared_code");
 986
 987         i40e_set_mac_type(hw);
 988
 989         switch (hw->mac.type) {
 990         case I40E_MAC_XL710:
 991         case I40E_MAC_X722:
 992                 break;
 993         default:
 994                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 995         }
 996
 997         hw->phy.get_link_info = true;
 998
 999         /* Determine port number and PF number*/
1000         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1001                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1002         hw->port = (u8)port;
1003         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1004                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1005         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1006         if (ari)
1007                 hw->pf_id = (u8)(func_rid & 0xff);
1008         else
1009                 hw->pf_id = (u8)(func_rid & 0x7);
1010
1011         if (hw->mac.type == I40E_MAC_X722)
1012                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1013                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1014
1015         status = i40e_init_nvm(hw);
1016         return status;
1017 }
1018
1019 /**
1020  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1021  * @hw: pointer to the hw struct
1022  * @flags: a return indicator of what addresses were added to the addr store
1023  * @addrs: the requestor's mac addr store
1024  * @cmd_details: pointer to command details structure or NULL
1025  **/
1026 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1027                                    u16 *flags,
1028                                    struct i40e_aqc_mac_address_read_data *addrs,
1029                                    struct i40e_asq_cmd_details *cmd_details)
1030 {
1031         struct i40e_aq_desc desc;
1032         struct i40e_aqc_mac_address_read *cmd_data =
1033                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1034         enum i40e_status_code status;
1035
1036         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1037         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1038
1039         status = i40e_asq_send_command(hw, &desc, addrs,
1040                                        sizeof(*addrs), cmd_details);
1041         *flags = LE16_TO_CPU(cmd_data->command_flags);
1042
1043         return status;
1044 }
1045
1046 /**
1047  * i40e_aq_mac_address_write - Change the MAC addresses
1048  * @hw: pointer to the hw struct
1049  * @flags: indicates which MAC to be written
1050  * @mac_addr: address to write
1051  * @cmd_details: pointer to command details structure or NULL
1052  **/
1053 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1054                                     u16 flags, u8 *mac_addr,
1055                                     struct i40e_asq_cmd_details *cmd_details)
1056 {
1057         struct i40e_aq_desc desc;
1058         struct i40e_aqc_mac_address_write *cmd_data =
1059                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1060         enum i40e_status_code status;
1061
1062         i40e_fill_default_direct_cmd_desc(&desc,
1063                                           i40e_aqc_opc_mac_address_write);
1064         cmd_data->command_flags = CPU_TO_LE16(flags);
1065         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1066         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1067                                         ((u32)mac_addr[3] << 16) |
1068                                         ((u32)mac_addr[4] << 8) |
1069                                         mac_addr[5]);
1070
1071         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1072
1073         return status;
1074 }
1075
1076 /**
1077  * i40e_get_mac_addr - get MAC address
1078  * @hw: pointer to the HW structure
1079  * @mac_addr: pointer to MAC address
1080  *
1081  * Reads the adapter's MAC address from register
1082  **/
1083 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1084 {
1085         struct i40e_aqc_mac_address_read_data addrs;
1086         enum i40e_status_code status;
1087         u16 flags = 0;
1088
1089         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1090
1091         if (flags & I40E_AQC_LAN_ADDR_VALID)
1092                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1093                         I40E_NONDMA_TO_NONDMA);
1094
1095         return status;
1096 }
1097
1098 /**
1099  * i40e_get_port_mac_addr - get Port MAC address
1100  * @hw: pointer to the HW structure
1101  * @mac_addr: pointer to Port MAC address
1102  *
1103  * Reads the adapter's Port MAC address
1104  **/
1105 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1106 {
1107         struct i40e_aqc_mac_address_read_data addrs;
1108         enum i40e_status_code status;
1109         u16 flags = 0;
1110
1111         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1112         if (status)
1113                 return status;
1114
1115         if (flags & I40E_AQC_PORT_ADDR_VALID)
1116                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1117                         I40E_NONDMA_TO_NONDMA);
1118         else
1119                 status = I40E_ERR_INVALID_MAC_ADDR;
1120
1121         return status;
1122 }
1123
1124 /**
1125  * i40e_pre_tx_queue_cfg - pre tx queue configure
1126  * @hw: pointer to the HW structure
1127  * @queue: target pf queue index
1128  * @enable: state change request
1129  *
1130  * Handles hw requirement to indicate intention to enable
1131  * or disable target queue.
1132  **/
1133 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1134 {
1135         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1136         u32 reg_block = 0;
1137         u32 reg_val;
1138
1139         if (abs_queue_idx >= 128) {
1140                 reg_block = abs_queue_idx / 128;
1141                 abs_queue_idx %= 128;
1142         }
1143
1144         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1145         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1146         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1147
1148         if (enable)
1149                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1150         else
1151                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1152
1153         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1154 }
1155
1156 /**
1157  * i40e_get_san_mac_addr - get SAN MAC address
1158  * @hw: pointer to the HW structure
1159  * @mac_addr: pointer to SAN MAC address
1160  *
1161  * Reads the adapter's SAN MAC address from NVM
1162  **/
1163 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1164                                             u8 *mac_addr)
1165 {
1166         struct i40e_aqc_mac_address_read_data addrs;
1167         enum i40e_status_code status;
1168         u16 flags = 0;
1169
1170         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1171         if (status)
1172                 return status;
1173
1174         if (flags & I40E_AQC_SAN_ADDR_VALID)
1175                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1176                         I40E_NONDMA_TO_NONDMA);
1177         else
1178                 status = I40E_ERR_INVALID_MAC_ADDR;
1179
1180         return status;
1181 }
1182
1183 /**
1184  *  i40e_read_pba_string - Reads part number string from EEPROM
1185  *  @hw: pointer to hardware structure
1186  *  @pba_num: stores the part number string from the EEPROM
1187  *  @pba_num_size: part number string buffer length
1188  *
1189  *  Reads the part number string from the EEPROM.
1190  **/
1191 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1192                                             u32 pba_num_size)
1193 {
1194         enum i40e_status_code status = I40E_SUCCESS;
1195         u16 pba_word = 0;
1196         u16 pba_size = 0;
1197         u16 pba_ptr = 0;
1198         u16 i = 0;
1199
1200         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1201         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1202                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1203                 return status;
1204         }
1205
1206         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1207         if (status != I40E_SUCCESS) {
1208                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1209                 return status;
1210         }
1211
1212         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1213         if (status != I40E_SUCCESS) {
1214                 DEBUGOUT("Failed to read PBA Block size.\n");
1215                 return status;
1216         }
1217
1218         /* Subtract one to get PBA word count (PBA Size word is included in
1219          * total size)
1220          */
1221         pba_size--;
1222         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1223                 DEBUGOUT("Buffer to small for PBA data.\n");
1224                 return I40E_ERR_PARAM;
1225         }
1226
1227         for (i = 0; i < pba_size; i++) {
1228                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1229                 if (status != I40E_SUCCESS) {
1230                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1231                         return status;
1232                 }
1233
1234                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1235                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1236         }
1237         pba_num[(pba_size * 2)] = '\0';
1238
1239         return status;
1240 }
1241
1242 /**
1243  * i40e_get_media_type - Gets media type
1244  * @hw: pointer to the hardware structure
1245  **/
1246 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1247 {
1248         enum i40e_media_type media;
1249
1250         switch (hw->phy.link_info.phy_type) {
1251         case I40E_PHY_TYPE_10GBASE_SR:
1252         case I40E_PHY_TYPE_10GBASE_LR:
1253         case I40E_PHY_TYPE_1000BASE_SX:
1254         case I40E_PHY_TYPE_1000BASE_LX:
1255         case I40E_PHY_TYPE_40GBASE_SR4:
1256         case I40E_PHY_TYPE_40GBASE_LR4:
1257         case I40E_PHY_TYPE_25GBASE_LR:
1258         case I40E_PHY_TYPE_25GBASE_SR:
1259                 media = I40E_MEDIA_TYPE_FIBER;
1260                 break;
1261         case I40E_PHY_TYPE_100BASE_TX:
1262         case I40E_PHY_TYPE_1000BASE_T:
1263         case I40E_PHY_TYPE_10GBASE_T:
1264                 media = I40E_MEDIA_TYPE_BASET;
1265                 break;
1266         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1267         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1268         case I40E_PHY_TYPE_10GBASE_CR1:
1269         case I40E_PHY_TYPE_40GBASE_CR4:
1270         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1271         case I40E_PHY_TYPE_40GBASE_AOC:
1272         case I40E_PHY_TYPE_10GBASE_AOC:
1273         case I40E_PHY_TYPE_25GBASE_CR:
1274         case I40E_PHY_TYPE_25GBASE_AOC:
1275         case I40E_PHY_TYPE_25GBASE_ACC:
1276                 media = I40E_MEDIA_TYPE_DA;
1277                 break;
1278         case I40E_PHY_TYPE_1000BASE_KX:
1279         case I40E_PHY_TYPE_10GBASE_KX4:
1280         case I40E_PHY_TYPE_10GBASE_KR:
1281         case I40E_PHY_TYPE_40GBASE_KR4:
1282         case I40E_PHY_TYPE_20GBASE_KR2:
1283         case I40E_PHY_TYPE_25GBASE_KR:
1284                 media = I40E_MEDIA_TYPE_BACKPLANE;
1285                 break;
1286         case I40E_PHY_TYPE_SGMII:
1287         case I40E_PHY_TYPE_XAUI:
1288         case I40E_PHY_TYPE_XFI:
1289         case I40E_PHY_TYPE_XLAUI:
1290         case I40E_PHY_TYPE_XLPPI:
1291         default:
1292                 media = I40E_MEDIA_TYPE_UNKNOWN;
1293                 break;
1294         }
1295
1296         return media;
1297 }
1298
1299 /**
1300  * i40e_poll_globr - Poll for Global Reset completion
1301  * @hw: pointer to the hardware structure
1302  * @retry_limit: how many times to retry before failure
1303  **/
1304 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1305                                              u32 retry_limit)
1306 {
1307         u32 cnt, reg = 0;
1308
1309         for (cnt = 0; cnt < retry_limit; cnt++) {
1310                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1311                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1312                         return I40E_SUCCESS;
1313                 i40e_msec_delay(100);
1314         }
1315
1316         DEBUGOUT("Global reset failed.\n");
1317         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1318
1319         return I40E_ERR_RESET_FAILED;
1320 }
1321
1322 #define I40E_PF_RESET_WAIT_COUNT        200
1323 /**
1324  * i40e_pf_reset - Reset the PF
1325  * @hw: pointer to the hardware structure
1326  *
1327  * Assuming someone else has triggered a global reset,
1328  * assure the global reset is complete and then reset the PF
1329  **/
1330 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1331 {
1332         u32 cnt = 0;
1333         u32 cnt1 = 0;
1334         u32 reg = 0;
1335         u32 grst_del;
1336
1337         /* Poll for Global Reset steady state in case of recent GRST.
1338          * The grst delay value is in 100ms units, and we'll wait a
1339          * couple counts longer to be sure we don't just miss the end.
1340          */
1341         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1342                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1343                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1344
1345         grst_del = min(grst_del * 20, 160U);
1346
1347         for (cnt = 0; cnt < grst_del; cnt++) {
1348                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1349                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1350                         break;
1351                 i40e_msec_delay(100);
1352         }
1353         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1354                 DEBUGOUT("Global reset polling failed to complete.\n");
1355                 return I40E_ERR_RESET_FAILED;
1356         }
1357
1358         /* Now Wait for the FW to be ready */
1359         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1360                 reg = rd32(hw, I40E_GLNVM_ULD);
1361                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1362                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1363                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1364                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1365                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1366                         break;
1367                 }
1368                 i40e_msec_delay(10);
1369         }
1370         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1372                 DEBUGOUT("wait for FW Reset complete timedout\n");
1373                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1374                 return I40E_ERR_RESET_FAILED;
1375         }
1376
1377         /* If there was a Global Reset in progress when we got here,
1378          * we don't need to do the PF Reset
1379          */
1380         if (!cnt) {
1381                 u32 reg2 = 0;
1382
1383                 reg = rd32(hw, I40E_PFGEN_CTRL);
1384                 wr32(hw, I40E_PFGEN_CTRL,
1385                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1386                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1387                         reg = rd32(hw, I40E_PFGEN_CTRL);
1388                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1389                                 break;
1390                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1391                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1392                                 break;
1393                         i40e_msec_delay(1);
1394                 }
1395                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1396                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1397                                 return I40E_ERR_RESET_FAILED;
1398                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1399                         DEBUGOUT("PF reset polling failed to complete.\n");
1400                         return I40E_ERR_RESET_FAILED;
1401                 }
1402         }
1403
1404         i40e_clear_pxe_mode(hw);
1405
1406
1407         return I40E_SUCCESS;
1408 }
1409
1410 /**
1411  * i40e_clear_hw - clear out any left over hw state
1412  * @hw: pointer to the hw struct
1413  *
1414  * Clear queues and interrupts, typically called at init time,
1415  * but after the capabilities have been found so we know how many
1416  * queues and msix vectors have been allocated.
1417  **/
1418 void i40e_clear_hw(struct i40e_hw *hw)
1419 {
1420         u32 num_queues, base_queue;
1421         u32 num_pf_int;
1422         u32 num_vf_int;
1423         u32 num_vfs;
1424         u32 i, j;
1425         u32 val;
1426         u32 eol = 0x7ff;
1427
1428         /* get number of interrupts, queues, and vfs */
1429         val = rd32(hw, I40E_GLPCI_CNF2);
1430         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1431                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1432         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1433                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1434
1435         val = rd32(hw, I40E_PFLAN_QALLOC);
1436         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1437                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1438         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1439                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1440         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1441                 num_queues = (j - base_queue) + 1;
1442         else
1443                 num_queues = 0;
1444
1445         val = rd32(hw, I40E_PF_VT_PFALLOC);
1446         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1447                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1448         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1449                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1450         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1451                 num_vfs = (j - i) + 1;
1452         else
1453                 num_vfs = 0;
1454
1455         /* stop all the interrupts */
1456         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1457         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1458         for (i = 0; i < num_pf_int - 2; i++)
1459                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1460
1461         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1462         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1463         wr32(hw, I40E_PFINT_LNKLST0, val);
1464         for (i = 0; i < num_pf_int - 2; i++)
1465                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1466         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1467         for (i = 0; i < num_vfs; i++)
1468                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1469         for (i = 0; i < num_vf_int - 2; i++)
1470                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1471
1472         /* warn the HW of the coming Tx disables */
1473         for (i = 0; i < num_queues; i++) {
1474                 u32 abs_queue_idx = base_queue + i;
1475                 u32 reg_block = 0;
1476
1477                 if (abs_queue_idx >= 128) {
1478                         reg_block = abs_queue_idx / 128;
1479                         abs_queue_idx %= 128;
1480                 }
1481
1482                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1483                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1484                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1485                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1486
1487                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1488         }
1489         i40e_usec_delay(400);
1490
1491         /* stop all the queues */
1492         for (i = 0; i < num_queues; i++) {
1493                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1494                 wr32(hw, I40E_QTX_ENA(i), 0);
1495                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1496                 wr32(hw, I40E_QRX_ENA(i), 0);
1497         }
1498
1499         /* short wait for all queue disables to settle */
1500         i40e_usec_delay(50);
1501 }
1502
1503 /**
1504  * i40e_clear_pxe_mode - clear pxe operations mode
1505  * @hw: pointer to the hw struct
1506  *
1507  * Make sure all PXE mode settings are cleared, including things
1508  * like descriptor fetch/write-back mode.
1509  **/
1510 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1511 {
1512         if (i40e_check_asq_alive(hw))
1513                 i40e_aq_clear_pxe_mode(hw, NULL);
1514 }
1515
1516 /**
1517  * i40e_led_is_mine - helper to find matching led
1518  * @hw: pointer to the hw struct
1519  * @idx: index into GPIO registers
1520  *
1521  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1522  */
1523 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1524 {
1525         u32 gpio_val = 0;
1526         u32 port;
1527
1528         if (!hw->func_caps.led[idx])
1529                 return 0;
1530
1531         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1532         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1533                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1534
1535         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1536          * if it is not our port then ignore
1537          */
1538         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1539             (port != hw->port))
1540                 return 0;
1541
1542         return gpio_val;
1543 }
1544
1545 #define I40E_COMBINED_ACTIVITY 0xA
1546 #define I40E_FILTER_ACTIVITY 0xE
1547 #define I40E_LINK_ACTIVITY 0xC
1548 #define I40E_MAC_ACTIVITY 0xD
1549 #define I40E_LED0 22
1550
1551 /**
1552  * i40e_led_get - return current on/off mode
1553  * @hw: pointer to the hw struct
1554  *
1555  * The value returned is the 'mode' field as defined in the
1556  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1557  * values are variations of possible behaviors relating to
1558  * blink, link, and wire.
1559  **/
1560 u32 i40e_led_get(struct i40e_hw *hw)
1561 {
1562         u32 current_mode = 0;
1563         u32 mode = 0;
1564         int i;
1565
1566         /* as per the documentation GPIO 22-29 are the LED
1567          * GPIO pins named LED0..LED7
1568          */
1569         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1570                 u32 gpio_val = i40e_led_is_mine(hw, i);
1571
1572                 if (!gpio_val)
1573                         continue;
1574
1575                 /* ignore gpio LED src mode entries related to the activity
1576                  *  LEDs
1577                  */
1578                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1579                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1580                 switch (current_mode) {
1581                 case I40E_COMBINED_ACTIVITY:
1582                 case I40E_FILTER_ACTIVITY:
1583                 case I40E_MAC_ACTIVITY:
1584                 case I40E_LINK_ACTIVITY:
1585                         continue;
1586                 default:
1587                         break;
1588                 }
1589
1590                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1592                 break;
1593         }
1594
1595         return mode;
1596 }
1597
1598 /**
1599  * i40e_led_set - set new on/off mode
1600  * @hw: pointer to the hw struct
1601  * @mode: 0=off, 0xf=on (else see manual for mode details)
1602  * @blink: true if the LED should blink when on, false if steady
1603  *
1604  * if this function is used to turn on the blink it should
1605  * be used to disable the blink when restoring the original state.
1606  **/
1607 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1608 {
1609         u32 current_mode = 0;
1610         int i;
1611
1612         if (mode & 0xfffffff0)
1613                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1614
1615         /* as per the documentation GPIO 22-29 are the LED
1616          * GPIO pins named LED0..LED7
1617          */
1618         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1619                 u32 gpio_val = i40e_led_is_mine(hw, i);
1620
1621                 if (!gpio_val)
1622                         continue;
1623
1624                 /* ignore gpio LED src mode entries related to the activity
1625                  * LEDs
1626                  */
1627                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1628                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1629                 switch (current_mode) {
1630                 case I40E_COMBINED_ACTIVITY:
1631                 case I40E_FILTER_ACTIVITY:
1632                 case I40E_MAC_ACTIVITY:
1633                 case I40E_LINK_ACTIVITY:
1634                         continue;
1635                 default:
1636                         break;
1637                 }
1638
1639                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1640                 /* this & is a bit of paranoia, but serves as a range check */
1641                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1642                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1643
1644                 if (blink)
1645                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1646                 else
1647                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1648
1649                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1650                 break;
1651         }
1652 }
1653
1654 /* Admin command wrappers */
1655
1656 /**
1657  * i40e_aq_get_phy_capabilities
1658  * @hw: pointer to the hw struct
1659  * @abilities: structure for PHY capabilities to be filled
1660  * @qualified_modules: report Qualified Modules
1661  * @report_init: report init capabilities (active are default)
1662  * @cmd_details: pointer to command details structure or NULL
1663  *
1664  * Returns the various PHY abilities supported on the Port.
1665  **/
1666 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1667                         bool qualified_modules, bool report_init,
1668                         struct i40e_aq_get_phy_abilities_resp *abilities,
1669                         struct i40e_asq_cmd_details *cmd_details)
1670 {
1671         struct i40e_aq_desc desc;
1672         enum i40e_status_code status;
1673         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1674         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1675
1676         if (!abilities)
1677                 return I40E_ERR_PARAM;
1678
1679         do {
1680                 i40e_fill_default_direct_cmd_desc(&desc,
1681                                                i40e_aqc_opc_get_phy_abilities);
1682
1683                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1684                 if (abilities_size > I40E_AQ_LARGE_BUF)
1685                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1686
1687                 if (qualified_modules)
1688                         desc.params.external.param0 |=
1689                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1690
1691                 if (report_init)
1692                         desc.params.external.param0 |=
1693                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1694
1695                 status = i40e_asq_send_command(hw, &desc, abilities,
1696                                                abilities_size, cmd_details);
1697
1698                 if (status != I40E_SUCCESS)
1699                         break;
1700
1701                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1702                         status = I40E_ERR_UNKNOWN_PHY;
1703                         break;
1704                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1705                         i40e_msec_delay(1);
1706                         total_delay++;
1707                         status = I40E_ERR_TIMEOUT;
1708                 }
1709         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1710                  (total_delay < max_delay));
1711
1712         if (status != I40E_SUCCESS)
1713                 return status;
1714
1715         if (report_init) {
1716                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1717                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1718                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1719                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1720                 } else {
1721                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1722                         hw->phy.phy_types |=
1723                                         ((u64)abilities->phy_type_ext << 32);
1724                 }
1725         }
1726
1727         return status;
1728 }
1729
1730 /**
1731  * i40e_aq_set_phy_config
1732  * @hw: pointer to the hw struct
1733  * @config: structure with PHY configuration to be set
1734  * @cmd_details: pointer to command details structure or NULL
1735  *
1736  * Set the various PHY configuration parameters
1737  * supported on the Port.One or more of the Set PHY config parameters may be
1738  * ignored in an MFP mode as the PF may not have the privilege to set some
1739  * of the PHY Config parameters. This status will be indicated by the
1740  * command response.
1741  **/
1742 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1743                                 struct i40e_aq_set_phy_config *config,
1744                                 struct i40e_asq_cmd_details *cmd_details)
1745 {
1746         struct i40e_aq_desc desc;
1747         struct i40e_aq_set_phy_config *cmd =
1748                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1749         enum i40e_status_code status;
1750
1751         if (!config)
1752                 return I40E_ERR_PARAM;
1753
1754         i40e_fill_default_direct_cmd_desc(&desc,
1755                                           i40e_aqc_opc_set_phy_config);
1756
1757         *cmd = *config;
1758
1759         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1760
1761         return status;
1762 }
1763
1764 /**
1765  * i40e_set_fc
1766  * @hw: pointer to the hw struct
1767  * @aq_failures: buffer to return AdminQ failure information
1768  * @atomic_restart: whether to enable atomic link restart
1769  *
1770  * Set the requested flow control mode using set_phy_config.
1771  **/
1772 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1773                                   bool atomic_restart)
1774 {
1775         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1776         struct i40e_aq_get_phy_abilities_resp abilities;
1777         struct i40e_aq_set_phy_config config;
1778         enum i40e_status_code status;
1779         u8 pause_mask = 0x0;
1780
1781         *aq_failures = 0x0;
1782
1783         switch (fc_mode) {
1784         case I40E_FC_FULL:
1785                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1786                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1787                 break;
1788         case I40E_FC_RX_PAUSE:
1789                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1790                 break;
1791         case I40E_FC_TX_PAUSE:
1792                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1793                 break;
1794         default:
1795                 break;
1796         }
1797
1798         /* Get the current phy config */
1799         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1800                                               NULL);
1801         if (status) {
1802                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1803                 return status;
1804         }
1805
1806         memset(&config, 0, sizeof(config));
1807         /* clear the old pause settings */
1808         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1809                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1810         /* set the new abilities */
1811         config.abilities |= pause_mask;
1812         /* If the abilities have changed, then set the new config */
1813         if (config.abilities != abilities.abilities) {
1814                 /* Auto restart link so settings take effect */
1815                 if (atomic_restart)
1816                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1817                 /* Copy over all the old settings */
1818                 config.phy_type = abilities.phy_type;
1819                 config.phy_type_ext = abilities.phy_type_ext;
1820                 config.link_speed = abilities.link_speed;
1821                 config.eee_capability = abilities.eee_capability;
1822                 config.eeer = abilities.eeer_val;
1823                 config.low_power_ctrl = abilities.d3_lpan;
1824                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1825                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1826                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1827
1828                 if (status)
1829                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1830         }
1831         /* Update the link info */
1832         status = i40e_update_link_info(hw);
1833         if (status) {
1834                 /* Wait a little bit (on 40G cards it sometimes takes a really
1835                  * long time for link to come back from the atomic reset)
1836                  * and try once more
1837                  */
1838                 i40e_msec_delay(1000);
1839                 status = i40e_update_link_info(hw);
1840         }
1841         if (status)
1842                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1843
1844         return status;
1845 }
1846
1847 /**
1848  * i40e_aq_set_mac_config
1849  * @hw: pointer to the hw struct
1850  * @max_frame_size: Maximum Frame Size to be supported by the port
1851  * @crc_en: Tell HW to append a CRC to outgoing frames
1852  * @pacing: Pacing configurations
1853  * @cmd_details: pointer to command details structure or NULL
1854  *
1855  * Configure MAC settings for frame size, jumbo frame support and the
1856  * addition of a CRC by the hardware.
1857  **/
1858 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1859                                 u16 max_frame_size,
1860                                 bool crc_en, u16 pacing,
1861                                 struct i40e_asq_cmd_details *cmd_details)
1862 {
1863         struct i40e_aq_desc desc;
1864         struct i40e_aq_set_mac_config *cmd =
1865                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1866         enum i40e_status_code status;
1867
1868         if (max_frame_size == 0)
1869                 return I40E_ERR_PARAM;
1870
1871         i40e_fill_default_direct_cmd_desc(&desc,
1872                                           i40e_aqc_opc_set_mac_config);
1873
1874         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1875         cmd->params = ((u8)pacing & 0x0F) << 3;
1876         if (crc_en)
1877                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1878
1879         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1880
1881         return status;
1882 }
1883
1884 /**
1885  * i40e_aq_clear_pxe_mode
1886  * @hw: pointer to the hw struct
1887  * @cmd_details: pointer to command details structure or NULL
1888  *
1889  * Tell the firmware that the driver is taking over from PXE
1890  **/
1891 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1892                         struct i40e_asq_cmd_details *cmd_details)
1893 {
1894         enum i40e_status_code status;
1895         struct i40e_aq_desc desc;
1896         struct i40e_aqc_clear_pxe *cmd =
1897                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1898
1899         i40e_fill_default_direct_cmd_desc(&desc,
1900                                           i40e_aqc_opc_clear_pxe_mode);
1901
1902         cmd->rx_cnt = 0x2;
1903
1904         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1905
1906         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1907
1908         return status;
1909 }
1910
1911 /**
1912  * i40e_aq_set_link_restart_an
1913  * @hw: pointer to the hw struct
1914  * @enable_link: if true: enable link, if false: disable link
1915  * @cmd_details: pointer to command details structure or NULL
1916  *
1917  * Sets up the link and restarts the Auto-Negotiation over the link.
1918  **/
1919 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1920                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1921 {
1922         struct i40e_aq_desc desc;
1923         struct i40e_aqc_set_link_restart_an *cmd =
1924                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1925         enum i40e_status_code status;
1926
1927         i40e_fill_default_direct_cmd_desc(&desc,
1928                                           i40e_aqc_opc_set_link_restart_an);
1929
1930         cmd->command = I40E_AQ_PHY_RESTART_AN;
1931         if (enable_link)
1932                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1933         else
1934                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1935
1936         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1937
1938         return status;
1939 }
1940
1941 /**
1942  * i40e_aq_get_link_info
1943  * @hw: pointer to the hw struct
1944  * @enable_lse: enable/disable LinkStatusEvent reporting
1945  * @link: pointer to link status structure - optional
1946  * @cmd_details: pointer to command details structure or NULL
1947  *
1948  * Returns the link status of the adapter.
1949  **/
1950 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1951                                 bool enable_lse, struct i40e_link_status *link,
1952                                 struct i40e_asq_cmd_details *cmd_details)
1953 {
1954         struct i40e_aq_desc desc;
1955         struct i40e_aqc_get_link_status *resp =
1956                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1957         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1958         enum i40e_status_code status;
1959         bool tx_pause, rx_pause;
1960         u16 command_flags;
1961
1962         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1963
1964         if (enable_lse)
1965                 command_flags = I40E_AQ_LSE_ENABLE;
1966         else
1967                 command_flags = I40E_AQ_LSE_DISABLE;
1968         resp->command_flags = CPU_TO_LE16(command_flags);
1969
1970         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1971
1972         if (status != I40E_SUCCESS)
1973                 goto aq_get_link_info_exit;
1974
1975         /* save off old link status information */
1976         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1977                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1978
1979         /* update link status */
1980         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1981         hw->phy.media_type = i40e_get_media_type(hw);
1982         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1983         hw_link_info->link_info = resp->link_info;
1984         hw_link_info->an_info = resp->an_info;
1985         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1986                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1987         hw_link_info->ext_info = resp->ext_info;
1988         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1989         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1990         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1991
1992         /* update fc info */
1993         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1994         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1995         if (tx_pause & rx_pause)
1996                 hw->fc.current_mode = I40E_FC_FULL;
1997         else if (tx_pause)
1998                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1999         else if (rx_pause)
2000                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2001         else
2002                 hw->fc.current_mode = I40E_FC_NONE;
2003
2004         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2005                 hw_link_info->crc_enable = true;
2006         else
2007                 hw_link_info->crc_enable = false;
2008
2009         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2010                 hw_link_info->lse_enable = true;
2011         else
2012                 hw_link_info->lse_enable = false;
2013
2014         if ((hw->mac.type == I40E_MAC_XL710) &&
2015             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2016              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2017                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2018
2019         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2020             hw->aq.api_min_ver >= 7) {
2021                 __le32 tmp;
2022
2023                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2024                             I40E_NONDMA_TO_NONDMA);
2025                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2026                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2027         }
2028
2029         /* save link status information */
2030         if (link)
2031                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2032                             I40E_NONDMA_TO_NONDMA);
2033
2034         /* flag cleared so helper functions don't call AQ again */
2035         hw->phy.get_link_info = false;
2036
2037 aq_get_link_info_exit:
2038         return status;
2039 }
2040
2041 /**
2042  * i40e_aq_set_phy_int_mask
2043  * @hw: pointer to the hw struct
2044  * @mask: interrupt mask to be set
2045  * @cmd_details: pointer to command details structure or NULL
2046  *
2047  * Set link interrupt mask.
2048  **/
2049 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2050                                 u16 mask,
2051                                 struct i40e_asq_cmd_details *cmd_details)
2052 {
2053         struct i40e_aq_desc desc;
2054         struct i40e_aqc_set_phy_int_mask *cmd =
2055                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2056         enum i40e_status_code status;
2057
2058         i40e_fill_default_direct_cmd_desc(&desc,
2059                                           i40e_aqc_opc_set_phy_int_mask);
2060
2061         cmd->event_mask = CPU_TO_LE16(mask);
2062
2063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2064
2065         return status;
2066 }
2067
2068 /**
2069  * i40e_aq_get_local_advt_reg
2070  * @hw: pointer to the hw struct
2071  * @advt_reg: local AN advertisement register value
2072  * @cmd_details: pointer to command details structure or NULL
2073  *
2074  * Get the Local AN advertisement register value.
2075  **/
2076 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2077                                 u64 *advt_reg,
2078                                 struct i40e_asq_cmd_details *cmd_details)
2079 {
2080         struct i40e_aq_desc desc;
2081         struct i40e_aqc_an_advt_reg *resp =
2082                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2083         enum i40e_status_code status;
2084
2085         i40e_fill_default_direct_cmd_desc(&desc,
2086                                           i40e_aqc_opc_get_local_advt_reg);
2087
2088         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2089
2090         if (status != I40E_SUCCESS)
2091                 goto aq_get_local_advt_reg_exit;
2092
2093         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2094         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2095
2096 aq_get_local_advt_reg_exit:
2097         return status;
2098 }
2099
2100 /**
2101  * i40e_aq_set_local_advt_reg
2102  * @hw: pointer to the hw struct
2103  * @advt_reg: local AN advertisement register value
2104  * @cmd_details: pointer to command details structure or NULL
2105  *
2106  * Get the Local AN advertisement register value.
2107  **/
2108 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2109                                 u64 advt_reg,
2110                                 struct i40e_asq_cmd_details *cmd_details)
2111 {
2112         struct i40e_aq_desc desc;
2113         struct i40e_aqc_an_advt_reg *cmd =
2114                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2115         enum i40e_status_code status;
2116
2117         i40e_fill_default_direct_cmd_desc(&desc,
2118                                           i40e_aqc_opc_get_local_advt_reg);
2119
2120         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2121         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2122
2123         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2124
2125         return status;
2126 }
2127
2128 /**
2129  * i40e_aq_get_partner_advt
2130  * @hw: pointer to the hw struct
2131  * @advt_reg: AN partner advertisement register value
2132  * @cmd_details: pointer to command details structure or NULL
2133  *
2134  * Get the link partner AN advertisement register value.
2135  **/
2136 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2137                                 u64 *advt_reg,
2138                                 struct i40e_asq_cmd_details *cmd_details)
2139 {
2140         struct i40e_aq_desc desc;
2141         struct i40e_aqc_an_advt_reg *resp =
2142                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2143         enum i40e_status_code status;
2144
2145         i40e_fill_default_direct_cmd_desc(&desc,
2146                                           i40e_aqc_opc_get_partner_advt);
2147
2148         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2149
2150         if (status != I40E_SUCCESS)
2151                 goto aq_get_partner_advt_exit;
2152
2153         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2154         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2155
2156 aq_get_partner_advt_exit:
2157         return status;
2158 }
2159
2160 /**
2161  * i40e_aq_set_lb_modes
2162  * @hw: pointer to the hw struct
2163  * @lb_modes: loopback mode to be set
2164  * @cmd_details: pointer to command details structure or NULL
2165  *
2166  * Sets loopback modes.
2167  **/
2168 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2169                                 u16 lb_modes,
2170                                 struct i40e_asq_cmd_details *cmd_details)
2171 {
2172         struct i40e_aq_desc desc;
2173         struct i40e_aqc_set_lb_mode *cmd =
2174                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2175         enum i40e_status_code status;
2176
2177         i40e_fill_default_direct_cmd_desc(&desc,
2178                                           i40e_aqc_opc_set_lb_modes);
2179
2180         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2181
2182         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2183
2184         return status;
2185 }
2186
2187 /**
2188  * i40e_aq_set_phy_debug
2189  * @hw: pointer to the hw struct
2190  * @cmd_flags: debug command flags
2191  * @cmd_details: pointer to command details structure or NULL
2192  *
2193  * Reset the external PHY.
2194  **/
2195 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2196                                 struct i40e_asq_cmd_details *cmd_details)
2197 {
2198         struct i40e_aq_desc desc;
2199         struct i40e_aqc_set_phy_debug *cmd =
2200                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2201         enum i40e_status_code status;
2202
2203         i40e_fill_default_direct_cmd_desc(&desc,
2204                                           i40e_aqc_opc_set_phy_debug);
2205
2206         cmd->command_flags = cmd_flags;
2207
2208         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2209
2210         return status;
2211 }
2212
2213 /**
2214  * i40e_aq_add_vsi
2215  * @hw: pointer to the hw struct
2216  * @vsi_ctx: pointer to a vsi context struct
2217  * @cmd_details: pointer to command details structure or NULL
2218  *
2219  * Add a VSI context to the hardware.
2220 **/
2221 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2222                                 struct i40e_vsi_context *vsi_ctx,
2223                                 struct i40e_asq_cmd_details *cmd_details)
2224 {
2225         struct i40e_aq_desc desc;
2226         struct i40e_aqc_add_get_update_vsi *cmd =
2227                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2228         struct i40e_aqc_add_get_update_vsi_completion *resp =
2229                 (struct i40e_aqc_add_get_update_vsi_completion *)
2230                 &desc.params.raw;
2231         enum i40e_status_code status;
2232
2233         i40e_fill_default_direct_cmd_desc(&desc,
2234                                           i40e_aqc_opc_add_vsi);
2235
2236         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2237         cmd->connection_type = vsi_ctx->connection_type;
2238         cmd->vf_id = vsi_ctx->vf_num;
2239         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2240
2241         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2242
2243         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2244                                     sizeof(vsi_ctx->info), cmd_details);
2245
2246         if (status != I40E_SUCCESS)
2247                 goto aq_add_vsi_exit;
2248
2249         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2250         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2251         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2252         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2253
2254 aq_add_vsi_exit:
2255         return status;
2256 }
2257
2258 /**
2259  * i40e_aq_set_default_vsi
2260  * @hw: pointer to the hw struct
2261  * @seid: vsi number
2262  * @cmd_details: pointer to command details structure or NULL
2263  **/
2264 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2265                                 u16 seid,
2266                                 struct i40e_asq_cmd_details *cmd_details)
2267 {
2268         struct i40e_aq_desc desc;
2269         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2270                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2271                 &desc.params.raw;
2272         enum i40e_status_code status;
2273
2274         i40e_fill_default_direct_cmd_desc(&desc,
2275                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2276
2277         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2278         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2279         cmd->seid = CPU_TO_LE16(seid);
2280
2281         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2282
2283         return status;
2284 }
2285
2286 /**
2287  * i40e_aq_clear_default_vsi
2288  * @hw: pointer to the hw struct
2289  * @seid: vsi number
2290  * @cmd_details: pointer to command details structure or NULL
2291  **/
2292 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2293                                 u16 seid,
2294                                 struct i40e_asq_cmd_details *cmd_details)
2295 {
2296         struct i40e_aq_desc desc;
2297         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2298                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2299                 &desc.params.raw;
2300         enum i40e_status_code status;
2301
2302         i40e_fill_default_direct_cmd_desc(&desc,
2303                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2304
2305         cmd->promiscuous_flags = CPU_TO_LE16(0);
2306         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2307         cmd->seid = CPU_TO_LE16(seid);
2308
2309         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2310
2311         return status;
2312 }
2313
2314 /**
2315  * i40e_aq_set_vsi_unicast_promiscuous
2316  * @hw: pointer to the hw struct
2317  * @seid: vsi number
2318  * @set: set unicast promiscuous enable/disable
2319  * @cmd_details: pointer to command details structure or NULL
2320  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2321  **/
2322 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2323                                 u16 seid, bool set,
2324                                 struct i40e_asq_cmd_details *cmd_details,
2325                                 bool rx_only_promisc)
2326 {
2327         struct i40e_aq_desc desc;
2328         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2329                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2330         enum i40e_status_code status;
2331         u16 flags = 0;
2332
2333         i40e_fill_default_direct_cmd_desc(&desc,
2334                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2335
2336         if (set) {
2337                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2338                 if (rx_only_promisc &&
2339                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2340                      (hw->aq.api_maj_ver > 1)))
2341                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2342         }
2343
2344         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2345
2346         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2347         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2348              (hw->aq.api_maj_ver > 1))
2349                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2350
2351         cmd->seid = CPU_TO_LE16(seid);
2352         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2353
2354         return status;
2355 }
2356
2357 /**
2358  * i40e_aq_set_vsi_multicast_promiscuous
2359  * @hw: pointer to the hw struct
2360  * @seid: vsi number
2361  * @set: set multicast promiscuous enable/disable
2362  * @cmd_details: pointer to command details structure or NULL
2363  **/
2364 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2365                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2366 {
2367         struct i40e_aq_desc desc;
2368         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2369                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2370         enum i40e_status_code status;
2371         u16 flags = 0;
2372
2373         i40e_fill_default_direct_cmd_desc(&desc,
2374                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2375
2376         if (set)
2377                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2378
2379         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2380
2381         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2382
2383         cmd->seid = CPU_TO_LE16(seid);
2384         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2385
2386         return status;
2387 }
2388
2389 /**
2390 * i40e_aq_set_vsi_full_promiscuous
2391 * @hw: pointer to the hw struct
2392 * @seid: VSI number
2393 * @set: set promiscuous enable/disable
2394 * @cmd_details: pointer to command details structure or NULL
2395 **/
2396 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2397                                 u16 seid, bool set,
2398                                 struct i40e_asq_cmd_details *cmd_details)
2399 {
2400         struct i40e_aq_desc desc;
2401         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2402                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2403         enum i40e_status_code status;
2404         u16 flags = 0;
2405
2406         i40e_fill_default_direct_cmd_desc(&desc,
2407                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2408
2409         if (set)
2410                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2411                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2412                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2413
2414         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2415
2416         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2417                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2418                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2419
2420         cmd->seid = CPU_TO_LE16(seid);
2421         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2422
2423         return status;
2424 }
2425
2426 /**
2427  * i40e_aq_set_vsi_mc_promisc_on_vlan
2428  * @hw: pointer to the hw struct
2429  * @seid: vsi number
2430  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2431  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2432  * @cmd_details: pointer to command details structure or NULL
2433  **/
2434 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2435                                 u16 seid, bool enable, u16 vid,
2436                                 struct i40e_asq_cmd_details *cmd_details)
2437 {
2438         struct i40e_aq_desc desc;
2439         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2440                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2441         enum i40e_status_code status;
2442         u16 flags = 0;
2443
2444         i40e_fill_default_direct_cmd_desc(&desc,
2445                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2446
2447         if (enable)
2448                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2449
2450         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2451         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2452         cmd->seid = CPU_TO_LE16(seid);
2453         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2454
2455         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2456
2457         return status;
2458 }
2459
2460 /**
2461  * i40e_aq_set_vsi_uc_promisc_on_vlan
2462  * @hw: pointer to the hw struct
2463  * @seid: vsi number
2464  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2465  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2466  * @cmd_details: pointer to command details structure or NULL
2467  **/
2468 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2469                                 u16 seid, bool enable, u16 vid,
2470                                 struct i40e_asq_cmd_details *cmd_details)
2471 {
2472         struct i40e_aq_desc desc;
2473         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2474                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2475         enum i40e_status_code status;
2476         u16 flags = 0;
2477
2478         i40e_fill_default_direct_cmd_desc(&desc,
2479                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2480
2481         if (enable)
2482                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2483
2484         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2485         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2486         cmd->seid = CPU_TO_LE16(seid);
2487         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2488
2489         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2490
2491         return status;
2492 }
2493
2494 /**
2495  * i40e_aq_set_vsi_bc_promisc_on_vlan
2496  * @hw: pointer to the hw struct
2497  * @seid: vsi number
2498  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2499  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2500  * @cmd_details: pointer to command details structure or NULL
2501  **/
2502 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2503                                 u16 seid, bool enable, u16 vid,
2504                                 struct i40e_asq_cmd_details *cmd_details)
2505 {
2506         struct i40e_aq_desc desc;
2507         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2508                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2509         enum i40e_status_code status;
2510         u16 flags = 0;
2511
2512         i40e_fill_default_direct_cmd_desc(&desc,
2513                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2514
2515         if (enable)
2516                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2517
2518         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2519         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2520         cmd->seid = CPU_TO_LE16(seid);
2521         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2522
2523         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2524
2525         return status;
2526 }
2527
2528 /**
2529  * i40e_aq_set_vsi_broadcast
2530  * @hw: pointer to the hw struct
2531  * @seid: vsi number
2532  * @set_filter: true to set filter, false to clear filter
2533  * @cmd_details: pointer to command details structure or NULL
2534  *
2535  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2536  **/
2537 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2538                                 u16 seid, bool set_filter,
2539                                 struct i40e_asq_cmd_details *cmd_details)
2540 {
2541         struct i40e_aq_desc desc;
2542         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2543                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2544         enum i40e_status_code status;
2545
2546         i40e_fill_default_direct_cmd_desc(&desc,
2547                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2548
2549         if (set_filter)
2550                 cmd->promiscuous_flags
2551                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2552         else
2553                 cmd->promiscuous_flags
2554                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2555
2556         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2557         cmd->seid = CPU_TO_LE16(seid);
2558         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2559
2560         return status;
2561 }
2562
2563 /**
2564  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2565  * @hw: pointer to the hw struct
2566  * @seid: vsi number
2567  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2568  * @cmd_details: pointer to command details structure or NULL
2569  **/
2570 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2571                                 u16 seid, bool enable,
2572                                 struct i40e_asq_cmd_details *cmd_details)
2573 {
2574         struct i40e_aq_desc desc;
2575         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2576                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2577         enum i40e_status_code status;
2578         u16 flags = 0;
2579
2580         i40e_fill_default_direct_cmd_desc(&desc,
2581                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2582         if (enable)
2583                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2584
2585         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2586         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2587         cmd->seid = CPU_TO_LE16(seid);
2588
2589         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2590
2591         return status;
2592 }
2593
2594 /**
2595  * i40e_get_vsi_params - get VSI configuration info
2596  * @hw: pointer to the hw struct
2597  * @vsi_ctx: pointer to a vsi context struct
2598  * @cmd_details: pointer to command details structure or NULL
2599  **/
2600 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2601                                 struct i40e_vsi_context *vsi_ctx,
2602                                 struct i40e_asq_cmd_details *cmd_details)
2603 {
2604         struct i40e_aq_desc desc;
2605         struct i40e_aqc_add_get_update_vsi *cmd =
2606                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2607         struct i40e_aqc_add_get_update_vsi_completion *resp =
2608                 (struct i40e_aqc_add_get_update_vsi_completion *)
2609                 &desc.params.raw;
2610         enum i40e_status_code status;
2611
2612         UNREFERENCED_1PARAMETER(cmd_details);
2613         i40e_fill_default_direct_cmd_desc(&desc,
2614                                           i40e_aqc_opc_get_vsi_parameters);
2615
2616         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2617
2618         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2619
2620         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2621                                     sizeof(vsi_ctx->info), NULL);
2622
2623         if (status != I40E_SUCCESS)
2624                 goto aq_get_vsi_params_exit;
2625
2626         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2627         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2628         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2629         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2630
2631 aq_get_vsi_params_exit:
2632         return status;
2633 }
2634
2635 /**
2636  * i40e_aq_update_vsi_params
2637  * @hw: pointer to the hw struct
2638  * @vsi_ctx: pointer to a vsi context struct
2639  * @cmd_details: pointer to command details structure or NULL
2640  *
2641  * Update a VSI context.
2642  **/
2643 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2644                                 struct i40e_vsi_context *vsi_ctx,
2645                                 struct i40e_asq_cmd_details *cmd_details)
2646 {
2647         struct i40e_aq_desc desc;
2648         struct i40e_aqc_add_get_update_vsi *cmd =
2649                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2650         struct i40e_aqc_add_get_update_vsi_completion *resp =
2651                 (struct i40e_aqc_add_get_update_vsi_completion *)
2652                 &desc.params.raw;
2653         enum i40e_status_code status;
2654
2655         i40e_fill_default_direct_cmd_desc(&desc,
2656                                           i40e_aqc_opc_update_vsi_parameters);
2657         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2658
2659         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2660
2661         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2662                                     sizeof(vsi_ctx->info), cmd_details);
2663
2664         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2665         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2666
2667         return status;
2668 }
2669
2670 /**
2671  * i40e_aq_get_switch_config
2672  * @hw: pointer to the hardware structure
2673  * @buf: pointer to the result buffer
2674  * @buf_size: length of input buffer
2675  * @start_seid: seid to start for the report, 0 == beginning
2676  * @cmd_details: pointer to command details structure or NULL
2677  *
2678  * Fill the buf with switch configuration returned from AdminQ command
2679  **/
2680 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2681                                 struct i40e_aqc_get_switch_config_resp *buf,
2682                                 u16 buf_size, u16 *start_seid,
2683                                 struct i40e_asq_cmd_details *cmd_details)
2684 {
2685         struct i40e_aq_desc desc;
2686         struct i40e_aqc_switch_seid *scfg =
2687                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2688         enum i40e_status_code status;
2689
2690         i40e_fill_default_direct_cmd_desc(&desc,
2691                                           i40e_aqc_opc_get_switch_config);
2692         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2693         if (buf_size > I40E_AQ_LARGE_BUF)
2694                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2695         scfg->seid = CPU_TO_LE16(*start_seid);
2696
2697         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2698         *start_seid = LE16_TO_CPU(scfg->seid);
2699
2700         return status;
2701 }
2702
2703 /**
2704  * i40e_aq_set_switch_config
2705  * @hw: pointer to the hardware structure
2706  * @flags: bit flag values to set
2707  * @mode: cloud filter mode
2708  * @valid_flags: which bit flags to set
2709  * @cmd_details: pointer to command details structure or NULL
2710  *
2711  * Set switch configuration bits
2712  **/
2713 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2714                                 u16 flags, u16 valid_flags, u8 mode,
2715                                 struct i40e_asq_cmd_details *cmd_details)
2716 {
2717         struct i40e_aq_desc desc;
2718         struct i40e_aqc_set_switch_config *scfg =
2719                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2720         enum i40e_status_code status;
2721
2722         i40e_fill_default_direct_cmd_desc(&desc,
2723                                           i40e_aqc_opc_set_switch_config);
2724         scfg->flags = CPU_TO_LE16(flags);
2725         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2726         scfg->mode = mode;
2727         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2728                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2729                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2730                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2731         }
2732         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2733
2734         return status;
2735 }
2736
2737 /**
2738  * i40e_aq_get_firmware_version
2739  * @hw: pointer to the hw struct
2740  * @fw_major_version: firmware major version
2741  * @fw_minor_version: firmware minor version
2742  * @fw_build: firmware build number
2743  * @api_major_version: major queue version
2744  * @api_minor_version: minor queue version
2745  * @cmd_details: pointer to command details structure or NULL
2746  *
2747  * Get the firmware version from the admin queue commands
2748  **/
2749 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2750                                 u16 *fw_major_version, u16 *fw_minor_version,
2751                                 u32 *fw_build,
2752                                 u16 *api_major_version, u16 *api_minor_version,
2753                                 struct i40e_asq_cmd_details *cmd_details)
2754 {
2755         struct i40e_aq_desc desc;
2756         struct i40e_aqc_get_version *resp =
2757                 (struct i40e_aqc_get_version *)&desc.params.raw;
2758         enum i40e_status_code status;
2759
2760         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2761
2762         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2763
2764         if (status == I40E_SUCCESS) {
2765                 if (fw_major_version != NULL)
2766                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2767                 if (fw_minor_version != NULL)
2768                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2769                 if (fw_build != NULL)
2770                         *fw_build = LE32_TO_CPU(resp->fw_build);
2771                 if (api_major_version != NULL)
2772                         *api_major_version = LE16_TO_CPU(resp->api_major);
2773                 if (api_minor_version != NULL)
2774                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2775
2776                 /* A workaround to fix the API version in SW */
2777                 if (api_major_version && api_minor_version &&
2778                     fw_major_version && fw_minor_version &&
2779                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2780                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2781                      (*fw_major_version > 4)))
2782                         *api_minor_version = 2;
2783         }
2784
2785         return status;
2786 }
2787
2788 /**
2789  * i40e_aq_send_driver_version
2790  * @hw: pointer to the hw struct
2791  * @dv: driver's major, minor version
2792  * @cmd_details: pointer to command details structure or NULL
2793  *
2794  * Send the driver version to the firmware
2795  **/
2796 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2797                                 struct i40e_driver_version *dv,
2798                                 struct i40e_asq_cmd_details *cmd_details)
2799 {
2800         struct i40e_aq_desc desc;
2801         struct i40e_aqc_driver_version *cmd =
2802                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2803         enum i40e_status_code status;
2804         u16 len;
2805
2806         if (dv == NULL)
2807                 return I40E_ERR_PARAM;
2808
2809         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2810
2811         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2812         cmd->driver_major_ver = dv->major_version;
2813         cmd->driver_minor_ver = dv->minor_version;
2814         cmd->driver_build_ver = dv->build_version;
2815         cmd->driver_subbuild_ver = dv->subbuild_version;
2816
2817         len = 0;
2818         while (len < sizeof(dv->driver_string) &&
2819                (dv->driver_string[len] < 0x80) &&
2820                dv->driver_string[len])
2821                 len++;
2822         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2823                                        len, cmd_details);
2824
2825         return status;
2826 }
2827
2828 /**
2829  * i40e_get_link_status - get status of the HW network link
2830  * @hw: pointer to the hw struct
2831  * @link_up: pointer to bool (true/false = linkup/linkdown)
2832  *
2833  * Variable link_up true if link is up, false if link is down.
2834  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2835  *
2836  * Side effect: LinkStatusEvent reporting becomes enabled
2837  **/
2838 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2839 {
2840         enum i40e_status_code status = I40E_SUCCESS;
2841
2842         if (hw->phy.get_link_info) {
2843                 status = i40e_update_link_info(hw);
2844
2845                 if (status != I40E_SUCCESS)
2846                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2847                                    status);
2848         }
2849
2850         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2851
2852         return status;
2853 }
2854
2855 /**
2856  * i40e_updatelink_status - update status of the HW network link
2857  * @hw: pointer to the hw struct
2858  **/
2859 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2860 {
2861         struct i40e_aq_get_phy_abilities_resp abilities;
2862         enum i40e_status_code status = I40E_SUCCESS;
2863
2864         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2865         if (status)
2866                 return status;
2867
2868         /* extra checking needed to ensure link info to user is timely */
2869         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2870             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2871              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2872                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2873                                                       &abilities, NULL);
2874                 if (status)
2875                         return status;
2876
2877                 hw->phy.link_info.req_fec_info =
2878                         abilities.fec_cfg_curr_mod_ext_info &
2879                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2880
2881                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2882                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2883         }
2884         return status;
2885 }
2886
2887
2888 /**
2889  * i40e_get_link_speed
2890  * @hw: pointer to the hw struct
2891  *
2892  * Returns the link speed of the adapter.
2893  **/
2894 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2895 {
2896         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2897         enum i40e_status_code status = I40E_SUCCESS;
2898
2899         if (hw->phy.get_link_info) {
2900                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2901
2902                 if (status != I40E_SUCCESS)
2903                         goto i40e_link_speed_exit;
2904         }
2905
2906         speed = hw->phy.link_info.link_speed;
2907
2908 i40e_link_speed_exit:
2909         return speed;
2910 }
2911
2912 /**
2913  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2914  * @hw: pointer to the hw struct
2915  * @uplink_seid: the MAC or other gizmo SEID
2916  * @downlink_seid: the VSI SEID
2917  * @enabled_tc: bitmap of TCs to be enabled
2918  * @default_port: true for default port VSI, false for control port
2919  * @veb_seid: pointer to where to put the resulting VEB SEID
2920  * @enable_stats: true to turn on VEB stats
2921  * @cmd_details: pointer to command details structure or NULL
2922  *
2923  * This asks the FW to add a VEB between the uplink and downlink
2924  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2925  **/
2926 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2927                                 u16 downlink_seid, u8 enabled_tc,
2928                                 bool default_port, u16 *veb_seid,
2929                                 bool enable_stats,
2930                                 struct i40e_asq_cmd_details *cmd_details)
2931 {
2932         struct i40e_aq_desc desc;
2933         struct i40e_aqc_add_veb *cmd =
2934                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2935         struct i40e_aqc_add_veb_completion *resp =
2936                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2937         enum i40e_status_code status;
2938         u16 veb_flags = 0;
2939
2940         /* SEIDs need to either both be set or both be 0 for floating VEB */
2941         if (!!uplink_seid != !!downlink_seid)
2942                 return I40E_ERR_PARAM;
2943
2944         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2945
2946         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2947         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2948         cmd->enable_tcs = enabled_tc;
2949         if (!uplink_seid)
2950                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2951         if (default_port)
2952                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2953         else
2954                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2955
2956         /* reverse logic here: set the bitflag to disable the stats */
2957         if (!enable_stats)
2958                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2959
2960         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2961
2962         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2963
2964         if (!status && veb_seid)
2965                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2966
2967         return status;
2968 }
2969
2970 /**
2971  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2972  * @hw: pointer to the hw struct
2973  * @veb_seid: the SEID of the VEB to query
2974  * @switch_id: the uplink switch id
2975  * @floating: set to true if the VEB is floating
2976  * @statistic_index: index of the stats counter block for this VEB
2977  * @vebs_used: number of VEB's used by function
2978  * @vebs_free: total VEB's not reserved by any function
2979  * @cmd_details: pointer to command details structure or NULL
2980  *
2981  * This retrieves the parameters for a particular VEB, specified by
2982  * uplink_seid, and returns them to the caller.
2983  **/
2984 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2985                                 u16 veb_seid, u16 *switch_id,
2986                                 bool *floating, u16 *statistic_index,
2987                                 u16 *vebs_used, u16 *vebs_free,
2988                                 struct i40e_asq_cmd_details *cmd_details)
2989 {
2990         struct i40e_aq_desc desc;
2991         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2992                 (struct i40e_aqc_get_veb_parameters_completion *)
2993                 &desc.params.raw;
2994         enum i40e_status_code status;
2995
2996         if (veb_seid == 0)
2997                 return I40E_ERR_PARAM;
2998
2999         i40e_fill_default_direct_cmd_desc(&desc,
3000                                           i40e_aqc_opc_get_veb_parameters);
3001         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3002
3003         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3004         if (status)
3005                 goto get_veb_exit;
3006
3007         if (switch_id)
3008                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3009         if (statistic_index)
3010                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3011         if (vebs_used)
3012                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3013         if (vebs_free)
3014                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3015         if (floating) {
3016                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3017
3018                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3019                         *floating = true;
3020                 else
3021                         *floating = false;
3022         }
3023
3024 get_veb_exit:
3025         return status;
3026 }
3027
3028 /**
3029  * i40e_aq_add_macvlan
3030  * @hw: pointer to the hw struct
3031  * @seid: VSI for the mac address
3032  * @mv_list: list of macvlans to be added
3033  * @count: length of the list
3034  * @cmd_details: pointer to command details structure or NULL
3035  *
3036  * Add MAC/VLAN addresses to the HW filtering
3037  **/
3038 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3039                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3040                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3041 {
3042         struct i40e_aq_desc desc;
3043         struct i40e_aqc_macvlan *cmd =
3044                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3045         enum i40e_status_code status;
3046         u16 buf_size;
3047         int i;
3048
3049         if (count == 0 || !mv_list || !hw)
3050                 return I40E_ERR_PARAM;
3051
3052         buf_size = count * sizeof(*mv_list);
3053
3054         /* prep the rest of the request */
3055         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3056         cmd->num_addresses = CPU_TO_LE16(count);
3057         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3058         cmd->seid[1] = 0;
3059         cmd->seid[2] = 0;
3060
3061         for (i = 0; i < count; i++)
3062                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3063                         mv_list[i].flags |=
3064                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3065
3066         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3067         if (buf_size > I40E_AQ_LARGE_BUF)
3068                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3069
3070         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3071                                        cmd_details);
3072
3073         return status;
3074 }
3075
3076 /**
3077  * i40e_aq_remove_macvlan
3078  * @hw: pointer to the hw struct
3079  * @seid: VSI for the mac address
3080  * @mv_list: list of macvlans to be removed
3081  * @count: length of the list
3082  * @cmd_details: pointer to command details structure or NULL
3083  *
3084  * Remove MAC/VLAN addresses from the HW filtering
3085  **/
3086 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3087                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3088                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3089 {
3090         struct i40e_aq_desc desc;
3091         struct i40e_aqc_macvlan *cmd =
3092                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3093         enum i40e_status_code status;
3094         u16 buf_size;
3095
3096         if (count == 0 || !mv_list || !hw)
3097                 return I40E_ERR_PARAM;
3098
3099         buf_size = count * sizeof(*mv_list);
3100
3101         /* prep the rest of the request */
3102         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3103         cmd->num_addresses = CPU_TO_LE16(count);
3104         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3105         cmd->seid[1] = 0;
3106         cmd->seid[2] = 0;
3107
3108         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3109         if (buf_size > I40E_AQ_LARGE_BUF)
3110                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3111
3112         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3113                                        cmd_details);
3114
3115         return status;
3116 }
3117
3118 /**
3119  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3120  * @hw: pointer to the hw struct
3121  * @opcode: AQ opcode for add or delete mirror rule
3122  * @sw_seid: Switch SEID (to which rule refers)
3123  * @rule_type: Rule Type (ingress/egress/VLAN)
3124  * @id: Destination VSI SEID or Rule ID
3125  * @count: length of the list
3126  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3127  * @cmd_details: pointer to command details structure or NULL
3128  * @rule_id: Rule ID returned from FW
3129  * @rules_used: Number of rules used in internal switch
3130  * @rules_free: Number of rules free in internal switch
3131  *
3132  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3133  * VEBs/VEPA elements only
3134  **/
3135 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3136                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3137                         u16 count, __le16 *mr_list,
3138                         struct i40e_asq_cmd_details *cmd_details,
3139                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3140 {
3141         struct i40e_aq_desc desc;
3142         struct i40e_aqc_add_delete_mirror_rule *cmd =
3143                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3144         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3145         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3146         enum i40e_status_code status;
3147         u16 buf_size;
3148
3149         buf_size = count * sizeof(*mr_list);
3150
3151         /* prep the rest of the request */
3152         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3153         cmd->seid = CPU_TO_LE16(sw_seid);
3154         cmd->rule_type = CPU_TO_LE16(rule_type &
3155                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3156         cmd->num_entries = CPU_TO_LE16(count);
3157         /* Dest VSI for add, rule_id for delete */
3158         cmd->destination = CPU_TO_LE16(id);
3159         if (mr_list) {
3160                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3161                                                 I40E_AQ_FLAG_RD));
3162                 if (buf_size > I40E_AQ_LARGE_BUF)
3163                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3164         }
3165
3166         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3167                                        cmd_details);
3168         if (status == I40E_SUCCESS ||
3169             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3170                 if (rule_id)
3171                         *rule_id = LE16_TO_CPU(resp->rule_id);
3172                 if (rules_used)
3173                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3174                 if (rules_free)
3175                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3176         }
3177         return status;
3178 }
3179
3180 /**
3181  * i40e_aq_add_mirrorrule - add a mirror rule
3182  * @hw: pointer to the hw struct
3183  * @sw_seid: Switch SEID (to which rule refers)
3184  * @rule_type: Rule Type (ingress/egress/VLAN)
3185  * @dest_vsi: SEID of VSI to which packets will be mirrored
3186  * @count: length of the list
3187  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3188  * @cmd_details: pointer to command details structure or NULL
3189  * @rule_id: Rule ID returned from FW
3190  * @rules_used: Number of rules used in internal switch
3191  * @rules_free: Number of rules free in internal switch
3192  *
3193  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3194  **/
3195 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3196                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3197                         struct i40e_asq_cmd_details *cmd_details,
3198                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3199 {
3200         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3201             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3202                 if (count == 0 || !mr_list)
3203                         return I40E_ERR_PARAM;
3204         }
3205
3206         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3207                                   rule_type, dest_vsi, count, mr_list,
3208                                   cmd_details, rule_id, rules_used, rules_free);
3209 }
3210
3211 /**
3212  * i40e_aq_delete_mirrorrule - delete a mirror rule
3213  * @hw: pointer to the hw struct
3214  * @sw_seid: Switch SEID (to which rule refers)
3215  * @rule_type: Rule Type (ingress/egress/VLAN)
3216  * @count: length of the list
3217  * @rule_id: Rule ID that is returned in the receive desc as part of
3218  *              add_mirrorrule.
3219  * @mr_list: list of mirrored VLAN IDs to be removed
3220  * @cmd_details: pointer to command details structure or NULL
3221  * @rules_used: Number of rules used in internal switch
3222  * @rules_free: Number of rules free in internal switch
3223  *
3224  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3225  **/
3226 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3227                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3228                         struct i40e_asq_cmd_details *cmd_details,
3229                         u16 *rules_used, u16 *rules_free)
3230 {
3231         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3232         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3233                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3234                  * mirroring. For other rule_type, count and rule_type should
3235                  * not matter.
3236                  */
3237                 if (count == 0 || !mr_list)
3238                         return I40E_ERR_PARAM;
3239         }
3240
3241         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3242                                   rule_type, rule_id, count, mr_list,
3243                                   cmd_details, NULL, rules_used, rules_free);
3244 }
3245
3246 /**
3247  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3248  * @hw: pointer to the hw struct
3249  * @seid: VSI for the vlan filters
3250  * @v_list: list of vlan filters to be added
3251  * @count: length of the list
3252  * @cmd_details: pointer to command details structure or NULL
3253  **/
3254 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3255                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3256                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3257 {
3258         struct i40e_aq_desc desc;
3259         struct i40e_aqc_macvlan *cmd =
3260                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3261         enum i40e_status_code status;
3262         u16 buf_size;
3263
3264         if (count == 0 || !v_list || !hw)
3265                 return I40E_ERR_PARAM;
3266
3267         buf_size = count * sizeof(*v_list);
3268
3269         /* prep the rest of the request */
3270         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3271         cmd->num_addresses = CPU_TO_LE16(count);
3272         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3273         cmd->seid[1] = 0;
3274         cmd->seid[2] = 0;
3275
3276         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3277         if (buf_size > I40E_AQ_LARGE_BUF)
3278                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3279
3280         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3281                                        cmd_details);
3282
3283         return status;
3284 }
3285
3286 /**
3287  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3288  * @hw: pointer to the hw struct
3289  * @seid: VSI for the vlan filters
3290  * @v_list: list of macvlans to be removed
3291  * @count: length of the list
3292  * @cmd_details: pointer to command details structure or NULL
3293  **/
3294 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3295                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3296                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3297 {
3298         struct i40e_aq_desc desc;
3299         struct i40e_aqc_macvlan *cmd =
3300                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3301         enum i40e_status_code status;
3302         u16 buf_size;
3303
3304         if (count == 0 || !v_list || !hw)
3305                 return I40E_ERR_PARAM;
3306
3307         buf_size = count * sizeof(*v_list);
3308
3309         /* prep the rest of the request */
3310         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3311         cmd->num_addresses = CPU_TO_LE16(count);
3312         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3313         cmd->seid[1] = 0;
3314         cmd->seid[2] = 0;
3315
3316         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3317         if (buf_size > I40E_AQ_LARGE_BUF)
3318                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3319
3320         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3321                                        cmd_details);
3322
3323         return status;
3324 }
3325
3326 /**
3327  * i40e_aq_send_msg_to_vf
3328  * @hw: pointer to the hardware structure
3329  * @vfid: vf id to send msg
3330  * @v_opcode: opcodes for VF-PF communication
3331  * @v_retval: return error code
3332  * @msg: pointer to the msg buffer
3333  * @msglen: msg length
3334  * @cmd_details: pointer to command details
3335  *
3336  * send msg to vf
3337  **/
3338 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3339                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3340                                 struct i40e_asq_cmd_details *cmd_details)
3341 {
3342         struct i40e_aq_desc desc;
3343         struct i40e_aqc_pf_vf_message *cmd =
3344                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3345         enum i40e_status_code status;
3346
3347         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3348         cmd->id = CPU_TO_LE32(vfid);
3349         desc.cookie_high = CPU_TO_LE32(v_opcode);
3350         desc.cookie_low = CPU_TO_LE32(v_retval);
3351         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3352         if (msglen) {
3353                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3354                                                 I40E_AQ_FLAG_RD));
3355                 if (msglen > I40E_AQ_LARGE_BUF)
3356                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3357                 desc.datalen = CPU_TO_LE16(msglen);
3358         }
3359         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3360
3361         return status;
3362 }
3363
3364 /**
3365  * i40e_aq_debug_read_register
3366  * @hw: pointer to the hw struct
3367  * @reg_addr: register address
3368  * @reg_val: register value
3369  * @cmd_details: pointer to command details structure or NULL
3370  *
3371  * Read the register using the admin queue commands
3372  **/
3373 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3374                                 u32 reg_addr, u64 *reg_val,
3375                                 struct i40e_asq_cmd_details *cmd_details)
3376 {
3377         struct i40e_aq_desc desc;
3378         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3379                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3380         enum i40e_status_code status;
3381
3382         if (reg_val == NULL)
3383                 return I40E_ERR_PARAM;
3384
3385         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3386
3387         cmd_resp->address = CPU_TO_LE32(reg_addr);
3388
3389         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3390
3391         if (status == I40E_SUCCESS) {
3392                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3393                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3394         }
3395
3396         return status;
3397 }
3398
3399 /**
3400  * i40e_aq_debug_write_register
3401  * @hw: pointer to the hw struct
3402  * @reg_addr: register address
3403  * @reg_val: register value
3404  * @cmd_details: pointer to command details structure or NULL
3405  *
3406  * Write to a register using the admin queue commands
3407  **/
3408 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3409                                 u32 reg_addr, u64 reg_val,
3410                                 struct i40e_asq_cmd_details *cmd_details)
3411 {
3412         struct i40e_aq_desc desc;
3413         struct i40e_aqc_debug_reg_read_write *cmd =
3414                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3415         enum i40e_status_code status;
3416
3417         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3418
3419         cmd->address = CPU_TO_LE32(reg_addr);
3420         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3421         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3422
3423         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3424
3425         return status;
3426 }
3427
3428 /**
3429  * i40e_aq_request_resource
3430  * @hw: pointer to the hw struct
3431  * @resource: resource id
3432  * @access: access type
3433  * @sdp_number: resource number
3434  * @timeout: the maximum time in ms that the driver may hold the resource
3435  * @cmd_details: pointer to command details structure or NULL
3436  *
3437  * requests common resource using the admin queue commands
3438  **/
3439 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3440                                 enum i40e_aq_resources_ids resource,
3441                                 enum i40e_aq_resource_access_type access,
3442                                 u8 sdp_number, u64 *timeout,
3443                                 struct i40e_asq_cmd_details *cmd_details)
3444 {
3445         struct i40e_aq_desc desc;
3446         struct i40e_aqc_request_resource *cmd_resp =
3447                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3448         enum i40e_status_code status;
3449
3450         DEBUGFUNC("i40e_aq_request_resource");
3451
3452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3453
3454         cmd_resp->resource_id = CPU_TO_LE16(resource);
3455         cmd_resp->access_type = CPU_TO_LE16(access);
3456         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3457
3458         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3459         /* The completion specifies the maximum time in ms that the driver
3460          * may hold the resource in the Timeout field.
3461          * If the resource is held by someone else, the command completes with
3462          * busy return value and the timeout field indicates the maximum time
3463          * the current owner of the resource has to free it.
3464          */
3465         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3466                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3467
3468         return status;
3469 }
3470
3471 /**
3472  * i40e_aq_release_resource
3473  * @hw: pointer to the hw struct
3474  * @resource: resource id
3475  * @sdp_number: resource number
3476  * @cmd_details: pointer to command details structure or NULL
3477  *
3478  * release common resource using the admin queue commands
3479  **/
3480 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3481                                 enum i40e_aq_resources_ids resource,
3482                                 u8 sdp_number,
3483                                 struct i40e_asq_cmd_details *cmd_details)
3484 {
3485         struct i40e_aq_desc desc;
3486         struct i40e_aqc_request_resource *cmd =
3487                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3488         enum i40e_status_code status;
3489
3490         DEBUGFUNC("i40e_aq_release_resource");
3491
3492         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3493
3494         cmd->resource_id = CPU_TO_LE16(resource);
3495         cmd->resource_number = CPU_TO_LE32(sdp_number);
3496
3497         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3498
3499         return status;
3500 }
3501
3502 /**
3503  * i40e_aq_read_nvm
3504  * @hw: pointer to the hw struct
3505  * @module_pointer: module pointer location in words from the NVM beginning
3506  * @offset: byte offset from the module beginning
3507  * @length: length of the section to be read (in bytes from the offset)
3508  * @data: command buffer (size [bytes] = length)
3509  * @last_command: tells if this is the last command in a series
3510  * @cmd_details: pointer to command details structure or NULL
3511  *
3512  * Read the NVM using the admin queue commands
3513  **/
3514 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3515                                 u32 offset, u16 length, void *data,
3516                                 bool last_command,
3517                                 struct i40e_asq_cmd_details *cmd_details)
3518 {
3519         struct i40e_aq_desc desc;
3520         struct i40e_aqc_nvm_update *cmd =
3521                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3522         enum i40e_status_code status;
3523
3524         DEBUGFUNC("i40e_aq_read_nvm");
3525
3526         /* In offset the highest byte must be zeroed. */
3527         if (offset & 0xFF000000) {
3528                 status = I40E_ERR_PARAM;
3529                 goto i40e_aq_read_nvm_exit;
3530         }
3531
3532         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3533
3534         /* If this is the last command in a series, set the proper flag. */
3535         if (last_command)
3536                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3537         cmd->module_pointer = module_pointer;
3538         cmd->offset = CPU_TO_LE32(offset);
3539         cmd->length = CPU_TO_LE16(length);
3540
3541         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3542         if (length > I40E_AQ_LARGE_BUF)
3543                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3544
3545         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3546
3547 i40e_aq_read_nvm_exit:
3548         return status;
3549 }
3550
3551 /**
3552  * i40e_aq_read_nvm_config - read an nvm config block
3553  * @hw: pointer to the hw struct
3554  * @cmd_flags: NVM access admin command bits
3555  * @field_id: field or feature id
3556  * @data: buffer for result
3557  * @buf_size: buffer size
3558  * @element_count: pointer to count of elements read by FW
3559  * @cmd_details: pointer to command details structure or NULL
3560  **/
3561 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3562                                 u8 cmd_flags, u32 field_id, void *data,
3563                                 u16 buf_size, u16 *element_count,
3564                                 struct i40e_asq_cmd_details *cmd_details)
3565 {
3566         struct i40e_aq_desc desc;
3567         struct i40e_aqc_nvm_config_read *cmd =
3568                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3569         enum i40e_status_code status;
3570
3571         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3572         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3573         if (buf_size > I40E_AQ_LARGE_BUF)
3574                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3575
3576         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3577         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3578         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3579                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3580         else
3581                 cmd->element_id_msw = 0;
3582
3583         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3584
3585         if (!status && element_count)
3586                 *element_count = LE16_TO_CPU(cmd->element_count);
3587
3588         return status;
3589 }
3590
3591 /**
3592  * i40e_aq_write_nvm_config - write an nvm config block
3593  * @hw: pointer to the hw struct
3594  * @cmd_flags: NVM access admin command bits
3595  * @data: buffer for result
3596  * @buf_size: buffer size
3597  * @element_count: count of elements to be written
3598  * @cmd_details: pointer to command details structure or NULL
3599  **/
3600 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3601                                 u8 cmd_flags, void *data, u16 buf_size,
3602                                 u16 element_count,
3603                                 struct i40e_asq_cmd_details *cmd_details)
3604 {
3605         struct i40e_aq_desc desc;
3606         struct i40e_aqc_nvm_config_write *cmd =
3607                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3608         enum i40e_status_code status;
3609
3610         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3611         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3612         if (buf_size > I40E_AQ_LARGE_BUF)
3613                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3614
3615         cmd->element_count = CPU_TO_LE16(element_count);
3616         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3617         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3618
3619         return status;
3620 }
3621
3622 /**
3623  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3624  * @hw: pointer to the hw struct
3625  * @buff: buffer for result
3626  * @buff_size: buffer size
3627  * @cmd_details: pointer to command details structure or NULL
3628  **/
3629 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3630                                 void *buff, u16 buff_size,
3631                                 struct i40e_asq_cmd_details *cmd_details)
3632 {
3633         struct i40e_aq_desc desc;
3634         enum i40e_status_code status;
3635
3636         UNREFERENCED_2PARAMETER(buff, buff_size);
3637
3638         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3639         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3640         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3641                 status = I40E_ERR_NOT_IMPLEMENTED;
3642
3643         return status;
3644 }
3645
3646 /**
3647  * i40e_aq_erase_nvm
3648  * @hw: pointer to the hw struct
3649  * @module_pointer: module pointer location in words from the NVM beginning
3650  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3651  * @length: length of the section to be erased (expressed in 4 KB)
3652  * @last_command: tells if this is the last command in a series
3653  * @cmd_details: pointer to command details structure or NULL
3654  *
3655  * Erase the NVM sector using the admin queue commands
3656  **/
3657 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3658                                 u32 offset, u16 length, bool last_command,
3659                                 struct i40e_asq_cmd_details *cmd_details)
3660 {
3661         struct i40e_aq_desc desc;
3662         struct i40e_aqc_nvm_update *cmd =
3663                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3664         enum i40e_status_code status;
3665
3666         DEBUGFUNC("i40e_aq_erase_nvm");
3667
3668         /* In offset the highest byte must be zeroed. */
3669         if (offset & 0xFF000000) {
3670                 status = I40E_ERR_PARAM;
3671                 goto i40e_aq_erase_nvm_exit;
3672         }
3673
3674         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3675
3676         /* If this is the last command in a series, set the proper flag. */
3677         if (last_command)
3678                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3679         cmd->module_pointer = module_pointer;
3680         cmd->offset = CPU_TO_LE32(offset);
3681         cmd->length = CPU_TO_LE16(length);
3682
3683         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3684
3685 i40e_aq_erase_nvm_exit:
3686         return status;
3687 }
3688
3689 /**
3690  * i40e_parse_discover_capabilities
3691  * @hw: pointer to the hw struct
3692  * @buff: pointer to a buffer containing device/function capability records
3693  * @cap_count: number of capability records in the list
3694  * @list_type_opc: type of capabilities list to parse
3695  *
3696  * Parse the device/function capabilities list.
3697  **/
3698 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3699                                      u32 cap_count,
3700                                      enum i40e_admin_queue_opc list_type_opc)
3701 {
3702         struct i40e_aqc_list_capabilities_element_resp *cap;
3703         u32 valid_functions, num_functions;
3704         u32 number, logical_id, phys_id;
3705         struct i40e_hw_capabilities *p;
3706         enum i40e_status_code status;
3707         u16 id, ocp_cfg_word0;
3708         u8 major_rev;
3709         u32 i = 0;
3710
3711         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3712
3713         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3714                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3715         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3716                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3717         else
3718                 return;
3719
3720         for (i = 0; i < cap_count; i++, cap++) {
3721                 id = LE16_TO_CPU(cap->id);
3722                 number = LE32_TO_CPU(cap->number);
3723                 logical_id = LE32_TO_CPU(cap->logical_id);
3724                 phys_id = LE32_TO_CPU(cap->phys_id);
3725                 major_rev = cap->major_rev;
3726
3727                 switch (id) {
3728                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3729                         p->switch_mode = number;
3730                         i40e_debug(hw, I40E_DEBUG_INIT,
3731                                    "HW Capability: Switch mode = %d\n",
3732                                    p->switch_mode);
3733                         break;
3734                 case I40E_AQ_CAP_ID_MNG_MODE:
3735                         p->management_mode = number;
3736                         if (major_rev > 1) {
3737                                 p->mng_protocols_over_mctp = logical_id;
3738                                 i40e_debug(hw, I40E_DEBUG_INIT,
3739                                            "HW Capability: Protocols over MCTP = %d\n",
3740                                            p->mng_protocols_over_mctp);
3741                         } else {
3742                                 p->mng_protocols_over_mctp = 0;
3743                         }
3744                         i40e_debug(hw, I40E_DEBUG_INIT,
3745                                    "HW Capability: Management Mode = %d\n",
3746                                    p->management_mode);
3747                         break;
3748                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3749                         p->npar_enable = number;
3750                         i40e_debug(hw, I40E_DEBUG_INIT,
3751                                    "HW Capability: NPAR enable = %d\n",
3752                                    p->npar_enable);
3753                         break;
3754                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3755                         p->os2bmc = number;
3756                         i40e_debug(hw, I40E_DEBUG_INIT,
3757                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3758                         break;
3759                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3760                         p->valid_functions = number;
3761                         i40e_debug(hw, I40E_DEBUG_INIT,
3762                                    "HW Capability: Valid Functions = %d\n",
3763                                    p->valid_functions);
3764                         break;
3765                 case I40E_AQ_CAP_ID_SRIOV:
3766                         if (number == 1)
3767                                 p->sr_iov_1_1 = true;
3768                         i40e_debug(hw, I40E_DEBUG_INIT,
3769                                    "HW Capability: SR-IOV = %d\n",
3770                                    p->sr_iov_1_1);
3771                         break;
3772                 case I40E_AQ_CAP_ID_VF:
3773                         p->num_vfs = number;
3774                         p->vf_base_id = logical_id;
3775                         i40e_debug(hw, I40E_DEBUG_INIT,
3776                                    "HW Capability: VF count = %d\n",
3777                                    p->num_vfs);
3778                         i40e_debug(hw, I40E_DEBUG_INIT,
3779                                    "HW Capability: VF base_id = %d\n",
3780                                    p->vf_base_id);
3781                         break;
3782                 case I40E_AQ_CAP_ID_VMDQ:
3783                         if (number == 1)
3784                                 p->vmdq = true;
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3787                         break;
3788                 case I40E_AQ_CAP_ID_8021QBG:
3789                         if (number == 1)
3790                                 p->evb_802_1_qbg = true;
3791                         i40e_debug(hw, I40E_DEBUG_INIT,
3792                                    "HW Capability: 802.1Qbg = %d\n", number);
3793                         break;
3794                 case I40E_AQ_CAP_ID_8021QBR:
3795                         if (number == 1)
3796                                 p->evb_802_1_qbh = true;
3797                         i40e_debug(hw, I40E_DEBUG_INIT,
3798                                    "HW Capability: 802.1Qbh = %d\n", number);
3799                         break;
3800                 case I40E_AQ_CAP_ID_VSI:
3801                         p->num_vsis = number;
3802                         i40e_debug(hw, I40E_DEBUG_INIT,
3803                                    "HW Capability: VSI count = %d\n",
3804                                    p->num_vsis);
3805                         break;
3806                 case I40E_AQ_CAP_ID_DCB:
3807                         if (number == 1) {
3808                                 p->dcb = true;
3809                                 p->enabled_tcmap = logical_id;
3810                                 p->maxtc = phys_id;
3811                         }
3812                         i40e_debug(hw, I40E_DEBUG_INIT,
3813                                    "HW Capability: DCB = %d\n", p->dcb);
3814                         i40e_debug(hw, I40E_DEBUG_INIT,
3815                                    "HW Capability: TC Mapping = %d\n",
3816                                    logical_id);
3817                         i40e_debug(hw, I40E_DEBUG_INIT,
3818                                    "HW Capability: TC Max = %d\n", p->maxtc);
3819                         break;
3820                 case I40E_AQ_CAP_ID_FCOE:
3821                         if (number == 1)
3822                                 p->fcoe = true;
3823                         i40e_debug(hw, I40E_DEBUG_INIT,
3824                                    "HW Capability: FCOE = %d\n", p->fcoe);
3825                         break;
3826                 case I40E_AQ_CAP_ID_ISCSI:
3827                         if (number == 1)
3828                                 p->iscsi = true;
3829                         i40e_debug(hw, I40E_DEBUG_INIT,
3830                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3831                         break;
3832                 case I40E_AQ_CAP_ID_RSS:
3833                         p->rss = true;
3834                         p->rss_table_size = number;
3835                         p->rss_table_entry_width = logical_id;
3836                         i40e_debug(hw, I40E_DEBUG_INIT,
3837                                    "HW Capability: RSS = %d\n", p->rss);
3838                         i40e_debug(hw, I40E_DEBUG_INIT,
3839                                    "HW Capability: RSS table size = %d\n",
3840                                    p->rss_table_size);
3841                         i40e_debug(hw, I40E_DEBUG_INIT,
3842                                    "HW Capability: RSS table width = %d\n",
3843                                    p->rss_table_entry_width);
3844                         break;
3845                 case I40E_AQ_CAP_ID_RXQ:
3846                         p->num_rx_qp = number;
3847                         p->base_queue = phys_id;
3848                         i40e_debug(hw, I40E_DEBUG_INIT,
3849                                    "HW Capability: Rx QP = %d\n", number);
3850                         i40e_debug(hw, I40E_DEBUG_INIT,
3851                                    "HW Capability: base_queue = %d\n",
3852                                    p->base_queue);
3853                         break;
3854                 case I40E_AQ_CAP_ID_TXQ:
3855                         p->num_tx_qp = number;
3856                         p->base_queue = phys_id;
3857                         i40e_debug(hw, I40E_DEBUG_INIT,
3858                                    "HW Capability: Tx QP = %d\n", number);
3859                         i40e_debug(hw, I40E_DEBUG_INIT,
3860                                    "HW Capability: base_queue = %d\n",
3861                                    p->base_queue);
3862                         break;
3863                 case I40E_AQ_CAP_ID_MSIX:
3864                         p->num_msix_vectors = number;
3865                         i40e_debug(hw, I40E_DEBUG_INIT,
3866                                    "HW Capability: MSIX vector count = %d\n",
3867                                    p->num_msix_vectors);
3868                         break;
3869                 case I40E_AQ_CAP_ID_VF_MSIX:
3870                         p->num_msix_vectors_vf = number;
3871                         i40e_debug(hw, I40E_DEBUG_INIT,
3872                                    "HW Capability: MSIX VF vector count = %d\n",
3873                                    p->num_msix_vectors_vf);
3874                         break;
3875                 case I40E_AQ_CAP_ID_FLEX10:
3876                         if (major_rev == 1) {
3877                                 if (number == 1) {
3878                                         p->flex10_enable = true;
3879                                         p->flex10_capable = true;
3880                                 }
3881                         } else {
3882                                 /* Capability revision >= 2 */
3883                                 if (number & 1)
3884                                         p->flex10_enable = true;
3885                                 if (number & 2)
3886                                         p->flex10_capable = true;
3887                         }
3888                         p->flex10_mode = logical_id;
3889                         p->flex10_status = phys_id;
3890                         i40e_debug(hw, I40E_DEBUG_INIT,
3891                                    "HW Capability: Flex10 mode = %d\n",
3892                                    p->flex10_mode);
3893                         i40e_debug(hw, I40E_DEBUG_INIT,
3894                                    "HW Capability: Flex10 status = %d\n",
3895                                    p->flex10_status);
3896                         break;
3897                 case I40E_AQ_CAP_ID_CEM:
3898                         if (number == 1)
3899                                 p->mgmt_cem = true;
3900                         i40e_debug(hw, I40E_DEBUG_INIT,
3901                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3902                         break;
3903                 case I40E_AQ_CAP_ID_IWARP:
3904                         if (number == 1)
3905                                 p->iwarp = true;
3906                         i40e_debug(hw, I40E_DEBUG_INIT,
3907                                    "HW Capability: iWARP = %d\n", p->iwarp);
3908                         break;
3909                 case I40E_AQ_CAP_ID_LED:
3910                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3911                                 p->led[phys_id] = true;
3912                         i40e_debug(hw, I40E_DEBUG_INIT,
3913                                    "HW Capability: LED - PIN %d\n", phys_id);
3914                         break;
3915                 case I40E_AQ_CAP_ID_SDP:
3916                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3917                                 p->sdp[phys_id] = true;
3918                         i40e_debug(hw, I40E_DEBUG_INIT,
3919                                    "HW Capability: SDP - PIN %d\n", phys_id);
3920                         break;
3921                 case I40E_AQ_CAP_ID_MDIO:
3922                         if (number == 1) {
3923                                 p->mdio_port_num = phys_id;
3924                                 p->mdio_port_mode = logical_id;
3925                         }
3926                         i40e_debug(hw, I40E_DEBUG_INIT,
3927                                    "HW Capability: MDIO port number = %d\n",
3928                                    p->mdio_port_num);
3929                         i40e_debug(hw, I40E_DEBUG_INIT,
3930                                    "HW Capability: MDIO port mode = %d\n",
3931                                    p->mdio_port_mode);
3932                         break;
3933                 case I40E_AQ_CAP_ID_1588:
3934                         if (number == 1)
3935                                 p->ieee_1588 = true;
3936                         i40e_debug(hw, I40E_DEBUG_INIT,
3937                                    "HW Capability: IEEE 1588 = %d\n",
3938                                    p->ieee_1588);
3939                         break;
3940                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3941                         p->fd = true;
3942                         p->fd_filters_guaranteed = number;
3943                         p->fd_filters_best_effort = logical_id;
3944                         i40e_debug(hw, I40E_DEBUG_INIT,
3945                                    "HW Capability: Flow Director = 1\n");
3946                         i40e_debug(hw, I40E_DEBUG_INIT,
3947                                    "HW Capability: Guaranteed FD filters = %d\n",
3948                                    p->fd_filters_guaranteed);
3949                         break;
3950                 case I40E_AQ_CAP_ID_WSR_PROT:
3951                         p->wr_csr_prot = (u64)number;
3952                         p->wr_csr_prot |= (u64)logical_id << 32;
3953                         i40e_debug(hw, I40E_DEBUG_INIT,
3954                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3955                                    (p->wr_csr_prot & 0xffff));
3956                         break;
3957                 case I40E_AQ_CAP_ID_NVM_MGMT:
3958                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3959                                 p->sec_rev_disabled = true;
3960                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3961                                 p->update_disabled = true;
3962                         break;
3963                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3964                         hw->num_wol_proxy_filters = (u16)number;
3965                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3966                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3967                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3968                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3969                         else
3970                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3971                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3972                         i40e_debug(hw, I40E_DEBUG_INIT,
3973                                    "HW Capability: WOL proxy filters = %d\n",
3974                                    hw->num_wol_proxy_filters);
3975                         break;
3976                 default:
3977                         break;
3978                 }
3979         }
3980
3981         if (p->fcoe)
3982                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3983
3984         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3985         p->fcoe = false;
3986
3987         /* count the enabled ports (aka the "not disabled" ports) */
3988         hw->num_ports = 0;
3989         for (i = 0; i < 4; i++) {
3990                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3991                 u64 port_cfg = 0;
3992
3993                 /* use AQ read to get the physical register offset instead
3994                  * of the port relative offset
3995                  */
3996                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3997                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3998                         hw->num_ports++;
3999         }
4000
4001         /* OCP cards case: if a mezz is removed the ethernet port is at
4002          * disabled state in PRTGEN_CNF register. Additional NVM read is
4003          * needed in order to check if we are dealing with OCP card.
4004          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4005          * physical ports results in wrong partition id calculation and thus
4006          * not supporting WoL.
4007          */
4008         if (hw->mac.type == I40E_MAC_X722) {
4009                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4010                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4011                                                   2 * I40E_SR_OCP_CFG_WORD0,
4012                                                   sizeof(ocp_cfg_word0),
4013                                                   &ocp_cfg_word0, true, NULL);
4014                         if (status == I40E_SUCCESS &&
4015                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4016                                 hw->num_ports = 4;
4017                         i40e_release_nvm(hw);
4018                 }
4019         }
4020
4021         valid_functions = p->valid_functions;
4022         num_functions = 0;
4023         while (valid_functions) {
4024                 if (valid_functions & 1)
4025                         num_functions++;
4026                 valid_functions >>= 1;
4027         }
4028
4029         /* partition id is 1-based, and functions are evenly spread
4030          * across the ports as partitions
4031          */
4032         if (hw->num_ports != 0) {
4033                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4034                 hw->num_partitions = num_functions / hw->num_ports;
4035         }
4036
4037         /* additional HW specific goodies that might
4038          * someday be HW version specific
4039          */
4040         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4041 }
4042
4043 /**
4044  * i40e_aq_discover_capabilities
4045  * @hw: pointer to the hw struct
4046  * @buff: a virtual buffer to hold the capabilities
4047  * @buff_size: Size of the virtual buffer
4048  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4049  * @list_type_opc: capabilities type to discover - pass in the command opcode
4050  * @cmd_details: pointer to command details structure or NULL
4051  *
4052  * Get the device capabilities descriptions from the firmware
4053  **/
4054 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4055                                 void *buff, u16 buff_size, u16 *data_size,
4056                                 enum i40e_admin_queue_opc list_type_opc,
4057                                 struct i40e_asq_cmd_details *cmd_details)
4058 {
4059         struct i40e_aqc_list_capabilites *cmd;
4060         struct i40e_aq_desc desc;
4061         enum i40e_status_code status = I40E_SUCCESS;
4062
4063         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4064
4065         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4066                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4067                 status = I40E_ERR_PARAM;
4068                 goto exit;
4069         }
4070
4071         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4072
4073         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4074         if (buff_size > I40E_AQ_LARGE_BUF)
4075                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4076
4077         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4078         *data_size = LE16_TO_CPU(desc.datalen);
4079
4080         if (status)
4081                 goto exit;
4082
4083         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4084                                          list_type_opc);
4085
4086 exit:
4087         return status;
4088 }
4089
4090 /**
4091  * i40e_aq_update_nvm
4092  * @hw: pointer to the hw struct
4093  * @module_pointer: module pointer location in words from the NVM beginning
4094  * @offset: byte offset from the module beginning
4095  * @length: length of the section to be written (in bytes from the offset)
4096  * @data: command buffer (size [bytes] = length)
4097  * @last_command: tells if this is the last command in a series
4098  * @preservation_flags: Preservation mode flags
4099  * @cmd_details: pointer to command details structure or NULL
4100  *
4101  * Update the NVM using the admin queue commands
4102  **/
4103 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4104                                 u32 offset, u16 length, void *data,
4105                                 bool last_command, u8 preservation_flags,
4106                                 struct i40e_asq_cmd_details *cmd_details)
4107 {
4108         struct i40e_aq_desc desc;
4109         struct i40e_aqc_nvm_update *cmd =
4110                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4111         enum i40e_status_code status;
4112
4113         DEBUGFUNC("i40e_aq_update_nvm");
4114
4115         /* In offset the highest byte must be zeroed. */
4116         if (offset & 0xFF000000) {
4117                 status = I40E_ERR_PARAM;
4118                 goto i40e_aq_update_nvm_exit;
4119         }
4120
4121         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4122
4123         /* If this is the last command in a series, set the proper flag. */
4124         if (last_command)
4125                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4126         if (hw->mac.type == I40E_MAC_X722) {
4127                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4128                         cmd->command_flags |=
4129                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4130                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4131                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4132                         cmd->command_flags |=
4133                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4134                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4135         }
4136         cmd->module_pointer = module_pointer;
4137         cmd->offset = CPU_TO_LE32(offset);
4138         cmd->length = CPU_TO_LE16(length);
4139
4140         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4141         if (length > I40E_AQ_LARGE_BUF)
4142                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4143
4144         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4145
4146 i40e_aq_update_nvm_exit:
4147         return status;
4148 }
4149
4150 /**
4151  * i40e_aq_nvm_progress
4152  * @hw: pointer to the hw struct
4153  * @progress: pointer to progress returned from AQ
4154  * @cmd_details: pointer to command details structure or NULL
4155  *
4156  * Gets progress of flash rearrangement process
4157  **/
4158 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4159                                 struct i40e_asq_cmd_details *cmd_details)
4160 {
4161         enum i40e_status_code status;
4162         struct i40e_aq_desc desc;
4163
4164         DEBUGFUNC("i40e_aq_nvm_progress");
4165
4166         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4167         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4168         *progress = desc.params.raw[0];
4169         return status;
4170 }
4171
4172 /**
4173  * i40e_aq_get_lldp_mib
4174  * @hw: pointer to the hw struct
4175  * @bridge_type: type of bridge requested
4176  * @mib_type: Local, Remote or both Local and Remote MIBs
4177  * @buff: pointer to a user supplied buffer to store the MIB block
4178  * @buff_size: size of the buffer (in bytes)
4179  * @local_len : length of the returned Local LLDP MIB
4180  * @remote_len: length of the returned Remote LLDP MIB
4181  * @cmd_details: pointer to command details structure or NULL
4182  *
4183  * Requests the complete LLDP MIB (entire packet).
4184  **/
4185 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4186                                 u8 mib_type, void *buff, u16 buff_size,
4187                                 u16 *local_len, u16 *remote_len,
4188                                 struct i40e_asq_cmd_details *cmd_details)
4189 {
4190         struct i40e_aq_desc desc;
4191         struct i40e_aqc_lldp_get_mib *cmd =
4192                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4193         struct i40e_aqc_lldp_get_mib *resp =
4194                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4195         enum i40e_status_code status;
4196
4197         if (buff_size == 0 || !buff)
4198                 return I40E_ERR_PARAM;
4199
4200         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4201         /* Indirect Command */
4202         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4203
4204         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4205         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4206                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4207
4208         desc.datalen = CPU_TO_LE16(buff_size);
4209
4210         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4211         if (buff_size > I40E_AQ_LARGE_BUF)
4212                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4213
4214         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4215         if (!status) {
4216                 if (local_len != NULL)
4217                         *local_len = LE16_TO_CPU(resp->local_len);
4218                 if (remote_len != NULL)
4219                         *remote_len = LE16_TO_CPU(resp->remote_len);
4220         }
4221
4222         return status;
4223 }
4224
4225  /**
4226  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4227  * @hw: pointer to the hw struct
4228  * @mib_type: Local, Remote or both Local and Remote MIBs
4229  * @buff: pointer to a user supplied buffer to store the MIB block
4230  * @buff_size: size of the buffer (in bytes)
4231  * @cmd_details: pointer to command details structure or NULL
4232  *
4233  * Set the LLDP MIB.
4234  **/
4235 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4236                                 u8 mib_type, void *buff, u16 buff_size,
4237                                 struct i40e_asq_cmd_details *cmd_details)
4238 {
4239         struct i40e_aq_desc desc;
4240         struct i40e_aqc_lldp_set_local_mib *cmd =
4241                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4242         enum i40e_status_code status;
4243
4244         if (buff_size == 0 || !buff)
4245                 return I40E_ERR_PARAM;
4246
4247         i40e_fill_default_direct_cmd_desc(&desc,
4248                                 i40e_aqc_opc_lldp_set_local_mib);
4249         /* Indirect Command */
4250         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4251         if (buff_size > I40E_AQ_LARGE_BUF)
4252                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4253         desc.datalen = CPU_TO_LE16(buff_size);
4254
4255         cmd->type = mib_type;
4256         cmd->length = CPU_TO_LE16(buff_size);
4257         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4258         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4259
4260         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4261         return status;
4262 }
4263
4264 /**
4265  * i40e_aq_cfg_lldp_mib_change_event
4266  * @hw: pointer to the hw struct
4267  * @enable_update: Enable or Disable event posting
4268  * @cmd_details: pointer to command details structure or NULL
4269  *
4270  * Enable or Disable posting of an event on ARQ when LLDP MIB
4271  * associated with the interface changes
4272  **/
4273 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4274                                 bool enable_update,
4275                                 struct i40e_asq_cmd_details *cmd_details)
4276 {
4277         struct i40e_aq_desc desc;
4278         struct i40e_aqc_lldp_update_mib *cmd =
4279                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4280         enum i40e_status_code status;
4281
4282         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4283
4284         if (!enable_update)
4285                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4286
4287         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4288
4289         return status;
4290 }
4291
4292 /**
4293  * i40e_aq_add_lldp_tlv
4294  * @hw: pointer to the hw struct
4295  * @bridge_type: type of bridge
4296  * @buff: buffer with TLV to add
4297  * @buff_size: length of the buffer
4298  * @tlv_len: length of the TLV to be added
4299  * @mib_len: length of the LLDP MIB returned in response
4300  * @cmd_details: pointer to command details structure or NULL
4301  *
4302  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4303  * it is responsibility of the caller to make sure that the TLV is not
4304  * already present in the LLDPDU.
4305  * In return firmware will write the complete LLDP MIB with the newly
4306  * added TLV in the response buffer.
4307  **/
4308 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4309                                 void *buff, u16 buff_size, u16 tlv_len,
4310                                 u16 *mib_len,
4311                                 struct i40e_asq_cmd_details *cmd_details)
4312 {
4313         struct i40e_aq_desc desc;
4314         struct i40e_aqc_lldp_add_tlv *cmd =
4315                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4316         enum i40e_status_code status;
4317
4318         if (buff_size == 0 || !buff || tlv_len == 0)
4319                 return I40E_ERR_PARAM;
4320
4321         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4322
4323         /* Indirect Command */
4324         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4325         if (buff_size > I40E_AQ_LARGE_BUF)
4326                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4327         desc.datalen = CPU_TO_LE16(buff_size);
4328
4329         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4330                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4331         cmd->len = CPU_TO_LE16(tlv_len);
4332
4333         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4334         if (!status) {
4335                 if (mib_len != NULL)
4336                         *mib_len = LE16_TO_CPU(desc.datalen);
4337         }
4338
4339         return status;
4340 }
4341
4342 /**
4343  * i40e_aq_update_lldp_tlv
4344  * @hw: pointer to the hw struct
4345  * @bridge_type: type of bridge
4346  * @buff: buffer with TLV to update
4347  * @buff_size: size of the buffer holding original and updated TLVs
4348  * @old_len: Length of the Original TLV
4349  * @new_len: Length of the Updated TLV
4350  * @offset: offset of the updated TLV in the buff
4351  * @mib_len: length of the returned LLDP MIB
4352  * @cmd_details: pointer to command details structure or NULL
4353  *
4354  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4355  * Firmware will place the complete LLDP MIB in response buffer with the
4356  * updated TLV.
4357  **/
4358 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4359                                 u8 bridge_type, void *buff, u16 buff_size,
4360                                 u16 old_len, u16 new_len, u16 offset,
4361                                 u16 *mib_len,
4362                                 struct i40e_asq_cmd_details *cmd_details)
4363 {
4364         struct i40e_aq_desc desc;
4365         struct i40e_aqc_lldp_update_tlv *cmd =
4366                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4367         enum i40e_status_code status;
4368
4369         if (buff_size == 0 || !buff || offset == 0 ||
4370             old_len == 0 || new_len == 0)
4371                 return I40E_ERR_PARAM;
4372
4373         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4374
4375         /* Indirect Command */
4376         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4377         if (buff_size > I40E_AQ_LARGE_BUF)
4378                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4379         desc.datalen = CPU_TO_LE16(buff_size);
4380
4381         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4382                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4383         cmd->old_len = CPU_TO_LE16(old_len);
4384         cmd->new_offset = CPU_TO_LE16(offset);
4385         cmd->new_len = CPU_TO_LE16(new_len);
4386
4387         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4388         if (!status) {
4389                 if (mib_len != NULL)
4390                         *mib_len = LE16_TO_CPU(desc.datalen);
4391         }
4392
4393         return status;
4394 }
4395
4396 /**
4397  * i40e_aq_delete_lldp_tlv
4398  * @hw: pointer to the hw struct
4399  * @bridge_type: type of bridge
4400  * @buff: pointer to a user supplied buffer that has the TLV
4401  * @buff_size: length of the buffer
4402  * @tlv_len: length of the TLV to be deleted
4403  * @mib_len: length of the returned LLDP MIB
4404  * @cmd_details: pointer to command details structure or NULL
4405  *
4406  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4407  * The firmware places the entire LLDP MIB in the response buffer.
4408  **/
4409 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4410                                 u8 bridge_type, void *buff, u16 buff_size,
4411                                 u16 tlv_len, u16 *mib_len,
4412                                 struct i40e_asq_cmd_details *cmd_details)
4413 {
4414         struct i40e_aq_desc desc;
4415         struct i40e_aqc_lldp_add_tlv *cmd =
4416                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4417         enum i40e_status_code status;
4418
4419         if (buff_size == 0 || !buff)
4420                 return I40E_ERR_PARAM;
4421
4422         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4423
4424         /* Indirect Command */
4425         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4426         if (buff_size > I40E_AQ_LARGE_BUF)
4427                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4428         desc.datalen = CPU_TO_LE16(buff_size);
4429         cmd->len = CPU_TO_LE16(tlv_len);
4430         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4431                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4432
4433         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4434         if (!status) {
4435                 if (mib_len != NULL)
4436                         *mib_len = LE16_TO_CPU(desc.datalen);
4437         }
4438
4439         return status;
4440 }
4441
4442 /**
4443  * i40e_aq_stop_lldp
4444  * @hw: pointer to the hw struct
4445  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4446  * @cmd_details: pointer to command details structure or NULL
4447  *
4448  * Stop or Shutdown the embedded LLDP Agent
4449  **/
4450 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4451                                 struct i40e_asq_cmd_details *cmd_details)
4452 {
4453         struct i40e_aq_desc desc;
4454         struct i40e_aqc_lldp_stop *cmd =
4455                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4456         enum i40e_status_code status;
4457
4458         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4459
4460         if (shutdown_agent)
4461                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4462
4463         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4464
4465         return status;
4466 }
4467
4468 /**
4469  * i40e_aq_start_lldp
4470  * @hw: pointer to the hw struct
4471  * @cmd_details: pointer to command details structure or NULL
4472  *
4473  * Start the embedded LLDP Agent on all ports.
4474  **/
4475 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4476                                 struct i40e_asq_cmd_details *cmd_details)
4477 {
4478         struct i40e_aq_desc desc;
4479         struct i40e_aqc_lldp_start *cmd =
4480                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4481         enum i40e_status_code status;
4482
4483         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4484
4485         cmd->command = I40E_AQ_LLDP_AGENT_START;
4486         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4487
4488         return status;
4489 }
4490
4491 /**
4492  * i40e_aq_set_dcb_parameters
4493  * @hw: pointer to the hw struct
4494  * @cmd_details: pointer to command details structure or NULL
4495  * @dcb_enable: True if DCB configuration needs to be applied
4496  *
4497  **/
4498 enum i40e_status_code
4499 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4500                            struct i40e_asq_cmd_details *cmd_details)
4501 {
4502         struct i40e_aq_desc desc;
4503         struct i40e_aqc_set_dcb_parameters *cmd =
4504                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4505         enum i40e_status_code status;
4506
4507         i40e_fill_default_direct_cmd_desc(&desc,
4508                                           i40e_aqc_opc_set_dcb_parameters);
4509
4510         if (dcb_enable) {
4511                 cmd->valid_flags = I40E_DCB_VALID;
4512                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4513         }
4514         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4515
4516         return status;
4517 }
4518
4519 /**
4520  * i40e_aq_get_cee_dcb_config
4521  * @hw: pointer to the hw struct
4522  * @buff: response buffer that stores CEE operational configuration
4523  * @buff_size: size of the buffer passed
4524  * @cmd_details: pointer to command details structure or NULL
4525  *
4526  * Get CEE DCBX mode operational configuration from firmware
4527  **/
4528 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4529                                 void *buff, u16 buff_size,
4530                                 struct i40e_asq_cmd_details *cmd_details)
4531 {
4532         struct i40e_aq_desc desc;
4533         enum i40e_status_code status;
4534
4535         if (buff_size == 0 || !buff)
4536                 return I40E_ERR_PARAM;
4537
4538         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4539
4540         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4541         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4542                                        cmd_details);
4543
4544         return status;
4545 }
4546
4547 /**
4548  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4549  * @hw: pointer to the hw struct
4550  * @start_agent: True if DCBx Agent needs to be Started
4551  *                              False if DCBx Agent needs to be Stopped
4552  * @cmd_details: pointer to command details structure or NULL
4553  *
4554  * Start/Stop the embedded dcbx Agent
4555  **/
4556 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4557                                 bool start_agent,
4558                                 struct i40e_asq_cmd_details *cmd_details)
4559 {
4560         struct i40e_aq_desc desc;
4561         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4562                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4563                                 &desc.params.raw;
4564         enum i40e_status_code status;
4565
4566         i40e_fill_default_direct_cmd_desc(&desc,
4567                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4568
4569         if (start_agent)
4570                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4571
4572         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4573
4574         return status;
4575 }
4576
4577 /**
4578  * i40e_aq_add_udp_tunnel
4579  * @hw: pointer to the hw struct
4580  * @udp_port: the UDP port to add in Host byte order
4581  * @protocol_index: protocol index type
4582  * @filter_index: pointer to filter index
4583  * @cmd_details: pointer to command details structure or NULL
4584  *
4585  * Note: Firmware expects the udp_port value to be in Little Endian format,
4586  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4587  * Little Endian order.
4588  **/
4589 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4590                                 u16 udp_port, u8 protocol_index,
4591                                 u8 *filter_index,
4592                                 struct i40e_asq_cmd_details *cmd_details)
4593 {
4594         struct i40e_aq_desc desc;
4595         struct i40e_aqc_add_udp_tunnel *cmd =
4596                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4597         struct i40e_aqc_del_udp_tunnel_completion *resp =
4598                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4599         enum i40e_status_code status;
4600
4601         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4602
4603         cmd->udp_port = CPU_TO_LE16(udp_port);
4604         cmd->protocol_type = protocol_index;
4605
4606         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4607
4608         if (!status && filter_index)
4609                 *filter_index = resp->index;
4610
4611         return status;
4612 }
4613
4614 /**
4615  * i40e_aq_del_udp_tunnel
4616  * @hw: pointer to the hw struct
4617  * @index: filter index
4618  * @cmd_details: pointer to command details structure or NULL
4619  **/
4620 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4621                                 struct i40e_asq_cmd_details *cmd_details)
4622 {
4623         struct i40e_aq_desc desc;
4624         struct i40e_aqc_remove_udp_tunnel *cmd =
4625                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4626         enum i40e_status_code status;
4627
4628         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4629
4630         cmd->index = index;
4631
4632         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4633
4634         return status;
4635 }
4636
4637 /**
4638  * i40e_aq_get_switch_resource_alloc (0x0204)
4639  * @hw: pointer to the hw struct
4640  * @num_entries: pointer to u8 to store the number of resource entries returned
4641  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4642  *        to store the resource information for all resource types.  Each
4643  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4644  * @count: size, in bytes, of the buffer provided
4645  * @cmd_details: pointer to command details structure or NULL
4646  *
4647  * Query the resources allocated to a function.
4648  **/
4649 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4650                         u8 *num_entries,
4651                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4652                         u16 count,
4653                         struct i40e_asq_cmd_details *cmd_details)
4654 {
4655         struct i40e_aq_desc desc;
4656         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4657                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4658         enum i40e_status_code status;
4659         u16 length = count * sizeof(*buf);
4660
4661         i40e_fill_default_direct_cmd_desc(&desc,
4662                                         i40e_aqc_opc_get_switch_resource_alloc);
4663
4664         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4665         if (length > I40E_AQ_LARGE_BUF)
4666                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4667
4668         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4669
4670         if (!status && num_entries)
4671                 *num_entries = cmd_resp->num_entries;
4672
4673         return status;
4674 }
4675
4676 /**
4677  * i40e_aq_delete_element - Delete switch element
4678  * @hw: pointer to the hw struct
4679  * @seid: the SEID to delete from the switch
4680  * @cmd_details: pointer to command details structure or NULL
4681  *
4682  * This deletes a switch element from the switch.
4683  **/
4684 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4685                                 struct i40e_asq_cmd_details *cmd_details)
4686 {
4687         struct i40e_aq_desc desc;
4688         struct i40e_aqc_switch_seid *cmd =
4689                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4690         enum i40e_status_code status;
4691
4692         if (seid == 0)
4693                 return I40E_ERR_PARAM;
4694
4695         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4696
4697         cmd->seid = CPU_TO_LE16(seid);
4698
4699         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4700
4701         return status;
4702 }
4703
4704 /**
4705  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4706  * @hw: pointer to the hw struct
4707  * @flags: component flags
4708  * @mac_seid: uplink seid (MAC SEID)
4709  * @vsi_seid: connected vsi seid
4710  * @ret_seid: seid of create pv component
4711  *
4712  * This instantiates an i40e port virtualizer with specified flags.
4713  * Depending on specified flags the port virtualizer can act as a
4714  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4715  */
4716 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4717                                        u16 mac_seid, u16 vsi_seid,
4718                                        u16 *ret_seid)
4719 {
4720         struct i40e_aq_desc desc;
4721         struct i40e_aqc_add_update_pv *cmd =
4722                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4723         struct i40e_aqc_add_update_pv_completion *resp =
4724                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4725         enum i40e_status_code status;
4726
4727         if (vsi_seid == 0)
4728                 return I40E_ERR_PARAM;
4729
4730         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4731         cmd->command_flags = CPU_TO_LE16(flags);
4732         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4733         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4734
4735         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4736         if (!status && ret_seid)
4737                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4738
4739         return status;
4740 }
4741
4742 /**
4743  * i40e_aq_add_tag - Add an S/E-tag
4744  * @hw: pointer to the hw struct
4745  * @direct_to_queue: should s-tag direct flow to a specific queue
4746  * @vsi_seid: VSI SEID to use this tag
4747  * @tag: value of the tag
4748  * @queue_num: queue number, only valid is direct_to_queue is true
4749  * @tags_used: return value, number of tags in use by this PF
4750  * @tags_free: return value, number of unallocated tags
4751  * @cmd_details: pointer to command details structure or NULL
4752  *
4753  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4754  * the number of tags allocated by the PF, and the number of unallocated
4755  * tags available.
4756  **/
4757 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4758                                 u16 vsi_seid, u16 tag, u16 queue_num,
4759                                 u16 *tags_used, u16 *tags_free,
4760                                 struct i40e_asq_cmd_details *cmd_details)
4761 {
4762         struct i40e_aq_desc desc;
4763         struct i40e_aqc_add_tag *cmd =
4764                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4765         struct i40e_aqc_add_remove_tag_completion *resp =
4766                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4767         enum i40e_status_code status;
4768
4769         if (vsi_seid == 0)
4770                 return I40E_ERR_PARAM;
4771
4772         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4773
4774         cmd->seid = CPU_TO_LE16(vsi_seid);
4775         cmd->tag = CPU_TO_LE16(tag);
4776         if (direct_to_queue) {
4777                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4778                 cmd->queue_number = CPU_TO_LE16(queue_num);
4779         }
4780
4781         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4782
4783         if (!status) {
4784                 if (tags_used != NULL)
4785                         *tags_used = LE16_TO_CPU(resp->tags_used);
4786                 if (tags_free != NULL)
4787                         *tags_free = LE16_TO_CPU(resp->tags_free);
4788         }
4789
4790         return status;
4791 }
4792
4793 /**
4794  * i40e_aq_remove_tag - Remove an S- or E-tag
4795  * @hw: pointer to the hw struct
4796  * @vsi_seid: VSI SEID this tag is associated with
4797  * @tag: value of the S-tag to delete
4798  * @tags_used: return value, number of tags in use by this PF
4799  * @tags_free: return value, number of unallocated tags
4800  * @cmd_details: pointer to command details structure or NULL
4801  *
4802  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4803  * the number of tags allocated by the PF, and the number of unallocated
4804  * tags available.
4805  **/
4806 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4807                                 u16 tag, u16 *tags_used, u16 *tags_free,
4808                                 struct i40e_asq_cmd_details *cmd_details)
4809 {
4810         struct i40e_aq_desc desc;
4811         struct i40e_aqc_remove_tag *cmd =
4812                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4813         struct i40e_aqc_add_remove_tag_completion *resp =
4814                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4815         enum i40e_status_code status;
4816
4817         if (vsi_seid == 0)
4818                 return I40E_ERR_PARAM;
4819
4820         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4821
4822         cmd->seid = CPU_TO_LE16(vsi_seid);
4823         cmd->tag = CPU_TO_LE16(tag);
4824
4825         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4826
4827         if (!status) {
4828                 if (tags_used != NULL)
4829                         *tags_used = LE16_TO_CPU(resp->tags_used);
4830                 if (tags_free != NULL)
4831                         *tags_free = LE16_TO_CPU(resp->tags_free);
4832         }
4833
4834         return status;
4835 }
4836
4837 /**
4838  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4839  * @hw: pointer to the hw struct
4840  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4841  * @etag: value of E-tag to add
4842  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4843  * @buf: address of indirect buffer
4844  * @tags_used: return value, number of E-tags in use by this port
4845  * @tags_free: return value, number of unallocated M-tags
4846  * @cmd_details: pointer to command details structure or NULL
4847  *
4848  * This associates a multicast E-tag to a port virtualizer.  It will return
4849  * the number of tags allocated by the PF, and the number of unallocated
4850  * tags available.
4851  *
4852  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4853  * num_tags_in_buf long.
4854  **/
4855 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4856                                 u16 etag, u8 num_tags_in_buf, void *buf,
4857                                 u16 *tags_used, u16 *tags_free,
4858                                 struct i40e_asq_cmd_details *cmd_details)
4859 {
4860         struct i40e_aq_desc desc;
4861         struct i40e_aqc_add_remove_mcast_etag *cmd =
4862                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4863         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4864            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4865         enum i40e_status_code status;
4866         u16 length = sizeof(u16) * num_tags_in_buf;
4867
4868         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4869                 return I40E_ERR_PARAM;
4870
4871         i40e_fill_default_direct_cmd_desc(&desc,
4872                                           i40e_aqc_opc_add_multicast_etag);
4873
4874         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4875         cmd->etag = CPU_TO_LE16(etag);
4876         cmd->num_unicast_etags = num_tags_in_buf;
4877
4878         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4879         if (length > I40E_AQ_LARGE_BUF)
4880                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4881
4882         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4883
4884         if (!status) {
4885                 if (tags_used != NULL)
4886                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4887                 if (tags_free != NULL)
4888                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4889         }
4890
4891         return status;
4892 }
4893
4894 /**
4895  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4896  * @hw: pointer to the hw struct
4897  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4898  * @etag: value of the E-tag to remove
4899  * @tags_used: return value, number of tags in use by this port
4900  * @tags_free: return value, number of unallocated tags
4901  * @cmd_details: pointer to command details structure or NULL
4902  *
4903  * This deletes an E-tag from the port virtualizer.  It will return
4904  * the number of tags allocated by the port, and the number of unallocated
4905  * tags available.
4906  **/
4907 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4908                                 u16 etag, u16 *tags_used, u16 *tags_free,
4909                                 struct i40e_asq_cmd_details *cmd_details)
4910 {
4911         struct i40e_aq_desc desc;
4912         struct i40e_aqc_add_remove_mcast_etag *cmd =
4913                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4914         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4915            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4916         enum i40e_status_code status;
4917
4918
4919         if (pv_seid == 0)
4920                 return I40E_ERR_PARAM;
4921
4922         i40e_fill_default_direct_cmd_desc(&desc,
4923                                           i40e_aqc_opc_remove_multicast_etag);
4924
4925         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4926         cmd->etag = CPU_TO_LE16(etag);
4927
4928         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4929
4930         if (!status) {
4931                 if (tags_used != NULL)
4932                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4933                 if (tags_free != NULL)
4934                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4935         }
4936
4937         return status;
4938 }
4939
4940 /**
4941  * i40e_aq_update_tag - Update an S/E-tag
4942  * @hw: pointer to the hw struct
4943  * @vsi_seid: VSI SEID using this S-tag
4944  * @old_tag: old tag value
4945  * @new_tag: new tag value
4946  * @tags_used: return value, number of tags in use by this PF
4947  * @tags_free: return value, number of unallocated tags
4948  * @cmd_details: pointer to command details structure or NULL
4949  *
4950  * This updates the value of the tag currently attached to this VSI
4951  * in the switch complex.  It will return the number of tags allocated
4952  * by the PF, and the number of unallocated tags available.
4953  **/
4954 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4955                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4956                                 u16 *tags_free,
4957                                 struct i40e_asq_cmd_details *cmd_details)
4958 {
4959         struct i40e_aq_desc desc;
4960         struct i40e_aqc_update_tag *cmd =
4961                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4962         struct i40e_aqc_update_tag_completion *resp =
4963                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4964         enum i40e_status_code status;
4965
4966         if (vsi_seid == 0)
4967                 return I40E_ERR_PARAM;
4968
4969         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4970
4971         cmd->seid = CPU_TO_LE16(vsi_seid);
4972         cmd->old_tag = CPU_TO_LE16(old_tag);
4973         cmd->new_tag = CPU_TO_LE16(new_tag);
4974
4975         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4976
4977         if (!status) {
4978                 if (tags_used != NULL)
4979                         *tags_used = LE16_TO_CPU(resp->tags_used);
4980                 if (tags_free != NULL)
4981                         *tags_free = LE16_TO_CPU(resp->tags_free);
4982         }
4983
4984         return status;
4985 }
4986
4987 /**
4988  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4989  * @hw: pointer to the hw struct
4990  * @tcmap: TC map for request/release any ignore PFC condition
4991  * @request: request or release ignore PFC condition
4992  * @tcmap_ret: return TCs for which PFC is currently ignored
4993  * @cmd_details: pointer to command details structure or NULL
4994  *
4995  * This sends out request/release to ignore PFC condition for a TC.
4996  * It will return the TCs for which PFC is currently ignored.
4997  **/
4998 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4999                                 bool request, u8 *tcmap_ret,
5000                                 struct i40e_asq_cmd_details *cmd_details)
5001 {
5002         struct i40e_aq_desc desc;
5003         struct i40e_aqc_pfc_ignore *cmd_resp =
5004                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5005         enum i40e_status_code status;
5006
5007         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5008
5009         if (request)
5010                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5011
5012         cmd_resp->tc_bitmap = tcmap;
5013
5014         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5015
5016         if (!status) {
5017                 if (tcmap_ret != NULL)
5018                         *tcmap_ret = cmd_resp->tc_bitmap;
5019         }
5020
5021         return status;
5022 }
5023
5024 /**
5025  * i40e_aq_dcb_updated - DCB Updated Command
5026  * @hw: pointer to the hw struct
5027  * @cmd_details: pointer to command details structure or NULL
5028  *
5029  * When LLDP is handled in PF this command is used by the PF
5030  * to notify EMP that a DCB setting is modified.
5031  * When LLDP is handled in EMP this command is used by the PF
5032  * to notify EMP whenever one of the following parameters get
5033  * modified:
5034  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5035  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5036  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5037  * EMP will return when the shared RPB settings have been
5038  * recomputed and modified. The retval field in the descriptor
5039  * will be set to 0 when RPB is modified.
5040  **/
5041 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5042                                 struct i40e_asq_cmd_details *cmd_details)
5043 {
5044         struct i40e_aq_desc desc;
5045         enum i40e_status_code status;
5046
5047         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5048
5049         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5050
5051         return status;
5052 }
5053
5054 /**
5055  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5056  * @hw: pointer to the hw struct
5057  * @seid: defines the SEID of the switch for which the stats are requested
5058  * @vlan_id: the VLAN ID for which the statistics are requested
5059  * @stat_index: index of the statistics counters block assigned to this VLAN
5060  * @cmd_details: pointer to command details structure or NULL
5061  *
5062  * XL710 supports 128 smonVlanStats counters.This command is used to
5063  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5064  * switch.
5065  **/
5066 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5067                                 u16 vlan_id, u16 *stat_index,
5068                                 struct i40e_asq_cmd_details *cmd_details)
5069 {
5070         struct i40e_aq_desc desc;
5071         struct i40e_aqc_add_remove_statistics *cmd_resp =
5072                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5073         enum i40e_status_code status;
5074
5075         if ((seid == 0) || (stat_index == NULL))
5076                 return I40E_ERR_PARAM;
5077
5078         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5079
5080         cmd_resp->seid = CPU_TO_LE16(seid);
5081         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5082
5083         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5084
5085         if (!status && stat_index)
5086                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5087
5088         return status;
5089 }
5090
5091 /**
5092  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5093  * @hw: pointer to the hw struct
5094  * @seid: defines the SEID of the switch for which the stats are requested
5095  * @vlan_id: the VLAN ID for which the statistics are requested
5096  * @stat_index: index of the statistics counters block assigned to this VLAN
5097  * @cmd_details: pointer to command details structure or NULL
5098  *
5099  * XL710 supports 128 smonVlanStats counters.This command is used to
5100  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5101  * switch.
5102  **/
5103 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5104                                 u16 vlan_id, u16 stat_index,
5105                                 struct i40e_asq_cmd_details *cmd_details)
5106 {
5107         struct i40e_aq_desc desc;
5108         struct i40e_aqc_add_remove_statistics *cmd =
5109                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5110         enum i40e_status_code status;
5111
5112         if (seid == 0)
5113                 return I40E_ERR_PARAM;
5114
5115         i40e_fill_default_direct_cmd_desc(&desc,
5116                                           i40e_aqc_opc_remove_statistics);
5117
5118         cmd->seid = CPU_TO_LE16(seid);
5119         cmd->vlan  = CPU_TO_LE16(vlan_id);
5120         cmd->stat_index = CPU_TO_LE16(stat_index);
5121
5122         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5123
5124         return status;
5125 }
5126
5127 /**
5128  * i40e_aq_set_port_parameters - set physical port parameters.
5129  * @hw: pointer to the hw struct
5130  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5131  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5132  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5133  * @double_vlan: if set double VLAN is enabled
5134  * @cmd_details: pointer to command details structure or NULL
5135  **/
5136 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5137                                 u16 bad_frame_vsi, bool save_bad_pac,
5138                                 bool pad_short_pac, bool double_vlan,
5139                                 struct i40e_asq_cmd_details *cmd_details)
5140 {
5141         struct i40e_aqc_set_port_parameters *cmd;
5142         enum i40e_status_code status;
5143         struct i40e_aq_desc desc;
5144         u16 command_flags = 0;
5145
5146         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5147
5148         i40e_fill_default_direct_cmd_desc(&desc,
5149                                           i40e_aqc_opc_set_port_parameters);
5150
5151         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5152         if (save_bad_pac)
5153                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5154         if (pad_short_pac)
5155                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5156         if (double_vlan)
5157                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5158         cmd->command_flags = CPU_TO_LE16(command_flags);
5159
5160         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5161
5162         return status;
5163 }
5164
5165 /**
5166  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5167  * @hw: pointer to the hw struct
5168  * @seid: seid for the physical port/switching component/vsi
5169  * @buff: Indirect buffer to hold data parameters and response
5170  * @buff_size: Indirect buffer size
5171  * @opcode: Tx scheduler AQ command opcode
5172  * @cmd_details: pointer to command details structure or NULL
5173  *
5174  * Generic command handler for Tx scheduler AQ commands
5175  **/
5176 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5177                                 void *buff, u16 buff_size,
5178                                  enum i40e_admin_queue_opc opcode,
5179                                 struct i40e_asq_cmd_details *cmd_details)
5180 {
5181         struct i40e_aq_desc desc;
5182         struct i40e_aqc_tx_sched_ind *cmd =
5183                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5184         enum i40e_status_code status;
5185         bool cmd_param_flag = false;
5186
5187         switch (opcode) {
5188         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5189         case i40e_aqc_opc_configure_vsi_tc_bw:
5190         case i40e_aqc_opc_enable_switching_comp_ets:
5191         case i40e_aqc_opc_modify_switching_comp_ets:
5192         case i40e_aqc_opc_disable_switching_comp_ets:
5193         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5194         case i40e_aqc_opc_configure_switching_comp_bw_config:
5195                 cmd_param_flag = true;
5196                 break;
5197         case i40e_aqc_opc_query_vsi_bw_config:
5198         case i40e_aqc_opc_query_vsi_ets_sla_config:
5199         case i40e_aqc_opc_query_switching_comp_ets_config:
5200         case i40e_aqc_opc_query_port_ets_config:
5201         case i40e_aqc_opc_query_switching_comp_bw_config:
5202                 cmd_param_flag = false;
5203                 break;
5204         default:
5205                 return I40E_ERR_PARAM;
5206         }
5207
5208         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5209
5210         /* Indirect command */
5211         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5212         if (cmd_param_flag)
5213                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5214         if (buff_size > I40E_AQ_LARGE_BUF)
5215                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5216
5217         desc.datalen = CPU_TO_LE16(buff_size);
5218
5219         cmd->vsi_seid = CPU_TO_LE16(seid);
5220
5221         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5222
5223         return status;
5224 }
5225
5226 /**
5227  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5228  * @hw: pointer to the hw struct
5229  * @seid: VSI seid
5230  * @credit: BW limit credits (0 = disabled)
5231  * @max_credit: Max BW limit credits
5232  * @cmd_details: pointer to command details structure or NULL
5233  **/
5234 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5235                                 u16 seid, u16 credit, u8 max_credit,
5236                                 struct i40e_asq_cmd_details *cmd_details)
5237 {
5238         struct i40e_aq_desc desc;
5239         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5240                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5241         enum i40e_status_code status;
5242
5243         i40e_fill_default_direct_cmd_desc(&desc,
5244                                           i40e_aqc_opc_configure_vsi_bw_limit);
5245
5246         cmd->vsi_seid = CPU_TO_LE16(seid);
5247         cmd->credit = CPU_TO_LE16(credit);
5248         cmd->max_credit = max_credit;
5249
5250         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5251
5252         return status;
5253 }
5254
5255 /**
5256  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5257  * @hw: pointer to the hw struct
5258  * @seid: switching component seid
5259  * @credit: BW limit credits (0 = disabled)
5260  * @max_bw: Max BW limit credits
5261  * @cmd_details: pointer to command details structure or NULL
5262  **/
5263 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5264                                 u16 seid, u16 credit, u8 max_bw,
5265                                 struct i40e_asq_cmd_details *cmd_details)
5266 {
5267         struct i40e_aq_desc desc;
5268         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5269           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5270         enum i40e_status_code status;
5271
5272         i40e_fill_default_direct_cmd_desc(&desc,
5273                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5274
5275         cmd->seid = CPU_TO_LE16(seid);
5276         cmd->credit = CPU_TO_LE16(credit);
5277         cmd->max_bw = max_bw;
5278
5279         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5280
5281         return status;
5282 }
5283
5284 /**
5285  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5286  * @hw: pointer to the hw struct
5287  * @seid: VSI seid
5288  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5289  * @cmd_details: pointer to command details structure or NULL
5290  **/
5291 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5292                         u16 seid,
5293                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5294                         struct i40e_asq_cmd_details *cmd_details)
5295 {
5296         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5297                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5298                                     cmd_details);
5299 }
5300
5301 /**
5302  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5303  * @hw: pointer to the hw struct
5304  * @seid: VSI seid
5305  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5306  * @cmd_details: pointer to command details structure or NULL
5307  **/
5308 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5309                         u16 seid,
5310                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5311                         struct i40e_asq_cmd_details *cmd_details)
5312 {
5313         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5314                                     i40e_aqc_opc_configure_vsi_tc_bw,
5315                                     cmd_details);
5316 }
5317
5318 /**
5319  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5320  * @hw: pointer to the hw struct
5321  * @seid: seid of the switching component connected to Physical Port
5322  * @ets_data: Buffer holding ETS parameters
5323  * @opcode: Tx scheduler AQ command opcode
5324  * @cmd_details: pointer to command details structure or NULL
5325  **/
5326 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5327                 u16 seid,
5328                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5329                 enum i40e_admin_queue_opc opcode,
5330                 struct i40e_asq_cmd_details *cmd_details)
5331 {
5332         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5333                                     sizeof(*ets_data), opcode, cmd_details);
5334 }
5335
5336 /**
5337  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5338  * @hw: pointer to the hw struct
5339  * @seid: seid of the switching component
5340  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5341  * @cmd_details: pointer to command details structure or NULL
5342  **/
5343 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5344         u16 seid,
5345         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5346         struct i40e_asq_cmd_details *cmd_details)
5347 {
5348         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5349                             i40e_aqc_opc_configure_switching_comp_bw_config,
5350                             cmd_details);
5351 }
5352
5353 /**
5354  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5355  * @hw: pointer to the hw struct
5356  * @seid: seid of the switching component
5357  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5358  * @cmd_details: pointer to command details structure or NULL
5359  **/
5360 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5361         struct i40e_hw *hw, u16 seid,
5362         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5363         struct i40e_asq_cmd_details *cmd_details)
5364 {
5365         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5366                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5367                             cmd_details);
5368 }
5369
5370 /**
5371  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5372  * @hw: pointer to the hw struct
5373  * @seid: seid of the VSI
5374  * @bw_data: Buffer to hold VSI BW configuration
5375  * @cmd_details: pointer to command details structure or NULL
5376  **/
5377 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5378                         u16 seid,
5379                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5380                         struct i40e_asq_cmd_details *cmd_details)
5381 {
5382         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5383                                     i40e_aqc_opc_query_vsi_bw_config,
5384                                     cmd_details);
5385 }
5386
5387 /**
5388  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5389  * @hw: pointer to the hw struct
5390  * @seid: seid of the VSI
5391  * @bw_data: Buffer to hold VSI BW configuration per TC
5392  * @cmd_details: pointer to command details structure or NULL
5393  **/
5394 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5395                         u16 seid,
5396                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5397                         struct i40e_asq_cmd_details *cmd_details)
5398 {
5399         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5400                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5401                                     cmd_details);
5402 }
5403
5404 /**
5405  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5406  * @hw: pointer to the hw struct
5407  * @seid: seid of the switching component
5408  * @bw_data: Buffer to hold switching component's per TC BW config
5409  * @cmd_details: pointer to command details structure or NULL
5410  **/
5411 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5412                 u16 seid,
5413                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5414                 struct i40e_asq_cmd_details *cmd_details)
5415 {
5416         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5417                                    i40e_aqc_opc_query_switching_comp_ets_config,
5418                                    cmd_details);
5419 }
5420
5421 /**
5422  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5423  * @hw: pointer to the hw struct
5424  * @seid: seid of the VSI or switching component connected to Physical Port
5425  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5426  * @cmd_details: pointer to command details structure or NULL
5427  **/
5428 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5429                         u16 seid,
5430                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5431                         struct i40e_asq_cmd_details *cmd_details)
5432 {
5433         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5434                                     i40e_aqc_opc_query_port_ets_config,
5435                                     cmd_details);
5436 }
5437
5438 /**
5439  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5440  * @hw: pointer to the hw struct
5441  * @seid: seid of the switching component
5442  * @bw_data: Buffer to hold switching component's BW configuration
5443  * @cmd_details: pointer to command details structure or NULL
5444  **/
5445 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5446                 u16 seid,
5447                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5448                 struct i40e_asq_cmd_details *cmd_details)
5449 {
5450         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5451                                     i40e_aqc_opc_query_switching_comp_bw_config,
5452                                     cmd_details);
5453 }
5454
5455 /**
5456  * i40e_validate_filter_settings
5457  * @hw: pointer to the hardware structure
5458  * @settings: Filter control settings
5459  *
5460  * Check and validate the filter control settings passed.
5461  * The function checks for the valid filter/context sizes being
5462  * passed for FCoE and PE.
5463  *
5464  * Returns I40E_SUCCESS if the values passed are valid and within
5465  * range else returns an error.
5466  **/
5467 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5468                                 struct i40e_filter_control_settings *settings)
5469 {
5470         u32 fcoe_cntx_size, fcoe_filt_size;
5471         u32 pe_cntx_size, pe_filt_size;
5472         u32 fcoe_fmax;
5473
5474         u32 val;
5475
5476         /* Validate FCoE settings passed */
5477         switch (settings->fcoe_filt_num) {
5478         case I40E_HASH_FILTER_SIZE_1K:
5479         case I40E_HASH_FILTER_SIZE_2K:
5480         case I40E_HASH_FILTER_SIZE_4K:
5481         case I40E_HASH_FILTER_SIZE_8K:
5482         case I40E_HASH_FILTER_SIZE_16K:
5483         case I40E_HASH_FILTER_SIZE_32K:
5484                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5485                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5486                 break;
5487         default:
5488                 return I40E_ERR_PARAM;
5489         }
5490
5491         switch (settings->fcoe_cntx_num) {
5492         case I40E_DMA_CNTX_SIZE_512:
5493         case I40E_DMA_CNTX_SIZE_1K:
5494         case I40E_DMA_CNTX_SIZE_2K:
5495         case I40E_DMA_CNTX_SIZE_4K:
5496                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5497                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5498                 break;
5499         default:
5500                 return I40E_ERR_PARAM;
5501         }
5502
5503         /* Validate PE settings passed */
5504         switch (settings->pe_filt_num) {
5505         case I40E_HASH_FILTER_SIZE_1K:
5506         case I40E_HASH_FILTER_SIZE_2K:
5507         case I40E_HASH_FILTER_SIZE_4K:
5508         case I40E_HASH_FILTER_SIZE_8K:
5509         case I40E_HASH_FILTER_SIZE_16K:
5510         case I40E_HASH_FILTER_SIZE_32K:
5511         case I40E_HASH_FILTER_SIZE_64K:
5512         case I40E_HASH_FILTER_SIZE_128K:
5513         case I40E_HASH_FILTER_SIZE_256K:
5514         case I40E_HASH_FILTER_SIZE_512K:
5515         case I40E_HASH_FILTER_SIZE_1M:
5516                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5517                 pe_filt_size <<= (u32)settings->pe_filt_num;
5518                 break;
5519         default:
5520                 return I40E_ERR_PARAM;
5521         }
5522
5523         switch (settings->pe_cntx_num) {
5524         case I40E_DMA_CNTX_SIZE_512:
5525         case I40E_DMA_CNTX_SIZE_1K:
5526         case I40E_DMA_CNTX_SIZE_2K:
5527         case I40E_DMA_CNTX_SIZE_4K:
5528         case I40E_DMA_CNTX_SIZE_8K:
5529         case I40E_DMA_CNTX_SIZE_16K:
5530         case I40E_DMA_CNTX_SIZE_32K:
5531         case I40E_DMA_CNTX_SIZE_64K:
5532         case I40E_DMA_CNTX_SIZE_128K:
5533         case I40E_DMA_CNTX_SIZE_256K:
5534                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5535                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5536                 break;
5537         default:
5538                 return I40E_ERR_PARAM;
5539         }
5540
5541         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5542         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5543         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5544                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5545         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5546                 return I40E_ERR_INVALID_SIZE;
5547
5548         return I40E_SUCCESS;
5549 }
5550
5551 /**
5552  * i40e_set_filter_control
5553  * @hw: pointer to the hardware structure
5554  * @settings: Filter control settings
5555  *
5556  * Set the Queue Filters for PE/FCoE and enable filters required
5557  * for a single PF. It is expected that these settings are programmed
5558  * at the driver initialization time.
5559  **/
5560 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5561                                 struct i40e_filter_control_settings *settings)
5562 {
5563         enum i40e_status_code ret = I40E_SUCCESS;
5564         u32 hash_lut_size = 0;
5565         u32 val;
5566
5567         if (!settings)
5568                 return I40E_ERR_PARAM;
5569
5570         /* Validate the input settings */
5571         ret = i40e_validate_filter_settings(hw, settings);
5572         if (ret)
5573                 return ret;
5574
5575         /* Read the PF Queue Filter control register */
5576         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5577
5578         /* Program required PE hash buckets for the PF */
5579         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5580         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5581                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5582         /* Program required PE contexts for the PF */
5583         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5584         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5585                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5586
5587         /* Program required FCoE hash buckets for the PF */
5588         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5589         val |= ((u32)settings->fcoe_filt_num <<
5590                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5591                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5592         /* Program required FCoE DDP contexts for the PF */
5593         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5594         val |= ((u32)settings->fcoe_cntx_num <<
5595                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5596                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5597
5598         /* Program Hash LUT size for the PF */
5599         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5600         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5601                 hash_lut_size = 1;
5602         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5603                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5604
5605         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5606         if (settings->enable_fdir)
5607                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5608         if (settings->enable_ethtype)
5609                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5610         if (settings->enable_macvlan)
5611                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5612
5613         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5614
5615         return I40E_SUCCESS;
5616 }
5617
5618 /**
5619  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5620  * @hw: pointer to the hw struct
5621  * @mac_addr: MAC address to use in the filter
5622  * @ethtype: Ethertype to use in the filter
5623  * @flags: Flags that needs to be applied to the filter
5624  * @vsi_seid: seid of the control VSI
5625  * @queue: VSI queue number to send the packet to
5626  * @is_add: Add control packet filter if True else remove
5627  * @stats: Structure to hold information on control filter counts
5628  * @cmd_details: pointer to command details structure or NULL
5629  *
5630  * This command will Add or Remove control packet filter for a control VSI.
5631  * In return it will update the total number of perfect filter count in
5632  * the stats member.
5633  **/
5634 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5635                                 u8 *mac_addr, u16 ethtype, u16 flags,
5636                                 u16 vsi_seid, u16 queue, bool is_add,
5637                                 struct i40e_control_filter_stats *stats,
5638                                 struct i40e_asq_cmd_details *cmd_details)
5639 {
5640         struct i40e_aq_desc desc;
5641         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5642                 (struct i40e_aqc_add_remove_control_packet_filter *)
5643                 &desc.params.raw;
5644         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5645                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5646                 &desc.params.raw;
5647         enum i40e_status_code status;
5648
5649         if (vsi_seid == 0)
5650                 return I40E_ERR_PARAM;
5651
5652         if (is_add) {
5653                 i40e_fill_default_direct_cmd_desc(&desc,
5654                                 i40e_aqc_opc_add_control_packet_filter);
5655                 cmd->queue = CPU_TO_LE16(queue);
5656         } else {
5657                 i40e_fill_default_direct_cmd_desc(&desc,
5658                                 i40e_aqc_opc_remove_control_packet_filter);
5659         }
5660
5661         if (mac_addr)
5662                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5663                             I40E_NONDMA_TO_NONDMA);
5664
5665         cmd->etype = CPU_TO_LE16(ethtype);
5666         cmd->flags = CPU_TO_LE16(flags);
5667         cmd->seid = CPU_TO_LE16(vsi_seid);
5668
5669         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5670
5671         if (!status && stats) {
5672                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5673                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5674                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5675                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5676         }
5677
5678         return status;
5679 }
5680
5681 /**
5682  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5683  * @hw: pointer to the hw struct
5684  * @seid: VSI seid to add ethertype filter from
5685  **/
5686 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5687                                                     u16 seid)
5688 {
5689 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5690         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5691                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5692                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5693         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5694         enum i40e_status_code status;
5695
5696         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5697                                                        seid, 0, true, NULL,
5698                                                        NULL);
5699         if (status)
5700                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5701 }
5702
5703 /**
5704  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5705  * @filters: list of cloud filters
5706  * @filter_count: length of list
5707  *
5708  * There's an issue in the device where the Geneve VNI layout needs
5709  * to be shifted 1 byte over from the VxLAN VNI
5710  **/
5711 STATIC void i40e_fix_up_geneve_vni(
5712         struct i40e_aqc_cloud_filters_element_data *filters,
5713         u8 filter_count)
5714 {
5715         struct i40e_aqc_cloud_filters_element_data *f = filters;
5716         int i;
5717
5718         for (i = 0; i < filter_count; i++) {
5719                 u16 tnl_type;
5720                 u32 ti;
5721
5722                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5723                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5724                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5725                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5726                         ti = LE32_TO_CPU(f[i].tenant_id);
5727                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5728                 }
5729         }
5730 }
5731
5732 /**
5733  * i40e_aq_add_cloud_filters
5734  * @hw: pointer to the hardware structure
5735  * @seid: VSI seid to add cloud filters from
5736  * @filters: Buffer which contains the filters to be added
5737  * @filter_count: number of filters contained in the buffer
5738  *
5739  * Set the cloud filters for a given VSI.  The contents of the
5740  * i40e_aqc_cloud_filters_element_data are filled
5741  * in by the caller of the function.
5742  *
5743  **/
5744 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5745         u16 seid,
5746         struct i40e_aqc_cloud_filters_element_data *filters,
5747         u8 filter_count)
5748 {
5749         struct i40e_aq_desc desc;
5750         struct i40e_aqc_add_remove_cloud_filters *cmd =
5751         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5752         enum i40e_status_code status;
5753         u16 buff_len;
5754
5755         i40e_fill_default_direct_cmd_desc(&desc,
5756                                           i40e_aqc_opc_add_cloud_filters);
5757
5758         buff_len = filter_count * sizeof(*filters);
5759         desc.datalen = CPU_TO_LE16(buff_len);
5760         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5761         cmd->num_filters = filter_count;
5762         cmd->seid = CPU_TO_LE16(seid);
5763
5764         i40e_fix_up_geneve_vni(filters, filter_count);
5765
5766         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5767
5768         return status;
5769 }
5770
5771 /**
5772  * i40e_aq_add_cloud_filters_bb
5773  * @hw: pointer to the hardware structure
5774  * @seid: VSI seid to add cloud filters from
5775  * @filters: Buffer which contains the filters in big buffer to be added
5776  * @filter_count: number of filters contained in the buffer
5777  *
5778  * Set the cloud filters for a given VSI.  The contents of the
5779  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5780  * the function.
5781  *
5782  **/
5783 enum i40e_status_code
5784 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5785                              struct i40e_aqc_cloud_filters_element_bb *filters,
5786                              u8 filter_count)
5787 {
5788         struct i40e_aq_desc desc;
5789         struct i40e_aqc_add_remove_cloud_filters *cmd =
5790         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5791         enum i40e_status_code status;
5792         u16 buff_len;
5793         int i;
5794
5795         i40e_fill_default_direct_cmd_desc(&desc,
5796                                           i40e_aqc_opc_add_cloud_filters);
5797
5798         buff_len = filter_count * sizeof(*filters);
5799         desc.datalen = CPU_TO_LE16(buff_len);
5800         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5801         cmd->num_filters = filter_count;
5802         cmd->seid = CPU_TO_LE16(seid);
5803         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5804
5805         for (i = 0; i < filter_count; i++) {
5806                 u16 tnl_type;
5807                 u32 ti;
5808
5809                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5810                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5811                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5812
5813                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5814                  * one more byte further than normally used for Tenant ID in
5815                  * other tunnel types.
5816                  */
5817                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5818                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5819                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5820                 }
5821         }
5822
5823         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5824
5825         return status;
5826 }
5827
5828 /**
5829  * i40e_aq_rem_cloud_filters
5830  * @hw: pointer to the hardware structure
5831  * @seid: VSI seid to remove cloud filters from
5832  * @filters: Buffer which contains the filters to be removed
5833  * @filter_count: number of filters contained in the buffer
5834  *
5835  * Remove the cloud filters for a given VSI.  The contents of the
5836  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5837  * of the function.
5838  *
5839  **/
5840 enum i40e_status_code
5841 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5842                           struct i40e_aqc_cloud_filters_element_data *filters,
5843                           u8 filter_count)
5844 {
5845         struct i40e_aq_desc desc;
5846         struct i40e_aqc_add_remove_cloud_filters *cmd =
5847         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5848         enum i40e_status_code status;
5849         u16 buff_len;
5850
5851         i40e_fill_default_direct_cmd_desc(&desc,
5852                                           i40e_aqc_opc_remove_cloud_filters);
5853
5854         buff_len = filter_count * sizeof(*filters);
5855         desc.datalen = CPU_TO_LE16(buff_len);
5856         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5857         cmd->num_filters = filter_count;
5858         cmd->seid = CPU_TO_LE16(seid);
5859
5860         i40e_fix_up_geneve_vni(filters, filter_count);
5861
5862         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5863
5864         return status;
5865 }
5866
5867 /**
5868  * i40e_aq_rem_cloud_filters_bb
5869  * @hw: pointer to the hardware structure
5870  * @seid: VSI seid to remove cloud filters from
5871  * @filters: Buffer which contains the filters in big buffer to be removed
5872  * @filter_count: number of filters contained in the buffer
5873  *
5874  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5875  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5876  * function.
5877  *
5878  **/
5879 enum i40e_status_code
5880 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5881                              struct i40e_aqc_cloud_filters_element_bb *filters,
5882                              u8 filter_count)
5883 {
5884         struct i40e_aq_desc desc;
5885         struct i40e_aqc_add_remove_cloud_filters *cmd =
5886         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5887         enum i40e_status_code status;
5888         u16 buff_len;
5889         int i;
5890
5891         i40e_fill_default_direct_cmd_desc(&desc,
5892                                           i40e_aqc_opc_remove_cloud_filters);
5893
5894         buff_len = filter_count * sizeof(*filters);
5895         desc.datalen = CPU_TO_LE16(buff_len);
5896         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5897         cmd->num_filters = filter_count;
5898         cmd->seid = CPU_TO_LE16(seid);
5899         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5900
5901         for (i = 0; i < filter_count; i++) {
5902                 u16 tnl_type;
5903                 u32 ti;
5904
5905                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5906                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5907                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5908
5909                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5910                  * one more byte further than normally used for Tenant ID in
5911                  * other tunnel types.
5912                  */
5913                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5914                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5915                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5916                 }
5917         }
5918
5919         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5920
5921         return status;
5922 }
5923
5924 /**
5925  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5926  * @hw: pointer to the hw struct
5927  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5928  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5929  *
5930  **/
5931 enum
5932 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5933         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5934         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5935 {
5936         struct i40e_aq_desc desc;
5937         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5938                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5939         enum i40e_status_code status = I40E_SUCCESS;
5940         int i = 0;
5941
5942         i40e_fill_default_direct_cmd_desc(&desc,
5943                                           i40e_aqc_opc_replace_cloud_filters);
5944
5945         desc.datalen = CPU_TO_LE16(32);
5946         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5947         cmd->old_filter_type = filters->old_filter_type;
5948         cmd->new_filter_type = filters->new_filter_type;
5949         cmd->valid_flags = filters->valid_flags;
5950         cmd->tr_bit = filters->tr_bit;
5951
5952         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5953                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5954
5955         /* for get cloud filters command */
5956         for (i = 0; i < 32; i += 4) {
5957                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5958                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5959                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5960                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5961         }
5962
5963         return status;
5964 }
5965
5966
5967 /**
5968  * i40e_aq_alternate_write
5969  * @hw: pointer to the hardware structure
5970  * @reg_addr0: address of first dword to be read
5971  * @reg_val0: value to be written under 'reg_addr0'
5972  * @reg_addr1: address of second dword to be read
5973  * @reg_val1: value to be written under 'reg_addr1'
5974  *
5975  * Write one or two dwords to alternate structure. Fields are indicated
5976  * by 'reg_addr0' and 'reg_addr1' register numbers.
5977  *
5978  **/
5979 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5980                                 u32 reg_addr0, u32 reg_val0,
5981                                 u32 reg_addr1, u32 reg_val1)
5982 {
5983         struct i40e_aq_desc desc;
5984         struct i40e_aqc_alternate_write *cmd_resp =
5985                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5986         enum i40e_status_code status;
5987
5988         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5989         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5990         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5991         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5992         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5993
5994         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5995
5996         return status;
5997 }
5998
5999 /**
6000  * i40e_aq_alternate_write_indirect
6001  * @hw: pointer to the hardware structure
6002  * @addr: address of a first register to be modified
6003  * @dw_count: number of alternate structure fields to write
6004  * @buffer: pointer to the command buffer
6005  *
6006  * Write 'dw_count' dwords from 'buffer' to alternate structure
6007  * starting at 'addr'.
6008  *
6009  **/
6010 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6011                                 u32 addr, u32 dw_count, void *buffer)
6012 {
6013         struct i40e_aq_desc desc;
6014         struct i40e_aqc_alternate_ind_write *cmd_resp =
6015                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6016         enum i40e_status_code status;
6017
6018         if (buffer == NULL)
6019                 return I40E_ERR_PARAM;
6020
6021         /* Indirect command */
6022         i40e_fill_default_direct_cmd_desc(&desc,
6023                                          i40e_aqc_opc_alternate_write_indirect);
6024
6025         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6026         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6027         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6028                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6029
6030         cmd_resp->address = CPU_TO_LE32(addr);
6031         cmd_resp->length = CPU_TO_LE32(dw_count);
6032
6033         status = i40e_asq_send_command(hw, &desc, buffer,
6034                                        I40E_LO_DWORD(4*dw_count), NULL);
6035
6036         return status;
6037 }
6038
6039 /**
6040  * i40e_aq_alternate_read
6041  * @hw: pointer to the hardware structure
6042  * @reg_addr0: address of first dword to be read
6043  * @reg_val0: pointer for data read from 'reg_addr0'
6044  * @reg_addr1: address of second dword to be read
6045  * @reg_val1: pointer for data read from 'reg_addr1'
6046  *
6047  * Read one or two dwords from alternate structure. Fields are indicated
6048  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6049  * is not passed then only register at 'reg_addr0' is read.
6050  *
6051  **/
6052 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6053                                 u32 reg_addr0, u32 *reg_val0,
6054                                 u32 reg_addr1, u32 *reg_val1)
6055 {
6056         struct i40e_aq_desc desc;
6057         struct i40e_aqc_alternate_write *cmd_resp =
6058                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6059         enum i40e_status_code status;
6060
6061         if (reg_val0 == NULL)
6062                 return I40E_ERR_PARAM;
6063
6064         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6065         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6066         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6067
6068         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6069
6070         if (status == I40E_SUCCESS) {
6071                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6072
6073                 if (reg_val1 != NULL)
6074                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6075         }
6076
6077         return status;
6078 }
6079
6080 /**
6081  * i40e_aq_alternate_read_indirect
6082  * @hw: pointer to the hardware structure
6083  * @addr: address of the alternate structure field
6084  * @dw_count: number of alternate structure fields to read
6085  * @buffer: pointer to the command buffer
6086  *
6087  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6088  * place them in 'buffer'. The buffer should be allocated by caller.
6089  *
6090  **/
6091 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6092                                 u32 addr, u32 dw_count, void *buffer)
6093 {
6094         struct i40e_aq_desc desc;
6095         struct i40e_aqc_alternate_ind_write *cmd_resp =
6096                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6097         enum i40e_status_code status;
6098
6099         if (buffer == NULL)
6100                 return I40E_ERR_PARAM;
6101
6102         /* Indirect command */
6103         i40e_fill_default_direct_cmd_desc(&desc,
6104                 i40e_aqc_opc_alternate_read_indirect);
6105
6106         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6107         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6108         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6109                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6110
6111         cmd_resp->address = CPU_TO_LE32(addr);
6112         cmd_resp->length = CPU_TO_LE32(dw_count);
6113
6114         status = i40e_asq_send_command(hw, &desc, buffer,
6115                                        I40E_LO_DWORD(4*dw_count), NULL);
6116
6117         return status;
6118 }
6119
6120 /**
6121  *  i40e_aq_alternate_clear
6122  *  @hw: pointer to the HW structure.
6123  *
6124  *  Clear the alternate structures of the port from which the function
6125  *  is called.
6126  *
6127  **/
6128 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6129 {
6130         struct i40e_aq_desc desc;
6131         enum i40e_status_code status;
6132
6133         i40e_fill_default_direct_cmd_desc(&desc,
6134                                           i40e_aqc_opc_alternate_clear_port);
6135
6136         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6137
6138         return status;
6139 }
6140
6141 /**
6142  *  i40e_aq_alternate_write_done
6143  *  @hw: pointer to the HW structure.
6144  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6145  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6146  *
6147  *  Indicates to the FW that alternate structures have been changed.
6148  *
6149  **/
6150 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6151                 u8 bios_mode, bool *reset_needed)
6152 {
6153         struct i40e_aq_desc desc;
6154         struct i40e_aqc_alternate_write_done *cmd =
6155                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6156         enum i40e_status_code status;
6157
6158         if (reset_needed == NULL)
6159                 return I40E_ERR_PARAM;
6160
6161         i40e_fill_default_direct_cmd_desc(&desc,
6162                                           i40e_aqc_opc_alternate_write_done);
6163
6164         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6165
6166         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6167         if (!status && reset_needed)
6168                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6169                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6170
6171         return status;
6172 }
6173
6174 /**
6175  *  i40e_aq_set_oem_mode
6176  *  @hw: pointer to the HW structure.
6177  *  @oem_mode: the OEM mode to be used
6178  *
6179  *  Sets the device to a specific operating mode. Currently the only supported
6180  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6181  *
6182  **/
6183 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6184                 u8 oem_mode)
6185 {
6186         struct i40e_aq_desc desc;
6187         struct i40e_aqc_alternate_write_done *cmd =
6188                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6189         enum i40e_status_code status;
6190
6191         i40e_fill_default_direct_cmd_desc(&desc,
6192                                           i40e_aqc_opc_alternate_set_mode);
6193
6194         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6195
6196         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6197
6198         return status;
6199 }
6200
6201 /**
6202  * i40e_aq_resume_port_tx
6203  * @hw: pointer to the hardware structure
6204  * @cmd_details: pointer to command details structure or NULL
6205  *
6206  * Resume port's Tx traffic
6207  **/
6208 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6209                                 struct i40e_asq_cmd_details *cmd_details)
6210 {
6211         struct i40e_aq_desc desc;
6212         enum i40e_status_code status;
6213
6214         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6215
6216         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6217
6218         return status;
6219 }
6220
6221 /**
6222  * i40e_set_pci_config_data - store PCI bus info
6223  * @hw: pointer to hardware structure
6224  * @link_status: the link status word from PCI config space
6225  *
6226  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6227  **/
6228 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6229 {
6230         hw->bus.type = i40e_bus_type_pci_express;
6231
6232         switch (link_status & I40E_PCI_LINK_WIDTH) {
6233         case I40E_PCI_LINK_WIDTH_1:
6234                 hw->bus.width = i40e_bus_width_pcie_x1;
6235                 break;
6236         case I40E_PCI_LINK_WIDTH_2:
6237                 hw->bus.width = i40e_bus_width_pcie_x2;
6238                 break;
6239         case I40E_PCI_LINK_WIDTH_4:
6240                 hw->bus.width = i40e_bus_width_pcie_x4;
6241                 break;
6242         case I40E_PCI_LINK_WIDTH_8:
6243                 hw->bus.width = i40e_bus_width_pcie_x8;
6244                 break;
6245         default:
6246                 hw->bus.width = i40e_bus_width_unknown;
6247                 break;
6248         }
6249
6250         switch (link_status & I40E_PCI_LINK_SPEED) {
6251         case I40E_PCI_LINK_SPEED_2500:
6252                 hw->bus.speed = i40e_bus_speed_2500;
6253                 break;
6254         case I40E_PCI_LINK_SPEED_5000:
6255                 hw->bus.speed = i40e_bus_speed_5000;
6256                 break;
6257         case I40E_PCI_LINK_SPEED_8000:
6258                 hw->bus.speed = i40e_bus_speed_8000;
6259                 break;
6260         default:
6261                 hw->bus.speed = i40e_bus_speed_unknown;
6262                 break;
6263         }
6264 }
6265
6266 /**
6267  * i40e_aq_debug_dump
6268  * @hw: pointer to the hardware structure
6269  * @cluster_id: specific cluster to dump
6270  * @table_id: table id within cluster
6271  * @start_index: index of line in the block to read
6272  * @buff_size: dump buffer size
6273  * @buff: dump buffer
6274  * @ret_buff_size: actual buffer size returned
6275  * @ret_next_table: next block to read
6276  * @ret_next_index: next index to read
6277  * @cmd_details: pointer to command details structure or NULL
6278  *
6279  * Dump internal FW/HW data for debug purposes.
6280  *
6281  **/
6282 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6283                                 u8 table_id, u32 start_index, u16 buff_size,
6284                                 void *buff, u16 *ret_buff_size,
6285                                 u8 *ret_next_table, u32 *ret_next_index,
6286                                 struct i40e_asq_cmd_details *cmd_details)
6287 {
6288         struct i40e_aq_desc desc;
6289         struct i40e_aqc_debug_dump_internals *cmd =
6290                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6291         struct i40e_aqc_debug_dump_internals *resp =
6292                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6293         enum i40e_status_code status;
6294
6295         if (buff_size == 0 || !buff)
6296                 return I40E_ERR_PARAM;
6297
6298         i40e_fill_default_direct_cmd_desc(&desc,
6299                                           i40e_aqc_opc_debug_dump_internals);
6300         /* Indirect Command */
6301         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6302         if (buff_size > I40E_AQ_LARGE_BUF)
6303                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6304
6305         cmd->cluster_id = cluster_id;
6306         cmd->table_id = table_id;
6307         cmd->idx = CPU_TO_LE32(start_index);
6308
6309         desc.datalen = CPU_TO_LE16(buff_size);
6310
6311         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6312         if (!status) {
6313                 if (ret_buff_size != NULL)
6314                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6315                 if (ret_next_table != NULL)
6316                         *ret_next_table = resp->table_id;
6317                 if (ret_next_index != NULL)
6318                         *ret_next_index = LE32_TO_CPU(resp->idx);
6319         }
6320
6321         return status;
6322 }
6323
6324 /**
6325  * i40e_read_bw_from_alt_ram
6326  * @hw: pointer to the hardware structure
6327  * @max_bw: pointer for max_bw read
6328  * @min_bw: pointer for min_bw read
6329  * @min_valid: pointer for bool that is true if min_bw is a valid value
6330  * @max_valid: pointer for bool that is true if max_bw is a valid value
6331  *
6332  * Read bw from the alternate ram for the given pf
6333  **/
6334 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6335                                         u32 *max_bw, u32 *min_bw,
6336                                         bool *min_valid, bool *max_valid)
6337 {
6338         enum i40e_status_code status;
6339         u32 max_bw_addr, min_bw_addr;
6340
6341         /* Calculate the address of the min/max bw registers */
6342         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6343                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6344                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6345         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6346                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6347                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6348
6349         /* Read the bandwidths from alt ram */
6350         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6351                                         min_bw_addr, min_bw);
6352
6353         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6354                 *min_valid = true;
6355         else
6356                 *min_valid = false;
6357
6358         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6359                 *max_valid = true;
6360         else
6361                 *max_valid = false;
6362
6363         return status;
6364 }
6365
6366 /**
6367  * i40e_aq_configure_partition_bw
6368  * @hw: pointer to the hardware structure
6369  * @bw_data: Buffer holding valid pfs and bw limits
6370  * @cmd_details: pointer to command details
6371  *
6372  * Configure partitions guaranteed/max bw
6373  **/
6374 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6375                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6376                         struct i40e_asq_cmd_details *cmd_details)
6377 {
6378         enum i40e_status_code status;
6379         struct i40e_aq_desc desc;
6380         u16 bwd_size = sizeof(*bw_data);
6381
6382         i40e_fill_default_direct_cmd_desc(&desc,
6383                                 i40e_aqc_opc_configure_partition_bw);
6384
6385         /* Indirect command */
6386         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6387         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6388
6389         desc.datalen = CPU_TO_LE16(bwd_size);
6390
6391         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6392
6393         return status;
6394 }
6395
6396 /**
6397  * i40e_read_phy_register_clause22
6398  * @hw: pointer to the HW structure
6399  * @reg: register address in the page
6400  * @phy_addr: PHY address on MDIO interface
6401  * @value: PHY register value
6402  *
6403  * Reads specified PHY register value
6404  **/
6405 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6406                                         u16 reg, u8 phy_addr, u16 *value)
6407 {
6408         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6409         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6410         u32 command = 0;
6411         u16 retry = 1000;
6412
6413         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6414                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6415                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6416                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6417                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6418         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6419         do {
6420                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6421                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6422                         status = I40E_SUCCESS;
6423                         break;
6424                 }
6425                 i40e_usec_delay(10);
6426                 retry--;
6427         } while (retry);
6428
6429         if (status) {
6430                 i40e_debug(hw, I40E_DEBUG_PHY,
6431                            "PHY: Can't write command to external PHY.\n");
6432         } else {
6433                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6434                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6435                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6436         }
6437
6438         return status;
6439 }
6440
6441 /**
6442  * i40e_write_phy_register_clause22
6443  * @hw: pointer to the HW structure
6444  * @reg: register address in the page
6445  * @phy_addr: PHY address on MDIO interface
6446  * @value: PHY register value
6447  *
6448  * Writes specified PHY register value
6449  **/
6450 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6451                                         u16 reg, u8 phy_addr, u16 value)
6452 {
6453         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6454         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6455         u32 command  = 0;
6456         u16 retry = 1000;
6457
6458         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6459         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6460
6461         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6462                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6463                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6464                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6465                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6466
6467         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6468         do {
6469                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6470                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6471                         status = I40E_SUCCESS;
6472                         break;
6473                 }
6474                 i40e_usec_delay(10);
6475                 retry--;
6476         } while (retry);
6477
6478         return status;
6479 }
6480
6481 /**
6482  * i40e_read_phy_register_clause45
6483  * @hw: pointer to the HW structure
6484  * @page: registers page number
6485  * @reg: register address in the page
6486  * @phy_addr: PHY address on MDIO interface
6487  * @value: PHY register value
6488  *
6489  * Reads specified PHY register value
6490  **/
6491 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6492                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6493 {
6494         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6495         u32 command  = 0;
6496         u16 retry = 1000;
6497         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6498
6499         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6500                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6501                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6502                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6503                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6504                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6505                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6506         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6507         do {
6508                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6509                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6510                         status = I40E_SUCCESS;
6511                         break;
6512                 }
6513                 i40e_usec_delay(10);
6514                 retry--;
6515         } while (retry);
6516
6517         if (status) {
6518                 i40e_debug(hw, I40E_DEBUG_PHY,
6519                            "PHY: Can't write command to external PHY.\n");
6520                 goto phy_read_end;
6521         }
6522
6523         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6524                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6525                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6526                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6527                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6528                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6529         status = I40E_ERR_TIMEOUT;
6530         retry = 1000;
6531         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6532         do {
6533                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6534                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6535                         status = I40E_SUCCESS;
6536                         break;
6537                 }
6538                 i40e_usec_delay(10);
6539                 retry--;
6540         } while (retry);
6541
6542         if (!status) {
6543                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6544                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6545                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6546         } else {
6547                 i40e_debug(hw, I40E_DEBUG_PHY,
6548                            "PHY: Can't read register value from external PHY.\n");
6549         }
6550
6551 phy_read_end:
6552         return status;
6553 }
6554
6555 /**
6556  * i40e_write_phy_register_clause45
6557  * @hw: pointer to the HW structure
6558  * @page: registers page number
6559  * @reg: register address in the page
6560  * @phy_addr: PHY address on MDIO interface
6561  * @value: PHY register value
6562  *
6563  * Writes value to specified PHY register
6564  **/
6565 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6566                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6567 {
6568         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6569         u32 command  = 0;
6570         u16 retry = 1000;
6571         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6572
6573         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6574                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6575                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6576                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6577                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6578                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6579                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6580         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6581         do {
6582                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6583                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6584                         status = I40E_SUCCESS;
6585                         break;
6586                 }
6587                 i40e_usec_delay(10);
6588                 retry--;
6589         } while (retry);
6590         if (status) {
6591                 i40e_debug(hw, I40E_DEBUG_PHY,
6592                            "PHY: Can't write command to external PHY.\n");
6593                 goto phy_write_end;
6594         }
6595
6596         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6597         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6598
6599         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6600                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6601                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6602                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6603                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6604                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6605         status = I40E_ERR_TIMEOUT;
6606         retry = 1000;
6607         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6608         do {
6609                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6610                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6611                         status = I40E_SUCCESS;
6612                         break;
6613                 }
6614                 i40e_usec_delay(10);
6615                 retry--;
6616         } while (retry);
6617
6618 phy_write_end:
6619         return status;
6620 }
6621
6622 /**
6623  * i40e_write_phy_register
6624  * @hw: pointer to the HW structure
6625  * @page: registers page number
6626  * @reg: register address in the page
6627  * @phy_addr: PHY address on MDIO interface
6628  * @value: PHY register value
6629  *
6630  * Writes value to specified PHY register
6631  **/
6632 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6633                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6634 {
6635         enum i40e_status_code status;
6636
6637         switch (hw->device_id) {
6638         case I40E_DEV_ID_1G_BASE_T_X722:
6639                 status = i40e_write_phy_register_clause22(hw,
6640                         reg, phy_addr, value);
6641                 break;
6642         case I40E_DEV_ID_10G_BASE_T:
6643         case I40E_DEV_ID_10G_BASE_T4:
6644         case I40E_DEV_ID_10G_BASE_T_X722:
6645         case I40E_DEV_ID_25G_B:
6646         case I40E_DEV_ID_25G_SFP28:
6647                 status = i40e_write_phy_register_clause45(hw,
6648                         page, reg, phy_addr, value);
6649                 break;
6650         default:
6651                 status = I40E_ERR_UNKNOWN_PHY;
6652                 break;
6653         }
6654
6655         return status;
6656 }
6657
6658 /**
6659  * i40e_read_phy_register
6660  * @hw: pointer to the HW structure
6661  * @page: registers page number
6662  * @reg: register address in the page
6663  * @phy_addr: PHY address on MDIO interface
6664  * @value: PHY register value
6665  *
6666  * Reads specified PHY register value
6667  **/
6668 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6669                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6670 {
6671         enum i40e_status_code status;
6672
6673         switch (hw->device_id) {
6674         case I40E_DEV_ID_1G_BASE_T_X722:
6675                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6676                                                          value);
6677                 break;
6678         case I40E_DEV_ID_10G_BASE_T:
6679         case I40E_DEV_ID_10G_BASE_T4:
6680         case I40E_DEV_ID_10G_BASE_T_X722:
6681         case I40E_DEV_ID_25G_B:
6682         case I40E_DEV_ID_25G_SFP28:
6683                 status = i40e_read_phy_register_clause45(hw, page, reg,
6684                                                          phy_addr, value);
6685                 break;
6686         default:
6687                 status = I40E_ERR_UNKNOWN_PHY;
6688                 break;
6689         }
6690
6691         return status;
6692 }
6693
6694 /**
6695  * i40e_get_phy_address
6696  * @hw: pointer to the HW structure
6697  * @dev_num: PHY port num that address we want
6698  *
6699  * Gets PHY address for current port
6700  **/
6701 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6702 {
6703         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6704         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6705
6706         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6707 }
6708
6709 /**
6710  * i40e_blink_phy_led
6711  * @hw: pointer to the HW structure
6712  * @time: time how long led will blinks in secs
6713  * @interval: gap between LED on and off in msecs
6714  *
6715  * Blinks PHY link LED
6716  **/
6717 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6718                                               u32 time, u32 interval)
6719 {
6720         enum i40e_status_code status = I40E_SUCCESS;
6721         u32 i;
6722         u16 led_ctl = 0;
6723         u16 gpio_led_port;
6724         u16 led_reg;
6725         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6726         u8 phy_addr = 0;
6727         u8 port_num;
6728
6729         i = rd32(hw, I40E_PFGEN_PORTNUM);
6730         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6731         phy_addr = i40e_get_phy_address(hw, port_num);
6732
6733         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6734              led_addr++) {
6735                 status = i40e_read_phy_register_clause45(hw,
6736                                                          I40E_PHY_COM_REG_PAGE,
6737                                                          led_addr, phy_addr,
6738                                                          &led_reg);
6739                 if (status)
6740                         goto phy_blinking_end;
6741                 led_ctl = led_reg;
6742                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6743                         led_reg = 0;
6744                         status = i40e_write_phy_register_clause45(hw,
6745                                                          I40E_PHY_COM_REG_PAGE,
6746                                                          led_addr, phy_addr,
6747                                                          led_reg);
6748                         if (status)
6749                                 goto phy_blinking_end;
6750                         break;
6751                 }
6752         }
6753
6754         if (time > 0 && interval > 0) {
6755                 for (i = 0; i < time * 1000; i += interval) {
6756                         status = i40e_read_phy_register_clause45(hw,
6757                                                 I40E_PHY_COM_REG_PAGE,
6758                                                 led_addr, phy_addr, &led_reg);
6759                         if (status)
6760                                 goto restore_config;
6761                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6762                                 led_reg = 0;
6763                         else
6764                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6765                         status = i40e_write_phy_register_clause45(hw,
6766                                                 I40E_PHY_COM_REG_PAGE,
6767                                                 led_addr, phy_addr, led_reg);
6768                         if (status)
6769                                 goto restore_config;
6770                         i40e_msec_delay(interval);
6771                 }
6772         }
6773
6774 restore_config:
6775         status = i40e_write_phy_register_clause45(hw,
6776                                                   I40E_PHY_COM_REG_PAGE,
6777                                                   led_addr, phy_addr, led_ctl);
6778
6779 phy_blinking_end:
6780         return status;
6781 }
6782
6783 /**
6784  * i40e_led_get_reg - read LED register
6785  * @hw: pointer to the HW structure
6786  * @led_addr: LED register address
6787  * @reg_val: read register value
6788  **/
6789 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6790                                               u32 *reg_val)
6791 {
6792         enum i40e_status_code status;
6793         u8 phy_addr = 0;
6794
6795         *reg_val = 0;
6796         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6797                 status = i40e_aq_get_phy_register(hw,
6798                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6799                                                 I40E_PHY_COM_REG_PAGE,
6800                                                 I40E_PHY_LED_PROV_REG_1,
6801                                                 reg_val, NULL);
6802         } else {
6803                 phy_addr = i40e_get_phy_address(hw, hw->port);
6804                 status = i40e_read_phy_register_clause45(hw,
6805                                                          I40E_PHY_COM_REG_PAGE,
6806                                                          led_addr, phy_addr,
6807                                                          (u16 *)reg_val);
6808         }
6809         return status;
6810 }
6811
6812 /**
6813  * i40e_led_set_reg - write LED register
6814  * @hw: pointer to the HW structure
6815  * @led_addr: LED register address
6816  * @reg_val: register value to write
6817  **/
6818 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6819                                               u32 reg_val)
6820 {
6821         enum i40e_status_code status;
6822         u8 phy_addr = 0;
6823
6824         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6825                 status = i40e_aq_set_phy_register(hw,
6826                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6827                                                 I40E_PHY_COM_REG_PAGE,
6828                                                 I40E_PHY_LED_PROV_REG_1,
6829                                                 reg_val, NULL);
6830         } else {
6831                 phy_addr = i40e_get_phy_address(hw, hw->port);
6832                 status = i40e_write_phy_register_clause45(hw,
6833                                                           I40E_PHY_COM_REG_PAGE,
6834                                                           led_addr, phy_addr,
6835                                                           (u16)reg_val);
6836         }
6837
6838         return status;
6839 }
6840
6841 /**
6842  * i40e_led_get_phy - return current on/off mode
6843  * @hw: pointer to the hw struct
6844  * @led_addr: address of led register to use
6845  * @val: original value of register to use
6846  *
6847  **/
6848 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6849                                        u16 *val)
6850 {
6851         enum i40e_status_code status = I40E_SUCCESS;
6852         u16 gpio_led_port;
6853         u32 reg_val_aq;
6854         u16 temp_addr;
6855         u8 phy_addr = 0;
6856         u16 reg_val;
6857
6858         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6859                 status = i40e_aq_get_phy_register(hw,
6860                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6861                                                 I40E_PHY_COM_REG_PAGE,
6862                                                 I40E_PHY_LED_PROV_REG_1,
6863                                                 &reg_val_aq, NULL);
6864                 if (status == I40E_SUCCESS)
6865                         *val = (u16)reg_val_aq;
6866                 return status;
6867         }
6868         temp_addr = I40E_PHY_LED_PROV_REG_1;
6869         phy_addr = i40e_get_phy_address(hw, hw->port);
6870         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6871              temp_addr++) {
6872                 status = i40e_read_phy_register_clause45(hw,
6873                                                          I40E_PHY_COM_REG_PAGE,
6874                                                          temp_addr, phy_addr,
6875                                                          &reg_val);
6876                 if (status)
6877                         return status;
6878                 *val = reg_val;
6879                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6880                         *led_addr = temp_addr;
6881                         break;
6882                 }
6883         }
6884         return status;
6885 }
6886
6887 /**
6888  * i40e_led_set_phy
6889  * @hw: pointer to the HW structure
6890  * @on: true or false
6891  * @led_addr: address of led register to use
6892  * @mode: original val plus bit for set or ignore
6893  *
6894  * Set led's on or off when controlled by the PHY
6895  *
6896  **/
6897 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6898                                        u16 led_addr, u32 mode)
6899 {
6900         enum i40e_status_code status = I40E_SUCCESS;
6901         u32 led_ctl = 0;
6902         u32 led_reg = 0;
6903
6904         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6905         if (status)
6906                 return status;
6907         led_ctl = led_reg;
6908         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6909                 led_reg = 0;
6910                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6911                 if (status)
6912                         return status;
6913         }
6914         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6915         if (status)
6916                 goto restore_config;
6917         if (on)
6918                 led_reg = I40E_PHY_LED_MANUAL_ON;
6919         else
6920                 led_reg = 0;
6921         status = i40e_led_set_reg(hw, led_addr, led_reg);
6922         if (status)
6923                 goto restore_config;
6924         if (mode & I40E_PHY_LED_MODE_ORIG) {
6925                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6926                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6927         }
6928         return status;
6929
6930 restore_config:
6931         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6932         return status;
6933 }
6934 #endif /* PF_DRIVER */
6935
6936 /**
6937  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6938  * @hw: pointer to the hw struct
6939  * @reg_addr: register address
6940  * @reg_val: ptr to register value
6941  * @cmd_details: pointer to command details structure or NULL
6942  *
6943  * Use the firmware to read the Rx control register,
6944  * especially useful if the Rx unit is under heavy pressure
6945  **/
6946 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6947                                 u32 reg_addr, u32 *reg_val,
6948                                 struct i40e_asq_cmd_details *cmd_details)
6949 {
6950         struct i40e_aq_desc desc;
6951         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6952                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6953         enum i40e_status_code status;
6954
6955         if (reg_val == NULL)
6956                 return I40E_ERR_PARAM;
6957
6958         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6959
6960         cmd_resp->address = CPU_TO_LE32(reg_addr);
6961
6962         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6963
6964         if (status == I40E_SUCCESS)
6965                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6966
6967         return status;
6968 }
6969
6970 /**
6971  * i40e_read_rx_ctl - read from an Rx control register
6972  * @hw: pointer to the hw struct
6973  * @reg_addr: register address
6974  **/
6975 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6976 {
6977         enum i40e_status_code status = I40E_SUCCESS;
6978         bool use_register;
6979         int retry = 5;
6980         u32 val = 0;
6981
6982         use_register = (((hw->aq.api_maj_ver == 1) &&
6983                         (hw->aq.api_min_ver < 5)) ||
6984                         (hw->mac.type == I40E_MAC_X722));
6985         if (!use_register) {
6986 do_retry:
6987                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6988                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6989                         i40e_msec_delay(1);
6990                         retry--;
6991                         goto do_retry;
6992                 }
6993         }
6994
6995         /* if the AQ access failed, try the old-fashioned way */
6996         if (status || use_register)
6997                 val = rd32(hw, reg_addr);
6998
6999         return val;
7000 }
7001
7002 /**
7003  * i40e_aq_rx_ctl_write_register
7004  * @hw: pointer to the hw struct
7005  * @reg_addr: register address
7006  * @reg_val: register value
7007  * @cmd_details: pointer to command details structure or NULL
7008  *
7009  * Use the firmware to write to an Rx control register,
7010  * especially useful if the Rx unit is under heavy pressure
7011  **/
7012 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7013                                 u32 reg_addr, u32 reg_val,
7014                                 struct i40e_asq_cmd_details *cmd_details)
7015 {
7016         struct i40e_aq_desc desc;
7017         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7018                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7019         enum i40e_status_code status;
7020
7021         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7022
7023         cmd->address = CPU_TO_LE32(reg_addr);
7024         cmd->value = CPU_TO_LE32(reg_val);
7025
7026         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7027
7028         return status;
7029 }
7030
7031 /**
7032  * i40e_write_rx_ctl - write to an Rx control register
7033  * @hw: pointer to the hw struct
7034  * @reg_addr: register address
7035  * @reg_val: register value
7036  **/
7037 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7038 {
7039         enum i40e_status_code status = I40E_SUCCESS;
7040         bool use_register;
7041         int retry = 5;
7042
7043         use_register = (((hw->aq.api_maj_ver == 1) &&
7044                         (hw->aq.api_min_ver < 5)) ||
7045                         (hw->mac.type == I40E_MAC_X722));
7046         if (!use_register) {
7047 do_retry:
7048                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7049                                                        reg_val, NULL);
7050                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7051                         i40e_msec_delay(1);
7052                         retry--;
7053                         goto do_retry;
7054                 }
7055         }
7056
7057         /* if the AQ access failed, try the old-fashioned way */
7058         if (status || use_register)
7059                 wr32(hw, reg_addr, reg_val);
7060 }
7061
7062 /**
7063  * i40e_aq_set_phy_register
7064  * @hw: pointer to the hw struct
7065  * @phy_select: select which phy should be accessed
7066  * @dev_addr: PHY device address
7067  * @reg_addr: PHY register address
7068  * @reg_val: new register value
7069  * @cmd_details: pointer to command details structure or NULL
7070  *
7071  * Write the external PHY register.
7072  **/
7073 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7074                                 u8 phy_select, u8 dev_addr,
7075                                 u32 reg_addr, u32 reg_val,
7076                                 struct i40e_asq_cmd_details *cmd_details)
7077 {
7078         struct i40e_aq_desc desc;
7079         struct i40e_aqc_phy_register_access *cmd =
7080                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7081         enum i40e_status_code status;
7082
7083         i40e_fill_default_direct_cmd_desc(&desc,
7084                                           i40e_aqc_opc_set_phy_register);
7085
7086         cmd->phy_interface = phy_select;
7087         cmd->dev_addres = dev_addr;
7088         cmd->reg_address = CPU_TO_LE32(reg_addr);
7089         cmd->reg_value = CPU_TO_LE32(reg_val);
7090
7091         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7092
7093         return status;
7094 }
7095
7096 /**
7097  * i40e_aq_get_phy_register
7098  * @hw: pointer to the hw struct
7099  * @phy_select: select which phy should be accessed
7100  * @dev_addr: PHY device address
7101  * @reg_addr: PHY register address
7102  * @reg_val: read register value
7103  * @cmd_details: pointer to command details structure or NULL
7104  *
7105  * Read the external PHY register.
7106  **/
7107 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7108                                 u8 phy_select, u8 dev_addr,
7109                                 u32 reg_addr, u32 *reg_val,
7110                                 struct i40e_asq_cmd_details *cmd_details)
7111 {
7112         struct i40e_aq_desc desc;
7113         struct i40e_aqc_phy_register_access *cmd =
7114                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7115         enum i40e_status_code status;
7116
7117         i40e_fill_default_direct_cmd_desc(&desc,
7118                                           i40e_aqc_opc_get_phy_register);
7119
7120         cmd->phy_interface = phy_select;
7121         cmd->dev_addres = dev_addr;
7122         cmd->reg_address = CPU_TO_LE32(reg_addr);
7123
7124         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7125         if (!status)
7126                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7127
7128         return status;
7129 }
7130
7131 #ifdef VF_DRIVER
7132
7133 /**
7134  * i40e_aq_send_msg_to_pf
7135  * @hw: pointer to the hardware structure
7136  * @v_opcode: opcodes for VF-PF communication
7137  * @v_retval: return error code
7138  * @msg: pointer to the msg buffer
7139  * @msglen: msg length
7140  * @cmd_details: pointer to command details
7141  *
7142  * Send message to PF driver using admin queue. By default, this message
7143  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7144  * completion before returning.
7145  **/
7146 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7147                                 enum virtchnl_ops v_opcode,
7148                                 enum i40e_status_code v_retval,
7149                                 u8 *msg, u16 msglen,
7150                                 struct i40e_asq_cmd_details *cmd_details)
7151 {
7152         struct i40e_aq_desc desc;
7153         struct i40e_asq_cmd_details details;
7154         enum i40e_status_code status;
7155
7156         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7157         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7158         desc.cookie_high = CPU_TO_LE32(v_opcode);
7159         desc.cookie_low = CPU_TO_LE32(v_retval);
7160         if (msglen) {
7161                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7162                                                 | I40E_AQ_FLAG_RD));
7163                 if (msglen > I40E_AQ_LARGE_BUF)
7164                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7165                 desc.datalen = CPU_TO_LE16(msglen);
7166         }
7167         if (!cmd_details) {
7168                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7169                 details.async = true;
7170                 cmd_details = &details;
7171         }
7172         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7173                                        msglen, cmd_details);
7174         return status;
7175 }
7176
7177 /**
7178  * i40e_vf_parse_hw_config
7179  * @hw: pointer to the hardware structure
7180  * @msg: pointer to the virtual channel VF resource structure
7181  *
7182  * Given a VF resource message from the PF, populate the hw struct
7183  * with appropriate information.
7184  **/
7185 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7186                              struct virtchnl_vf_resource *msg)
7187 {
7188         struct virtchnl_vsi_resource *vsi_res;
7189         int i;
7190
7191         vsi_res = &msg->vsi_res[0];
7192
7193         hw->dev_caps.num_vsis = msg->num_vsis;
7194         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7195         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7196         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7197         hw->dev_caps.dcb = msg->vf_cap_flags &
7198                            VIRTCHNL_VF_OFFLOAD_L2;
7199         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7200                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7201         for (i = 0; i < msg->num_vsis; i++) {
7202                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7203                         i40e_memcpy(hw->mac.perm_addr,
7204                                     vsi_res->default_mac_addr,
7205                                     ETH_ALEN,
7206                                     I40E_NONDMA_TO_NONDMA);
7207                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7208                                     ETH_ALEN,
7209                                     I40E_NONDMA_TO_NONDMA);
7210                 }
7211                 vsi_res++;
7212         }
7213 }
7214
7215 /**
7216  * i40e_vf_reset
7217  * @hw: pointer to the hardware structure
7218  *
7219  * Send a VF_RESET message to the PF. Does not wait for response from PF
7220  * as none will be forthcoming. Immediately after calling this function,
7221  * the admin queue should be shut down and (optionally) reinitialized.
7222  **/
7223 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7224 {
7225         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7226                                       I40E_SUCCESS, NULL, 0, NULL);
7227 }
7228 #endif /* VF_DRIVER */
7229
7230 /**
7231  * i40e_aq_set_arp_proxy_config
7232  * @hw: pointer to the HW structure
7233  * @proxy_config: pointer to proxy config command table struct
7234  * @cmd_details: pointer to command details
7235  *
7236  * Set ARP offload parameters from pre-populated
7237  * i40e_aqc_arp_proxy_data struct
7238  **/
7239 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7240                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7241                                 struct i40e_asq_cmd_details *cmd_details)
7242 {
7243         struct i40e_aq_desc desc;
7244         enum i40e_status_code status;
7245
7246         if (!proxy_config)
7247                 return I40E_ERR_PARAM;
7248
7249         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7250
7251         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7252         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7253         desc.params.external.addr_high =
7254                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7255         desc.params.external.addr_low =
7256                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7257         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7258
7259         status = i40e_asq_send_command(hw, &desc, proxy_config,
7260                                        sizeof(struct i40e_aqc_arp_proxy_data),
7261                                        cmd_details);
7262
7263         return status;
7264 }
7265
7266 /**
7267  * i40e_aq_opc_set_ns_proxy_table_entry
7268  * @hw: pointer to the HW structure
7269  * @ns_proxy_table_entry: pointer to NS table entry command struct
7270  * @cmd_details: pointer to command details
7271  *
7272  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7273  * from pre-populated i40e_aqc_ns_proxy_data struct
7274  **/
7275 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7276                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7277                         struct i40e_asq_cmd_details *cmd_details)
7278 {
7279         struct i40e_aq_desc desc;
7280         enum i40e_status_code status;
7281
7282         if (!ns_proxy_table_entry)
7283                 return I40E_ERR_PARAM;
7284
7285         i40e_fill_default_direct_cmd_desc(&desc,
7286                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7287
7288         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7289         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7290         desc.params.external.addr_high =
7291                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7292         desc.params.external.addr_low =
7293                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7294         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7295
7296         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7297                                        sizeof(struct i40e_aqc_ns_proxy_data),
7298                                        cmd_details);
7299
7300         return status;
7301 }
7302
7303 /**
7304  * i40e_aq_set_clear_wol_filter
7305  * @hw: pointer to the hw struct
7306  * @filter_index: index of filter to modify (0-7)
7307  * @filter: buffer containing filter to be set
7308  * @set_filter: true to set filter, false to clear filter
7309  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7310  *              if false, pass through packets may cause wake-up
7311  * @filter_valid: true if filter action is valid
7312  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7313  * @cmd_details: pointer to command details structure or NULL
7314  *
7315  * Set or clear WoL filter for port attached to the PF
7316  **/
7317 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7318                                 u8 filter_index,
7319                                 struct i40e_aqc_set_wol_filter_data *filter,
7320                                 bool set_filter, bool no_wol_tco,
7321                                 bool filter_valid, bool no_wol_tco_valid,
7322                                 struct i40e_asq_cmd_details *cmd_details)
7323 {
7324         struct i40e_aq_desc desc;
7325         struct i40e_aqc_set_wol_filter *cmd =
7326                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7327         enum i40e_status_code status;
7328         u16 cmd_flags = 0;
7329         u16 valid_flags = 0;
7330         u16 buff_len = 0;
7331
7332         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7333
7334         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7335                 return  I40E_ERR_PARAM;
7336         cmd->filter_index = CPU_TO_LE16(filter_index);
7337
7338         if (set_filter) {
7339                 if (!filter)
7340                         return  I40E_ERR_PARAM;
7341
7342                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7343                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7344         }
7345
7346         if (no_wol_tco)
7347                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7348         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7349
7350         if (filter_valid)
7351                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7352         if (no_wol_tco_valid)
7353                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7354         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7355
7356         buff_len = sizeof(*filter);
7357         desc.datalen = CPU_TO_LE16(buff_len);
7358
7359         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7360         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7361
7362         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7363         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7364
7365         status = i40e_asq_send_command(hw, &desc, filter,
7366                                        buff_len, cmd_details);
7367
7368         return status;
7369 }
7370
7371 /**
7372  * i40e_aq_get_wake_event_reason
7373  * @hw: pointer to the hw struct
7374  * @wake_reason: return value, index of matching filter
7375  * @cmd_details: pointer to command details structure or NULL
7376  *
7377  * Get information for the reason of a Wake Up event
7378  **/
7379 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7380                                 u16 *wake_reason,
7381                                 struct i40e_asq_cmd_details *cmd_details)
7382 {
7383         struct i40e_aq_desc desc;
7384         struct i40e_aqc_get_wake_reason_completion *resp =
7385                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7386         enum i40e_status_code status;
7387
7388         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7389
7390         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7391
7392         if (status == I40E_SUCCESS)
7393                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7394
7395         return status;
7396 }
7397
7398 /**
7399 * i40e_aq_clear_all_wol_filters
7400 * @hw: pointer to the hw struct
7401 * @cmd_details: pointer to command details structure or NULL
7402 *
7403 * Get information for the reason of a Wake Up event
7404 **/
7405 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7406         struct i40e_asq_cmd_details *cmd_details)
7407 {
7408         struct i40e_aq_desc desc;
7409         enum i40e_status_code status;
7410
7411         i40e_fill_default_direct_cmd_desc(&desc,
7412                                           i40e_aqc_opc_clear_all_wol_filters);
7413
7414         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7415
7416         return status;
7417 }
7418
7419 /**
7420  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7421  * @hw: pointer to the hw struct
7422  * @buff: command buffer (size in bytes = buff_size)
7423  * @buff_size: buffer size in bytes
7424  * @track_id: package tracking id
7425  * @error_offset: returns error offset
7426  * @error_info: returns error information
7427  * @cmd_details: pointer to command details structure or NULL
7428  **/
7429 enum
7430 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7431                                    u16 buff_size, u32 track_id,
7432                                    u32 *error_offset, u32 *error_info,
7433                                    struct i40e_asq_cmd_details *cmd_details)
7434 {
7435         struct i40e_aq_desc desc;
7436         struct i40e_aqc_write_personalization_profile *cmd =
7437                 (struct i40e_aqc_write_personalization_profile *)
7438                 &desc.params.raw;
7439         struct i40e_aqc_write_ddp_resp *resp;
7440         enum i40e_status_code status;
7441
7442         i40e_fill_default_direct_cmd_desc(&desc,
7443                                   i40e_aqc_opc_write_personalization_profile);
7444
7445         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7446         if (buff_size > I40E_AQ_LARGE_BUF)
7447                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7448
7449         desc.datalen = CPU_TO_LE16(buff_size);
7450
7451         cmd->profile_track_id = CPU_TO_LE32(track_id);
7452
7453         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7454         if (!status) {
7455                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7456                 if (error_offset)
7457                         *error_offset = LE32_TO_CPU(resp->error_offset);
7458                 if (error_info)
7459                         *error_info = LE32_TO_CPU(resp->error_info);
7460         }
7461
7462         return status;
7463 }
7464
7465 /**
7466  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7467  * @hw: pointer to the hw struct
7468  * @buff: command buffer (size in bytes = buff_size)
7469  * @buff_size: buffer size in bytes
7470  * @flags: AdminQ command flags
7471  * @cmd_details: pointer to command details structure or NULL
7472  **/
7473 enum
7474 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7475                                       u16 buff_size, u8 flags,
7476                                       struct i40e_asq_cmd_details *cmd_details)
7477 {
7478         struct i40e_aq_desc desc;
7479         struct i40e_aqc_get_applied_profiles *cmd =
7480                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7481         enum i40e_status_code status;
7482
7483         i40e_fill_default_direct_cmd_desc(&desc,
7484                           i40e_aqc_opc_get_personalization_profile_list);
7485
7486         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7487         if (buff_size > I40E_AQ_LARGE_BUF)
7488                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7489         desc.datalen = CPU_TO_LE16(buff_size);
7490
7491         cmd->flags = flags;
7492
7493         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7494
7495         return status;
7496 }
7497
7498 /**
7499  * i40e_find_segment_in_package
7500  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7501  * @pkg_hdr: pointer to the package header to be searched
7502  *
7503  * This function searches a package file for a particular segment type. On
7504  * success it returns a pointer to the segment header, otherwise it will
7505  * return NULL.
7506  **/
7507 struct i40e_generic_seg_header *
7508 i40e_find_segment_in_package(u32 segment_type,
7509                              struct i40e_package_header *pkg_hdr)
7510 {
7511         struct i40e_generic_seg_header *segment;
7512         u32 i;
7513
7514         /* Search all package segments for the requested segment type */
7515         for (i = 0; i < pkg_hdr->segment_count; i++) {
7516                 segment =
7517                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7518                          pkg_hdr->segment_offset[i]);
7519
7520                 if (segment->type == segment_type)
7521                         return segment;
7522         }
7523
7524         return NULL;
7525 }
7526
7527 /* Get section table in profile */
7528 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7529         do {                                                            \
7530                 struct i40e_profile_segment *p = (profile);             \
7531                 u32 count;                                              \
7532                 u32 *nvm;                                               \
7533                 count = p->device_table_count;                          \
7534                 nvm = (u32 *)&p->device_table[count];                   \
7535                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7536         } while (0)
7537
7538 /* Get section header in profile */
7539 #define I40E_SECTION_HEADER(profile, offset)                            \
7540         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7541
7542 /**
7543  * i40e_find_section_in_profile
7544  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7545  * @profile: pointer to the i40e segment header to be searched
7546  *
7547  * This function searches i40e segment for a particular section type. On
7548  * success it returns a pointer to the section header, otherwise it will
7549  * return NULL.
7550  **/
7551 struct i40e_profile_section_header *
7552 i40e_find_section_in_profile(u32 section_type,
7553                              struct i40e_profile_segment *profile)
7554 {
7555         struct i40e_profile_section_header *sec;
7556         struct i40e_section_table *sec_tbl;
7557         u32 sec_off;
7558         u32 i;
7559
7560         if (profile->header.type != SEGMENT_TYPE_I40E)
7561                 return NULL;
7562
7563         I40E_SECTION_TABLE(profile, sec_tbl);
7564
7565         for (i = 0; i < sec_tbl->section_count; i++) {
7566                 sec_off = sec_tbl->section_offset[i];
7567                 sec = I40E_SECTION_HEADER(profile, sec_off);
7568                 if (sec->section.type == section_type)
7569                         return sec;
7570         }
7571
7572         return NULL;
7573 }
7574
7575 /**
7576  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7577  * @hw: pointer to the hw struct
7578  * @aq: command buffer containing all data to execute AQ
7579  **/
7580 STATIC enum
7581 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7582                                           struct i40e_profile_aq_section *aq)
7583 {
7584         enum i40e_status_code status;
7585         struct i40e_aq_desc desc;
7586         u8 *msg = NULL;
7587         u16 msglen;
7588
7589         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7590         desc.flags |= CPU_TO_LE16(aq->flags);
7591         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7592                     I40E_NONDMA_TO_NONDMA);
7593
7594         msglen = aq->datalen;
7595         if (msglen) {
7596                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7597                                                 I40E_AQ_FLAG_RD));
7598                 if (msglen > I40E_AQ_LARGE_BUF)
7599                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7600                 desc.datalen = CPU_TO_LE16(msglen);
7601                 msg = &aq->data[0];
7602         }
7603
7604         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7605
7606         if (status != I40E_SUCCESS) {
7607                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7608                            "unable to exec DDP AQ opcode %u, error %d\n",
7609                            aq->opcode, status);
7610                 return status;
7611         }
7612
7613         /* copy returned desc to aq_buf */
7614         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7615                     I40E_NONDMA_TO_NONDMA);
7616
7617         return I40E_SUCCESS;
7618 }
7619
7620 /**
7621  * i40e_validate_profile
7622  * @hw: pointer to the hardware structure
7623  * @profile: pointer to the profile segment of the package to be validated
7624  * @track_id: package tracking id
7625  * @rollback: flag if the profile is for rollback.
7626  *
7627  * Validates supported devices and profile's sections.
7628  */
7629 STATIC enum i40e_status_code
7630 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7631                       u32 track_id, bool rollback)
7632 {
7633         struct i40e_profile_section_header *sec = NULL;
7634         enum i40e_status_code status = I40E_SUCCESS;
7635         struct i40e_section_table *sec_tbl;
7636         u32 vendor_dev_id;
7637         u32 dev_cnt;
7638         u32 sec_off;
7639         u32 i;
7640
7641         if (track_id == I40E_DDP_TRACKID_INVALID) {
7642                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7643                 return I40E_NOT_SUPPORTED;
7644         }
7645
7646         dev_cnt = profile->device_table_count;
7647         for (i = 0; i < dev_cnt; i++) {
7648                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7649                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7650                     hw->device_id == (vendor_dev_id & 0xFFFF))
7651                         break;
7652         }
7653         if (dev_cnt && (i == dev_cnt)) {
7654                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7655                            "Device doesn't support DDP\n");
7656                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7657         }
7658
7659         I40E_SECTION_TABLE(profile, sec_tbl);
7660
7661         /* Validate sections types */
7662         for (i = 0; i < sec_tbl->section_count; i++) {
7663                 sec_off = sec_tbl->section_offset[i];
7664                 sec = I40E_SECTION_HEADER(profile, sec_off);
7665                 if (rollback) {
7666                         if (sec->section.type == SECTION_TYPE_MMIO ||
7667                             sec->section.type == SECTION_TYPE_AQ ||
7668                             sec->section.type == SECTION_TYPE_RB_AQ) {
7669                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7670                                            "Not a roll-back package\n");
7671                                 return I40E_NOT_SUPPORTED;
7672                         }
7673                 } else {
7674                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7675                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7676                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7677                                            "Not an original package\n");
7678                                 return I40E_NOT_SUPPORTED;
7679                         }
7680                 }
7681         }
7682
7683         return status;
7684 }
7685
7686 /**
7687  * i40e_write_profile
7688  * @hw: pointer to the hardware structure
7689  * @profile: pointer to the profile segment of the package to be downloaded
7690  * @track_id: package tracking id
7691  *
7692  * Handles the download of a complete package.
7693  */
7694 enum i40e_status_code
7695 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7696                    u32 track_id)
7697 {
7698         enum i40e_status_code status = I40E_SUCCESS;
7699         struct i40e_section_table *sec_tbl;
7700         struct i40e_profile_section_header *sec = NULL;
7701         struct i40e_profile_aq_section *ddp_aq;
7702         u32 section_size = 0;
7703         u32 offset = 0, info = 0;
7704         u32 sec_off;
7705         u32 i;
7706
7707         status = i40e_validate_profile(hw, profile, track_id, false);
7708         if (status)
7709                 return status;
7710
7711         I40E_SECTION_TABLE(profile, sec_tbl);
7712
7713         for (i = 0; i < sec_tbl->section_count; i++) {
7714                 sec_off = sec_tbl->section_offset[i];
7715                 sec = I40E_SECTION_HEADER(profile, sec_off);
7716                 /* Process generic admin command */
7717                 if (sec->section.type == SECTION_TYPE_AQ) {
7718                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7719                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7720                         if (status) {
7721                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7722                                            "Failed to execute aq: section %d, opcode %u\n",
7723                                            i, ddp_aq->opcode);
7724                                 break;
7725                         }
7726                         sec->section.type = SECTION_TYPE_RB_AQ;
7727                 }
7728
7729                 /* Skip any non-mmio sections */
7730                 if (sec->section.type != SECTION_TYPE_MMIO)
7731                         continue;
7732
7733                 section_size = sec->section.size +
7734                         sizeof(struct i40e_profile_section_header);
7735
7736                 /* Write MMIO section */
7737                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7738                                            track_id, &offset, &info, NULL);
7739                 if (status) {
7740                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7741                                    "Failed to write profile: section %d, offset %d, info %d\n",
7742                                    i, offset, info);
7743                         break;
7744                 }
7745         }
7746         return status;
7747 }
7748
7749 /**
7750  * i40e_rollback_profile
7751  * @hw: pointer to the hardware structure
7752  * @profile: pointer to the profile segment of the package to be removed
7753  * @track_id: package tracking id
7754  *
7755  * Rolls back previously loaded package.
7756  */
7757 enum i40e_status_code
7758 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7759                       u32 track_id)
7760 {
7761         struct i40e_profile_section_header *sec = NULL;
7762         enum i40e_status_code status = I40E_SUCCESS;
7763         struct i40e_section_table *sec_tbl;
7764         u32 offset = 0, info = 0;
7765         u32 section_size = 0;
7766         u32 sec_off;
7767         int i;
7768
7769         status = i40e_validate_profile(hw, profile, track_id, true);
7770         if (status)
7771                 return status;
7772
7773         I40E_SECTION_TABLE(profile, sec_tbl);
7774
7775         /* For rollback write sections in reverse */
7776         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7777                 sec_off = sec_tbl->section_offset[i];
7778                 sec = I40E_SECTION_HEADER(profile, sec_off);
7779
7780                 /* Skip any non-rollback sections */
7781                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7782                         continue;
7783
7784                 section_size = sec->section.size +
7785                         sizeof(struct i40e_profile_section_header);
7786
7787                 /* Write roll-back MMIO section */
7788                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7789                                            track_id, &offset, &info, NULL);
7790                 if (status) {
7791                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7792                                    "Failed to write profile: section %d, offset %d, info %d\n",
7793                                    i, offset, info);
7794                         break;
7795                 }
7796         }
7797         return status;
7798 }
7799
7800 /**
7801  * i40e_add_pinfo_to_list
7802  * @hw: pointer to the hardware structure
7803  * @profile: pointer to the profile segment of the package
7804  * @profile_info_sec: buffer for information section
7805  * @track_id: package tracking id
7806  *
7807  * Register a profile to the list of loaded profiles.
7808  */
7809 enum i40e_status_code
7810 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7811                        struct i40e_profile_segment *profile,
7812                        u8 *profile_info_sec, u32 track_id)
7813 {
7814         enum i40e_status_code status = I40E_SUCCESS;
7815         struct i40e_profile_section_header *sec = NULL;
7816         struct i40e_profile_info *pinfo;
7817         u32 offset = 0, info = 0;
7818
7819         sec = (struct i40e_profile_section_header *)profile_info_sec;
7820         sec->tbl_size = 1;
7821         sec->data_end = sizeof(struct i40e_profile_section_header) +
7822                         sizeof(struct i40e_profile_info);
7823         sec->section.type = SECTION_TYPE_INFO;
7824         sec->section.offset = sizeof(struct i40e_profile_section_header);
7825         sec->section.size = sizeof(struct i40e_profile_info);
7826         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7827                                              sec->section.offset);
7828         pinfo->track_id = track_id;
7829         pinfo->version = profile->version;
7830         pinfo->op = I40E_DDP_ADD_TRACKID;
7831         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7832                     I40E_NONDMA_TO_NONDMA);
7833
7834         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7835                                    track_id, &offset, &info, NULL);
7836         return status;
7837 }