drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  18 {
  19         enum i40e_status_code status = I40E_SUCCESS;
  20
  21         DEBUGFUNC("i40e_set_mac_type\n");
  22
  23         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  24                 switch (hw->device_id) {
  25                 case I40E_DEV_ID_SFP_XL710:
  26                 case I40E_DEV_ID_QEMU:
  27                 case I40E_DEV_ID_KX_B:
  28                 case I40E_DEV_ID_KX_C:
  29                 case I40E_DEV_ID_QSFP_A:
  30                 case I40E_DEV_ID_QSFP_B:
  31                 case I40E_DEV_ID_QSFP_C:
  32                 case I40E_DEV_ID_10G_BASE_T:
  33                 case I40E_DEV_ID_10G_BASE_T4:
  34                 case I40E_DEV_ID_10G_BASE_T_BC:
  35                 case I40E_DEV_ID_10G_B:
  36                 case I40E_DEV_ID_10G_SFP:
  37                 case I40E_DEV_ID_5G_BASE_T_BC:
  38                 case I40E_DEV_ID_20G_KR2:
  39                 case I40E_DEV_ID_20G_KR2_A:
  40                 case I40E_DEV_ID_25G_B:
  41                 case I40E_DEV_ID_25G_SFP28:
  42                 case I40E_DEV_ID_X710_N3000:
  43                 case I40E_DEV_ID_XXV710_N3000:
  44                         hw->mac.type = I40E_MAC_XL710;
  45                         break;
  46 #ifdef X722_A0_SUPPORT
  47                 case I40E_DEV_ID_X722_A0:
  48 #endif
  49                 case I40E_DEV_ID_KX_X722:
  50                 case I40E_DEV_ID_QSFP_X722:
  51                 case I40E_DEV_ID_SFP_X722:
  52                 case I40E_DEV_ID_1G_BASE_T_X722:
  53                 case I40E_DEV_ID_10G_BASE_T_X722:
  54                 case I40E_DEV_ID_SFP_I_X722:
  55                         hw->mac.type = I40E_MAC_X722;
  56                         break;
  57 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  58                 case I40E_DEV_ID_X722_VF:
  59 #ifdef X722_A0_SUPPORT
  60                 case I40E_DEV_ID_X722_A0_VF:
  61 #endif
  62                         hw->mac.type = I40E_MAC_X722_VF;
  63                         break;
  64 #endif /* INTEGRATED_VF || VF_DRIVER */
  65 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  66                 case I40E_DEV_ID_VF:
  67                 case I40E_DEV_ID_VF_HV:
  68                 case I40E_DEV_ID_ADAPTIVE_VF:
  69                         hw->mac.type = I40E_MAC_VF;
  70                         break;
  71 #endif
  72                 default:
  73                         hw->mac.type = I40E_MAC_GENERIC;
  74                         break;
  75                 }
  76         } else {
  77                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  78         }
  79
  80         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  81                   hw->mac.type, status);
  82         return status;
  83 }
  84
  85 /**
  86  * i40e_aq_str - convert AQ err code to a string
  87  * @hw: pointer to the HW structure
  88  * @aq_err: the AQ error code to convert
  89  **/
  90 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  91 {
  92         switch (aq_err) {
  93         case I40E_AQ_RC_OK:
  94                 return "OK";
  95         case I40E_AQ_RC_EPERM:
  96                 return "I40E_AQ_RC_EPERM";
  97         case I40E_AQ_RC_ENOENT:
  98                 return "I40E_AQ_RC_ENOENT";
  99         case I40E_AQ_RC_ESRCH:
 100                 return "I40E_AQ_RC_ESRCH";
 101         case I40E_AQ_RC_EINTR:
 102                 return "I40E_AQ_RC_EINTR";
 103         case I40E_AQ_RC_EIO:
 104                 return "I40E_AQ_RC_EIO";
 105         case I40E_AQ_RC_ENXIO:
 106                 return "I40E_AQ_RC_ENXIO";
 107         case I40E_AQ_RC_E2BIG:
 108                 return "I40E_AQ_RC_E2BIG";
 109         case I40E_AQ_RC_EAGAIN:
 110                 return "I40E_AQ_RC_EAGAIN";
 111         case I40E_AQ_RC_ENOMEM:
 112                 return "I40E_AQ_RC_ENOMEM";
 113         case I40E_AQ_RC_EACCES:
 114                 return "I40E_AQ_RC_EACCES";
 115         case I40E_AQ_RC_EFAULT:
 116                 return "I40E_AQ_RC_EFAULT";
 117         case I40E_AQ_RC_EBUSY:
 118                 return "I40E_AQ_RC_EBUSY";
 119         case I40E_AQ_RC_EEXIST:
 120                 return "I40E_AQ_RC_EEXIST";
 121         case I40E_AQ_RC_EINVAL:
 122                 return "I40E_AQ_RC_EINVAL";
 123         case I40E_AQ_RC_ENOTTY:
 124                 return "I40E_AQ_RC_ENOTTY";
 125         case I40E_AQ_RC_ENOSPC:
 126                 return "I40E_AQ_RC_ENOSPC";
 127         case I40E_AQ_RC_ENOSYS:
 128                 return "I40E_AQ_RC_ENOSYS";
 129         case I40E_AQ_RC_ERANGE:
 130                 return "I40E_AQ_RC_ERANGE";
 131         case I40E_AQ_RC_EFLUSHED:
 132                 return "I40E_AQ_RC_EFLUSHED";
 133         case I40E_AQ_RC_BAD_ADDR:
 134                 return "I40E_AQ_RC_BAD_ADDR";
 135         case I40E_AQ_RC_EMODE:
 136                 return "I40E_AQ_RC_EMODE";
 137         case I40E_AQ_RC_EFBIG:
 138                 return "I40E_AQ_RC_EFBIG";
 139         }
 140
 141         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 142         return hw->err_str;
 143 }
 144
 145 /**
 146  * i40e_stat_str - convert status err code to a string
 147  * @hw: pointer to the HW structure
 148  * @stat_err: the status error code to convert
 149  **/
 150 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 151 {
 152         switch (stat_err) {
 153         case I40E_SUCCESS:
 154                 return "OK";
 155         case I40E_ERR_NVM:
 156                 return "I40E_ERR_NVM";
 157         case I40E_ERR_NVM_CHECKSUM:
 158                 return "I40E_ERR_NVM_CHECKSUM";
 159         case I40E_ERR_PHY:
 160                 return "I40E_ERR_PHY";
 161         case I40E_ERR_CONFIG:
 162                 return "I40E_ERR_CONFIG";
 163         case I40E_ERR_PARAM:
 164                 return "I40E_ERR_PARAM";
 165         case I40E_ERR_MAC_TYPE:
 166                 return "I40E_ERR_MAC_TYPE";
 167         case I40E_ERR_UNKNOWN_PHY:
 168                 return "I40E_ERR_UNKNOWN_PHY";
 169         case I40E_ERR_LINK_SETUP:
 170                 return "I40E_ERR_LINK_SETUP";
 171         case I40E_ERR_ADAPTER_STOPPED:
 172                 return "I40E_ERR_ADAPTER_STOPPED";
 173         case I40E_ERR_INVALID_MAC_ADDR:
 174                 return "I40E_ERR_INVALID_MAC_ADDR";
 175         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 176                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 177         case I40E_ERR_MASTER_REQUESTS_PENDING:
 178                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 179         case I40E_ERR_INVALID_LINK_SETTINGS:
 180                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 181         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 182                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 183         case I40E_ERR_RESET_FAILED:
 184                 return "I40E_ERR_RESET_FAILED";
 185         case I40E_ERR_SWFW_SYNC:
 186                 return "I40E_ERR_SWFW_SYNC";
 187         case I40E_ERR_NO_AVAILABLE_VSI:
 188                 return "I40E_ERR_NO_AVAILABLE_VSI";
 189         case I40E_ERR_NO_MEMORY:
 190                 return "I40E_ERR_NO_MEMORY";
 191         case I40E_ERR_BAD_PTR:
 192                 return "I40E_ERR_BAD_PTR";
 193         case I40E_ERR_RING_FULL:
 194                 return "I40E_ERR_RING_FULL";
 195         case I40E_ERR_INVALID_PD_ID:
 196                 return "I40E_ERR_INVALID_PD_ID";
 197         case I40E_ERR_INVALID_QP_ID:
 198                 return "I40E_ERR_INVALID_QP_ID";
 199         case I40E_ERR_INVALID_CQ_ID:
 200                 return "I40E_ERR_INVALID_CQ_ID";
 201         case I40E_ERR_INVALID_CEQ_ID:
 202                 return "I40E_ERR_INVALID_CEQ_ID";
 203         case I40E_ERR_INVALID_AEQ_ID:
 204                 return "I40E_ERR_INVALID_AEQ_ID";
 205         case I40E_ERR_INVALID_SIZE:
 206                 return "I40E_ERR_INVALID_SIZE";
 207         case I40E_ERR_INVALID_ARP_INDEX:
 208                 return "I40E_ERR_INVALID_ARP_INDEX";
 209         case I40E_ERR_INVALID_FPM_FUNC_ID:
 210                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 211         case I40E_ERR_QP_INVALID_MSG_SIZE:
 212                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 213         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 214                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 215         case I40E_ERR_INVALID_FRAG_COUNT:
 216                 return "I40E_ERR_INVALID_FRAG_COUNT";
 217         case I40E_ERR_QUEUE_EMPTY:
 218                 return "I40E_ERR_QUEUE_EMPTY";
 219         case I40E_ERR_INVALID_ALIGNMENT:
 220                 return "I40E_ERR_INVALID_ALIGNMENT";
 221         case I40E_ERR_FLUSHED_QUEUE:
 222                 return "I40E_ERR_FLUSHED_QUEUE";
 223         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 224                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 225         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 226                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 227         case I40E_ERR_TIMEOUT:
 228                 return "I40E_ERR_TIMEOUT";
 229         case I40E_ERR_OPCODE_MISMATCH:
 230                 return "I40E_ERR_OPCODE_MISMATCH";
 231         case I40E_ERR_CQP_COMPL_ERROR:
 232                 return "I40E_ERR_CQP_COMPL_ERROR";
 233         case I40E_ERR_INVALID_VF_ID:
 234                 return "I40E_ERR_INVALID_VF_ID";
 235         case I40E_ERR_INVALID_HMCFN_ID:
 236                 return "I40E_ERR_INVALID_HMCFN_ID";
 237         case I40E_ERR_BACKING_PAGE_ERROR:
 238                 return "I40E_ERR_BACKING_PAGE_ERROR";
 239         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 240                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 241         case I40E_ERR_INVALID_PBLE_INDEX:
 242                 return "I40E_ERR_INVALID_PBLE_INDEX";
 243         case I40E_ERR_INVALID_SD_INDEX:
 244                 return "I40E_ERR_INVALID_SD_INDEX";
 245         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 246                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 247         case I40E_ERR_INVALID_SD_TYPE:
 248                 return "I40E_ERR_INVALID_SD_TYPE";
 249         case I40E_ERR_MEMCPY_FAILED:
 250                 return "I40E_ERR_MEMCPY_FAILED";
 251         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 252                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 253         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 254                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 255         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 256                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 257         case I40E_ERR_SRQ_ENABLED:
 258                 return "I40E_ERR_SRQ_ENABLED";
 259         case I40E_ERR_ADMIN_QUEUE_ERROR:
 260                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 261         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 262                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 263         case I40E_ERR_BUF_TOO_SHORT:
 264                 return "I40E_ERR_BUF_TOO_SHORT";
 265         case I40E_ERR_ADMIN_QUEUE_FULL:
 266                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 267         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 268                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 269         case I40E_ERR_BAD_IWARP_CQE:
 270                 return "I40E_ERR_BAD_IWARP_CQE";
 271         case I40E_ERR_NVM_BLANK_MODE:
 272                 return "I40E_ERR_NVM_BLANK_MODE";
 273         case I40E_ERR_NOT_IMPLEMENTED:
 274                 return "I40E_ERR_NOT_IMPLEMENTED";
 275         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 276                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 277         case I40E_ERR_DIAG_TEST_FAILED:
 278                 return "I40E_ERR_DIAG_TEST_FAILED";
 279         case I40E_ERR_NOT_READY:
 280                 return "I40E_ERR_NOT_READY";
 281         case I40E_NOT_SUPPORTED:
 282                 return "I40E_NOT_SUPPORTED";
 283         case I40E_ERR_FIRMWARE_API_VERSION:
 284                 return "I40E_ERR_FIRMWARE_API_VERSION";
 285         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 286                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 287         }
 288
 289         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 290         return hw->err_str;
 291 }
 292
 293 /**
 294  * i40e_debug_aq
 295  * @hw: debug mask related to admin queue
 296  * @mask: debug mask
 297  * @desc: pointer to admin queue descriptor
 298  * @buffer: pointer to command buffer
 299  * @buf_len: max length of buffer
 300  *
 301  * Dumps debug log about adminq command with descriptor contents.
 302  **/
 303 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 304                    void *buffer, u16 buf_len)
 305 {
 306         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 307         u32 effective_mask = hw->debug_mask & mask;
 308         u8 *buf = (u8 *)buffer;
 309         u16 len;
 310         u16 i;
 311
 312         if (!effective_mask || !desc)
 313                 return;
 314
 315         len = LE16_TO_CPU(aq_desc->datalen);
 316
 317         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 318                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 319                    LE16_TO_CPU(aq_desc->opcode),
 320                    LE16_TO_CPU(aq_desc->flags),
 321                    LE16_TO_CPU(aq_desc->datalen),
 322                    LE16_TO_CPU(aq_desc->retval));
 323         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 324                    "\tcookie (h,l) 0x%08X 0x%08X\n",
 325                    LE32_TO_CPU(aq_desc->cookie_high),
 326                    LE32_TO_CPU(aq_desc->cookie_low));
 327         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 328                    "\tparam (0,1)  0x%08X 0x%08X\n",
 329                    LE32_TO_CPU(aq_desc->params.internal.param0),
 330                    LE32_TO_CPU(aq_desc->params.internal.param1));
 331         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 332                    "\taddr (h,l)   0x%08X 0x%08X\n",
 333                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 334                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 335
 336         if (buffer && (buf_len != 0) && (len != 0) &&
 337             (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
 338                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 339                 if (buf_len < len)
 340                         len = buf_len;
 341                 /* write the full 16-byte chunks */
 342                 for (i = 0; i < (len - 16); i += 16)
 343                         i40e_debug(hw, mask,
 344                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 345                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 346                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 347                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 348                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 349                 /* the most we could have left is 16 bytes, pad with zeros */
 350                 if (i < len) {
 351                         char d_buf[16];
 352                         int j, i_sav;
 353
 354                         i_sav = i;
 355                         memset(d_buf, 0, sizeof(d_buf));
 356                         for (j = 0; i < len; j++, i++)
 357                                 d_buf[j] = buf[i];
 358                         i40e_debug(hw, mask,
 359                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 360                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 361                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 362                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 363                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 364                 }
 365         }
 366 }
 367
 368 /**
 369  * i40e_check_asq_alive
 370  * @hw: pointer to the hw struct
 371  *
 372  * Returns true if Queue is enabled else false.
 373  **/
 374 bool i40e_check_asq_alive(struct i40e_hw *hw)
 375 {
 376         if (hw->aq.asq.len)
 377 #ifdef PF_DRIVER
 378 #ifdef INTEGRATED_VF
 379                 if (!i40e_is_vf(hw))
 380                         return !!(rd32(hw, hw->aq.asq.len) &
 381                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 382 #else
 383                 return !!(rd32(hw, hw->aq.asq.len) &
 384                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 385 #endif /* INTEGRATED_VF */
 386 #endif /* PF_DRIVER */
 387 #ifdef VF_DRIVER
 388 #ifdef INTEGRATED_VF
 389                 if (i40e_is_vf(hw))
 390                         return !!(rd32(hw, hw->aq.asq.len) &
 391                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 392 #else
 393                 return !!(rd32(hw, hw->aq.asq.len) &
 394                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 395 #endif /* INTEGRATED_VF */
 396 #endif /* VF_DRIVER */
 397         return false;
 398 }
 399
 400 /**
 401  * i40e_aq_queue_shutdown
 402  * @hw: pointer to the hw struct
 403  * @unloading: is the driver unloading itself
 404  *
 405  * Tell the Firmware that we're shutting down the AdminQ and whether
 406  * or not the driver is unloading as well.
 407  **/
 408 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 409                                              bool unloading)
 410 {
 411         struct i40e_aq_desc desc;
 412         struct i40e_aqc_queue_shutdown *cmd =
 413                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 414         enum i40e_status_code status;
 415
 416         i40e_fill_default_direct_cmd_desc(&desc,
 417                                           i40e_aqc_opc_queue_shutdown);
 418
 419         if (unloading)
 420                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 421         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 422
 423         return status;
 424 }
 425
 426 /**
 427  * i40e_aq_get_set_rss_lut
 428  * @hw: pointer to the hardware structure
 429  * @vsi_id: vsi fw index
 430  * @pf_lut: for PF table set true, for VSI table set false
 431  * @lut: pointer to the lut buffer provided by the caller
 432  * @lut_size: size of the lut buffer
 433  * @set: set true to set the table, false to get the table
 434  *
 435  * Internal function to get or set RSS look up table
 436  **/
 437 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 438                                                      u16 vsi_id, bool pf_lut,
 439                                                      u8 *lut, u16 lut_size,
 440                                                      bool set)
 441 {
 442         enum i40e_status_code status;
 443         struct i40e_aq_desc desc;
 444         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 445                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 446
 447         if (set)
 448                 i40e_fill_default_direct_cmd_desc(&desc,
 449                                                   i40e_aqc_opc_set_rss_lut);
 450         else
 451                 i40e_fill_default_direct_cmd_desc(&desc,
 452                                                   i40e_aqc_opc_get_rss_lut);
 453
 454         /* Indirect command */
 455         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 456         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 457
 458         cmd_resp->vsi_id =
 459                         CPU_TO_LE16((u16)((vsi_id <<
 460                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 461                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 462         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 463
 464         if (pf_lut)
 465                 cmd_resp->flags |= CPU_TO_LE16((u16)
 466                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 467                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 468                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 469         else
 470                 cmd_resp->flags |= CPU_TO_LE16((u16)
 471                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 472                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 473                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 474
 475         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 476
 477         return status;
 478 }
 479
 480 /**
 481  * i40e_aq_get_rss_lut
 482  * @hw: pointer to the hardware structure
 483  * @vsi_id: vsi fw index
 484  * @pf_lut: for PF table set true, for VSI table set false
 485  * @lut: pointer to the lut buffer provided by the caller
 486  * @lut_size: size of the lut buffer
 487  *
 488  * get the RSS lookup table, PF or VSI type
 489  **/
 490 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 491                                           bool pf_lut, u8 *lut, u16 lut_size)
 492 {
 493         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 494                                        false);
 495 }
 496
 497 /**
 498  * i40e_aq_set_rss_lut
 499  * @hw: pointer to the hardware structure
 500  * @vsi_id: vsi fw index
 501  * @pf_lut: for PF table set true, for VSI table set false
 502  * @lut: pointer to the lut buffer provided by the caller
 503  * @lut_size: size of the lut buffer
 504  *
 505  * set the RSS lookup table, PF or VSI type
 506  **/
 507 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 508                                           bool pf_lut, u8 *lut, u16 lut_size)
 509 {
 510         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 511 }
 512
 513 /**
 514  * i40e_aq_get_set_rss_key
 515  * @hw: pointer to the hw struct
 516  * @vsi_id: vsi fw index
 517  * @key: pointer to key info struct
 518  * @set: set true to set the key, false to get the key
 519  *
 520  * get the RSS key per VSI
 521  **/
 522 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 523                                       u16 vsi_id,
 524                                       struct i40e_aqc_get_set_rss_key_data *key,
 525                                       bool set)
 526 {
 527         enum i40e_status_code status;
 528         struct i40e_aq_desc desc;
 529         struct i40e_aqc_get_set_rss_key *cmd_resp =
 530                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 531         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 532
 533         if (set)
 534                 i40e_fill_default_direct_cmd_desc(&desc,
 535                                                   i40e_aqc_opc_set_rss_key);
 536         else
 537                 i40e_fill_default_direct_cmd_desc(&desc,
 538                                                   i40e_aqc_opc_get_rss_key);
 539
 540         /* Indirect command */
 541         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 542         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 543
 544         cmd_resp->vsi_id =
 545                         CPU_TO_LE16((u16)((vsi_id <<
 546                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 547                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 548         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 549
 550         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 551
 552         return status;
 553 }
 554
 555 /**
 556  * i40e_aq_get_rss_key
 557  * @hw: pointer to the hw struct
 558  * @vsi_id: vsi fw index
 559  * @key: pointer to key info struct
 560  *
 561  **/
 562 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 563                                       u16 vsi_id,
 564                                       struct i40e_aqc_get_set_rss_key_data *key)
 565 {
 566         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 567 }
 568
 569 /**
 570  * i40e_aq_set_rss_key
 571  * @hw: pointer to the hw struct
 572  * @vsi_id: vsi fw index
 573  * @key: pointer to key info struct
 574  *
 575  * set the RSS key per VSI
 576  **/
 577 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 578                                       u16 vsi_id,
 579                                       struct i40e_aqc_get_set_rss_key_data *key)
 580 {
 581         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 582 }
 583
 584 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 585  * hardware to a bit-field that can be used by SW to more easily determine the
 586  * packet type.
 587  *
 588  * Macros are used to shorten the table lines and make this table human
 589  * readable.
 590  *
 591  * We store the PTYPE in the top byte of the bit field - this is just so that
 592  * we can check that the table doesn't have a row missing, as the index into
 593  * the table should be the PTYPE.
 594  *
 595  * Typical work flow:
 596  *
 597  * IF NOT i40e_ptype_lookup[ptype].known
 598  * THEN
 599  *      Packet is unknown
 600  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 601  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 602  * ELSE
 603  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 604  * ENDIF
 605  */
 606
 607 /* macro to make the table lines short */
 608 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 609         {       PTYPE, \
 610                 1, \
 611                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 612                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 613                 I40E_RX_PTYPE_##OUTER_FRAG, \
 614                 I40E_RX_PTYPE_TUNNEL_##T, \
 615                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 616                 I40E_RX_PTYPE_##TEF, \
 617                 I40E_RX_PTYPE_INNER_PROT_##I, \
 618                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 619
 620 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 621                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 622
 623 /* shorter macros makes the table fit but are terse */
 624 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 625 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 626 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 627
 628 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 629 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 630         /* L2 Packet types */
 631         I40E_PTT_UNUSED_ENTRY(0),
 632         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 633         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 634         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 635         I40E_PTT_UNUSED_ENTRY(4),
 636         I40E_PTT_UNUSED_ENTRY(5),
 637         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 638         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 639         I40E_PTT_UNUSED_ENTRY(8),
 640         I40E_PTT_UNUSED_ENTRY(9),
 641         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 642         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 643         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 651         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 652         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 653
 654         /* Non Tunneled IPv4 */
 655         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 656         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 657         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 658         I40E_PTT_UNUSED_ENTRY(25),
 659         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 660         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 661         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 662
 663         /* IPv4 --> IPv4 */
 664         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 665         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 666         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 667         I40E_PTT_UNUSED_ENTRY(32),
 668         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 669         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 670         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 671
 672         /* IPv4 --> IPv6 */
 673         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 674         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 675         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 676         I40E_PTT_UNUSED_ENTRY(39),
 677         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 678         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 679         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 680
 681         /* IPv4 --> GRE/NAT */
 682         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 683
 684         /* IPv4 --> GRE/NAT --> IPv4 */
 685         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 686         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 687         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 688         I40E_PTT_UNUSED_ENTRY(47),
 689         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 690         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 691         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 692
 693         /* IPv4 --> GRE/NAT --> IPv6 */
 694         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 695         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 696         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 697         I40E_PTT_UNUSED_ENTRY(54),
 698         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 699         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 700         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 701
 702         /* IPv4 --> GRE/NAT --> MAC */
 703         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 704
 705         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 706         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 707         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 708         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 709         I40E_PTT_UNUSED_ENTRY(62),
 710         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 711         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 712         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 713
 714         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 715         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 716         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 717         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 718         I40E_PTT_UNUSED_ENTRY(69),
 719         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 720         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 721         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 722
 723         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 724         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 725
 726         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 727         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 728         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 729         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 730         I40E_PTT_UNUSED_ENTRY(77),
 731         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 732         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 733         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 734
 735         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 736         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 737         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 738         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 739         I40E_PTT_UNUSED_ENTRY(84),
 740         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 741         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 742         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 743
 744         /* Non Tunneled IPv6 */
 745         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 746         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 747         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 748         I40E_PTT_UNUSED_ENTRY(91),
 749         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 750         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 751         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 752
 753         /* IPv6 --> IPv4 */
 754         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 755         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 756         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 757         I40E_PTT_UNUSED_ENTRY(98),
 758         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 759         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 760         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 761
 762         /* IPv6 --> IPv6 */
 763         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 764         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 765         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 766         I40E_PTT_UNUSED_ENTRY(105),
 767         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 768         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 769         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 770
 771         /* IPv6 --> GRE/NAT */
 772         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 773
 774         /* IPv6 --> GRE/NAT -> IPv4 */
 775         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 776         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 777         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 778         I40E_PTT_UNUSED_ENTRY(113),
 779         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 780         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 781         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 782
 783         /* IPv6 --> GRE/NAT -> IPv6 */
 784         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 785         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 786         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 787         I40E_PTT_UNUSED_ENTRY(120),
 788         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 789         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 790         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 791
 792         /* IPv6 --> GRE/NAT -> MAC */
 793         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 794
 795         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 796         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 797         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 798         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 799         I40E_PTT_UNUSED_ENTRY(128),
 800         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 801         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 802         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 803
 804         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 805         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 806         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 807         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 808         I40E_PTT_UNUSED_ENTRY(135),
 809         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 810         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 811         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 812
 813         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 814         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 815
 816         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 817         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 818         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 819         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 820         I40E_PTT_UNUSED_ENTRY(143),
 821         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 822         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 823         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 824
 825         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 826         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 827         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 828         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 829         I40E_PTT_UNUSED_ENTRY(150),
 830         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 831         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 832         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 833
 834         /* unused entries */
 835         I40E_PTT_UNUSED_ENTRY(154),
 836         I40E_PTT_UNUSED_ENTRY(155),
 837         I40E_PTT_UNUSED_ENTRY(156),
 838         I40E_PTT_UNUSED_ENTRY(157),
 839         I40E_PTT_UNUSED_ENTRY(158),
 840         I40E_PTT_UNUSED_ENTRY(159),
 841
 842         I40E_PTT_UNUSED_ENTRY(160),
 843         I40E_PTT_UNUSED_ENTRY(161),
 844         I40E_PTT_UNUSED_ENTRY(162),
 845         I40E_PTT_UNUSED_ENTRY(163),
 846         I40E_PTT_UNUSED_ENTRY(164),
 847         I40E_PTT_UNUSED_ENTRY(165),
 848         I40E_PTT_UNUSED_ENTRY(166),
 849         I40E_PTT_UNUSED_ENTRY(167),
 850         I40E_PTT_UNUSED_ENTRY(168),
 851         I40E_PTT_UNUSED_ENTRY(169),
 852
 853         I40E_PTT_UNUSED_ENTRY(170),
 854         I40E_PTT_UNUSED_ENTRY(171),
 855         I40E_PTT_UNUSED_ENTRY(172),
 856         I40E_PTT_UNUSED_ENTRY(173),
 857         I40E_PTT_UNUSED_ENTRY(174),
 858         I40E_PTT_UNUSED_ENTRY(175),
 859         I40E_PTT_UNUSED_ENTRY(176),
 860         I40E_PTT_UNUSED_ENTRY(177),
 861         I40E_PTT_UNUSED_ENTRY(178),
 862         I40E_PTT_UNUSED_ENTRY(179),
 863
 864         I40E_PTT_UNUSED_ENTRY(180),
 865         I40E_PTT_UNUSED_ENTRY(181),
 866         I40E_PTT_UNUSED_ENTRY(182),
 867         I40E_PTT_UNUSED_ENTRY(183),
 868         I40E_PTT_UNUSED_ENTRY(184),
 869         I40E_PTT_UNUSED_ENTRY(185),
 870         I40E_PTT_UNUSED_ENTRY(186),
 871         I40E_PTT_UNUSED_ENTRY(187),
 872         I40E_PTT_UNUSED_ENTRY(188),
 873         I40E_PTT_UNUSED_ENTRY(189),
 874
 875         I40E_PTT_UNUSED_ENTRY(190),
 876         I40E_PTT_UNUSED_ENTRY(191),
 877         I40E_PTT_UNUSED_ENTRY(192),
 878         I40E_PTT_UNUSED_ENTRY(193),
 879         I40E_PTT_UNUSED_ENTRY(194),
 880         I40E_PTT_UNUSED_ENTRY(195),
 881         I40E_PTT_UNUSED_ENTRY(196),
 882         I40E_PTT_UNUSED_ENTRY(197),
 883         I40E_PTT_UNUSED_ENTRY(198),
 884         I40E_PTT_UNUSED_ENTRY(199),
 885
 886         I40E_PTT_UNUSED_ENTRY(200),
 887         I40E_PTT_UNUSED_ENTRY(201),
 888         I40E_PTT_UNUSED_ENTRY(202),
 889         I40E_PTT_UNUSED_ENTRY(203),
 890         I40E_PTT_UNUSED_ENTRY(204),
 891         I40E_PTT_UNUSED_ENTRY(205),
 892         I40E_PTT_UNUSED_ENTRY(206),
 893         I40E_PTT_UNUSED_ENTRY(207),
 894         I40E_PTT_UNUSED_ENTRY(208),
 895         I40E_PTT_UNUSED_ENTRY(209),
 896
 897         I40E_PTT_UNUSED_ENTRY(210),
 898         I40E_PTT_UNUSED_ENTRY(211),
 899         I40E_PTT_UNUSED_ENTRY(212),
 900         I40E_PTT_UNUSED_ENTRY(213),
 901         I40E_PTT_UNUSED_ENTRY(214),
 902         I40E_PTT_UNUSED_ENTRY(215),
 903         I40E_PTT_UNUSED_ENTRY(216),
 904         I40E_PTT_UNUSED_ENTRY(217),
 905         I40E_PTT_UNUSED_ENTRY(218),
 906         I40E_PTT_UNUSED_ENTRY(219),
 907
 908         I40E_PTT_UNUSED_ENTRY(220),
 909         I40E_PTT_UNUSED_ENTRY(221),
 910         I40E_PTT_UNUSED_ENTRY(222),
 911         I40E_PTT_UNUSED_ENTRY(223),
 912         I40E_PTT_UNUSED_ENTRY(224),
 913         I40E_PTT_UNUSED_ENTRY(225),
 914         I40E_PTT_UNUSED_ENTRY(226),
 915         I40E_PTT_UNUSED_ENTRY(227),
 916         I40E_PTT_UNUSED_ENTRY(228),
 917         I40E_PTT_UNUSED_ENTRY(229),
 918
 919         I40E_PTT_UNUSED_ENTRY(230),
 920         I40E_PTT_UNUSED_ENTRY(231),
 921         I40E_PTT_UNUSED_ENTRY(232),
 922         I40E_PTT_UNUSED_ENTRY(233),
 923         I40E_PTT_UNUSED_ENTRY(234),
 924         I40E_PTT_UNUSED_ENTRY(235),
 925         I40E_PTT_UNUSED_ENTRY(236),
 926         I40E_PTT_UNUSED_ENTRY(237),
 927         I40E_PTT_UNUSED_ENTRY(238),
 928         I40E_PTT_UNUSED_ENTRY(239),
 929
 930         I40E_PTT_UNUSED_ENTRY(240),
 931         I40E_PTT_UNUSED_ENTRY(241),
 932         I40E_PTT_UNUSED_ENTRY(242),
 933         I40E_PTT_UNUSED_ENTRY(243),
 934         I40E_PTT_UNUSED_ENTRY(244),
 935         I40E_PTT_UNUSED_ENTRY(245),
 936         I40E_PTT_UNUSED_ENTRY(246),
 937         I40E_PTT_UNUSED_ENTRY(247),
 938         I40E_PTT_UNUSED_ENTRY(248),
 939         I40E_PTT_UNUSED_ENTRY(249),
 940
 941         I40E_PTT_UNUSED_ENTRY(250),
 942         I40E_PTT_UNUSED_ENTRY(251),
 943         I40E_PTT_UNUSED_ENTRY(252),
 944         I40E_PTT_UNUSED_ENTRY(253),
 945         I40E_PTT_UNUSED_ENTRY(254),
 946         I40E_PTT_UNUSED_ENTRY(255)
 947 };
 948
 949
 950 /**
 951  * i40e_validate_mac_addr - Validate unicast MAC address
 952  * @mac_addr: pointer to MAC address
 953  *
 954  * Tests a MAC address to ensure it is a valid Individual Address
 955  **/
 956 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 957 {
 958         enum i40e_status_code status = I40E_SUCCESS;
 959
 960         DEBUGFUNC("i40e_validate_mac_addr");
 961
 962         /* Broadcast addresses ARE multicast addresses
 963          * Make sure it is not a multicast address
 964          * Reject the zero address
 965          */
 966         if (I40E_IS_MULTICAST(mac_addr) ||
 967             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 968               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 969                 status = I40E_ERR_INVALID_MAC_ADDR;
 970
 971         return status;
 972 }
 973 #ifdef PF_DRIVER
 974
 975 /**
 976  * i40e_init_shared_code - Initialize the shared code
 977  * @hw: pointer to hardware structure
 978  *
 979  * This assigns the MAC type and PHY code and inits the NVM.
 980  * Does not touch the hardware. This function must be called prior to any
 981  * other function in the shared code. The i40e_hw structure should be
 982  * memset to 0 prior to calling this function.  The following fields in
 983  * hw structure should be filled in prior to calling this function:
 984  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 985  * subsystem_vendor_id, and revision_id
 986  **/
 987 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 988 {
 989         enum i40e_status_code status = I40E_SUCCESS;
 990         u32 port, ari, func_rid;
 991
 992         DEBUGFUNC("i40e_init_shared_code");
 993
 994         i40e_set_mac_type(hw);
 995
 996         switch (hw->mac.type) {
 997         case I40E_MAC_XL710:
 998         case I40E_MAC_X722:
 999                 break;
1000         default:
1001                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1002         }
1003
1004         hw->phy.get_link_info = true;
1005
1006         /* Determine port number and PF number*/
1007         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1008                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1009         hw->port = (u8)port;
1010         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1011                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1012         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1013         if (ari)
1014                 hw->pf_id = (u8)(func_rid & 0xff);
1015         else
1016                 hw->pf_id = (u8)(func_rid & 0x7);
1017
1018         if (hw->mac.type == I40E_MAC_X722)
1019                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1020                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1021         /* NVMUpdate features structure initialization */
1022         hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1023         hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1024         hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1025         i40e_memset(hw->nvmupd_features.features, 0x0,
1026                     I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1027                     sizeof(*hw->nvmupd_features.features),
1028                     I40E_NONDMA_MEM);
1029
1030         /* No features supported at the moment */
1031         hw->nvmupd_features.features[0] = 0;
1032
1033         status = i40e_init_nvm(hw);
1034         return status;
1035 }
1036
1037 /**
1038  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1039  * @hw: pointer to the hw struct
1040  * @flags: a return indicator of what addresses were added to the addr store
1041  * @addrs: the requestor's mac addr store
1042  * @cmd_details: pointer to command details structure or NULL
1043  **/
1044 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1045                                    u16 *flags,
1046                                    struct i40e_aqc_mac_address_read_data *addrs,
1047                                    struct i40e_asq_cmd_details *cmd_details)
1048 {
1049         struct i40e_aq_desc desc;
1050         struct i40e_aqc_mac_address_read *cmd_data =
1051                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1052         enum i40e_status_code status;
1053
1054         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1055         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1056
1057         status = i40e_asq_send_command(hw, &desc, addrs,
1058                                        sizeof(*addrs), cmd_details);
1059         *flags = LE16_TO_CPU(cmd_data->command_flags);
1060
1061         return status;
1062 }
1063
1064 /**
1065  * i40e_aq_mac_address_write - Change the MAC addresses
1066  * @hw: pointer to the hw struct
1067  * @flags: indicates which MAC to be written
1068  * @mac_addr: address to write
1069  * @cmd_details: pointer to command details structure or NULL
1070  **/
1071 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1072                                     u16 flags, u8 *mac_addr,
1073                                     struct i40e_asq_cmd_details *cmd_details)
1074 {
1075         struct i40e_aq_desc desc;
1076         struct i40e_aqc_mac_address_write *cmd_data =
1077                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1078         enum i40e_status_code status;
1079
1080         i40e_fill_default_direct_cmd_desc(&desc,
1081                                           i40e_aqc_opc_mac_address_write);
1082         cmd_data->command_flags = CPU_TO_LE16(flags);
1083         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1084         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1085                                         ((u32)mac_addr[3] << 16) |
1086                                         ((u32)mac_addr[4] << 8) |
1087                                         mac_addr[5]);
1088
1089         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1090
1091         return status;
1092 }
1093
1094 /**
1095  * i40e_get_mac_addr - get MAC address
1096  * @hw: pointer to the HW structure
1097  * @mac_addr: pointer to MAC address
1098  *
1099  * Reads the adapter's MAC address from register
1100  **/
1101 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1102 {
1103         struct i40e_aqc_mac_address_read_data addrs;
1104         enum i40e_status_code status;
1105         u16 flags = 0;
1106
1107         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1108
1109         if (flags & I40E_AQC_LAN_ADDR_VALID)
1110                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1111                         I40E_NONDMA_TO_NONDMA);
1112
1113         return status;
1114 }
1115
1116 /**
1117  * i40e_get_port_mac_addr - get Port MAC address
1118  * @hw: pointer to the HW structure
1119  * @mac_addr: pointer to Port MAC address
1120  *
1121  * Reads the adapter's Port MAC address
1122  **/
1123 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1124 {
1125         struct i40e_aqc_mac_address_read_data addrs;
1126         enum i40e_status_code status;
1127         u16 flags = 0;
1128
1129         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1130         if (status)
1131                 return status;
1132
1133         if (flags & I40E_AQC_PORT_ADDR_VALID)
1134                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1135                         I40E_NONDMA_TO_NONDMA);
1136         else
1137                 status = I40E_ERR_INVALID_MAC_ADDR;
1138
1139         return status;
1140 }
1141
1142 /**
1143  * i40e_pre_tx_queue_cfg - pre tx queue configure
1144  * @hw: pointer to the HW structure
1145  * @queue: target pf queue index
1146  * @enable: state change request
1147  *
1148  * Handles hw requirement to indicate intention to enable
1149  * or disable target queue.
1150  **/
1151 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1152 {
1153         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1154         u32 reg_block = 0;
1155         u32 reg_val;
1156
1157         if (abs_queue_idx >= 128) {
1158                 reg_block = abs_queue_idx / 128;
1159                 abs_queue_idx %= 128;
1160         }
1161
1162         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1163         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1164         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1165
1166         if (enable)
1167                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1168         else
1169                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1170
1171         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1172 }
1173
1174 /**
1175  * i40e_get_san_mac_addr - get SAN MAC address
1176  * @hw: pointer to the HW structure
1177  * @mac_addr: pointer to SAN MAC address
1178  *
1179  * Reads the adapter's SAN MAC address from NVM
1180  **/
1181 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1182                                             u8 *mac_addr)
1183 {
1184         struct i40e_aqc_mac_address_read_data addrs;
1185         enum i40e_status_code status;
1186         u16 flags = 0;
1187
1188         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1189         if (status)
1190                 return status;
1191
1192         if (flags & I40E_AQC_SAN_ADDR_VALID)
1193                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1194                         I40E_NONDMA_TO_NONDMA);
1195         else
1196                 status = I40E_ERR_INVALID_MAC_ADDR;
1197
1198         return status;
1199 }
1200
1201 /**
1202  *  i40e_read_pba_string - Reads part number string from EEPROM
1203  *  @hw: pointer to hardware structure
1204  *  @pba_num: stores the part number string from the EEPROM
1205  *  @pba_num_size: part number string buffer length
1206  *
1207  *  Reads the part number string from the EEPROM.
1208  **/
1209 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1210                                             u32 pba_num_size)
1211 {
1212         enum i40e_status_code status = I40E_SUCCESS;
1213         u16 pba_word = 0;
1214         u16 pba_size = 0;
1215         u16 pba_ptr = 0;
1216         u16 i = 0;
1217
1218         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1219         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1220                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1221                 return status;
1222         }
1223
1224         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1225         if (status != I40E_SUCCESS) {
1226                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1227                 return status;
1228         }
1229
1230         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1231         if (status != I40E_SUCCESS) {
1232                 DEBUGOUT("Failed to read PBA Block size.\n");
1233                 return status;
1234         }
1235
1236         /* Subtract one to get PBA word count (PBA Size word is included in
1237          * total size)
1238          */
1239         pba_size--;
1240         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1241                 DEBUGOUT("Buffer to small for PBA data.\n");
1242                 return I40E_ERR_PARAM;
1243         }
1244
1245         for (i = 0; i < pba_size; i++) {
1246                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1247                 if (status != I40E_SUCCESS) {
1248                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1249                         return status;
1250                 }
1251
1252                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1253                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1254         }
1255         pba_num[(pba_size * 2)] = '\0';
1256
1257         return status;
1258 }
1259
1260 /**
1261  * i40e_get_media_type - Gets media type
1262  * @hw: pointer to the hardware structure
1263  **/
1264 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1265 {
1266         enum i40e_media_type media;
1267
1268         switch (hw->phy.link_info.phy_type) {
1269         case I40E_PHY_TYPE_10GBASE_SR:
1270         case I40E_PHY_TYPE_10GBASE_LR:
1271         case I40E_PHY_TYPE_1000BASE_SX:
1272         case I40E_PHY_TYPE_1000BASE_LX:
1273         case I40E_PHY_TYPE_40GBASE_SR4:
1274         case I40E_PHY_TYPE_40GBASE_LR4:
1275         case I40E_PHY_TYPE_25GBASE_LR:
1276         case I40E_PHY_TYPE_25GBASE_SR:
1277                 media = I40E_MEDIA_TYPE_FIBER;
1278                 break;
1279         case I40E_PHY_TYPE_100BASE_TX:
1280         case I40E_PHY_TYPE_1000BASE_T:
1281         case I40E_PHY_TYPE_2_5GBASE_T:
1282         case I40E_PHY_TYPE_5GBASE_T:
1283         case I40E_PHY_TYPE_10GBASE_T:
1284                 media = I40E_MEDIA_TYPE_BASET;
1285                 break;
1286         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1287         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1288         case I40E_PHY_TYPE_10GBASE_CR1:
1289         case I40E_PHY_TYPE_40GBASE_CR4:
1290         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1291         case I40E_PHY_TYPE_40GBASE_AOC:
1292         case I40E_PHY_TYPE_10GBASE_AOC:
1293         case I40E_PHY_TYPE_25GBASE_CR:
1294         case I40E_PHY_TYPE_25GBASE_AOC:
1295         case I40E_PHY_TYPE_25GBASE_ACC:
1296                 media = I40E_MEDIA_TYPE_DA;
1297                 break;
1298         case I40E_PHY_TYPE_1000BASE_KX:
1299         case I40E_PHY_TYPE_10GBASE_KX4:
1300         case I40E_PHY_TYPE_10GBASE_KR:
1301         case I40E_PHY_TYPE_40GBASE_KR4:
1302         case I40E_PHY_TYPE_20GBASE_KR2:
1303         case I40E_PHY_TYPE_25GBASE_KR:
1304                 media = I40E_MEDIA_TYPE_BACKPLANE;
1305                 break;
1306         case I40E_PHY_TYPE_SGMII:
1307         case I40E_PHY_TYPE_XAUI:
1308         case I40E_PHY_TYPE_XFI:
1309         case I40E_PHY_TYPE_XLAUI:
1310         case I40E_PHY_TYPE_XLPPI:
1311         default:
1312                 media = I40E_MEDIA_TYPE_UNKNOWN;
1313                 break;
1314         }
1315
1316         return media;
1317 }
1318
1319 /**
1320  * i40e_poll_globr - Poll for Global Reset completion
1321  * @hw: pointer to the hardware structure
1322  * @retry_limit: how many times to retry before failure
1323  **/
1324 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1325                                              u32 retry_limit)
1326 {
1327         u32 cnt, reg = 0;
1328
1329         for (cnt = 0; cnt < retry_limit; cnt++) {
1330                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1331                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1332                         return I40E_SUCCESS;
1333                 i40e_msec_delay(100);
1334         }
1335
1336         DEBUGOUT("Global reset failed.\n");
1337         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1338
1339         return I40E_ERR_RESET_FAILED;
1340 }
1341
1342 #define I40E_PF_RESET_WAIT_COUNT        200
1343 /**
1344  * i40e_pf_reset - Reset the PF
1345  * @hw: pointer to the hardware structure
1346  *
1347  * Assuming someone else has triggered a global reset,
1348  * assure the global reset is complete and then reset the PF
1349  **/
1350 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1351 {
1352         u32 cnt = 0;
1353         u32 cnt1 = 0;
1354         u32 reg = 0;
1355         u32 grst_del;
1356
1357         /* Poll for Global Reset steady state in case of recent GRST.
1358          * The grst delay value is in 100ms units, and we'll wait a
1359          * couple counts longer to be sure we don't just miss the end.
1360          */
1361         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1362                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1363                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1364
1365         grst_del = min(grst_del * 20, 160U);
1366
1367         for (cnt = 0; cnt < grst_del; cnt++) {
1368                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1369                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1370                         break;
1371                 i40e_msec_delay(100);
1372         }
1373         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1374                 DEBUGOUT("Global reset polling failed to complete.\n");
1375                 return I40E_ERR_RESET_FAILED;
1376         }
1377
1378         /* Now Wait for the FW to be ready */
1379         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1380                 reg = rd32(hw, I40E_GLNVM_ULD);
1381                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1383                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1384                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1385                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1386                         break;
1387                 }
1388                 i40e_msec_delay(10);
1389         }
1390         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1391                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1392                 DEBUGOUT("wait for FW Reset complete timedout\n");
1393                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1394                 return I40E_ERR_RESET_FAILED;
1395         }
1396
1397         /* If there was a Global Reset in progress when we got here,
1398          * we don't need to do the PF Reset
1399          */
1400         if (!cnt) {
1401                 u32 reg2 = 0;
1402
1403                 reg = rd32(hw, I40E_PFGEN_CTRL);
1404                 wr32(hw, I40E_PFGEN_CTRL,
1405                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1406                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1407                         reg = rd32(hw, I40E_PFGEN_CTRL);
1408                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1409                                 break;
1410                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1411                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1412                                 break;
1413                         i40e_msec_delay(1);
1414                 }
1415                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1416                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1417                                 return I40E_ERR_RESET_FAILED;
1418                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1419                         DEBUGOUT("PF reset polling failed to complete.\n");
1420                         return I40E_ERR_RESET_FAILED;
1421                 }
1422         }
1423
1424         i40e_clear_pxe_mode(hw);
1425
1426
1427         return I40E_SUCCESS;
1428 }
1429
1430 /**
1431  * i40e_clear_hw - clear out any left over hw state
1432  * @hw: pointer to the hw struct
1433  *
1434  * Clear queues and interrupts, typically called at init time,
1435  * but after the capabilities have been found so we know how many
1436  * queues and msix vectors have been allocated.
1437  **/
1438 void i40e_clear_hw(struct i40e_hw *hw)
1439 {
1440         u32 num_queues, base_queue;
1441         u32 num_pf_int;
1442         u32 num_vf_int;
1443         u32 num_vfs;
1444         u32 i, j;
1445         u32 val;
1446         u32 eol = 0x7ff;
1447
1448         /* get number of interrupts, queues, and vfs */
1449         val = rd32(hw, I40E_GLPCI_CNF2);
1450         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1451                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1452         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1453                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1454
1455         val = rd32(hw, I40E_PFLAN_QALLOC);
1456         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1457                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1458         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1459                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1460         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1461                 num_queues = (j - base_queue) + 1;
1462         else
1463                 num_queues = 0;
1464
1465         val = rd32(hw, I40E_PF_VT_PFALLOC);
1466         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1467                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1468         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1469                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1470         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1471                 num_vfs = (j - i) + 1;
1472         else
1473                 num_vfs = 0;
1474
1475         /* stop all the interrupts */
1476         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1477         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1478         for (i = 0; i < num_pf_int - 2; i++)
1479                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1480
1481         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1482         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1483         wr32(hw, I40E_PFINT_LNKLST0, val);
1484         for (i = 0; i < num_pf_int - 2; i++)
1485                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1486         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1487         for (i = 0; i < num_vfs; i++)
1488                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1489         for (i = 0; i < num_vf_int - 2; i++)
1490                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1491
1492         /* warn the HW of the coming Tx disables */
1493         for (i = 0; i < num_queues; i++) {
1494                 u32 abs_queue_idx = base_queue + i;
1495                 u32 reg_block = 0;
1496
1497                 if (abs_queue_idx >= 128) {
1498                         reg_block = abs_queue_idx / 128;
1499                         abs_queue_idx %= 128;
1500                 }
1501
1502                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1503                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1504                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1505                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1506
1507                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1508         }
1509         i40e_usec_delay(400);
1510
1511         /* stop all the queues */
1512         for (i = 0; i < num_queues; i++) {
1513                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1514                 wr32(hw, I40E_QTX_ENA(i), 0);
1515                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1516                 wr32(hw, I40E_QRX_ENA(i), 0);
1517         }
1518
1519         /* short wait for all queue disables to settle */
1520         i40e_usec_delay(50);
1521 }
1522
1523 /**
1524  * i40e_clear_pxe_mode - clear pxe operations mode
1525  * @hw: pointer to the hw struct
1526  *
1527  * Make sure all PXE mode settings are cleared, including things
1528  * like descriptor fetch/write-back mode.
1529  **/
1530 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1531 {
1532         if (i40e_check_asq_alive(hw))
1533                 i40e_aq_clear_pxe_mode(hw, NULL);
1534 }
1535
1536 /**
1537  * i40e_led_is_mine - helper to find matching led
1538  * @hw: pointer to the hw struct
1539  * @idx: index into GPIO registers
1540  *
1541  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1542  */
1543 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1544 {
1545         u32 gpio_val = 0;
1546         u32 port;
1547
1548         if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1549             !hw->func_caps.led[idx])
1550                 return 0;
1551         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1552         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1553                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1554
1555         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1556          * if it is not our port then ignore
1557          */
1558         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1559             (port != hw->port))
1560                 return 0;
1561
1562         return gpio_val;
1563 }
1564
1565 #define I40E_COMBINED_ACTIVITY 0xA
1566 #define I40E_FILTER_ACTIVITY 0xE
1567 #define I40E_LINK_ACTIVITY 0xC
1568 #define I40E_MAC_ACTIVITY 0xD
1569 #define I40E_FW_LED BIT(4)
1570 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1571                              I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1572
1573 #define I40E_LED0 22
1574
1575 #define I40E_PIN_FUNC_SDP 0x0
1576 #define I40E_PIN_FUNC_LED 0x1
1577
1578 /**
1579  * i40e_led_get - return current on/off mode
1580  * @hw: pointer to the hw struct
1581  *
1582  * The value returned is the 'mode' field as defined in the
1583  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1584  * values are variations of possible behaviors relating to
1585  * blink, link, and wire.
1586  **/
1587 u32 i40e_led_get(struct i40e_hw *hw)
1588 {
1589         u32 current_mode = 0;
1590         u32 mode = 0;
1591         int i;
1592
1593         /* as per the documentation GPIO 22-29 are the LED
1594          * GPIO pins named LED0..LED7
1595          */
1596         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1597                 u32 gpio_val = i40e_led_is_mine(hw, i);
1598
1599                 if (!gpio_val)
1600                         continue;
1601
1602                 /* ignore gpio LED src mode entries related to the activity
1603                  *  LEDs
1604                  */
1605                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1606                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1607                 switch (current_mode) {
1608                 case I40E_COMBINED_ACTIVITY:
1609                 case I40E_FILTER_ACTIVITY:
1610                 case I40E_MAC_ACTIVITY:
1611                 case I40E_LINK_ACTIVITY:
1612                         continue;
1613                 default:
1614                         break;
1615                 }
1616
1617                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1618                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1619                 break;
1620         }
1621
1622         return mode;
1623 }
1624
1625 /**
1626  * i40e_led_set - set new on/off mode
1627  * @hw: pointer to the hw struct
1628  * @mode: 0=off, 0xf=on (else see manual for mode details)
1629  * @blink: true if the LED should blink when on, false if steady
1630  *
1631  * if this function is used to turn on the blink it should
1632  * be used to disable the blink when restoring the original state.
1633  **/
1634 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1635 {
1636         u32 current_mode = 0;
1637         int i;
1638
1639         if (mode & ~I40E_LED_MODE_VALID) {
1640                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1641                 return;
1642         }
1643
1644         /* as per the documentation GPIO 22-29 are the LED
1645          * GPIO pins named LED0..LED7
1646          */
1647         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1648                 u32 gpio_val = i40e_led_is_mine(hw, i);
1649
1650                 if (!gpio_val)
1651                         continue;
1652
1653                 /* ignore gpio LED src mode entries related to the activity
1654                  * LEDs
1655                  */
1656                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1657                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1658                 switch (current_mode) {
1659                 case I40E_COMBINED_ACTIVITY:
1660                 case I40E_FILTER_ACTIVITY:
1661                 case I40E_MAC_ACTIVITY:
1662                 case I40E_LINK_ACTIVITY:
1663                         continue;
1664                 default:
1665                         break;
1666                 }
1667
1668                 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1669                         u32 pin_func = 0;
1670
1671                         if (mode & I40E_FW_LED)
1672                                 pin_func = I40E_PIN_FUNC_SDP;
1673                         else
1674                                 pin_func = I40E_PIN_FUNC_LED;
1675
1676                         gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1677                         gpio_val |= ((pin_func <<
1678                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1679                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1680                 }
1681                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1682                 /* this & is a bit of paranoia, but serves as a range check */
1683                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1684                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1685
1686                 if (blink)
1687                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1688                 else
1689                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1690
1691                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1692                 break;
1693         }
1694 }
1695
1696 /* Admin command wrappers */
1697
1698 /**
1699  * i40e_aq_get_phy_capabilities
1700  * @hw: pointer to the hw struct
1701  * @abilities: structure for PHY capabilities to be filled
1702  * @qualified_modules: report Qualified Modules
1703  * @report_init: report init capabilities (active are default)
1704  * @cmd_details: pointer to command details structure or NULL
1705  *
1706  * Returns the various PHY abilities supported on the Port.
1707  **/
1708 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1709                         bool qualified_modules, bool report_init,
1710                         struct i40e_aq_get_phy_abilities_resp *abilities,
1711                         struct i40e_asq_cmd_details *cmd_details)
1712 {
1713         struct i40e_aq_desc desc;
1714         enum i40e_status_code status;
1715         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1716         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1717
1718         if (!abilities)
1719                 return I40E_ERR_PARAM;
1720
1721         do {
1722                 i40e_fill_default_direct_cmd_desc(&desc,
1723                                                i40e_aqc_opc_get_phy_abilities);
1724
1725                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1726                 if (abilities_size > I40E_AQ_LARGE_BUF)
1727                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1728
1729                 if (qualified_modules)
1730                         desc.params.external.param0 |=
1731                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1732
1733                 if (report_init)
1734                         desc.params.external.param0 |=
1735                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1736
1737                 status = i40e_asq_send_command(hw, &desc, abilities,
1738                                                abilities_size, cmd_details);
1739
1740                 switch (hw->aq.asq_last_status) {
1741                 case I40E_AQ_RC_EIO:
1742                         status = I40E_ERR_UNKNOWN_PHY;
1743                         break;
1744                 case I40E_AQ_RC_EAGAIN:
1745                         i40e_msec_delay(1);
1746                         total_delay++;
1747                         status = I40E_ERR_TIMEOUT;
1748                         break;
1749                 /* also covers I40E_AQ_RC_OK */
1750                 default:
1751                         break;
1752                 }
1753
1754         } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1755                 (total_delay < max_delay));
1756
1757         if (status != I40E_SUCCESS)
1758                 return status;
1759
1760         if (report_init) {
1761                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1762                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1763                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1764                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1765                 } else {
1766                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1767                         hw->phy.phy_types |=
1768                                         ((u64)abilities->phy_type_ext << 32);
1769                 }
1770         }
1771
1772         return status;
1773 }
1774
1775 /**
1776  * i40e_aq_set_phy_config
1777  * @hw: pointer to the hw struct
1778  * @config: structure with PHY configuration to be set
1779  * @cmd_details: pointer to command details structure or NULL
1780  *
1781  * Set the various PHY configuration parameters
1782  * supported on the Port.One or more of the Set PHY config parameters may be
1783  * ignored in an MFP mode as the PF may not have the privilege to set some
1784  * of the PHY Config parameters. This status will be indicated by the
1785  * command response.
1786  **/
1787 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1788                                 struct i40e_aq_set_phy_config *config,
1789                                 struct i40e_asq_cmd_details *cmd_details)
1790 {
1791         struct i40e_aq_desc desc;
1792         struct i40e_aq_set_phy_config *cmd =
1793                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1794         enum i40e_status_code status;
1795
1796         if (!config)
1797                 return I40E_ERR_PARAM;
1798
1799         i40e_fill_default_direct_cmd_desc(&desc,
1800                                           i40e_aqc_opc_set_phy_config);
1801
1802         *cmd = *config;
1803
1804         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1805
1806         return status;
1807 }
1808
1809 /**
1810  * i40e_set_fc
1811  * @hw: pointer to the hw struct
1812  * @aq_failures: buffer to return AdminQ failure information
1813  * @atomic_restart: whether to enable atomic link restart
1814  *
1815  * Set the requested flow control mode using set_phy_config.
1816  **/
1817 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1818                                   bool atomic_restart)
1819 {
1820         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1821         struct i40e_aq_get_phy_abilities_resp abilities;
1822         struct i40e_aq_set_phy_config config;
1823         enum i40e_status_code status;
1824         u8 pause_mask = 0x0;
1825
1826         *aq_failures = 0x0;
1827
1828         switch (fc_mode) {
1829         case I40E_FC_FULL:
1830                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1831                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1832                 break;
1833         case I40E_FC_RX_PAUSE:
1834                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1835                 break;
1836         case I40E_FC_TX_PAUSE:
1837                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1838                 break;
1839         default:
1840                 break;
1841         }
1842
1843         /* Get the current phy config */
1844         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1845                                               NULL);
1846         if (status) {
1847                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1848                 return status;
1849         }
1850
1851         memset(&config, 0, sizeof(config));
1852         /* clear the old pause settings */
1853         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1854                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1855         /* set the new abilities */
1856         config.abilities |= pause_mask;
1857         /* If the abilities have changed, then set the new config */
1858         if (config.abilities != abilities.abilities) {
1859                 /* Auto restart link so settings take effect */
1860                 if (atomic_restart)
1861                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1862                 /* Copy over all the old settings */
1863                 config.phy_type = abilities.phy_type;
1864                 config.phy_type_ext = abilities.phy_type_ext;
1865                 config.link_speed = abilities.link_speed;
1866                 config.eee_capability = abilities.eee_capability;
1867                 config.eeer = abilities.eeer_val;
1868                 config.low_power_ctrl = abilities.d3_lpan;
1869                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1870                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1871                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1872
1873                 if (status)
1874                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1875         }
1876         /* Update the link info */
1877         status = i40e_update_link_info(hw);
1878         if (status) {
1879                 /* Wait a little bit (on 40G cards it sometimes takes a really
1880                  * long time for link to come back from the atomic reset)
1881                  * and try once more
1882                  */
1883                 i40e_msec_delay(1000);
1884                 status = i40e_update_link_info(hw);
1885         }
1886         if (status)
1887                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1888
1889         return status;
1890 }
1891
1892 /**
1893  * i40e_aq_set_mac_config
1894  * @hw: pointer to the hw struct
1895  * @max_frame_size: Maximum Frame Size to be supported by the port
1896  * @crc_en: Tell HW to append a CRC to outgoing frames
1897  * @pacing: Pacing configurations
1898  * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1899  * @cmd_details: pointer to command details structure or NULL
1900  *
1901  * Configure MAC settings for frame size, jumbo frame support and the
1902  * addition of a CRC by the hardware.
1903  **/
1904 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1905                                 u16 max_frame_size,
1906                                 bool crc_en, u16 pacing,
1907                                 bool auto_drop_blocking_packets,
1908                                 struct i40e_asq_cmd_details *cmd_details)
1909 {
1910         struct i40e_aq_desc desc;
1911         struct i40e_aq_set_mac_config *cmd =
1912                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1913         enum i40e_status_code status;
1914
1915         if (max_frame_size == 0)
1916                 return I40E_ERR_PARAM;
1917
1918         i40e_fill_default_direct_cmd_desc(&desc,
1919                                           i40e_aqc_opc_set_mac_config);
1920
1921         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1922         cmd->params = ((u8)pacing & 0x0F) << 3;
1923         if (crc_en)
1924                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1925
1926         if (auto_drop_blocking_packets) {
1927                 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1928                         cmd->params |=
1929                                 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1930                 else
1931                         i40e_debug(hw, I40E_DEBUG_ALL,
1932                                    "This FW api version does not support drop mode.\n");
1933         }
1934
1935 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1936         cmd->fc_refresh_threshold =
1937                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1938
1939         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1940
1941         return status;
1942 }
1943
1944 /**
1945  * i40e_aq_clear_pxe_mode
1946  * @hw: pointer to the hw struct
1947  * @cmd_details: pointer to command details structure or NULL
1948  *
1949  * Tell the firmware that the driver is taking over from PXE
1950  **/
1951 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1952                         struct i40e_asq_cmd_details *cmd_details)
1953 {
1954         enum i40e_status_code status;
1955         struct i40e_aq_desc desc;
1956         struct i40e_aqc_clear_pxe *cmd =
1957                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1958
1959         i40e_fill_default_direct_cmd_desc(&desc,
1960                                           i40e_aqc_opc_clear_pxe_mode);
1961
1962         cmd->rx_cnt = 0x2;
1963
1964         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1965
1966         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1967
1968         return status;
1969 }
1970
1971 /**
1972  * i40e_aq_set_link_restart_an
1973  * @hw: pointer to the hw struct
1974  * @enable_link: if true: enable link, if false: disable link
1975  * @cmd_details: pointer to command details structure or NULL
1976  *
1977  * Sets up the link and restarts the Auto-Negotiation over the link.
1978  **/
1979 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1980                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1981 {
1982         struct i40e_aq_desc desc;
1983         struct i40e_aqc_set_link_restart_an *cmd =
1984                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1985         enum i40e_status_code status;
1986
1987         i40e_fill_default_direct_cmd_desc(&desc,
1988                                           i40e_aqc_opc_set_link_restart_an);
1989
1990         cmd->command = I40E_AQ_PHY_RESTART_AN;
1991         if (enable_link)
1992                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1993         else
1994                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1995
1996         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1997
1998         return status;
1999 }
2000
2001 /**
2002  * i40e_aq_get_link_info
2003  * @hw: pointer to the hw struct
2004  * @enable_lse: enable/disable LinkStatusEvent reporting
2005  * @link: pointer to link status structure - optional
2006  * @cmd_details: pointer to command details structure or NULL
2007  *
2008  * Returns the link status of the adapter.
2009  **/
2010 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
2011                                 bool enable_lse, struct i40e_link_status *link,
2012                                 struct i40e_asq_cmd_details *cmd_details)
2013 {
2014         struct i40e_aq_desc desc;
2015         struct i40e_aqc_get_link_status *resp =
2016                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
2017         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
2018         enum i40e_status_code status;
2019         bool tx_pause, rx_pause;
2020         u16 command_flags;
2021
2022         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2023
2024         if (enable_lse)
2025                 command_flags = I40E_AQ_LSE_ENABLE;
2026         else
2027                 command_flags = I40E_AQ_LSE_DISABLE;
2028         resp->command_flags = CPU_TO_LE16(command_flags);
2029
2030         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2031
2032         if (status != I40E_SUCCESS)
2033                 goto aq_get_link_info_exit;
2034
2035         /* save off old link status information */
2036         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2037                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2038
2039         /* update link status */
2040         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2041         hw->phy.media_type = i40e_get_media_type(hw);
2042         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2043         hw_link_info->link_info = resp->link_info;
2044         hw_link_info->an_info = resp->an_info;
2045         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2046                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
2047         hw_link_info->ext_info = resp->ext_info;
2048         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2049         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2050         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2051
2052         /* update fc info */
2053         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2054         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2055         if (tx_pause & rx_pause)
2056                 hw->fc.current_mode = I40E_FC_FULL;
2057         else if (tx_pause)
2058                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2059         else if (rx_pause)
2060                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2061         else
2062                 hw->fc.current_mode = I40E_FC_NONE;
2063
2064         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2065                 hw_link_info->crc_enable = true;
2066         else
2067                 hw_link_info->crc_enable = false;
2068
2069         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2070                 hw_link_info->lse_enable = true;
2071         else
2072                 hw_link_info->lse_enable = false;
2073
2074         if ((hw->mac.type == I40E_MAC_XL710) &&
2075             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2076              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2077                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2078
2079         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2080             hw->mac.type != I40E_MAC_X722) {
2081                 __le32 tmp;
2082
2083                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2084                             I40E_NONDMA_TO_NONDMA);
2085                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2086                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2087         }
2088
2089         /* save link status information */
2090         if (link)
2091                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2092                             I40E_NONDMA_TO_NONDMA);
2093
2094         /* flag cleared so helper functions don't call AQ again */
2095         hw->phy.get_link_info = false;
2096
2097 aq_get_link_info_exit:
2098         return status;
2099 }
2100
2101 /**
2102  * i40e_aq_set_phy_int_mask
2103  * @hw: pointer to the hw struct
2104  * @mask: interrupt mask to be set
2105  * @cmd_details: pointer to command details structure or NULL
2106  *
2107  * Set link interrupt mask.
2108  **/
2109 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2110                                 u16 mask,
2111                                 struct i40e_asq_cmd_details *cmd_details)
2112 {
2113         struct i40e_aq_desc desc;
2114         struct i40e_aqc_set_phy_int_mask *cmd =
2115                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2116         enum i40e_status_code status;
2117
2118         i40e_fill_default_direct_cmd_desc(&desc,
2119                                           i40e_aqc_opc_set_phy_int_mask);
2120
2121         cmd->event_mask = CPU_TO_LE16(mask);
2122
2123         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2124
2125         return status;
2126 }
2127
2128 /**
2129  * i40e_aq_get_local_advt_reg
2130  * @hw: pointer to the hw struct
2131  * @advt_reg: local AN advertisement register value
2132  * @cmd_details: pointer to command details structure or NULL
2133  *
2134  * Get the Local AN advertisement register value.
2135  **/
2136 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2137                                 u64 *advt_reg,
2138                                 struct i40e_asq_cmd_details *cmd_details)
2139 {
2140         struct i40e_aq_desc desc;
2141         struct i40e_aqc_an_advt_reg *resp =
2142                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2143         enum i40e_status_code status;
2144
2145         i40e_fill_default_direct_cmd_desc(&desc,
2146                                           i40e_aqc_opc_get_local_advt_reg);
2147
2148         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2149
2150         if (status != I40E_SUCCESS)
2151                 goto aq_get_local_advt_reg_exit;
2152
2153         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2154         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2155
2156 aq_get_local_advt_reg_exit:
2157         return status;
2158 }
2159
2160 /**
2161  * i40e_aq_set_local_advt_reg
2162  * @hw: pointer to the hw struct
2163  * @advt_reg: local AN advertisement register value
2164  * @cmd_details: pointer to command details structure or NULL
2165  *
2166  * Get the Local AN advertisement register value.
2167  **/
2168 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2169                                 u64 advt_reg,
2170                                 struct i40e_asq_cmd_details *cmd_details)
2171 {
2172         struct i40e_aq_desc desc;
2173         struct i40e_aqc_an_advt_reg *cmd =
2174                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2175         enum i40e_status_code status;
2176
2177         i40e_fill_default_direct_cmd_desc(&desc,
2178                                           i40e_aqc_opc_get_local_advt_reg);
2179
2180         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2181         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2182
2183         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2184
2185         return status;
2186 }
2187
2188 /**
2189  * i40e_aq_get_partner_advt
2190  * @hw: pointer to the hw struct
2191  * @advt_reg: AN partner advertisement register value
2192  * @cmd_details: pointer to command details structure or NULL
2193  *
2194  * Get the link partner AN advertisement register value.
2195  **/
2196 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2197                                 u64 *advt_reg,
2198                                 struct i40e_asq_cmd_details *cmd_details)
2199 {
2200         struct i40e_aq_desc desc;
2201         struct i40e_aqc_an_advt_reg *resp =
2202                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2203         enum i40e_status_code status;
2204
2205         i40e_fill_default_direct_cmd_desc(&desc,
2206                                           i40e_aqc_opc_get_partner_advt);
2207
2208         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2209
2210         if (status != I40E_SUCCESS)
2211                 goto aq_get_partner_advt_exit;
2212
2213         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2214         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2215
2216 aq_get_partner_advt_exit:
2217         return status;
2218 }
2219
2220 /**
2221  * i40e_aq_set_lb_modes
2222  * @hw: pointer to the hw struct
2223  * @lb_modes: loopback mode to be set
2224  * @cmd_details: pointer to command details structure or NULL
2225  *
2226  * Sets loopback modes.
2227  **/
2228 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2229                                 u16 lb_modes,
2230                                 struct i40e_asq_cmd_details *cmd_details)
2231 {
2232         struct i40e_aq_desc desc;
2233         struct i40e_aqc_set_lb_mode *cmd =
2234                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2235         enum i40e_status_code status;
2236
2237         i40e_fill_default_direct_cmd_desc(&desc,
2238                                           i40e_aqc_opc_set_lb_modes);
2239
2240         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2241
2242         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2243
2244         return status;
2245 }
2246
2247 /**
2248  * i40e_aq_set_phy_debug
2249  * @hw: pointer to the hw struct
2250  * @cmd_flags: debug command flags
2251  * @cmd_details: pointer to command details structure or NULL
2252  *
2253  * Reset the external PHY.
2254  **/
2255 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2256                                 struct i40e_asq_cmd_details *cmd_details)
2257 {
2258         struct i40e_aq_desc desc;
2259         struct i40e_aqc_set_phy_debug *cmd =
2260                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2261         enum i40e_status_code status;
2262
2263         i40e_fill_default_direct_cmd_desc(&desc,
2264                                           i40e_aqc_opc_set_phy_debug);
2265
2266         cmd->command_flags = cmd_flags;
2267
2268         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2269
2270         return status;
2271 }
2272
2273 /**
2274  * i40e_aq_add_vsi
2275  * @hw: pointer to the hw struct
2276  * @vsi_ctx: pointer to a vsi context struct
2277  * @cmd_details: pointer to command details structure or NULL
2278  *
2279  * Add a VSI context to the hardware.
2280 **/
2281 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2282                                 struct i40e_vsi_context *vsi_ctx,
2283                                 struct i40e_asq_cmd_details *cmd_details)
2284 {
2285         struct i40e_aq_desc desc;
2286         struct i40e_aqc_add_get_update_vsi *cmd =
2287                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2288         struct i40e_aqc_add_get_update_vsi_completion *resp =
2289                 (struct i40e_aqc_add_get_update_vsi_completion *)
2290                 &desc.params.raw;
2291         enum i40e_status_code status;
2292
2293         i40e_fill_default_direct_cmd_desc(&desc,
2294                                           i40e_aqc_opc_add_vsi);
2295
2296         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2297         cmd->connection_type = vsi_ctx->connection_type;
2298         cmd->vf_id = vsi_ctx->vf_num;
2299         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2300
2301         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2302
2303         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2304                                     sizeof(vsi_ctx->info), cmd_details);
2305
2306         if (status != I40E_SUCCESS)
2307                 goto aq_add_vsi_exit;
2308
2309         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2310         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2311         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2312         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2313
2314 aq_add_vsi_exit:
2315         return status;
2316 }
2317
2318 /**
2319  * i40e_aq_set_default_vsi
2320  * @hw: pointer to the hw struct
2321  * @seid: vsi number
2322  * @cmd_details: pointer to command details structure or NULL
2323  **/
2324 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2325                                 u16 seid,
2326                                 struct i40e_asq_cmd_details *cmd_details)
2327 {
2328         struct i40e_aq_desc desc;
2329         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2330                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2331                 &desc.params.raw;
2332         enum i40e_status_code status;
2333
2334         i40e_fill_default_direct_cmd_desc(&desc,
2335                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2336
2337         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2338         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2339         cmd->seid = CPU_TO_LE16(seid);
2340
2341         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2342
2343         return status;
2344 }
2345
2346 /**
2347  * i40e_aq_clear_default_vsi
2348  * @hw: pointer to the hw struct
2349  * @seid: vsi number
2350  * @cmd_details: pointer to command details structure or NULL
2351  **/
2352 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2353                                 u16 seid,
2354                                 struct i40e_asq_cmd_details *cmd_details)
2355 {
2356         struct i40e_aq_desc desc;
2357         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2358                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2359                 &desc.params.raw;
2360         enum i40e_status_code status;
2361
2362         i40e_fill_default_direct_cmd_desc(&desc,
2363                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2364
2365         cmd->promiscuous_flags = CPU_TO_LE16(0);
2366         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2367         cmd->seid = CPU_TO_LE16(seid);
2368
2369         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2370
2371         return status;
2372 }
2373
2374 /**
2375  * i40e_aq_set_vsi_unicast_promiscuous
2376  * @hw: pointer to the hw struct
2377  * @seid: vsi number
2378  * @set: set unicast promiscuous enable/disable
2379  * @cmd_details: pointer to command details structure or NULL
2380  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2381  **/
2382 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2383                                 u16 seid, bool set,
2384                                 struct i40e_asq_cmd_details *cmd_details,
2385                                 bool rx_only_promisc)
2386 {
2387         struct i40e_aq_desc desc;
2388         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2389                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2390         enum i40e_status_code status;
2391         u16 flags = 0;
2392
2393         i40e_fill_default_direct_cmd_desc(&desc,
2394                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2395
2396         if (set) {
2397                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2398                 if (rx_only_promisc &&
2399                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2400                      (hw->aq.api_maj_ver > 1)))
2401                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2402         }
2403
2404         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2405
2406         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2407         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2408              (hw->aq.api_maj_ver > 1))
2409                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2410
2411         cmd->seid = CPU_TO_LE16(seid);
2412         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2413
2414         return status;
2415 }
2416
2417 /**
2418  * i40e_aq_set_vsi_multicast_promiscuous
2419  * @hw: pointer to the hw struct
2420  * @seid: vsi number
2421  * @set: set multicast promiscuous enable/disable
2422  * @cmd_details: pointer to command details structure or NULL
2423  **/
2424 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2425                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2426 {
2427         struct i40e_aq_desc desc;
2428         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2429                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2430         enum i40e_status_code status;
2431         u16 flags = 0;
2432
2433         i40e_fill_default_direct_cmd_desc(&desc,
2434                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2435
2436         if (set)
2437                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2438
2439         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2440
2441         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2442
2443         cmd->seid = CPU_TO_LE16(seid);
2444         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2445
2446         return status;
2447 }
2448
2449 /**
2450 * i40e_aq_set_vsi_full_promiscuous
2451 * @hw: pointer to the hw struct
2452 * @seid: VSI number
2453 * @set: set promiscuous enable/disable
2454 * @cmd_details: pointer to command details structure or NULL
2455 **/
2456 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2457                                 u16 seid, bool set,
2458                                 struct i40e_asq_cmd_details *cmd_details)
2459 {
2460         struct i40e_aq_desc desc;
2461         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2462                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2463         enum i40e_status_code status;
2464         u16 flags = 0;
2465
2466         i40e_fill_default_direct_cmd_desc(&desc,
2467                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2468
2469         if (set)
2470                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2471                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2472                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2473
2474         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2475
2476         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2477                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2478                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2479
2480         cmd->seid = CPU_TO_LE16(seid);
2481         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2482
2483         return status;
2484 }
2485
2486 /**
2487  * i40e_aq_set_vsi_mc_promisc_on_vlan
2488  * @hw: pointer to the hw struct
2489  * @seid: vsi number
2490  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2491  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2492  * @cmd_details: pointer to command details structure or NULL
2493  **/
2494 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2495                                 u16 seid, bool enable, u16 vid,
2496                                 struct i40e_asq_cmd_details *cmd_details)
2497 {
2498         struct i40e_aq_desc desc;
2499         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2500                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2501         enum i40e_status_code status;
2502         u16 flags = 0;
2503
2504         i40e_fill_default_direct_cmd_desc(&desc,
2505                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2506
2507         if (enable)
2508                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2509
2510         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2511         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2512         cmd->seid = CPU_TO_LE16(seid);
2513         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2514
2515         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2516
2517         return status;
2518 }
2519
2520 /**
2521  * i40e_aq_set_vsi_uc_promisc_on_vlan
2522  * @hw: pointer to the hw struct
2523  * @seid: vsi number
2524  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2525  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2526  * @cmd_details: pointer to command details structure or NULL
2527  **/
2528 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2529                                 u16 seid, bool enable, u16 vid,
2530                                 struct i40e_asq_cmd_details *cmd_details)
2531 {
2532         struct i40e_aq_desc desc;
2533         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2534                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2535         enum i40e_status_code status;
2536         u16 flags = 0;
2537
2538         i40e_fill_default_direct_cmd_desc(&desc,
2539                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2540
2541         if (enable)
2542                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2543
2544         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2545         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2546         cmd->seid = CPU_TO_LE16(seid);
2547         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2548
2549         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2550
2551         return status;
2552 }
2553
2554 /**
2555  * i40e_aq_set_vsi_bc_promisc_on_vlan
2556  * @hw: pointer to the hw struct
2557  * @seid: vsi number
2558  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2559  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2560  * @cmd_details: pointer to command details structure or NULL
2561  **/
2562 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2563                                 u16 seid, bool enable, u16 vid,
2564                                 struct i40e_asq_cmd_details *cmd_details)
2565 {
2566         struct i40e_aq_desc desc;
2567         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2568                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2569         enum i40e_status_code status;
2570         u16 flags = 0;
2571
2572         i40e_fill_default_direct_cmd_desc(&desc,
2573                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2574
2575         if (enable)
2576                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2577
2578         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2579         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2580         cmd->seid = CPU_TO_LE16(seid);
2581         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2582
2583         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2584
2585         return status;
2586 }
2587
2588 /**
2589  * i40e_aq_set_vsi_broadcast
2590  * @hw: pointer to the hw struct
2591  * @seid: vsi number
2592  * @set_filter: true to set filter, false to clear filter
2593  * @cmd_details: pointer to command details structure or NULL
2594  *
2595  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2596  **/
2597 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2598                                 u16 seid, bool set_filter,
2599                                 struct i40e_asq_cmd_details *cmd_details)
2600 {
2601         struct i40e_aq_desc desc;
2602         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2603                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2604         enum i40e_status_code status;
2605
2606         i40e_fill_default_direct_cmd_desc(&desc,
2607                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2608
2609         if (set_filter)
2610                 cmd->promiscuous_flags
2611                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2612         else
2613                 cmd->promiscuous_flags
2614                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2615
2616         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2617         cmd->seid = CPU_TO_LE16(seid);
2618         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2619
2620         return status;
2621 }
2622
2623 /**
2624  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2625  * @hw: pointer to the hw struct
2626  * @seid: vsi number
2627  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2628  * @cmd_details: pointer to command details structure or NULL
2629  **/
2630 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2631                                 u16 seid, bool enable,
2632                                 struct i40e_asq_cmd_details *cmd_details)
2633 {
2634         struct i40e_aq_desc desc;
2635         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2636                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2637         enum i40e_status_code status;
2638         u16 flags = 0;
2639
2640         i40e_fill_default_direct_cmd_desc(&desc,
2641                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2642         if (enable)
2643                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2644
2645         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2646         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2647         cmd->seid = CPU_TO_LE16(seid);
2648
2649         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2650
2651         return status;
2652 }
2653
2654 /**
2655  * i40e_get_vsi_params - get VSI configuration info
2656  * @hw: pointer to the hw struct
2657  * @vsi_ctx: pointer to a vsi context struct
2658  * @cmd_details: pointer to command details structure or NULL
2659  **/
2660 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2661                                 struct i40e_vsi_context *vsi_ctx,
2662                                 struct i40e_asq_cmd_details *cmd_details)
2663 {
2664         struct i40e_aq_desc desc;
2665         struct i40e_aqc_add_get_update_vsi *cmd =
2666                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2667         struct i40e_aqc_add_get_update_vsi_completion *resp =
2668                 (struct i40e_aqc_add_get_update_vsi_completion *)
2669                 &desc.params.raw;
2670         enum i40e_status_code status;
2671
2672         UNREFERENCED_1PARAMETER(cmd_details);
2673         i40e_fill_default_direct_cmd_desc(&desc,
2674                                           i40e_aqc_opc_get_vsi_parameters);
2675
2676         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2677
2678         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2679
2680         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2681                                     sizeof(vsi_ctx->info), NULL);
2682
2683         if (status != I40E_SUCCESS)
2684                 goto aq_get_vsi_params_exit;
2685
2686         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2687         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2688         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2689         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2690
2691 aq_get_vsi_params_exit:
2692         return status;
2693 }
2694
2695 /**
2696  * i40e_aq_update_vsi_params
2697  * @hw: pointer to the hw struct
2698  * @vsi_ctx: pointer to a vsi context struct
2699  * @cmd_details: pointer to command details structure or NULL
2700  *
2701  * Update a VSI context.
2702  **/
2703 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2704                                 struct i40e_vsi_context *vsi_ctx,
2705                                 struct i40e_asq_cmd_details *cmd_details)
2706 {
2707         struct i40e_aq_desc desc;
2708         struct i40e_aqc_add_get_update_vsi *cmd =
2709                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2710         struct i40e_aqc_add_get_update_vsi_completion *resp =
2711                 (struct i40e_aqc_add_get_update_vsi_completion *)
2712                 &desc.params.raw;
2713         enum i40e_status_code status;
2714
2715         i40e_fill_default_direct_cmd_desc(&desc,
2716                                           i40e_aqc_opc_update_vsi_parameters);
2717         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2718
2719         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2720
2721         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2722                                     sizeof(vsi_ctx->info), cmd_details);
2723
2724         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2725         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2726
2727         return status;
2728 }
2729
2730 /**
2731  * i40e_aq_get_switch_config
2732  * @hw: pointer to the hardware structure
2733  * @buf: pointer to the result buffer
2734  * @buf_size: length of input buffer
2735  * @start_seid: seid to start for the report, 0 == beginning
2736  * @cmd_details: pointer to command details structure or NULL
2737  *
2738  * Fill the buf with switch configuration returned from AdminQ command
2739  **/
2740 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2741                                 struct i40e_aqc_get_switch_config_resp *buf,
2742                                 u16 buf_size, u16 *start_seid,
2743                                 struct i40e_asq_cmd_details *cmd_details)
2744 {
2745         struct i40e_aq_desc desc;
2746         struct i40e_aqc_switch_seid *scfg =
2747                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2748         enum i40e_status_code status;
2749
2750         i40e_fill_default_direct_cmd_desc(&desc,
2751                                           i40e_aqc_opc_get_switch_config);
2752         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2753         if (buf_size > I40E_AQ_LARGE_BUF)
2754                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2755         scfg->seid = CPU_TO_LE16(*start_seid);
2756
2757         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2758         *start_seid = LE16_TO_CPU(scfg->seid);
2759
2760         return status;
2761 }
2762
2763 /**
2764  * i40e_aq_set_switch_config
2765  * @hw: pointer to the hardware structure
2766  * @flags: bit flag values to set
2767  * @mode: cloud filter mode
2768  * @valid_flags: which bit flags to set
2769  * @cmd_details: pointer to command details structure or NULL
2770  *
2771  * Set switch configuration bits
2772  **/
2773 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2774                                 u16 flags, u16 valid_flags, u8 mode,
2775                                 struct i40e_asq_cmd_details *cmd_details)
2776 {
2777         struct i40e_aq_desc desc;
2778         struct i40e_aqc_set_switch_config *scfg =
2779                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2780         enum i40e_status_code status;
2781
2782         i40e_fill_default_direct_cmd_desc(&desc,
2783                                           i40e_aqc_opc_set_switch_config);
2784         scfg->flags = CPU_TO_LE16(flags);
2785         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2786         scfg->mode = mode;
2787         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2788                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2789                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2790                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2791         }
2792         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2793
2794         return status;
2795 }
2796
2797 /**
2798  * i40e_aq_get_firmware_version
2799  * @hw: pointer to the hw struct
2800  * @fw_major_version: firmware major version
2801  * @fw_minor_version: firmware minor version
2802  * @fw_build: firmware build number
2803  * @api_major_version: major queue version
2804  * @api_minor_version: minor queue version
2805  * @cmd_details: pointer to command details structure or NULL
2806  *
2807  * Get the firmware version from the admin queue commands
2808  **/
2809 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2810                                 u16 *fw_major_version, u16 *fw_minor_version,
2811                                 u32 *fw_build,
2812                                 u16 *api_major_version, u16 *api_minor_version,
2813                                 struct i40e_asq_cmd_details *cmd_details)
2814 {
2815         struct i40e_aq_desc desc;
2816         struct i40e_aqc_get_version *resp =
2817                 (struct i40e_aqc_get_version *)&desc.params.raw;
2818         enum i40e_status_code status;
2819
2820         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2821
2822         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2823
2824         if (status == I40E_SUCCESS) {
2825                 if (fw_major_version != NULL)
2826                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2827                 if (fw_minor_version != NULL)
2828                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2829                 if (fw_build != NULL)
2830                         *fw_build = LE32_TO_CPU(resp->fw_build);
2831                 if (api_major_version != NULL)
2832                         *api_major_version = LE16_TO_CPU(resp->api_major);
2833                 if (api_minor_version != NULL)
2834                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2835
2836                 /* A workaround to fix the API version in SW */
2837                 if (api_major_version && api_minor_version &&
2838                     fw_major_version && fw_minor_version &&
2839                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2840                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2841                      (*fw_major_version > 4)))
2842                         *api_minor_version = 2;
2843         }
2844
2845         return status;
2846 }
2847
2848 /**
2849  * i40e_aq_send_driver_version
2850  * @hw: pointer to the hw struct
2851  * @dv: driver's major, minor version
2852  * @cmd_details: pointer to command details structure or NULL
2853  *
2854  * Send the driver version to the firmware
2855  **/
2856 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2857                                 struct i40e_driver_version *dv,
2858                                 struct i40e_asq_cmd_details *cmd_details)
2859 {
2860         struct i40e_aq_desc desc;
2861         struct i40e_aqc_driver_version *cmd =
2862                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2863         enum i40e_status_code status;
2864         u16 len;
2865
2866         if (dv == NULL)
2867                 return I40E_ERR_PARAM;
2868
2869         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2870
2871         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2872         cmd->driver_major_ver = dv->major_version;
2873         cmd->driver_minor_ver = dv->minor_version;
2874         cmd->driver_build_ver = dv->build_version;
2875         cmd->driver_subbuild_ver = dv->subbuild_version;
2876
2877         len = 0;
2878         while (len < sizeof(dv->driver_string) &&
2879                (dv->driver_string[len] < 0x80) &&
2880                dv->driver_string[len])
2881                 len++;
2882         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2883                                        len, cmd_details);
2884
2885         return status;
2886 }
2887
2888 /**
2889  * i40e_get_link_status - get status of the HW network link
2890  * @hw: pointer to the hw struct
2891  * @link_up: pointer to bool (true/false = linkup/linkdown)
2892  *
2893  * Variable link_up true if link is up, false if link is down.
2894  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2895  *
2896  * Side effect: LinkStatusEvent reporting becomes enabled
2897  **/
2898 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2899 {
2900         enum i40e_status_code status = I40E_SUCCESS;
2901
2902         if (hw->phy.get_link_info) {
2903                 status = i40e_update_link_info(hw);
2904
2905                 if (status != I40E_SUCCESS)
2906                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2907                                    status);
2908         }
2909
2910         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2911
2912         return status;
2913 }
2914
2915 /**
2916  * i40e_updatelink_status - update status of the HW network link
2917  * @hw: pointer to the hw struct
2918  **/
2919 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2920 {
2921         struct i40e_aq_get_phy_abilities_resp abilities;
2922         enum i40e_status_code status = I40E_SUCCESS;
2923
2924         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2925         if (status)
2926                 return status;
2927
2928         /* extra checking needed to ensure link info to user is timely */
2929         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2930             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2931              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2932                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2933                                                       &abilities, NULL);
2934                 if (status)
2935                         return status;
2936
2937                 if (abilities.fec_cfg_curr_mod_ext_info &
2938                     I40E_AQ_ENABLE_FEC_AUTO)
2939                         hw->phy.link_info.req_fec_info =
2940                                 (I40E_AQ_REQUEST_FEC_KR |
2941                                  I40E_AQ_REQUEST_FEC_RS);
2942                 else
2943                         hw->phy.link_info.req_fec_info =
2944                                 abilities.fec_cfg_curr_mod_ext_info &
2945                                 (I40E_AQ_REQUEST_FEC_KR |
2946                                  I40E_AQ_REQUEST_FEC_RS);
2947
2948                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2949                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2950         }
2951         return status;
2952 }
2953
2954
2955 /**
2956  * i40e_get_link_speed
2957  * @hw: pointer to the hw struct
2958  *
2959  * Returns the link speed of the adapter.
2960  **/
2961 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2962 {
2963         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2964         enum i40e_status_code status = I40E_SUCCESS;
2965
2966         if (hw->phy.get_link_info) {
2967                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2968
2969                 if (status != I40E_SUCCESS)
2970                         goto i40e_link_speed_exit;
2971         }
2972
2973         speed = hw->phy.link_info.link_speed;
2974
2975 i40e_link_speed_exit:
2976         return speed;
2977 }
2978
2979 /**
2980  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2981  * @hw: pointer to the hw struct
2982  * @uplink_seid: the MAC or other gizmo SEID
2983  * @downlink_seid: the VSI SEID
2984  * @enabled_tc: bitmap of TCs to be enabled
2985  * @default_port: true for default port VSI, false for control port
2986  * @veb_seid: pointer to where to put the resulting VEB SEID
2987  * @enable_stats: true to turn on VEB stats
2988  * @cmd_details: pointer to command details structure or NULL
2989  *
2990  * This asks the FW to add a VEB between the uplink and downlink
2991  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2992  **/
2993 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2994                                 u16 downlink_seid, u8 enabled_tc,
2995                                 bool default_port, u16 *veb_seid,
2996                                 bool enable_stats,
2997                                 struct i40e_asq_cmd_details *cmd_details)
2998 {
2999         struct i40e_aq_desc desc;
3000         struct i40e_aqc_add_veb *cmd =
3001                 (struct i40e_aqc_add_veb *)&desc.params.raw;
3002         struct i40e_aqc_add_veb_completion *resp =
3003                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
3004         enum i40e_status_code status;
3005         u16 veb_flags = 0;
3006
3007         /* SEIDs need to either both be set or both be 0 for floating VEB */
3008         if (!!uplink_seid != !!downlink_seid)
3009                 return I40E_ERR_PARAM;
3010
3011         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
3012
3013         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
3014         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
3015         cmd->enable_tcs = enabled_tc;
3016         if (!uplink_seid)
3017                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
3018         if (default_port)
3019                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
3020         else
3021                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
3022
3023         /* reverse logic here: set the bitflag to disable the stats */
3024         if (!enable_stats)
3025                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
3026
3027         cmd->veb_flags = CPU_TO_LE16(veb_flags);
3028
3029         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3030
3031         if (!status && veb_seid)
3032                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
3033
3034         return status;
3035 }
3036
3037 /**
3038  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
3039  * @hw: pointer to the hw struct
3040  * @veb_seid: the SEID of the VEB to query
3041  * @switch_id: the uplink switch id
3042  * @floating: set to true if the VEB is floating
3043  * @statistic_index: index of the stats counter block for this VEB
3044  * @vebs_used: number of VEB's used by function
3045  * @vebs_free: total VEB's not reserved by any function
3046  * @cmd_details: pointer to command details structure or NULL
3047  *
3048  * This retrieves the parameters for a particular VEB, specified by
3049  * uplink_seid, and returns them to the caller.
3050  **/
3051 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3052                                 u16 veb_seid, u16 *switch_id,
3053                                 bool *floating, u16 *statistic_index,
3054                                 u16 *vebs_used, u16 *vebs_free,
3055                                 struct i40e_asq_cmd_details *cmd_details)
3056 {
3057         struct i40e_aq_desc desc;
3058         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3059                 (struct i40e_aqc_get_veb_parameters_completion *)
3060                 &desc.params.raw;
3061         enum i40e_status_code status;
3062
3063         if (veb_seid == 0)
3064                 return I40E_ERR_PARAM;
3065
3066         i40e_fill_default_direct_cmd_desc(&desc,
3067                                           i40e_aqc_opc_get_veb_parameters);
3068         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3069
3070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3071         if (status)
3072                 goto get_veb_exit;
3073
3074         if (switch_id)
3075                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3076         if (statistic_index)
3077                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3078         if (vebs_used)
3079                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3080         if (vebs_free)
3081                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3082         if (floating) {
3083                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3084
3085                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3086                         *floating = true;
3087                 else
3088                         *floating = false;
3089         }
3090
3091 get_veb_exit:
3092         return status;
3093 }
3094
3095 /**
3096  * i40e_aq_add_macvlan
3097  * @hw: pointer to the hw struct
3098  * @seid: VSI for the mac address
3099  * @mv_list: list of macvlans to be added
3100  * @count: length of the list
3101  * @cmd_details: pointer to command details structure or NULL
3102  *
3103  * Add MAC/VLAN addresses to the HW filtering
3104  **/
3105 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3106                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3107                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3108 {
3109         struct i40e_aq_desc desc;
3110         struct i40e_aqc_macvlan *cmd =
3111                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3112         enum i40e_status_code status;
3113         u16 buf_size;
3114         int i;
3115
3116         if (count == 0 || !mv_list || !hw)
3117                 return I40E_ERR_PARAM;
3118
3119         buf_size = count * sizeof(*mv_list);
3120
3121         /* prep the rest of the request */
3122         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3123         cmd->num_addresses = CPU_TO_LE16(count);
3124         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3125         cmd->seid[1] = 0;
3126         cmd->seid[2] = 0;
3127
3128         for (i = 0; i < count; i++)
3129                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3130                         mv_list[i].flags |=
3131                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3132
3133         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3134         if (buf_size > I40E_AQ_LARGE_BUF)
3135                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3136
3137         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3138                                        cmd_details);
3139
3140         return status;
3141 }
3142
3143 /**
3144  * i40e_aq_remove_macvlan
3145  * @hw: pointer to the hw struct
3146  * @seid: VSI for the mac address
3147  * @mv_list: list of macvlans to be removed
3148  * @count: length of the list
3149  * @cmd_details: pointer to command details structure or NULL
3150  *
3151  * Remove MAC/VLAN addresses from the HW filtering
3152  **/
3153 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3154                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3155                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3156 {
3157         struct i40e_aq_desc desc;
3158         struct i40e_aqc_macvlan *cmd =
3159                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3160         enum i40e_status_code status;
3161         u16 buf_size;
3162
3163         if (count == 0 || !mv_list || !hw)
3164                 return I40E_ERR_PARAM;
3165
3166         buf_size = count * sizeof(*mv_list);
3167
3168         /* prep the rest of the request */
3169         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3170         cmd->num_addresses = CPU_TO_LE16(count);
3171         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3172         cmd->seid[1] = 0;
3173         cmd->seid[2] = 0;
3174
3175         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3176         if (buf_size > I40E_AQ_LARGE_BUF)
3177                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3178
3179         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3180                                        cmd_details);
3181
3182         return status;
3183 }
3184
3185 /**
3186  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3187  * @hw: pointer to the hw struct
3188  * @opcode: AQ opcode for add or delete mirror rule
3189  * @sw_seid: Switch SEID (to which rule refers)
3190  * @rule_type: Rule Type (ingress/egress/VLAN)
3191  * @id: Destination VSI SEID or Rule ID
3192  * @count: length of the list
3193  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3194  * @cmd_details: pointer to command details structure or NULL
3195  * @rule_id: Rule ID returned from FW
3196  * @rules_used: Number of rules used in internal switch
3197  * @rules_free: Number of rules free in internal switch
3198  *
3199  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3200  * VEBs/VEPA elements only
3201  **/
3202 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3203                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3204                         u16 count, __le16 *mr_list,
3205                         struct i40e_asq_cmd_details *cmd_details,
3206                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3207 {
3208         struct i40e_aq_desc desc;
3209         struct i40e_aqc_add_delete_mirror_rule *cmd =
3210                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3211         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3212         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3213         enum i40e_status_code status;
3214         u16 buf_size;
3215
3216         buf_size = count * sizeof(*mr_list);
3217
3218         /* prep the rest of the request */
3219         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3220         cmd->seid = CPU_TO_LE16(sw_seid);
3221         cmd->rule_type = CPU_TO_LE16(rule_type &
3222                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3223         cmd->num_entries = CPU_TO_LE16(count);
3224         /* Dest VSI for add, rule_id for delete */
3225         cmd->destination = CPU_TO_LE16(id);
3226         if (mr_list) {
3227                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3228                                                 I40E_AQ_FLAG_RD));
3229                 if (buf_size > I40E_AQ_LARGE_BUF)
3230                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3231         }
3232
3233         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3234                                        cmd_details);
3235         if (status == I40E_SUCCESS ||
3236             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3237                 if (rule_id)
3238                         *rule_id = LE16_TO_CPU(resp->rule_id);
3239                 if (rules_used)
3240                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3241                 if (rules_free)
3242                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3243         }
3244         return status;
3245 }
3246
3247 /**
3248  * i40e_aq_add_mirrorrule - add a mirror rule
3249  * @hw: pointer to the hw struct
3250  * @sw_seid: Switch SEID (to which rule refers)
3251  * @rule_type: Rule Type (ingress/egress/VLAN)
3252  * @dest_vsi: SEID of VSI to which packets will be mirrored
3253  * @count: length of the list
3254  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3255  * @cmd_details: pointer to command details structure or NULL
3256  * @rule_id: Rule ID returned from FW
3257  * @rules_used: Number of rules used in internal switch
3258  * @rules_free: Number of rules free in internal switch
3259  *
3260  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3261  **/
3262 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3263                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3264                         struct i40e_asq_cmd_details *cmd_details,
3265                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3266 {
3267         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3268             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3269                 if (count == 0 || !mr_list)
3270                         return I40E_ERR_PARAM;
3271         }
3272
3273         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3274                                   rule_type, dest_vsi, count, mr_list,
3275                                   cmd_details, rule_id, rules_used, rules_free);
3276 }
3277
3278 /**
3279  * i40e_aq_delete_mirrorrule - delete a mirror rule
3280  * @hw: pointer to the hw struct
3281  * @sw_seid: Switch SEID (to which rule refers)
3282  * @rule_type: Rule Type (ingress/egress/VLAN)
3283  * @count: length of the list
3284  * @rule_id: Rule ID that is returned in the receive desc as part of
3285  *              add_mirrorrule.
3286  * @mr_list: list of mirrored VLAN IDs to be removed
3287  * @cmd_details: pointer to command details structure or NULL
3288  * @rules_used: Number of rules used in internal switch
3289  * @rules_free: Number of rules free in internal switch
3290  *
3291  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3292  **/
3293 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3294                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3295                         struct i40e_asq_cmd_details *cmd_details,
3296                         u16 *rules_used, u16 *rules_free)
3297 {
3298         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3299         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3300                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3301                  * mirroring. For other rule_type, count and rule_type should
3302                  * not matter.
3303                  */
3304                 if (count == 0 || !mr_list)
3305                         return I40E_ERR_PARAM;
3306         }
3307
3308         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3309                                   rule_type, rule_id, count, mr_list,
3310                                   cmd_details, NULL, rules_used, rules_free);
3311 }
3312
3313 /**
3314  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3315  * @hw: pointer to the hw struct
3316  * @seid: VSI for the vlan filters
3317  * @v_list: list of vlan filters to be added
3318  * @count: length of the list
3319  * @cmd_details: pointer to command details structure or NULL
3320  **/
3321 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3322                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3323                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3324 {
3325         struct i40e_aq_desc desc;
3326         struct i40e_aqc_macvlan *cmd =
3327                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3328         enum i40e_status_code status;
3329         u16 buf_size;
3330
3331         if (count == 0 || !v_list || !hw)
3332                 return I40E_ERR_PARAM;
3333
3334         buf_size = count * sizeof(*v_list);
3335
3336         /* prep the rest of the request */
3337         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3338         cmd->num_addresses = CPU_TO_LE16(count);
3339         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3340         cmd->seid[1] = 0;
3341         cmd->seid[2] = 0;
3342
3343         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3344         if (buf_size > I40E_AQ_LARGE_BUF)
3345                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3346
3347         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3348                                        cmd_details);
3349
3350         return status;
3351 }
3352
3353 /**
3354  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3355  * @hw: pointer to the hw struct
3356  * @seid: VSI for the vlan filters
3357  * @v_list: list of macvlans to be removed
3358  * @count: length of the list
3359  * @cmd_details: pointer to command details structure or NULL
3360  **/
3361 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3362                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3363                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3364 {
3365         struct i40e_aq_desc desc;
3366         struct i40e_aqc_macvlan *cmd =
3367                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3368         enum i40e_status_code status;
3369         u16 buf_size;
3370
3371         if (count == 0 || !v_list || !hw)
3372                 return I40E_ERR_PARAM;
3373
3374         buf_size = count * sizeof(*v_list);
3375
3376         /* prep the rest of the request */
3377         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3378         cmd->num_addresses = CPU_TO_LE16(count);
3379         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3380         cmd->seid[1] = 0;
3381         cmd->seid[2] = 0;
3382
3383         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3384         if (buf_size > I40E_AQ_LARGE_BUF)
3385                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3386
3387         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3388                                        cmd_details);
3389
3390         return status;
3391 }
3392
3393 /**
3394  * i40e_aq_send_msg_to_vf
3395  * @hw: pointer to the hardware structure
3396  * @vfid: vf id to send msg
3397  * @v_opcode: opcodes for VF-PF communication
3398  * @v_retval: return error code
3399  * @msg: pointer to the msg buffer
3400  * @msglen: msg length
3401  * @cmd_details: pointer to command details
3402  *
3403  * send msg to vf
3404  **/
3405 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3406                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3407                                 struct i40e_asq_cmd_details *cmd_details)
3408 {
3409         struct i40e_aq_desc desc;
3410         struct i40e_aqc_pf_vf_message *cmd =
3411                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3412         enum i40e_status_code status;
3413
3414         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3415         cmd->id = CPU_TO_LE32(vfid);
3416         desc.cookie_high = CPU_TO_LE32(v_opcode);
3417         desc.cookie_low = CPU_TO_LE32(v_retval);
3418         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3419         if (msglen) {
3420                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3421                                                 I40E_AQ_FLAG_RD));
3422                 if (msglen > I40E_AQ_LARGE_BUF)
3423                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3424                 desc.datalen = CPU_TO_LE16(msglen);
3425         }
3426         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3427
3428         return status;
3429 }
3430
3431 /**
3432  * i40e_aq_debug_read_register
3433  * @hw: pointer to the hw struct
3434  * @reg_addr: register address
3435  * @reg_val: register value
3436  * @cmd_details: pointer to command details structure or NULL
3437  *
3438  * Read the register using the admin queue commands
3439  **/
3440 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3441                                 u32 reg_addr, u64 *reg_val,
3442                                 struct i40e_asq_cmd_details *cmd_details)
3443 {
3444         struct i40e_aq_desc desc;
3445         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3446                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3447         enum i40e_status_code status;
3448
3449         if (reg_val == NULL)
3450                 return I40E_ERR_PARAM;
3451
3452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3453
3454         cmd_resp->address = CPU_TO_LE32(reg_addr);
3455
3456         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3457
3458         if (status == I40E_SUCCESS) {
3459                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3460                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3461         }
3462
3463         return status;
3464 }
3465
3466 /**
3467  * i40e_aq_debug_write_register
3468  * @hw: pointer to the hw struct
3469  * @reg_addr: register address
3470  * @reg_val: register value
3471  * @cmd_details: pointer to command details structure or NULL
3472  *
3473  * Write to a register using the admin queue commands
3474  **/
3475 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3476                                 u32 reg_addr, u64 reg_val,
3477                                 struct i40e_asq_cmd_details *cmd_details)
3478 {
3479         struct i40e_aq_desc desc;
3480         struct i40e_aqc_debug_reg_read_write *cmd =
3481                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3482         enum i40e_status_code status;
3483
3484         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3485
3486         cmd->address = CPU_TO_LE32(reg_addr);
3487         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3488         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3489
3490         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3491
3492         return status;
3493 }
3494
3495 /**
3496  * i40e_aq_request_resource
3497  * @hw: pointer to the hw struct
3498  * @resource: resource id
3499  * @access: access type
3500  * @sdp_number: resource number
3501  * @timeout: the maximum time in ms that the driver may hold the resource
3502  * @cmd_details: pointer to command details structure or NULL
3503  *
3504  * requests common resource using the admin queue commands
3505  **/
3506 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3507                                 enum i40e_aq_resources_ids resource,
3508                                 enum i40e_aq_resource_access_type access,
3509                                 u8 sdp_number, u64 *timeout,
3510                                 struct i40e_asq_cmd_details *cmd_details)
3511 {
3512         struct i40e_aq_desc desc;
3513         struct i40e_aqc_request_resource *cmd_resp =
3514                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3515         enum i40e_status_code status;
3516
3517         DEBUGFUNC("i40e_aq_request_resource");
3518
3519         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3520
3521         cmd_resp->resource_id = CPU_TO_LE16(resource);
3522         cmd_resp->access_type = CPU_TO_LE16(access);
3523         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3524
3525         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3526         /* The completion specifies the maximum time in ms that the driver
3527          * may hold the resource in the Timeout field.
3528          * If the resource is held by someone else, the command completes with
3529          * busy return value and the timeout field indicates the maximum time
3530          * the current owner of the resource has to free it.
3531          */
3532         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3533                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3534
3535         return status;
3536 }
3537
3538 /**
3539  * i40e_aq_release_resource
3540  * @hw: pointer to the hw struct
3541  * @resource: resource id
3542  * @sdp_number: resource number
3543  * @cmd_details: pointer to command details structure or NULL
3544  *
3545  * release common resource using the admin queue commands
3546  **/
3547 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3548                                 enum i40e_aq_resources_ids resource,
3549                                 u8 sdp_number,
3550                                 struct i40e_asq_cmd_details *cmd_details)
3551 {
3552         struct i40e_aq_desc desc;
3553         struct i40e_aqc_request_resource *cmd =
3554                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3555         enum i40e_status_code status;
3556
3557         DEBUGFUNC("i40e_aq_release_resource");
3558
3559         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3560
3561         cmd->resource_id = CPU_TO_LE16(resource);
3562         cmd->resource_number = CPU_TO_LE32(sdp_number);
3563
3564         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3565
3566         return status;
3567 }
3568
3569 /**
3570  * i40e_aq_read_nvm
3571  * @hw: pointer to the hw struct
3572  * @module_pointer: module pointer location in words from the NVM beginning
3573  * @offset: byte offset from the module beginning
3574  * @length: length of the section to be read (in bytes from the offset)
3575  * @data: command buffer (size [bytes] = length)
3576  * @last_command: tells if this is the last command in a series
3577  * @cmd_details: pointer to command details structure or NULL
3578  *
3579  * Read the NVM using the admin queue commands
3580  **/
3581 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3582                                 u32 offset, u16 length, void *data,
3583                                 bool last_command,
3584                                 struct i40e_asq_cmd_details *cmd_details)
3585 {
3586         struct i40e_aq_desc desc;
3587         struct i40e_aqc_nvm_update *cmd =
3588                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3589         enum i40e_status_code status;
3590
3591         DEBUGFUNC("i40e_aq_read_nvm");
3592
3593         /* In offset the highest byte must be zeroed. */
3594         if (offset & 0xFF000000) {
3595                 status = I40E_ERR_PARAM;
3596                 goto i40e_aq_read_nvm_exit;
3597         }
3598
3599         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3600
3601         /* If this is the last command in a series, set the proper flag. */
3602         if (last_command)
3603                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3604         cmd->module_pointer = module_pointer;
3605         cmd->offset = CPU_TO_LE32(offset);
3606         cmd->length = CPU_TO_LE16(length);
3607
3608         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3609         if (length > I40E_AQ_LARGE_BUF)
3610                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3611
3612         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3613
3614 i40e_aq_read_nvm_exit:
3615         return status;
3616 }
3617
3618 /**
3619  * i40e_aq_read_nvm_config - read an nvm config block
3620  * @hw: pointer to the hw struct
3621  * @cmd_flags: NVM access admin command bits
3622  * @field_id: field or feature id
3623  * @data: buffer for result
3624  * @buf_size: buffer size
3625  * @element_count: pointer to count of elements read by FW
3626  * @cmd_details: pointer to command details structure or NULL
3627  **/
3628 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3629                                 u8 cmd_flags, u32 field_id, void *data,
3630                                 u16 buf_size, u16 *element_count,
3631                                 struct i40e_asq_cmd_details *cmd_details)
3632 {
3633         struct i40e_aq_desc desc;
3634         struct i40e_aqc_nvm_config_read *cmd =
3635                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3636         enum i40e_status_code status;
3637
3638         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3639         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3640         if (buf_size > I40E_AQ_LARGE_BUF)
3641                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3642
3643         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3644         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3645         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3646                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3647         else
3648                 cmd->element_id_msw = 0;
3649
3650         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3651
3652         if (!status && element_count)
3653                 *element_count = LE16_TO_CPU(cmd->element_count);
3654
3655         return status;
3656 }
3657
3658 /**
3659  * i40e_aq_write_nvm_config - write an nvm config block
3660  * @hw: pointer to the hw struct
3661  * @cmd_flags: NVM access admin command bits
3662  * @data: buffer for result
3663  * @buf_size: buffer size
3664  * @element_count: count of elements to be written
3665  * @cmd_details: pointer to command details structure or NULL
3666  **/
3667 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3668                                 u8 cmd_flags, void *data, u16 buf_size,
3669                                 u16 element_count,
3670                                 struct i40e_asq_cmd_details *cmd_details)
3671 {
3672         struct i40e_aq_desc desc;
3673         struct i40e_aqc_nvm_config_write *cmd =
3674                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3675         enum i40e_status_code status;
3676
3677         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3678         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3679         if (buf_size > I40E_AQ_LARGE_BUF)
3680                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3681
3682         cmd->element_count = CPU_TO_LE16(element_count);
3683         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3684         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3685
3686         return status;
3687 }
3688
3689 /**
3690  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3691  * @hw: pointer to the hw struct
3692  * @buff: buffer for result
3693  * @buff_size: buffer size
3694  * @cmd_details: pointer to command details structure or NULL
3695  **/
3696 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3697                                 void *buff, u16 buff_size,
3698                                 struct i40e_asq_cmd_details *cmd_details)
3699 {
3700         struct i40e_aq_desc desc;
3701         enum i40e_status_code status;
3702
3703         UNREFERENCED_2PARAMETER(buff, buff_size);
3704
3705         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3706         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3707         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3708                 status = I40E_ERR_NOT_IMPLEMENTED;
3709
3710         return status;
3711 }
3712
3713 /**
3714  * i40e_aq_erase_nvm
3715  * @hw: pointer to the hw struct
3716  * @module_pointer: module pointer location in words from the NVM beginning
3717  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3718  * @length: length of the section to be erased (expressed in 4 KB)
3719  * @last_command: tells if this is the last command in a series
3720  * @cmd_details: pointer to command details structure or NULL
3721  *
3722  * Erase the NVM sector using the admin queue commands
3723  **/
3724 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3725                                 u32 offset, u16 length, bool last_command,
3726                                 struct i40e_asq_cmd_details *cmd_details)
3727 {
3728         struct i40e_aq_desc desc;
3729         struct i40e_aqc_nvm_update *cmd =
3730                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3731         enum i40e_status_code status;
3732
3733         DEBUGFUNC("i40e_aq_erase_nvm");
3734
3735         /* In offset the highest byte must be zeroed. */
3736         if (offset & 0xFF000000) {
3737                 status = I40E_ERR_PARAM;
3738                 goto i40e_aq_erase_nvm_exit;
3739         }
3740
3741         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3742
3743         /* If this is the last command in a series, set the proper flag. */
3744         if (last_command)
3745                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3746         cmd->module_pointer = module_pointer;
3747         cmd->offset = CPU_TO_LE32(offset);
3748         cmd->length = CPU_TO_LE16(length);
3749
3750         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3751
3752 i40e_aq_erase_nvm_exit:
3753         return status;
3754 }
3755
3756 /**
3757  * i40e_parse_discover_capabilities
3758  * @hw: pointer to the hw struct
3759  * @buff: pointer to a buffer containing device/function capability records
3760  * @cap_count: number of capability records in the list
3761  * @list_type_opc: type of capabilities list to parse
3762  *
3763  * Parse the device/function capabilities list.
3764  **/
3765 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3766                                      u32 cap_count,
3767                                      enum i40e_admin_queue_opc list_type_opc)
3768 {
3769         struct i40e_aqc_list_capabilities_element_resp *cap;
3770         u32 valid_functions, num_functions;
3771         u32 number, logical_id, phys_id;
3772         struct i40e_hw_capabilities *p;
3773         enum i40e_status_code status;
3774         u16 id, ocp_cfg_word0;
3775         u8 major_rev;
3776         u32 i = 0;
3777
3778         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3779
3780         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3781                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3782         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3783                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3784         else
3785                 return;
3786
3787         for (i = 0; i < cap_count; i++, cap++) {
3788                 id = LE16_TO_CPU(cap->id);
3789                 number = LE32_TO_CPU(cap->number);
3790                 logical_id = LE32_TO_CPU(cap->logical_id);
3791                 phys_id = LE32_TO_CPU(cap->phys_id);
3792                 major_rev = cap->major_rev;
3793
3794                 switch (id) {
3795                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3796                         p->switch_mode = number;
3797                         i40e_debug(hw, I40E_DEBUG_INIT,
3798                                    "HW Capability: Switch mode = %d\n",
3799                                    p->switch_mode);
3800                         break;
3801                 case I40E_AQ_CAP_ID_MNG_MODE:
3802                         p->management_mode = number;
3803                         if (major_rev > 1) {
3804                                 p->mng_protocols_over_mctp = logical_id;
3805                                 i40e_debug(hw, I40E_DEBUG_INIT,
3806                                            "HW Capability: Protocols over MCTP = %d\n",
3807                                            p->mng_protocols_over_mctp);
3808                         } else {
3809                                 p->mng_protocols_over_mctp = 0;
3810                         }
3811                         i40e_debug(hw, I40E_DEBUG_INIT,
3812                                    "HW Capability: Management Mode = %d\n",
3813                                    p->management_mode);
3814                         break;
3815                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3816                         p->npar_enable = number;
3817                         i40e_debug(hw, I40E_DEBUG_INIT,
3818                                    "HW Capability: NPAR enable = %d\n",
3819                                    p->npar_enable);
3820                         break;
3821                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3822                         p->os2bmc = number;
3823                         i40e_debug(hw, I40E_DEBUG_INIT,
3824                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3825                         break;
3826                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3827                         p->valid_functions = number;
3828                         i40e_debug(hw, I40E_DEBUG_INIT,
3829                                    "HW Capability: Valid Functions = %d\n",
3830                                    p->valid_functions);
3831                         break;
3832                 case I40E_AQ_CAP_ID_SRIOV:
3833                         if (number == 1)
3834                                 p->sr_iov_1_1 = true;
3835                         i40e_debug(hw, I40E_DEBUG_INIT,
3836                                    "HW Capability: SR-IOV = %d\n",
3837                                    p->sr_iov_1_1);
3838                         break;
3839                 case I40E_AQ_CAP_ID_VF:
3840                         p->num_vfs = number;
3841                         p->vf_base_id = logical_id;
3842                         i40e_debug(hw, I40E_DEBUG_INIT,
3843                                    "HW Capability: VF count = %d\n",
3844                                    p->num_vfs);
3845                         i40e_debug(hw, I40E_DEBUG_INIT,
3846                                    "HW Capability: VF base_id = %d\n",
3847                                    p->vf_base_id);
3848                         break;
3849                 case I40E_AQ_CAP_ID_VMDQ:
3850                         if (number == 1)
3851                                 p->vmdq = true;
3852                         i40e_debug(hw, I40E_DEBUG_INIT,
3853                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3854                         break;
3855                 case I40E_AQ_CAP_ID_8021QBG:
3856                         if (number == 1)
3857                                 p->evb_802_1_qbg = true;
3858                         i40e_debug(hw, I40E_DEBUG_INIT,
3859                                    "HW Capability: 802.1Qbg = %d\n", number);
3860                         break;
3861                 case I40E_AQ_CAP_ID_8021QBR:
3862                         if (number == 1)
3863                                 p->evb_802_1_qbh = true;
3864                         i40e_debug(hw, I40E_DEBUG_INIT,
3865                                    "HW Capability: 802.1Qbh = %d\n", number);
3866                         break;
3867                 case I40E_AQ_CAP_ID_VSI:
3868                         p->num_vsis = number;
3869                         i40e_debug(hw, I40E_DEBUG_INIT,
3870                                    "HW Capability: VSI count = %d\n",
3871                                    p->num_vsis);
3872                         break;
3873                 case I40E_AQ_CAP_ID_DCB:
3874                         if (number == 1) {
3875                                 p->dcb = true;
3876                                 p->enabled_tcmap = logical_id;
3877                                 p->maxtc = phys_id;
3878                         }
3879                         i40e_debug(hw, I40E_DEBUG_INIT,
3880                                    "HW Capability: DCB = %d\n", p->dcb);
3881                         i40e_debug(hw, I40E_DEBUG_INIT,
3882                                    "HW Capability: TC Mapping = %d\n",
3883                                    logical_id);
3884                         i40e_debug(hw, I40E_DEBUG_INIT,
3885                                    "HW Capability: TC Max = %d\n", p->maxtc);
3886                         break;
3887                 case I40E_AQ_CAP_ID_FCOE:
3888                         if (number == 1)
3889                                 p->fcoe = true;
3890                         i40e_debug(hw, I40E_DEBUG_INIT,
3891                                    "HW Capability: FCOE = %d\n", p->fcoe);
3892                         break;
3893                 case I40E_AQ_CAP_ID_ISCSI:
3894                         if (number == 1)
3895                                 p->iscsi = true;
3896                         i40e_debug(hw, I40E_DEBUG_INIT,
3897                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3898                         break;
3899                 case I40E_AQ_CAP_ID_RSS:
3900                         p->rss = true;
3901                         p->rss_table_size = number;
3902                         p->rss_table_entry_width = logical_id;
3903                         i40e_debug(hw, I40E_DEBUG_INIT,
3904                                    "HW Capability: RSS = %d\n", p->rss);
3905                         i40e_debug(hw, I40E_DEBUG_INIT,
3906                                    "HW Capability: RSS table size = %d\n",
3907                                    p->rss_table_size);
3908                         i40e_debug(hw, I40E_DEBUG_INIT,
3909                                    "HW Capability: RSS table width = %d\n",
3910                                    p->rss_table_entry_width);
3911                         break;
3912                 case I40E_AQ_CAP_ID_RXQ:
3913                         p->num_rx_qp = number;
3914                         p->base_queue = phys_id;
3915                         i40e_debug(hw, I40E_DEBUG_INIT,
3916                                    "HW Capability: Rx QP = %d\n", number);
3917                         i40e_debug(hw, I40E_DEBUG_INIT,
3918                                    "HW Capability: base_queue = %d\n",
3919                                    p->base_queue);
3920                         break;
3921                 case I40E_AQ_CAP_ID_TXQ:
3922                         p->num_tx_qp = number;
3923                         p->base_queue = phys_id;
3924                         i40e_debug(hw, I40E_DEBUG_INIT,
3925                                    "HW Capability: Tx QP = %d\n", number);
3926                         i40e_debug(hw, I40E_DEBUG_INIT,
3927                                    "HW Capability: base_queue = %d\n",
3928                                    p->base_queue);
3929                         break;
3930                 case I40E_AQ_CAP_ID_MSIX:
3931                         p->num_msix_vectors = number;
3932                         i40e_debug(hw, I40E_DEBUG_INIT,
3933                                    "HW Capability: MSIX vector count = %d\n",
3934                                    p->num_msix_vectors);
3935                         break;
3936                 case I40E_AQ_CAP_ID_VF_MSIX:
3937                         p->num_msix_vectors_vf = number;
3938                         i40e_debug(hw, I40E_DEBUG_INIT,
3939                                    "HW Capability: MSIX VF vector count = %d\n",
3940                                    p->num_msix_vectors_vf);
3941                         break;
3942                 case I40E_AQ_CAP_ID_FLEX10:
3943                         if (major_rev == 1) {
3944                                 if (number == 1) {
3945                                         p->flex10_enable = true;
3946                                         p->flex10_capable = true;
3947                                 }
3948                         } else {
3949                                 /* Capability revision >= 2 */
3950                                 if (number & 1)
3951                                         p->flex10_enable = true;
3952                                 if (number & 2)
3953                                         p->flex10_capable = true;
3954                         }
3955                         p->flex10_mode = logical_id;
3956                         p->flex10_status = phys_id;
3957                         i40e_debug(hw, I40E_DEBUG_INIT,
3958                                    "HW Capability: Flex10 mode = %d\n",
3959                                    p->flex10_mode);
3960                         i40e_debug(hw, I40E_DEBUG_INIT,
3961                                    "HW Capability: Flex10 status = %d\n",
3962                                    p->flex10_status);
3963                         break;
3964                 case I40E_AQ_CAP_ID_CEM:
3965                         if (number == 1)
3966                                 p->mgmt_cem = true;
3967                         i40e_debug(hw, I40E_DEBUG_INIT,
3968                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3969                         break;
3970                 case I40E_AQ_CAP_ID_IWARP:
3971                         if (number == 1)
3972                                 p->iwarp = true;
3973                         i40e_debug(hw, I40E_DEBUG_INIT,
3974                                    "HW Capability: iWARP = %d\n", p->iwarp);
3975                         break;
3976                 case I40E_AQ_CAP_ID_LED:
3977                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3978                                 p->led[phys_id] = true;
3979                         i40e_debug(hw, I40E_DEBUG_INIT,
3980                                    "HW Capability: LED - PIN %d\n", phys_id);
3981                         break;
3982                 case I40E_AQ_CAP_ID_SDP:
3983                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3984                                 p->sdp[phys_id] = true;
3985                         i40e_debug(hw, I40E_DEBUG_INIT,
3986                                    "HW Capability: SDP - PIN %d\n", phys_id);
3987                         break;
3988                 case I40E_AQ_CAP_ID_MDIO:
3989                         if (number == 1) {
3990                                 p->mdio_port_num = phys_id;
3991                                 p->mdio_port_mode = logical_id;
3992                         }
3993                         i40e_debug(hw, I40E_DEBUG_INIT,
3994                                    "HW Capability: MDIO port number = %d\n",
3995                                    p->mdio_port_num);
3996                         i40e_debug(hw, I40E_DEBUG_INIT,
3997                                    "HW Capability: MDIO port mode = %d\n",
3998                                    p->mdio_port_mode);
3999                         break;
4000                 case I40E_AQ_CAP_ID_1588:
4001                         if (number == 1)
4002                                 p->ieee_1588 = true;
4003                         i40e_debug(hw, I40E_DEBUG_INIT,
4004                                    "HW Capability: IEEE 1588 = %d\n",
4005                                    p->ieee_1588);
4006                         break;
4007                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
4008                         p->fd = true;
4009                         p->fd_filters_guaranteed = number;
4010                         p->fd_filters_best_effort = logical_id;
4011                         i40e_debug(hw, I40E_DEBUG_INIT,
4012                                    "HW Capability: Flow Director = 1\n");
4013                         i40e_debug(hw, I40E_DEBUG_INIT,
4014                                    "HW Capability: Guaranteed FD filters = %d\n",
4015                                    p->fd_filters_guaranteed);
4016                         break;
4017                 case I40E_AQ_CAP_ID_WSR_PROT:
4018                         p->wr_csr_prot = (u64)number;
4019                         p->wr_csr_prot |= (u64)logical_id << 32;
4020                         i40e_debug(hw, I40E_DEBUG_INIT,
4021                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
4022                                    (p->wr_csr_prot & 0xffff));
4023                         break;
4024                 case I40E_AQ_CAP_ID_NVM_MGMT:
4025                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
4026                                 p->sec_rev_disabled = true;
4027                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
4028                                 p->update_disabled = true;
4029                         break;
4030                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
4031                         hw->num_wol_proxy_filters = (u16)number;
4032                         hw->wol_proxy_vsi_seid = (u16)logical_id;
4033                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
4034                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
4035                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
4036                         else
4037                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
4038                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
4039                         i40e_debug(hw, I40E_DEBUG_INIT,
4040                                    "HW Capability: WOL proxy filters = %d\n",
4041                                    hw->num_wol_proxy_filters);
4042                         break;
4043                 default:
4044                         break;
4045                 }
4046         }
4047
4048         if (p->fcoe)
4049                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4050
4051         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4052         p->fcoe = false;
4053
4054         /* count the enabled ports (aka the "not disabled" ports) */
4055         hw->num_ports = 0;
4056         for (i = 0; i < 4; i++) {
4057                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4058                 u64 port_cfg = 0;
4059
4060                 /* use AQ read to get the physical register offset instead
4061                  * of the port relative offset
4062                  */
4063                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4064                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4065                         hw->num_ports++;
4066         }
4067
4068         /* OCP cards case: if a mezz is removed the ethernet port is at
4069          * disabled state in PRTGEN_CNF register. Additional NVM read is
4070          * needed in order to check if we are dealing with OCP card.
4071          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4072          * physical ports results in wrong partition id calculation and thus
4073          * not supporting WoL.
4074          */
4075         if (hw->mac.type == I40E_MAC_X722) {
4076                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4077                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4078                                                   2 * I40E_SR_OCP_CFG_WORD0,
4079                                                   sizeof(ocp_cfg_word0),
4080                                                   &ocp_cfg_word0, true, NULL);
4081                         if (status == I40E_SUCCESS &&
4082                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4083                                 hw->num_ports = 4;
4084                         i40e_release_nvm(hw);
4085                 }
4086         }
4087
4088         valid_functions = p->valid_functions;
4089         num_functions = 0;
4090         while (valid_functions) {
4091                 if (valid_functions & 1)
4092                         num_functions++;
4093                 valid_functions >>= 1;
4094         }
4095
4096         /* partition id is 1-based, and functions are evenly spread
4097          * across the ports as partitions
4098          */
4099         if (hw->num_ports != 0) {
4100                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4101                 hw->num_partitions = num_functions / hw->num_ports;
4102         }
4103
4104         /* additional HW specific goodies that might
4105          * someday be HW version specific
4106          */
4107         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4108 }
4109
4110 /**
4111  * i40e_aq_discover_capabilities
4112  * @hw: pointer to the hw struct
4113  * @buff: a virtual buffer to hold the capabilities
4114  * @buff_size: Size of the virtual buffer
4115  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4116  * @list_type_opc: capabilities type to discover - pass in the command opcode
4117  * @cmd_details: pointer to command details structure or NULL
4118  *
4119  * Get the device capabilities descriptions from the firmware
4120  **/
4121 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4122                                 void *buff, u16 buff_size, u16 *data_size,
4123                                 enum i40e_admin_queue_opc list_type_opc,
4124                                 struct i40e_asq_cmd_details *cmd_details)
4125 {
4126         struct i40e_aqc_list_capabilites *cmd;
4127         struct i40e_aq_desc desc;
4128         enum i40e_status_code status = I40E_SUCCESS;
4129
4130         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4131
4132         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4133                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4134                 status = I40E_ERR_PARAM;
4135                 goto exit;
4136         }
4137
4138         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4139
4140         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4141         if (buff_size > I40E_AQ_LARGE_BUF)
4142                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4143
4144         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4145         *data_size = LE16_TO_CPU(desc.datalen);
4146
4147         if (status)
4148                 goto exit;
4149
4150         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4151                                          list_type_opc);
4152
4153 exit:
4154         return status;
4155 }
4156
4157 /**
4158  * i40e_aq_update_nvm
4159  * @hw: pointer to the hw struct
4160  * @module_pointer: module pointer location in words from the NVM beginning
4161  * @offset: byte offset from the module beginning
4162  * @length: length of the section to be written (in bytes from the offset)
4163  * @data: command buffer (size [bytes] = length)
4164  * @last_command: tells if this is the last command in a series
4165  * @preservation_flags: Preservation mode flags
4166  * @cmd_details: pointer to command details structure or NULL
4167  *
4168  * Update the NVM using the admin queue commands
4169  **/
4170 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4171                                 u32 offset, u16 length, void *data,
4172                                 bool last_command, u8 preservation_flags,
4173                                 struct i40e_asq_cmd_details *cmd_details)
4174 {
4175         struct i40e_aq_desc desc;
4176         struct i40e_aqc_nvm_update *cmd =
4177                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4178         enum i40e_status_code status;
4179
4180         DEBUGFUNC("i40e_aq_update_nvm");
4181
4182         /* In offset the highest byte must be zeroed. */
4183         if (offset & 0xFF000000) {
4184                 status = I40E_ERR_PARAM;
4185                 goto i40e_aq_update_nvm_exit;
4186         }
4187
4188         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4189
4190         /* If this is the last command in a series, set the proper flag. */
4191         if (last_command)
4192                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4193         if (hw->mac.type == I40E_MAC_X722) {
4194                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4195                         cmd->command_flags |=
4196                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4197                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4198                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4199                         cmd->command_flags |=
4200                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4201                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4202         }
4203         cmd->module_pointer = module_pointer;
4204         cmd->offset = CPU_TO_LE32(offset);
4205         cmd->length = CPU_TO_LE16(length);
4206
4207         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4208         if (length > I40E_AQ_LARGE_BUF)
4209                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4210
4211         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4212
4213 i40e_aq_update_nvm_exit:
4214         return status;
4215 }
4216
4217 /**
4218  * i40e_aq_rearrange_nvm
4219  * @hw: pointer to the hw struct
4220  * @rearrange_nvm: defines direction of rearrangement
4221  * @cmd_details: pointer to command details structure or NULL
4222  *
4223  * Rearrange NVM structure, available only for transition FW
4224  **/
4225 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4226                                 u8 rearrange_nvm,
4227                                 struct i40e_asq_cmd_details *cmd_details)
4228 {
4229         struct i40e_aqc_nvm_update *cmd;
4230         enum i40e_status_code status;
4231         struct i40e_aq_desc desc;
4232
4233         DEBUGFUNC("i40e_aq_rearrange_nvm");
4234
4235         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4236
4237         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4238
4239         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4240                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4241
4242         if (!rearrange_nvm) {
4243                 status = I40E_ERR_PARAM;
4244                 goto i40e_aq_rearrange_nvm_exit;
4245         }
4246
4247         cmd->command_flags |= rearrange_nvm;
4248         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4249
4250 i40e_aq_rearrange_nvm_exit:
4251         return status;
4252 }
4253
4254 /**
4255  * i40e_aq_nvm_progress
4256  * @hw: pointer to the hw struct
4257  * @progress: pointer to progress returned from AQ
4258  * @cmd_details: pointer to command details structure or NULL
4259  *
4260  * Gets progress of flash rearrangement process
4261  **/
4262 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4263                                 struct i40e_asq_cmd_details *cmd_details)
4264 {
4265         enum i40e_status_code status;
4266         struct i40e_aq_desc desc;
4267
4268         DEBUGFUNC("i40e_aq_nvm_progress");
4269
4270         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4271         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4272         *progress = desc.params.raw[0];
4273         return status;
4274 }
4275
4276 /**
4277  * i40e_aq_get_lldp_mib
4278  * @hw: pointer to the hw struct
4279  * @bridge_type: type of bridge requested
4280  * @mib_type: Local, Remote or both Local and Remote MIBs
4281  * @buff: pointer to a user supplied buffer to store the MIB block
4282  * @buff_size: size of the buffer (in bytes)
4283  * @local_len : length of the returned Local LLDP MIB
4284  * @remote_len: length of the returned Remote LLDP MIB
4285  * @cmd_details: pointer to command details structure or NULL
4286  *
4287  * Requests the complete LLDP MIB (entire packet).
4288  **/
4289 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4290                                 u8 mib_type, void *buff, u16 buff_size,
4291                                 u16 *local_len, u16 *remote_len,
4292                                 struct i40e_asq_cmd_details *cmd_details)
4293 {
4294         struct i40e_aq_desc desc;
4295         struct i40e_aqc_lldp_get_mib *cmd =
4296                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4297         struct i40e_aqc_lldp_get_mib *resp =
4298                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4299         enum i40e_status_code status;
4300
4301         if (buff_size == 0 || !buff)
4302                 return I40E_ERR_PARAM;
4303
4304         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4305         /* Indirect Command */
4306         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4307
4308         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4309         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4310                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4311
4312         desc.datalen = CPU_TO_LE16(buff_size);
4313
4314         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4315         if (buff_size > I40E_AQ_LARGE_BUF)
4316                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4317
4318         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4319         if (!status) {
4320                 if (local_len != NULL)
4321                         *local_len = LE16_TO_CPU(resp->local_len);
4322                 if (remote_len != NULL)
4323                         *remote_len = LE16_TO_CPU(resp->remote_len);
4324         }
4325
4326         return status;
4327 }
4328
4329  /**
4330  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4331  * @hw: pointer to the hw struct
4332  * @mib_type: Local, Remote or both Local and Remote MIBs
4333  * @buff: pointer to a user supplied buffer to store the MIB block
4334  * @buff_size: size of the buffer (in bytes)
4335  * @cmd_details: pointer to command details structure or NULL
4336  *
4337  * Set the LLDP MIB.
4338  **/
4339 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4340                                 u8 mib_type, void *buff, u16 buff_size,
4341                                 struct i40e_asq_cmd_details *cmd_details)
4342 {
4343         struct i40e_aq_desc desc;
4344         struct i40e_aqc_lldp_set_local_mib *cmd =
4345                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4346         enum i40e_status_code status;
4347
4348         if (buff_size == 0 || !buff)
4349                 return I40E_ERR_PARAM;
4350
4351         i40e_fill_default_direct_cmd_desc(&desc,
4352                                 i40e_aqc_opc_lldp_set_local_mib);
4353         /* Indirect Command */
4354         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4355         if (buff_size > I40E_AQ_LARGE_BUF)
4356                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4357         desc.datalen = CPU_TO_LE16(buff_size);
4358
4359         cmd->type = mib_type;
4360         cmd->length = CPU_TO_LE16(buff_size);
4361         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4362         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4363
4364         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4365         return status;
4366 }
4367
4368 /**
4369  * i40e_aq_cfg_lldp_mib_change_event
4370  * @hw: pointer to the hw struct
4371  * @enable_update: Enable or Disable event posting
4372  * @cmd_details: pointer to command details structure or NULL
4373  *
4374  * Enable or Disable posting of an event on ARQ when LLDP MIB
4375  * associated with the interface changes
4376  **/
4377 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4378                                 bool enable_update,
4379                                 struct i40e_asq_cmd_details *cmd_details)
4380 {
4381         struct i40e_aq_desc desc;
4382         struct i40e_aqc_lldp_update_mib *cmd =
4383                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4384         enum i40e_status_code status;
4385
4386         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4387
4388         if (!enable_update)
4389                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4390
4391         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4392
4393         return status;
4394 }
4395
4396 /**
4397  * i40e_aq_restore_lldp
4398  * @hw: pointer to the hw struct
4399  * @setting: pointer to factory setting variable or NULL
4400  * @restore: True if factory settings should be restored
4401  * @cmd_details: pointer to command details structure or NULL
4402  *
4403  * Restore LLDP Agent factory settings if @restore set to True. In other case
4404  * only returns factory setting in AQ response.
4405  **/
4406 enum i40e_status_code
4407 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4408                      struct i40e_asq_cmd_details *cmd_details)
4409 {
4410         struct i40e_aq_desc desc;
4411         struct i40e_aqc_lldp_restore *cmd =
4412                 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4413         enum i40e_status_code status;
4414
4415         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4416                 i40e_debug(hw, I40E_DEBUG_ALL,
4417                            "Restore LLDP not supported by current FW version.\n");
4418                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4419         }
4420
4421         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4422
4423         if (restore)
4424                 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4425
4426         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4427
4428         if (setting)
4429                 *setting = cmd->command & 1;
4430
4431         return status;
4432 }
4433
4434 /**
4435  * i40e_aq_stop_lldp
4436  * @hw: pointer to the hw struct
4437  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4438  * @persist: True if stop of LLDP should be persistent across power cycles
4439  * @cmd_details: pointer to command details structure or NULL
4440  *
4441  * Stop or Shutdown the embedded LLDP Agent
4442  **/
4443 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4444                                 bool persist,
4445                                 struct i40e_asq_cmd_details *cmd_details)
4446 {
4447         struct i40e_aq_desc desc;
4448         struct i40e_aqc_lldp_stop *cmd =
4449                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4450         enum i40e_status_code status;
4451
4452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4453
4454         if (shutdown_agent)
4455                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4456
4457         if (persist) {
4458                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4459                         cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4460                 else
4461                         i40e_debug(hw, I40E_DEBUG_ALL,
4462                                    "Persistent Stop LLDP not supported by current FW version.\n");
4463         }
4464
4465         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4466
4467         return status;
4468 }
4469
4470 /**
4471  * i40e_aq_start_lldp
4472  * @hw: pointer to the hw struct
4473  * @persist: True if start of LLDP should be persistent across power cycles
4474  * @cmd_details: pointer to command details structure or NULL
4475  *
4476  * Start the embedded LLDP Agent on all ports.
4477  **/
4478 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4479                                 bool persist,
4480                                 struct i40e_asq_cmd_details *cmd_details)
4481 {
4482         struct i40e_aq_desc desc;
4483         struct i40e_aqc_lldp_start *cmd =
4484                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4485         enum i40e_status_code status;
4486
4487         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4488
4489         cmd->command = I40E_AQ_LLDP_AGENT_START;
4490
4491         if (persist) {
4492                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4493                         cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4494                 else
4495                         i40e_debug(hw, I40E_DEBUG_ALL,
4496                                    "Persistent Start LLDP not supported by current FW version.\n");
4497         }
4498
4499         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4500
4501         return status;
4502 }
4503
4504 /**
4505  * i40e_aq_set_dcb_parameters
4506  * @hw: pointer to the hw struct
4507  * @cmd_details: pointer to command details structure or NULL
4508  * @dcb_enable: True if DCB configuration needs to be applied
4509  *
4510  **/
4511 enum i40e_status_code
4512 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4513                            struct i40e_asq_cmd_details *cmd_details)
4514 {
4515         struct i40e_aq_desc desc;
4516         struct i40e_aqc_set_dcb_parameters *cmd =
4517                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4518         enum i40e_status_code status;
4519
4520         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4521                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4522
4523         i40e_fill_default_direct_cmd_desc(&desc,
4524                                           i40e_aqc_opc_set_dcb_parameters);
4525
4526         if (dcb_enable) {
4527                 cmd->valid_flags = I40E_DCB_VALID;
4528                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4529         }
4530         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4531
4532         return status;
4533 }
4534
4535 /**
4536  * i40e_aq_get_cee_dcb_config
4537  * @hw: pointer to the hw struct
4538  * @buff: response buffer that stores CEE operational configuration
4539  * @buff_size: size of the buffer passed
4540  * @cmd_details: pointer to command details structure or NULL
4541  *
4542  * Get CEE DCBX mode operational configuration from firmware
4543  **/
4544 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4545                                 void *buff, u16 buff_size,
4546                                 struct i40e_asq_cmd_details *cmd_details)
4547 {
4548         struct i40e_aq_desc desc;
4549         enum i40e_status_code status;
4550
4551         if (buff_size == 0 || !buff)
4552                 return I40E_ERR_PARAM;
4553
4554         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4555
4556         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4557         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4558                                        cmd_details);
4559
4560         return status;
4561 }
4562
4563 /**
4564  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4565  * @hw: pointer to the hw struct
4566  * @start_agent: True if DCBx Agent needs to be Started
4567  *                              False if DCBx Agent needs to be Stopped
4568  * @cmd_details: pointer to command details structure or NULL
4569  *
4570  * Start/Stop the embedded dcbx Agent
4571  **/
4572 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4573                                 bool start_agent,
4574                                 struct i40e_asq_cmd_details *cmd_details)
4575 {
4576         struct i40e_aq_desc desc;
4577         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4578                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4579                                 &desc.params.raw;
4580         enum i40e_status_code status;
4581
4582         i40e_fill_default_direct_cmd_desc(&desc,
4583                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4584
4585         if (start_agent)
4586                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4587
4588         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4589
4590         return status;
4591 }
4592
4593 /**
4594  * i40e_aq_add_udp_tunnel
4595  * @hw: pointer to the hw struct
4596  * @udp_port: the UDP port to add in Host byte order
4597  * @protocol_index: protocol index type
4598  * @filter_index: pointer to filter index
4599  * @cmd_details: pointer to command details structure or NULL
4600  *
4601  * Note: Firmware expects the udp_port value to be in Little Endian format,
4602  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4603  * Little Endian order.
4604  **/
4605 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4606                                 u16 udp_port, u8 protocol_index,
4607                                 u8 *filter_index,
4608                                 struct i40e_asq_cmd_details *cmd_details)
4609 {
4610         struct i40e_aq_desc desc;
4611         struct i40e_aqc_add_udp_tunnel *cmd =
4612                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4613         struct i40e_aqc_del_udp_tunnel_completion *resp =
4614                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4615         enum i40e_status_code status;
4616
4617         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4618
4619         cmd->udp_port = CPU_TO_LE16(udp_port);
4620         cmd->protocol_type = protocol_index;
4621
4622         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4623
4624         if (!status && filter_index)
4625                 *filter_index = resp->index;
4626
4627         return status;
4628 }
4629
4630 /**
4631  * i40e_aq_del_udp_tunnel
4632  * @hw: pointer to the hw struct
4633  * @index: filter index
4634  * @cmd_details: pointer to command details structure or NULL
4635  **/
4636 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4637                                 struct i40e_asq_cmd_details *cmd_details)
4638 {
4639         struct i40e_aq_desc desc;
4640         struct i40e_aqc_remove_udp_tunnel *cmd =
4641                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4642         enum i40e_status_code status;
4643
4644         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4645
4646         cmd->index = index;
4647
4648         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4649
4650         return status;
4651 }
4652
4653 /**
4654  * i40e_aq_get_switch_resource_alloc (0x0204)
4655  * @hw: pointer to the hw struct
4656  * @num_entries: pointer to u8 to store the number of resource entries returned
4657  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4658  *        to store the resource information for all resource types.  Each
4659  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4660  * @count: size, in bytes, of the buffer provided
4661  * @cmd_details: pointer to command details structure or NULL
4662  *
4663  * Query the resources allocated to a function.
4664  **/
4665 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4666                         u8 *num_entries,
4667                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4668                         u16 count,
4669                         struct i40e_asq_cmd_details *cmd_details)
4670 {
4671         struct i40e_aq_desc desc;
4672         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4673                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4674         enum i40e_status_code status;
4675         u16 length = count * sizeof(*buf);
4676
4677         i40e_fill_default_direct_cmd_desc(&desc,
4678                                         i40e_aqc_opc_get_switch_resource_alloc);
4679
4680         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4681         if (length > I40E_AQ_LARGE_BUF)
4682                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4683
4684         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4685
4686         if (!status && num_entries)
4687                 *num_entries = cmd_resp->num_entries;
4688
4689         return status;
4690 }
4691
4692 /**
4693  * i40e_aq_delete_element - Delete switch element
4694  * @hw: pointer to the hw struct
4695  * @seid: the SEID to delete from the switch
4696  * @cmd_details: pointer to command details structure or NULL
4697  *
4698  * This deletes a switch element from the switch.
4699  **/
4700 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4701                                 struct i40e_asq_cmd_details *cmd_details)
4702 {
4703         struct i40e_aq_desc desc;
4704         struct i40e_aqc_switch_seid *cmd =
4705                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4706         enum i40e_status_code status;
4707
4708         if (seid == 0)
4709                 return I40E_ERR_PARAM;
4710
4711         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4712
4713         cmd->seid = CPU_TO_LE16(seid);
4714
4715         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4716
4717         return status;
4718 }
4719
4720 /**
4721  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4722  * @hw: pointer to the hw struct
4723  * @flags: component flags
4724  * @mac_seid: uplink seid (MAC SEID)
4725  * @vsi_seid: connected vsi seid
4726  * @ret_seid: seid of create pv component
4727  *
4728  * This instantiates an i40e port virtualizer with specified flags.
4729  * Depending on specified flags the port virtualizer can act as a
4730  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4731  */
4732 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4733                                        u16 mac_seid, u16 vsi_seid,
4734                                        u16 *ret_seid)
4735 {
4736         struct i40e_aq_desc desc;
4737         struct i40e_aqc_add_update_pv *cmd =
4738                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4739         struct i40e_aqc_add_update_pv_completion *resp =
4740                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4741         enum i40e_status_code status;
4742
4743         if (vsi_seid == 0)
4744                 return I40E_ERR_PARAM;
4745
4746         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4747         cmd->command_flags = CPU_TO_LE16(flags);
4748         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4749         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4750
4751         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4752         if (!status && ret_seid)
4753                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4754
4755         return status;
4756 }
4757
4758 /**
4759  * i40e_aq_add_tag - Add an S/E-tag
4760  * @hw: pointer to the hw struct
4761  * @direct_to_queue: should s-tag direct flow to a specific queue
4762  * @vsi_seid: VSI SEID to use this tag
4763  * @tag: value of the tag
4764  * @queue_num: queue number, only valid is direct_to_queue is true
4765  * @tags_used: return value, number of tags in use by this PF
4766  * @tags_free: return value, number of unallocated tags
4767  * @cmd_details: pointer to command details structure or NULL
4768  *
4769  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4770  * the number of tags allocated by the PF, and the number of unallocated
4771  * tags available.
4772  **/
4773 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4774                                 u16 vsi_seid, u16 tag, u16 queue_num,
4775                                 u16 *tags_used, u16 *tags_free,
4776                                 struct i40e_asq_cmd_details *cmd_details)
4777 {
4778         struct i40e_aq_desc desc;
4779         struct i40e_aqc_add_tag *cmd =
4780                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4781         struct i40e_aqc_add_remove_tag_completion *resp =
4782                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4783         enum i40e_status_code status;
4784
4785         if (vsi_seid == 0)
4786                 return I40E_ERR_PARAM;
4787
4788         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4789
4790         cmd->seid = CPU_TO_LE16(vsi_seid);
4791         cmd->tag = CPU_TO_LE16(tag);
4792         if (direct_to_queue) {
4793                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4794                 cmd->queue_number = CPU_TO_LE16(queue_num);
4795         }
4796
4797         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4798
4799         if (!status) {
4800                 if (tags_used != NULL)
4801                         *tags_used = LE16_TO_CPU(resp->tags_used);
4802                 if (tags_free != NULL)
4803                         *tags_free = LE16_TO_CPU(resp->tags_free);
4804         }
4805
4806         return status;
4807 }
4808
4809 /**
4810  * i40e_aq_remove_tag - Remove an S- or E-tag
4811  * @hw: pointer to the hw struct
4812  * @vsi_seid: VSI SEID this tag is associated with
4813  * @tag: value of the S-tag to delete
4814  * @tags_used: return value, number of tags in use by this PF
4815  * @tags_free: return value, number of unallocated tags
4816  * @cmd_details: pointer to command details structure or NULL
4817  *
4818  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4819  * the number of tags allocated by the PF, and the number of unallocated
4820  * tags available.
4821  **/
4822 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4823                                 u16 tag, u16 *tags_used, u16 *tags_free,
4824                                 struct i40e_asq_cmd_details *cmd_details)
4825 {
4826         struct i40e_aq_desc desc;
4827         struct i40e_aqc_remove_tag *cmd =
4828                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4829         struct i40e_aqc_add_remove_tag_completion *resp =
4830                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4831         enum i40e_status_code status;
4832
4833         if (vsi_seid == 0)
4834                 return I40E_ERR_PARAM;
4835
4836         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4837
4838         cmd->seid = CPU_TO_LE16(vsi_seid);
4839         cmd->tag = CPU_TO_LE16(tag);
4840
4841         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4842
4843         if (!status) {
4844                 if (tags_used != NULL)
4845                         *tags_used = LE16_TO_CPU(resp->tags_used);
4846                 if (tags_free != NULL)
4847                         *tags_free = LE16_TO_CPU(resp->tags_free);
4848         }
4849
4850         return status;
4851 }
4852
4853 /**
4854  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4855  * @hw: pointer to the hw struct
4856  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4857  * @etag: value of E-tag to add
4858  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4859  * @buf: address of indirect buffer
4860  * @tags_used: return value, number of E-tags in use by this port
4861  * @tags_free: return value, number of unallocated M-tags
4862  * @cmd_details: pointer to command details structure or NULL
4863  *
4864  * This associates a multicast E-tag to a port virtualizer.  It will return
4865  * the number of tags allocated by the PF, and the number of unallocated
4866  * tags available.
4867  *
4868  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4869  * num_tags_in_buf long.
4870  **/
4871 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4872                                 u16 etag, u8 num_tags_in_buf, void *buf,
4873                                 u16 *tags_used, u16 *tags_free,
4874                                 struct i40e_asq_cmd_details *cmd_details)
4875 {
4876         struct i40e_aq_desc desc;
4877         struct i40e_aqc_add_remove_mcast_etag *cmd =
4878                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4879         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4880            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4881         enum i40e_status_code status;
4882         u16 length = sizeof(u16) * num_tags_in_buf;
4883
4884         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4885                 return I40E_ERR_PARAM;
4886
4887         i40e_fill_default_direct_cmd_desc(&desc,
4888                                           i40e_aqc_opc_add_multicast_etag);
4889
4890         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4891         cmd->etag = CPU_TO_LE16(etag);
4892         cmd->num_unicast_etags = num_tags_in_buf;
4893
4894         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4895
4896         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4897
4898         if (!status) {
4899                 if (tags_used != NULL)
4900                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4901                 if (tags_free != NULL)
4902                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4903         }
4904
4905         return status;
4906 }
4907
4908 /**
4909  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4910  * @hw: pointer to the hw struct
4911  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4912  * @etag: value of the E-tag to remove
4913  * @tags_used: return value, number of tags in use by this port
4914  * @tags_free: return value, number of unallocated tags
4915  * @cmd_details: pointer to command details structure or NULL
4916  *
4917  * This deletes an E-tag from the port virtualizer.  It will return
4918  * the number of tags allocated by the port, and the number of unallocated
4919  * tags available.
4920  **/
4921 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4922                                 u16 etag, u16 *tags_used, u16 *tags_free,
4923                                 struct i40e_asq_cmd_details *cmd_details)
4924 {
4925         struct i40e_aq_desc desc;
4926         struct i40e_aqc_add_remove_mcast_etag *cmd =
4927                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4928         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4929            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4930         enum i40e_status_code status;
4931
4932
4933         if (pv_seid == 0)
4934                 return I40E_ERR_PARAM;
4935
4936         i40e_fill_default_direct_cmd_desc(&desc,
4937                                           i40e_aqc_opc_remove_multicast_etag);
4938
4939         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4940         cmd->etag = CPU_TO_LE16(etag);
4941
4942         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4943
4944         if (!status) {
4945                 if (tags_used != NULL)
4946                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4947                 if (tags_free != NULL)
4948                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4949         }
4950
4951         return status;
4952 }
4953
4954 /**
4955  * i40e_aq_update_tag - Update an S/E-tag
4956  * @hw: pointer to the hw struct
4957  * @vsi_seid: VSI SEID using this S-tag
4958  * @old_tag: old tag value
4959  * @new_tag: new tag value
4960  * @tags_used: return value, number of tags in use by this PF
4961  * @tags_free: return value, number of unallocated tags
4962  * @cmd_details: pointer to command details structure or NULL
4963  *
4964  * This updates the value of the tag currently attached to this VSI
4965  * in the switch complex.  It will return the number of tags allocated
4966  * by the PF, and the number of unallocated tags available.
4967  **/
4968 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4969                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4970                                 u16 *tags_free,
4971                                 struct i40e_asq_cmd_details *cmd_details)
4972 {
4973         struct i40e_aq_desc desc;
4974         struct i40e_aqc_update_tag *cmd =
4975                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4976         struct i40e_aqc_update_tag_completion *resp =
4977                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4978         enum i40e_status_code status;
4979
4980         if (vsi_seid == 0)
4981                 return I40E_ERR_PARAM;
4982
4983         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4984
4985         cmd->seid = CPU_TO_LE16(vsi_seid);
4986         cmd->old_tag = CPU_TO_LE16(old_tag);
4987         cmd->new_tag = CPU_TO_LE16(new_tag);
4988
4989         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4990
4991         if (!status) {
4992                 if (tags_used != NULL)
4993                         *tags_used = LE16_TO_CPU(resp->tags_used);
4994                 if (tags_free != NULL)
4995                         *tags_free = LE16_TO_CPU(resp->tags_free);
4996         }
4997
4998         return status;
4999 }
5000
5001 /**
5002  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5003  * @hw: pointer to the hw struct
5004  * @tcmap: TC map for request/release any ignore PFC condition
5005  * @request: request or release ignore PFC condition
5006  * @tcmap_ret: return TCs for which PFC is currently ignored
5007  * @cmd_details: pointer to command details structure or NULL
5008  *
5009  * This sends out request/release to ignore PFC condition for a TC.
5010  * It will return the TCs for which PFC is currently ignored.
5011  **/
5012 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5013                                 bool request, u8 *tcmap_ret,
5014                                 struct i40e_asq_cmd_details *cmd_details)
5015 {
5016         struct i40e_aq_desc desc;
5017         struct i40e_aqc_pfc_ignore *cmd_resp =
5018                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5019         enum i40e_status_code status;
5020
5021         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5022
5023         if (request)
5024                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5025
5026         cmd_resp->tc_bitmap = tcmap;
5027
5028         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5029
5030         if (!status) {
5031                 if (tcmap_ret != NULL)
5032                         *tcmap_ret = cmd_resp->tc_bitmap;
5033         }
5034
5035         return status;
5036 }
5037
5038 /**
5039  * i40e_aq_dcb_updated - DCB Updated Command
5040  * @hw: pointer to the hw struct
5041  * @cmd_details: pointer to command details structure or NULL
5042  *
5043  * When LLDP is handled in PF this command is used by the PF
5044  * to notify EMP that a DCB setting is modified.
5045  * When LLDP is handled in EMP this command is used by the PF
5046  * to notify EMP whenever one of the following parameters get
5047  * modified:
5048  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5049  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5050  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5051  * EMP will return when the shared RPB settings have been
5052  * recomputed and modified. The retval field in the descriptor
5053  * will be set to 0 when RPB is modified.
5054  **/
5055 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5056                                 struct i40e_asq_cmd_details *cmd_details)
5057 {
5058         struct i40e_aq_desc desc;
5059         enum i40e_status_code status;
5060
5061         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5062
5063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5064
5065         return status;
5066 }
5067
5068 /**
5069  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5070  * @hw: pointer to the hw struct
5071  * @seid: defines the SEID of the switch for which the stats are requested
5072  * @vlan_id: the VLAN ID for which the statistics are requested
5073  * @stat_index: index of the statistics counters block assigned to this VLAN
5074  * @cmd_details: pointer to command details structure or NULL
5075  *
5076  * XL710 supports 128 smonVlanStats counters.This command is used to
5077  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5078  * switch.
5079  **/
5080 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5081                                 u16 vlan_id, u16 *stat_index,
5082                                 struct i40e_asq_cmd_details *cmd_details)
5083 {
5084         struct i40e_aq_desc desc;
5085         struct i40e_aqc_add_remove_statistics *cmd_resp =
5086                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5087         enum i40e_status_code status;
5088
5089         if ((seid == 0) || (stat_index == NULL))
5090                 return I40E_ERR_PARAM;
5091
5092         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5093
5094         cmd_resp->seid = CPU_TO_LE16(seid);
5095         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5096
5097         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5098
5099         if (!status && stat_index)
5100                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5101
5102         return status;
5103 }
5104
5105 /**
5106  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5107  * @hw: pointer to the hw struct
5108  * @seid: defines the SEID of the switch for which the stats are requested
5109  * @vlan_id: the VLAN ID for which the statistics are requested
5110  * @stat_index: index of the statistics counters block assigned to this VLAN
5111  * @cmd_details: pointer to command details structure or NULL
5112  *
5113  * XL710 supports 128 smonVlanStats counters.This command is used to
5114  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5115  * switch.
5116  **/
5117 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5118                                 u16 vlan_id, u16 stat_index,
5119                                 struct i40e_asq_cmd_details *cmd_details)
5120 {
5121         struct i40e_aq_desc desc;
5122         struct i40e_aqc_add_remove_statistics *cmd =
5123                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5124         enum i40e_status_code status;
5125
5126         if (seid == 0)
5127                 return I40E_ERR_PARAM;
5128
5129         i40e_fill_default_direct_cmd_desc(&desc,
5130                                           i40e_aqc_opc_remove_statistics);
5131
5132         cmd->seid = CPU_TO_LE16(seid);
5133         cmd->vlan  = CPU_TO_LE16(vlan_id);
5134         cmd->stat_index = CPU_TO_LE16(stat_index);
5135
5136         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5137
5138         return status;
5139 }
5140
5141 /**
5142  * i40e_aq_set_port_parameters - set physical port parameters.
5143  * @hw: pointer to the hw struct
5144  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5145  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5146  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5147  * @double_vlan: if set double VLAN is enabled
5148  * @cmd_details: pointer to command details structure or NULL
5149  **/
5150 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5151                                 u16 bad_frame_vsi, bool save_bad_pac,
5152                                 bool pad_short_pac, bool double_vlan,
5153                                 struct i40e_asq_cmd_details *cmd_details)
5154 {
5155         struct i40e_aqc_set_port_parameters *cmd;
5156         enum i40e_status_code status;
5157         struct i40e_aq_desc desc;
5158         u16 command_flags = 0;
5159
5160         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5161
5162         i40e_fill_default_direct_cmd_desc(&desc,
5163                                           i40e_aqc_opc_set_port_parameters);
5164
5165         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5166         if (save_bad_pac)
5167                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5168         if (pad_short_pac)
5169                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5170         if (double_vlan)
5171                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5172         cmd->command_flags = CPU_TO_LE16(command_flags);
5173
5174         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5175
5176         return status;
5177 }
5178
5179 /**
5180  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5181  * @hw: pointer to the hw struct
5182  * @seid: seid for the physical port/switching component/vsi
5183  * @buff: Indirect buffer to hold data parameters and response
5184  * @buff_size: Indirect buffer size
5185  * @opcode: Tx scheduler AQ command opcode
5186  * @cmd_details: pointer to command details structure or NULL
5187  *
5188  * Generic command handler for Tx scheduler AQ commands
5189  **/
5190 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5191                                 void *buff, u16 buff_size,
5192                                  enum i40e_admin_queue_opc opcode,
5193                                 struct i40e_asq_cmd_details *cmd_details)
5194 {
5195         struct i40e_aq_desc desc;
5196         struct i40e_aqc_tx_sched_ind *cmd =
5197                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5198         enum i40e_status_code status;
5199         bool cmd_param_flag = false;
5200
5201         switch (opcode) {
5202         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5203         case i40e_aqc_opc_configure_vsi_tc_bw:
5204         case i40e_aqc_opc_enable_switching_comp_ets:
5205         case i40e_aqc_opc_modify_switching_comp_ets:
5206         case i40e_aqc_opc_disable_switching_comp_ets:
5207         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5208         case i40e_aqc_opc_configure_switching_comp_bw_config:
5209                 cmd_param_flag = true;
5210                 break;
5211         case i40e_aqc_opc_query_vsi_bw_config:
5212         case i40e_aqc_opc_query_vsi_ets_sla_config:
5213         case i40e_aqc_opc_query_switching_comp_ets_config:
5214         case i40e_aqc_opc_query_port_ets_config:
5215         case i40e_aqc_opc_query_switching_comp_bw_config:
5216                 cmd_param_flag = false;
5217                 break;
5218         default:
5219                 return I40E_ERR_PARAM;
5220         }
5221
5222         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5223
5224         /* Indirect command */
5225         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5226         if (cmd_param_flag)
5227                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5228         if (buff_size > I40E_AQ_LARGE_BUF)
5229                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5230
5231         desc.datalen = CPU_TO_LE16(buff_size);
5232
5233         cmd->vsi_seid = CPU_TO_LE16(seid);
5234
5235         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5236
5237         return status;
5238 }
5239
5240 /**
5241  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5242  * @hw: pointer to the hw struct
5243  * @seid: VSI seid
5244  * @credit: BW limit credits (0 = disabled)
5245  * @max_credit: Max BW limit credits
5246  * @cmd_details: pointer to command details structure or NULL
5247  **/
5248 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5249                                 u16 seid, u16 credit, u8 max_credit,
5250                                 struct i40e_asq_cmd_details *cmd_details)
5251 {
5252         struct i40e_aq_desc desc;
5253         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5254                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5255         enum i40e_status_code status;
5256
5257         i40e_fill_default_direct_cmd_desc(&desc,
5258                                           i40e_aqc_opc_configure_vsi_bw_limit);
5259
5260         cmd->vsi_seid = CPU_TO_LE16(seid);
5261         cmd->credit = CPU_TO_LE16(credit);
5262         cmd->max_credit = max_credit;
5263
5264         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5265
5266         return status;
5267 }
5268
5269 /**
5270  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5271  * @hw: pointer to the hw struct
5272  * @seid: switching component seid
5273  * @credit: BW limit credits (0 = disabled)
5274  * @max_bw: Max BW limit credits
5275  * @cmd_details: pointer to command details structure or NULL
5276  **/
5277 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5278                                 u16 seid, u16 credit, u8 max_bw,
5279                                 struct i40e_asq_cmd_details *cmd_details)
5280 {
5281         struct i40e_aq_desc desc;
5282         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5283           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5284         enum i40e_status_code status;
5285
5286         i40e_fill_default_direct_cmd_desc(&desc,
5287                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5288
5289         cmd->seid = CPU_TO_LE16(seid);
5290         cmd->credit = CPU_TO_LE16(credit);
5291         cmd->max_bw = max_bw;
5292
5293         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5294
5295         return status;
5296 }
5297
5298 /**
5299  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5300  * @hw: pointer to the hw struct
5301  * @seid: VSI seid
5302  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5303  * @cmd_details: pointer to command details structure or NULL
5304  **/
5305 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5306                         u16 seid,
5307                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5308                         struct i40e_asq_cmd_details *cmd_details)
5309 {
5310         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5311                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5312                                     cmd_details);
5313 }
5314
5315 /**
5316  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5317  * @hw: pointer to the hw struct
5318  * @seid: VSI seid
5319  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5320  * @cmd_details: pointer to command details structure or NULL
5321  **/
5322 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5323                         u16 seid,
5324                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5325                         struct i40e_asq_cmd_details *cmd_details)
5326 {
5327         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5328                                     i40e_aqc_opc_configure_vsi_tc_bw,
5329                                     cmd_details);
5330 }
5331
5332 /**
5333  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5334  * @hw: pointer to the hw struct
5335  * @seid: seid of the switching component connected to Physical Port
5336  * @ets_data: Buffer holding ETS parameters
5337  * @opcode: Tx scheduler AQ command opcode
5338  * @cmd_details: pointer to command details structure or NULL
5339  **/
5340 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5341                 u16 seid,
5342                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5343                 enum i40e_admin_queue_opc opcode,
5344                 struct i40e_asq_cmd_details *cmd_details)
5345 {
5346         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5347                                     sizeof(*ets_data), opcode, cmd_details);
5348 }
5349
5350 /**
5351  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5352  * @hw: pointer to the hw struct
5353  * @seid: seid of the switching component
5354  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5355  * @cmd_details: pointer to command details structure or NULL
5356  **/
5357 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5358         u16 seid,
5359         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5360         struct i40e_asq_cmd_details *cmd_details)
5361 {
5362         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5363                             i40e_aqc_opc_configure_switching_comp_bw_config,
5364                             cmd_details);
5365 }
5366
5367 /**
5368  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5369  * @hw: pointer to the hw struct
5370  * @seid: seid of the switching component
5371  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5372  * @cmd_details: pointer to command details structure or NULL
5373  **/
5374 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5375         struct i40e_hw *hw, u16 seid,
5376         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5377         struct i40e_asq_cmd_details *cmd_details)
5378 {
5379         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5380                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5381                             cmd_details);
5382 }
5383
5384 /**
5385  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5386  * @hw: pointer to the hw struct
5387  * @seid: seid of the VSI
5388  * @bw_data: Buffer to hold VSI BW configuration
5389  * @cmd_details: pointer to command details structure or NULL
5390  **/
5391 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5392                         u16 seid,
5393                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5394                         struct i40e_asq_cmd_details *cmd_details)
5395 {
5396         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5397                                     i40e_aqc_opc_query_vsi_bw_config,
5398                                     cmd_details);
5399 }
5400
5401 /**
5402  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5403  * @hw: pointer to the hw struct
5404  * @seid: seid of the VSI
5405  * @bw_data: Buffer to hold VSI BW configuration per TC
5406  * @cmd_details: pointer to command details structure or NULL
5407  **/
5408 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5409                         u16 seid,
5410                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5411                         struct i40e_asq_cmd_details *cmd_details)
5412 {
5413         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5414                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5415                                     cmd_details);
5416 }
5417
5418 /**
5419  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5420  * @hw: pointer to the hw struct
5421  * @seid: seid of the switching component
5422  * @bw_data: Buffer to hold switching component's per TC BW config
5423  * @cmd_details: pointer to command details structure or NULL
5424  **/
5425 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5426                 u16 seid,
5427                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5428                 struct i40e_asq_cmd_details *cmd_details)
5429 {
5430         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5431                                    i40e_aqc_opc_query_switching_comp_ets_config,
5432                                    cmd_details);
5433 }
5434
5435 /**
5436  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5437  * @hw: pointer to the hw struct
5438  * @seid: seid of the VSI or switching component connected to Physical Port
5439  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5440  * @cmd_details: pointer to command details structure or NULL
5441  **/
5442 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5443                         u16 seid,
5444                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5445                         struct i40e_asq_cmd_details *cmd_details)
5446 {
5447         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5448                                     i40e_aqc_opc_query_port_ets_config,
5449                                     cmd_details);
5450 }
5451
5452 /**
5453  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5454  * @hw: pointer to the hw struct
5455  * @seid: seid of the switching component
5456  * @bw_data: Buffer to hold switching component's BW configuration
5457  * @cmd_details: pointer to command details structure or NULL
5458  **/
5459 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5460                 u16 seid,
5461                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5462                 struct i40e_asq_cmd_details *cmd_details)
5463 {
5464         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5465                                     i40e_aqc_opc_query_switching_comp_bw_config,
5466                                     cmd_details);
5467 }
5468
5469 /**
5470  * i40e_validate_filter_settings
5471  * @hw: pointer to the hardware structure
5472  * @settings: Filter control settings
5473  *
5474  * Check and validate the filter control settings passed.
5475  * The function checks for the valid filter/context sizes being
5476  * passed for FCoE and PE.
5477  *
5478  * Returns I40E_SUCCESS if the values passed are valid and within
5479  * range else returns an error.
5480  **/
5481 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5482                                 struct i40e_filter_control_settings *settings)
5483 {
5484         u32 fcoe_cntx_size, fcoe_filt_size;
5485         u32 pe_cntx_size, pe_filt_size;
5486         u32 fcoe_fmax;
5487
5488         u32 val;
5489
5490         /* Validate FCoE settings passed */
5491         switch (settings->fcoe_filt_num) {
5492         case I40E_HASH_FILTER_SIZE_1K:
5493         case I40E_HASH_FILTER_SIZE_2K:
5494         case I40E_HASH_FILTER_SIZE_4K:
5495         case I40E_HASH_FILTER_SIZE_8K:
5496         case I40E_HASH_FILTER_SIZE_16K:
5497         case I40E_HASH_FILTER_SIZE_32K:
5498                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5499                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5500                 break;
5501         default:
5502                 return I40E_ERR_PARAM;
5503         }
5504
5505         switch (settings->fcoe_cntx_num) {
5506         case I40E_DMA_CNTX_SIZE_512:
5507         case I40E_DMA_CNTX_SIZE_1K:
5508         case I40E_DMA_CNTX_SIZE_2K:
5509         case I40E_DMA_CNTX_SIZE_4K:
5510                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5511                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5512                 break;
5513         default:
5514                 return I40E_ERR_PARAM;
5515         }
5516
5517         /* Validate PE settings passed */
5518         switch (settings->pe_filt_num) {
5519         case I40E_HASH_FILTER_SIZE_1K:
5520         case I40E_HASH_FILTER_SIZE_2K:
5521         case I40E_HASH_FILTER_SIZE_4K:
5522         case I40E_HASH_FILTER_SIZE_8K:
5523         case I40E_HASH_FILTER_SIZE_16K:
5524         case I40E_HASH_FILTER_SIZE_32K:
5525         case I40E_HASH_FILTER_SIZE_64K:
5526         case I40E_HASH_FILTER_SIZE_128K:
5527         case I40E_HASH_FILTER_SIZE_256K:
5528         case I40E_HASH_FILTER_SIZE_512K:
5529         case I40E_HASH_FILTER_SIZE_1M:
5530                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5531                 pe_filt_size <<= (u32)settings->pe_filt_num;
5532                 break;
5533         default:
5534                 return I40E_ERR_PARAM;
5535         }
5536
5537         switch (settings->pe_cntx_num) {
5538         case I40E_DMA_CNTX_SIZE_512:
5539         case I40E_DMA_CNTX_SIZE_1K:
5540         case I40E_DMA_CNTX_SIZE_2K:
5541         case I40E_DMA_CNTX_SIZE_4K:
5542         case I40E_DMA_CNTX_SIZE_8K:
5543         case I40E_DMA_CNTX_SIZE_16K:
5544         case I40E_DMA_CNTX_SIZE_32K:
5545         case I40E_DMA_CNTX_SIZE_64K:
5546         case I40E_DMA_CNTX_SIZE_128K:
5547         case I40E_DMA_CNTX_SIZE_256K:
5548                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5549                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5550                 break;
5551         default:
5552                 return I40E_ERR_PARAM;
5553         }
5554
5555         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5556         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5557         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5558                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5559         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5560                 return I40E_ERR_INVALID_SIZE;
5561
5562         return I40E_SUCCESS;
5563 }
5564
5565 /**
5566  * i40e_set_filter_control
5567  * @hw: pointer to the hardware structure
5568  * @settings: Filter control settings
5569  *
5570  * Set the Queue Filters for PE/FCoE and enable filters required
5571  * for a single PF. It is expected that these settings are programmed
5572  * at the driver initialization time.
5573  **/
5574 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5575                                 struct i40e_filter_control_settings *settings)
5576 {
5577         enum i40e_status_code ret = I40E_SUCCESS;
5578         u32 hash_lut_size = 0;
5579         u32 val;
5580
5581         if (!settings)
5582                 return I40E_ERR_PARAM;
5583
5584         /* Validate the input settings */
5585         ret = i40e_validate_filter_settings(hw, settings);
5586         if (ret)
5587                 return ret;
5588
5589         /* Read the PF Queue Filter control register */
5590         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5591
5592         /* Program required PE hash buckets for the PF */
5593         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5594         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5595                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5596         /* Program required PE contexts for the PF */
5597         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5598         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5599                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5600
5601         /* Program required FCoE hash buckets for the PF */
5602         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5603         val |= ((u32)settings->fcoe_filt_num <<
5604                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5605                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5606         /* Program required FCoE DDP contexts for the PF */
5607         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5608         val |= ((u32)settings->fcoe_cntx_num <<
5609                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5610                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5611
5612         /* Program Hash LUT size for the PF */
5613         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5614         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5615                 hash_lut_size = 1;
5616         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5617                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5618
5619         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5620         if (settings->enable_fdir)
5621                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5622         if (settings->enable_ethtype)
5623                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5624         if (settings->enable_macvlan)
5625                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5626
5627         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5628
5629         return I40E_SUCCESS;
5630 }
5631
5632 /**
5633  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5634  * @hw: pointer to the hw struct
5635  * @mac_addr: MAC address to use in the filter
5636  * @ethtype: Ethertype to use in the filter
5637  * @flags: Flags that needs to be applied to the filter
5638  * @vsi_seid: seid of the control VSI
5639  * @queue: VSI queue number to send the packet to
5640  * @is_add: Add control packet filter if True else remove
5641  * @stats: Structure to hold information on control filter counts
5642  * @cmd_details: pointer to command details structure or NULL
5643  *
5644  * This command will Add or Remove control packet filter for a control VSI.
5645  * In return it will update the total number of perfect filter count in
5646  * the stats member.
5647  **/
5648 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5649                                 u8 *mac_addr, u16 ethtype, u16 flags,
5650                                 u16 vsi_seid, u16 queue, bool is_add,
5651                                 struct i40e_control_filter_stats *stats,
5652                                 struct i40e_asq_cmd_details *cmd_details)
5653 {
5654         struct i40e_aq_desc desc;
5655         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5656                 (struct i40e_aqc_add_remove_control_packet_filter *)
5657                 &desc.params.raw;
5658         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5659                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5660                 &desc.params.raw;
5661         enum i40e_status_code status;
5662
5663         if (vsi_seid == 0)
5664                 return I40E_ERR_PARAM;
5665
5666         if (is_add) {
5667                 i40e_fill_default_direct_cmd_desc(&desc,
5668                                 i40e_aqc_opc_add_control_packet_filter);
5669                 cmd->queue = CPU_TO_LE16(queue);
5670         } else {
5671                 i40e_fill_default_direct_cmd_desc(&desc,
5672                                 i40e_aqc_opc_remove_control_packet_filter);
5673         }
5674
5675         if (mac_addr)
5676                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5677                             I40E_NONDMA_TO_NONDMA);
5678
5679         cmd->etype = CPU_TO_LE16(ethtype);
5680         cmd->flags = CPU_TO_LE16(flags);
5681         cmd->seid = CPU_TO_LE16(vsi_seid);
5682
5683         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5684
5685         if (!status && stats) {
5686                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5687                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5688                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5689                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5690         }
5691
5692         return status;
5693 }
5694
5695 /**
5696  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5697  * @hw: pointer to the hw struct
5698  * @seid: VSI seid to add ethertype filter from
5699  **/
5700 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5701                                                     u16 seid)
5702 {
5703 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5704         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5705                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5706                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5707         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5708         enum i40e_status_code status;
5709
5710         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5711                                                        seid, 0, true, NULL,
5712                                                        NULL);
5713         if (status)
5714                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5715 }
5716
5717 /**
5718  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5719  * @filters: list of cloud filters
5720  * @filter_count: length of list
5721  *
5722  * There's an issue in the device where the Geneve VNI layout needs
5723  * to be shifted 1 byte over from the VxLAN VNI
5724  **/
5725 STATIC void i40e_fix_up_geneve_vni(
5726         struct i40e_aqc_cloud_filters_element_data *filters,
5727         u8 filter_count)
5728 {
5729         struct i40e_aqc_cloud_filters_element_data *f = filters;
5730         int i;
5731
5732         for (i = 0; i < filter_count; i++) {
5733                 u16 tnl_type;
5734                 u32 ti;
5735
5736                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5737                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5738                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5739                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5740                         ti = LE32_TO_CPU(f[i].tenant_id);
5741                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5742                 }
5743         }
5744 }
5745
5746 /**
5747  * i40e_aq_add_cloud_filters
5748  * @hw: pointer to the hardware structure
5749  * @seid: VSI seid to add cloud filters from
5750  * @filters: Buffer which contains the filters to be added
5751  * @filter_count: number of filters contained in the buffer
5752  *
5753  * Set the cloud filters for a given VSI.  The contents of the
5754  * i40e_aqc_cloud_filters_element_data are filled
5755  * in by the caller of the function.
5756  *
5757  **/
5758 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5759         u16 seid,
5760         struct i40e_aqc_cloud_filters_element_data *filters,
5761         u8 filter_count)
5762 {
5763         struct i40e_aq_desc desc;
5764         struct i40e_aqc_add_remove_cloud_filters *cmd =
5765         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5766         enum i40e_status_code status;
5767         u16 buff_len;
5768
5769         i40e_fill_default_direct_cmd_desc(&desc,
5770                                           i40e_aqc_opc_add_cloud_filters);
5771
5772         buff_len = filter_count * sizeof(*filters);
5773         desc.datalen = CPU_TO_LE16(buff_len);
5774         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5775         cmd->num_filters = filter_count;
5776         cmd->seid = CPU_TO_LE16(seid);
5777
5778         i40e_fix_up_geneve_vni(filters, filter_count);
5779
5780         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5781
5782         return status;
5783 }
5784
5785 /**
5786  * i40e_aq_add_cloud_filters_bb
5787  * @hw: pointer to the hardware structure
5788  * @seid: VSI seid to add cloud filters from
5789  * @filters: Buffer which contains the filters in big buffer to be added
5790  * @filter_count: number of filters contained in the buffer
5791  *
5792  * Set the cloud filters for a given VSI.  The contents of the
5793  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5794  * the function.
5795  *
5796  **/
5797 enum i40e_status_code
5798 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5799                              struct i40e_aqc_cloud_filters_element_bb *filters,
5800                              u8 filter_count)
5801 {
5802         struct i40e_aq_desc desc;
5803         struct i40e_aqc_add_remove_cloud_filters *cmd =
5804         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5805         enum i40e_status_code status;
5806         u16 buff_len;
5807         int i;
5808
5809         i40e_fill_default_direct_cmd_desc(&desc,
5810                                           i40e_aqc_opc_add_cloud_filters);
5811
5812         buff_len = filter_count * sizeof(*filters);
5813         desc.datalen = CPU_TO_LE16(buff_len);
5814         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5815         cmd->num_filters = filter_count;
5816         cmd->seid = CPU_TO_LE16(seid);
5817         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5818
5819         for (i = 0; i < filter_count; i++) {
5820                 u16 tnl_type;
5821                 u32 ti;
5822
5823                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5824                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5825                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5826
5827                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5828                  * one more byte further than normally used for Tenant ID in
5829                  * other tunnel types.
5830                  */
5831                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5832                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5833                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5834                 }
5835         }
5836
5837         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5838
5839         return status;
5840 }
5841
5842 /**
5843  * i40e_aq_rem_cloud_filters
5844  * @hw: pointer to the hardware structure
5845  * @seid: VSI seid to remove cloud filters from
5846  * @filters: Buffer which contains the filters to be removed
5847  * @filter_count: number of filters contained in the buffer
5848  *
5849  * Remove the cloud filters for a given VSI.  The contents of the
5850  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5851  * of the function.
5852  *
5853  **/
5854 enum i40e_status_code
5855 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5856                           struct i40e_aqc_cloud_filters_element_data *filters,
5857                           u8 filter_count)
5858 {
5859         struct i40e_aq_desc desc;
5860         struct i40e_aqc_add_remove_cloud_filters *cmd =
5861         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5862         enum i40e_status_code status;
5863         u16 buff_len;
5864
5865         i40e_fill_default_direct_cmd_desc(&desc,
5866                                           i40e_aqc_opc_remove_cloud_filters);
5867
5868         buff_len = filter_count * sizeof(*filters);
5869         desc.datalen = CPU_TO_LE16(buff_len);
5870         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5871         cmd->num_filters = filter_count;
5872         cmd->seid = CPU_TO_LE16(seid);
5873
5874         i40e_fix_up_geneve_vni(filters, filter_count);
5875
5876         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5877
5878         return status;
5879 }
5880
5881 /**
5882  * i40e_aq_rem_cloud_filters_bb
5883  * @hw: pointer to the hardware structure
5884  * @seid: VSI seid to remove cloud filters from
5885  * @filters: Buffer which contains the filters in big buffer to be removed
5886  * @filter_count: number of filters contained in the buffer
5887  *
5888  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5889  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5890  * function.
5891  *
5892  **/
5893 enum i40e_status_code
5894 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5895                              struct i40e_aqc_cloud_filters_element_bb *filters,
5896                              u8 filter_count)
5897 {
5898         struct i40e_aq_desc desc;
5899         struct i40e_aqc_add_remove_cloud_filters *cmd =
5900         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5901         enum i40e_status_code status;
5902         u16 buff_len;
5903         int i;
5904
5905         i40e_fill_default_direct_cmd_desc(&desc,
5906                                           i40e_aqc_opc_remove_cloud_filters);
5907
5908         buff_len = filter_count * sizeof(*filters);
5909         desc.datalen = CPU_TO_LE16(buff_len);
5910         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5911         cmd->num_filters = filter_count;
5912         cmd->seid = CPU_TO_LE16(seid);
5913         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5914
5915         for (i = 0; i < filter_count; i++) {
5916                 u16 tnl_type;
5917                 u32 ti;
5918
5919                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5920                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5921                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5922
5923                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5924                  * one more byte further than normally used for Tenant ID in
5925                  * other tunnel types.
5926                  */
5927                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5928                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5929                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5930                 }
5931         }
5932
5933         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5934
5935         return status;
5936 }
5937
5938 /**
5939  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5940  * @hw: pointer to the hw struct
5941  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5942  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5943  *
5944  **/
5945 enum
5946 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5947         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5948         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5949 {
5950         struct i40e_aq_desc desc;
5951         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5952                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5953         enum i40e_status_code status = I40E_SUCCESS;
5954         int i = 0;
5955
5956         /* X722 doesn't support this command */
5957         if (hw->mac.type == I40E_MAC_X722)
5958                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5959
5960         /* need FW version greater than 6.00 */
5961         if (hw->aq.fw_maj_ver < 6)
5962                 return I40E_NOT_SUPPORTED;
5963
5964         i40e_fill_default_direct_cmd_desc(&desc,
5965                                           i40e_aqc_opc_replace_cloud_filters);
5966
5967         desc.datalen = CPU_TO_LE16(32);
5968         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5969         cmd->old_filter_type = filters->old_filter_type;
5970         cmd->new_filter_type = filters->new_filter_type;
5971         cmd->valid_flags = filters->valid_flags;
5972         cmd->tr_bit = filters->tr_bit;
5973         cmd->tr_bit2 = filters->tr_bit2;
5974
5975         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5976                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5977
5978         /* for get cloud filters command */
5979         for (i = 0; i < 32; i += 4) {
5980                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5981                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5982                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5983                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5984         }
5985
5986         return status;
5987 }
5988
5989
5990 /**
5991  * i40e_aq_alternate_write
5992  * @hw: pointer to the hardware structure
5993  * @reg_addr0: address of first dword to be read
5994  * @reg_val0: value to be written under 'reg_addr0'
5995  * @reg_addr1: address of second dword to be read
5996  * @reg_val1: value to be written under 'reg_addr1'
5997  *
5998  * Write one or two dwords to alternate structure. Fields are indicated
5999  * by 'reg_addr0' and 'reg_addr1' register numbers.
6000  *
6001  **/
6002 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6003                                 u32 reg_addr0, u32 reg_val0,
6004                                 u32 reg_addr1, u32 reg_val1)
6005 {
6006         struct i40e_aq_desc desc;
6007         struct i40e_aqc_alternate_write *cmd_resp =
6008                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6009         enum i40e_status_code status;
6010
6011         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6012         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6013         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6014         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6015         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6016
6017         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6018
6019         return status;
6020 }
6021
6022 /**
6023  * i40e_aq_alternate_write_indirect
6024  * @hw: pointer to the hardware structure
6025  * @addr: address of a first register to be modified
6026  * @dw_count: number of alternate structure fields to write
6027  * @buffer: pointer to the command buffer
6028  *
6029  * Write 'dw_count' dwords from 'buffer' to alternate structure
6030  * starting at 'addr'.
6031  *
6032  **/
6033 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6034                                 u32 addr, u32 dw_count, void *buffer)
6035 {
6036         struct i40e_aq_desc desc;
6037         struct i40e_aqc_alternate_ind_write *cmd_resp =
6038                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6039         enum i40e_status_code status;
6040
6041         if (buffer == NULL)
6042                 return I40E_ERR_PARAM;
6043
6044         /* Indirect command */
6045         i40e_fill_default_direct_cmd_desc(&desc,
6046                                          i40e_aqc_opc_alternate_write_indirect);
6047
6048         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6049         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6050         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6051                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6052
6053         cmd_resp->address = CPU_TO_LE32(addr);
6054         cmd_resp->length = CPU_TO_LE32(dw_count);
6055
6056         status = i40e_asq_send_command(hw, &desc, buffer,
6057                                        I40E_LO_DWORD(4*dw_count), NULL);
6058
6059         return status;
6060 }
6061
6062 /**
6063  * i40e_aq_alternate_read
6064  * @hw: pointer to the hardware structure
6065  * @reg_addr0: address of first dword to be read
6066  * @reg_val0: pointer for data read from 'reg_addr0'
6067  * @reg_addr1: address of second dword to be read
6068  * @reg_val1: pointer for data read from 'reg_addr1'
6069  *
6070  * Read one or two dwords from alternate structure. Fields are indicated
6071  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6072  * is not passed then only register at 'reg_addr0' is read.
6073  *
6074  **/
6075 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6076                                 u32 reg_addr0, u32 *reg_val0,
6077                                 u32 reg_addr1, u32 *reg_val1)
6078 {
6079         struct i40e_aq_desc desc;
6080         struct i40e_aqc_alternate_write *cmd_resp =
6081                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6082         enum i40e_status_code status;
6083
6084         if (reg_val0 == NULL)
6085                 return I40E_ERR_PARAM;
6086
6087         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6088         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6089         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6090
6091         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6092
6093         if (status == I40E_SUCCESS) {
6094                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6095
6096                 if (reg_val1 != NULL)
6097                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6098         }
6099
6100         return status;
6101 }
6102
6103 /**
6104  * i40e_aq_alternate_read_indirect
6105  * @hw: pointer to the hardware structure
6106  * @addr: address of the alternate structure field
6107  * @dw_count: number of alternate structure fields to read
6108  * @buffer: pointer to the command buffer
6109  *
6110  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6111  * place them in 'buffer'. The buffer should be allocated by caller.
6112  *
6113  **/
6114 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6115                                 u32 addr, u32 dw_count, void *buffer)
6116 {
6117         struct i40e_aq_desc desc;
6118         struct i40e_aqc_alternate_ind_write *cmd_resp =
6119                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6120         enum i40e_status_code status;
6121
6122         if (buffer == NULL)
6123                 return I40E_ERR_PARAM;
6124
6125         /* Indirect command */
6126         i40e_fill_default_direct_cmd_desc(&desc,
6127                 i40e_aqc_opc_alternate_read_indirect);
6128
6129         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6130         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6131         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6132                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6133
6134         cmd_resp->address = CPU_TO_LE32(addr);
6135         cmd_resp->length = CPU_TO_LE32(dw_count);
6136
6137         status = i40e_asq_send_command(hw, &desc, buffer,
6138                                        I40E_LO_DWORD(4*dw_count), NULL);
6139
6140         return status;
6141 }
6142
6143 /**
6144  *  i40e_aq_alternate_clear
6145  *  @hw: pointer to the HW structure.
6146  *
6147  *  Clear the alternate structures of the port from which the function
6148  *  is called.
6149  *
6150  **/
6151 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6152 {
6153         struct i40e_aq_desc desc;
6154         enum i40e_status_code status;
6155
6156         i40e_fill_default_direct_cmd_desc(&desc,
6157                                           i40e_aqc_opc_alternate_clear_port);
6158
6159         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6160
6161         return status;
6162 }
6163
6164 /**
6165  *  i40e_aq_alternate_write_done
6166  *  @hw: pointer to the HW structure.
6167  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6168  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6169  *
6170  *  Indicates to the FW that alternate structures have been changed.
6171  *
6172  **/
6173 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6174                 u8 bios_mode, bool *reset_needed)
6175 {
6176         struct i40e_aq_desc desc;
6177         struct i40e_aqc_alternate_write_done *cmd =
6178                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6179         enum i40e_status_code status;
6180
6181         if (reset_needed == NULL)
6182                 return I40E_ERR_PARAM;
6183
6184         i40e_fill_default_direct_cmd_desc(&desc,
6185                                           i40e_aqc_opc_alternate_write_done);
6186
6187         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6188
6189         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6190         if (!status && reset_needed)
6191                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6192                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6193
6194         return status;
6195 }
6196
6197 /**
6198  *  i40e_aq_set_oem_mode
6199  *  @hw: pointer to the HW structure.
6200  *  @oem_mode: the OEM mode to be used
6201  *
6202  *  Sets the device to a specific operating mode. Currently the only supported
6203  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6204  *
6205  **/
6206 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6207                 u8 oem_mode)
6208 {
6209         struct i40e_aq_desc desc;
6210         struct i40e_aqc_alternate_write_done *cmd =
6211                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6212         enum i40e_status_code status;
6213
6214         i40e_fill_default_direct_cmd_desc(&desc,
6215                                           i40e_aqc_opc_alternate_set_mode);
6216
6217         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6218
6219         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6220
6221         return status;
6222 }
6223
6224 /**
6225  * i40e_aq_resume_port_tx
6226  * @hw: pointer to the hardware structure
6227  * @cmd_details: pointer to command details structure or NULL
6228  *
6229  * Resume port's Tx traffic
6230  **/
6231 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6232                                 struct i40e_asq_cmd_details *cmd_details)
6233 {
6234         struct i40e_aq_desc desc;
6235         enum i40e_status_code status;
6236
6237         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6238
6239         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6240
6241         return status;
6242 }
6243
6244 /**
6245  * i40e_set_pci_config_data - store PCI bus info
6246  * @hw: pointer to hardware structure
6247  * @link_status: the link status word from PCI config space
6248  *
6249  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6250  **/
6251 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6252 {
6253         hw->bus.type = i40e_bus_type_pci_express;
6254
6255         switch (link_status & I40E_PCI_LINK_WIDTH) {
6256         case I40E_PCI_LINK_WIDTH_1:
6257                 hw->bus.width = i40e_bus_width_pcie_x1;
6258                 break;
6259         case I40E_PCI_LINK_WIDTH_2:
6260                 hw->bus.width = i40e_bus_width_pcie_x2;
6261                 break;
6262         case I40E_PCI_LINK_WIDTH_4:
6263                 hw->bus.width = i40e_bus_width_pcie_x4;
6264                 break;
6265         case I40E_PCI_LINK_WIDTH_8:
6266                 hw->bus.width = i40e_bus_width_pcie_x8;
6267                 break;
6268         default:
6269                 hw->bus.width = i40e_bus_width_unknown;
6270                 break;
6271         }
6272
6273         switch (link_status & I40E_PCI_LINK_SPEED) {
6274         case I40E_PCI_LINK_SPEED_2500:
6275                 hw->bus.speed = i40e_bus_speed_2500;
6276                 break;
6277         case I40E_PCI_LINK_SPEED_5000:
6278                 hw->bus.speed = i40e_bus_speed_5000;
6279                 break;
6280         case I40E_PCI_LINK_SPEED_8000:
6281                 hw->bus.speed = i40e_bus_speed_8000;
6282                 break;
6283         default:
6284                 hw->bus.speed = i40e_bus_speed_unknown;
6285                 break;
6286         }
6287 }
6288
6289 /**
6290  * i40e_aq_debug_dump
6291  * @hw: pointer to the hardware structure
6292  * @cluster_id: specific cluster to dump
6293  * @table_id: table id within cluster
6294  * @start_index: index of line in the block to read
6295  * @buff_size: dump buffer size
6296  * @buff: dump buffer
6297  * @ret_buff_size: actual buffer size returned
6298  * @ret_next_table: next block to read
6299  * @ret_next_index: next index to read
6300  * @cmd_details: pointer to command details structure or NULL
6301  *
6302  * Dump internal FW/HW data for debug purposes.
6303  *
6304  **/
6305 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6306                                 u8 table_id, u32 start_index, u16 buff_size,
6307                                 void *buff, u16 *ret_buff_size,
6308                                 u8 *ret_next_table, u32 *ret_next_index,
6309                                 struct i40e_asq_cmd_details *cmd_details)
6310 {
6311         struct i40e_aq_desc desc;
6312         struct i40e_aqc_debug_dump_internals *cmd =
6313                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6314         struct i40e_aqc_debug_dump_internals *resp =
6315                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6316         enum i40e_status_code status;
6317
6318         if (buff_size == 0 || !buff)
6319                 return I40E_ERR_PARAM;
6320
6321         i40e_fill_default_direct_cmd_desc(&desc,
6322                                           i40e_aqc_opc_debug_dump_internals);
6323         /* Indirect Command */
6324         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6325         if (buff_size > I40E_AQ_LARGE_BUF)
6326                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6327
6328         cmd->cluster_id = cluster_id;
6329         cmd->table_id = table_id;
6330         cmd->idx = CPU_TO_LE32(start_index);
6331
6332         desc.datalen = CPU_TO_LE16(buff_size);
6333
6334         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6335         if (!status) {
6336                 if (ret_buff_size != NULL)
6337                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6338                 if (ret_next_table != NULL)
6339                         *ret_next_table = resp->table_id;
6340                 if (ret_next_index != NULL)
6341                         *ret_next_index = LE32_TO_CPU(resp->idx);
6342         }
6343
6344         return status;
6345 }
6346
6347
6348 /**
6349  * i40e_enable_eee
6350  * @hw: pointer to the hardware structure
6351  * @enable: state of Energy Efficient Ethernet mode to be set
6352  *
6353  * Enables or disables Energy Efficient Ethernet (EEE) mode
6354  * accordingly to @enable parameter.
6355  **/
6356 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6357 {
6358         struct i40e_aq_get_phy_abilities_resp abilities;
6359         struct i40e_aq_set_phy_config config;
6360         enum i40e_status_code status;
6361         __le16 eee_capability;
6362
6363         /* Get initial PHY capabilities */
6364         status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6365                                               NULL);
6366         if (status)
6367                 goto err;
6368
6369         /* Check whether NIC configuration is compatible with Energy Efficient
6370          * Ethernet (EEE) mode.
6371          */
6372         if (abilities.eee_capability == 0) {
6373                 status = I40E_ERR_CONFIG;
6374                 goto err;
6375         }
6376
6377         /* Cache initial EEE capability */
6378         eee_capability = abilities.eee_capability;
6379
6380         /* Get current configuration */
6381         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6382                                               NULL);
6383         if (status)
6384                 goto err;
6385
6386         /* Cache current configuration */
6387         config.phy_type = abilities.phy_type;
6388         config.link_speed = abilities.link_speed;
6389         config.abilities = abilities.abilities |
6390                            I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6391         config.eeer = abilities.eeer_val;
6392         config.low_power_ctrl = abilities.d3_lpan;
6393         config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6394                             I40E_AQ_PHY_FEC_CONFIG_MASK;
6395
6396         /* Set desired EEE state */
6397         if (enable) {
6398                 config.eee_capability = eee_capability;
6399                 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6400         } else {
6401                 config.eee_capability = 0;
6402                 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6403         }
6404
6405         /* Save modified config */
6406         status = i40e_aq_set_phy_config(hw, &config, NULL);
6407 err:
6408         return status;
6409 }
6410
6411 /**
6412  * i40e_read_bw_from_alt_ram
6413  * @hw: pointer to the hardware structure
6414  * @max_bw: pointer for max_bw read
6415  * @min_bw: pointer for min_bw read
6416  * @min_valid: pointer for bool that is true if min_bw is a valid value
6417  * @max_valid: pointer for bool that is true if max_bw is a valid value
6418  *
6419  * Read bw from the alternate ram for the given pf
6420  **/
6421 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6422                                         u32 *max_bw, u32 *min_bw,
6423                                         bool *min_valid, bool *max_valid)
6424 {
6425         enum i40e_status_code status;
6426         u32 max_bw_addr, min_bw_addr;
6427
6428         /* Calculate the address of the min/max bw registers */
6429         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6430                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6431                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6432         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6433                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6434                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6435
6436         /* Read the bandwidths from alt ram */
6437         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6438                                         min_bw_addr, min_bw);
6439
6440         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6441                 *min_valid = true;
6442         else
6443                 *min_valid = false;
6444
6445         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6446                 *max_valid = true;
6447         else
6448                 *max_valid = false;
6449
6450         return status;
6451 }
6452
6453 /**
6454  * i40e_aq_configure_partition_bw
6455  * @hw: pointer to the hardware structure
6456  * @bw_data: Buffer holding valid pfs and bw limits
6457  * @cmd_details: pointer to command details
6458  *
6459  * Configure partitions guaranteed/max bw
6460  **/
6461 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6462                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6463                         struct i40e_asq_cmd_details *cmd_details)
6464 {
6465         enum i40e_status_code status;
6466         struct i40e_aq_desc desc;
6467         u16 bwd_size = sizeof(*bw_data);
6468
6469         i40e_fill_default_direct_cmd_desc(&desc,
6470                                 i40e_aqc_opc_configure_partition_bw);
6471
6472         /* Indirect command */
6473         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6474         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6475
6476         desc.datalen = CPU_TO_LE16(bwd_size);
6477
6478         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6479
6480         return status;
6481 }
6482
6483 /**
6484  * i40e_read_phy_register_clause22
6485  * @hw: pointer to the HW structure
6486  * @reg: register address in the page
6487  * @phy_addr: PHY address on MDIO interface
6488  * @value: PHY register value
6489  *
6490  * Reads specified PHY register value
6491  **/
6492 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6493                                         u16 reg, u8 phy_addr, u16 *value)
6494 {
6495         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6496         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6497         u32 command = 0;
6498         u16 retry = 1000;
6499
6500         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6501                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6502                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6503                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6504                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6505         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6506         do {
6507                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6508                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6509                         status = I40E_SUCCESS;
6510                         break;
6511                 }
6512                 i40e_usec_delay(10);
6513                 retry--;
6514         } while (retry);
6515
6516         if (status) {
6517                 i40e_debug(hw, I40E_DEBUG_PHY,
6518                            "PHY: Can't write command to external PHY.\n");
6519         } else {
6520                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6521                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6522                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6523         }
6524
6525         return status;
6526 }
6527
6528 /**
6529  * i40e_write_phy_register_clause22
6530  * @hw: pointer to the HW structure
6531  * @reg: register address in the page
6532  * @phy_addr: PHY address on MDIO interface
6533  * @value: PHY register value
6534  *
6535  * Writes specified PHY register value
6536  **/
6537 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6538                                         u16 reg, u8 phy_addr, u16 value)
6539 {
6540         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6541         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6542         u32 command  = 0;
6543         u16 retry = 1000;
6544
6545         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6546         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6547
6548         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6549                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6550                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6551                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6552                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6553
6554         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6555         do {
6556                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6557                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6558                         status = I40E_SUCCESS;
6559                         break;
6560                 }
6561                 i40e_usec_delay(10);
6562                 retry--;
6563         } while (retry);
6564
6565         return status;
6566 }
6567
6568 /**
6569  * i40e_read_phy_register_clause45
6570  * @hw: pointer to the HW structure
6571  * @page: registers page number
6572  * @reg: register address in the page
6573  * @phy_addr: PHY address on MDIO interface
6574  * @value: PHY register value
6575  *
6576  * Reads specified PHY register value
6577  **/
6578 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6579                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6580 {
6581         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6582         u32 command  = 0;
6583         u16 retry = 1000;
6584         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6585
6586         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6587                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6588                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6589                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6590                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6591                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6592                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6593         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6594         do {
6595                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6596                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6597                         status = I40E_SUCCESS;
6598                         break;
6599                 }
6600                 i40e_usec_delay(10);
6601                 retry--;
6602         } while (retry);
6603
6604         if (status) {
6605                 i40e_debug(hw, I40E_DEBUG_PHY,
6606                            "PHY: Can't write command to external PHY.\n");
6607                 goto phy_read_end;
6608         }
6609
6610         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6611                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6612                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6613                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6614                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6615                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6616         status = I40E_ERR_TIMEOUT;
6617         retry = 1000;
6618         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6619         do {
6620                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6621                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6622                         status = I40E_SUCCESS;
6623                         break;
6624                 }
6625                 i40e_usec_delay(10);
6626                 retry--;
6627         } while (retry);
6628
6629         if (!status) {
6630                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6631                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6632                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6633         } else {
6634                 i40e_debug(hw, I40E_DEBUG_PHY,
6635                            "PHY: Can't read register value from external PHY.\n");
6636         }
6637
6638 phy_read_end:
6639         return status;
6640 }
6641
6642 /**
6643  * i40e_write_phy_register_clause45
6644  * @hw: pointer to the HW structure
6645  * @page: registers page number
6646  * @reg: register address in the page
6647  * @phy_addr: PHY address on MDIO interface
6648  * @value: PHY register value
6649  *
6650  * Writes value to specified PHY register
6651  **/
6652 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6653                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6654 {
6655         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6656         u32 command  = 0;
6657         u16 retry = 1000;
6658         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6659
6660         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6661                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6662                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6663                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6664                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6665                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6666                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6667         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6668         do {
6669                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6670                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6671                         status = I40E_SUCCESS;
6672                         break;
6673                 }
6674                 i40e_usec_delay(10);
6675                 retry--;
6676         } while (retry);
6677         if (status) {
6678                 i40e_debug(hw, I40E_DEBUG_PHY,
6679                            "PHY: Can't write command to external PHY.\n");
6680                 goto phy_write_end;
6681         }
6682
6683         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6684         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6685
6686         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6687                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6688                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6689                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6690                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6691                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6692         status = I40E_ERR_TIMEOUT;
6693         retry = 1000;
6694         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6695         do {
6696                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6697                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6698                         status = I40E_SUCCESS;
6699                         break;
6700                 }
6701                 i40e_usec_delay(10);
6702                 retry--;
6703         } while (retry);
6704
6705 phy_write_end:
6706         return status;
6707 }
6708
6709 /**
6710  * i40e_write_phy_register
6711  * @hw: pointer to the HW structure
6712  * @page: registers page number
6713  * @reg: register address in the page
6714  * @phy_addr: PHY address on MDIO interface
6715  * @value: PHY register value
6716  *
6717  * Writes value to specified PHY register
6718  **/
6719 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6720                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6721 {
6722         enum i40e_status_code status;
6723
6724         switch (hw->device_id) {
6725         case I40E_DEV_ID_1G_BASE_T_X722:
6726                 status = i40e_write_phy_register_clause22(hw,
6727                         reg, phy_addr, value);
6728                 break;
6729         case I40E_DEV_ID_10G_BASE_T:
6730         case I40E_DEV_ID_10G_BASE_T4:
6731         case I40E_DEV_ID_10G_BASE_T_BC:
6732         case I40E_DEV_ID_5G_BASE_T_BC:
6733         case I40E_DEV_ID_10G_BASE_T_X722:
6734         case I40E_DEV_ID_25G_B:
6735         case I40E_DEV_ID_25G_SFP28:
6736                 status = i40e_write_phy_register_clause45(hw,
6737                         page, reg, phy_addr, value);
6738                 break;
6739         default:
6740                 status = I40E_ERR_UNKNOWN_PHY;
6741                 break;
6742         }
6743
6744         return status;
6745 }
6746
6747 /**
6748  * i40e_read_phy_register
6749  * @hw: pointer to the HW structure
6750  * @page: registers page number
6751  * @reg: register address in the page
6752  * @phy_addr: PHY address on MDIO interface
6753  * @value: PHY register value
6754  *
6755  * Reads specified PHY register value
6756  **/
6757 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6758                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6759 {
6760         enum i40e_status_code status;
6761
6762         switch (hw->device_id) {
6763         case I40E_DEV_ID_1G_BASE_T_X722:
6764                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6765                                                          value);
6766                 break;
6767         case I40E_DEV_ID_10G_BASE_T:
6768         case I40E_DEV_ID_10G_BASE_T4:
6769         case I40E_DEV_ID_5G_BASE_T_BC:
6770         case I40E_DEV_ID_10G_BASE_T_X722:
6771         case I40E_DEV_ID_25G_B:
6772         case I40E_DEV_ID_25G_SFP28:
6773                 status = i40e_read_phy_register_clause45(hw, page, reg,
6774                                                          phy_addr, value);
6775                 break;
6776         default:
6777                 status = I40E_ERR_UNKNOWN_PHY;
6778                 break;
6779         }
6780
6781         return status;
6782 }
6783
6784 /**
6785  * i40e_get_phy_address
6786  * @hw: pointer to the HW structure
6787  * @dev_num: PHY port num that address we want
6788  *
6789  * Gets PHY address for current port
6790  **/
6791 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6792 {
6793         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6794         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6795
6796         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6797 }
6798
6799 /**
6800  * i40e_blink_phy_led
6801  * @hw: pointer to the HW structure
6802  * @time: time how long led will blinks in secs
6803  * @interval: gap between LED on and off in msecs
6804  *
6805  * Blinks PHY link LED
6806  **/
6807 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6808                                               u32 time, u32 interval)
6809 {
6810         enum i40e_status_code status = I40E_SUCCESS;
6811         u32 i;
6812         u16 led_ctl = 0;
6813         u16 gpio_led_port;
6814         u16 led_reg;
6815         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6816         u8 phy_addr = 0;
6817         u8 port_num;
6818
6819         i = rd32(hw, I40E_PFGEN_PORTNUM);
6820         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6821         phy_addr = i40e_get_phy_address(hw, port_num);
6822
6823         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6824              led_addr++) {
6825                 status = i40e_read_phy_register_clause45(hw,
6826                                                          I40E_PHY_COM_REG_PAGE,
6827                                                          led_addr, phy_addr,
6828                                                          &led_reg);
6829                 if (status)
6830                         goto phy_blinking_end;
6831                 led_ctl = led_reg;
6832                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6833                         led_reg = 0;
6834                         status = i40e_write_phy_register_clause45(hw,
6835                                                          I40E_PHY_COM_REG_PAGE,
6836                                                          led_addr, phy_addr,
6837                                                          led_reg);
6838                         if (status)
6839                                 goto phy_blinking_end;
6840                         break;
6841                 }
6842         }
6843
6844         if (time > 0 && interval > 0) {
6845                 for (i = 0; i < time * 1000; i += interval) {
6846                         status = i40e_read_phy_register_clause45(hw,
6847                                                 I40E_PHY_COM_REG_PAGE,
6848                                                 led_addr, phy_addr, &led_reg);
6849                         if (status)
6850                                 goto restore_config;
6851                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6852                                 led_reg = 0;
6853                         else
6854                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6855                         status = i40e_write_phy_register_clause45(hw,
6856                                                 I40E_PHY_COM_REG_PAGE,
6857                                                 led_addr, phy_addr, led_reg);
6858                         if (status)
6859                                 goto restore_config;
6860                         i40e_msec_delay(interval);
6861                 }
6862         }
6863
6864 restore_config:
6865         status = i40e_write_phy_register_clause45(hw,
6866                                                   I40E_PHY_COM_REG_PAGE,
6867                                                   led_addr, phy_addr, led_ctl);
6868
6869 phy_blinking_end:
6870         return status;
6871 }
6872
6873 /**
6874  * i40e_led_get_reg - read LED register
6875  * @hw: pointer to the HW structure
6876  * @led_addr: LED register address
6877  * @reg_val: read register value
6878  **/
6879 enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6880                                        u32 *reg_val)
6881 {
6882         enum i40e_status_code status;
6883         u8 phy_addr = 0;
6884
6885         *reg_val = 0;
6886         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6887                 status = i40e_aq_get_phy_register(hw,
6888                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6889                                                 I40E_PHY_COM_REG_PAGE, true,
6890                                                 I40E_PHY_LED_PROV_REG_1,
6891                                                 reg_val, NULL);
6892         } else {
6893                 phy_addr = i40e_get_phy_address(hw, hw->port);
6894                 status = i40e_read_phy_register_clause45(hw,
6895                                                          I40E_PHY_COM_REG_PAGE,
6896                                                          led_addr, phy_addr,
6897                                                          (u16 *)reg_val);
6898         }
6899         return status;
6900 }
6901
6902 /**
6903  * i40e_led_set_reg - write LED register
6904  * @hw: pointer to the HW structure
6905  * @led_addr: LED register address
6906  * @reg_val: register value to write
6907  **/
6908 enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6909                                        u32 reg_val)
6910 {
6911         enum i40e_status_code status;
6912         u8 phy_addr = 0;
6913
6914         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6915                 status = i40e_aq_set_phy_register(hw,
6916                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6917                                                 I40E_PHY_COM_REG_PAGE, true,
6918                                                 I40E_PHY_LED_PROV_REG_1,
6919                                                 reg_val, NULL);
6920         } else {
6921                 phy_addr = i40e_get_phy_address(hw, hw->port);
6922                 status = i40e_write_phy_register_clause45(hw,
6923                                                           I40E_PHY_COM_REG_PAGE,
6924                                                           led_addr, phy_addr,
6925                                                           (u16)reg_val);
6926         }
6927
6928         return status;
6929 }
6930
6931 /**
6932  * i40e_led_get_phy - return current on/off mode
6933  * @hw: pointer to the hw struct
6934  * @led_addr: address of led register to use
6935  * @val: original value of register to use
6936  *
6937  **/
6938 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6939                                        u16 *val)
6940 {
6941         enum i40e_status_code status = I40E_SUCCESS;
6942         u16 gpio_led_port;
6943         u32 reg_val_aq;
6944         u16 temp_addr;
6945         u8 phy_addr = 0;
6946         u16 reg_val;
6947
6948         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6949                 status = i40e_aq_get_phy_register(hw,
6950                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6951                                                 I40E_PHY_COM_REG_PAGE, true,
6952                                                 I40E_PHY_LED_PROV_REG_1,
6953                                                 &reg_val_aq, NULL);
6954                 if (status == I40E_SUCCESS)
6955                         *val = (u16)reg_val_aq;
6956                 return status;
6957         }
6958         temp_addr = I40E_PHY_LED_PROV_REG_1;
6959         phy_addr = i40e_get_phy_address(hw, hw->port);
6960         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6961              temp_addr++) {
6962                 status = i40e_read_phy_register_clause45(hw,
6963                                                          I40E_PHY_COM_REG_PAGE,
6964                                                          temp_addr, phy_addr,
6965                                                          &reg_val);
6966                 if (status)
6967                         return status;
6968                 *val = reg_val;
6969                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6970                         *led_addr = temp_addr;
6971                         break;
6972                 }
6973         }
6974         return status;
6975 }
6976
6977 /**
6978  * i40e_led_set_phy
6979  * @hw: pointer to the HW structure
6980  * @on: true or false
6981  * @led_addr: address of led register to use
6982  * @mode: original val plus bit for set or ignore
6983  *
6984  * Set led's on or off when controlled by the PHY
6985  *
6986  **/
6987 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6988                                        u16 led_addr, u32 mode)
6989 {
6990         enum i40e_status_code status = I40E_SUCCESS;
6991         u32 led_ctl = 0;
6992         u32 led_reg = 0;
6993
6994         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6995         if (status)
6996                 return status;
6997         led_ctl = led_reg;
6998         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6999                 led_reg = 0;
7000                 status = i40e_led_set_reg(hw, led_addr, led_reg);
7001                 if (status)
7002                         return status;
7003         }
7004         status = i40e_led_get_reg(hw, led_addr, &led_reg);
7005         if (status)
7006                 goto restore_config;
7007         if (on)
7008                 led_reg = I40E_PHY_LED_MANUAL_ON;
7009         else
7010                 led_reg = 0;
7011         status = i40e_led_set_reg(hw, led_addr, led_reg);
7012         if (status)
7013                 goto restore_config;
7014         if (mode & I40E_PHY_LED_MODE_ORIG) {
7015                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
7016                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
7017         }
7018         return status;
7019
7020 restore_config:
7021         status = i40e_led_set_reg(hw, led_addr, led_ctl);
7022         return status;
7023 }
7024 #endif /* PF_DRIVER */
7025 /**
7026  * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
7027  * @hw: pointer to the hw struct
7028  * @stat: pointer to structure with status of rx and tx lpi
7029  *
7030  * Read LPI state directly from external PHY register or from MAC
7031  * register, depending on device ID and current link speed.
7032  */
7033 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
7034                                               struct i40e_hw_port_stats *stat)
7035 {
7036         enum i40e_status_code ret = I40E_SUCCESS;
7037         u32 val;
7038
7039         stat->rx_lpi_status = 0;
7040         stat->tx_lpi_status = 0;
7041
7042         if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7043              hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7044             (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7045              hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
7046                 ret = i40e_aq_get_phy_register(hw,
7047                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7048                                                I40E_BCM_PHY_PCS_STATUS1_PAGE,
7049                                                true,
7050                                                I40E_BCM_PHY_PCS_STATUS1_REG,
7051                                                &val, NULL);
7052
7053                 if (ret != I40E_SUCCESS)
7054                         return ret;
7055
7056                 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7057                 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7058
7059                 return ret;
7060         }
7061
7062         val = rd32(hw, I40E_PRTPM_EEE_STAT);
7063         stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7064                                I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7065         stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7066                                I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7067
7068         return ret;
7069 }
7070
7071 /**
7072  * i40e_get_lpi_counters - read LPI counters from EEE statistics
7073  * @hw: pointer to the hw struct
7074  * @tx_counter: pointer to memory for TX LPI counter
7075  * @rx_counter: pointer to memory for RX LPI counter
7076  * @is_clear:   returns true if counters are clear after read
7077  *
7078  * Read Low Power Idle (LPI) mode counters from Energy Efficient
7079  * Ethernet (EEE) statistics.
7080  **/
7081 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7082                                             u32 *tx_counter, u32 *rx_counter,
7083                                             bool *is_clear)
7084 {
7085         /* only X710-T*L requires special handling of counters
7086          * for other devices we just read the MAC registers
7087          */
7088         if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7089              hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7090             hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7091                 enum i40e_status_code retval;
7092                 u32 cmd_status = 0;
7093
7094                 *is_clear = false;
7095                 retval = i40e_aq_run_phy_activity(hw,
7096                                 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7097                                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7098                                 &cmd_status, tx_counter, rx_counter, NULL);
7099
7100                 if (cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7101                         retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7102
7103                 return retval;
7104         }
7105
7106         *is_clear = true;
7107         *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7108         *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7109
7110         return I40E_SUCCESS;
7111 }
7112
7113 /**
7114  * i40e_get_lpi_duration - read LPI time duration from EEE statistics
7115  * @hw: pointer to the hw struct
7116  * @stat: pointer to structure with status of rx and tx lpi
7117  * @tx_duration: pointer to memory for TX LPI time duration
7118  * @rx_duration: pointer to memory for RX LPI time duration
7119  *
7120  * Read Low Power Idle (LPI) mode time duration from Energy Efficient
7121  * Ethernet (EEE) statistics.
7122  */
7123 enum i40e_status_code i40e_get_lpi_duration(struct i40e_hw *hw,
7124                                             struct i40e_hw_port_stats *stat,
7125                                             u64 *tx_duration, u64 *rx_duration)
7126 {
7127         u32 tx_time_dur, rx_time_dur;
7128         enum i40e_status_code retval;
7129         u32 cmd_status;
7130
7131         if (hw->device_id != I40E_DEV_ID_10G_BASE_T_BC &&
7132             hw->device_id != I40E_DEV_ID_5G_BASE_T_BC)
7133                 return I40E_ERR_NOT_IMPLEMENTED;
7134
7135         retval = i40e_aq_run_phy_activity
7136                 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7137                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR,
7138                 &cmd_status, &tx_time_dur, &rx_time_dur, NULL);
7139
7140         if (retval)
7141                 return retval;
7142         if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7143             I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7144                 return I40E_ERR_ADMIN_QUEUE_ERROR;
7145
7146         if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB &&
7147             !tx_time_dur && !rx_time_dur &&
7148             stat->tx_lpi_status && stat->rx_lpi_status) {
7149                 retval = i40e_aq_run_phy_activity
7150                         (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7151                         I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR,
7152                         &cmd_status,
7153                         &tx_time_dur, &rx_time_dur, NULL);
7154
7155                 if (retval)
7156                         return retval;
7157                 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7158                     I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7159                         return I40E_ERR_ADMIN_QUEUE_ERROR;
7160                 tx_time_dur = 0;
7161                 rx_time_dur = 0;
7162         }
7163
7164         *tx_duration = tx_time_dur;
7165         *rx_duration = rx_time_dur;
7166
7167         return retval;
7168 }
7169
7170 /**
7171  * i40e_lpi_stat_update - update LPI counters with values relative to offset
7172  * @hw: pointer to the hw struct
7173  * @offset_loaded: flag indicating need of writing current value to offset
7174  * @tx_offset: pointer to offset of TX LPI counter
7175  * @tx_stat: pointer to value of TX LPI counter
7176  * @rx_offset: pointer to offset of RX LPI counter
7177  * @rx_stat: pointer to value of RX LPI counter
7178  *
7179  * Update Low Power Idle (LPI) mode counters while having regard to passed
7180  * offsets.
7181  **/
7182 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7183                                            bool offset_loaded, u64 *tx_offset,
7184                                            u64 *tx_stat, u64 *rx_offset,
7185                                            u64 *rx_stat)
7186 {
7187         enum i40e_status_code retval;
7188         u32 tx_counter, rx_counter;
7189         bool is_clear;
7190
7191         retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7192         if (retval)
7193                 goto err;
7194
7195         if (is_clear) {
7196                 *tx_stat += tx_counter;
7197                 *rx_stat += rx_counter;
7198         } else {
7199                 if (!offset_loaded) {
7200                         *tx_offset = tx_counter;
7201                         *rx_offset = rx_counter;
7202                 }
7203
7204                 *tx_stat = (tx_counter >= *tx_offset) ?
7205                         (u32)(tx_counter - *tx_offset) :
7206                         (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7207                 *rx_stat = (rx_counter >= *rx_offset) ?
7208                         (u32)(rx_counter - *rx_offset) :
7209                         (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7210         }
7211 err:
7212         return retval;
7213 }
7214
7215 /**
7216  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7217  * @hw: pointer to the hw struct
7218  * @reg_addr: register address
7219  * @reg_val: ptr to register value
7220  * @cmd_details: pointer to command details structure or NULL
7221  *
7222  * Use the firmware to read the Rx control register,
7223  * especially useful if the Rx unit is under heavy pressure
7224  **/
7225 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7226                                 u32 reg_addr, u32 *reg_val,
7227                                 struct i40e_asq_cmd_details *cmd_details)
7228 {
7229         struct i40e_aq_desc desc;
7230         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7231                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7232         enum i40e_status_code status;
7233
7234         if (reg_val == NULL)
7235                 return I40E_ERR_PARAM;
7236
7237         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7238
7239         cmd_resp->address = CPU_TO_LE32(reg_addr);
7240
7241         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7242
7243         if (status == I40E_SUCCESS)
7244                 *reg_val = LE32_TO_CPU(cmd_resp->value);
7245
7246         return status;
7247 }
7248
7249 /**
7250  * i40e_read_rx_ctl - read from an Rx control register
7251  * @hw: pointer to the hw struct
7252  * @reg_addr: register address
7253  **/
7254 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7255 {
7256         enum i40e_status_code status = I40E_SUCCESS;
7257         bool use_register;
7258         int retry = 5;
7259         u32 val = 0;
7260
7261         use_register = (((hw->aq.api_maj_ver == 1) &&
7262                         (hw->aq.api_min_ver < 5)) ||
7263                         (hw->mac.type == I40E_MAC_X722));
7264         if (!use_register) {
7265 do_retry:
7266                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7267                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7268                         i40e_msec_delay(1);
7269                         retry--;
7270                         goto do_retry;
7271                 }
7272         }
7273
7274         /* if the AQ access failed, try the old-fashioned way */
7275         if (status || use_register)
7276                 val = rd32(hw, reg_addr);
7277
7278         return val;
7279 }
7280
7281 /**
7282  * i40e_aq_rx_ctl_write_register
7283  * @hw: pointer to the hw struct
7284  * @reg_addr: register address
7285  * @reg_val: register value
7286  * @cmd_details: pointer to command details structure or NULL
7287  *
7288  * Use the firmware to write to an Rx control register,
7289  * especially useful if the Rx unit is under heavy pressure
7290  **/
7291 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7292                                 u32 reg_addr, u32 reg_val,
7293                                 struct i40e_asq_cmd_details *cmd_details)
7294 {
7295         struct i40e_aq_desc desc;
7296         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7297                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7298         enum i40e_status_code status;
7299
7300         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7301
7302         cmd->address = CPU_TO_LE32(reg_addr);
7303         cmd->value = CPU_TO_LE32(reg_val);
7304
7305         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7306
7307         return status;
7308 }
7309
7310 /**
7311  * i40e_write_rx_ctl - write to an Rx control register
7312  * @hw: pointer to the hw struct
7313  * @reg_addr: register address
7314  * @reg_val: register value
7315  **/
7316 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7317 {
7318         enum i40e_status_code status = I40E_SUCCESS;
7319         bool use_register;
7320         int retry = 5;
7321
7322         use_register = (((hw->aq.api_maj_ver == 1) &&
7323                         (hw->aq.api_min_ver < 5)) ||
7324                         (hw->mac.type == I40E_MAC_X722));
7325         if (!use_register) {
7326 do_retry:
7327                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7328                                                        reg_val, NULL);
7329                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7330                         i40e_msec_delay(1);
7331                         retry--;
7332                         goto do_retry;
7333                 }
7334         }
7335
7336         /* if the AQ access failed, try the old-fashioned way */
7337         if (status || use_register)
7338                 wr32(hw, reg_addr, reg_val);
7339 }
7340
7341 /**
7342  * i40e_mdio_if_number_selection - MDIO I/F number selection
7343  * @hw: pointer to the hw struct
7344  * @set_mdio: use MDIO I/F number specified by mdio_num
7345  * @mdio_num: MDIO I/F number
7346  * @cmd: pointer to PHY Register command structure
7347  **/
7348 static void
7349 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7350                               struct i40e_aqc_phy_register_access *cmd)
7351 {
7352         if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7353                 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7354                         cmd->cmd_flags |=
7355                                 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7356                                 ((mdio_num <<
7357                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7358                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7359                 else
7360                         i40e_debug(hw, I40E_DEBUG_PHY,
7361                                    "MDIO I/F number selection not supported by current FW version.\n");
7362         }
7363 }
7364
7365 /**
7366  * i40e_aq_set_phy_register_ext
7367  * @hw: pointer to the hw struct
7368  * @phy_select: select which phy should be accessed
7369  * @dev_addr: PHY device address
7370  * @page_change: enable auto page change
7371  * @set_mdio: use MDIO I/F number specified by mdio_num
7372  * @mdio_num: MDIO I/F number
7373  * @reg_addr: PHY register address
7374  * @reg_val: new register value
7375  * @cmd_details: pointer to command details structure or NULL
7376  *
7377  * Write the external PHY register.
7378  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7379  * may use simple wrapper i40e_aq_set_phy_register.
7380  **/
7381 enum i40e_status_code
7382 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7383                              u8 phy_select, u8 dev_addr, bool page_change,
7384                              bool set_mdio, u8 mdio_num,
7385                              u32 reg_addr, u32 reg_val,
7386                              struct i40e_asq_cmd_details *cmd_details)
7387 {
7388         struct i40e_aq_desc desc;
7389         struct i40e_aqc_phy_register_access *cmd =
7390                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7391         enum i40e_status_code status;
7392
7393         i40e_fill_default_direct_cmd_desc(&desc,
7394                                           i40e_aqc_opc_set_phy_register);
7395
7396         cmd->phy_interface = phy_select;
7397         cmd->dev_addres = dev_addr;
7398         cmd->reg_address = CPU_TO_LE32(reg_addr);
7399         cmd->reg_value = CPU_TO_LE32(reg_val);
7400
7401         if (!page_change)
7402                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7403
7404         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7405
7406         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7407
7408         return status;
7409 }
7410
7411 /**
7412  * i40e_aq_get_phy_register_ext
7413  * @hw: pointer to the hw struct
7414  * @phy_select: select which phy should be accessed
7415  * @dev_addr: PHY device address
7416  * @page_change: enable auto page change
7417  * @set_mdio: use MDIO I/F number specified by mdio_num
7418  * @mdio_num: MDIO I/F number
7419  * @reg_addr: PHY register address
7420  * @reg_val: read register value
7421  * @cmd_details: pointer to command details structure or NULL
7422  *
7423  * Read the external PHY register.
7424  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7425  * may use simple wrapper i40e_aq_get_phy_register.
7426  **/
7427 enum i40e_status_code
7428 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7429                              u8 phy_select, u8 dev_addr, bool page_change,
7430                              bool set_mdio, u8 mdio_num,
7431                              u32 reg_addr, u32 *reg_val,
7432                              struct i40e_asq_cmd_details *cmd_details)
7433 {
7434         struct i40e_aq_desc desc;
7435         struct i40e_aqc_phy_register_access *cmd =
7436                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7437         enum i40e_status_code status;
7438
7439         i40e_fill_default_direct_cmd_desc(&desc,
7440                                           i40e_aqc_opc_get_phy_register);
7441
7442         cmd->phy_interface = phy_select;
7443         cmd->dev_addres = dev_addr;
7444         cmd->reg_address = CPU_TO_LE32(reg_addr);
7445
7446         if (!page_change)
7447                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7448
7449         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7450
7451         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7452         if (!status)
7453                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7454
7455         return status;
7456 }
7457
7458 /**
7459  * i40e_aq_run_phy_activity
7460  * @hw: pointer to the hw struct
7461  * @activity_id: ID of DNL activity to run
7462  * @dnl_opcode: opcode passed to DNL script
7463  * @cmd_status: pointer to memory to write return value of DNL script
7464  * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7465  * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7466  * @cmd_details: pointer to command details structure or NULL
7467  *
7468  * Run DNL admin command.
7469  **/
7470 enum i40e_status_code
7471 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7472                          u32 *cmd_status, u32 *data0, u32 *data1,
7473                          struct i40e_asq_cmd_details *cmd_details)
7474 {
7475         struct i40e_aqc_run_phy_activity *cmd;
7476         enum i40e_status_code retval;
7477         struct i40e_aq_desc desc;
7478
7479         cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7480
7481         if (!cmd_status || !data0 || !data1) {
7482                 retval = I40E_ERR_PARAM;
7483                 goto err;
7484         }
7485
7486         i40e_fill_default_direct_cmd_desc(&desc,
7487                                           i40e_aqc_opc_run_phy_activity);
7488
7489         cmd->activity_id = CPU_TO_LE16(activity_id);
7490         cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7491
7492         retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7493         if (retval)
7494                 goto err;
7495
7496         *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7497         *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7498         *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7499 err:
7500         return retval;
7501 }
7502
7503 #ifdef VF_DRIVER
7504
7505 /**
7506  * i40e_aq_send_msg_to_pf
7507  * @hw: pointer to the hardware structure
7508  * @v_opcode: opcodes for VF-PF communication
7509  * @v_retval: return error code
7510  * @msg: pointer to the msg buffer
7511  * @msglen: msg length
7512  * @cmd_details: pointer to command details
7513  *
7514  * Send message to PF driver using admin queue. By default, this message
7515  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7516  * completion before returning.
7517  **/
7518 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7519                                 enum virtchnl_ops v_opcode,
7520                                 enum i40e_status_code v_retval,
7521                                 u8 *msg, u16 msglen,
7522                                 struct i40e_asq_cmd_details *cmd_details)
7523 {
7524         struct i40e_aq_desc desc;
7525         struct i40e_asq_cmd_details details;
7526         enum i40e_status_code status;
7527
7528         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7529         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7530         desc.cookie_high = CPU_TO_LE32(v_opcode);
7531         desc.cookie_low = CPU_TO_LE32(v_retval);
7532         if (msglen) {
7533                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7534                                                 | I40E_AQ_FLAG_RD));
7535                 if (msglen > I40E_AQ_LARGE_BUF)
7536                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7537                 desc.datalen = CPU_TO_LE16(msglen);
7538         }
7539         if (!cmd_details) {
7540                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7541                 details.async = true;
7542                 cmd_details = &details;
7543         }
7544         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7545                                        msglen, cmd_details);
7546         return status;
7547 }
7548
7549 /**
7550  * i40e_vf_parse_hw_config
7551  * @hw: pointer to the hardware structure
7552  * @msg: pointer to the virtual channel VF resource structure
7553  *
7554  * Given a VF resource message from the PF, populate the hw struct
7555  * with appropriate information.
7556  **/
7557 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7558                              struct virtchnl_vf_resource *msg)
7559 {
7560         struct virtchnl_vsi_resource *vsi_res;
7561         int i;
7562
7563         vsi_res = &msg->vsi_res[0];
7564
7565         hw->dev_caps.num_vsis = msg->num_vsis;
7566         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7567         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7568         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7569         hw->dev_caps.dcb = msg->vf_cap_flags &
7570                            VIRTCHNL_VF_OFFLOAD_L2;
7571         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7572                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7573         for (i = 0; i < msg->num_vsis; i++) {
7574                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7575                         i40e_memcpy(hw->mac.perm_addr,
7576                                     vsi_res->default_mac_addr,
7577                                     ETH_ALEN,
7578                                     I40E_NONDMA_TO_NONDMA);
7579                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7580                                     ETH_ALEN,
7581                                     I40E_NONDMA_TO_NONDMA);
7582                 }
7583                 vsi_res++;
7584         }
7585 }
7586
7587 /**
7588  * i40e_vf_reset
7589  * @hw: pointer to the hardware structure
7590  *
7591  * Send a VF_RESET message to the PF. Does not wait for response from PF
7592  * as none will be forthcoming. Immediately after calling this function,
7593  * the admin queue should be shut down and (optionally) reinitialized.
7594  **/
7595 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7596 {
7597         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7598                                       I40E_SUCCESS, NULL, 0, NULL);
7599 }
7600 #endif /* VF_DRIVER */
7601
7602 /**
7603  * i40e_aq_set_arp_proxy_config
7604  * @hw: pointer to the HW structure
7605  * @proxy_config: pointer to proxy config command table struct
7606  * @cmd_details: pointer to command details
7607  *
7608  * Set ARP offload parameters from pre-populated
7609  * i40e_aqc_arp_proxy_data struct
7610  **/
7611 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7612                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7613                                 struct i40e_asq_cmd_details *cmd_details)
7614 {
7615         struct i40e_aq_desc desc;
7616         enum i40e_status_code status;
7617
7618         if (!proxy_config)
7619                 return I40E_ERR_PARAM;
7620
7621         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7622
7623         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7624         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7625         desc.params.external.addr_high =
7626                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7627         desc.params.external.addr_low =
7628                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7629         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7630
7631         status = i40e_asq_send_command(hw, &desc, proxy_config,
7632                                        sizeof(struct i40e_aqc_arp_proxy_data),
7633                                        cmd_details);
7634
7635         return status;
7636 }
7637
7638 /**
7639  * i40e_aq_opc_set_ns_proxy_table_entry
7640  * @hw: pointer to the HW structure
7641  * @ns_proxy_table_entry: pointer to NS table entry command struct
7642  * @cmd_details: pointer to command details
7643  *
7644  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7645  * from pre-populated i40e_aqc_ns_proxy_data struct
7646  **/
7647 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7648                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7649                         struct i40e_asq_cmd_details *cmd_details)
7650 {
7651         struct i40e_aq_desc desc;
7652         enum i40e_status_code status;
7653
7654         if (!ns_proxy_table_entry)
7655                 return I40E_ERR_PARAM;
7656
7657         i40e_fill_default_direct_cmd_desc(&desc,
7658                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7659
7660         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7661         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7662         desc.params.external.addr_high =
7663                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7664         desc.params.external.addr_low =
7665                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7666         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7667
7668         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7669                                        sizeof(struct i40e_aqc_ns_proxy_data),
7670                                        cmd_details);
7671
7672         return status;
7673 }
7674
7675 /**
7676  * i40e_aq_set_clear_wol_filter
7677  * @hw: pointer to the hw struct
7678  * @filter_index: index of filter to modify (0-7)
7679  * @filter: buffer containing filter to be set
7680  * @set_filter: true to set filter, false to clear filter
7681  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7682  *              if false, pass through packets may cause wake-up
7683  * @filter_valid: true if filter action is valid
7684  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7685  * @cmd_details: pointer to command details structure or NULL
7686  *
7687  * Set or clear WoL filter for port attached to the PF
7688  **/
7689 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7690                                 u8 filter_index,
7691                                 struct i40e_aqc_set_wol_filter_data *filter,
7692                                 bool set_filter, bool no_wol_tco,
7693                                 bool filter_valid, bool no_wol_tco_valid,
7694                                 struct i40e_asq_cmd_details *cmd_details)
7695 {
7696         struct i40e_aq_desc desc;
7697         struct i40e_aqc_set_wol_filter *cmd =
7698                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7699         enum i40e_status_code status;
7700         u16 cmd_flags = 0;
7701         u16 valid_flags = 0;
7702         u16 buff_len = 0;
7703
7704         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7705
7706         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7707                 return  I40E_ERR_PARAM;
7708         cmd->filter_index = CPU_TO_LE16(filter_index);
7709
7710         if (set_filter) {
7711                 if (!filter)
7712                         return  I40E_ERR_PARAM;
7713
7714                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7715                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7716         }
7717
7718         if (no_wol_tco)
7719                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7720         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7721
7722         if (filter_valid)
7723                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7724         if (no_wol_tco_valid)
7725                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7726         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7727
7728         buff_len = sizeof(*filter);
7729         desc.datalen = CPU_TO_LE16(buff_len);
7730
7731         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7732         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7733
7734         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7735         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7736
7737         status = i40e_asq_send_command(hw, &desc, filter,
7738                                        buff_len, cmd_details);
7739
7740         return status;
7741 }
7742
7743 /**
7744  * i40e_aq_get_wake_event_reason
7745  * @hw: pointer to the hw struct
7746  * @wake_reason: return value, index of matching filter
7747  * @cmd_details: pointer to command details structure or NULL
7748  *
7749  * Get information for the reason of a Wake Up event
7750  **/
7751 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7752                                 u16 *wake_reason,
7753                                 struct i40e_asq_cmd_details *cmd_details)
7754 {
7755         struct i40e_aq_desc desc;
7756         struct i40e_aqc_get_wake_reason_completion *resp =
7757                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7758         enum i40e_status_code status;
7759
7760         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7761
7762         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7763
7764         if (status == I40E_SUCCESS)
7765                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7766
7767         return status;
7768 }
7769
7770 /**
7771 * i40e_aq_clear_all_wol_filters
7772 * @hw: pointer to the hw struct
7773 * @cmd_details: pointer to command details structure or NULL
7774 *
7775 * Get information for the reason of a Wake Up event
7776 **/
7777 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7778         struct i40e_asq_cmd_details *cmd_details)
7779 {
7780         struct i40e_aq_desc desc;
7781         enum i40e_status_code status;
7782
7783         i40e_fill_default_direct_cmd_desc(&desc,
7784                                           i40e_aqc_opc_clear_all_wol_filters);
7785
7786         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7787
7788         return status;
7789 }
7790
7791 /**
7792  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7793  * @hw: pointer to the hw struct
7794  * @buff: command buffer (size in bytes = buff_size)
7795  * @buff_size: buffer size in bytes
7796  * @track_id: package tracking id
7797  * @error_offset: returns error offset
7798  * @error_info: returns error information
7799  * @cmd_details: pointer to command details structure or NULL
7800  **/
7801 enum
7802 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7803                                    u16 buff_size, u32 track_id,
7804                                    u32 *error_offset, u32 *error_info,
7805                                    struct i40e_asq_cmd_details *cmd_details)
7806 {
7807         struct i40e_aq_desc desc;
7808         struct i40e_aqc_write_personalization_profile *cmd =
7809                 (struct i40e_aqc_write_personalization_profile *)
7810                 &desc.params.raw;
7811         struct i40e_aqc_write_ddp_resp *resp;
7812         enum i40e_status_code status;
7813
7814         i40e_fill_default_direct_cmd_desc(&desc,
7815                                   i40e_aqc_opc_write_personalization_profile);
7816
7817         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7818         if (buff_size > I40E_AQ_LARGE_BUF)
7819                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7820
7821         desc.datalen = CPU_TO_LE16(buff_size);
7822
7823         cmd->profile_track_id = CPU_TO_LE32(track_id);
7824
7825         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7826         if (!status) {
7827                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7828                 if (error_offset)
7829                         *error_offset = LE32_TO_CPU(resp->error_offset);
7830                 if (error_info)
7831                         *error_info = LE32_TO_CPU(resp->error_info);
7832         }
7833
7834         return status;
7835 }
7836
7837 /**
7838  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7839  * @hw: pointer to the hw struct
7840  * @buff: command buffer (size in bytes = buff_size)
7841  * @buff_size: buffer size in bytes
7842  * @flags: AdminQ command flags
7843  * @cmd_details: pointer to command details structure or NULL
7844  **/
7845 enum
7846 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7847                                       u16 buff_size, u8 flags,
7848                                       struct i40e_asq_cmd_details *cmd_details)
7849 {
7850         struct i40e_aq_desc desc;
7851         struct i40e_aqc_get_applied_profiles *cmd =
7852                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7853         enum i40e_status_code status;
7854
7855         i40e_fill_default_direct_cmd_desc(&desc,
7856                           i40e_aqc_opc_get_personalization_profile_list);
7857
7858         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7859         if (buff_size > I40E_AQ_LARGE_BUF)
7860                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7861         desc.datalen = CPU_TO_LE16(buff_size);
7862
7863         cmd->flags = flags;
7864
7865         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7866
7867         return status;
7868 }
7869
7870 /**
7871  * i40e_find_segment_in_package
7872  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7873  * @pkg_hdr: pointer to the package header to be searched
7874  *
7875  * This function searches a package file for a particular segment type. On
7876  * success it returns a pointer to the segment header, otherwise it will
7877  * return NULL.
7878  **/
7879 struct i40e_generic_seg_header *
7880 i40e_find_segment_in_package(u32 segment_type,
7881                              struct i40e_package_header *pkg_hdr)
7882 {
7883         struct i40e_generic_seg_header *segment;
7884         u32 i;
7885
7886         /* Search all package segments for the requested segment type */
7887         for (i = 0; i < pkg_hdr->segment_count; i++) {
7888                 segment =
7889                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7890                          pkg_hdr->segment_offset[i]);
7891
7892                 if (segment->type == segment_type)
7893                         return segment;
7894         }
7895
7896         return NULL;
7897 }
7898
7899 /* Get section table in profile */
7900 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7901         do {                                                            \
7902                 struct i40e_profile_segment *p = (profile);             \
7903                 u32 count;                                              \
7904                 u32 *nvm;                                               \
7905                 count = p->device_table_count;                          \
7906                 nvm = (u32 *)&p->device_table[count];                   \
7907                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7908         } while (0)
7909
7910 /* Get section header in profile */
7911 #define I40E_SECTION_HEADER(profile, offset)                            \
7912         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7913
7914 /**
7915  * i40e_find_section_in_profile
7916  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7917  * @profile: pointer to the i40e segment header to be searched
7918  *
7919  * This function searches i40e segment for a particular section type. On
7920  * success it returns a pointer to the section header, otherwise it will
7921  * return NULL.
7922  **/
7923 struct i40e_profile_section_header *
7924 i40e_find_section_in_profile(u32 section_type,
7925                              struct i40e_profile_segment *profile)
7926 {
7927         struct i40e_profile_section_header *sec;
7928         struct i40e_section_table *sec_tbl;
7929         u32 sec_off;
7930         u32 i;
7931
7932         if (profile->header.type != SEGMENT_TYPE_I40E)
7933                 return NULL;
7934
7935         I40E_SECTION_TABLE(profile, sec_tbl);
7936
7937         for (i = 0; i < sec_tbl->section_count; i++) {
7938                 sec_off = sec_tbl->section_offset[i];
7939                 sec = I40E_SECTION_HEADER(profile, sec_off);
7940                 if (sec->section.type == section_type)
7941                         return sec;
7942         }
7943
7944         return NULL;
7945 }
7946
7947 /**
7948  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7949  * @hw: pointer to the hw struct
7950  * @aq: command buffer containing all data to execute AQ
7951  **/
7952 STATIC enum
7953 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7954                                           struct i40e_profile_aq_section *aq)
7955 {
7956         enum i40e_status_code status;
7957         struct i40e_aq_desc desc;
7958         u8 *msg = NULL;
7959         u16 msglen;
7960
7961         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7962         desc.flags |= CPU_TO_LE16(aq->flags);
7963         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7964                     I40E_NONDMA_TO_NONDMA);
7965
7966         msglen = aq->datalen;
7967         if (msglen) {
7968                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7969                                                 I40E_AQ_FLAG_RD));
7970                 if (msglen > I40E_AQ_LARGE_BUF)
7971                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7972                 desc.datalen = CPU_TO_LE16(msglen);
7973                 msg = &aq->data[0];
7974         }
7975
7976         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7977
7978         if (status != I40E_SUCCESS) {
7979                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7980                            "unable to exec DDP AQ opcode %u, error %d\n",
7981                            aq->opcode, status);
7982                 return status;
7983         }
7984
7985         /* copy returned desc to aq_buf */
7986         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7987                     I40E_NONDMA_TO_NONDMA);
7988
7989         return I40E_SUCCESS;
7990 }
7991
7992 /**
7993  * i40e_validate_profile
7994  * @hw: pointer to the hardware structure
7995  * @profile: pointer to the profile segment of the package to be validated
7996  * @track_id: package tracking id
7997  * @rollback: flag if the profile is for rollback.
7998  *
7999  * Validates supported devices and profile's sections.
8000  */
8001 STATIC enum i40e_status_code
8002 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8003                       u32 track_id, bool rollback)
8004 {
8005         struct i40e_profile_section_header *sec = NULL;
8006         enum i40e_status_code status = I40E_SUCCESS;
8007         struct i40e_section_table *sec_tbl;
8008         u32 vendor_dev_id;
8009         u32 dev_cnt;
8010         u32 sec_off;
8011         u32 i;
8012
8013         if (track_id == I40E_DDP_TRACKID_INVALID) {
8014                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
8015                 return I40E_NOT_SUPPORTED;
8016         }
8017
8018         dev_cnt = profile->device_table_count;
8019         for (i = 0; i < dev_cnt; i++) {
8020                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
8021                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
8022                     hw->device_id == (vendor_dev_id & 0xFFFF))
8023                         break;
8024         }
8025         if (dev_cnt && (i == dev_cnt)) {
8026                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8027                            "Device doesn't support DDP\n");
8028                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
8029         }
8030
8031         I40E_SECTION_TABLE(profile, sec_tbl);
8032
8033         /* Validate sections types */
8034         for (i = 0; i < sec_tbl->section_count; i++) {
8035                 sec_off = sec_tbl->section_offset[i];
8036                 sec = I40E_SECTION_HEADER(profile, sec_off);
8037                 if (rollback) {
8038                         if (sec->section.type == SECTION_TYPE_MMIO ||
8039                             sec->section.type == SECTION_TYPE_AQ ||
8040                             sec->section.type == SECTION_TYPE_RB_AQ) {
8041                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8042                                            "Not a roll-back package\n");
8043                                 return I40E_NOT_SUPPORTED;
8044                         }
8045                 } else {
8046                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
8047                             sec->section.type == SECTION_TYPE_RB_MMIO) {
8048                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8049                                            "Not an original package\n");
8050                                 return I40E_NOT_SUPPORTED;
8051                         }
8052                 }
8053         }
8054
8055         return status;
8056 }
8057
8058 /**
8059  * i40e_write_profile
8060  * @hw: pointer to the hardware structure
8061  * @profile: pointer to the profile segment of the package to be downloaded
8062  * @track_id: package tracking id
8063  *
8064  * Handles the download of a complete package.
8065  */
8066 enum i40e_status_code
8067 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8068                    u32 track_id)
8069 {
8070         enum i40e_status_code status = I40E_SUCCESS;
8071         struct i40e_section_table *sec_tbl;
8072         struct i40e_profile_section_header *sec = NULL;
8073         struct i40e_profile_aq_section *ddp_aq;
8074         u32 section_size = 0;
8075         u32 offset = 0, info = 0;
8076         u32 sec_off;
8077         u32 i;
8078
8079         status = i40e_validate_profile(hw, profile, track_id, false);
8080         if (status)
8081                 return status;
8082
8083         I40E_SECTION_TABLE(profile, sec_tbl);
8084
8085         for (i = 0; i < sec_tbl->section_count; i++) {
8086                 sec_off = sec_tbl->section_offset[i];
8087                 sec = I40E_SECTION_HEADER(profile, sec_off);
8088                 /* Process generic admin command */
8089                 if (sec->section.type == SECTION_TYPE_AQ) {
8090                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
8091                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
8092                         if (status) {
8093                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8094                                            "Failed to execute aq: section %d, opcode %u\n",
8095                                            i, ddp_aq->opcode);
8096                                 break;
8097                         }
8098                         sec->section.type = SECTION_TYPE_RB_AQ;
8099                 }
8100
8101                 /* Skip any non-mmio sections */
8102                 if (sec->section.type != SECTION_TYPE_MMIO)
8103                         continue;
8104
8105                 section_size = sec->section.size +
8106                         sizeof(struct i40e_profile_section_header);
8107
8108                 /* Write MMIO section */
8109                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8110                                            track_id, &offset, &info, NULL);
8111                 if (status) {
8112                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8113                                    "Failed to write profile: section %d, offset %d, info %d\n",
8114                                    i, offset, info);
8115                         break;
8116                 }
8117         }
8118         return status;
8119 }
8120
8121 /**
8122  * i40e_rollback_profile
8123  * @hw: pointer to the hardware structure
8124  * @profile: pointer to the profile segment of the package to be removed
8125  * @track_id: package tracking id
8126  *
8127  * Rolls back previously loaded package.
8128  */
8129 enum i40e_status_code
8130 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8131                       u32 track_id)
8132 {
8133         struct i40e_profile_section_header *sec = NULL;
8134         enum i40e_status_code status = I40E_SUCCESS;
8135         struct i40e_section_table *sec_tbl;
8136         u32 offset = 0, info = 0;
8137         u32 section_size = 0;
8138         u32 sec_off;
8139         int i;
8140
8141         status = i40e_validate_profile(hw, profile, track_id, true);
8142         if (status)
8143                 return status;
8144
8145         I40E_SECTION_TABLE(profile, sec_tbl);
8146
8147         /* For rollback write sections in reverse */
8148         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8149                 sec_off = sec_tbl->section_offset[i];
8150                 sec = I40E_SECTION_HEADER(profile, sec_off);
8151
8152                 /* Skip any non-rollback sections */
8153                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8154                         continue;
8155
8156                 section_size = sec->section.size +
8157                         sizeof(struct i40e_profile_section_header);
8158
8159                 /* Write roll-back MMIO section */
8160                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8161                                            track_id, &offset, &info, NULL);
8162                 if (status) {
8163                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8164                                    "Failed to write profile: section %d, offset %d, info %d\n",
8165                                    i, offset, info);
8166                         break;
8167                 }
8168         }
8169         return status;
8170 }
8171
8172 /**
8173  * i40e_add_pinfo_to_list
8174  * @hw: pointer to the hardware structure
8175  * @profile: pointer to the profile segment of the package
8176  * @profile_info_sec: buffer for information section
8177  * @track_id: package tracking id
8178  *
8179  * Register a profile to the list of loaded profiles.
8180  */
8181 enum i40e_status_code
8182 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8183                        struct i40e_profile_segment *profile,
8184                        u8 *profile_info_sec, u32 track_id)
8185 {
8186         enum i40e_status_code status = I40E_SUCCESS;
8187         struct i40e_profile_section_header *sec = NULL;
8188         struct i40e_profile_info *pinfo;
8189         u32 offset = 0, info = 0;
8190
8191         sec = (struct i40e_profile_section_header *)profile_info_sec;
8192         sec->tbl_size = 1;
8193         sec->data_end = sizeof(struct i40e_profile_section_header) +
8194                         sizeof(struct i40e_profile_info);
8195         sec->section.type = SECTION_TYPE_INFO;
8196         sec->section.offset = sizeof(struct i40e_profile_section_header);
8197         sec->section.size = sizeof(struct i40e_profile_info);
8198         pinfo = (struct i40e_profile_info *)(profile_info_sec +
8199                                              sec->section.offset);
8200         pinfo->track_id = track_id;
8201         pinfo->version = profile->version;
8202         pinfo->op = I40E_DDP_ADD_TRACKID;
8203         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8204                     I40E_NONDMA_TO_NONDMA);
8205
8206         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8207                                    track_id, &offset, &info, NULL);
8208         return status;
8209 }