drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  19 #else
  20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  21 #endif
  22 {
  23         enum i40e_status_code status = I40E_SUCCESS;
  24
  25         DEBUGFUNC("i40e_set_mac_type\n");
  26
  27         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  28                 switch (hw->device_id) {
  29                 case I40E_DEV_ID_SFP_XL710:
  30                 case I40E_DEV_ID_QEMU:
  31                 case I40E_DEV_ID_KX_B:
  32                 case I40E_DEV_ID_KX_C:
  33                 case I40E_DEV_ID_QSFP_A:
  34                 case I40E_DEV_ID_QSFP_B:
  35                 case I40E_DEV_ID_QSFP_C:
  36                 case I40E_DEV_ID_10G_BASE_T:
  37                 case I40E_DEV_ID_10G_BASE_T4:
  38                 case I40E_DEV_ID_10G_BASE_T_BC:
  39                 case I40E_DEV_ID_10G_B:
  40                 case I40E_DEV_ID_10G_SFP:
  41                 case I40E_DEV_ID_20G_KR2:
  42                 case I40E_DEV_ID_20G_KR2_A:
  43                 case I40E_DEV_ID_25G_B:
  44                 case I40E_DEV_ID_25G_SFP28:
  45                 case I40E_DEV_ID_X710_N3000:
  46                 case I40E_DEV_ID_XXV710_N3000:
  47                         hw->mac.type = I40E_MAC_XL710;
  48                         break;
  49 #ifdef X722_A0_SUPPORT
  50                 case I40E_DEV_ID_X722_A0:
  51 #endif
  52                 case I40E_DEV_ID_KX_X722:
  53                 case I40E_DEV_ID_QSFP_X722:
  54                 case I40E_DEV_ID_SFP_X722:
  55                 case I40E_DEV_ID_1G_BASE_T_X722:
  56                 case I40E_DEV_ID_10G_BASE_T_X722:
  57                 case I40E_DEV_ID_SFP_I_X722:
  58                         hw->mac.type = I40E_MAC_X722;
  59                         break;
  60 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  61                 case I40E_DEV_ID_X722_VF:
  62 #ifdef X722_A0_SUPPORT
  63                 case I40E_DEV_ID_X722_A0_VF:
  64 #endif
  65                         hw->mac.type = I40E_MAC_X722_VF;
  66                         break;
  67 #endif /* INTEGRATED_VF || VF_DRIVER */
  68 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  69                 case I40E_DEV_ID_VF:
  70                 case I40E_DEV_ID_VF_HV:
  71                 case I40E_DEV_ID_ADAPTIVE_VF:
  72                         hw->mac.type = I40E_MAC_VF;
  73                         break;
  74 #endif
  75                 default:
  76                         hw->mac.type = I40E_MAC_GENERIC;
  77                         break;
  78                 }
  79         } else {
  80                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  81         }
  82
  83         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  84                   hw->mac.type, status);
  85         return status;
  86 }
  87
  88 /**
  89  * i40e_aq_str - convert AQ err code to a string
  90  * @hw: pointer to the HW structure
  91  * @aq_err: the AQ error code to convert
  92  **/
  93 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  94 {
  95         switch (aq_err) {
  96         case I40E_AQ_RC_OK:
  97                 return "OK";
  98         case I40E_AQ_RC_EPERM:
  99                 return "I40E_AQ_RC_EPERM";
 100         case I40E_AQ_RC_ENOENT:
 101                 return "I40E_AQ_RC_ENOENT";
 102         case I40E_AQ_RC_ESRCH:
 103                 return "I40E_AQ_RC_ESRCH";
 104         case I40E_AQ_RC_EINTR:
 105                 return "I40E_AQ_RC_EINTR";
 106         case I40E_AQ_RC_EIO:
 107                 return "I40E_AQ_RC_EIO";
 108         case I40E_AQ_RC_ENXIO:
 109                 return "I40E_AQ_RC_ENXIO";
 110         case I40E_AQ_RC_E2BIG:
 111                 return "I40E_AQ_RC_E2BIG";
 112         case I40E_AQ_RC_EAGAIN:
 113                 return "I40E_AQ_RC_EAGAIN";
 114         case I40E_AQ_RC_ENOMEM:
 115                 return "I40E_AQ_RC_ENOMEM";
 116         case I40E_AQ_RC_EACCES:
 117                 return "I40E_AQ_RC_EACCES";
 118         case I40E_AQ_RC_EFAULT:
 119                 return "I40E_AQ_RC_EFAULT";
 120         case I40E_AQ_RC_EBUSY:
 121                 return "I40E_AQ_RC_EBUSY";
 122         case I40E_AQ_RC_EEXIST:
 123                 return "I40E_AQ_RC_EEXIST";
 124         case I40E_AQ_RC_EINVAL:
 125                 return "I40E_AQ_RC_EINVAL";
 126         case I40E_AQ_RC_ENOTTY:
 127                 return "I40E_AQ_RC_ENOTTY";
 128         case I40E_AQ_RC_ENOSPC:
 129                 return "I40E_AQ_RC_ENOSPC";
 130         case I40E_AQ_RC_ENOSYS:
 131                 return "I40E_AQ_RC_ENOSYS";
 132         case I40E_AQ_RC_ERANGE:
 133                 return "I40E_AQ_RC_ERANGE";
 134         case I40E_AQ_RC_EFLUSHED:
 135                 return "I40E_AQ_RC_EFLUSHED";
 136         case I40E_AQ_RC_BAD_ADDR:
 137                 return "I40E_AQ_RC_BAD_ADDR";
 138         case I40E_AQ_RC_EMODE:
 139                 return "I40E_AQ_RC_EMODE";
 140         case I40E_AQ_RC_EFBIG:
 141                 return "I40E_AQ_RC_EFBIG";
 142         }
 143
 144         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 145         return hw->err_str;
 146 }
 147
 148 /**
 149  * i40e_stat_str - convert status err code to a string
 150  * @hw: pointer to the HW structure
 151  * @stat_err: the status error code to convert
 152  **/
 153 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 154 {
 155         switch (stat_err) {
 156         case I40E_SUCCESS:
 157                 return "OK";
 158         case I40E_ERR_NVM:
 159                 return "I40E_ERR_NVM";
 160         case I40E_ERR_NVM_CHECKSUM:
 161                 return "I40E_ERR_NVM_CHECKSUM";
 162         case I40E_ERR_PHY:
 163                 return "I40E_ERR_PHY";
 164         case I40E_ERR_CONFIG:
 165                 return "I40E_ERR_CONFIG";
 166         case I40E_ERR_PARAM:
 167                 return "I40E_ERR_PARAM";
 168         case I40E_ERR_MAC_TYPE:
 169                 return "I40E_ERR_MAC_TYPE";
 170         case I40E_ERR_UNKNOWN_PHY:
 171                 return "I40E_ERR_UNKNOWN_PHY";
 172         case I40E_ERR_LINK_SETUP:
 173                 return "I40E_ERR_LINK_SETUP";
 174         case I40E_ERR_ADAPTER_STOPPED:
 175                 return "I40E_ERR_ADAPTER_STOPPED";
 176         case I40E_ERR_INVALID_MAC_ADDR:
 177                 return "I40E_ERR_INVALID_MAC_ADDR";
 178         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 179                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 180         case I40E_ERR_MASTER_REQUESTS_PENDING:
 181                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 182         case I40E_ERR_INVALID_LINK_SETTINGS:
 183                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 184         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 185                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 186         case I40E_ERR_RESET_FAILED:
 187                 return "I40E_ERR_RESET_FAILED";
 188         case I40E_ERR_SWFW_SYNC:
 189                 return "I40E_ERR_SWFW_SYNC";
 190         case I40E_ERR_NO_AVAILABLE_VSI:
 191                 return "I40E_ERR_NO_AVAILABLE_VSI";
 192         case I40E_ERR_NO_MEMORY:
 193                 return "I40E_ERR_NO_MEMORY";
 194         case I40E_ERR_BAD_PTR:
 195                 return "I40E_ERR_BAD_PTR";
 196         case I40E_ERR_RING_FULL:
 197                 return "I40E_ERR_RING_FULL";
 198         case I40E_ERR_INVALID_PD_ID:
 199                 return "I40E_ERR_INVALID_PD_ID";
 200         case I40E_ERR_INVALID_QP_ID:
 201                 return "I40E_ERR_INVALID_QP_ID";
 202         case I40E_ERR_INVALID_CQ_ID:
 203                 return "I40E_ERR_INVALID_CQ_ID";
 204         case I40E_ERR_INVALID_CEQ_ID:
 205                 return "I40E_ERR_INVALID_CEQ_ID";
 206         case I40E_ERR_INVALID_AEQ_ID:
 207                 return "I40E_ERR_INVALID_AEQ_ID";
 208         case I40E_ERR_INVALID_SIZE:
 209                 return "I40E_ERR_INVALID_SIZE";
 210         case I40E_ERR_INVALID_ARP_INDEX:
 211                 return "I40E_ERR_INVALID_ARP_INDEX";
 212         case I40E_ERR_INVALID_FPM_FUNC_ID:
 213                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 214         case I40E_ERR_QP_INVALID_MSG_SIZE:
 215                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 216         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 217                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 218         case I40E_ERR_INVALID_FRAG_COUNT:
 219                 return "I40E_ERR_INVALID_FRAG_COUNT";
 220         case I40E_ERR_QUEUE_EMPTY:
 221                 return "I40E_ERR_QUEUE_EMPTY";
 222         case I40E_ERR_INVALID_ALIGNMENT:
 223                 return "I40E_ERR_INVALID_ALIGNMENT";
 224         case I40E_ERR_FLUSHED_QUEUE:
 225                 return "I40E_ERR_FLUSHED_QUEUE";
 226         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 227                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 228         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 229                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 230         case I40E_ERR_TIMEOUT:
 231                 return "I40E_ERR_TIMEOUT";
 232         case I40E_ERR_OPCODE_MISMATCH:
 233                 return "I40E_ERR_OPCODE_MISMATCH";
 234         case I40E_ERR_CQP_COMPL_ERROR:
 235                 return "I40E_ERR_CQP_COMPL_ERROR";
 236         case I40E_ERR_INVALID_VF_ID:
 237                 return "I40E_ERR_INVALID_VF_ID";
 238         case I40E_ERR_INVALID_HMCFN_ID:
 239                 return "I40E_ERR_INVALID_HMCFN_ID";
 240         case I40E_ERR_BACKING_PAGE_ERROR:
 241                 return "I40E_ERR_BACKING_PAGE_ERROR";
 242         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 243                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 244         case I40E_ERR_INVALID_PBLE_INDEX:
 245                 return "I40E_ERR_INVALID_PBLE_INDEX";
 246         case I40E_ERR_INVALID_SD_INDEX:
 247                 return "I40E_ERR_INVALID_SD_INDEX";
 248         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 249                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 250         case I40E_ERR_INVALID_SD_TYPE:
 251                 return "I40E_ERR_INVALID_SD_TYPE";
 252         case I40E_ERR_MEMCPY_FAILED:
 253                 return "I40E_ERR_MEMCPY_FAILED";
 254         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 255                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 256         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 257                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 258         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 259                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 260         case I40E_ERR_SRQ_ENABLED:
 261                 return "I40E_ERR_SRQ_ENABLED";
 262         case I40E_ERR_ADMIN_QUEUE_ERROR:
 263                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 264         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 265                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 266         case I40E_ERR_BUF_TOO_SHORT:
 267                 return "I40E_ERR_BUF_TOO_SHORT";
 268         case I40E_ERR_ADMIN_QUEUE_FULL:
 269                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 270         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 271                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 272         case I40E_ERR_BAD_IWARP_CQE:
 273                 return "I40E_ERR_BAD_IWARP_CQE";
 274         case I40E_ERR_NVM_BLANK_MODE:
 275                 return "I40E_ERR_NVM_BLANK_MODE";
 276         case I40E_ERR_NOT_IMPLEMENTED:
 277                 return "I40E_ERR_NOT_IMPLEMENTED";
 278         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 279                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 280         case I40E_ERR_DIAG_TEST_FAILED:
 281                 return "I40E_ERR_DIAG_TEST_FAILED";
 282         case I40E_ERR_NOT_READY:
 283                 return "I40E_ERR_NOT_READY";
 284         case I40E_NOT_SUPPORTED:
 285                 return "I40E_NOT_SUPPORTED";
 286         case I40E_ERR_FIRMWARE_API_VERSION:
 287                 return "I40E_ERR_FIRMWARE_API_VERSION";
 288         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 289                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 290         }
 291
 292         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 293         return hw->err_str;
 294 }
 295
 296 /**
 297  * i40e_debug_aq
 298  * @hw: debug mask related to admin queue
 299  * @mask: debug mask
 300  * @desc: pointer to admin queue descriptor
 301  * @buffer: pointer to command buffer
 302  * @buf_len: max length of buffer
 303  *
 304  * Dumps debug log about adminq command with descriptor contents.
 305  **/
 306 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 307                    void *buffer, u16 buf_len)
 308 {
 309         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 310         u8 *buf = (u8 *)buffer;
 311         u16 len;
 312         u16 i = 0;
 313
 314         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 315                 return;
 316
 317         len = LE16_TO_CPU(aq_desc->datalen);
 318
 319         i40e_debug(hw, mask,
 320                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 321                    LE16_TO_CPU(aq_desc->opcode),
 322                    LE16_TO_CPU(aq_desc->flags),
 323                    LE16_TO_CPU(aq_desc->datalen),
 324                    LE16_TO_CPU(aq_desc->retval));
 325         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 326                    LE32_TO_CPU(aq_desc->cookie_high),
 327                    LE32_TO_CPU(aq_desc->cookie_low));
 328         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 329                    LE32_TO_CPU(aq_desc->params.internal.param0),
 330                    LE32_TO_CPU(aq_desc->params.internal.param1));
 331         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 332                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 333                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 334
 335         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 336                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 337                 if (buf_len < len)
 338                         len = buf_len;
 339                 /* write the full 16-byte chunks */
 340                 for (i = 0; i < (len - 16); i += 16)
 341                         i40e_debug(hw, mask,
 342                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 343                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 344                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 345                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 346                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 347                 /* the most we could have left is 16 bytes, pad with zeros */
 348                 if (i < len) {
 349                         char d_buf[16];
 350                         int j, i_sav;
 351
 352                         i_sav = i;
 353                         memset(d_buf, 0, sizeof(d_buf));
 354                         for (j = 0; i < len; j++, i++)
 355                                 d_buf[j] = buf[i];
 356                         i40e_debug(hw, mask,
 357                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 358                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 359                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 360                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 361                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 362                 }
 363         }
 364 }
 365
 366 /**
 367  * i40e_check_asq_alive
 368  * @hw: pointer to the hw struct
 369  *
 370  * Returns true if Queue is enabled else false.
 371  **/
 372 bool i40e_check_asq_alive(struct i40e_hw *hw)
 373 {
 374         if (hw->aq.asq.len)
 375 #ifdef PF_DRIVER
 376 #ifdef INTEGRATED_VF
 377                 if (!i40e_is_vf(hw))
 378                         return !!(rd32(hw, hw->aq.asq.len) &
 379                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 380 #else
 381                 return !!(rd32(hw, hw->aq.asq.len) &
 382                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 383 #endif /* INTEGRATED_VF */
 384 #endif /* PF_DRIVER */
 385 #ifdef VF_DRIVER
 386 #ifdef INTEGRATED_VF
 387                 if (i40e_is_vf(hw))
 388                         return !!(rd32(hw, hw->aq.asq.len) &
 389                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 390 #else
 391                 return !!(rd32(hw, hw->aq.asq.len) &
 392                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 393 #endif /* INTEGRATED_VF */
 394 #endif /* VF_DRIVER */
 395         return false;
 396 }
 397
 398 /**
 399  * i40e_aq_queue_shutdown
 400  * @hw: pointer to the hw struct
 401  * @unloading: is the driver unloading itself
 402  *
 403  * Tell the Firmware that we're shutting down the AdminQ and whether
 404  * or not the driver is unloading as well.
 405  **/
 406 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 407                                              bool unloading)
 408 {
 409         struct i40e_aq_desc desc;
 410         struct i40e_aqc_queue_shutdown *cmd =
 411                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 412         enum i40e_status_code status;
 413
 414         i40e_fill_default_direct_cmd_desc(&desc,
 415                                           i40e_aqc_opc_queue_shutdown);
 416
 417         if (unloading)
 418                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 419         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 420
 421         return status;
 422 }
 423
 424 /**
 425  * i40e_aq_get_set_rss_lut
 426  * @hw: pointer to the hardware structure
 427  * @vsi_id: vsi fw index
 428  * @pf_lut: for PF table set true, for VSI table set false
 429  * @lut: pointer to the lut buffer provided by the caller
 430  * @lut_size: size of the lut buffer
 431  * @set: set true to set the table, false to get the table
 432  *
 433  * Internal function to get or set RSS look up table
 434  **/
 435 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 436                                                      u16 vsi_id, bool pf_lut,
 437                                                      u8 *lut, u16 lut_size,
 438                                                      bool set)
 439 {
 440         enum i40e_status_code status;
 441         struct i40e_aq_desc desc;
 442         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 443                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 444
 445         if (set)
 446                 i40e_fill_default_direct_cmd_desc(&desc,
 447                                                   i40e_aqc_opc_set_rss_lut);
 448         else
 449                 i40e_fill_default_direct_cmd_desc(&desc,
 450                                                   i40e_aqc_opc_get_rss_lut);
 451
 452         /* Indirect command */
 453         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 454         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 455
 456         cmd_resp->vsi_id =
 457                         CPU_TO_LE16((u16)((vsi_id <<
 458                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 459                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 460         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 461
 462         if (pf_lut)
 463                 cmd_resp->flags |= CPU_TO_LE16((u16)
 464                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 465                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 466                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 467         else
 468                 cmd_resp->flags |= CPU_TO_LE16((u16)
 469                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 470                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 471                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 472
 473         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 474
 475         return status;
 476 }
 477
 478 /**
 479  * i40e_aq_get_rss_lut
 480  * @hw: pointer to the hardware structure
 481  * @vsi_id: vsi fw index
 482  * @pf_lut: for PF table set true, for VSI table set false
 483  * @lut: pointer to the lut buffer provided by the caller
 484  * @lut_size: size of the lut buffer
 485  *
 486  * get the RSS lookup table, PF or VSI type
 487  **/
 488 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 489                                           bool pf_lut, u8 *lut, u16 lut_size)
 490 {
 491         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 492                                        false);
 493 }
 494
 495 /**
 496  * i40e_aq_set_rss_lut
 497  * @hw: pointer to the hardware structure
 498  * @vsi_id: vsi fw index
 499  * @pf_lut: for PF table set true, for VSI table set false
 500  * @lut: pointer to the lut buffer provided by the caller
 501  * @lut_size: size of the lut buffer
 502  *
 503  * set the RSS lookup table, PF or VSI type
 504  **/
 505 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 506                                           bool pf_lut, u8 *lut, u16 lut_size)
 507 {
 508         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 509 }
 510
 511 /**
 512  * i40e_aq_get_set_rss_key
 513  * @hw: pointer to the hw struct
 514  * @vsi_id: vsi fw index
 515  * @key: pointer to key info struct
 516  * @set: set true to set the key, false to get the key
 517  *
 518  * get the RSS key per VSI
 519  **/
 520 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 521                                       u16 vsi_id,
 522                                       struct i40e_aqc_get_set_rss_key_data *key,
 523                                       bool set)
 524 {
 525         enum i40e_status_code status;
 526         struct i40e_aq_desc desc;
 527         struct i40e_aqc_get_set_rss_key *cmd_resp =
 528                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 529         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 530
 531         if (set)
 532                 i40e_fill_default_direct_cmd_desc(&desc,
 533                                                   i40e_aqc_opc_set_rss_key);
 534         else
 535                 i40e_fill_default_direct_cmd_desc(&desc,
 536                                                   i40e_aqc_opc_get_rss_key);
 537
 538         /* Indirect command */
 539         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 540         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 541
 542         cmd_resp->vsi_id =
 543                         CPU_TO_LE16((u16)((vsi_id <<
 544                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 545                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 546         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 547
 548         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 549
 550         return status;
 551 }
 552
 553 /**
 554  * i40e_aq_get_rss_key
 555  * @hw: pointer to the hw struct
 556  * @vsi_id: vsi fw index
 557  * @key: pointer to key info struct
 558  *
 559  **/
 560 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 561                                       u16 vsi_id,
 562                                       struct i40e_aqc_get_set_rss_key_data *key)
 563 {
 564         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 565 }
 566
 567 /**
 568  * i40e_aq_set_rss_key
 569  * @hw: pointer to the hw struct
 570  * @vsi_id: vsi fw index
 571  * @key: pointer to key info struct
 572  *
 573  * set the RSS key per VSI
 574  **/
 575 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 576                                       u16 vsi_id,
 577                                       struct i40e_aqc_get_set_rss_key_data *key)
 578 {
 579         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 580 }
 581
 582 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 583  * hardware to a bit-field that can be used by SW to more easily determine the
 584  * packet type.
 585  *
 586  * Macros are used to shorten the table lines and make this table human
 587  * readable.
 588  *
 589  * We store the PTYPE in the top byte of the bit field - this is just so that
 590  * we can check that the table doesn't have a row missing, as the index into
 591  * the table should be the PTYPE.
 592  *
 593  * Typical work flow:
 594  *
 595  * IF NOT i40e_ptype_lookup[ptype].known
 596  * THEN
 597  *      Packet is unknown
 598  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 599  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 600  * ELSE
 601  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 602  * ENDIF
 603  */
 604
 605 /* macro to make the table lines short */
 606 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 607         {       PTYPE, \
 608                 1, \
 609                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 610                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 611                 I40E_RX_PTYPE_##OUTER_FRAG, \
 612                 I40E_RX_PTYPE_TUNNEL_##T, \
 613                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 614                 I40E_RX_PTYPE_##TEF, \
 615                 I40E_RX_PTYPE_INNER_PROT_##I, \
 616                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 617
 618 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 619                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 620
 621 /* shorter macros makes the table fit but are terse */
 622 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 623 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 624 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 625
 626 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 627 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 628         /* L2 Packet types */
 629         I40E_PTT_UNUSED_ENTRY(0),
 630         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 631         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 632         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 633         I40E_PTT_UNUSED_ENTRY(4),
 634         I40E_PTT_UNUSED_ENTRY(5),
 635         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 636         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 637         I40E_PTT_UNUSED_ENTRY(8),
 638         I40E_PTT_UNUSED_ENTRY(9),
 639         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 640         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 641         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 642         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 651
 652         /* Non Tunneled IPv4 */
 653         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 654         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 655         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 656         I40E_PTT_UNUSED_ENTRY(25),
 657         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 658         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 659         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 660
 661         /* IPv4 --> IPv4 */
 662         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 663         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 664         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 665         I40E_PTT_UNUSED_ENTRY(32),
 666         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 667         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 668         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 669
 670         /* IPv4 --> IPv6 */
 671         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 672         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 673         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 674         I40E_PTT_UNUSED_ENTRY(39),
 675         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 676         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 677         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 678
 679         /* IPv4 --> GRE/NAT */
 680         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 681
 682         /* IPv4 --> GRE/NAT --> IPv4 */
 683         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 684         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 685         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 686         I40E_PTT_UNUSED_ENTRY(47),
 687         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 688         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 689         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 690
 691         /* IPv4 --> GRE/NAT --> IPv6 */
 692         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 693         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 694         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 695         I40E_PTT_UNUSED_ENTRY(54),
 696         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 697         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 698         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 699
 700         /* IPv4 --> GRE/NAT --> MAC */
 701         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 702
 703         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 704         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 705         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 706         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 707         I40E_PTT_UNUSED_ENTRY(62),
 708         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 709         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 710         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 711
 712         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 713         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 714         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 715         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 716         I40E_PTT_UNUSED_ENTRY(69),
 717         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 718         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 719         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 720
 721         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 722         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 723
 724         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 725         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 726         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 727         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 728         I40E_PTT_UNUSED_ENTRY(77),
 729         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 730         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 731         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 732
 733         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 734         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 735         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 736         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 737         I40E_PTT_UNUSED_ENTRY(84),
 738         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 739         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 740         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 741
 742         /* Non Tunneled IPv6 */
 743         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 744         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 745         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 746         I40E_PTT_UNUSED_ENTRY(91),
 747         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 748         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 749         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 750
 751         /* IPv6 --> IPv4 */
 752         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 753         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 754         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 755         I40E_PTT_UNUSED_ENTRY(98),
 756         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 757         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 758         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 759
 760         /* IPv6 --> IPv6 */
 761         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 762         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 763         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 764         I40E_PTT_UNUSED_ENTRY(105),
 765         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 766         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 767         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 768
 769         /* IPv6 --> GRE/NAT */
 770         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 771
 772         /* IPv6 --> GRE/NAT -> IPv4 */
 773         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 774         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 775         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 776         I40E_PTT_UNUSED_ENTRY(113),
 777         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 778         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 779         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 780
 781         /* IPv6 --> GRE/NAT -> IPv6 */
 782         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 783         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 784         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 785         I40E_PTT_UNUSED_ENTRY(120),
 786         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 787         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 788         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 789
 790         /* IPv6 --> GRE/NAT -> MAC */
 791         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 792
 793         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 794         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 795         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 796         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 797         I40E_PTT_UNUSED_ENTRY(128),
 798         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 799         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 800         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 801
 802         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 803         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 804         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 805         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 806         I40E_PTT_UNUSED_ENTRY(135),
 807         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 808         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 809         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 810
 811         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 812         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 813
 814         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 815         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 816         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 817         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 818         I40E_PTT_UNUSED_ENTRY(143),
 819         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 820         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 821         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 822
 823         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 824         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 825         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 826         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 827         I40E_PTT_UNUSED_ENTRY(150),
 828         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 829         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 830         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 831
 832         /* unused entries */
 833         I40E_PTT_UNUSED_ENTRY(154),
 834         I40E_PTT_UNUSED_ENTRY(155),
 835         I40E_PTT_UNUSED_ENTRY(156),
 836         I40E_PTT_UNUSED_ENTRY(157),
 837         I40E_PTT_UNUSED_ENTRY(158),
 838         I40E_PTT_UNUSED_ENTRY(159),
 839
 840         I40E_PTT_UNUSED_ENTRY(160),
 841         I40E_PTT_UNUSED_ENTRY(161),
 842         I40E_PTT_UNUSED_ENTRY(162),
 843         I40E_PTT_UNUSED_ENTRY(163),
 844         I40E_PTT_UNUSED_ENTRY(164),
 845         I40E_PTT_UNUSED_ENTRY(165),
 846         I40E_PTT_UNUSED_ENTRY(166),
 847         I40E_PTT_UNUSED_ENTRY(167),
 848         I40E_PTT_UNUSED_ENTRY(168),
 849         I40E_PTT_UNUSED_ENTRY(169),
 850
 851         I40E_PTT_UNUSED_ENTRY(170),
 852         I40E_PTT_UNUSED_ENTRY(171),
 853         I40E_PTT_UNUSED_ENTRY(172),
 854         I40E_PTT_UNUSED_ENTRY(173),
 855         I40E_PTT_UNUSED_ENTRY(174),
 856         I40E_PTT_UNUSED_ENTRY(175),
 857         I40E_PTT_UNUSED_ENTRY(176),
 858         I40E_PTT_UNUSED_ENTRY(177),
 859         I40E_PTT_UNUSED_ENTRY(178),
 860         I40E_PTT_UNUSED_ENTRY(179),
 861
 862         I40E_PTT_UNUSED_ENTRY(180),
 863         I40E_PTT_UNUSED_ENTRY(181),
 864         I40E_PTT_UNUSED_ENTRY(182),
 865         I40E_PTT_UNUSED_ENTRY(183),
 866         I40E_PTT_UNUSED_ENTRY(184),
 867         I40E_PTT_UNUSED_ENTRY(185),
 868         I40E_PTT_UNUSED_ENTRY(186),
 869         I40E_PTT_UNUSED_ENTRY(187),
 870         I40E_PTT_UNUSED_ENTRY(188),
 871         I40E_PTT_UNUSED_ENTRY(189),
 872
 873         I40E_PTT_UNUSED_ENTRY(190),
 874         I40E_PTT_UNUSED_ENTRY(191),
 875         I40E_PTT_UNUSED_ENTRY(192),
 876         I40E_PTT_UNUSED_ENTRY(193),
 877         I40E_PTT_UNUSED_ENTRY(194),
 878         I40E_PTT_UNUSED_ENTRY(195),
 879         I40E_PTT_UNUSED_ENTRY(196),
 880         I40E_PTT_UNUSED_ENTRY(197),
 881         I40E_PTT_UNUSED_ENTRY(198),
 882         I40E_PTT_UNUSED_ENTRY(199),
 883
 884         I40E_PTT_UNUSED_ENTRY(200),
 885         I40E_PTT_UNUSED_ENTRY(201),
 886         I40E_PTT_UNUSED_ENTRY(202),
 887         I40E_PTT_UNUSED_ENTRY(203),
 888         I40E_PTT_UNUSED_ENTRY(204),
 889         I40E_PTT_UNUSED_ENTRY(205),
 890         I40E_PTT_UNUSED_ENTRY(206),
 891         I40E_PTT_UNUSED_ENTRY(207),
 892         I40E_PTT_UNUSED_ENTRY(208),
 893         I40E_PTT_UNUSED_ENTRY(209),
 894
 895         I40E_PTT_UNUSED_ENTRY(210),
 896         I40E_PTT_UNUSED_ENTRY(211),
 897         I40E_PTT_UNUSED_ENTRY(212),
 898         I40E_PTT_UNUSED_ENTRY(213),
 899         I40E_PTT_UNUSED_ENTRY(214),
 900         I40E_PTT_UNUSED_ENTRY(215),
 901         I40E_PTT_UNUSED_ENTRY(216),
 902         I40E_PTT_UNUSED_ENTRY(217),
 903         I40E_PTT_UNUSED_ENTRY(218),
 904         I40E_PTT_UNUSED_ENTRY(219),
 905
 906         I40E_PTT_UNUSED_ENTRY(220),
 907         I40E_PTT_UNUSED_ENTRY(221),
 908         I40E_PTT_UNUSED_ENTRY(222),
 909         I40E_PTT_UNUSED_ENTRY(223),
 910         I40E_PTT_UNUSED_ENTRY(224),
 911         I40E_PTT_UNUSED_ENTRY(225),
 912         I40E_PTT_UNUSED_ENTRY(226),
 913         I40E_PTT_UNUSED_ENTRY(227),
 914         I40E_PTT_UNUSED_ENTRY(228),
 915         I40E_PTT_UNUSED_ENTRY(229),
 916
 917         I40E_PTT_UNUSED_ENTRY(230),
 918         I40E_PTT_UNUSED_ENTRY(231),
 919         I40E_PTT_UNUSED_ENTRY(232),
 920         I40E_PTT_UNUSED_ENTRY(233),
 921         I40E_PTT_UNUSED_ENTRY(234),
 922         I40E_PTT_UNUSED_ENTRY(235),
 923         I40E_PTT_UNUSED_ENTRY(236),
 924         I40E_PTT_UNUSED_ENTRY(237),
 925         I40E_PTT_UNUSED_ENTRY(238),
 926         I40E_PTT_UNUSED_ENTRY(239),
 927
 928         I40E_PTT_UNUSED_ENTRY(240),
 929         I40E_PTT_UNUSED_ENTRY(241),
 930         I40E_PTT_UNUSED_ENTRY(242),
 931         I40E_PTT_UNUSED_ENTRY(243),
 932         I40E_PTT_UNUSED_ENTRY(244),
 933         I40E_PTT_UNUSED_ENTRY(245),
 934         I40E_PTT_UNUSED_ENTRY(246),
 935         I40E_PTT_UNUSED_ENTRY(247),
 936         I40E_PTT_UNUSED_ENTRY(248),
 937         I40E_PTT_UNUSED_ENTRY(249),
 938
 939         I40E_PTT_UNUSED_ENTRY(250),
 940         I40E_PTT_UNUSED_ENTRY(251),
 941         I40E_PTT_UNUSED_ENTRY(252),
 942         I40E_PTT_UNUSED_ENTRY(253),
 943         I40E_PTT_UNUSED_ENTRY(254),
 944         I40E_PTT_UNUSED_ENTRY(255)
 945 };
 946
 947
 948 /**
 949  * i40e_validate_mac_addr - Validate unicast MAC address
 950  * @mac_addr: pointer to MAC address
 951  *
 952  * Tests a MAC address to ensure it is a valid Individual Address
 953  **/
 954 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 955 {
 956         enum i40e_status_code status = I40E_SUCCESS;
 957
 958         DEBUGFUNC("i40e_validate_mac_addr");
 959
 960         /* Broadcast addresses ARE multicast addresses
 961          * Make sure it is not a multicast address
 962          * Reject the zero address
 963          */
 964         if (I40E_IS_MULTICAST(mac_addr) ||
 965             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 966               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 967                 status = I40E_ERR_INVALID_MAC_ADDR;
 968
 969         return status;
 970 }
 971 #ifdef PF_DRIVER
 972
 973 /**
 974  * i40e_init_shared_code - Initialize the shared code
 975  * @hw: pointer to hardware structure
 976  *
 977  * This assigns the MAC type and PHY code and inits the NVM.
 978  * Does not touch the hardware. This function must be called prior to any
 979  * other function in the shared code. The i40e_hw structure should be
 980  * memset to 0 prior to calling this function.  The following fields in
 981  * hw structure should be filled in prior to calling this function:
 982  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 983  * subsystem_vendor_id, and revision_id
 984  **/
 985 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 986 {
 987         enum i40e_status_code status = I40E_SUCCESS;
 988         u32 port, ari, func_rid;
 989
 990         DEBUGFUNC("i40e_init_shared_code");
 991
 992         i40e_set_mac_type(hw);
 993
 994         switch (hw->mac.type) {
 995         case I40E_MAC_XL710:
 996         case I40E_MAC_X722:
 997                 break;
 998         default:
 999                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1000         }
1001
1002         hw->phy.get_link_info = true;
1003
1004         /* Determine port number and PF number*/
1005         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1006                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1007         hw->port = (u8)port;
1008         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1009                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1010         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1011         if (ari)
1012                 hw->pf_id = (u8)(func_rid & 0xff);
1013         else
1014                 hw->pf_id = (u8)(func_rid & 0x7);
1015
1016         if (hw->mac.type == I40E_MAC_X722)
1017                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1018                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1019         /* NVMUpdate features structure initialization */
1020         hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1021         hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1022         hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1023         i40e_memset(hw->nvmupd_features.features, 0x0,
1024                     I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1025                     sizeof(*hw->nvmupd_features.features),
1026                     I40E_NONDMA_MEM);
1027
1028         /* No features supported at the moment */
1029         hw->nvmupd_features.features[0] = 0;
1030
1031         status = i40e_init_nvm(hw);
1032         return status;
1033 }
1034
1035 /**
1036  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1037  * @hw: pointer to the hw struct
1038  * @flags: a return indicator of what addresses were added to the addr store
1039  * @addrs: the requestor's mac addr store
1040  * @cmd_details: pointer to command details structure or NULL
1041  **/
1042 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1043                                    u16 *flags,
1044                                    struct i40e_aqc_mac_address_read_data *addrs,
1045                                    struct i40e_asq_cmd_details *cmd_details)
1046 {
1047         struct i40e_aq_desc desc;
1048         struct i40e_aqc_mac_address_read *cmd_data =
1049                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1050         enum i40e_status_code status;
1051
1052         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1053         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1054
1055         status = i40e_asq_send_command(hw, &desc, addrs,
1056                                        sizeof(*addrs), cmd_details);
1057         *flags = LE16_TO_CPU(cmd_data->command_flags);
1058
1059         return status;
1060 }
1061
1062 /**
1063  * i40e_aq_mac_address_write - Change the MAC addresses
1064  * @hw: pointer to the hw struct
1065  * @flags: indicates which MAC to be written
1066  * @mac_addr: address to write
1067  * @cmd_details: pointer to command details structure or NULL
1068  **/
1069 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1070                                     u16 flags, u8 *mac_addr,
1071                                     struct i40e_asq_cmd_details *cmd_details)
1072 {
1073         struct i40e_aq_desc desc;
1074         struct i40e_aqc_mac_address_write *cmd_data =
1075                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1076         enum i40e_status_code status;
1077
1078         i40e_fill_default_direct_cmd_desc(&desc,
1079                                           i40e_aqc_opc_mac_address_write);
1080         cmd_data->command_flags = CPU_TO_LE16(flags);
1081         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1082         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1083                                         ((u32)mac_addr[3] << 16) |
1084                                         ((u32)mac_addr[4] << 8) |
1085                                         mac_addr[5]);
1086
1087         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1088
1089         return status;
1090 }
1091
1092 /**
1093  * i40e_get_mac_addr - get MAC address
1094  * @hw: pointer to the HW structure
1095  * @mac_addr: pointer to MAC address
1096  *
1097  * Reads the adapter's MAC address from register
1098  **/
1099 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1100 {
1101         struct i40e_aqc_mac_address_read_data addrs;
1102         enum i40e_status_code status;
1103         u16 flags = 0;
1104
1105         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1106
1107         if (flags & I40E_AQC_LAN_ADDR_VALID)
1108                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1109                         I40E_NONDMA_TO_NONDMA);
1110
1111         return status;
1112 }
1113
1114 /**
1115  * i40e_get_port_mac_addr - get Port MAC address
1116  * @hw: pointer to the HW structure
1117  * @mac_addr: pointer to Port MAC address
1118  *
1119  * Reads the adapter's Port MAC address
1120  **/
1121 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1122 {
1123         struct i40e_aqc_mac_address_read_data addrs;
1124         enum i40e_status_code status;
1125         u16 flags = 0;
1126
1127         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1128         if (status)
1129                 return status;
1130
1131         if (flags & I40E_AQC_PORT_ADDR_VALID)
1132                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1133                         I40E_NONDMA_TO_NONDMA);
1134         else
1135                 status = I40E_ERR_INVALID_MAC_ADDR;
1136
1137         return status;
1138 }
1139
1140 /**
1141  * i40e_pre_tx_queue_cfg - pre tx queue configure
1142  * @hw: pointer to the HW structure
1143  * @queue: target pf queue index
1144  * @enable: state change request
1145  *
1146  * Handles hw requirement to indicate intention to enable
1147  * or disable target queue.
1148  **/
1149 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1150 {
1151         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1152         u32 reg_block = 0;
1153         u32 reg_val;
1154
1155         if (abs_queue_idx >= 128) {
1156                 reg_block = abs_queue_idx / 128;
1157                 abs_queue_idx %= 128;
1158         }
1159
1160         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1161         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1162         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1163
1164         if (enable)
1165                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1166         else
1167                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1168
1169         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1170 }
1171
1172 /**
1173  * i40e_get_san_mac_addr - get SAN MAC address
1174  * @hw: pointer to the HW structure
1175  * @mac_addr: pointer to SAN MAC address
1176  *
1177  * Reads the adapter's SAN MAC address from NVM
1178  **/
1179 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1180                                             u8 *mac_addr)
1181 {
1182         struct i40e_aqc_mac_address_read_data addrs;
1183         enum i40e_status_code status;
1184         u16 flags = 0;
1185
1186         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1187         if (status)
1188                 return status;
1189
1190         if (flags & I40E_AQC_SAN_ADDR_VALID)
1191                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1192                         I40E_NONDMA_TO_NONDMA);
1193         else
1194                 status = I40E_ERR_INVALID_MAC_ADDR;
1195
1196         return status;
1197 }
1198
1199 /**
1200  *  i40e_read_pba_string - Reads part number string from EEPROM
1201  *  @hw: pointer to hardware structure
1202  *  @pba_num: stores the part number string from the EEPROM
1203  *  @pba_num_size: part number string buffer length
1204  *
1205  *  Reads the part number string from the EEPROM.
1206  **/
1207 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1208                                             u32 pba_num_size)
1209 {
1210         enum i40e_status_code status = I40E_SUCCESS;
1211         u16 pba_word = 0;
1212         u16 pba_size = 0;
1213         u16 pba_ptr = 0;
1214         u16 i = 0;
1215
1216         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1217         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1218                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1219                 return status;
1220         }
1221
1222         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1223         if (status != I40E_SUCCESS) {
1224                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1225                 return status;
1226         }
1227
1228         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1229         if (status != I40E_SUCCESS) {
1230                 DEBUGOUT("Failed to read PBA Block size.\n");
1231                 return status;
1232         }
1233
1234         /* Subtract one to get PBA word count (PBA Size word is included in
1235          * total size)
1236          */
1237         pba_size--;
1238         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1239                 DEBUGOUT("Buffer to small for PBA data.\n");
1240                 return I40E_ERR_PARAM;
1241         }
1242
1243         for (i = 0; i < pba_size; i++) {
1244                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1245                 if (status != I40E_SUCCESS) {
1246                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1247                         return status;
1248                 }
1249
1250                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1251                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1252         }
1253         pba_num[(pba_size * 2)] = '\0';
1254
1255         return status;
1256 }
1257
1258 /**
1259  * i40e_get_media_type - Gets media type
1260  * @hw: pointer to the hardware structure
1261  **/
1262 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1263 {
1264         enum i40e_media_type media;
1265
1266         switch (hw->phy.link_info.phy_type) {
1267         case I40E_PHY_TYPE_10GBASE_SR:
1268         case I40E_PHY_TYPE_10GBASE_LR:
1269         case I40E_PHY_TYPE_1000BASE_SX:
1270         case I40E_PHY_TYPE_1000BASE_LX:
1271         case I40E_PHY_TYPE_40GBASE_SR4:
1272         case I40E_PHY_TYPE_40GBASE_LR4:
1273         case I40E_PHY_TYPE_25GBASE_LR:
1274         case I40E_PHY_TYPE_25GBASE_SR:
1275                 media = I40E_MEDIA_TYPE_FIBER;
1276                 break;
1277         case I40E_PHY_TYPE_100BASE_TX:
1278         case I40E_PHY_TYPE_1000BASE_T:
1279         case I40E_PHY_TYPE_2_5GBASE_T:
1280         case I40E_PHY_TYPE_5GBASE_T:
1281         case I40E_PHY_TYPE_10GBASE_T:
1282                 media = I40E_MEDIA_TYPE_BASET;
1283                 break;
1284         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1285         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1286         case I40E_PHY_TYPE_10GBASE_CR1:
1287         case I40E_PHY_TYPE_40GBASE_CR4:
1288         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1289         case I40E_PHY_TYPE_40GBASE_AOC:
1290         case I40E_PHY_TYPE_10GBASE_AOC:
1291         case I40E_PHY_TYPE_25GBASE_CR:
1292         case I40E_PHY_TYPE_25GBASE_AOC:
1293         case I40E_PHY_TYPE_25GBASE_ACC:
1294                 media = I40E_MEDIA_TYPE_DA;
1295                 break;
1296         case I40E_PHY_TYPE_1000BASE_KX:
1297         case I40E_PHY_TYPE_10GBASE_KX4:
1298         case I40E_PHY_TYPE_10GBASE_KR:
1299         case I40E_PHY_TYPE_40GBASE_KR4:
1300         case I40E_PHY_TYPE_20GBASE_KR2:
1301         case I40E_PHY_TYPE_25GBASE_KR:
1302                 media = I40E_MEDIA_TYPE_BACKPLANE;
1303                 break;
1304         case I40E_PHY_TYPE_SGMII:
1305         case I40E_PHY_TYPE_XAUI:
1306         case I40E_PHY_TYPE_XFI:
1307         case I40E_PHY_TYPE_XLAUI:
1308         case I40E_PHY_TYPE_XLPPI:
1309         default:
1310                 media = I40E_MEDIA_TYPE_UNKNOWN;
1311                 break;
1312         }
1313
1314         return media;
1315 }
1316
1317 /**
1318  * i40e_poll_globr - Poll for Global Reset completion
1319  * @hw: pointer to the hardware structure
1320  * @retry_limit: how many times to retry before failure
1321  **/
1322 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1323                                              u32 retry_limit)
1324 {
1325         u32 cnt, reg = 0;
1326
1327         for (cnt = 0; cnt < retry_limit; cnt++) {
1328                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1329                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1330                         return I40E_SUCCESS;
1331                 i40e_msec_delay(100);
1332         }
1333
1334         DEBUGOUT("Global reset failed.\n");
1335         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1336
1337         return I40E_ERR_RESET_FAILED;
1338 }
1339
1340 #define I40E_PF_RESET_WAIT_COUNT        200
1341 /**
1342  * i40e_pf_reset - Reset the PF
1343  * @hw: pointer to the hardware structure
1344  *
1345  * Assuming someone else has triggered a global reset,
1346  * assure the global reset is complete and then reset the PF
1347  **/
1348 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1349 {
1350         u32 cnt = 0;
1351         u32 cnt1 = 0;
1352         u32 reg = 0;
1353         u32 grst_del;
1354
1355         /* Poll for Global Reset steady state in case of recent GRST.
1356          * The grst delay value is in 100ms units, and we'll wait a
1357          * couple counts longer to be sure we don't just miss the end.
1358          */
1359         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1360                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1361                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1362
1363         grst_del = min(grst_del * 20, 160U);
1364
1365         for (cnt = 0; cnt < grst_del; cnt++) {
1366                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1367                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1368                         break;
1369                 i40e_msec_delay(100);
1370         }
1371         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1372                 DEBUGOUT("Global reset polling failed to complete.\n");
1373                 return I40E_ERR_RESET_FAILED;
1374         }
1375
1376         /* Now Wait for the FW to be ready */
1377         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1378                 reg = rd32(hw, I40E_GLNVM_ULD);
1379                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1380                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1381                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1383                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1384                         break;
1385                 }
1386                 i40e_msec_delay(10);
1387         }
1388         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1389                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1390                 DEBUGOUT("wait for FW Reset complete timedout\n");
1391                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1392                 return I40E_ERR_RESET_FAILED;
1393         }
1394
1395         /* If there was a Global Reset in progress when we got here,
1396          * we don't need to do the PF Reset
1397          */
1398         if (!cnt) {
1399                 u32 reg2 = 0;
1400
1401                 reg = rd32(hw, I40E_PFGEN_CTRL);
1402                 wr32(hw, I40E_PFGEN_CTRL,
1403                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1404                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1405                         reg = rd32(hw, I40E_PFGEN_CTRL);
1406                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1407                                 break;
1408                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1409                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1410                                 break;
1411                         i40e_msec_delay(1);
1412                 }
1413                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1414                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1415                                 return I40E_ERR_RESET_FAILED;
1416                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1417                         DEBUGOUT("PF reset polling failed to complete.\n");
1418                         return I40E_ERR_RESET_FAILED;
1419                 }
1420         }
1421
1422         i40e_clear_pxe_mode(hw);
1423
1424
1425         return I40E_SUCCESS;
1426 }
1427
1428 /**
1429  * i40e_clear_hw - clear out any left over hw state
1430  * @hw: pointer to the hw struct
1431  *
1432  * Clear queues and interrupts, typically called at init time,
1433  * but after the capabilities have been found so we know how many
1434  * queues and msix vectors have been allocated.
1435  **/
1436 void i40e_clear_hw(struct i40e_hw *hw)
1437 {
1438         u32 num_queues, base_queue;
1439         u32 num_pf_int;
1440         u32 num_vf_int;
1441         u32 num_vfs;
1442         u32 i, j;
1443         u32 val;
1444         u32 eol = 0x7ff;
1445
1446         /* get number of interrupts, queues, and vfs */
1447         val = rd32(hw, I40E_GLPCI_CNF2);
1448         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1449                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1450         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1451                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1452
1453         val = rd32(hw, I40E_PFLAN_QALLOC);
1454         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1455                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1456         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1457                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1458         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1459                 num_queues = (j - base_queue) + 1;
1460         else
1461                 num_queues = 0;
1462
1463         val = rd32(hw, I40E_PF_VT_PFALLOC);
1464         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1465                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1466         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1467                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1468         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1469                 num_vfs = (j - i) + 1;
1470         else
1471                 num_vfs = 0;
1472
1473         /* stop all the interrupts */
1474         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1475         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1476         for (i = 0; i < num_pf_int - 2; i++)
1477                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1478
1479         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1480         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1481         wr32(hw, I40E_PFINT_LNKLST0, val);
1482         for (i = 0; i < num_pf_int - 2; i++)
1483                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1484         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1485         for (i = 0; i < num_vfs; i++)
1486                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1487         for (i = 0; i < num_vf_int - 2; i++)
1488                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1489
1490         /* warn the HW of the coming Tx disables */
1491         for (i = 0; i < num_queues; i++) {
1492                 u32 abs_queue_idx = base_queue + i;
1493                 u32 reg_block = 0;
1494
1495                 if (abs_queue_idx >= 128) {
1496                         reg_block = abs_queue_idx / 128;
1497                         abs_queue_idx %= 128;
1498                 }
1499
1500                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1501                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1502                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1503                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1504
1505                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1506         }
1507         i40e_usec_delay(400);
1508
1509         /* stop all the queues */
1510         for (i = 0; i < num_queues; i++) {
1511                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1512                 wr32(hw, I40E_QTX_ENA(i), 0);
1513                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1514                 wr32(hw, I40E_QRX_ENA(i), 0);
1515         }
1516
1517         /* short wait for all queue disables to settle */
1518         i40e_usec_delay(50);
1519 }
1520
1521 /**
1522  * i40e_clear_pxe_mode - clear pxe operations mode
1523  * @hw: pointer to the hw struct
1524  *
1525  * Make sure all PXE mode settings are cleared, including things
1526  * like descriptor fetch/write-back mode.
1527  **/
1528 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1529 {
1530         if (i40e_check_asq_alive(hw))
1531                 i40e_aq_clear_pxe_mode(hw, NULL);
1532 }
1533
1534 /**
1535  * i40e_led_is_mine - helper to find matching led
1536  * @hw: pointer to the hw struct
1537  * @idx: index into GPIO registers
1538  *
1539  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1540  */
1541 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1542 {
1543         u32 gpio_val = 0;
1544         u32 port;
1545
1546         if (!hw->func_caps.led[idx])
1547                 return 0;
1548
1549         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1550         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1551                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1552
1553         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1554          * if it is not our port then ignore
1555          */
1556         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1557             (port != hw->port))
1558                 return 0;
1559
1560         return gpio_val;
1561 }
1562
1563 #define I40E_COMBINED_ACTIVITY 0xA
1564 #define I40E_FILTER_ACTIVITY 0xE
1565 #define I40E_LINK_ACTIVITY 0xC
1566 #define I40E_MAC_ACTIVITY 0xD
1567 #define I40E_LED0 22
1568
1569 /**
1570  * i40e_led_get - return current on/off mode
1571  * @hw: pointer to the hw struct
1572  *
1573  * The value returned is the 'mode' field as defined in the
1574  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1575  * values are variations of possible behaviors relating to
1576  * blink, link, and wire.
1577  **/
1578 u32 i40e_led_get(struct i40e_hw *hw)
1579 {
1580         u32 current_mode = 0;
1581         u32 mode = 0;
1582         int i;
1583
1584         /* as per the documentation GPIO 22-29 are the LED
1585          * GPIO pins named LED0..LED7
1586          */
1587         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1588                 u32 gpio_val = i40e_led_is_mine(hw, i);
1589
1590                 if (!gpio_val)
1591                         continue;
1592
1593                 /* ignore gpio LED src mode entries related to the activity
1594                  *  LEDs
1595                  */
1596                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1597                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1598                 switch (current_mode) {
1599                 case I40E_COMBINED_ACTIVITY:
1600                 case I40E_FILTER_ACTIVITY:
1601                 case I40E_MAC_ACTIVITY:
1602                 case I40E_LINK_ACTIVITY:
1603                         continue;
1604                 default:
1605                         break;
1606                 }
1607
1608                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1609                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1610                 break;
1611         }
1612
1613         return mode;
1614 }
1615
1616 /**
1617  * i40e_led_set - set new on/off mode
1618  * @hw: pointer to the hw struct
1619  * @mode: 0=off, 0xf=on (else see manual for mode details)
1620  * @blink: true if the LED should blink when on, false if steady
1621  *
1622  * if this function is used to turn on the blink it should
1623  * be used to disable the blink when restoring the original state.
1624  **/
1625 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1626 {
1627         u32 current_mode = 0;
1628         int i;
1629
1630         if (mode & 0xfffffff0)
1631                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1632
1633         /* as per the documentation GPIO 22-29 are the LED
1634          * GPIO pins named LED0..LED7
1635          */
1636         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1637                 u32 gpio_val = i40e_led_is_mine(hw, i);
1638
1639                 if (!gpio_val)
1640                         continue;
1641
1642                 /* ignore gpio LED src mode entries related to the activity
1643                  * LEDs
1644                  */
1645                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1646                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1647                 switch (current_mode) {
1648                 case I40E_COMBINED_ACTIVITY:
1649                 case I40E_FILTER_ACTIVITY:
1650                 case I40E_MAC_ACTIVITY:
1651                 case I40E_LINK_ACTIVITY:
1652                         continue;
1653                 default:
1654                         break;
1655                 }
1656
1657                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1658                 /* this & is a bit of paranoia, but serves as a range check */
1659                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1660                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1661
1662                 if (blink)
1663                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1664                 else
1665                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1666
1667                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1668                 break;
1669         }
1670 }
1671
1672 /* Admin command wrappers */
1673
1674 /**
1675  * i40e_aq_get_phy_capabilities
1676  * @hw: pointer to the hw struct
1677  * @abilities: structure for PHY capabilities to be filled
1678  * @qualified_modules: report Qualified Modules
1679  * @report_init: report init capabilities (active are default)
1680  * @cmd_details: pointer to command details structure or NULL
1681  *
1682  * Returns the various PHY abilities supported on the Port.
1683  **/
1684 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1685                         bool qualified_modules, bool report_init,
1686                         struct i40e_aq_get_phy_abilities_resp *abilities,
1687                         struct i40e_asq_cmd_details *cmd_details)
1688 {
1689         struct i40e_aq_desc desc;
1690         enum i40e_status_code status;
1691         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1692         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1693
1694         if (!abilities)
1695                 return I40E_ERR_PARAM;
1696
1697         do {
1698                 i40e_fill_default_direct_cmd_desc(&desc,
1699                                                i40e_aqc_opc_get_phy_abilities);
1700
1701                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1702                 if (abilities_size > I40E_AQ_LARGE_BUF)
1703                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1704
1705                 if (qualified_modules)
1706                         desc.params.external.param0 |=
1707                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1708
1709                 if (report_init)
1710                         desc.params.external.param0 |=
1711                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1712
1713                 status = i40e_asq_send_command(hw, &desc, abilities,
1714                                                abilities_size, cmd_details);
1715
1716                 if (status != I40E_SUCCESS)
1717                         break;
1718
1719                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1720                         status = I40E_ERR_UNKNOWN_PHY;
1721                         break;
1722                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1723                         i40e_msec_delay(1);
1724                         total_delay++;
1725                         status = I40E_ERR_TIMEOUT;
1726                 }
1727         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1728                  (total_delay < max_delay));
1729
1730         if (status != I40E_SUCCESS)
1731                 return status;
1732
1733         if (report_init) {
1734                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1735                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1736                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1737                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1738                 } else {
1739                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1740                         hw->phy.phy_types |=
1741                                         ((u64)abilities->phy_type_ext << 32);
1742                 }
1743         }
1744
1745         return status;
1746 }
1747
1748 /**
1749  * i40e_aq_set_phy_config
1750  * @hw: pointer to the hw struct
1751  * @config: structure with PHY configuration to be set
1752  * @cmd_details: pointer to command details structure or NULL
1753  *
1754  * Set the various PHY configuration parameters
1755  * supported on the Port.One or more of the Set PHY config parameters may be
1756  * ignored in an MFP mode as the PF may not have the privilege to set some
1757  * of the PHY Config parameters. This status will be indicated by the
1758  * command response.
1759  **/
1760 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1761                                 struct i40e_aq_set_phy_config *config,
1762                                 struct i40e_asq_cmd_details *cmd_details)
1763 {
1764         struct i40e_aq_desc desc;
1765         struct i40e_aq_set_phy_config *cmd =
1766                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1767         enum i40e_status_code status;
1768
1769         if (!config)
1770                 return I40E_ERR_PARAM;
1771
1772         i40e_fill_default_direct_cmd_desc(&desc,
1773                                           i40e_aqc_opc_set_phy_config);
1774
1775         *cmd = *config;
1776
1777         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1778
1779         return status;
1780 }
1781
1782 /**
1783  * i40e_set_fc
1784  * @hw: pointer to the hw struct
1785  * @aq_failures: buffer to return AdminQ failure information
1786  * @atomic_restart: whether to enable atomic link restart
1787  *
1788  * Set the requested flow control mode using set_phy_config.
1789  **/
1790 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1791                                   bool atomic_restart)
1792 {
1793         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1794         struct i40e_aq_get_phy_abilities_resp abilities;
1795         struct i40e_aq_set_phy_config config;
1796         enum i40e_status_code status;
1797         u8 pause_mask = 0x0;
1798
1799         *aq_failures = 0x0;
1800
1801         switch (fc_mode) {
1802         case I40E_FC_FULL:
1803                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1804                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1805                 break;
1806         case I40E_FC_RX_PAUSE:
1807                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1808                 break;
1809         case I40E_FC_TX_PAUSE:
1810                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1811                 break;
1812         default:
1813                 break;
1814         }
1815
1816         /* Get the current phy config */
1817         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1818                                               NULL);
1819         if (status) {
1820                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1821                 return status;
1822         }
1823
1824         memset(&config, 0, sizeof(config));
1825         /* clear the old pause settings */
1826         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1827                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1828         /* set the new abilities */
1829         config.abilities |= pause_mask;
1830         /* If the abilities have changed, then set the new config */
1831         if (config.abilities != abilities.abilities) {
1832                 /* Auto restart link so settings take effect */
1833                 if (atomic_restart)
1834                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1835                 /* Copy over all the old settings */
1836                 config.phy_type = abilities.phy_type;
1837                 config.phy_type_ext = abilities.phy_type_ext;
1838                 config.link_speed = abilities.link_speed;
1839                 config.eee_capability = abilities.eee_capability;
1840                 config.eeer = abilities.eeer_val;
1841                 config.low_power_ctrl = abilities.d3_lpan;
1842                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1843                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1844                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1845
1846                 if (status)
1847                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1848         }
1849         /* Update the link info */
1850         status = i40e_update_link_info(hw);
1851         if (status) {
1852                 /* Wait a little bit (on 40G cards it sometimes takes a really
1853                  * long time for link to come back from the atomic reset)
1854                  * and try once more
1855                  */
1856                 i40e_msec_delay(1000);
1857                 status = i40e_update_link_info(hw);
1858         }
1859         if (status)
1860                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1861
1862         return status;
1863 }
1864
1865 /**
1866  * i40e_aq_set_mac_config
1867  * @hw: pointer to the hw struct
1868  * @max_frame_size: Maximum Frame Size to be supported by the port
1869  * @crc_en: Tell HW to append a CRC to outgoing frames
1870  * @pacing: Pacing configurations
1871  * @cmd_details: pointer to command details structure or NULL
1872  *
1873  * Configure MAC settings for frame size, jumbo frame support and the
1874  * addition of a CRC by the hardware.
1875  **/
1876 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1877                                 u16 max_frame_size,
1878                                 bool crc_en, u16 pacing,
1879                                 struct i40e_asq_cmd_details *cmd_details)
1880 {
1881         struct i40e_aq_desc desc;
1882         struct i40e_aq_set_mac_config *cmd =
1883                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1884         enum i40e_status_code status;
1885
1886         if (max_frame_size == 0)
1887                 return I40E_ERR_PARAM;
1888
1889         i40e_fill_default_direct_cmd_desc(&desc,
1890                                           i40e_aqc_opc_set_mac_config);
1891
1892         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1893         cmd->params = ((u8)pacing & 0x0F) << 3;
1894         if (crc_en)
1895                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1896
1897 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1898         cmd->fc_refresh_threshold =
1899                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1900
1901         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1902
1903         return status;
1904 }
1905
1906 /**
1907  * i40e_aq_clear_pxe_mode
1908  * @hw: pointer to the hw struct
1909  * @cmd_details: pointer to command details structure or NULL
1910  *
1911  * Tell the firmware that the driver is taking over from PXE
1912  **/
1913 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1914                         struct i40e_asq_cmd_details *cmd_details)
1915 {
1916         enum i40e_status_code status;
1917         struct i40e_aq_desc desc;
1918         struct i40e_aqc_clear_pxe *cmd =
1919                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1920
1921         i40e_fill_default_direct_cmd_desc(&desc,
1922                                           i40e_aqc_opc_clear_pxe_mode);
1923
1924         cmd->rx_cnt = 0x2;
1925
1926         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1927
1928         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1929
1930         return status;
1931 }
1932
1933 /**
1934  * i40e_aq_set_link_restart_an
1935  * @hw: pointer to the hw struct
1936  * @enable_link: if true: enable link, if false: disable link
1937  * @cmd_details: pointer to command details structure or NULL
1938  *
1939  * Sets up the link and restarts the Auto-Negotiation over the link.
1940  **/
1941 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1942                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1943 {
1944         struct i40e_aq_desc desc;
1945         struct i40e_aqc_set_link_restart_an *cmd =
1946                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1947         enum i40e_status_code status;
1948
1949         i40e_fill_default_direct_cmd_desc(&desc,
1950                                           i40e_aqc_opc_set_link_restart_an);
1951
1952         cmd->command = I40E_AQ_PHY_RESTART_AN;
1953         if (enable_link)
1954                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1955         else
1956                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1957
1958         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1959
1960         return status;
1961 }
1962
1963 /**
1964  * i40e_aq_get_link_info
1965  * @hw: pointer to the hw struct
1966  * @enable_lse: enable/disable LinkStatusEvent reporting
1967  * @link: pointer to link status structure - optional
1968  * @cmd_details: pointer to command details structure or NULL
1969  *
1970  * Returns the link status of the adapter.
1971  **/
1972 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1973                                 bool enable_lse, struct i40e_link_status *link,
1974                                 struct i40e_asq_cmd_details *cmd_details)
1975 {
1976         struct i40e_aq_desc desc;
1977         struct i40e_aqc_get_link_status *resp =
1978                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1979         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1980         enum i40e_status_code status;
1981         bool tx_pause, rx_pause;
1982         u16 command_flags;
1983
1984         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1985
1986         if (enable_lse)
1987                 command_flags = I40E_AQ_LSE_ENABLE;
1988         else
1989                 command_flags = I40E_AQ_LSE_DISABLE;
1990         resp->command_flags = CPU_TO_LE16(command_flags);
1991
1992         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1993
1994         if (status != I40E_SUCCESS)
1995                 goto aq_get_link_info_exit;
1996
1997         /* save off old link status information */
1998         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1999                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2000
2001         /* update link status */
2002         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2003         hw->phy.media_type = i40e_get_media_type(hw);
2004         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2005         hw_link_info->link_info = resp->link_info;
2006         hw_link_info->an_info = resp->an_info;
2007         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2008                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
2009         hw_link_info->ext_info = resp->ext_info;
2010         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2011         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2012         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2013
2014         /* update fc info */
2015         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2016         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2017         if (tx_pause & rx_pause)
2018                 hw->fc.current_mode = I40E_FC_FULL;
2019         else if (tx_pause)
2020                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2021         else if (rx_pause)
2022                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2023         else
2024                 hw->fc.current_mode = I40E_FC_NONE;
2025
2026         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2027                 hw_link_info->crc_enable = true;
2028         else
2029                 hw_link_info->crc_enable = false;
2030
2031         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2032                 hw_link_info->lse_enable = true;
2033         else
2034                 hw_link_info->lse_enable = false;
2035
2036         if ((hw->mac.type == I40E_MAC_XL710) &&
2037             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2038              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2039                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2040
2041         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2042             hw->aq.api_min_ver >= 7) {
2043                 __le32 tmp;
2044
2045                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2046                             I40E_NONDMA_TO_NONDMA);
2047                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2048                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2049         }
2050
2051         /* save link status information */
2052         if (link)
2053                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2054                             I40E_NONDMA_TO_NONDMA);
2055
2056         /* flag cleared so helper functions don't call AQ again */
2057         hw->phy.get_link_info = false;
2058
2059 aq_get_link_info_exit:
2060         return status;
2061 }
2062
2063 /**
2064  * i40e_aq_set_phy_int_mask
2065  * @hw: pointer to the hw struct
2066  * @mask: interrupt mask to be set
2067  * @cmd_details: pointer to command details structure or NULL
2068  *
2069  * Set link interrupt mask.
2070  **/
2071 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2072                                 u16 mask,
2073                                 struct i40e_asq_cmd_details *cmd_details)
2074 {
2075         struct i40e_aq_desc desc;
2076         struct i40e_aqc_set_phy_int_mask *cmd =
2077                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2078         enum i40e_status_code status;
2079
2080         i40e_fill_default_direct_cmd_desc(&desc,
2081                                           i40e_aqc_opc_set_phy_int_mask);
2082
2083         cmd->event_mask = CPU_TO_LE16(mask);
2084
2085         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2086
2087         return status;
2088 }
2089
2090 /**
2091  * i40e_aq_get_local_advt_reg
2092  * @hw: pointer to the hw struct
2093  * @advt_reg: local AN advertisement register value
2094  * @cmd_details: pointer to command details structure or NULL
2095  *
2096  * Get the Local AN advertisement register value.
2097  **/
2098 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2099                                 u64 *advt_reg,
2100                                 struct i40e_asq_cmd_details *cmd_details)
2101 {
2102         struct i40e_aq_desc desc;
2103         struct i40e_aqc_an_advt_reg *resp =
2104                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2105         enum i40e_status_code status;
2106
2107         i40e_fill_default_direct_cmd_desc(&desc,
2108                                           i40e_aqc_opc_get_local_advt_reg);
2109
2110         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2111
2112         if (status != I40E_SUCCESS)
2113                 goto aq_get_local_advt_reg_exit;
2114
2115         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2116         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2117
2118 aq_get_local_advt_reg_exit:
2119         return status;
2120 }
2121
2122 /**
2123  * i40e_aq_set_local_advt_reg
2124  * @hw: pointer to the hw struct
2125  * @advt_reg: local AN advertisement register value
2126  * @cmd_details: pointer to command details structure or NULL
2127  *
2128  * Get the Local AN advertisement register value.
2129  **/
2130 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2131                                 u64 advt_reg,
2132                                 struct i40e_asq_cmd_details *cmd_details)
2133 {
2134         struct i40e_aq_desc desc;
2135         struct i40e_aqc_an_advt_reg *cmd =
2136                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2137         enum i40e_status_code status;
2138
2139         i40e_fill_default_direct_cmd_desc(&desc,
2140                                           i40e_aqc_opc_get_local_advt_reg);
2141
2142         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2143         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2144
2145         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2146
2147         return status;
2148 }
2149
2150 /**
2151  * i40e_aq_get_partner_advt
2152  * @hw: pointer to the hw struct
2153  * @advt_reg: AN partner advertisement register value
2154  * @cmd_details: pointer to command details structure or NULL
2155  *
2156  * Get the link partner AN advertisement register value.
2157  **/
2158 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2159                                 u64 *advt_reg,
2160                                 struct i40e_asq_cmd_details *cmd_details)
2161 {
2162         struct i40e_aq_desc desc;
2163         struct i40e_aqc_an_advt_reg *resp =
2164                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2165         enum i40e_status_code status;
2166
2167         i40e_fill_default_direct_cmd_desc(&desc,
2168                                           i40e_aqc_opc_get_partner_advt);
2169
2170         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2171
2172         if (status != I40E_SUCCESS)
2173                 goto aq_get_partner_advt_exit;
2174
2175         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2176         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2177
2178 aq_get_partner_advt_exit:
2179         return status;
2180 }
2181
2182 /**
2183  * i40e_aq_set_lb_modes
2184  * @hw: pointer to the hw struct
2185  * @lb_modes: loopback mode to be set
2186  * @cmd_details: pointer to command details structure or NULL
2187  *
2188  * Sets loopback modes.
2189  **/
2190 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2191                                 u16 lb_modes,
2192                                 struct i40e_asq_cmd_details *cmd_details)
2193 {
2194         struct i40e_aq_desc desc;
2195         struct i40e_aqc_set_lb_mode *cmd =
2196                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2197         enum i40e_status_code status;
2198
2199         i40e_fill_default_direct_cmd_desc(&desc,
2200                                           i40e_aqc_opc_set_lb_modes);
2201
2202         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2203
2204         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2205
2206         return status;
2207 }
2208
2209 /**
2210  * i40e_aq_set_phy_debug
2211  * @hw: pointer to the hw struct
2212  * @cmd_flags: debug command flags
2213  * @cmd_details: pointer to command details structure or NULL
2214  *
2215  * Reset the external PHY.
2216  **/
2217 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2218                                 struct i40e_asq_cmd_details *cmd_details)
2219 {
2220         struct i40e_aq_desc desc;
2221         struct i40e_aqc_set_phy_debug *cmd =
2222                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2223         enum i40e_status_code status;
2224
2225         i40e_fill_default_direct_cmd_desc(&desc,
2226                                           i40e_aqc_opc_set_phy_debug);
2227
2228         cmd->command_flags = cmd_flags;
2229
2230         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2231
2232         return status;
2233 }
2234
2235 /**
2236  * i40e_aq_add_vsi
2237  * @hw: pointer to the hw struct
2238  * @vsi_ctx: pointer to a vsi context struct
2239  * @cmd_details: pointer to command details structure or NULL
2240  *
2241  * Add a VSI context to the hardware.
2242 **/
2243 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2244                                 struct i40e_vsi_context *vsi_ctx,
2245                                 struct i40e_asq_cmd_details *cmd_details)
2246 {
2247         struct i40e_aq_desc desc;
2248         struct i40e_aqc_add_get_update_vsi *cmd =
2249                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2250         struct i40e_aqc_add_get_update_vsi_completion *resp =
2251                 (struct i40e_aqc_add_get_update_vsi_completion *)
2252                 &desc.params.raw;
2253         enum i40e_status_code status;
2254
2255         i40e_fill_default_direct_cmd_desc(&desc,
2256                                           i40e_aqc_opc_add_vsi);
2257
2258         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2259         cmd->connection_type = vsi_ctx->connection_type;
2260         cmd->vf_id = vsi_ctx->vf_num;
2261         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2262
2263         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2264
2265         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2266                                     sizeof(vsi_ctx->info), cmd_details);
2267
2268         if (status != I40E_SUCCESS)
2269                 goto aq_add_vsi_exit;
2270
2271         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2272         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2273         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2274         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2275
2276 aq_add_vsi_exit:
2277         return status;
2278 }
2279
2280 /**
2281  * i40e_aq_set_default_vsi
2282  * @hw: pointer to the hw struct
2283  * @seid: vsi number
2284  * @cmd_details: pointer to command details structure or NULL
2285  **/
2286 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2287                                 u16 seid,
2288                                 struct i40e_asq_cmd_details *cmd_details)
2289 {
2290         struct i40e_aq_desc desc;
2291         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2292                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2293                 &desc.params.raw;
2294         enum i40e_status_code status;
2295
2296         i40e_fill_default_direct_cmd_desc(&desc,
2297                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2298
2299         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2300         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2301         cmd->seid = CPU_TO_LE16(seid);
2302
2303         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2304
2305         return status;
2306 }
2307
2308 /**
2309  * i40e_aq_clear_default_vsi
2310  * @hw: pointer to the hw struct
2311  * @seid: vsi number
2312  * @cmd_details: pointer to command details structure or NULL
2313  **/
2314 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2315                                 u16 seid,
2316                                 struct i40e_asq_cmd_details *cmd_details)
2317 {
2318         struct i40e_aq_desc desc;
2319         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2320                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2321                 &desc.params.raw;
2322         enum i40e_status_code status;
2323
2324         i40e_fill_default_direct_cmd_desc(&desc,
2325                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2326
2327         cmd->promiscuous_flags = CPU_TO_LE16(0);
2328         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2329         cmd->seid = CPU_TO_LE16(seid);
2330
2331         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2332
2333         return status;
2334 }
2335
2336 /**
2337  * i40e_aq_set_vsi_unicast_promiscuous
2338  * @hw: pointer to the hw struct
2339  * @seid: vsi number
2340  * @set: set unicast promiscuous enable/disable
2341  * @cmd_details: pointer to command details structure or NULL
2342  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2343  **/
2344 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2345                                 u16 seid, bool set,
2346                                 struct i40e_asq_cmd_details *cmd_details,
2347                                 bool rx_only_promisc)
2348 {
2349         struct i40e_aq_desc desc;
2350         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2351                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2352         enum i40e_status_code status;
2353         u16 flags = 0;
2354
2355         i40e_fill_default_direct_cmd_desc(&desc,
2356                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2357
2358         if (set) {
2359                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2360                 if (rx_only_promisc &&
2361                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2362                      (hw->aq.api_maj_ver > 1)))
2363                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2364         }
2365
2366         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2367
2368         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2369         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2370              (hw->aq.api_maj_ver > 1))
2371                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2372
2373         cmd->seid = CPU_TO_LE16(seid);
2374         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2375
2376         return status;
2377 }
2378
2379 /**
2380  * i40e_aq_set_vsi_multicast_promiscuous
2381  * @hw: pointer to the hw struct
2382  * @seid: vsi number
2383  * @set: set multicast promiscuous enable/disable
2384  * @cmd_details: pointer to command details structure or NULL
2385  **/
2386 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2387                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2388 {
2389         struct i40e_aq_desc desc;
2390         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2391                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2392         enum i40e_status_code status;
2393         u16 flags = 0;
2394
2395         i40e_fill_default_direct_cmd_desc(&desc,
2396                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2397
2398         if (set)
2399                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2400
2401         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2402
2403         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2404
2405         cmd->seid = CPU_TO_LE16(seid);
2406         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2407
2408         return status;
2409 }
2410
2411 /**
2412 * i40e_aq_set_vsi_full_promiscuous
2413 * @hw: pointer to the hw struct
2414 * @seid: VSI number
2415 * @set: set promiscuous enable/disable
2416 * @cmd_details: pointer to command details structure or NULL
2417 **/
2418 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2419                                 u16 seid, bool set,
2420                                 struct i40e_asq_cmd_details *cmd_details)
2421 {
2422         struct i40e_aq_desc desc;
2423         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2424                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2425         enum i40e_status_code status;
2426         u16 flags = 0;
2427
2428         i40e_fill_default_direct_cmd_desc(&desc,
2429                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2430
2431         if (set)
2432                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2433                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2434                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2435
2436         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2437
2438         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2439                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2440                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2441
2442         cmd->seid = CPU_TO_LE16(seid);
2443         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2444
2445         return status;
2446 }
2447
2448 /**
2449  * i40e_aq_set_vsi_mc_promisc_on_vlan
2450  * @hw: pointer to the hw struct
2451  * @seid: vsi number
2452  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2453  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2454  * @cmd_details: pointer to command details structure or NULL
2455  **/
2456 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2457                                 u16 seid, bool enable, u16 vid,
2458                                 struct i40e_asq_cmd_details *cmd_details)
2459 {
2460         struct i40e_aq_desc desc;
2461         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2462                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2463         enum i40e_status_code status;
2464         u16 flags = 0;
2465
2466         i40e_fill_default_direct_cmd_desc(&desc,
2467                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2468
2469         if (enable)
2470                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2471
2472         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2473         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2474         cmd->seid = CPU_TO_LE16(seid);
2475         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2476
2477         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2478
2479         return status;
2480 }
2481
2482 /**
2483  * i40e_aq_set_vsi_uc_promisc_on_vlan
2484  * @hw: pointer to the hw struct
2485  * @seid: vsi number
2486  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2487  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2488  * @cmd_details: pointer to command details structure or NULL
2489  **/
2490 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2491                                 u16 seid, bool enable, u16 vid,
2492                                 struct i40e_asq_cmd_details *cmd_details)
2493 {
2494         struct i40e_aq_desc desc;
2495         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2496                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2497         enum i40e_status_code status;
2498         u16 flags = 0;
2499
2500         i40e_fill_default_direct_cmd_desc(&desc,
2501                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2502
2503         if (enable)
2504                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2505
2506         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2507         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2508         cmd->seid = CPU_TO_LE16(seid);
2509         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2510
2511         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2512
2513         return status;
2514 }
2515
2516 /**
2517  * i40e_aq_set_vsi_bc_promisc_on_vlan
2518  * @hw: pointer to the hw struct
2519  * @seid: vsi number
2520  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2521  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2522  * @cmd_details: pointer to command details structure or NULL
2523  **/
2524 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2525                                 u16 seid, bool enable, u16 vid,
2526                                 struct i40e_asq_cmd_details *cmd_details)
2527 {
2528         struct i40e_aq_desc desc;
2529         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2530                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2531         enum i40e_status_code status;
2532         u16 flags = 0;
2533
2534         i40e_fill_default_direct_cmd_desc(&desc,
2535                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2536
2537         if (enable)
2538                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2539
2540         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2541         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2542         cmd->seid = CPU_TO_LE16(seid);
2543         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2544
2545         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2546
2547         return status;
2548 }
2549
2550 /**
2551  * i40e_aq_set_vsi_broadcast
2552  * @hw: pointer to the hw struct
2553  * @seid: vsi number
2554  * @set_filter: true to set filter, false to clear filter
2555  * @cmd_details: pointer to command details structure or NULL
2556  *
2557  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2558  **/
2559 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2560                                 u16 seid, bool set_filter,
2561                                 struct i40e_asq_cmd_details *cmd_details)
2562 {
2563         struct i40e_aq_desc desc;
2564         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2565                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2566         enum i40e_status_code status;
2567
2568         i40e_fill_default_direct_cmd_desc(&desc,
2569                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2570
2571         if (set_filter)
2572                 cmd->promiscuous_flags
2573                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2574         else
2575                 cmd->promiscuous_flags
2576                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2577
2578         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2579         cmd->seid = CPU_TO_LE16(seid);
2580         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2581
2582         return status;
2583 }
2584
2585 /**
2586  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2587  * @hw: pointer to the hw struct
2588  * @seid: vsi number
2589  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2590  * @cmd_details: pointer to command details structure or NULL
2591  **/
2592 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2593                                 u16 seid, bool enable,
2594                                 struct i40e_asq_cmd_details *cmd_details)
2595 {
2596         struct i40e_aq_desc desc;
2597         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2598                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2599         enum i40e_status_code status;
2600         u16 flags = 0;
2601
2602         i40e_fill_default_direct_cmd_desc(&desc,
2603                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2604         if (enable)
2605                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2606
2607         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2608         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2609         cmd->seid = CPU_TO_LE16(seid);
2610
2611         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2612
2613         return status;
2614 }
2615
2616 /**
2617  * i40e_get_vsi_params - get VSI configuration info
2618  * @hw: pointer to the hw struct
2619  * @vsi_ctx: pointer to a vsi context struct
2620  * @cmd_details: pointer to command details structure or NULL
2621  **/
2622 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2623                                 struct i40e_vsi_context *vsi_ctx,
2624                                 struct i40e_asq_cmd_details *cmd_details)
2625 {
2626         struct i40e_aq_desc desc;
2627         struct i40e_aqc_add_get_update_vsi *cmd =
2628                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2629         struct i40e_aqc_add_get_update_vsi_completion *resp =
2630                 (struct i40e_aqc_add_get_update_vsi_completion *)
2631                 &desc.params.raw;
2632         enum i40e_status_code status;
2633
2634         UNREFERENCED_1PARAMETER(cmd_details);
2635         i40e_fill_default_direct_cmd_desc(&desc,
2636                                           i40e_aqc_opc_get_vsi_parameters);
2637
2638         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2639
2640         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2641
2642         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2643                                     sizeof(vsi_ctx->info), NULL);
2644
2645         if (status != I40E_SUCCESS)
2646                 goto aq_get_vsi_params_exit;
2647
2648         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2649         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2650         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2651         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2652
2653 aq_get_vsi_params_exit:
2654         return status;
2655 }
2656
2657 /**
2658  * i40e_aq_update_vsi_params
2659  * @hw: pointer to the hw struct
2660  * @vsi_ctx: pointer to a vsi context struct
2661  * @cmd_details: pointer to command details structure or NULL
2662  *
2663  * Update a VSI context.
2664  **/
2665 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2666                                 struct i40e_vsi_context *vsi_ctx,
2667                                 struct i40e_asq_cmd_details *cmd_details)
2668 {
2669         struct i40e_aq_desc desc;
2670         struct i40e_aqc_add_get_update_vsi *cmd =
2671                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2672         struct i40e_aqc_add_get_update_vsi_completion *resp =
2673                 (struct i40e_aqc_add_get_update_vsi_completion *)
2674                 &desc.params.raw;
2675         enum i40e_status_code status;
2676
2677         i40e_fill_default_direct_cmd_desc(&desc,
2678                                           i40e_aqc_opc_update_vsi_parameters);
2679         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2680
2681         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2682
2683         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2684                                     sizeof(vsi_ctx->info), cmd_details);
2685
2686         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2687         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2688
2689         return status;
2690 }
2691
2692 /**
2693  * i40e_aq_get_switch_config
2694  * @hw: pointer to the hardware structure
2695  * @buf: pointer to the result buffer
2696  * @buf_size: length of input buffer
2697  * @start_seid: seid to start for the report, 0 == beginning
2698  * @cmd_details: pointer to command details structure or NULL
2699  *
2700  * Fill the buf with switch configuration returned from AdminQ command
2701  **/
2702 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2703                                 struct i40e_aqc_get_switch_config_resp *buf,
2704                                 u16 buf_size, u16 *start_seid,
2705                                 struct i40e_asq_cmd_details *cmd_details)
2706 {
2707         struct i40e_aq_desc desc;
2708         struct i40e_aqc_switch_seid *scfg =
2709                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2710         enum i40e_status_code status;
2711
2712         i40e_fill_default_direct_cmd_desc(&desc,
2713                                           i40e_aqc_opc_get_switch_config);
2714         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2715         if (buf_size > I40E_AQ_LARGE_BUF)
2716                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2717         scfg->seid = CPU_TO_LE16(*start_seid);
2718
2719         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2720         *start_seid = LE16_TO_CPU(scfg->seid);
2721
2722         return status;
2723 }
2724
2725 /**
2726  * i40e_aq_set_switch_config
2727  * @hw: pointer to the hardware structure
2728  * @flags: bit flag values to set
2729  * @mode: cloud filter mode
2730  * @valid_flags: which bit flags to set
2731  * @cmd_details: pointer to command details structure or NULL
2732  *
2733  * Set switch configuration bits
2734  **/
2735 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2736                                 u16 flags, u16 valid_flags, u8 mode,
2737                                 struct i40e_asq_cmd_details *cmd_details)
2738 {
2739         struct i40e_aq_desc desc;
2740         struct i40e_aqc_set_switch_config *scfg =
2741                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2742         enum i40e_status_code status;
2743
2744         i40e_fill_default_direct_cmd_desc(&desc,
2745                                           i40e_aqc_opc_set_switch_config);
2746         scfg->flags = CPU_TO_LE16(flags);
2747         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2748         scfg->mode = mode;
2749         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2750                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2751                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2752                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2753         }
2754         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2755
2756         return status;
2757 }
2758
2759 /**
2760  * i40e_aq_get_firmware_version
2761  * @hw: pointer to the hw struct
2762  * @fw_major_version: firmware major version
2763  * @fw_minor_version: firmware minor version
2764  * @fw_build: firmware build number
2765  * @api_major_version: major queue version
2766  * @api_minor_version: minor queue version
2767  * @cmd_details: pointer to command details structure or NULL
2768  *
2769  * Get the firmware version from the admin queue commands
2770  **/
2771 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2772                                 u16 *fw_major_version, u16 *fw_minor_version,
2773                                 u32 *fw_build,
2774                                 u16 *api_major_version, u16 *api_minor_version,
2775                                 struct i40e_asq_cmd_details *cmd_details)
2776 {
2777         struct i40e_aq_desc desc;
2778         struct i40e_aqc_get_version *resp =
2779                 (struct i40e_aqc_get_version *)&desc.params.raw;
2780         enum i40e_status_code status;
2781
2782         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2783
2784         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2785
2786         if (status == I40E_SUCCESS) {
2787                 if (fw_major_version != NULL)
2788                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2789                 if (fw_minor_version != NULL)
2790                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2791                 if (fw_build != NULL)
2792                         *fw_build = LE32_TO_CPU(resp->fw_build);
2793                 if (api_major_version != NULL)
2794                         *api_major_version = LE16_TO_CPU(resp->api_major);
2795                 if (api_minor_version != NULL)
2796                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2797
2798                 /* A workaround to fix the API version in SW */
2799                 if (api_major_version && api_minor_version &&
2800                     fw_major_version && fw_minor_version &&
2801                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2802                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2803                      (*fw_major_version > 4)))
2804                         *api_minor_version = 2;
2805         }
2806
2807         return status;
2808 }
2809
2810 /**
2811  * i40e_aq_send_driver_version
2812  * @hw: pointer to the hw struct
2813  * @dv: driver's major, minor version
2814  * @cmd_details: pointer to command details structure or NULL
2815  *
2816  * Send the driver version to the firmware
2817  **/
2818 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2819                                 struct i40e_driver_version *dv,
2820                                 struct i40e_asq_cmd_details *cmd_details)
2821 {
2822         struct i40e_aq_desc desc;
2823         struct i40e_aqc_driver_version *cmd =
2824                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2825         enum i40e_status_code status;
2826         u16 len;
2827
2828         if (dv == NULL)
2829                 return I40E_ERR_PARAM;
2830
2831         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2832
2833         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2834         cmd->driver_major_ver = dv->major_version;
2835         cmd->driver_minor_ver = dv->minor_version;
2836         cmd->driver_build_ver = dv->build_version;
2837         cmd->driver_subbuild_ver = dv->subbuild_version;
2838
2839         len = 0;
2840         while (len < sizeof(dv->driver_string) &&
2841                (dv->driver_string[len] < 0x80) &&
2842                dv->driver_string[len])
2843                 len++;
2844         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2845                                        len, cmd_details);
2846
2847         return status;
2848 }
2849
2850 /**
2851  * i40e_get_link_status - get status of the HW network link
2852  * @hw: pointer to the hw struct
2853  * @link_up: pointer to bool (true/false = linkup/linkdown)
2854  *
2855  * Variable link_up true if link is up, false if link is down.
2856  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2857  *
2858  * Side effect: LinkStatusEvent reporting becomes enabled
2859  **/
2860 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2861 {
2862         enum i40e_status_code status = I40E_SUCCESS;
2863
2864         if (hw->phy.get_link_info) {
2865                 status = i40e_update_link_info(hw);
2866
2867                 if (status != I40E_SUCCESS)
2868                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2869                                    status);
2870         }
2871
2872         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2873
2874         return status;
2875 }
2876
2877 /**
2878  * i40e_updatelink_status - update status of the HW network link
2879  * @hw: pointer to the hw struct
2880  **/
2881 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2882 {
2883         struct i40e_aq_get_phy_abilities_resp abilities;
2884         enum i40e_status_code status = I40E_SUCCESS;
2885
2886         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2887         if (status)
2888                 return status;
2889
2890         /* extra checking needed to ensure link info to user is timely */
2891         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2892             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2893              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2894                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2895                                                       &abilities, NULL);
2896                 if (status)
2897                         return status;
2898
2899                 hw->phy.link_info.req_fec_info =
2900                         abilities.fec_cfg_curr_mod_ext_info &
2901                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2902
2903                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2904                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2905         }
2906         return status;
2907 }
2908
2909
2910 /**
2911  * i40e_get_link_speed
2912  * @hw: pointer to the hw struct
2913  *
2914  * Returns the link speed of the adapter.
2915  **/
2916 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2917 {
2918         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2919         enum i40e_status_code status = I40E_SUCCESS;
2920
2921         if (hw->phy.get_link_info) {
2922                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2923
2924                 if (status != I40E_SUCCESS)
2925                         goto i40e_link_speed_exit;
2926         }
2927
2928         speed = hw->phy.link_info.link_speed;
2929
2930 i40e_link_speed_exit:
2931         return speed;
2932 }
2933
2934 /**
2935  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2936  * @hw: pointer to the hw struct
2937  * @uplink_seid: the MAC or other gizmo SEID
2938  * @downlink_seid: the VSI SEID
2939  * @enabled_tc: bitmap of TCs to be enabled
2940  * @default_port: true for default port VSI, false for control port
2941  * @veb_seid: pointer to where to put the resulting VEB SEID
2942  * @enable_stats: true to turn on VEB stats
2943  * @cmd_details: pointer to command details structure or NULL
2944  *
2945  * This asks the FW to add a VEB between the uplink and downlink
2946  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2947  **/
2948 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2949                                 u16 downlink_seid, u8 enabled_tc,
2950                                 bool default_port, u16 *veb_seid,
2951                                 bool enable_stats,
2952                                 struct i40e_asq_cmd_details *cmd_details)
2953 {
2954         struct i40e_aq_desc desc;
2955         struct i40e_aqc_add_veb *cmd =
2956                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2957         struct i40e_aqc_add_veb_completion *resp =
2958                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2959         enum i40e_status_code status;
2960         u16 veb_flags = 0;
2961
2962         /* SEIDs need to either both be set or both be 0 for floating VEB */
2963         if (!!uplink_seid != !!downlink_seid)
2964                 return I40E_ERR_PARAM;
2965
2966         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2967
2968         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2969         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2970         cmd->enable_tcs = enabled_tc;
2971         if (!uplink_seid)
2972                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2973         if (default_port)
2974                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2975         else
2976                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2977
2978         /* reverse logic here: set the bitflag to disable the stats */
2979         if (!enable_stats)
2980                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2981
2982         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2983
2984         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2985
2986         if (!status && veb_seid)
2987                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2988
2989         return status;
2990 }
2991
2992 /**
2993  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2994  * @hw: pointer to the hw struct
2995  * @veb_seid: the SEID of the VEB to query
2996  * @switch_id: the uplink switch id
2997  * @floating: set to true if the VEB is floating
2998  * @statistic_index: index of the stats counter block for this VEB
2999  * @vebs_used: number of VEB's used by function
3000  * @vebs_free: total VEB's not reserved by any function
3001  * @cmd_details: pointer to command details structure or NULL
3002  *
3003  * This retrieves the parameters for a particular VEB, specified by
3004  * uplink_seid, and returns them to the caller.
3005  **/
3006 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3007                                 u16 veb_seid, u16 *switch_id,
3008                                 bool *floating, u16 *statistic_index,
3009                                 u16 *vebs_used, u16 *vebs_free,
3010                                 struct i40e_asq_cmd_details *cmd_details)
3011 {
3012         struct i40e_aq_desc desc;
3013         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3014                 (struct i40e_aqc_get_veb_parameters_completion *)
3015                 &desc.params.raw;
3016         enum i40e_status_code status;
3017
3018         if (veb_seid == 0)
3019                 return I40E_ERR_PARAM;
3020
3021         i40e_fill_default_direct_cmd_desc(&desc,
3022                                           i40e_aqc_opc_get_veb_parameters);
3023         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3024
3025         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3026         if (status)
3027                 goto get_veb_exit;
3028
3029         if (switch_id)
3030                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3031         if (statistic_index)
3032                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3033         if (vebs_used)
3034                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3035         if (vebs_free)
3036                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3037         if (floating) {
3038                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3039
3040                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3041                         *floating = true;
3042                 else
3043                         *floating = false;
3044         }
3045
3046 get_veb_exit:
3047         return status;
3048 }
3049
3050 /**
3051  * i40e_aq_add_macvlan
3052  * @hw: pointer to the hw struct
3053  * @seid: VSI for the mac address
3054  * @mv_list: list of macvlans to be added
3055  * @count: length of the list
3056  * @cmd_details: pointer to command details structure or NULL
3057  *
3058  * Add MAC/VLAN addresses to the HW filtering
3059  **/
3060 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3061                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3062                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3063 {
3064         struct i40e_aq_desc desc;
3065         struct i40e_aqc_macvlan *cmd =
3066                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3067         enum i40e_status_code status;
3068         u16 buf_size;
3069         int i;
3070
3071         if (count == 0 || !mv_list || !hw)
3072                 return I40E_ERR_PARAM;
3073
3074         buf_size = count * sizeof(*mv_list);
3075
3076         /* prep the rest of the request */
3077         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3078         cmd->num_addresses = CPU_TO_LE16(count);
3079         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3080         cmd->seid[1] = 0;
3081         cmd->seid[2] = 0;
3082
3083         for (i = 0; i < count; i++)
3084                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3085                         mv_list[i].flags |=
3086                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3087
3088         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3089         if (buf_size > I40E_AQ_LARGE_BUF)
3090                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3091
3092         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3093                                        cmd_details);
3094
3095         return status;
3096 }
3097
3098 /**
3099  * i40e_aq_remove_macvlan
3100  * @hw: pointer to the hw struct
3101  * @seid: VSI for the mac address
3102  * @mv_list: list of macvlans to be removed
3103  * @count: length of the list
3104  * @cmd_details: pointer to command details structure or NULL
3105  *
3106  * Remove MAC/VLAN addresses from the HW filtering
3107  **/
3108 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3109                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3110                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3111 {
3112         struct i40e_aq_desc desc;
3113         struct i40e_aqc_macvlan *cmd =
3114                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3115         enum i40e_status_code status;
3116         u16 buf_size;
3117
3118         if (count == 0 || !mv_list || !hw)
3119                 return I40E_ERR_PARAM;
3120
3121         buf_size = count * sizeof(*mv_list);
3122
3123         /* prep the rest of the request */
3124         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3125         cmd->num_addresses = CPU_TO_LE16(count);
3126         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3127         cmd->seid[1] = 0;
3128         cmd->seid[2] = 0;
3129
3130         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3131         if (buf_size > I40E_AQ_LARGE_BUF)
3132                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3133
3134         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3135                                        cmd_details);
3136
3137         return status;
3138 }
3139
3140 /**
3141  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3142  * @hw: pointer to the hw struct
3143  * @opcode: AQ opcode for add or delete mirror rule
3144  * @sw_seid: Switch SEID (to which rule refers)
3145  * @rule_type: Rule Type (ingress/egress/VLAN)
3146  * @id: Destination VSI SEID or Rule ID
3147  * @count: length of the list
3148  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3149  * @cmd_details: pointer to command details structure or NULL
3150  * @rule_id: Rule ID returned from FW
3151  * @rules_used: Number of rules used in internal switch
3152  * @rules_free: Number of rules free in internal switch
3153  *
3154  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3155  * VEBs/VEPA elements only
3156  **/
3157 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3158                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3159                         u16 count, __le16 *mr_list,
3160                         struct i40e_asq_cmd_details *cmd_details,
3161                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3162 {
3163         struct i40e_aq_desc desc;
3164         struct i40e_aqc_add_delete_mirror_rule *cmd =
3165                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3166         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3167         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3168         enum i40e_status_code status;
3169         u16 buf_size;
3170
3171         buf_size = count * sizeof(*mr_list);
3172
3173         /* prep the rest of the request */
3174         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3175         cmd->seid = CPU_TO_LE16(sw_seid);
3176         cmd->rule_type = CPU_TO_LE16(rule_type &
3177                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3178         cmd->num_entries = CPU_TO_LE16(count);
3179         /* Dest VSI for add, rule_id for delete */
3180         cmd->destination = CPU_TO_LE16(id);
3181         if (mr_list) {
3182                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3183                                                 I40E_AQ_FLAG_RD));
3184                 if (buf_size > I40E_AQ_LARGE_BUF)
3185                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3186         }
3187
3188         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3189                                        cmd_details);
3190         if (status == I40E_SUCCESS ||
3191             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3192                 if (rule_id)
3193                         *rule_id = LE16_TO_CPU(resp->rule_id);
3194                 if (rules_used)
3195                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3196                 if (rules_free)
3197                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3198         }
3199         return status;
3200 }
3201
3202 /**
3203  * i40e_aq_add_mirrorrule - add a mirror rule
3204  * @hw: pointer to the hw struct
3205  * @sw_seid: Switch SEID (to which rule refers)
3206  * @rule_type: Rule Type (ingress/egress/VLAN)
3207  * @dest_vsi: SEID of VSI to which packets will be mirrored
3208  * @count: length of the list
3209  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3210  * @cmd_details: pointer to command details structure or NULL
3211  * @rule_id: Rule ID returned from FW
3212  * @rules_used: Number of rules used in internal switch
3213  * @rules_free: Number of rules free in internal switch
3214  *
3215  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3216  **/
3217 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3218                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3219                         struct i40e_asq_cmd_details *cmd_details,
3220                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3221 {
3222         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3223             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3224                 if (count == 0 || !mr_list)
3225                         return I40E_ERR_PARAM;
3226         }
3227
3228         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3229                                   rule_type, dest_vsi, count, mr_list,
3230                                   cmd_details, rule_id, rules_used, rules_free);
3231 }
3232
3233 /**
3234  * i40e_aq_delete_mirrorrule - delete a mirror rule
3235  * @hw: pointer to the hw struct
3236  * @sw_seid: Switch SEID (to which rule refers)
3237  * @rule_type: Rule Type (ingress/egress/VLAN)
3238  * @count: length of the list
3239  * @rule_id: Rule ID that is returned in the receive desc as part of
3240  *              add_mirrorrule.
3241  * @mr_list: list of mirrored VLAN IDs to be removed
3242  * @cmd_details: pointer to command details structure or NULL
3243  * @rules_used: Number of rules used in internal switch
3244  * @rules_free: Number of rules free in internal switch
3245  *
3246  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3247  **/
3248 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3249                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3250                         struct i40e_asq_cmd_details *cmd_details,
3251                         u16 *rules_used, u16 *rules_free)
3252 {
3253         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3254         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3255                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3256                  * mirroring. For other rule_type, count and rule_type should
3257                  * not matter.
3258                  */
3259                 if (count == 0 || !mr_list)
3260                         return I40E_ERR_PARAM;
3261         }
3262
3263         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3264                                   rule_type, rule_id, count, mr_list,
3265                                   cmd_details, NULL, rules_used, rules_free);
3266 }
3267
3268 /**
3269  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3270  * @hw: pointer to the hw struct
3271  * @seid: VSI for the vlan filters
3272  * @v_list: list of vlan filters to be added
3273  * @count: length of the list
3274  * @cmd_details: pointer to command details structure or NULL
3275  **/
3276 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3277                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3278                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3279 {
3280         struct i40e_aq_desc desc;
3281         struct i40e_aqc_macvlan *cmd =
3282                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3283         enum i40e_status_code status;
3284         u16 buf_size;
3285
3286         if (count == 0 || !v_list || !hw)
3287                 return I40E_ERR_PARAM;
3288
3289         buf_size = count * sizeof(*v_list);
3290
3291         /* prep the rest of the request */
3292         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3293         cmd->num_addresses = CPU_TO_LE16(count);
3294         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3295         cmd->seid[1] = 0;
3296         cmd->seid[2] = 0;
3297
3298         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3299         if (buf_size > I40E_AQ_LARGE_BUF)
3300                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3301
3302         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3303                                        cmd_details);
3304
3305         return status;
3306 }
3307
3308 /**
3309  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3310  * @hw: pointer to the hw struct
3311  * @seid: VSI for the vlan filters
3312  * @v_list: list of macvlans to be removed
3313  * @count: length of the list
3314  * @cmd_details: pointer to command details structure or NULL
3315  **/
3316 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3317                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3318                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3319 {
3320         struct i40e_aq_desc desc;
3321         struct i40e_aqc_macvlan *cmd =
3322                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3323         enum i40e_status_code status;
3324         u16 buf_size;
3325
3326         if (count == 0 || !v_list || !hw)
3327                 return I40E_ERR_PARAM;
3328
3329         buf_size = count * sizeof(*v_list);
3330
3331         /* prep the rest of the request */
3332         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3333         cmd->num_addresses = CPU_TO_LE16(count);
3334         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3335         cmd->seid[1] = 0;
3336         cmd->seid[2] = 0;
3337
3338         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3339         if (buf_size > I40E_AQ_LARGE_BUF)
3340                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3341
3342         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3343                                        cmd_details);
3344
3345         return status;
3346 }
3347
3348 /**
3349  * i40e_aq_send_msg_to_vf
3350  * @hw: pointer to the hardware structure
3351  * @vfid: vf id to send msg
3352  * @v_opcode: opcodes for VF-PF communication
3353  * @v_retval: return error code
3354  * @msg: pointer to the msg buffer
3355  * @msglen: msg length
3356  * @cmd_details: pointer to command details
3357  *
3358  * send msg to vf
3359  **/
3360 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3361                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3362                                 struct i40e_asq_cmd_details *cmd_details)
3363 {
3364         struct i40e_aq_desc desc;
3365         struct i40e_aqc_pf_vf_message *cmd =
3366                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3367         enum i40e_status_code status;
3368
3369         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3370         cmd->id = CPU_TO_LE32(vfid);
3371         desc.cookie_high = CPU_TO_LE32(v_opcode);
3372         desc.cookie_low = CPU_TO_LE32(v_retval);
3373         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3374         if (msglen) {
3375                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3376                                                 I40E_AQ_FLAG_RD));
3377                 if (msglen > I40E_AQ_LARGE_BUF)
3378                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3379                 desc.datalen = CPU_TO_LE16(msglen);
3380         }
3381         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3382
3383         return status;
3384 }
3385
3386 /**
3387  * i40e_aq_debug_read_register
3388  * @hw: pointer to the hw struct
3389  * @reg_addr: register address
3390  * @reg_val: register value
3391  * @cmd_details: pointer to command details structure or NULL
3392  *
3393  * Read the register using the admin queue commands
3394  **/
3395 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3396                                 u32 reg_addr, u64 *reg_val,
3397                                 struct i40e_asq_cmd_details *cmd_details)
3398 {
3399         struct i40e_aq_desc desc;
3400         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3401                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3402         enum i40e_status_code status;
3403
3404         if (reg_val == NULL)
3405                 return I40E_ERR_PARAM;
3406
3407         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3408
3409         cmd_resp->address = CPU_TO_LE32(reg_addr);
3410
3411         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3412
3413         if (status == I40E_SUCCESS) {
3414                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3415                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3416         }
3417
3418         return status;
3419 }
3420
3421 /**
3422  * i40e_aq_debug_write_register
3423  * @hw: pointer to the hw struct
3424  * @reg_addr: register address
3425  * @reg_val: register value
3426  * @cmd_details: pointer to command details structure or NULL
3427  *
3428  * Write to a register using the admin queue commands
3429  **/
3430 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3431                                 u32 reg_addr, u64 reg_val,
3432                                 struct i40e_asq_cmd_details *cmd_details)
3433 {
3434         struct i40e_aq_desc desc;
3435         struct i40e_aqc_debug_reg_read_write *cmd =
3436                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3437         enum i40e_status_code status;
3438
3439         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3440
3441         cmd->address = CPU_TO_LE32(reg_addr);
3442         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3443         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3444
3445         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3446
3447         return status;
3448 }
3449
3450 /**
3451  * i40e_aq_request_resource
3452  * @hw: pointer to the hw struct
3453  * @resource: resource id
3454  * @access: access type
3455  * @sdp_number: resource number
3456  * @timeout: the maximum time in ms that the driver may hold the resource
3457  * @cmd_details: pointer to command details structure or NULL
3458  *
3459  * requests common resource using the admin queue commands
3460  **/
3461 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3462                                 enum i40e_aq_resources_ids resource,
3463                                 enum i40e_aq_resource_access_type access,
3464                                 u8 sdp_number, u64 *timeout,
3465                                 struct i40e_asq_cmd_details *cmd_details)
3466 {
3467         struct i40e_aq_desc desc;
3468         struct i40e_aqc_request_resource *cmd_resp =
3469                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3470         enum i40e_status_code status;
3471
3472         DEBUGFUNC("i40e_aq_request_resource");
3473
3474         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3475
3476         cmd_resp->resource_id = CPU_TO_LE16(resource);
3477         cmd_resp->access_type = CPU_TO_LE16(access);
3478         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3479
3480         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3481         /* The completion specifies the maximum time in ms that the driver
3482          * may hold the resource in the Timeout field.
3483          * If the resource is held by someone else, the command completes with
3484          * busy return value and the timeout field indicates the maximum time
3485          * the current owner of the resource has to free it.
3486          */
3487         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3488                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3489
3490         return status;
3491 }
3492
3493 /**
3494  * i40e_aq_release_resource
3495  * @hw: pointer to the hw struct
3496  * @resource: resource id
3497  * @sdp_number: resource number
3498  * @cmd_details: pointer to command details structure or NULL
3499  *
3500  * release common resource using the admin queue commands
3501  **/
3502 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3503                                 enum i40e_aq_resources_ids resource,
3504                                 u8 sdp_number,
3505                                 struct i40e_asq_cmd_details *cmd_details)
3506 {
3507         struct i40e_aq_desc desc;
3508         struct i40e_aqc_request_resource *cmd =
3509                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3510         enum i40e_status_code status;
3511
3512         DEBUGFUNC("i40e_aq_release_resource");
3513
3514         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3515
3516         cmd->resource_id = CPU_TO_LE16(resource);
3517         cmd->resource_number = CPU_TO_LE32(sdp_number);
3518
3519         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3520
3521         return status;
3522 }
3523
3524 /**
3525  * i40e_aq_read_nvm
3526  * @hw: pointer to the hw struct
3527  * @module_pointer: module pointer location in words from the NVM beginning
3528  * @offset: byte offset from the module beginning
3529  * @length: length of the section to be read (in bytes from the offset)
3530  * @data: command buffer (size [bytes] = length)
3531  * @last_command: tells if this is the last command in a series
3532  * @cmd_details: pointer to command details structure or NULL
3533  *
3534  * Read the NVM using the admin queue commands
3535  **/
3536 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3537                                 u32 offset, u16 length, void *data,
3538                                 bool last_command,
3539                                 struct i40e_asq_cmd_details *cmd_details)
3540 {
3541         struct i40e_aq_desc desc;
3542         struct i40e_aqc_nvm_update *cmd =
3543                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3544         enum i40e_status_code status;
3545
3546         DEBUGFUNC("i40e_aq_read_nvm");
3547
3548         /* In offset the highest byte must be zeroed. */
3549         if (offset & 0xFF000000) {
3550                 status = I40E_ERR_PARAM;
3551                 goto i40e_aq_read_nvm_exit;
3552         }
3553
3554         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3555
3556         /* If this is the last command in a series, set the proper flag. */
3557         if (last_command)
3558                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3559         cmd->module_pointer = module_pointer;
3560         cmd->offset = CPU_TO_LE32(offset);
3561         cmd->length = CPU_TO_LE16(length);
3562
3563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3564         if (length > I40E_AQ_LARGE_BUF)
3565                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3566
3567         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3568
3569 i40e_aq_read_nvm_exit:
3570         return status;
3571 }
3572
3573 /**
3574  * i40e_aq_read_nvm_config - read an nvm config block
3575  * @hw: pointer to the hw struct
3576  * @cmd_flags: NVM access admin command bits
3577  * @field_id: field or feature id
3578  * @data: buffer for result
3579  * @buf_size: buffer size
3580  * @element_count: pointer to count of elements read by FW
3581  * @cmd_details: pointer to command details structure or NULL
3582  **/
3583 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3584                                 u8 cmd_flags, u32 field_id, void *data,
3585                                 u16 buf_size, u16 *element_count,
3586                                 struct i40e_asq_cmd_details *cmd_details)
3587 {
3588         struct i40e_aq_desc desc;
3589         struct i40e_aqc_nvm_config_read *cmd =
3590                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3591         enum i40e_status_code status;
3592
3593         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3594         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3595         if (buf_size > I40E_AQ_LARGE_BUF)
3596                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3597
3598         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3599         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3600         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3601                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3602         else
3603                 cmd->element_id_msw = 0;
3604
3605         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3606
3607         if (!status && element_count)
3608                 *element_count = LE16_TO_CPU(cmd->element_count);
3609
3610         return status;
3611 }
3612
3613 /**
3614  * i40e_aq_write_nvm_config - write an nvm config block
3615  * @hw: pointer to the hw struct
3616  * @cmd_flags: NVM access admin command bits
3617  * @data: buffer for result
3618  * @buf_size: buffer size
3619  * @element_count: count of elements to be written
3620  * @cmd_details: pointer to command details structure or NULL
3621  **/
3622 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3623                                 u8 cmd_flags, void *data, u16 buf_size,
3624                                 u16 element_count,
3625                                 struct i40e_asq_cmd_details *cmd_details)
3626 {
3627         struct i40e_aq_desc desc;
3628         struct i40e_aqc_nvm_config_write *cmd =
3629                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3630         enum i40e_status_code status;
3631
3632         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3633         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3634         if (buf_size > I40E_AQ_LARGE_BUF)
3635                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3636
3637         cmd->element_count = CPU_TO_LE16(element_count);
3638         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3639         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3640
3641         return status;
3642 }
3643
3644 /**
3645  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3646  * @hw: pointer to the hw struct
3647  * @buff: buffer for result
3648  * @buff_size: buffer size
3649  * @cmd_details: pointer to command details structure or NULL
3650  **/
3651 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3652                                 void *buff, u16 buff_size,
3653                                 struct i40e_asq_cmd_details *cmd_details)
3654 {
3655         struct i40e_aq_desc desc;
3656         enum i40e_status_code status;
3657
3658         UNREFERENCED_2PARAMETER(buff, buff_size);
3659
3660         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3661         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3662         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3663                 status = I40E_ERR_NOT_IMPLEMENTED;
3664
3665         return status;
3666 }
3667
3668 /**
3669  * i40e_aq_erase_nvm
3670  * @hw: pointer to the hw struct
3671  * @module_pointer: module pointer location in words from the NVM beginning
3672  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3673  * @length: length of the section to be erased (expressed in 4 KB)
3674  * @last_command: tells if this is the last command in a series
3675  * @cmd_details: pointer to command details structure or NULL
3676  *
3677  * Erase the NVM sector using the admin queue commands
3678  **/
3679 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3680                                 u32 offset, u16 length, bool last_command,
3681                                 struct i40e_asq_cmd_details *cmd_details)
3682 {
3683         struct i40e_aq_desc desc;
3684         struct i40e_aqc_nvm_update *cmd =
3685                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3686         enum i40e_status_code status;
3687
3688         DEBUGFUNC("i40e_aq_erase_nvm");
3689
3690         /* In offset the highest byte must be zeroed. */
3691         if (offset & 0xFF000000) {
3692                 status = I40E_ERR_PARAM;
3693                 goto i40e_aq_erase_nvm_exit;
3694         }
3695
3696         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3697
3698         /* If this is the last command in a series, set the proper flag. */
3699         if (last_command)
3700                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3701         cmd->module_pointer = module_pointer;
3702         cmd->offset = CPU_TO_LE32(offset);
3703         cmd->length = CPU_TO_LE16(length);
3704
3705         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3706
3707 i40e_aq_erase_nvm_exit:
3708         return status;
3709 }
3710
3711 /**
3712  * i40e_parse_discover_capabilities
3713  * @hw: pointer to the hw struct
3714  * @buff: pointer to a buffer containing device/function capability records
3715  * @cap_count: number of capability records in the list
3716  * @list_type_opc: type of capabilities list to parse
3717  *
3718  * Parse the device/function capabilities list.
3719  **/
3720 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3721                                      u32 cap_count,
3722                                      enum i40e_admin_queue_opc list_type_opc)
3723 {
3724         struct i40e_aqc_list_capabilities_element_resp *cap;
3725         u32 valid_functions, num_functions;
3726         u32 number, logical_id, phys_id;
3727         struct i40e_hw_capabilities *p;
3728         enum i40e_status_code status;
3729         u16 id, ocp_cfg_word0;
3730         u8 major_rev;
3731         u32 i = 0;
3732
3733         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3734
3735         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3736                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3737         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3738                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3739         else
3740                 return;
3741
3742         for (i = 0; i < cap_count; i++, cap++) {
3743                 id = LE16_TO_CPU(cap->id);
3744                 number = LE32_TO_CPU(cap->number);
3745                 logical_id = LE32_TO_CPU(cap->logical_id);
3746                 phys_id = LE32_TO_CPU(cap->phys_id);
3747                 major_rev = cap->major_rev;
3748
3749                 switch (id) {
3750                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3751                         p->switch_mode = number;
3752                         i40e_debug(hw, I40E_DEBUG_INIT,
3753                                    "HW Capability: Switch mode = %d\n",
3754                                    p->switch_mode);
3755                         break;
3756                 case I40E_AQ_CAP_ID_MNG_MODE:
3757                         p->management_mode = number;
3758                         if (major_rev > 1) {
3759                                 p->mng_protocols_over_mctp = logical_id;
3760                                 i40e_debug(hw, I40E_DEBUG_INIT,
3761                                            "HW Capability: Protocols over MCTP = %d\n",
3762                                            p->mng_protocols_over_mctp);
3763                         } else {
3764                                 p->mng_protocols_over_mctp = 0;
3765                         }
3766                         i40e_debug(hw, I40E_DEBUG_INIT,
3767                                    "HW Capability: Management Mode = %d\n",
3768                                    p->management_mode);
3769                         break;
3770                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3771                         p->npar_enable = number;
3772                         i40e_debug(hw, I40E_DEBUG_INIT,
3773                                    "HW Capability: NPAR enable = %d\n",
3774                                    p->npar_enable);
3775                         break;
3776                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3777                         p->os2bmc = number;
3778                         i40e_debug(hw, I40E_DEBUG_INIT,
3779                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3780                         break;
3781                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3782                         p->valid_functions = number;
3783                         i40e_debug(hw, I40E_DEBUG_INIT,
3784                                    "HW Capability: Valid Functions = %d\n",
3785                                    p->valid_functions);
3786                         break;
3787                 case I40E_AQ_CAP_ID_SRIOV:
3788                         if (number == 1)
3789                                 p->sr_iov_1_1 = true;
3790                         i40e_debug(hw, I40E_DEBUG_INIT,
3791                                    "HW Capability: SR-IOV = %d\n",
3792                                    p->sr_iov_1_1);
3793                         break;
3794                 case I40E_AQ_CAP_ID_VF:
3795                         p->num_vfs = number;
3796                         p->vf_base_id = logical_id;
3797                         i40e_debug(hw, I40E_DEBUG_INIT,
3798                                    "HW Capability: VF count = %d\n",
3799                                    p->num_vfs);
3800                         i40e_debug(hw, I40E_DEBUG_INIT,
3801                                    "HW Capability: VF base_id = %d\n",
3802                                    p->vf_base_id);
3803                         break;
3804                 case I40E_AQ_CAP_ID_VMDQ:
3805                         if (number == 1)
3806                                 p->vmdq = true;
3807                         i40e_debug(hw, I40E_DEBUG_INIT,
3808                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3809                         break;
3810                 case I40E_AQ_CAP_ID_8021QBG:
3811                         if (number == 1)
3812                                 p->evb_802_1_qbg = true;
3813                         i40e_debug(hw, I40E_DEBUG_INIT,
3814                                    "HW Capability: 802.1Qbg = %d\n", number);
3815                         break;
3816                 case I40E_AQ_CAP_ID_8021QBR:
3817                         if (number == 1)
3818                                 p->evb_802_1_qbh = true;
3819                         i40e_debug(hw, I40E_DEBUG_INIT,
3820                                    "HW Capability: 802.1Qbh = %d\n", number);
3821                         break;
3822                 case I40E_AQ_CAP_ID_VSI:
3823                         p->num_vsis = number;
3824                         i40e_debug(hw, I40E_DEBUG_INIT,
3825                                    "HW Capability: VSI count = %d\n",
3826                                    p->num_vsis);
3827                         break;
3828                 case I40E_AQ_CAP_ID_DCB:
3829                         if (number == 1) {
3830                                 p->dcb = true;
3831                                 p->enabled_tcmap = logical_id;
3832                                 p->maxtc = phys_id;
3833                         }
3834                         i40e_debug(hw, I40E_DEBUG_INIT,
3835                                    "HW Capability: DCB = %d\n", p->dcb);
3836                         i40e_debug(hw, I40E_DEBUG_INIT,
3837                                    "HW Capability: TC Mapping = %d\n",
3838                                    logical_id);
3839                         i40e_debug(hw, I40E_DEBUG_INIT,
3840                                    "HW Capability: TC Max = %d\n", p->maxtc);
3841                         break;
3842                 case I40E_AQ_CAP_ID_FCOE:
3843                         if (number == 1)
3844                                 p->fcoe = true;
3845                         i40e_debug(hw, I40E_DEBUG_INIT,
3846                                    "HW Capability: FCOE = %d\n", p->fcoe);
3847                         break;
3848                 case I40E_AQ_CAP_ID_ISCSI:
3849                         if (number == 1)
3850                                 p->iscsi = true;
3851                         i40e_debug(hw, I40E_DEBUG_INIT,
3852                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3853                         break;
3854                 case I40E_AQ_CAP_ID_RSS:
3855                         p->rss = true;
3856                         p->rss_table_size = number;
3857                         p->rss_table_entry_width = logical_id;
3858                         i40e_debug(hw, I40E_DEBUG_INIT,
3859                                    "HW Capability: RSS = %d\n", p->rss);
3860                         i40e_debug(hw, I40E_DEBUG_INIT,
3861                                    "HW Capability: RSS table size = %d\n",
3862                                    p->rss_table_size);
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: RSS table width = %d\n",
3865                                    p->rss_table_entry_width);
3866                         break;
3867                 case I40E_AQ_CAP_ID_RXQ:
3868                         p->num_rx_qp = number;
3869                         p->base_queue = phys_id;
3870                         i40e_debug(hw, I40E_DEBUG_INIT,
3871                                    "HW Capability: Rx QP = %d\n", number);
3872                         i40e_debug(hw, I40E_DEBUG_INIT,
3873                                    "HW Capability: base_queue = %d\n",
3874                                    p->base_queue);
3875                         break;
3876                 case I40E_AQ_CAP_ID_TXQ:
3877                         p->num_tx_qp = number;
3878                         p->base_queue = phys_id;
3879                         i40e_debug(hw, I40E_DEBUG_INIT,
3880                                    "HW Capability: Tx QP = %d\n", number);
3881                         i40e_debug(hw, I40E_DEBUG_INIT,
3882                                    "HW Capability: base_queue = %d\n",
3883                                    p->base_queue);
3884                         break;
3885                 case I40E_AQ_CAP_ID_MSIX:
3886                         p->num_msix_vectors = number;
3887                         i40e_debug(hw, I40E_DEBUG_INIT,
3888                                    "HW Capability: MSIX vector count = %d\n",
3889                                    p->num_msix_vectors);
3890                         break;
3891                 case I40E_AQ_CAP_ID_VF_MSIX:
3892                         p->num_msix_vectors_vf = number;
3893                         i40e_debug(hw, I40E_DEBUG_INIT,
3894                                    "HW Capability: MSIX VF vector count = %d\n",
3895                                    p->num_msix_vectors_vf);
3896                         break;
3897                 case I40E_AQ_CAP_ID_FLEX10:
3898                         if (major_rev == 1) {
3899                                 if (number == 1) {
3900                                         p->flex10_enable = true;
3901                                         p->flex10_capable = true;
3902                                 }
3903                         } else {
3904                                 /* Capability revision >= 2 */
3905                                 if (number & 1)
3906                                         p->flex10_enable = true;
3907                                 if (number & 2)
3908                                         p->flex10_capable = true;
3909                         }
3910                         p->flex10_mode = logical_id;
3911                         p->flex10_status = phys_id;
3912                         i40e_debug(hw, I40E_DEBUG_INIT,
3913                                    "HW Capability: Flex10 mode = %d\n",
3914                                    p->flex10_mode);
3915                         i40e_debug(hw, I40E_DEBUG_INIT,
3916                                    "HW Capability: Flex10 status = %d\n",
3917                                    p->flex10_status);
3918                         break;
3919                 case I40E_AQ_CAP_ID_CEM:
3920                         if (number == 1)
3921                                 p->mgmt_cem = true;
3922                         i40e_debug(hw, I40E_DEBUG_INIT,
3923                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3924                         break;
3925                 case I40E_AQ_CAP_ID_IWARP:
3926                         if (number == 1)
3927                                 p->iwarp = true;
3928                         i40e_debug(hw, I40E_DEBUG_INIT,
3929                                    "HW Capability: iWARP = %d\n", p->iwarp);
3930                         break;
3931                 case I40E_AQ_CAP_ID_LED:
3932                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3933                                 p->led[phys_id] = true;
3934                         i40e_debug(hw, I40E_DEBUG_INIT,
3935                                    "HW Capability: LED - PIN %d\n", phys_id);
3936                         break;
3937                 case I40E_AQ_CAP_ID_SDP:
3938                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3939                                 p->sdp[phys_id] = true;
3940                         i40e_debug(hw, I40E_DEBUG_INIT,
3941                                    "HW Capability: SDP - PIN %d\n", phys_id);
3942                         break;
3943                 case I40E_AQ_CAP_ID_MDIO:
3944                         if (number == 1) {
3945                                 p->mdio_port_num = phys_id;
3946                                 p->mdio_port_mode = logical_id;
3947                         }
3948                         i40e_debug(hw, I40E_DEBUG_INIT,
3949                                    "HW Capability: MDIO port number = %d\n",
3950                                    p->mdio_port_num);
3951                         i40e_debug(hw, I40E_DEBUG_INIT,
3952                                    "HW Capability: MDIO port mode = %d\n",
3953                                    p->mdio_port_mode);
3954                         break;
3955                 case I40E_AQ_CAP_ID_1588:
3956                         if (number == 1)
3957                                 p->ieee_1588 = true;
3958                         i40e_debug(hw, I40E_DEBUG_INIT,
3959                                    "HW Capability: IEEE 1588 = %d\n",
3960                                    p->ieee_1588);
3961                         break;
3962                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3963                         p->fd = true;
3964                         p->fd_filters_guaranteed = number;
3965                         p->fd_filters_best_effort = logical_id;
3966                         i40e_debug(hw, I40E_DEBUG_INIT,
3967                                    "HW Capability: Flow Director = 1\n");
3968                         i40e_debug(hw, I40E_DEBUG_INIT,
3969                                    "HW Capability: Guaranteed FD filters = %d\n",
3970                                    p->fd_filters_guaranteed);
3971                         break;
3972                 case I40E_AQ_CAP_ID_WSR_PROT:
3973                         p->wr_csr_prot = (u64)number;
3974                         p->wr_csr_prot |= (u64)logical_id << 32;
3975                         i40e_debug(hw, I40E_DEBUG_INIT,
3976                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3977                                    (p->wr_csr_prot & 0xffff));
3978                         break;
3979                 case I40E_AQ_CAP_ID_NVM_MGMT:
3980                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3981                                 p->sec_rev_disabled = true;
3982                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3983                                 p->update_disabled = true;
3984                         break;
3985                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3986                         hw->num_wol_proxy_filters = (u16)number;
3987                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3988                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3989                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3990                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3991                         else
3992                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3993                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3994                         i40e_debug(hw, I40E_DEBUG_INIT,
3995                                    "HW Capability: WOL proxy filters = %d\n",
3996                                    hw->num_wol_proxy_filters);
3997                         break;
3998                 default:
3999                         break;
4000                 }
4001         }
4002
4003         if (p->fcoe)
4004                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4005
4006         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4007         p->fcoe = false;
4008
4009         /* count the enabled ports (aka the "not disabled" ports) */
4010         hw->num_ports = 0;
4011         for (i = 0; i < 4; i++) {
4012                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4013                 u64 port_cfg = 0;
4014
4015                 /* use AQ read to get the physical register offset instead
4016                  * of the port relative offset
4017                  */
4018                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4019                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4020                         hw->num_ports++;
4021         }
4022
4023         /* OCP cards case: if a mezz is removed the ethernet port is at
4024          * disabled state in PRTGEN_CNF register. Additional NVM read is
4025          * needed in order to check if we are dealing with OCP card.
4026          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4027          * physical ports results in wrong partition id calculation and thus
4028          * not supporting WoL.
4029          */
4030         if (hw->mac.type == I40E_MAC_X722) {
4031                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4032                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4033                                                   2 * I40E_SR_OCP_CFG_WORD0,
4034                                                   sizeof(ocp_cfg_word0),
4035                                                   &ocp_cfg_word0, true, NULL);
4036                         if (status == I40E_SUCCESS &&
4037                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4038                                 hw->num_ports = 4;
4039                         i40e_release_nvm(hw);
4040                 }
4041         }
4042
4043         valid_functions = p->valid_functions;
4044         num_functions = 0;
4045         while (valid_functions) {
4046                 if (valid_functions & 1)
4047                         num_functions++;
4048                 valid_functions >>= 1;
4049         }
4050
4051         /* partition id is 1-based, and functions are evenly spread
4052          * across the ports as partitions
4053          */
4054         if (hw->num_ports != 0) {
4055                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4056                 hw->num_partitions = num_functions / hw->num_ports;
4057         }
4058
4059         /* additional HW specific goodies that might
4060          * someday be HW version specific
4061          */
4062         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4063 }
4064
4065 /**
4066  * i40e_aq_discover_capabilities
4067  * @hw: pointer to the hw struct
4068  * @buff: a virtual buffer to hold the capabilities
4069  * @buff_size: Size of the virtual buffer
4070  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4071  * @list_type_opc: capabilities type to discover - pass in the command opcode
4072  * @cmd_details: pointer to command details structure or NULL
4073  *
4074  * Get the device capabilities descriptions from the firmware
4075  **/
4076 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4077                                 void *buff, u16 buff_size, u16 *data_size,
4078                                 enum i40e_admin_queue_opc list_type_opc,
4079                                 struct i40e_asq_cmd_details *cmd_details)
4080 {
4081         struct i40e_aqc_list_capabilites *cmd;
4082         struct i40e_aq_desc desc;
4083         enum i40e_status_code status = I40E_SUCCESS;
4084
4085         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4086
4087         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4088                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4089                 status = I40E_ERR_PARAM;
4090                 goto exit;
4091         }
4092
4093         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4094
4095         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4096         if (buff_size > I40E_AQ_LARGE_BUF)
4097                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4098
4099         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4100         *data_size = LE16_TO_CPU(desc.datalen);
4101
4102         if (status)
4103                 goto exit;
4104
4105         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4106                                          list_type_opc);
4107
4108 exit:
4109         return status;
4110 }
4111
4112 /**
4113  * i40e_aq_update_nvm
4114  * @hw: pointer to the hw struct
4115  * @module_pointer: module pointer location in words from the NVM beginning
4116  * @offset: byte offset from the module beginning
4117  * @length: length of the section to be written (in bytes from the offset)
4118  * @data: command buffer (size [bytes] = length)
4119  * @last_command: tells if this is the last command in a series
4120  * @preservation_flags: Preservation mode flags
4121  * @cmd_details: pointer to command details structure or NULL
4122  *
4123  * Update the NVM using the admin queue commands
4124  **/
4125 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4126                                 u32 offset, u16 length, void *data,
4127                                 bool last_command, u8 preservation_flags,
4128                                 struct i40e_asq_cmd_details *cmd_details)
4129 {
4130         struct i40e_aq_desc desc;
4131         struct i40e_aqc_nvm_update *cmd =
4132                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4133         enum i40e_status_code status;
4134
4135         DEBUGFUNC("i40e_aq_update_nvm");
4136
4137         /* In offset the highest byte must be zeroed. */
4138         if (offset & 0xFF000000) {
4139                 status = I40E_ERR_PARAM;
4140                 goto i40e_aq_update_nvm_exit;
4141         }
4142
4143         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4144
4145         /* If this is the last command in a series, set the proper flag. */
4146         if (last_command)
4147                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4148         if (hw->mac.type == I40E_MAC_X722) {
4149                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4150                         cmd->command_flags |=
4151                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4152                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4153                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4154                         cmd->command_flags |=
4155                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4156                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4157         }
4158         cmd->module_pointer = module_pointer;
4159         cmd->offset = CPU_TO_LE32(offset);
4160         cmd->length = CPU_TO_LE16(length);
4161
4162         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4163         if (length > I40E_AQ_LARGE_BUF)
4164                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4165
4166         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4167
4168 i40e_aq_update_nvm_exit:
4169         return status;
4170 }
4171
4172 /**
4173  * i40e_aq_rearrange_nvm
4174  * @hw: pointer to the hw struct
4175  * @rearrange_nvm: defines direction of rearrangement
4176  * @cmd_details: pointer to command details structure or NULL
4177  *
4178  * Rearrange NVM structure, available only for transition FW
4179  **/
4180 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4181                                 u8 rearrange_nvm,
4182                                 struct i40e_asq_cmd_details *cmd_details)
4183 {
4184         struct i40e_aqc_nvm_update *cmd;
4185         enum i40e_status_code status;
4186         struct i40e_aq_desc desc;
4187
4188         DEBUGFUNC("i40e_aq_rearrange_nvm");
4189
4190         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4191
4192         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4193
4194         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4195                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4196
4197         if (!rearrange_nvm) {
4198                 status = I40E_ERR_PARAM;
4199                 goto i40e_aq_rearrange_nvm_exit;
4200         }
4201
4202         cmd->command_flags |= rearrange_nvm;
4203         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4204
4205 i40e_aq_rearrange_nvm_exit:
4206         return status;
4207 }
4208
4209 /**
4210  * i40e_aq_nvm_progress
4211  * @hw: pointer to the hw struct
4212  * @progress: pointer to progress returned from AQ
4213  * @cmd_details: pointer to command details structure or NULL
4214  *
4215  * Gets progress of flash rearrangement process
4216  **/
4217 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4218                                 struct i40e_asq_cmd_details *cmd_details)
4219 {
4220         enum i40e_status_code status;
4221         struct i40e_aq_desc desc;
4222
4223         DEBUGFUNC("i40e_aq_nvm_progress");
4224
4225         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4226         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4227         *progress = desc.params.raw[0];
4228         return status;
4229 }
4230
4231 /**
4232  * i40e_aq_get_lldp_mib
4233  * @hw: pointer to the hw struct
4234  * @bridge_type: type of bridge requested
4235  * @mib_type: Local, Remote or both Local and Remote MIBs
4236  * @buff: pointer to a user supplied buffer to store the MIB block
4237  * @buff_size: size of the buffer (in bytes)
4238  * @local_len : length of the returned Local LLDP MIB
4239  * @remote_len: length of the returned Remote LLDP MIB
4240  * @cmd_details: pointer to command details structure or NULL
4241  *
4242  * Requests the complete LLDP MIB (entire packet).
4243  **/
4244 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4245                                 u8 mib_type, void *buff, u16 buff_size,
4246                                 u16 *local_len, u16 *remote_len,
4247                                 struct i40e_asq_cmd_details *cmd_details)
4248 {
4249         struct i40e_aq_desc desc;
4250         struct i40e_aqc_lldp_get_mib *cmd =
4251                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4252         struct i40e_aqc_lldp_get_mib *resp =
4253                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4254         enum i40e_status_code status;
4255
4256         if (buff_size == 0 || !buff)
4257                 return I40E_ERR_PARAM;
4258
4259         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4260         /* Indirect Command */
4261         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4262
4263         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4264         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4265                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4266
4267         desc.datalen = CPU_TO_LE16(buff_size);
4268
4269         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4270         if (buff_size > I40E_AQ_LARGE_BUF)
4271                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4272
4273         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4274         if (!status) {
4275                 if (local_len != NULL)
4276                         *local_len = LE16_TO_CPU(resp->local_len);
4277                 if (remote_len != NULL)
4278                         *remote_len = LE16_TO_CPU(resp->remote_len);
4279         }
4280
4281         return status;
4282 }
4283
4284  /**
4285  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4286  * @hw: pointer to the hw struct
4287  * @mib_type: Local, Remote or both Local and Remote MIBs
4288  * @buff: pointer to a user supplied buffer to store the MIB block
4289  * @buff_size: size of the buffer (in bytes)
4290  * @cmd_details: pointer to command details structure or NULL
4291  *
4292  * Set the LLDP MIB.
4293  **/
4294 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4295                                 u8 mib_type, void *buff, u16 buff_size,
4296                                 struct i40e_asq_cmd_details *cmd_details)
4297 {
4298         struct i40e_aq_desc desc;
4299         struct i40e_aqc_lldp_set_local_mib *cmd =
4300                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4301         enum i40e_status_code status;
4302
4303         if (buff_size == 0 || !buff)
4304                 return I40E_ERR_PARAM;
4305
4306         i40e_fill_default_direct_cmd_desc(&desc,
4307                                 i40e_aqc_opc_lldp_set_local_mib);
4308         /* Indirect Command */
4309         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4310         if (buff_size > I40E_AQ_LARGE_BUF)
4311                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4312         desc.datalen = CPU_TO_LE16(buff_size);
4313
4314         cmd->type = mib_type;
4315         cmd->length = CPU_TO_LE16(buff_size);
4316         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4317         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4318
4319         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4320         return status;
4321 }
4322
4323 /**
4324  * i40e_aq_cfg_lldp_mib_change_event
4325  * @hw: pointer to the hw struct
4326  * @enable_update: Enable or Disable event posting
4327  * @cmd_details: pointer to command details structure or NULL
4328  *
4329  * Enable or Disable posting of an event on ARQ when LLDP MIB
4330  * associated with the interface changes
4331  **/
4332 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4333                                 bool enable_update,
4334                                 struct i40e_asq_cmd_details *cmd_details)
4335 {
4336         struct i40e_aq_desc desc;
4337         struct i40e_aqc_lldp_update_mib *cmd =
4338                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4339         enum i40e_status_code status;
4340
4341         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4342
4343         if (!enable_update)
4344                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4345
4346         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4347
4348         return status;
4349 }
4350
4351 /**
4352  * i40e_aq_restore_lldp
4353  * @hw: pointer to the hw struct
4354  * @setting: pointer to factory setting variable or NULL
4355  * @restore: True if factory settings should be restored
4356  * @cmd_details: pointer to command details structure or NULL
4357  *
4358  * Restore LLDP Agent factory settings if @restore set to True. In other case
4359  * only returns factory setting in AQ response.
4360  **/
4361 enum i40e_status_code
4362 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4363                      struct i40e_asq_cmd_details *cmd_details)
4364 {
4365         struct i40e_aq_desc desc;
4366         struct i40e_aqc_lldp_restore *cmd =
4367                 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4368         enum i40e_status_code status;
4369
4370         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4371                 i40e_debug(hw, I40E_DEBUG_ALL,
4372                            "Restore LLDP not supported by current FW version.\n");
4373                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4374         }
4375
4376         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4377
4378         if (restore)
4379                 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4380
4381         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4382
4383         if (setting)
4384                 *setting = cmd->command & 1;
4385
4386         return status;
4387 }
4388
4389 /**
4390  * i40e_aq_stop_lldp
4391  * @hw: pointer to the hw struct
4392  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4393  * @persist: True if stop of LLDP should be persistent across power cycles
4394  * @cmd_details: pointer to command details structure or NULL
4395  *
4396  * Stop or Shutdown the embedded LLDP Agent
4397  **/
4398 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4399                                 bool persist,
4400                                 struct i40e_asq_cmd_details *cmd_details)
4401 {
4402         struct i40e_aq_desc desc;
4403         struct i40e_aqc_lldp_stop *cmd =
4404                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4405         enum i40e_status_code status;
4406
4407         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4408
4409         if (shutdown_agent)
4410                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4411
4412         if (persist) {
4413                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4414                         cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4415                 else
4416                         i40e_debug(hw, I40E_DEBUG_ALL,
4417                                    "Persistent Stop LLDP not supported by current FW version.\n");
4418         }
4419
4420         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4421
4422         return status;
4423 }
4424
4425 /**
4426  * i40e_aq_start_lldp
4427  * @hw: pointer to the hw struct
4428  * @persist: True if start of LLDP should be persistent across power cycles
4429  * @cmd_details: pointer to command details structure or NULL
4430  *
4431  * Start the embedded LLDP Agent on all ports.
4432  **/
4433 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4434                                 bool persist,
4435                                 struct i40e_asq_cmd_details *cmd_details)
4436 {
4437         struct i40e_aq_desc desc;
4438         struct i40e_aqc_lldp_start *cmd =
4439                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4440         enum i40e_status_code status;
4441
4442         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4443
4444         cmd->command = I40E_AQ_LLDP_AGENT_START;
4445
4446         if (persist) {
4447                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4448                         cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4449                 else
4450                         i40e_debug(hw, I40E_DEBUG_ALL,
4451                                    "Persistent Start LLDP not supported by current FW version.\n");
4452         }
4453
4454         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4455
4456         return status;
4457 }
4458
4459 /**
4460  * i40e_aq_set_dcb_parameters
4461  * @hw: pointer to the hw struct
4462  * @cmd_details: pointer to command details structure or NULL
4463  * @dcb_enable: True if DCB configuration needs to be applied
4464  *
4465  **/
4466 enum i40e_status_code
4467 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4468                            struct i40e_asq_cmd_details *cmd_details)
4469 {
4470         struct i40e_aq_desc desc;
4471         struct i40e_aqc_set_dcb_parameters *cmd =
4472                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4473         enum i40e_status_code status;
4474
4475         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4476                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4477
4478         i40e_fill_default_direct_cmd_desc(&desc,
4479                                           i40e_aqc_opc_set_dcb_parameters);
4480
4481         if (dcb_enable) {
4482                 cmd->valid_flags = I40E_DCB_VALID;
4483                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4484         }
4485         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4486
4487         return status;
4488 }
4489
4490 /**
4491  * i40e_aq_get_cee_dcb_config
4492  * @hw: pointer to the hw struct
4493  * @buff: response buffer that stores CEE operational configuration
4494  * @buff_size: size of the buffer passed
4495  * @cmd_details: pointer to command details structure or NULL
4496  *
4497  * Get CEE DCBX mode operational configuration from firmware
4498  **/
4499 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4500                                 void *buff, u16 buff_size,
4501                                 struct i40e_asq_cmd_details *cmd_details)
4502 {
4503         struct i40e_aq_desc desc;
4504         enum i40e_status_code status;
4505
4506         if (buff_size == 0 || !buff)
4507                 return I40E_ERR_PARAM;
4508
4509         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4510
4511         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4512         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4513                                        cmd_details);
4514
4515         return status;
4516 }
4517
4518 /**
4519  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4520  * @hw: pointer to the hw struct
4521  * @start_agent: True if DCBx Agent needs to be Started
4522  *                              False if DCBx Agent needs to be Stopped
4523  * @cmd_details: pointer to command details structure or NULL
4524  *
4525  * Start/Stop the embedded dcbx Agent
4526  **/
4527 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4528                                 bool start_agent,
4529                                 struct i40e_asq_cmd_details *cmd_details)
4530 {
4531         struct i40e_aq_desc desc;
4532         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4533                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4534                                 &desc.params.raw;
4535         enum i40e_status_code status;
4536
4537         i40e_fill_default_direct_cmd_desc(&desc,
4538                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4539
4540         if (start_agent)
4541                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4542
4543         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4544
4545         return status;
4546 }
4547
4548 /**
4549  * i40e_aq_add_udp_tunnel
4550  * @hw: pointer to the hw struct
4551  * @udp_port: the UDP port to add in Host byte order
4552  * @protocol_index: protocol index type
4553  * @filter_index: pointer to filter index
4554  * @cmd_details: pointer to command details structure or NULL
4555  *
4556  * Note: Firmware expects the udp_port value to be in Little Endian format,
4557  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4558  * Little Endian order.
4559  **/
4560 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4561                                 u16 udp_port, u8 protocol_index,
4562                                 u8 *filter_index,
4563                                 struct i40e_asq_cmd_details *cmd_details)
4564 {
4565         struct i40e_aq_desc desc;
4566         struct i40e_aqc_add_udp_tunnel *cmd =
4567                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4568         struct i40e_aqc_del_udp_tunnel_completion *resp =
4569                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4570         enum i40e_status_code status;
4571
4572         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4573
4574         cmd->udp_port = CPU_TO_LE16(udp_port);
4575         cmd->protocol_type = protocol_index;
4576
4577         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4578
4579         if (!status && filter_index)
4580                 *filter_index = resp->index;
4581
4582         return status;
4583 }
4584
4585 /**
4586  * i40e_aq_del_udp_tunnel
4587  * @hw: pointer to the hw struct
4588  * @index: filter index
4589  * @cmd_details: pointer to command details structure or NULL
4590  **/
4591 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4592                                 struct i40e_asq_cmd_details *cmd_details)
4593 {
4594         struct i40e_aq_desc desc;
4595         struct i40e_aqc_remove_udp_tunnel *cmd =
4596                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4597         enum i40e_status_code status;
4598
4599         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4600
4601         cmd->index = index;
4602
4603         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4604
4605         return status;
4606 }
4607
4608 /**
4609  * i40e_aq_get_switch_resource_alloc (0x0204)
4610  * @hw: pointer to the hw struct
4611  * @num_entries: pointer to u8 to store the number of resource entries returned
4612  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4613  *        to store the resource information for all resource types.  Each
4614  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4615  * @count: size, in bytes, of the buffer provided
4616  * @cmd_details: pointer to command details structure or NULL
4617  *
4618  * Query the resources allocated to a function.
4619  **/
4620 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4621                         u8 *num_entries,
4622                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4623                         u16 count,
4624                         struct i40e_asq_cmd_details *cmd_details)
4625 {
4626         struct i40e_aq_desc desc;
4627         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4628                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4629         enum i40e_status_code status;
4630         u16 length = count * sizeof(*buf);
4631
4632         i40e_fill_default_direct_cmd_desc(&desc,
4633                                         i40e_aqc_opc_get_switch_resource_alloc);
4634
4635         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4636         if (length > I40E_AQ_LARGE_BUF)
4637                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4638
4639         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4640
4641         if (!status && num_entries)
4642                 *num_entries = cmd_resp->num_entries;
4643
4644         return status;
4645 }
4646
4647 /**
4648  * i40e_aq_delete_element - Delete switch element
4649  * @hw: pointer to the hw struct
4650  * @seid: the SEID to delete from the switch
4651  * @cmd_details: pointer to command details structure or NULL
4652  *
4653  * This deletes a switch element from the switch.
4654  **/
4655 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4656                                 struct i40e_asq_cmd_details *cmd_details)
4657 {
4658         struct i40e_aq_desc desc;
4659         struct i40e_aqc_switch_seid *cmd =
4660                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4661         enum i40e_status_code status;
4662
4663         if (seid == 0)
4664                 return I40E_ERR_PARAM;
4665
4666         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4667
4668         cmd->seid = CPU_TO_LE16(seid);
4669
4670         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4671
4672         return status;
4673 }
4674
4675 /**
4676  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4677  * @hw: pointer to the hw struct
4678  * @flags: component flags
4679  * @mac_seid: uplink seid (MAC SEID)
4680  * @vsi_seid: connected vsi seid
4681  * @ret_seid: seid of create pv component
4682  *
4683  * This instantiates an i40e port virtualizer with specified flags.
4684  * Depending on specified flags the port virtualizer can act as a
4685  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4686  */
4687 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4688                                        u16 mac_seid, u16 vsi_seid,
4689                                        u16 *ret_seid)
4690 {
4691         struct i40e_aq_desc desc;
4692         struct i40e_aqc_add_update_pv *cmd =
4693                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4694         struct i40e_aqc_add_update_pv_completion *resp =
4695                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4696         enum i40e_status_code status;
4697
4698         if (vsi_seid == 0)
4699                 return I40E_ERR_PARAM;
4700
4701         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4702         cmd->command_flags = CPU_TO_LE16(flags);
4703         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4704         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4705
4706         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4707         if (!status && ret_seid)
4708                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4709
4710         return status;
4711 }
4712
4713 /**
4714  * i40e_aq_add_tag - Add an S/E-tag
4715  * @hw: pointer to the hw struct
4716  * @direct_to_queue: should s-tag direct flow to a specific queue
4717  * @vsi_seid: VSI SEID to use this tag
4718  * @tag: value of the tag
4719  * @queue_num: queue number, only valid is direct_to_queue is true
4720  * @tags_used: return value, number of tags in use by this PF
4721  * @tags_free: return value, number of unallocated tags
4722  * @cmd_details: pointer to command details structure or NULL
4723  *
4724  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4725  * the number of tags allocated by the PF, and the number of unallocated
4726  * tags available.
4727  **/
4728 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4729                                 u16 vsi_seid, u16 tag, u16 queue_num,
4730                                 u16 *tags_used, u16 *tags_free,
4731                                 struct i40e_asq_cmd_details *cmd_details)
4732 {
4733         struct i40e_aq_desc desc;
4734         struct i40e_aqc_add_tag *cmd =
4735                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4736         struct i40e_aqc_add_remove_tag_completion *resp =
4737                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4738         enum i40e_status_code status;
4739
4740         if (vsi_seid == 0)
4741                 return I40E_ERR_PARAM;
4742
4743         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4744
4745         cmd->seid = CPU_TO_LE16(vsi_seid);
4746         cmd->tag = CPU_TO_LE16(tag);
4747         if (direct_to_queue) {
4748                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4749                 cmd->queue_number = CPU_TO_LE16(queue_num);
4750         }
4751
4752         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4753
4754         if (!status) {
4755                 if (tags_used != NULL)
4756                         *tags_used = LE16_TO_CPU(resp->tags_used);
4757                 if (tags_free != NULL)
4758                         *tags_free = LE16_TO_CPU(resp->tags_free);
4759         }
4760
4761         return status;
4762 }
4763
4764 /**
4765  * i40e_aq_remove_tag - Remove an S- or E-tag
4766  * @hw: pointer to the hw struct
4767  * @vsi_seid: VSI SEID this tag is associated with
4768  * @tag: value of the S-tag to delete
4769  * @tags_used: return value, number of tags in use by this PF
4770  * @tags_free: return value, number of unallocated tags
4771  * @cmd_details: pointer to command details structure or NULL
4772  *
4773  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4774  * the number of tags allocated by the PF, and the number of unallocated
4775  * tags available.
4776  **/
4777 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4778                                 u16 tag, u16 *tags_used, u16 *tags_free,
4779                                 struct i40e_asq_cmd_details *cmd_details)
4780 {
4781         struct i40e_aq_desc desc;
4782         struct i40e_aqc_remove_tag *cmd =
4783                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4784         struct i40e_aqc_add_remove_tag_completion *resp =
4785                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4786         enum i40e_status_code status;
4787
4788         if (vsi_seid == 0)
4789                 return I40E_ERR_PARAM;
4790
4791         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4792
4793         cmd->seid = CPU_TO_LE16(vsi_seid);
4794         cmd->tag = CPU_TO_LE16(tag);
4795
4796         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4797
4798         if (!status) {
4799                 if (tags_used != NULL)
4800                         *tags_used = LE16_TO_CPU(resp->tags_used);
4801                 if (tags_free != NULL)
4802                         *tags_free = LE16_TO_CPU(resp->tags_free);
4803         }
4804
4805         return status;
4806 }
4807
4808 /**
4809  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4810  * @hw: pointer to the hw struct
4811  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4812  * @etag: value of E-tag to add
4813  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4814  * @buf: address of indirect buffer
4815  * @tags_used: return value, number of E-tags in use by this port
4816  * @tags_free: return value, number of unallocated M-tags
4817  * @cmd_details: pointer to command details structure or NULL
4818  *
4819  * This associates a multicast E-tag to a port virtualizer.  It will return
4820  * the number of tags allocated by the PF, and the number of unallocated
4821  * tags available.
4822  *
4823  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4824  * num_tags_in_buf long.
4825  **/
4826 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4827                                 u16 etag, u8 num_tags_in_buf, void *buf,
4828                                 u16 *tags_used, u16 *tags_free,
4829                                 struct i40e_asq_cmd_details *cmd_details)
4830 {
4831         struct i40e_aq_desc desc;
4832         struct i40e_aqc_add_remove_mcast_etag *cmd =
4833                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4834         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4835            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4836         enum i40e_status_code status;
4837         u16 length = sizeof(u16) * num_tags_in_buf;
4838
4839         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4840                 return I40E_ERR_PARAM;
4841
4842         i40e_fill_default_direct_cmd_desc(&desc,
4843                                           i40e_aqc_opc_add_multicast_etag);
4844
4845         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4846         cmd->etag = CPU_TO_LE16(etag);
4847         cmd->num_unicast_etags = num_tags_in_buf;
4848
4849         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4850         if (length > I40E_AQ_LARGE_BUF)
4851                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4852
4853         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4854
4855         if (!status) {
4856                 if (tags_used != NULL)
4857                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4858                 if (tags_free != NULL)
4859                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4860         }
4861
4862         return status;
4863 }
4864
4865 /**
4866  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4867  * @hw: pointer to the hw struct
4868  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4869  * @etag: value of the E-tag to remove
4870  * @tags_used: return value, number of tags in use by this port
4871  * @tags_free: return value, number of unallocated tags
4872  * @cmd_details: pointer to command details structure or NULL
4873  *
4874  * This deletes an E-tag from the port virtualizer.  It will return
4875  * the number of tags allocated by the port, and the number of unallocated
4876  * tags available.
4877  **/
4878 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4879                                 u16 etag, u16 *tags_used, u16 *tags_free,
4880                                 struct i40e_asq_cmd_details *cmd_details)
4881 {
4882         struct i40e_aq_desc desc;
4883         struct i40e_aqc_add_remove_mcast_etag *cmd =
4884                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4885         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4886            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4887         enum i40e_status_code status;
4888
4889
4890         if (pv_seid == 0)
4891                 return I40E_ERR_PARAM;
4892
4893         i40e_fill_default_direct_cmd_desc(&desc,
4894                                           i40e_aqc_opc_remove_multicast_etag);
4895
4896         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4897         cmd->etag = CPU_TO_LE16(etag);
4898
4899         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4900
4901         if (!status) {
4902                 if (tags_used != NULL)
4903                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4904                 if (tags_free != NULL)
4905                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4906         }
4907
4908         return status;
4909 }
4910
4911 /**
4912  * i40e_aq_update_tag - Update an S/E-tag
4913  * @hw: pointer to the hw struct
4914  * @vsi_seid: VSI SEID using this S-tag
4915  * @old_tag: old tag value
4916  * @new_tag: new tag value
4917  * @tags_used: return value, number of tags in use by this PF
4918  * @tags_free: return value, number of unallocated tags
4919  * @cmd_details: pointer to command details structure or NULL
4920  *
4921  * This updates the value of the tag currently attached to this VSI
4922  * in the switch complex.  It will return the number of tags allocated
4923  * by the PF, and the number of unallocated tags available.
4924  **/
4925 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4926                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4927                                 u16 *tags_free,
4928                                 struct i40e_asq_cmd_details *cmd_details)
4929 {
4930         struct i40e_aq_desc desc;
4931         struct i40e_aqc_update_tag *cmd =
4932                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4933         struct i40e_aqc_update_tag_completion *resp =
4934                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4935         enum i40e_status_code status;
4936
4937         if (vsi_seid == 0)
4938                 return I40E_ERR_PARAM;
4939
4940         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4941
4942         cmd->seid = CPU_TO_LE16(vsi_seid);
4943         cmd->old_tag = CPU_TO_LE16(old_tag);
4944         cmd->new_tag = CPU_TO_LE16(new_tag);
4945
4946         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4947
4948         if (!status) {
4949                 if (tags_used != NULL)
4950                         *tags_used = LE16_TO_CPU(resp->tags_used);
4951                 if (tags_free != NULL)
4952                         *tags_free = LE16_TO_CPU(resp->tags_free);
4953         }
4954
4955         return status;
4956 }
4957
4958 /**
4959  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4960  * @hw: pointer to the hw struct
4961  * @tcmap: TC map for request/release any ignore PFC condition
4962  * @request: request or release ignore PFC condition
4963  * @tcmap_ret: return TCs for which PFC is currently ignored
4964  * @cmd_details: pointer to command details structure or NULL
4965  *
4966  * This sends out request/release to ignore PFC condition for a TC.
4967  * It will return the TCs for which PFC is currently ignored.
4968  **/
4969 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4970                                 bool request, u8 *tcmap_ret,
4971                                 struct i40e_asq_cmd_details *cmd_details)
4972 {
4973         struct i40e_aq_desc desc;
4974         struct i40e_aqc_pfc_ignore *cmd_resp =
4975                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4976         enum i40e_status_code status;
4977
4978         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4979
4980         if (request)
4981                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4982
4983         cmd_resp->tc_bitmap = tcmap;
4984
4985         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4986
4987         if (!status) {
4988                 if (tcmap_ret != NULL)
4989                         *tcmap_ret = cmd_resp->tc_bitmap;
4990         }
4991
4992         return status;
4993 }
4994
4995 /**
4996  * i40e_aq_dcb_updated - DCB Updated Command
4997  * @hw: pointer to the hw struct
4998  * @cmd_details: pointer to command details structure or NULL
4999  *
5000  * When LLDP is handled in PF this command is used by the PF
5001  * to notify EMP that a DCB setting is modified.
5002  * When LLDP is handled in EMP this command is used by the PF
5003  * to notify EMP whenever one of the following parameters get
5004  * modified:
5005  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5006  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5007  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5008  * EMP will return when the shared RPB settings have been
5009  * recomputed and modified. The retval field in the descriptor
5010  * will be set to 0 when RPB is modified.
5011  **/
5012 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5013                                 struct i40e_asq_cmd_details *cmd_details)
5014 {
5015         struct i40e_aq_desc desc;
5016         enum i40e_status_code status;
5017
5018         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5019
5020         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5021
5022         return status;
5023 }
5024
5025 /**
5026  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5027  * @hw: pointer to the hw struct
5028  * @seid: defines the SEID of the switch for which the stats are requested
5029  * @vlan_id: the VLAN ID for which the statistics are requested
5030  * @stat_index: index of the statistics counters block assigned to this VLAN
5031  * @cmd_details: pointer to command details structure or NULL
5032  *
5033  * XL710 supports 128 smonVlanStats counters.This command is used to
5034  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5035  * switch.
5036  **/
5037 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5038                                 u16 vlan_id, u16 *stat_index,
5039                                 struct i40e_asq_cmd_details *cmd_details)
5040 {
5041         struct i40e_aq_desc desc;
5042         struct i40e_aqc_add_remove_statistics *cmd_resp =
5043                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5044         enum i40e_status_code status;
5045
5046         if ((seid == 0) || (stat_index == NULL))
5047                 return I40E_ERR_PARAM;
5048
5049         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5050
5051         cmd_resp->seid = CPU_TO_LE16(seid);
5052         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5053
5054         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5055
5056         if (!status && stat_index)
5057                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5058
5059         return status;
5060 }
5061
5062 /**
5063  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5064  * @hw: pointer to the hw struct
5065  * @seid: defines the SEID of the switch for which the stats are requested
5066  * @vlan_id: the VLAN ID for which the statistics are requested
5067  * @stat_index: index of the statistics counters block assigned to this VLAN
5068  * @cmd_details: pointer to command details structure or NULL
5069  *
5070  * XL710 supports 128 smonVlanStats counters.This command is used to
5071  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5072  * switch.
5073  **/
5074 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5075                                 u16 vlan_id, u16 stat_index,
5076                                 struct i40e_asq_cmd_details *cmd_details)
5077 {
5078         struct i40e_aq_desc desc;
5079         struct i40e_aqc_add_remove_statistics *cmd =
5080                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5081         enum i40e_status_code status;
5082
5083         if (seid == 0)
5084                 return I40E_ERR_PARAM;
5085
5086         i40e_fill_default_direct_cmd_desc(&desc,
5087                                           i40e_aqc_opc_remove_statistics);
5088
5089         cmd->seid = CPU_TO_LE16(seid);
5090         cmd->vlan  = CPU_TO_LE16(vlan_id);
5091         cmd->stat_index = CPU_TO_LE16(stat_index);
5092
5093         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5094
5095         return status;
5096 }
5097
5098 /**
5099  * i40e_aq_set_port_parameters - set physical port parameters.
5100  * @hw: pointer to the hw struct
5101  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5102  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5103  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5104  * @double_vlan: if set double VLAN is enabled
5105  * @cmd_details: pointer to command details structure or NULL
5106  **/
5107 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5108                                 u16 bad_frame_vsi, bool save_bad_pac,
5109                                 bool pad_short_pac, bool double_vlan,
5110                                 struct i40e_asq_cmd_details *cmd_details)
5111 {
5112         struct i40e_aqc_set_port_parameters *cmd;
5113         enum i40e_status_code status;
5114         struct i40e_aq_desc desc;
5115         u16 command_flags = 0;
5116
5117         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5118
5119         i40e_fill_default_direct_cmd_desc(&desc,
5120                                           i40e_aqc_opc_set_port_parameters);
5121
5122         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5123         if (save_bad_pac)
5124                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5125         if (pad_short_pac)
5126                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5127         if (double_vlan)
5128                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5129         cmd->command_flags = CPU_TO_LE16(command_flags);
5130
5131         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5132
5133         return status;
5134 }
5135
5136 /**
5137  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5138  * @hw: pointer to the hw struct
5139  * @seid: seid for the physical port/switching component/vsi
5140  * @buff: Indirect buffer to hold data parameters and response
5141  * @buff_size: Indirect buffer size
5142  * @opcode: Tx scheduler AQ command opcode
5143  * @cmd_details: pointer to command details structure or NULL
5144  *
5145  * Generic command handler for Tx scheduler AQ commands
5146  **/
5147 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5148                                 void *buff, u16 buff_size,
5149                                  enum i40e_admin_queue_opc opcode,
5150                                 struct i40e_asq_cmd_details *cmd_details)
5151 {
5152         struct i40e_aq_desc desc;
5153         struct i40e_aqc_tx_sched_ind *cmd =
5154                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5155         enum i40e_status_code status;
5156         bool cmd_param_flag = false;
5157
5158         switch (opcode) {
5159         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5160         case i40e_aqc_opc_configure_vsi_tc_bw:
5161         case i40e_aqc_opc_enable_switching_comp_ets:
5162         case i40e_aqc_opc_modify_switching_comp_ets:
5163         case i40e_aqc_opc_disable_switching_comp_ets:
5164         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5165         case i40e_aqc_opc_configure_switching_comp_bw_config:
5166                 cmd_param_flag = true;
5167                 break;
5168         case i40e_aqc_opc_query_vsi_bw_config:
5169         case i40e_aqc_opc_query_vsi_ets_sla_config:
5170         case i40e_aqc_opc_query_switching_comp_ets_config:
5171         case i40e_aqc_opc_query_port_ets_config:
5172         case i40e_aqc_opc_query_switching_comp_bw_config:
5173                 cmd_param_flag = false;
5174                 break;
5175         default:
5176                 return I40E_ERR_PARAM;
5177         }
5178
5179         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5180
5181         /* Indirect command */
5182         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5183         if (cmd_param_flag)
5184                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5185         if (buff_size > I40E_AQ_LARGE_BUF)
5186                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5187
5188         desc.datalen = CPU_TO_LE16(buff_size);
5189
5190         cmd->vsi_seid = CPU_TO_LE16(seid);
5191
5192         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5193
5194         return status;
5195 }
5196
5197 /**
5198  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5199  * @hw: pointer to the hw struct
5200  * @seid: VSI seid
5201  * @credit: BW limit credits (0 = disabled)
5202  * @max_credit: Max BW limit credits
5203  * @cmd_details: pointer to command details structure or NULL
5204  **/
5205 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5206                                 u16 seid, u16 credit, u8 max_credit,
5207                                 struct i40e_asq_cmd_details *cmd_details)
5208 {
5209         struct i40e_aq_desc desc;
5210         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5211                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5212         enum i40e_status_code status;
5213
5214         i40e_fill_default_direct_cmd_desc(&desc,
5215                                           i40e_aqc_opc_configure_vsi_bw_limit);
5216
5217         cmd->vsi_seid = CPU_TO_LE16(seid);
5218         cmd->credit = CPU_TO_LE16(credit);
5219         cmd->max_credit = max_credit;
5220
5221         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5222
5223         return status;
5224 }
5225
5226 /**
5227  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5228  * @hw: pointer to the hw struct
5229  * @seid: switching component seid
5230  * @credit: BW limit credits (0 = disabled)
5231  * @max_bw: Max BW limit credits
5232  * @cmd_details: pointer to command details structure or NULL
5233  **/
5234 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5235                                 u16 seid, u16 credit, u8 max_bw,
5236                                 struct i40e_asq_cmd_details *cmd_details)
5237 {
5238         struct i40e_aq_desc desc;
5239         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5240           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5241         enum i40e_status_code status;
5242
5243         i40e_fill_default_direct_cmd_desc(&desc,
5244                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5245
5246         cmd->seid = CPU_TO_LE16(seid);
5247         cmd->credit = CPU_TO_LE16(credit);
5248         cmd->max_bw = max_bw;
5249
5250         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5251
5252         return status;
5253 }
5254
5255 /**
5256  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5257  * @hw: pointer to the hw struct
5258  * @seid: VSI seid
5259  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5260  * @cmd_details: pointer to command details structure or NULL
5261  **/
5262 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5263                         u16 seid,
5264                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5265                         struct i40e_asq_cmd_details *cmd_details)
5266 {
5267         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5268                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5269                                     cmd_details);
5270 }
5271
5272 /**
5273  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5274  * @hw: pointer to the hw struct
5275  * @seid: VSI seid
5276  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5277  * @cmd_details: pointer to command details structure or NULL
5278  **/
5279 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5280                         u16 seid,
5281                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5282                         struct i40e_asq_cmd_details *cmd_details)
5283 {
5284         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5285                                     i40e_aqc_opc_configure_vsi_tc_bw,
5286                                     cmd_details);
5287 }
5288
5289 /**
5290  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5291  * @hw: pointer to the hw struct
5292  * @seid: seid of the switching component connected to Physical Port
5293  * @ets_data: Buffer holding ETS parameters
5294  * @opcode: Tx scheduler AQ command opcode
5295  * @cmd_details: pointer to command details structure or NULL
5296  **/
5297 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5298                 u16 seid,
5299                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5300                 enum i40e_admin_queue_opc opcode,
5301                 struct i40e_asq_cmd_details *cmd_details)
5302 {
5303         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5304                                     sizeof(*ets_data), opcode, cmd_details);
5305 }
5306
5307 /**
5308  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5309  * @hw: pointer to the hw struct
5310  * @seid: seid of the switching component
5311  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5312  * @cmd_details: pointer to command details structure or NULL
5313  **/
5314 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5315         u16 seid,
5316         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5317         struct i40e_asq_cmd_details *cmd_details)
5318 {
5319         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5320                             i40e_aqc_opc_configure_switching_comp_bw_config,
5321                             cmd_details);
5322 }
5323
5324 /**
5325  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5326  * @hw: pointer to the hw struct
5327  * @seid: seid of the switching component
5328  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5329  * @cmd_details: pointer to command details structure or NULL
5330  **/
5331 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5332         struct i40e_hw *hw, u16 seid,
5333         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5334         struct i40e_asq_cmd_details *cmd_details)
5335 {
5336         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5337                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5338                             cmd_details);
5339 }
5340
5341 /**
5342  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5343  * @hw: pointer to the hw struct
5344  * @seid: seid of the VSI
5345  * @bw_data: Buffer to hold VSI BW configuration
5346  * @cmd_details: pointer to command details structure or NULL
5347  **/
5348 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5349                         u16 seid,
5350                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5351                         struct i40e_asq_cmd_details *cmd_details)
5352 {
5353         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5354                                     i40e_aqc_opc_query_vsi_bw_config,
5355                                     cmd_details);
5356 }
5357
5358 /**
5359  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5360  * @hw: pointer to the hw struct
5361  * @seid: seid of the VSI
5362  * @bw_data: Buffer to hold VSI BW configuration per TC
5363  * @cmd_details: pointer to command details structure or NULL
5364  **/
5365 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5366                         u16 seid,
5367                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5368                         struct i40e_asq_cmd_details *cmd_details)
5369 {
5370         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5371                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5372                                     cmd_details);
5373 }
5374
5375 /**
5376  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5377  * @hw: pointer to the hw struct
5378  * @seid: seid of the switching component
5379  * @bw_data: Buffer to hold switching component's per TC BW config
5380  * @cmd_details: pointer to command details structure or NULL
5381  **/
5382 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5383                 u16 seid,
5384                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5385                 struct i40e_asq_cmd_details *cmd_details)
5386 {
5387         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5388                                    i40e_aqc_opc_query_switching_comp_ets_config,
5389                                    cmd_details);
5390 }
5391
5392 /**
5393  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5394  * @hw: pointer to the hw struct
5395  * @seid: seid of the VSI or switching component connected to Physical Port
5396  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5397  * @cmd_details: pointer to command details structure or NULL
5398  **/
5399 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5400                         u16 seid,
5401                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5402                         struct i40e_asq_cmd_details *cmd_details)
5403 {
5404         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5405                                     i40e_aqc_opc_query_port_ets_config,
5406                                     cmd_details);
5407 }
5408
5409 /**
5410  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5411  * @hw: pointer to the hw struct
5412  * @seid: seid of the switching component
5413  * @bw_data: Buffer to hold switching component's BW configuration
5414  * @cmd_details: pointer to command details structure or NULL
5415  **/
5416 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5417                 u16 seid,
5418                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5419                 struct i40e_asq_cmd_details *cmd_details)
5420 {
5421         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5422                                     i40e_aqc_opc_query_switching_comp_bw_config,
5423                                     cmd_details);
5424 }
5425
5426 /**
5427  * i40e_validate_filter_settings
5428  * @hw: pointer to the hardware structure
5429  * @settings: Filter control settings
5430  *
5431  * Check and validate the filter control settings passed.
5432  * The function checks for the valid filter/context sizes being
5433  * passed for FCoE and PE.
5434  *
5435  * Returns I40E_SUCCESS if the values passed are valid and within
5436  * range else returns an error.
5437  **/
5438 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5439                                 struct i40e_filter_control_settings *settings)
5440 {
5441         u32 fcoe_cntx_size, fcoe_filt_size;
5442         u32 pe_cntx_size, pe_filt_size;
5443         u32 fcoe_fmax;
5444
5445         u32 val;
5446
5447         /* Validate FCoE settings passed */
5448         switch (settings->fcoe_filt_num) {
5449         case I40E_HASH_FILTER_SIZE_1K:
5450         case I40E_HASH_FILTER_SIZE_2K:
5451         case I40E_HASH_FILTER_SIZE_4K:
5452         case I40E_HASH_FILTER_SIZE_8K:
5453         case I40E_HASH_FILTER_SIZE_16K:
5454         case I40E_HASH_FILTER_SIZE_32K:
5455                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5456                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5457                 break;
5458         default:
5459                 return I40E_ERR_PARAM;
5460         }
5461
5462         switch (settings->fcoe_cntx_num) {
5463         case I40E_DMA_CNTX_SIZE_512:
5464         case I40E_DMA_CNTX_SIZE_1K:
5465         case I40E_DMA_CNTX_SIZE_2K:
5466         case I40E_DMA_CNTX_SIZE_4K:
5467                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5468                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5469                 break;
5470         default:
5471                 return I40E_ERR_PARAM;
5472         }
5473
5474         /* Validate PE settings passed */
5475         switch (settings->pe_filt_num) {
5476         case I40E_HASH_FILTER_SIZE_1K:
5477         case I40E_HASH_FILTER_SIZE_2K:
5478         case I40E_HASH_FILTER_SIZE_4K:
5479         case I40E_HASH_FILTER_SIZE_8K:
5480         case I40E_HASH_FILTER_SIZE_16K:
5481         case I40E_HASH_FILTER_SIZE_32K:
5482         case I40E_HASH_FILTER_SIZE_64K:
5483         case I40E_HASH_FILTER_SIZE_128K:
5484         case I40E_HASH_FILTER_SIZE_256K:
5485         case I40E_HASH_FILTER_SIZE_512K:
5486         case I40E_HASH_FILTER_SIZE_1M:
5487                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5488                 pe_filt_size <<= (u32)settings->pe_filt_num;
5489                 break;
5490         default:
5491                 return I40E_ERR_PARAM;
5492         }
5493
5494         switch (settings->pe_cntx_num) {
5495         case I40E_DMA_CNTX_SIZE_512:
5496         case I40E_DMA_CNTX_SIZE_1K:
5497         case I40E_DMA_CNTX_SIZE_2K:
5498         case I40E_DMA_CNTX_SIZE_4K:
5499         case I40E_DMA_CNTX_SIZE_8K:
5500         case I40E_DMA_CNTX_SIZE_16K:
5501         case I40E_DMA_CNTX_SIZE_32K:
5502         case I40E_DMA_CNTX_SIZE_64K:
5503         case I40E_DMA_CNTX_SIZE_128K:
5504         case I40E_DMA_CNTX_SIZE_256K:
5505                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5506                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5507                 break;
5508         default:
5509                 return I40E_ERR_PARAM;
5510         }
5511
5512         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5513         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5514         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5515                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5516         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5517                 return I40E_ERR_INVALID_SIZE;
5518
5519         return I40E_SUCCESS;
5520 }
5521
5522 /**
5523  * i40e_set_filter_control
5524  * @hw: pointer to the hardware structure
5525  * @settings: Filter control settings
5526  *
5527  * Set the Queue Filters for PE/FCoE and enable filters required
5528  * for a single PF. It is expected that these settings are programmed
5529  * at the driver initialization time.
5530  **/
5531 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5532                                 struct i40e_filter_control_settings *settings)
5533 {
5534         enum i40e_status_code ret = I40E_SUCCESS;
5535         u32 hash_lut_size = 0;
5536         u32 val;
5537
5538         if (!settings)
5539                 return I40E_ERR_PARAM;
5540
5541         /* Validate the input settings */
5542         ret = i40e_validate_filter_settings(hw, settings);
5543         if (ret)
5544                 return ret;
5545
5546         /* Read the PF Queue Filter control register */
5547         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5548
5549         /* Program required PE hash buckets for the PF */
5550         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5551         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5552                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5553         /* Program required PE contexts for the PF */
5554         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5555         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5556                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5557
5558         /* Program required FCoE hash buckets for the PF */
5559         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5560         val |= ((u32)settings->fcoe_filt_num <<
5561                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5562                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5563         /* Program required FCoE DDP contexts for the PF */
5564         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5565         val |= ((u32)settings->fcoe_cntx_num <<
5566                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5567                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5568
5569         /* Program Hash LUT size for the PF */
5570         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5571         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5572                 hash_lut_size = 1;
5573         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5574                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5575
5576         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5577         if (settings->enable_fdir)
5578                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5579         if (settings->enable_ethtype)
5580                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5581         if (settings->enable_macvlan)
5582                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5583
5584         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5585
5586         return I40E_SUCCESS;
5587 }
5588
5589 /**
5590  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5591  * @hw: pointer to the hw struct
5592  * @mac_addr: MAC address to use in the filter
5593  * @ethtype: Ethertype to use in the filter
5594  * @flags: Flags that needs to be applied to the filter
5595  * @vsi_seid: seid of the control VSI
5596  * @queue: VSI queue number to send the packet to
5597  * @is_add: Add control packet filter if True else remove
5598  * @stats: Structure to hold information on control filter counts
5599  * @cmd_details: pointer to command details structure or NULL
5600  *
5601  * This command will Add or Remove control packet filter for a control VSI.
5602  * In return it will update the total number of perfect filter count in
5603  * the stats member.
5604  **/
5605 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5606                                 u8 *mac_addr, u16 ethtype, u16 flags,
5607                                 u16 vsi_seid, u16 queue, bool is_add,
5608                                 struct i40e_control_filter_stats *stats,
5609                                 struct i40e_asq_cmd_details *cmd_details)
5610 {
5611         struct i40e_aq_desc desc;
5612         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5613                 (struct i40e_aqc_add_remove_control_packet_filter *)
5614                 &desc.params.raw;
5615         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5616                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5617                 &desc.params.raw;
5618         enum i40e_status_code status;
5619
5620         if (vsi_seid == 0)
5621                 return I40E_ERR_PARAM;
5622
5623         if (is_add) {
5624                 i40e_fill_default_direct_cmd_desc(&desc,
5625                                 i40e_aqc_opc_add_control_packet_filter);
5626                 cmd->queue = CPU_TO_LE16(queue);
5627         } else {
5628                 i40e_fill_default_direct_cmd_desc(&desc,
5629                                 i40e_aqc_opc_remove_control_packet_filter);
5630         }
5631
5632         if (mac_addr)
5633                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5634                             I40E_NONDMA_TO_NONDMA);
5635
5636         cmd->etype = CPU_TO_LE16(ethtype);
5637         cmd->flags = CPU_TO_LE16(flags);
5638         cmd->seid = CPU_TO_LE16(vsi_seid);
5639
5640         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5641
5642         if (!status && stats) {
5643                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5644                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5645                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5646                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5647         }
5648
5649         return status;
5650 }
5651
5652 /**
5653  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5654  * @hw: pointer to the hw struct
5655  * @seid: VSI seid to add ethertype filter from
5656  **/
5657 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5658                                                     u16 seid)
5659 {
5660 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5661         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5662                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5663                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5664         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5665         enum i40e_status_code status;
5666
5667         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5668                                                        seid, 0, true, NULL,
5669                                                        NULL);
5670         if (status)
5671                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5672 }
5673
5674 /**
5675  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5676  * @filters: list of cloud filters
5677  * @filter_count: length of list
5678  *
5679  * There's an issue in the device where the Geneve VNI layout needs
5680  * to be shifted 1 byte over from the VxLAN VNI
5681  **/
5682 STATIC void i40e_fix_up_geneve_vni(
5683         struct i40e_aqc_cloud_filters_element_data *filters,
5684         u8 filter_count)
5685 {
5686         struct i40e_aqc_cloud_filters_element_data *f = filters;
5687         int i;
5688
5689         for (i = 0; i < filter_count; i++) {
5690                 u16 tnl_type;
5691                 u32 ti;
5692
5693                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5694                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5695                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5696                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5697                         ti = LE32_TO_CPU(f[i].tenant_id);
5698                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5699                 }
5700         }
5701 }
5702
5703 /**
5704  * i40e_aq_add_cloud_filters
5705  * @hw: pointer to the hardware structure
5706  * @seid: VSI seid to add cloud filters from
5707  * @filters: Buffer which contains the filters to be added
5708  * @filter_count: number of filters contained in the buffer
5709  *
5710  * Set the cloud filters for a given VSI.  The contents of the
5711  * i40e_aqc_cloud_filters_element_data are filled
5712  * in by the caller of the function.
5713  *
5714  **/
5715 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5716         u16 seid,
5717         struct i40e_aqc_cloud_filters_element_data *filters,
5718         u8 filter_count)
5719 {
5720         struct i40e_aq_desc desc;
5721         struct i40e_aqc_add_remove_cloud_filters *cmd =
5722         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5723         enum i40e_status_code status;
5724         u16 buff_len;
5725
5726         i40e_fill_default_direct_cmd_desc(&desc,
5727                                           i40e_aqc_opc_add_cloud_filters);
5728
5729         buff_len = filter_count * sizeof(*filters);
5730         desc.datalen = CPU_TO_LE16(buff_len);
5731         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5732         cmd->num_filters = filter_count;
5733         cmd->seid = CPU_TO_LE16(seid);
5734
5735         i40e_fix_up_geneve_vni(filters, filter_count);
5736
5737         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5738
5739         return status;
5740 }
5741
5742 /**
5743  * i40e_aq_add_cloud_filters_bb
5744  * @hw: pointer to the hardware structure
5745  * @seid: VSI seid to add cloud filters from
5746  * @filters: Buffer which contains the filters in big buffer to be added
5747  * @filter_count: number of filters contained in the buffer
5748  *
5749  * Set the cloud filters for a given VSI.  The contents of the
5750  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5751  * the function.
5752  *
5753  **/
5754 enum i40e_status_code
5755 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5756                              struct i40e_aqc_cloud_filters_element_bb *filters,
5757                              u8 filter_count)
5758 {
5759         struct i40e_aq_desc desc;
5760         struct i40e_aqc_add_remove_cloud_filters *cmd =
5761         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5762         enum i40e_status_code status;
5763         u16 buff_len;
5764         int i;
5765
5766         i40e_fill_default_direct_cmd_desc(&desc,
5767                                           i40e_aqc_opc_add_cloud_filters);
5768
5769         buff_len = filter_count * sizeof(*filters);
5770         desc.datalen = CPU_TO_LE16(buff_len);
5771         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5772         cmd->num_filters = filter_count;
5773         cmd->seid = CPU_TO_LE16(seid);
5774         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5775
5776         for (i = 0; i < filter_count; i++) {
5777                 u16 tnl_type;
5778                 u32 ti;
5779
5780                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5781                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5782                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5783
5784                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5785                  * one more byte further than normally used for Tenant ID in
5786                  * other tunnel types.
5787                  */
5788                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5789                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5790                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5791                 }
5792         }
5793
5794         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5795
5796         return status;
5797 }
5798
5799 /**
5800  * i40e_aq_rem_cloud_filters
5801  * @hw: pointer to the hardware structure
5802  * @seid: VSI seid to remove cloud filters from
5803  * @filters: Buffer which contains the filters to be removed
5804  * @filter_count: number of filters contained in the buffer
5805  *
5806  * Remove the cloud filters for a given VSI.  The contents of the
5807  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5808  * of the function.
5809  *
5810  **/
5811 enum i40e_status_code
5812 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5813                           struct i40e_aqc_cloud_filters_element_data *filters,
5814                           u8 filter_count)
5815 {
5816         struct i40e_aq_desc desc;
5817         struct i40e_aqc_add_remove_cloud_filters *cmd =
5818         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5819         enum i40e_status_code status;
5820         u16 buff_len;
5821
5822         i40e_fill_default_direct_cmd_desc(&desc,
5823                                           i40e_aqc_opc_remove_cloud_filters);
5824
5825         buff_len = filter_count * sizeof(*filters);
5826         desc.datalen = CPU_TO_LE16(buff_len);
5827         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5828         cmd->num_filters = filter_count;
5829         cmd->seid = CPU_TO_LE16(seid);
5830
5831         i40e_fix_up_geneve_vni(filters, filter_count);
5832
5833         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5834
5835         return status;
5836 }
5837
5838 /**
5839  * i40e_aq_rem_cloud_filters_bb
5840  * @hw: pointer to the hardware structure
5841  * @seid: VSI seid to remove cloud filters from
5842  * @filters: Buffer which contains the filters in big buffer to be removed
5843  * @filter_count: number of filters contained in the buffer
5844  *
5845  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5846  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5847  * function.
5848  *
5849  **/
5850 enum i40e_status_code
5851 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5852                              struct i40e_aqc_cloud_filters_element_bb *filters,
5853                              u8 filter_count)
5854 {
5855         struct i40e_aq_desc desc;
5856         struct i40e_aqc_add_remove_cloud_filters *cmd =
5857         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5858         enum i40e_status_code status;
5859         u16 buff_len;
5860         int i;
5861
5862         i40e_fill_default_direct_cmd_desc(&desc,
5863                                           i40e_aqc_opc_remove_cloud_filters);
5864
5865         buff_len = filter_count * sizeof(*filters);
5866         desc.datalen = CPU_TO_LE16(buff_len);
5867         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5868         cmd->num_filters = filter_count;
5869         cmd->seid = CPU_TO_LE16(seid);
5870         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5871
5872         for (i = 0; i < filter_count; i++) {
5873                 u16 tnl_type;
5874                 u32 ti;
5875
5876                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5877                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5878                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5879
5880                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5881                  * one more byte further than normally used for Tenant ID in
5882                  * other tunnel types.
5883                  */
5884                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5885                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5886                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5887                 }
5888         }
5889
5890         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5891
5892         return status;
5893 }
5894
5895 /**
5896  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5897  * @hw: pointer to the hw struct
5898  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5899  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5900  *
5901  **/
5902 enum
5903 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5904         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5905         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5906 {
5907         struct i40e_aq_desc desc;
5908         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5909                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5910         enum i40e_status_code status = I40E_SUCCESS;
5911         int i = 0;
5912
5913         /* X722 doesn't support this command */
5914         if (hw->mac.type == I40E_MAC_X722)
5915                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5916
5917         /* need FW version greater than 6.00 */
5918         if (hw->aq.fw_maj_ver < 6)
5919                 return I40E_NOT_SUPPORTED;
5920
5921         i40e_fill_default_direct_cmd_desc(&desc,
5922                                           i40e_aqc_opc_replace_cloud_filters);
5923
5924         desc.datalen = CPU_TO_LE16(32);
5925         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5926         cmd->old_filter_type = filters->old_filter_type;
5927         cmd->new_filter_type = filters->new_filter_type;
5928         cmd->valid_flags = filters->valid_flags;
5929         cmd->tr_bit = filters->tr_bit;
5930         cmd->tr_bit2 = filters->tr_bit2;
5931
5932         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5933                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5934
5935         /* for get cloud filters command */
5936         for (i = 0; i < 32; i += 4) {
5937                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5938                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5939                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5940                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5941         }
5942
5943         return status;
5944 }
5945
5946
5947 /**
5948  * i40e_aq_alternate_write
5949  * @hw: pointer to the hardware structure
5950  * @reg_addr0: address of first dword to be read
5951  * @reg_val0: value to be written under 'reg_addr0'
5952  * @reg_addr1: address of second dword to be read
5953  * @reg_val1: value to be written under 'reg_addr1'
5954  *
5955  * Write one or two dwords to alternate structure. Fields are indicated
5956  * by 'reg_addr0' and 'reg_addr1' register numbers.
5957  *
5958  **/
5959 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5960                                 u32 reg_addr0, u32 reg_val0,
5961                                 u32 reg_addr1, u32 reg_val1)
5962 {
5963         struct i40e_aq_desc desc;
5964         struct i40e_aqc_alternate_write *cmd_resp =
5965                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5966         enum i40e_status_code status;
5967
5968         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5969         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5970         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5971         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5972         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5973
5974         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5975
5976         return status;
5977 }
5978
5979 /**
5980  * i40e_aq_alternate_write_indirect
5981  * @hw: pointer to the hardware structure
5982  * @addr: address of a first register to be modified
5983  * @dw_count: number of alternate structure fields to write
5984  * @buffer: pointer to the command buffer
5985  *
5986  * Write 'dw_count' dwords from 'buffer' to alternate structure
5987  * starting at 'addr'.
5988  *
5989  **/
5990 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5991                                 u32 addr, u32 dw_count, void *buffer)
5992 {
5993         struct i40e_aq_desc desc;
5994         struct i40e_aqc_alternate_ind_write *cmd_resp =
5995                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5996         enum i40e_status_code status;
5997
5998         if (buffer == NULL)
5999                 return I40E_ERR_PARAM;
6000
6001         /* Indirect command */
6002         i40e_fill_default_direct_cmd_desc(&desc,
6003                                          i40e_aqc_opc_alternate_write_indirect);
6004
6005         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6006         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6007         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6008                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6009
6010         cmd_resp->address = CPU_TO_LE32(addr);
6011         cmd_resp->length = CPU_TO_LE32(dw_count);
6012
6013         status = i40e_asq_send_command(hw, &desc, buffer,
6014                                        I40E_LO_DWORD(4*dw_count), NULL);
6015
6016         return status;
6017 }
6018
6019 /**
6020  * i40e_aq_alternate_read
6021  * @hw: pointer to the hardware structure
6022  * @reg_addr0: address of first dword to be read
6023  * @reg_val0: pointer for data read from 'reg_addr0'
6024  * @reg_addr1: address of second dword to be read
6025  * @reg_val1: pointer for data read from 'reg_addr1'
6026  *
6027  * Read one or two dwords from alternate structure. Fields are indicated
6028  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6029  * is not passed then only register at 'reg_addr0' is read.
6030  *
6031  **/
6032 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6033                                 u32 reg_addr0, u32 *reg_val0,
6034                                 u32 reg_addr1, u32 *reg_val1)
6035 {
6036         struct i40e_aq_desc desc;
6037         struct i40e_aqc_alternate_write *cmd_resp =
6038                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6039         enum i40e_status_code status;
6040
6041         if (reg_val0 == NULL)
6042                 return I40E_ERR_PARAM;
6043
6044         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6045         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6046         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6047
6048         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6049
6050         if (status == I40E_SUCCESS) {
6051                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6052
6053                 if (reg_val1 != NULL)
6054                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6055         }
6056
6057         return status;
6058 }
6059
6060 /**
6061  * i40e_aq_alternate_read_indirect
6062  * @hw: pointer to the hardware structure
6063  * @addr: address of the alternate structure field
6064  * @dw_count: number of alternate structure fields to read
6065  * @buffer: pointer to the command buffer
6066  *
6067  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6068  * place them in 'buffer'. The buffer should be allocated by caller.
6069  *
6070  **/
6071 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6072                                 u32 addr, u32 dw_count, void *buffer)
6073 {
6074         struct i40e_aq_desc desc;
6075         struct i40e_aqc_alternate_ind_write *cmd_resp =
6076                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6077         enum i40e_status_code status;
6078
6079         if (buffer == NULL)
6080                 return I40E_ERR_PARAM;
6081
6082         /* Indirect command */
6083         i40e_fill_default_direct_cmd_desc(&desc,
6084                 i40e_aqc_opc_alternate_read_indirect);
6085
6086         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6087         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6088         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6089                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6090
6091         cmd_resp->address = CPU_TO_LE32(addr);
6092         cmd_resp->length = CPU_TO_LE32(dw_count);
6093
6094         status = i40e_asq_send_command(hw, &desc, buffer,
6095                                        I40E_LO_DWORD(4*dw_count), NULL);
6096
6097         return status;
6098 }
6099
6100 /**
6101  *  i40e_aq_alternate_clear
6102  *  @hw: pointer to the HW structure.
6103  *
6104  *  Clear the alternate structures of the port from which the function
6105  *  is called.
6106  *
6107  **/
6108 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6109 {
6110         struct i40e_aq_desc desc;
6111         enum i40e_status_code status;
6112
6113         i40e_fill_default_direct_cmd_desc(&desc,
6114                                           i40e_aqc_opc_alternate_clear_port);
6115
6116         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6117
6118         return status;
6119 }
6120
6121 /**
6122  *  i40e_aq_alternate_write_done
6123  *  @hw: pointer to the HW structure.
6124  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6125  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6126  *
6127  *  Indicates to the FW that alternate structures have been changed.
6128  *
6129  **/
6130 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6131                 u8 bios_mode, bool *reset_needed)
6132 {
6133         struct i40e_aq_desc desc;
6134         struct i40e_aqc_alternate_write_done *cmd =
6135                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6136         enum i40e_status_code status;
6137
6138         if (reset_needed == NULL)
6139                 return I40E_ERR_PARAM;
6140
6141         i40e_fill_default_direct_cmd_desc(&desc,
6142                                           i40e_aqc_opc_alternate_write_done);
6143
6144         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6145
6146         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6147         if (!status && reset_needed)
6148                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6149                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6150
6151         return status;
6152 }
6153
6154 /**
6155  *  i40e_aq_set_oem_mode
6156  *  @hw: pointer to the HW structure.
6157  *  @oem_mode: the OEM mode to be used
6158  *
6159  *  Sets the device to a specific operating mode. Currently the only supported
6160  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6161  *
6162  **/
6163 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6164                 u8 oem_mode)
6165 {
6166         struct i40e_aq_desc desc;
6167         struct i40e_aqc_alternate_write_done *cmd =
6168                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6169         enum i40e_status_code status;
6170
6171         i40e_fill_default_direct_cmd_desc(&desc,
6172                                           i40e_aqc_opc_alternate_set_mode);
6173
6174         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6175
6176         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6177
6178         return status;
6179 }
6180
6181 /**
6182  * i40e_aq_resume_port_tx
6183  * @hw: pointer to the hardware structure
6184  * @cmd_details: pointer to command details structure or NULL
6185  *
6186  * Resume port's Tx traffic
6187  **/
6188 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6189                                 struct i40e_asq_cmd_details *cmd_details)
6190 {
6191         struct i40e_aq_desc desc;
6192         enum i40e_status_code status;
6193
6194         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6195
6196         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6197
6198         return status;
6199 }
6200
6201 /**
6202  * i40e_set_pci_config_data - store PCI bus info
6203  * @hw: pointer to hardware structure
6204  * @link_status: the link status word from PCI config space
6205  *
6206  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6207  **/
6208 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6209 {
6210         hw->bus.type = i40e_bus_type_pci_express;
6211
6212         switch (link_status & I40E_PCI_LINK_WIDTH) {
6213         case I40E_PCI_LINK_WIDTH_1:
6214                 hw->bus.width = i40e_bus_width_pcie_x1;
6215                 break;
6216         case I40E_PCI_LINK_WIDTH_2:
6217                 hw->bus.width = i40e_bus_width_pcie_x2;
6218                 break;
6219         case I40E_PCI_LINK_WIDTH_4:
6220                 hw->bus.width = i40e_bus_width_pcie_x4;
6221                 break;
6222         case I40E_PCI_LINK_WIDTH_8:
6223                 hw->bus.width = i40e_bus_width_pcie_x8;
6224                 break;
6225         default:
6226                 hw->bus.width = i40e_bus_width_unknown;
6227                 break;
6228         }
6229
6230         switch (link_status & I40E_PCI_LINK_SPEED) {
6231         case I40E_PCI_LINK_SPEED_2500:
6232                 hw->bus.speed = i40e_bus_speed_2500;
6233                 break;
6234         case I40E_PCI_LINK_SPEED_5000:
6235                 hw->bus.speed = i40e_bus_speed_5000;
6236                 break;
6237         case I40E_PCI_LINK_SPEED_8000:
6238                 hw->bus.speed = i40e_bus_speed_8000;
6239                 break;
6240         default:
6241                 hw->bus.speed = i40e_bus_speed_unknown;
6242                 break;
6243         }
6244 }
6245
6246 /**
6247  * i40e_aq_debug_dump
6248  * @hw: pointer to the hardware structure
6249  * @cluster_id: specific cluster to dump
6250  * @table_id: table id within cluster
6251  * @start_index: index of line in the block to read
6252  * @buff_size: dump buffer size
6253  * @buff: dump buffer
6254  * @ret_buff_size: actual buffer size returned
6255  * @ret_next_table: next block to read
6256  * @ret_next_index: next index to read
6257  * @cmd_details: pointer to command details structure or NULL
6258  *
6259  * Dump internal FW/HW data for debug purposes.
6260  *
6261  **/
6262 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6263                                 u8 table_id, u32 start_index, u16 buff_size,
6264                                 void *buff, u16 *ret_buff_size,
6265                                 u8 *ret_next_table, u32 *ret_next_index,
6266                                 struct i40e_asq_cmd_details *cmd_details)
6267 {
6268         struct i40e_aq_desc desc;
6269         struct i40e_aqc_debug_dump_internals *cmd =
6270                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6271         struct i40e_aqc_debug_dump_internals *resp =
6272                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6273         enum i40e_status_code status;
6274
6275         if (buff_size == 0 || !buff)
6276                 return I40E_ERR_PARAM;
6277
6278         i40e_fill_default_direct_cmd_desc(&desc,
6279                                           i40e_aqc_opc_debug_dump_internals);
6280         /* Indirect Command */
6281         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6282         if (buff_size > I40E_AQ_LARGE_BUF)
6283                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6284
6285         cmd->cluster_id = cluster_id;
6286         cmd->table_id = table_id;
6287         cmd->idx = CPU_TO_LE32(start_index);
6288
6289         desc.datalen = CPU_TO_LE16(buff_size);
6290
6291         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6292         if (!status) {
6293                 if (ret_buff_size != NULL)
6294                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6295                 if (ret_next_table != NULL)
6296                         *ret_next_table = resp->table_id;
6297                 if (ret_next_index != NULL)
6298                         *ret_next_index = LE32_TO_CPU(resp->idx);
6299         }
6300
6301         return status;
6302 }
6303
6304 /**
6305  * i40e_read_bw_from_alt_ram
6306  * @hw: pointer to the hardware structure
6307  * @max_bw: pointer for max_bw read
6308  * @min_bw: pointer for min_bw read
6309  * @min_valid: pointer for bool that is true if min_bw is a valid value
6310  * @max_valid: pointer for bool that is true if max_bw is a valid value
6311  *
6312  * Read bw from the alternate ram for the given pf
6313  **/
6314 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6315                                         u32 *max_bw, u32 *min_bw,
6316                                         bool *min_valid, bool *max_valid)
6317 {
6318         enum i40e_status_code status;
6319         u32 max_bw_addr, min_bw_addr;
6320
6321         /* Calculate the address of the min/max bw registers */
6322         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6323                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6324                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6325         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6326                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6327                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6328
6329         /* Read the bandwidths from alt ram */
6330         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6331                                         min_bw_addr, min_bw);
6332
6333         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6334                 *min_valid = true;
6335         else
6336                 *min_valid = false;
6337
6338         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6339                 *max_valid = true;
6340         else
6341                 *max_valid = false;
6342
6343         return status;
6344 }
6345
6346 /**
6347  * i40e_aq_configure_partition_bw
6348  * @hw: pointer to the hardware structure
6349  * @bw_data: Buffer holding valid pfs and bw limits
6350  * @cmd_details: pointer to command details
6351  *
6352  * Configure partitions guaranteed/max bw
6353  **/
6354 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6355                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6356                         struct i40e_asq_cmd_details *cmd_details)
6357 {
6358         enum i40e_status_code status;
6359         struct i40e_aq_desc desc;
6360         u16 bwd_size = sizeof(*bw_data);
6361
6362         i40e_fill_default_direct_cmd_desc(&desc,
6363                                 i40e_aqc_opc_configure_partition_bw);
6364
6365         /* Indirect command */
6366         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6367         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6368
6369         desc.datalen = CPU_TO_LE16(bwd_size);
6370
6371         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6372
6373         return status;
6374 }
6375
6376 /**
6377  * i40e_read_phy_register_clause22
6378  * @hw: pointer to the HW structure
6379  * @reg: register address in the page
6380  * @phy_addr: PHY address on MDIO interface
6381  * @value: PHY register value
6382  *
6383  * Reads specified PHY register value
6384  **/
6385 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6386                                         u16 reg, u8 phy_addr, u16 *value)
6387 {
6388         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6389         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6390         u32 command = 0;
6391         u16 retry = 1000;
6392
6393         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6394                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6395                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6396                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6397                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6398         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6399         do {
6400                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6401                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6402                         status = I40E_SUCCESS;
6403                         break;
6404                 }
6405                 i40e_usec_delay(10);
6406                 retry--;
6407         } while (retry);
6408
6409         if (status) {
6410                 i40e_debug(hw, I40E_DEBUG_PHY,
6411                            "PHY: Can't write command to external PHY.\n");
6412         } else {
6413                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6414                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6415                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6416         }
6417
6418         return status;
6419 }
6420
6421 /**
6422  * i40e_write_phy_register_clause22
6423  * @hw: pointer to the HW structure
6424  * @reg: register address in the page
6425  * @phy_addr: PHY address on MDIO interface
6426  * @value: PHY register value
6427  *
6428  * Writes specified PHY register value
6429  **/
6430 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6431                                         u16 reg, u8 phy_addr, u16 value)
6432 {
6433         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6434         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6435         u32 command  = 0;
6436         u16 retry = 1000;
6437
6438         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6439         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6440
6441         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6442                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6443                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6444                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6445                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6446
6447         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6448         do {
6449                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6450                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6451                         status = I40E_SUCCESS;
6452                         break;
6453                 }
6454                 i40e_usec_delay(10);
6455                 retry--;
6456         } while (retry);
6457
6458         return status;
6459 }
6460
6461 /**
6462  * i40e_read_phy_register_clause45
6463  * @hw: pointer to the HW structure
6464  * @page: registers page number
6465  * @reg: register address in the page
6466  * @phy_addr: PHY address on MDIO interface
6467  * @value: PHY register value
6468  *
6469  * Reads specified PHY register value
6470  **/
6471 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6472                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6473 {
6474         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6475         u32 command  = 0;
6476         u16 retry = 1000;
6477         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6478
6479         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6480                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6481                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6482                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6483                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6484                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6485                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6486         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6487         do {
6488                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6489                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6490                         status = I40E_SUCCESS;
6491                         break;
6492                 }
6493                 i40e_usec_delay(10);
6494                 retry--;
6495         } while (retry);
6496
6497         if (status) {
6498                 i40e_debug(hw, I40E_DEBUG_PHY,
6499                            "PHY: Can't write command to external PHY.\n");
6500                 goto phy_read_end;
6501         }
6502
6503         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6504                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6505                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6506                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6507                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6508                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6509         status = I40E_ERR_TIMEOUT;
6510         retry = 1000;
6511         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6512         do {
6513                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6514                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6515                         status = I40E_SUCCESS;
6516                         break;
6517                 }
6518                 i40e_usec_delay(10);
6519                 retry--;
6520         } while (retry);
6521
6522         if (!status) {
6523                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6524                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6525                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6526         } else {
6527                 i40e_debug(hw, I40E_DEBUG_PHY,
6528                            "PHY: Can't read register value from external PHY.\n");
6529         }
6530
6531 phy_read_end:
6532         return status;
6533 }
6534
6535 /**
6536  * i40e_write_phy_register_clause45
6537  * @hw: pointer to the HW structure
6538  * @page: registers page number
6539  * @reg: register address in the page
6540  * @phy_addr: PHY address on MDIO interface
6541  * @value: PHY register value
6542  *
6543  * Writes value to specified PHY register
6544  **/
6545 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6546                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6547 {
6548         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6549         u32 command  = 0;
6550         u16 retry = 1000;
6551         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6552
6553         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6554                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6555                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6556                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6557                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6558                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6559                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6560         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6561         do {
6562                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6563                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6564                         status = I40E_SUCCESS;
6565                         break;
6566                 }
6567                 i40e_usec_delay(10);
6568                 retry--;
6569         } while (retry);
6570         if (status) {
6571                 i40e_debug(hw, I40E_DEBUG_PHY,
6572                            "PHY: Can't write command to external PHY.\n");
6573                 goto phy_write_end;
6574         }
6575
6576         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6577         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6578
6579         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6580                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6581                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6582                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6583                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6584                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6585         status = I40E_ERR_TIMEOUT;
6586         retry = 1000;
6587         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6588         do {
6589                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6590                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6591                         status = I40E_SUCCESS;
6592                         break;
6593                 }
6594                 i40e_usec_delay(10);
6595                 retry--;
6596         } while (retry);
6597
6598 phy_write_end:
6599         return status;
6600 }
6601
6602 /**
6603  * i40e_write_phy_register
6604  * @hw: pointer to the HW structure
6605  * @page: registers page number
6606  * @reg: register address in the page
6607  * @phy_addr: PHY address on MDIO interface
6608  * @value: PHY register value
6609  *
6610  * Writes value to specified PHY register
6611  **/
6612 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6613                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6614 {
6615         enum i40e_status_code status;
6616
6617         switch (hw->device_id) {
6618         case I40E_DEV_ID_1G_BASE_T_X722:
6619                 status = i40e_write_phy_register_clause22(hw,
6620                         reg, phy_addr, value);
6621                 break;
6622         case I40E_DEV_ID_10G_BASE_T:
6623         case I40E_DEV_ID_10G_BASE_T4:
6624         case I40E_DEV_ID_10G_BASE_T_BC:
6625         case I40E_DEV_ID_10G_BASE_T_X722:
6626         case I40E_DEV_ID_25G_B:
6627         case I40E_DEV_ID_25G_SFP28:
6628                 status = i40e_write_phy_register_clause45(hw,
6629                         page, reg, phy_addr, value);
6630                 break;
6631         default:
6632                 status = I40E_ERR_UNKNOWN_PHY;
6633                 break;
6634         }
6635
6636         return status;
6637 }
6638
6639 /**
6640  * i40e_read_phy_register
6641  * @hw: pointer to the HW structure
6642  * @page: registers page number
6643  * @reg: register address in the page
6644  * @phy_addr: PHY address on MDIO interface
6645  * @value: PHY register value
6646  *
6647  * Reads specified PHY register value
6648  **/
6649 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6650                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6651 {
6652         enum i40e_status_code status;
6653
6654         switch (hw->device_id) {
6655         case I40E_DEV_ID_1G_BASE_T_X722:
6656                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6657                                                          value);
6658                 break;
6659         case I40E_DEV_ID_10G_BASE_T:
6660         case I40E_DEV_ID_10G_BASE_T4:
6661         case I40E_DEV_ID_10G_BASE_T_X722:
6662         case I40E_DEV_ID_25G_B:
6663         case I40E_DEV_ID_25G_SFP28:
6664                 status = i40e_read_phy_register_clause45(hw, page, reg,
6665                                                          phy_addr, value);
6666                 break;
6667         default:
6668                 status = I40E_ERR_UNKNOWN_PHY;
6669                 break;
6670         }
6671
6672         return status;
6673 }
6674
6675 /**
6676  * i40e_get_phy_address
6677  * @hw: pointer to the HW structure
6678  * @dev_num: PHY port num that address we want
6679  *
6680  * Gets PHY address for current port
6681  **/
6682 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6683 {
6684         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6685         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6686
6687         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6688 }
6689
6690 /**
6691  * i40e_blink_phy_led
6692  * @hw: pointer to the HW structure
6693  * @time: time how long led will blinks in secs
6694  * @interval: gap between LED on and off in msecs
6695  *
6696  * Blinks PHY link LED
6697  **/
6698 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6699                                               u32 time, u32 interval)
6700 {
6701         enum i40e_status_code status = I40E_SUCCESS;
6702         u32 i;
6703         u16 led_ctl = 0;
6704         u16 gpio_led_port;
6705         u16 led_reg;
6706         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6707         u8 phy_addr = 0;
6708         u8 port_num;
6709
6710         i = rd32(hw, I40E_PFGEN_PORTNUM);
6711         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6712         phy_addr = i40e_get_phy_address(hw, port_num);
6713
6714         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6715              led_addr++) {
6716                 status = i40e_read_phy_register_clause45(hw,
6717                                                          I40E_PHY_COM_REG_PAGE,
6718                                                          led_addr, phy_addr,
6719                                                          &led_reg);
6720                 if (status)
6721                         goto phy_blinking_end;
6722                 led_ctl = led_reg;
6723                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6724                         led_reg = 0;
6725                         status = i40e_write_phy_register_clause45(hw,
6726                                                          I40E_PHY_COM_REG_PAGE,
6727                                                          led_addr, phy_addr,
6728                                                          led_reg);
6729                         if (status)
6730                                 goto phy_blinking_end;
6731                         break;
6732                 }
6733         }
6734
6735         if (time > 0 && interval > 0) {
6736                 for (i = 0; i < time * 1000; i += interval) {
6737                         status = i40e_read_phy_register_clause45(hw,
6738                                                 I40E_PHY_COM_REG_PAGE,
6739                                                 led_addr, phy_addr, &led_reg);
6740                         if (status)
6741                                 goto restore_config;
6742                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6743                                 led_reg = 0;
6744                         else
6745                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6746                         status = i40e_write_phy_register_clause45(hw,
6747                                                 I40E_PHY_COM_REG_PAGE,
6748                                                 led_addr, phy_addr, led_reg);
6749                         if (status)
6750                                 goto restore_config;
6751                         i40e_msec_delay(interval);
6752                 }
6753         }
6754
6755 restore_config:
6756         status = i40e_write_phy_register_clause45(hw,
6757                                                   I40E_PHY_COM_REG_PAGE,
6758                                                   led_addr, phy_addr, led_ctl);
6759
6760 phy_blinking_end:
6761         return status;
6762 }
6763
6764 /**
6765  * i40e_led_get_reg - read LED register
6766  * @hw: pointer to the HW structure
6767  * @led_addr: LED register address
6768  * @reg_val: read register value
6769  **/
6770 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6771                                               u32 *reg_val)
6772 {
6773         enum i40e_status_code status;
6774         u8 phy_addr = 0;
6775
6776         *reg_val = 0;
6777         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6778                 status = i40e_aq_get_phy_register(hw,
6779                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6780                                                 I40E_PHY_COM_REG_PAGE, true,
6781                                                 I40E_PHY_LED_PROV_REG_1,
6782                                                 reg_val, NULL);
6783         } else {
6784                 phy_addr = i40e_get_phy_address(hw, hw->port);
6785                 status = i40e_read_phy_register_clause45(hw,
6786                                                          I40E_PHY_COM_REG_PAGE,
6787                                                          led_addr, phy_addr,
6788                                                          (u16 *)reg_val);
6789         }
6790         return status;
6791 }
6792
6793 /**
6794  * i40e_led_set_reg - write LED register
6795  * @hw: pointer to the HW structure
6796  * @led_addr: LED register address
6797  * @reg_val: register value to write
6798  **/
6799 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6800                                               u32 reg_val)
6801 {
6802         enum i40e_status_code status;
6803         u8 phy_addr = 0;
6804
6805         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6806                 status = i40e_aq_set_phy_register(hw,
6807                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6808                                                 I40E_PHY_COM_REG_PAGE, true,
6809                                                 I40E_PHY_LED_PROV_REG_1,
6810                                                 reg_val, NULL);
6811         } else {
6812                 phy_addr = i40e_get_phy_address(hw, hw->port);
6813                 status = i40e_write_phy_register_clause45(hw,
6814                                                           I40E_PHY_COM_REG_PAGE,
6815                                                           led_addr, phy_addr,
6816                                                           (u16)reg_val);
6817         }
6818
6819         return status;
6820 }
6821
6822 /**
6823  * i40e_led_get_phy - return current on/off mode
6824  * @hw: pointer to the hw struct
6825  * @led_addr: address of led register to use
6826  * @val: original value of register to use
6827  *
6828  **/
6829 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6830                                        u16 *val)
6831 {
6832         enum i40e_status_code status = I40E_SUCCESS;
6833         u16 gpio_led_port;
6834         u32 reg_val_aq;
6835         u16 temp_addr;
6836         u8 phy_addr = 0;
6837         u16 reg_val;
6838
6839         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6840                 status = i40e_aq_get_phy_register(hw,
6841                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6842                                                 I40E_PHY_COM_REG_PAGE, true,
6843                                                 I40E_PHY_LED_PROV_REG_1,
6844                                                 &reg_val_aq, NULL);
6845                 if (status == I40E_SUCCESS)
6846                         *val = (u16)reg_val_aq;
6847                 return status;
6848         }
6849         temp_addr = I40E_PHY_LED_PROV_REG_1;
6850         phy_addr = i40e_get_phy_address(hw, hw->port);
6851         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6852              temp_addr++) {
6853                 status = i40e_read_phy_register_clause45(hw,
6854                                                          I40E_PHY_COM_REG_PAGE,
6855                                                          temp_addr, phy_addr,
6856                                                          &reg_val);
6857                 if (status)
6858                         return status;
6859                 *val = reg_val;
6860                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6861                         *led_addr = temp_addr;
6862                         break;
6863                 }
6864         }
6865         return status;
6866 }
6867
6868 /**
6869  * i40e_led_set_phy
6870  * @hw: pointer to the HW structure
6871  * @on: true or false
6872  * @led_addr: address of led register to use
6873  * @mode: original val plus bit for set or ignore
6874  *
6875  * Set led's on or off when controlled by the PHY
6876  *
6877  **/
6878 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6879                                        u16 led_addr, u32 mode)
6880 {
6881         enum i40e_status_code status = I40E_SUCCESS;
6882         u32 led_ctl = 0;
6883         u32 led_reg = 0;
6884
6885         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6886         if (status)
6887                 return status;
6888         led_ctl = led_reg;
6889         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6890                 led_reg = 0;
6891                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6892                 if (status)
6893                         return status;
6894         }
6895         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6896         if (status)
6897                 goto restore_config;
6898         if (on)
6899                 led_reg = I40E_PHY_LED_MANUAL_ON;
6900         else
6901                 led_reg = 0;
6902         status = i40e_led_set_reg(hw, led_addr, led_reg);
6903         if (status)
6904                 goto restore_config;
6905         if (mode & I40E_PHY_LED_MODE_ORIG) {
6906                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6907                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6908         }
6909         return status;
6910
6911 restore_config:
6912         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6913         return status;
6914 }
6915 #endif /* PF_DRIVER */
6916
6917 /**
6918  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6919  * @hw: pointer to the hw struct
6920  * @reg_addr: register address
6921  * @reg_val: ptr to register value
6922  * @cmd_details: pointer to command details structure or NULL
6923  *
6924  * Use the firmware to read the Rx control register,
6925  * especially useful if the Rx unit is under heavy pressure
6926  **/
6927 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6928                                 u32 reg_addr, u32 *reg_val,
6929                                 struct i40e_asq_cmd_details *cmd_details)
6930 {
6931         struct i40e_aq_desc desc;
6932         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6933                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6934         enum i40e_status_code status;
6935
6936         if (reg_val == NULL)
6937                 return I40E_ERR_PARAM;
6938
6939         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6940
6941         cmd_resp->address = CPU_TO_LE32(reg_addr);
6942
6943         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6944
6945         if (status == I40E_SUCCESS)
6946                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6947
6948         return status;
6949 }
6950
6951 /**
6952  * i40e_read_rx_ctl - read from an Rx control register
6953  * @hw: pointer to the hw struct
6954  * @reg_addr: register address
6955  **/
6956 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6957 {
6958         enum i40e_status_code status = I40E_SUCCESS;
6959         bool use_register;
6960         int retry = 5;
6961         u32 val = 0;
6962
6963         use_register = (((hw->aq.api_maj_ver == 1) &&
6964                         (hw->aq.api_min_ver < 5)) ||
6965                         (hw->mac.type == I40E_MAC_X722));
6966         if (!use_register) {
6967 do_retry:
6968                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6969                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6970                         i40e_msec_delay(1);
6971                         retry--;
6972                         goto do_retry;
6973                 }
6974         }
6975
6976         /* if the AQ access failed, try the old-fashioned way */
6977         if (status || use_register)
6978                 val = rd32(hw, reg_addr);
6979
6980         return val;
6981 }
6982
6983 /**
6984  * i40e_aq_rx_ctl_write_register
6985  * @hw: pointer to the hw struct
6986  * @reg_addr: register address
6987  * @reg_val: register value
6988  * @cmd_details: pointer to command details structure or NULL
6989  *
6990  * Use the firmware to write to an Rx control register,
6991  * especially useful if the Rx unit is under heavy pressure
6992  **/
6993 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6994                                 u32 reg_addr, u32 reg_val,
6995                                 struct i40e_asq_cmd_details *cmd_details)
6996 {
6997         struct i40e_aq_desc desc;
6998         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6999                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7000         enum i40e_status_code status;
7001
7002         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7003
7004         cmd->address = CPU_TO_LE32(reg_addr);
7005         cmd->value = CPU_TO_LE32(reg_val);
7006
7007         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7008
7009         return status;
7010 }
7011
7012 /**
7013  * i40e_write_rx_ctl - write to an Rx control register
7014  * @hw: pointer to the hw struct
7015  * @reg_addr: register address
7016  * @reg_val: register value
7017  **/
7018 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7019 {
7020         enum i40e_status_code status = I40E_SUCCESS;
7021         bool use_register;
7022         int retry = 5;
7023
7024         use_register = (((hw->aq.api_maj_ver == 1) &&
7025                         (hw->aq.api_min_ver < 5)) ||
7026                         (hw->mac.type == I40E_MAC_X722));
7027         if (!use_register) {
7028 do_retry:
7029                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7030                                                        reg_val, NULL);
7031                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7032                         i40e_msec_delay(1);
7033                         retry--;
7034                         goto do_retry;
7035                 }
7036         }
7037
7038         /* if the AQ access failed, try the old-fashioned way */
7039         if (status || use_register)
7040                 wr32(hw, reg_addr, reg_val);
7041 }
7042
7043 #ifdef PF_DRIVER
7044 /**
7045  * i40e_aq_set_phy_register
7046  * @hw: pointer to the hw struct
7047  * @phy_select: select which phy should be accessed
7048  * @dev_addr: PHY device address
7049  * @page_change: enable auto page change
7050  * @reg_addr: PHY register address
7051  * @reg_val: new register value
7052  * @cmd_details: pointer to command details structure or NULL
7053  *
7054  * Write the external PHY register.
7055  **/
7056 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7057                                 u8 phy_select, u8 dev_addr, bool page_change,
7058                                 u32 reg_addr, u32 reg_val,
7059                                 struct i40e_asq_cmd_details *cmd_details)
7060 {
7061         struct i40e_aq_desc desc;
7062         struct i40e_aqc_phy_register_access *cmd =
7063                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7064         enum i40e_status_code status;
7065
7066         i40e_fill_default_direct_cmd_desc(&desc,
7067                                           i40e_aqc_opc_set_phy_register);
7068
7069         cmd->phy_interface = phy_select;
7070         cmd->dev_addres = dev_addr;
7071         cmd->reg_address = CPU_TO_LE32(reg_addr);
7072         cmd->reg_value = CPU_TO_LE32(reg_val);
7073
7074         if (!page_change)
7075                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7076
7077         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7078
7079         return status;
7080 }
7081
7082 /**
7083  * i40e_aq_get_phy_register
7084  * @hw: pointer to the hw struct
7085  * @phy_select: select which phy should be accessed
7086  * @dev_addr: PHY device address
7087  * @page_change: enable auto page change
7088  * @reg_addr: PHY register address
7089  * @reg_val: read register value
7090  * @cmd_details: pointer to command details structure or NULL
7091  *
7092  * Read the external PHY register.
7093  **/
7094 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7095                                 u8 phy_select, u8 dev_addr, bool page_change,
7096                                 u32 reg_addr, u32 *reg_val,
7097                                 struct i40e_asq_cmd_details *cmd_details)
7098 {
7099         struct i40e_aq_desc desc;
7100         struct i40e_aqc_phy_register_access *cmd =
7101                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7102         enum i40e_status_code status;
7103
7104         i40e_fill_default_direct_cmd_desc(&desc,
7105                                           i40e_aqc_opc_get_phy_register);
7106
7107         cmd->phy_interface = phy_select;
7108         cmd->dev_addres = dev_addr;
7109         cmd->reg_address = CPU_TO_LE32(reg_addr);
7110
7111         if (!page_change)
7112                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7113
7114         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7115         if (!status)
7116                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7117
7118         return status;
7119 }
7120
7121 #endif /* PF_DRIVER */
7122 #ifdef VF_DRIVER
7123
7124 /**
7125  * i40e_aq_send_msg_to_pf
7126  * @hw: pointer to the hardware structure
7127  * @v_opcode: opcodes for VF-PF communication
7128  * @v_retval: return error code
7129  * @msg: pointer to the msg buffer
7130  * @msglen: msg length
7131  * @cmd_details: pointer to command details
7132  *
7133  * Send message to PF driver using admin queue. By default, this message
7134  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7135  * completion before returning.
7136  **/
7137 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7138                                 enum virtchnl_ops v_opcode,
7139                                 enum i40e_status_code v_retval,
7140                                 u8 *msg, u16 msglen,
7141                                 struct i40e_asq_cmd_details *cmd_details)
7142 {
7143         struct i40e_aq_desc desc;
7144         struct i40e_asq_cmd_details details;
7145         enum i40e_status_code status;
7146
7147         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7148         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7149         desc.cookie_high = CPU_TO_LE32(v_opcode);
7150         desc.cookie_low = CPU_TO_LE32(v_retval);
7151         if (msglen) {
7152                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7153                                                 | I40E_AQ_FLAG_RD));
7154                 if (msglen > I40E_AQ_LARGE_BUF)
7155                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7156                 desc.datalen = CPU_TO_LE16(msglen);
7157         }
7158         if (!cmd_details) {
7159                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7160                 details.async = true;
7161                 cmd_details = &details;
7162         }
7163         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7164                                        msglen, cmd_details);
7165         return status;
7166 }
7167
7168 /**
7169  * i40e_vf_parse_hw_config
7170  * @hw: pointer to the hardware structure
7171  * @msg: pointer to the virtual channel VF resource structure
7172  *
7173  * Given a VF resource message from the PF, populate the hw struct
7174  * with appropriate information.
7175  **/
7176 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7177                              struct virtchnl_vf_resource *msg)
7178 {
7179         struct virtchnl_vsi_resource *vsi_res;
7180         int i;
7181
7182         vsi_res = &msg->vsi_res[0];
7183
7184         hw->dev_caps.num_vsis = msg->num_vsis;
7185         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7186         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7187         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7188         hw->dev_caps.dcb = msg->vf_cap_flags &
7189                            VIRTCHNL_VF_OFFLOAD_L2;
7190         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7191                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7192         for (i = 0; i < msg->num_vsis; i++) {
7193                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7194                         i40e_memcpy(hw->mac.perm_addr,
7195                                     vsi_res->default_mac_addr,
7196                                     ETH_ALEN,
7197                                     I40E_NONDMA_TO_NONDMA);
7198                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7199                                     ETH_ALEN,
7200                                     I40E_NONDMA_TO_NONDMA);
7201                 }
7202                 vsi_res++;
7203         }
7204 }
7205
7206 /**
7207  * i40e_vf_reset
7208  * @hw: pointer to the hardware structure
7209  *
7210  * Send a VF_RESET message to the PF. Does not wait for response from PF
7211  * as none will be forthcoming. Immediately after calling this function,
7212  * the admin queue should be shut down and (optionally) reinitialized.
7213  **/
7214 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7215 {
7216         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7217                                       I40E_SUCCESS, NULL, 0, NULL);
7218 }
7219 #endif /* VF_DRIVER */
7220
7221 /**
7222  * i40e_aq_set_arp_proxy_config
7223  * @hw: pointer to the HW structure
7224  * @proxy_config: pointer to proxy config command table struct
7225  * @cmd_details: pointer to command details
7226  *
7227  * Set ARP offload parameters from pre-populated
7228  * i40e_aqc_arp_proxy_data struct
7229  **/
7230 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7231                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7232                                 struct i40e_asq_cmd_details *cmd_details)
7233 {
7234         struct i40e_aq_desc desc;
7235         enum i40e_status_code status;
7236
7237         if (!proxy_config)
7238                 return I40E_ERR_PARAM;
7239
7240         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7241
7242         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7243         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7244         desc.params.external.addr_high =
7245                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7246         desc.params.external.addr_low =
7247                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7248         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7249
7250         status = i40e_asq_send_command(hw, &desc, proxy_config,
7251                                        sizeof(struct i40e_aqc_arp_proxy_data),
7252                                        cmd_details);
7253
7254         return status;
7255 }
7256
7257 /**
7258  * i40e_aq_opc_set_ns_proxy_table_entry
7259  * @hw: pointer to the HW structure
7260  * @ns_proxy_table_entry: pointer to NS table entry command struct
7261  * @cmd_details: pointer to command details
7262  *
7263  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7264  * from pre-populated i40e_aqc_ns_proxy_data struct
7265  **/
7266 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7267                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7268                         struct i40e_asq_cmd_details *cmd_details)
7269 {
7270         struct i40e_aq_desc desc;
7271         enum i40e_status_code status;
7272
7273         if (!ns_proxy_table_entry)
7274                 return I40E_ERR_PARAM;
7275
7276         i40e_fill_default_direct_cmd_desc(&desc,
7277                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7278
7279         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7280         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7281         desc.params.external.addr_high =
7282                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7283         desc.params.external.addr_low =
7284                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7285         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7286
7287         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7288                                        sizeof(struct i40e_aqc_ns_proxy_data),
7289                                        cmd_details);
7290
7291         return status;
7292 }
7293
7294 /**
7295  * i40e_aq_set_clear_wol_filter
7296  * @hw: pointer to the hw struct
7297  * @filter_index: index of filter to modify (0-7)
7298  * @filter: buffer containing filter to be set
7299  * @set_filter: true to set filter, false to clear filter
7300  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7301  *              if false, pass through packets may cause wake-up
7302  * @filter_valid: true if filter action is valid
7303  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7304  * @cmd_details: pointer to command details structure or NULL
7305  *
7306  * Set or clear WoL filter for port attached to the PF
7307  **/
7308 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7309                                 u8 filter_index,
7310                                 struct i40e_aqc_set_wol_filter_data *filter,
7311                                 bool set_filter, bool no_wol_tco,
7312                                 bool filter_valid, bool no_wol_tco_valid,
7313                                 struct i40e_asq_cmd_details *cmd_details)
7314 {
7315         struct i40e_aq_desc desc;
7316         struct i40e_aqc_set_wol_filter *cmd =
7317                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7318         enum i40e_status_code status;
7319         u16 cmd_flags = 0;
7320         u16 valid_flags = 0;
7321         u16 buff_len = 0;
7322
7323         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7324
7325         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7326                 return  I40E_ERR_PARAM;
7327         cmd->filter_index = CPU_TO_LE16(filter_index);
7328
7329         if (set_filter) {
7330                 if (!filter)
7331                         return  I40E_ERR_PARAM;
7332
7333                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7334                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7335         }
7336
7337         if (no_wol_tco)
7338                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7339         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7340
7341         if (filter_valid)
7342                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7343         if (no_wol_tco_valid)
7344                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7345         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7346
7347         buff_len = sizeof(*filter);
7348         desc.datalen = CPU_TO_LE16(buff_len);
7349
7350         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7351         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7352
7353         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7354         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7355
7356         status = i40e_asq_send_command(hw, &desc, filter,
7357                                        buff_len, cmd_details);
7358
7359         return status;
7360 }
7361
7362 /**
7363  * i40e_aq_get_wake_event_reason
7364  * @hw: pointer to the hw struct
7365  * @wake_reason: return value, index of matching filter
7366  * @cmd_details: pointer to command details structure or NULL
7367  *
7368  * Get information for the reason of a Wake Up event
7369  **/
7370 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7371                                 u16 *wake_reason,
7372                                 struct i40e_asq_cmd_details *cmd_details)
7373 {
7374         struct i40e_aq_desc desc;
7375         struct i40e_aqc_get_wake_reason_completion *resp =
7376                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7377         enum i40e_status_code status;
7378
7379         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7380
7381         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7382
7383         if (status == I40E_SUCCESS)
7384                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7385
7386         return status;
7387 }
7388
7389 /**
7390 * i40e_aq_clear_all_wol_filters
7391 * @hw: pointer to the hw struct
7392 * @cmd_details: pointer to command details structure or NULL
7393 *
7394 * Get information for the reason of a Wake Up event
7395 **/
7396 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7397         struct i40e_asq_cmd_details *cmd_details)
7398 {
7399         struct i40e_aq_desc desc;
7400         enum i40e_status_code status;
7401
7402         i40e_fill_default_direct_cmd_desc(&desc,
7403                                           i40e_aqc_opc_clear_all_wol_filters);
7404
7405         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7406
7407         return status;
7408 }
7409
7410 /**
7411  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7412  * @hw: pointer to the hw struct
7413  * @buff: command buffer (size in bytes = buff_size)
7414  * @buff_size: buffer size in bytes
7415  * @track_id: package tracking id
7416  * @error_offset: returns error offset
7417  * @error_info: returns error information
7418  * @cmd_details: pointer to command details structure or NULL
7419  **/
7420 enum
7421 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7422                                    u16 buff_size, u32 track_id,
7423                                    u32 *error_offset, u32 *error_info,
7424                                    struct i40e_asq_cmd_details *cmd_details)
7425 {
7426         struct i40e_aq_desc desc;
7427         struct i40e_aqc_write_personalization_profile *cmd =
7428                 (struct i40e_aqc_write_personalization_profile *)
7429                 &desc.params.raw;
7430         struct i40e_aqc_write_ddp_resp *resp;
7431         enum i40e_status_code status;
7432
7433         i40e_fill_default_direct_cmd_desc(&desc,
7434                                   i40e_aqc_opc_write_personalization_profile);
7435
7436         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7437         if (buff_size > I40E_AQ_LARGE_BUF)
7438                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7439
7440         desc.datalen = CPU_TO_LE16(buff_size);
7441
7442         cmd->profile_track_id = CPU_TO_LE32(track_id);
7443
7444         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7445         if (!status) {
7446                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7447                 if (error_offset)
7448                         *error_offset = LE32_TO_CPU(resp->error_offset);
7449                 if (error_info)
7450                         *error_info = LE32_TO_CPU(resp->error_info);
7451         }
7452
7453         return status;
7454 }
7455
7456 /**
7457  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7458  * @hw: pointer to the hw struct
7459  * @buff: command buffer (size in bytes = buff_size)
7460  * @buff_size: buffer size in bytes
7461  * @flags: AdminQ command flags
7462  * @cmd_details: pointer to command details structure or NULL
7463  **/
7464 enum
7465 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7466                                       u16 buff_size, u8 flags,
7467                                       struct i40e_asq_cmd_details *cmd_details)
7468 {
7469         struct i40e_aq_desc desc;
7470         struct i40e_aqc_get_applied_profiles *cmd =
7471                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7472         enum i40e_status_code status;
7473
7474         i40e_fill_default_direct_cmd_desc(&desc,
7475                           i40e_aqc_opc_get_personalization_profile_list);
7476
7477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7478         if (buff_size > I40E_AQ_LARGE_BUF)
7479                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7480         desc.datalen = CPU_TO_LE16(buff_size);
7481
7482         cmd->flags = flags;
7483
7484         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7485
7486         return status;
7487 }
7488
7489 /**
7490  * i40e_find_segment_in_package
7491  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7492  * @pkg_hdr: pointer to the package header to be searched
7493  *
7494  * This function searches a package file for a particular segment type. On
7495  * success it returns a pointer to the segment header, otherwise it will
7496  * return NULL.
7497  **/
7498 struct i40e_generic_seg_header *
7499 i40e_find_segment_in_package(u32 segment_type,
7500                              struct i40e_package_header *pkg_hdr)
7501 {
7502         struct i40e_generic_seg_header *segment;
7503         u32 i;
7504
7505         /* Search all package segments for the requested segment type */
7506         for (i = 0; i < pkg_hdr->segment_count; i++) {
7507                 segment =
7508                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7509                          pkg_hdr->segment_offset[i]);
7510
7511                 if (segment->type == segment_type)
7512                         return segment;
7513         }
7514
7515         return NULL;
7516 }
7517
7518 /* Get section table in profile */
7519 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7520         do {                                                            \
7521                 struct i40e_profile_segment *p = (profile);             \
7522                 u32 count;                                              \
7523                 u32 *nvm;                                               \
7524                 count = p->device_table_count;                          \
7525                 nvm = (u32 *)&p->device_table[count];                   \
7526                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7527         } while (0)
7528
7529 /* Get section header in profile */
7530 #define I40E_SECTION_HEADER(profile, offset)                            \
7531         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7532
7533 /**
7534  * i40e_find_section_in_profile
7535  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7536  * @profile: pointer to the i40e segment header to be searched
7537  *
7538  * This function searches i40e segment for a particular section type. On
7539  * success it returns a pointer to the section header, otherwise it will
7540  * return NULL.
7541  **/
7542 struct i40e_profile_section_header *
7543 i40e_find_section_in_profile(u32 section_type,
7544                              struct i40e_profile_segment *profile)
7545 {
7546         struct i40e_profile_section_header *sec;
7547         struct i40e_section_table *sec_tbl;
7548         u32 sec_off;
7549         u32 i;
7550
7551         if (profile->header.type != SEGMENT_TYPE_I40E)
7552                 return NULL;
7553
7554         I40E_SECTION_TABLE(profile, sec_tbl);
7555
7556         for (i = 0; i < sec_tbl->section_count; i++) {
7557                 sec_off = sec_tbl->section_offset[i];
7558                 sec = I40E_SECTION_HEADER(profile, sec_off);
7559                 if (sec->section.type == section_type)
7560                         return sec;
7561         }
7562
7563         return NULL;
7564 }
7565
7566 /**
7567  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7568  * @hw: pointer to the hw struct
7569  * @aq: command buffer containing all data to execute AQ
7570  **/
7571 STATIC enum
7572 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7573                                           struct i40e_profile_aq_section *aq)
7574 {
7575         enum i40e_status_code status;
7576         struct i40e_aq_desc desc;
7577         u8 *msg = NULL;
7578         u16 msglen;
7579
7580         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7581         desc.flags |= CPU_TO_LE16(aq->flags);
7582         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7583                     I40E_NONDMA_TO_NONDMA);
7584
7585         msglen = aq->datalen;
7586         if (msglen) {
7587                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7588                                                 I40E_AQ_FLAG_RD));
7589                 if (msglen > I40E_AQ_LARGE_BUF)
7590                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7591                 desc.datalen = CPU_TO_LE16(msglen);
7592                 msg = &aq->data[0];
7593         }
7594
7595         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7596
7597         if (status != I40E_SUCCESS) {
7598                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7599                            "unable to exec DDP AQ opcode %u, error %d\n",
7600                            aq->opcode, status);
7601                 return status;
7602         }
7603
7604         /* copy returned desc to aq_buf */
7605         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7606                     I40E_NONDMA_TO_NONDMA);
7607
7608         return I40E_SUCCESS;
7609 }
7610
7611 /**
7612  * i40e_validate_profile
7613  * @hw: pointer to the hardware structure
7614  * @profile: pointer to the profile segment of the package to be validated
7615  * @track_id: package tracking id
7616  * @rollback: flag if the profile is for rollback.
7617  *
7618  * Validates supported devices and profile's sections.
7619  */
7620 STATIC enum i40e_status_code
7621 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7622                       u32 track_id, bool rollback)
7623 {
7624         struct i40e_profile_section_header *sec = NULL;
7625         enum i40e_status_code status = I40E_SUCCESS;
7626         struct i40e_section_table *sec_tbl;
7627         u32 vendor_dev_id;
7628         u32 dev_cnt;
7629         u32 sec_off;
7630         u32 i;
7631
7632         if (track_id == I40E_DDP_TRACKID_INVALID) {
7633                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7634                 return I40E_NOT_SUPPORTED;
7635         }
7636
7637         dev_cnt = profile->device_table_count;
7638         for (i = 0; i < dev_cnt; i++) {
7639                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7640                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7641                     hw->device_id == (vendor_dev_id & 0xFFFF))
7642                         break;
7643         }
7644         if (dev_cnt && (i == dev_cnt)) {
7645                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7646                            "Device doesn't support DDP\n");
7647                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7648         }
7649
7650         I40E_SECTION_TABLE(profile, sec_tbl);
7651
7652         /* Validate sections types */
7653         for (i = 0; i < sec_tbl->section_count; i++) {
7654                 sec_off = sec_tbl->section_offset[i];
7655                 sec = I40E_SECTION_HEADER(profile, sec_off);
7656                 if (rollback) {
7657                         if (sec->section.type == SECTION_TYPE_MMIO ||
7658                             sec->section.type == SECTION_TYPE_AQ ||
7659                             sec->section.type == SECTION_TYPE_RB_AQ) {
7660                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7661                                            "Not a roll-back package\n");
7662                                 return I40E_NOT_SUPPORTED;
7663                         }
7664                 } else {
7665                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7666                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7667                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7668                                            "Not an original package\n");
7669                                 return I40E_NOT_SUPPORTED;
7670                         }
7671                 }
7672         }
7673
7674         return status;
7675 }
7676
7677 /**
7678  * i40e_write_profile
7679  * @hw: pointer to the hardware structure
7680  * @profile: pointer to the profile segment of the package to be downloaded
7681  * @track_id: package tracking id
7682  *
7683  * Handles the download of a complete package.
7684  */
7685 enum i40e_status_code
7686 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7687                    u32 track_id)
7688 {
7689         enum i40e_status_code status = I40E_SUCCESS;
7690         struct i40e_section_table *sec_tbl;
7691         struct i40e_profile_section_header *sec = NULL;
7692         struct i40e_profile_aq_section *ddp_aq;
7693         u32 section_size = 0;
7694         u32 offset = 0, info = 0;
7695         u32 sec_off;
7696         u32 i;
7697
7698         status = i40e_validate_profile(hw, profile, track_id, false);
7699         if (status)
7700                 return status;
7701
7702         I40E_SECTION_TABLE(profile, sec_tbl);
7703
7704         for (i = 0; i < sec_tbl->section_count; i++) {
7705                 sec_off = sec_tbl->section_offset[i];
7706                 sec = I40E_SECTION_HEADER(profile, sec_off);
7707                 /* Process generic admin command */
7708                 if (sec->section.type == SECTION_TYPE_AQ) {
7709                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7710                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7711                         if (status) {
7712                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7713                                            "Failed to execute aq: section %d, opcode %u\n",
7714                                            i, ddp_aq->opcode);
7715                                 break;
7716                         }
7717                         sec->section.type = SECTION_TYPE_RB_AQ;
7718                 }
7719
7720                 /* Skip any non-mmio sections */
7721                 if (sec->section.type != SECTION_TYPE_MMIO)
7722                         continue;
7723
7724                 section_size = sec->section.size +
7725                         sizeof(struct i40e_profile_section_header);
7726
7727                 /* Write MMIO section */
7728                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7729                                            track_id, &offset, &info, NULL);
7730                 if (status) {
7731                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7732                                    "Failed to write profile: section %d, offset %d, info %d\n",
7733                                    i, offset, info);
7734                         break;
7735                 }
7736         }
7737         return status;
7738 }
7739
7740 /**
7741  * i40e_rollback_profile
7742  * @hw: pointer to the hardware structure
7743  * @profile: pointer to the profile segment of the package to be removed
7744  * @track_id: package tracking id
7745  *
7746  * Rolls back previously loaded package.
7747  */
7748 enum i40e_status_code
7749 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7750                       u32 track_id)
7751 {
7752         struct i40e_profile_section_header *sec = NULL;
7753         enum i40e_status_code status = I40E_SUCCESS;
7754         struct i40e_section_table *sec_tbl;
7755         u32 offset = 0, info = 0;
7756         u32 section_size = 0;
7757         u32 sec_off;
7758         int i;
7759
7760         status = i40e_validate_profile(hw, profile, track_id, true);
7761         if (status)
7762                 return status;
7763
7764         I40E_SECTION_TABLE(profile, sec_tbl);
7765
7766         /* For rollback write sections in reverse */
7767         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7768                 sec_off = sec_tbl->section_offset[i];
7769                 sec = I40E_SECTION_HEADER(profile, sec_off);
7770
7771                 /* Skip any non-rollback sections */
7772                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7773                         continue;
7774
7775                 section_size = sec->section.size +
7776                         sizeof(struct i40e_profile_section_header);
7777
7778                 /* Write roll-back MMIO section */
7779                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7780                                            track_id, &offset, &info, NULL);
7781                 if (status) {
7782                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7783                                    "Failed to write profile: section %d, offset %d, info %d\n",
7784                                    i, offset, info);
7785                         break;
7786                 }
7787         }
7788         return status;
7789 }
7790
7791 /**
7792  * i40e_add_pinfo_to_list
7793  * @hw: pointer to the hardware structure
7794  * @profile: pointer to the profile segment of the package
7795  * @profile_info_sec: buffer for information section
7796  * @track_id: package tracking id
7797  *
7798  * Register a profile to the list of loaded profiles.
7799  */
7800 enum i40e_status_code
7801 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7802                        struct i40e_profile_segment *profile,
7803                        u8 *profile_info_sec, u32 track_id)
7804 {
7805         enum i40e_status_code status = I40E_SUCCESS;
7806         struct i40e_profile_section_header *sec = NULL;
7807         struct i40e_profile_info *pinfo;
7808         u32 offset = 0, info = 0;
7809
7810         sec = (struct i40e_profile_section_header *)profile_info_sec;
7811         sec->tbl_size = 1;
7812         sec->data_end = sizeof(struct i40e_profile_section_header) +
7813                         sizeof(struct i40e_profile_info);
7814         sec->section.type = SECTION_TYPE_INFO;
7815         sec->section.offset = sizeof(struct i40e_profile_section_header);
7816         sec->section.size = sizeof(struct i40e_profile_info);
7817         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7818                                              sec->section.offset);
7819         pinfo->track_id = track_id;
7820         pinfo->version = profile->version;
7821         pinfo->op = I40E_DDP_ADD_TRACKID;
7822         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7823                     I40E_NONDMA_TO_NONDMA);
7824
7825         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7826                                    track_id, &offset, &info, NULL);
7827         return status;
7828 }