1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
74 #ifdef X722_A0_SUPPORT
75 case I40E_DEV_ID_X722_A0:
77 case I40E_DEV_ID_KX_X722:
78 case I40E_DEV_ID_QSFP_X722:
79 case I40E_DEV_ID_SFP_X722:
80 case I40E_DEV_ID_1G_BASE_T_X722:
81 case I40E_DEV_ID_10G_BASE_T_X722:
82 case I40E_DEV_ID_SFP_I_X722:
83 hw->mac.type = I40E_MAC_X722;
85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
86 case I40E_DEV_ID_X722_VF:
87 #ifdef X722_A0_SUPPORT
88 case I40E_DEV_ID_X722_A0_VF:
90 hw->mac.type = I40E_MAC_X722_VF;
92 #endif /* INTEGRATED_VF || VF_DRIVER */
93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
95 case I40E_DEV_ID_VF_HV:
96 case I40E_DEV_ID_ADAPTIVE_VF:
97 hw->mac.type = I40E_MAC_VF;
101 hw->mac.type = I40E_MAC_GENERIC;
105 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
108 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
109 hw->mac.type, status);
114 * i40e_aq_str - convert AQ err code to a string
115 * @hw: pointer to the HW structure
116 * @aq_err: the AQ error code to convert
118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
123 case I40E_AQ_RC_EPERM:
124 return "I40E_AQ_RC_EPERM";
125 case I40E_AQ_RC_ENOENT:
126 return "I40E_AQ_RC_ENOENT";
127 case I40E_AQ_RC_ESRCH:
128 return "I40E_AQ_RC_ESRCH";
129 case I40E_AQ_RC_EINTR:
130 return "I40E_AQ_RC_EINTR";
132 return "I40E_AQ_RC_EIO";
133 case I40E_AQ_RC_ENXIO:
134 return "I40E_AQ_RC_ENXIO";
135 case I40E_AQ_RC_E2BIG:
136 return "I40E_AQ_RC_E2BIG";
137 case I40E_AQ_RC_EAGAIN:
138 return "I40E_AQ_RC_EAGAIN";
139 case I40E_AQ_RC_ENOMEM:
140 return "I40E_AQ_RC_ENOMEM";
141 case I40E_AQ_RC_EACCES:
142 return "I40E_AQ_RC_EACCES";
143 case I40E_AQ_RC_EFAULT:
144 return "I40E_AQ_RC_EFAULT";
145 case I40E_AQ_RC_EBUSY:
146 return "I40E_AQ_RC_EBUSY";
147 case I40E_AQ_RC_EEXIST:
148 return "I40E_AQ_RC_EEXIST";
149 case I40E_AQ_RC_EINVAL:
150 return "I40E_AQ_RC_EINVAL";
151 case I40E_AQ_RC_ENOTTY:
152 return "I40E_AQ_RC_ENOTTY";
153 case I40E_AQ_RC_ENOSPC:
154 return "I40E_AQ_RC_ENOSPC";
155 case I40E_AQ_RC_ENOSYS:
156 return "I40E_AQ_RC_ENOSYS";
157 case I40E_AQ_RC_ERANGE:
158 return "I40E_AQ_RC_ERANGE";
159 case I40E_AQ_RC_EFLUSHED:
160 return "I40E_AQ_RC_EFLUSHED";
161 case I40E_AQ_RC_BAD_ADDR:
162 return "I40E_AQ_RC_BAD_ADDR";
163 case I40E_AQ_RC_EMODE:
164 return "I40E_AQ_RC_EMODE";
165 case I40E_AQ_RC_EFBIG:
166 return "I40E_AQ_RC_EFBIG";
169 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
174 * i40e_stat_str - convert status err code to a string
175 * @hw: pointer to the HW structure
176 * @stat_err: the status error code to convert
178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
184 return "I40E_ERR_NVM";
185 case I40E_ERR_NVM_CHECKSUM:
186 return "I40E_ERR_NVM_CHECKSUM";
188 return "I40E_ERR_PHY";
189 case I40E_ERR_CONFIG:
190 return "I40E_ERR_CONFIG";
192 return "I40E_ERR_PARAM";
193 case I40E_ERR_MAC_TYPE:
194 return "I40E_ERR_MAC_TYPE";
195 case I40E_ERR_UNKNOWN_PHY:
196 return "I40E_ERR_UNKNOWN_PHY";
197 case I40E_ERR_LINK_SETUP:
198 return "I40E_ERR_LINK_SETUP";
199 case I40E_ERR_ADAPTER_STOPPED:
200 return "I40E_ERR_ADAPTER_STOPPED";
201 case I40E_ERR_INVALID_MAC_ADDR:
202 return "I40E_ERR_INVALID_MAC_ADDR";
203 case I40E_ERR_DEVICE_NOT_SUPPORTED:
204 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
205 case I40E_ERR_MASTER_REQUESTS_PENDING:
206 return "I40E_ERR_MASTER_REQUESTS_PENDING";
207 case I40E_ERR_INVALID_LINK_SETTINGS:
208 return "I40E_ERR_INVALID_LINK_SETTINGS";
209 case I40E_ERR_AUTONEG_NOT_COMPLETE:
210 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
211 case I40E_ERR_RESET_FAILED:
212 return "I40E_ERR_RESET_FAILED";
213 case I40E_ERR_SWFW_SYNC:
214 return "I40E_ERR_SWFW_SYNC";
215 case I40E_ERR_NO_AVAILABLE_VSI:
216 return "I40E_ERR_NO_AVAILABLE_VSI";
217 case I40E_ERR_NO_MEMORY:
218 return "I40E_ERR_NO_MEMORY";
219 case I40E_ERR_BAD_PTR:
220 return "I40E_ERR_BAD_PTR";
221 case I40E_ERR_RING_FULL:
222 return "I40E_ERR_RING_FULL";
223 case I40E_ERR_INVALID_PD_ID:
224 return "I40E_ERR_INVALID_PD_ID";
225 case I40E_ERR_INVALID_QP_ID:
226 return "I40E_ERR_INVALID_QP_ID";
227 case I40E_ERR_INVALID_CQ_ID:
228 return "I40E_ERR_INVALID_CQ_ID";
229 case I40E_ERR_INVALID_CEQ_ID:
230 return "I40E_ERR_INVALID_CEQ_ID";
231 case I40E_ERR_INVALID_AEQ_ID:
232 return "I40E_ERR_INVALID_AEQ_ID";
233 case I40E_ERR_INVALID_SIZE:
234 return "I40E_ERR_INVALID_SIZE";
235 case I40E_ERR_INVALID_ARP_INDEX:
236 return "I40E_ERR_INVALID_ARP_INDEX";
237 case I40E_ERR_INVALID_FPM_FUNC_ID:
238 return "I40E_ERR_INVALID_FPM_FUNC_ID";
239 case I40E_ERR_QP_INVALID_MSG_SIZE:
240 return "I40E_ERR_QP_INVALID_MSG_SIZE";
241 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
242 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
243 case I40E_ERR_INVALID_FRAG_COUNT:
244 return "I40E_ERR_INVALID_FRAG_COUNT";
245 case I40E_ERR_QUEUE_EMPTY:
246 return "I40E_ERR_QUEUE_EMPTY";
247 case I40E_ERR_INVALID_ALIGNMENT:
248 return "I40E_ERR_INVALID_ALIGNMENT";
249 case I40E_ERR_FLUSHED_QUEUE:
250 return "I40E_ERR_FLUSHED_QUEUE";
251 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
252 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
253 case I40E_ERR_INVALID_IMM_DATA_SIZE:
254 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
255 case I40E_ERR_TIMEOUT:
256 return "I40E_ERR_TIMEOUT";
257 case I40E_ERR_OPCODE_MISMATCH:
258 return "I40E_ERR_OPCODE_MISMATCH";
259 case I40E_ERR_CQP_COMPL_ERROR:
260 return "I40E_ERR_CQP_COMPL_ERROR";
261 case I40E_ERR_INVALID_VF_ID:
262 return "I40E_ERR_INVALID_VF_ID";
263 case I40E_ERR_INVALID_HMCFN_ID:
264 return "I40E_ERR_INVALID_HMCFN_ID";
265 case I40E_ERR_BACKING_PAGE_ERROR:
266 return "I40E_ERR_BACKING_PAGE_ERROR";
267 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
268 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
269 case I40E_ERR_INVALID_PBLE_INDEX:
270 return "I40E_ERR_INVALID_PBLE_INDEX";
271 case I40E_ERR_INVALID_SD_INDEX:
272 return "I40E_ERR_INVALID_SD_INDEX";
273 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
274 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
275 case I40E_ERR_INVALID_SD_TYPE:
276 return "I40E_ERR_INVALID_SD_TYPE";
277 case I40E_ERR_MEMCPY_FAILED:
278 return "I40E_ERR_MEMCPY_FAILED";
279 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
280 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
281 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
282 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
283 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
284 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
285 case I40E_ERR_SRQ_ENABLED:
286 return "I40E_ERR_SRQ_ENABLED";
287 case I40E_ERR_ADMIN_QUEUE_ERROR:
288 return "I40E_ERR_ADMIN_QUEUE_ERROR";
289 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
290 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
291 case I40E_ERR_BUF_TOO_SHORT:
292 return "I40E_ERR_BUF_TOO_SHORT";
293 case I40E_ERR_ADMIN_QUEUE_FULL:
294 return "I40E_ERR_ADMIN_QUEUE_FULL";
295 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
296 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
297 case I40E_ERR_BAD_IWARP_CQE:
298 return "I40E_ERR_BAD_IWARP_CQE";
299 case I40E_ERR_NVM_BLANK_MODE:
300 return "I40E_ERR_NVM_BLANK_MODE";
301 case I40E_ERR_NOT_IMPLEMENTED:
302 return "I40E_ERR_NOT_IMPLEMENTED";
303 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
304 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
305 case I40E_ERR_DIAG_TEST_FAILED:
306 return "I40E_ERR_DIAG_TEST_FAILED";
307 case I40E_ERR_NOT_READY:
308 return "I40E_ERR_NOT_READY";
309 case I40E_NOT_SUPPORTED:
310 return "I40E_NOT_SUPPORTED";
311 case I40E_ERR_FIRMWARE_API_VERSION:
312 return "I40E_ERR_FIRMWARE_API_VERSION";
315 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
321 * @hw: debug mask related to admin queue
323 * @desc: pointer to admin queue descriptor
324 * @buffer: pointer to command buffer
325 * @buf_len: max length of buffer
327 * Dumps debug log about adminq command with descriptor contents.
329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
330 void *buffer, u16 buf_len)
332 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
333 u16 len = LE16_TO_CPU(aq_desc->datalen);
334 u8 *buf = (u8 *)buffer;
337 if ((!(mask & hw->debug_mask)) || (desc == NULL))
341 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
342 LE16_TO_CPU(aq_desc->opcode),
343 LE16_TO_CPU(aq_desc->flags),
344 LE16_TO_CPU(aq_desc->datalen),
345 LE16_TO_CPU(aq_desc->retval));
346 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
347 LE32_TO_CPU(aq_desc->cookie_high),
348 LE32_TO_CPU(aq_desc->cookie_low));
349 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
350 LE32_TO_CPU(aq_desc->params.internal.param0),
351 LE32_TO_CPU(aq_desc->params.internal.param1));
352 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
353 LE32_TO_CPU(aq_desc->params.external.addr_high),
354 LE32_TO_CPU(aq_desc->params.external.addr_low));
356 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
357 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
360 /* write the full 16-byte chunks */
361 for (i = 0; i < (len - 16); i += 16)
363 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
364 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
365 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
366 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
367 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
368 /* the most we could have left is 16 bytes, pad with zeros */
374 memset(d_buf, 0, sizeof(d_buf));
375 for (j = 0; i < len; j++, i++)
378 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
379 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
380 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
381 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
382 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
388 * i40e_check_asq_alive
389 * @hw: pointer to the hw struct
391 * Returns true if Queue is enabled else false.
393 bool i40e_check_asq_alive(struct i40e_hw *hw)
399 return !!(rd32(hw, hw->aq.asq.len) &
400 I40E_PF_ATQLEN_ATQENABLE_MASK);
402 return !!(rd32(hw, hw->aq.asq.len) &
403 I40E_PF_ATQLEN_ATQENABLE_MASK);
404 #endif /* INTEGRATED_VF */
405 #endif /* PF_DRIVER */
409 return !!(rd32(hw, hw->aq.asq.len) &
410 I40E_VF_ATQLEN1_ATQENABLE_MASK);
412 return !!(rd32(hw, hw->aq.asq.len) &
413 I40E_VF_ATQLEN1_ATQENABLE_MASK);
414 #endif /* INTEGRATED_VF */
415 #endif /* VF_DRIVER */
420 * i40e_aq_queue_shutdown
421 * @hw: pointer to the hw struct
422 * @unloading: is the driver unloading itself
424 * Tell the Firmware that we're shutting down the AdminQ and whether
425 * or not the driver is unloading as well.
427 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
430 struct i40e_aq_desc desc;
431 struct i40e_aqc_queue_shutdown *cmd =
432 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
433 enum i40e_status_code status;
435 i40e_fill_default_direct_cmd_desc(&desc,
436 i40e_aqc_opc_queue_shutdown);
439 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
440 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
446 * i40e_aq_get_set_rss_lut
447 * @hw: pointer to the hardware structure
448 * @vsi_id: vsi fw index
449 * @pf_lut: for PF table set true, for VSI table set false
450 * @lut: pointer to the lut buffer provided by the caller
451 * @lut_size: size of the lut buffer
452 * @set: set true to set the table, false to get the table
454 * Internal function to get or set RSS look up table
456 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
457 u16 vsi_id, bool pf_lut,
458 u8 *lut, u16 lut_size,
461 enum i40e_status_code status;
462 struct i40e_aq_desc desc;
463 struct i40e_aqc_get_set_rss_lut *cmd_resp =
464 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
467 i40e_fill_default_direct_cmd_desc(&desc,
468 i40e_aqc_opc_set_rss_lut);
470 i40e_fill_default_direct_cmd_desc(&desc,
471 i40e_aqc_opc_get_rss_lut);
473 /* Indirect command */
474 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
475 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
478 CPU_TO_LE16((u16)((vsi_id <<
479 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
480 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
481 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
484 cmd_resp->flags |= CPU_TO_LE16((u16)
485 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
486 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
487 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
489 cmd_resp->flags |= CPU_TO_LE16((u16)
490 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
491 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
492 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
494 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
500 * i40e_aq_get_rss_lut
501 * @hw: pointer to the hardware structure
502 * @vsi_id: vsi fw index
503 * @pf_lut: for PF table set true, for VSI table set false
504 * @lut: pointer to the lut buffer provided by the caller
505 * @lut_size: size of the lut buffer
507 * get the RSS lookup table, PF or VSI type
509 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
510 bool pf_lut, u8 *lut, u16 lut_size)
512 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
517 * i40e_aq_set_rss_lut
518 * @hw: pointer to the hardware structure
519 * @vsi_id: vsi fw index
520 * @pf_lut: for PF table set true, for VSI table set false
521 * @lut: pointer to the lut buffer provided by the caller
522 * @lut_size: size of the lut buffer
524 * set the RSS lookup table, PF or VSI type
526 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
527 bool pf_lut, u8 *lut, u16 lut_size)
529 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
533 * i40e_aq_get_set_rss_key
534 * @hw: pointer to the hw struct
535 * @vsi_id: vsi fw index
536 * @key: pointer to key info struct
537 * @set: set true to set the key, false to get the key
539 * get the RSS key per VSI
541 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
543 struct i40e_aqc_get_set_rss_key_data *key,
546 enum i40e_status_code status;
547 struct i40e_aq_desc desc;
548 struct i40e_aqc_get_set_rss_key *cmd_resp =
549 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
550 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
553 i40e_fill_default_direct_cmd_desc(&desc,
554 i40e_aqc_opc_set_rss_key);
556 i40e_fill_default_direct_cmd_desc(&desc,
557 i40e_aqc_opc_get_rss_key);
559 /* Indirect command */
560 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
561 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
564 CPU_TO_LE16((u16)((vsi_id <<
565 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
566 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
567 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
569 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
575 * i40e_aq_get_rss_key
576 * @hw: pointer to the hw struct
577 * @vsi_id: vsi fw index
578 * @key: pointer to key info struct
581 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
583 struct i40e_aqc_get_set_rss_key_data *key)
585 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
589 * i40e_aq_set_rss_key
590 * @hw: pointer to the hw struct
591 * @vsi_id: vsi fw index
592 * @key: pointer to key info struct
594 * set the RSS key per VSI
596 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
598 struct i40e_aqc_get_set_rss_key_data *key)
600 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
603 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
604 * hardware to a bit-field that can be used by SW to more easily determine the
607 * Macros are used to shorten the table lines and make this table human
610 * We store the PTYPE in the top byte of the bit field - this is just so that
611 * we can check that the table doesn't have a row missing, as the index into
612 * the table should be the PTYPE.
616 * IF NOT i40e_ptype_lookup[ptype].known
619 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
620 * Use the rest of the fields to look at the tunnels, inner protocols, etc
622 * Use the enum i40e_rx_l2_ptype to decode the packet type
626 /* macro to make the table lines short */
627 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
630 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
631 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
632 I40E_RX_PTYPE_##OUTER_FRAG, \
633 I40E_RX_PTYPE_TUNNEL_##T, \
634 I40E_RX_PTYPE_TUNNEL_END_##TE, \
635 I40E_RX_PTYPE_##TEF, \
636 I40E_RX_PTYPE_INNER_PROT_##I, \
637 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
639 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
640 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
642 /* shorter macros makes the table fit but are terse */
643 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
644 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
645 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
647 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
648 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
649 /* L2 Packet types */
650 I40E_PTT_UNUSED_ENTRY(0),
651 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
652 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
653 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
654 I40E_PTT_UNUSED_ENTRY(4),
655 I40E_PTT_UNUSED_ENTRY(5),
656 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
657 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
658 I40E_PTT_UNUSED_ENTRY(8),
659 I40E_PTT_UNUSED_ENTRY(9),
660 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
661 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
662 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
663 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
664 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
665 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
666 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
667 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
668 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
669 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
670 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 /* Non Tunneled IPv4 */
674 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
677 I40E_PTT_UNUSED_ENTRY(25),
678 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
679 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
680 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
683 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
684 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
685 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
686 I40E_PTT_UNUSED_ENTRY(32),
687 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
688 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
689 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
692 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
693 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
694 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
695 I40E_PTT_UNUSED_ENTRY(39),
696 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
697 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
698 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
700 /* IPv4 --> GRE/NAT */
701 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
703 /* IPv4 --> GRE/NAT --> IPv4 */
704 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
705 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
706 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
707 I40E_PTT_UNUSED_ENTRY(47),
708 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
709 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
710 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
712 /* IPv4 --> GRE/NAT --> IPv6 */
713 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
714 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
715 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
716 I40E_PTT_UNUSED_ENTRY(54),
717 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
718 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
719 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
721 /* IPv4 --> GRE/NAT --> MAC */
722 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
724 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
725 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(62),
729 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
733 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
734 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(69),
738 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
742 /* IPv4 --> GRE/NAT --> MAC/VLAN */
743 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
745 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
746 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
747 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
748 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
749 I40E_PTT_UNUSED_ENTRY(77),
750 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
751 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
752 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
754 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
755 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
756 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
757 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(84),
759 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
760 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
761 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
763 /* Non Tunneled IPv6 */
764 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
765 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
766 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
767 I40E_PTT_UNUSED_ENTRY(91),
768 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
769 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
770 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
773 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
774 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
775 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
776 I40E_PTT_UNUSED_ENTRY(98),
777 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
778 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
779 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
782 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
783 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
784 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
785 I40E_PTT_UNUSED_ENTRY(105),
786 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
787 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
788 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
790 /* IPv6 --> GRE/NAT */
791 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
793 /* IPv6 --> GRE/NAT -> IPv4 */
794 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
795 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
796 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
797 I40E_PTT_UNUSED_ENTRY(113),
798 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
799 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
800 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
802 /* IPv6 --> GRE/NAT -> IPv6 */
803 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
804 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
805 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
806 I40E_PTT_UNUSED_ENTRY(120),
807 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
808 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
809 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
811 /* IPv6 --> GRE/NAT -> MAC */
812 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
814 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
815 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
816 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
817 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
818 I40E_PTT_UNUSED_ENTRY(128),
819 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
820 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
821 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
823 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
824 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
825 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
826 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
827 I40E_PTT_UNUSED_ENTRY(135),
828 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
829 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
830 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
832 /* IPv6 --> GRE/NAT -> MAC/VLAN */
833 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
835 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
836 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
837 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
838 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
839 I40E_PTT_UNUSED_ENTRY(143),
840 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
841 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
842 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
844 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
845 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
846 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
847 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
848 I40E_PTT_UNUSED_ENTRY(150),
849 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
850 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
851 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
854 I40E_PTT_UNUSED_ENTRY(154),
855 I40E_PTT_UNUSED_ENTRY(155),
856 I40E_PTT_UNUSED_ENTRY(156),
857 I40E_PTT_UNUSED_ENTRY(157),
858 I40E_PTT_UNUSED_ENTRY(158),
859 I40E_PTT_UNUSED_ENTRY(159),
861 I40E_PTT_UNUSED_ENTRY(160),
862 I40E_PTT_UNUSED_ENTRY(161),
863 I40E_PTT_UNUSED_ENTRY(162),
864 I40E_PTT_UNUSED_ENTRY(163),
865 I40E_PTT_UNUSED_ENTRY(164),
866 I40E_PTT_UNUSED_ENTRY(165),
867 I40E_PTT_UNUSED_ENTRY(166),
868 I40E_PTT_UNUSED_ENTRY(167),
869 I40E_PTT_UNUSED_ENTRY(168),
870 I40E_PTT_UNUSED_ENTRY(169),
872 I40E_PTT_UNUSED_ENTRY(170),
873 I40E_PTT_UNUSED_ENTRY(171),
874 I40E_PTT_UNUSED_ENTRY(172),
875 I40E_PTT_UNUSED_ENTRY(173),
876 I40E_PTT_UNUSED_ENTRY(174),
877 I40E_PTT_UNUSED_ENTRY(175),
878 I40E_PTT_UNUSED_ENTRY(176),
879 I40E_PTT_UNUSED_ENTRY(177),
880 I40E_PTT_UNUSED_ENTRY(178),
881 I40E_PTT_UNUSED_ENTRY(179),
883 I40E_PTT_UNUSED_ENTRY(180),
884 I40E_PTT_UNUSED_ENTRY(181),
885 I40E_PTT_UNUSED_ENTRY(182),
886 I40E_PTT_UNUSED_ENTRY(183),
887 I40E_PTT_UNUSED_ENTRY(184),
888 I40E_PTT_UNUSED_ENTRY(185),
889 I40E_PTT_UNUSED_ENTRY(186),
890 I40E_PTT_UNUSED_ENTRY(187),
891 I40E_PTT_UNUSED_ENTRY(188),
892 I40E_PTT_UNUSED_ENTRY(189),
894 I40E_PTT_UNUSED_ENTRY(190),
895 I40E_PTT_UNUSED_ENTRY(191),
896 I40E_PTT_UNUSED_ENTRY(192),
897 I40E_PTT_UNUSED_ENTRY(193),
898 I40E_PTT_UNUSED_ENTRY(194),
899 I40E_PTT_UNUSED_ENTRY(195),
900 I40E_PTT_UNUSED_ENTRY(196),
901 I40E_PTT_UNUSED_ENTRY(197),
902 I40E_PTT_UNUSED_ENTRY(198),
903 I40E_PTT_UNUSED_ENTRY(199),
905 I40E_PTT_UNUSED_ENTRY(200),
906 I40E_PTT_UNUSED_ENTRY(201),
907 I40E_PTT_UNUSED_ENTRY(202),
908 I40E_PTT_UNUSED_ENTRY(203),
909 I40E_PTT_UNUSED_ENTRY(204),
910 I40E_PTT_UNUSED_ENTRY(205),
911 I40E_PTT_UNUSED_ENTRY(206),
912 I40E_PTT_UNUSED_ENTRY(207),
913 I40E_PTT_UNUSED_ENTRY(208),
914 I40E_PTT_UNUSED_ENTRY(209),
916 I40E_PTT_UNUSED_ENTRY(210),
917 I40E_PTT_UNUSED_ENTRY(211),
918 I40E_PTT_UNUSED_ENTRY(212),
919 I40E_PTT_UNUSED_ENTRY(213),
920 I40E_PTT_UNUSED_ENTRY(214),
921 I40E_PTT_UNUSED_ENTRY(215),
922 I40E_PTT_UNUSED_ENTRY(216),
923 I40E_PTT_UNUSED_ENTRY(217),
924 I40E_PTT_UNUSED_ENTRY(218),
925 I40E_PTT_UNUSED_ENTRY(219),
927 I40E_PTT_UNUSED_ENTRY(220),
928 I40E_PTT_UNUSED_ENTRY(221),
929 I40E_PTT_UNUSED_ENTRY(222),
930 I40E_PTT_UNUSED_ENTRY(223),
931 I40E_PTT_UNUSED_ENTRY(224),
932 I40E_PTT_UNUSED_ENTRY(225),
933 I40E_PTT_UNUSED_ENTRY(226),
934 I40E_PTT_UNUSED_ENTRY(227),
935 I40E_PTT_UNUSED_ENTRY(228),
936 I40E_PTT_UNUSED_ENTRY(229),
938 I40E_PTT_UNUSED_ENTRY(230),
939 I40E_PTT_UNUSED_ENTRY(231),
940 I40E_PTT_UNUSED_ENTRY(232),
941 I40E_PTT_UNUSED_ENTRY(233),
942 I40E_PTT_UNUSED_ENTRY(234),
943 I40E_PTT_UNUSED_ENTRY(235),
944 I40E_PTT_UNUSED_ENTRY(236),
945 I40E_PTT_UNUSED_ENTRY(237),
946 I40E_PTT_UNUSED_ENTRY(238),
947 I40E_PTT_UNUSED_ENTRY(239),
949 I40E_PTT_UNUSED_ENTRY(240),
950 I40E_PTT_UNUSED_ENTRY(241),
951 I40E_PTT_UNUSED_ENTRY(242),
952 I40E_PTT_UNUSED_ENTRY(243),
953 I40E_PTT_UNUSED_ENTRY(244),
954 I40E_PTT_UNUSED_ENTRY(245),
955 I40E_PTT_UNUSED_ENTRY(246),
956 I40E_PTT_UNUSED_ENTRY(247),
957 I40E_PTT_UNUSED_ENTRY(248),
958 I40E_PTT_UNUSED_ENTRY(249),
960 I40E_PTT_UNUSED_ENTRY(250),
961 I40E_PTT_UNUSED_ENTRY(251),
962 I40E_PTT_UNUSED_ENTRY(252),
963 I40E_PTT_UNUSED_ENTRY(253),
964 I40E_PTT_UNUSED_ENTRY(254),
965 I40E_PTT_UNUSED_ENTRY(255)
970 * i40e_validate_mac_addr - Validate unicast MAC address
971 * @mac_addr: pointer to MAC address
973 * Tests a MAC address to ensure it is a valid Individual Address
975 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
977 enum i40e_status_code status = I40E_SUCCESS;
979 DEBUGFUNC("i40e_validate_mac_addr");
981 /* Broadcast addresses ARE multicast addresses
982 * Make sure it is not a multicast address
983 * Reject the zero address
985 if (I40E_IS_MULTICAST(mac_addr) ||
986 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
987 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
988 status = I40E_ERR_INVALID_MAC_ADDR;
995 * i40e_init_shared_code - Initialize the shared code
996 * @hw: pointer to hardware structure
998 * This assigns the MAC type and PHY code and inits the NVM.
999 * Does not touch the hardware. This function must be called prior to any
1000 * other function in the shared code. The i40e_hw structure should be
1001 * memset to 0 prior to calling this function. The following fields in
1002 * hw structure should be filled in prior to calling this function:
1003 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1004 * subsystem_vendor_id, and revision_id
1006 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1008 enum i40e_status_code status = I40E_SUCCESS;
1009 u32 port, ari, func_rid;
1011 DEBUGFUNC("i40e_init_shared_code");
1013 i40e_set_mac_type(hw);
1015 switch (hw->mac.type) {
1016 case I40E_MAC_XL710:
1020 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1023 hw->phy.get_link_info = true;
1025 /* Determine port number and PF number*/
1026 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1027 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1028 hw->port = (u8)port;
1029 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1030 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1031 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1033 hw->pf_id = (u8)(func_rid & 0xff);
1035 hw->pf_id = (u8)(func_rid & 0x7);
1037 if (hw->mac.type == I40E_MAC_X722)
1038 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1040 status = i40e_init_nvm(hw);
1045 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1046 * @hw: pointer to the hw struct
1047 * @flags: a return indicator of what addresses were added to the addr store
1048 * @addrs: the requestor's mac addr store
1049 * @cmd_details: pointer to command details structure or NULL
1051 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1053 struct i40e_aqc_mac_address_read_data *addrs,
1054 struct i40e_asq_cmd_details *cmd_details)
1056 struct i40e_aq_desc desc;
1057 struct i40e_aqc_mac_address_read *cmd_data =
1058 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1059 enum i40e_status_code status;
1061 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1062 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1064 status = i40e_asq_send_command(hw, &desc, addrs,
1065 sizeof(*addrs), cmd_details);
1066 *flags = LE16_TO_CPU(cmd_data->command_flags);
1072 * i40e_aq_mac_address_write - Change the MAC addresses
1073 * @hw: pointer to the hw struct
1074 * @flags: indicates which MAC to be written
1075 * @mac_addr: address to write
1076 * @cmd_details: pointer to command details structure or NULL
1078 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1079 u16 flags, u8 *mac_addr,
1080 struct i40e_asq_cmd_details *cmd_details)
1082 struct i40e_aq_desc desc;
1083 struct i40e_aqc_mac_address_write *cmd_data =
1084 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1085 enum i40e_status_code status;
1087 i40e_fill_default_direct_cmd_desc(&desc,
1088 i40e_aqc_opc_mac_address_write);
1089 cmd_data->command_flags = CPU_TO_LE16(flags);
1090 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1091 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1092 ((u32)mac_addr[3] << 16) |
1093 ((u32)mac_addr[4] << 8) |
1096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1102 * i40e_get_mac_addr - get MAC address
1103 * @hw: pointer to the HW structure
1104 * @mac_addr: pointer to MAC address
1106 * Reads the adapter's MAC address from register
1108 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1110 struct i40e_aqc_mac_address_read_data addrs;
1111 enum i40e_status_code status;
1114 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1116 if (flags & I40E_AQC_LAN_ADDR_VALID)
1117 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1118 I40E_NONDMA_TO_NONDMA);
1124 * i40e_get_port_mac_addr - get Port MAC address
1125 * @hw: pointer to the HW structure
1126 * @mac_addr: pointer to Port MAC address
1128 * Reads the adapter's Port MAC address
1130 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1132 struct i40e_aqc_mac_address_read_data addrs;
1133 enum i40e_status_code status;
1136 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1140 if (flags & I40E_AQC_PORT_ADDR_VALID)
1141 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1142 I40E_NONDMA_TO_NONDMA);
1144 status = I40E_ERR_INVALID_MAC_ADDR;
1150 * i40e_pre_tx_queue_cfg - pre tx queue configure
1151 * @hw: pointer to the HW structure
1152 * @queue: target pf queue index
1153 * @enable: state change request
1155 * Handles hw requirement to indicate intention to enable
1156 * or disable target queue.
1158 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1160 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1164 if (abs_queue_idx >= 128) {
1165 reg_block = abs_queue_idx / 128;
1166 abs_queue_idx %= 128;
1169 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1170 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1171 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1174 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1176 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1178 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1182 * i40e_get_san_mac_addr - get SAN MAC address
1183 * @hw: pointer to the HW structure
1184 * @mac_addr: pointer to SAN MAC address
1186 * Reads the adapter's SAN MAC address from NVM
1188 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1191 struct i40e_aqc_mac_address_read_data addrs;
1192 enum i40e_status_code status;
1195 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1199 if (flags & I40E_AQC_SAN_ADDR_VALID)
1200 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1201 I40E_NONDMA_TO_NONDMA);
1203 status = I40E_ERR_INVALID_MAC_ADDR;
1209 * i40e_read_pba_string - Reads part number string from EEPROM
1210 * @hw: pointer to hardware structure
1211 * @pba_num: stores the part number string from the EEPROM
1212 * @pba_num_size: part number string buffer length
1214 * Reads the part number string from the EEPROM.
1216 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1219 enum i40e_status_code status = I40E_SUCCESS;
1225 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1226 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1227 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1231 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1232 if (status != I40E_SUCCESS) {
1233 DEBUGOUT("Failed to read PBA Block pointer.\n");
1237 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1238 if (status != I40E_SUCCESS) {
1239 DEBUGOUT("Failed to read PBA Block size.\n");
1243 /* Subtract one to get PBA word count (PBA Size word is included in
1247 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1248 DEBUGOUT("Buffer to small for PBA data.\n");
1249 return I40E_ERR_PARAM;
1252 for (i = 0; i < pba_size; i++) {
1253 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1254 if (status != I40E_SUCCESS) {
1255 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1259 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1260 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1262 pba_num[(pba_size * 2)] = '\0';
1268 * i40e_get_media_type - Gets media type
1269 * @hw: pointer to the hardware structure
1271 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1273 enum i40e_media_type media;
1275 switch (hw->phy.link_info.phy_type) {
1276 case I40E_PHY_TYPE_10GBASE_SR:
1277 case I40E_PHY_TYPE_10GBASE_LR:
1278 case I40E_PHY_TYPE_1000BASE_SX:
1279 case I40E_PHY_TYPE_1000BASE_LX:
1280 case I40E_PHY_TYPE_40GBASE_SR4:
1281 case I40E_PHY_TYPE_40GBASE_LR4:
1282 case I40E_PHY_TYPE_25GBASE_LR:
1283 case I40E_PHY_TYPE_25GBASE_SR:
1284 media = I40E_MEDIA_TYPE_FIBER;
1286 case I40E_PHY_TYPE_100BASE_TX:
1287 case I40E_PHY_TYPE_1000BASE_T:
1288 case I40E_PHY_TYPE_10GBASE_T:
1289 media = I40E_MEDIA_TYPE_BASET;
1291 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1292 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1293 case I40E_PHY_TYPE_10GBASE_CR1:
1294 case I40E_PHY_TYPE_40GBASE_CR4:
1295 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1296 case I40E_PHY_TYPE_40GBASE_AOC:
1297 case I40E_PHY_TYPE_10GBASE_AOC:
1298 case I40E_PHY_TYPE_25GBASE_CR:
1299 media = I40E_MEDIA_TYPE_DA;
1301 case I40E_PHY_TYPE_1000BASE_KX:
1302 case I40E_PHY_TYPE_10GBASE_KX4:
1303 case I40E_PHY_TYPE_10GBASE_KR:
1304 case I40E_PHY_TYPE_40GBASE_KR4:
1305 case I40E_PHY_TYPE_20GBASE_KR2:
1306 case I40E_PHY_TYPE_25GBASE_KR:
1307 media = I40E_MEDIA_TYPE_BACKPLANE;
1309 case I40E_PHY_TYPE_SGMII:
1310 case I40E_PHY_TYPE_XAUI:
1311 case I40E_PHY_TYPE_XFI:
1312 case I40E_PHY_TYPE_XLAUI:
1313 case I40E_PHY_TYPE_XLPPI:
1315 media = I40E_MEDIA_TYPE_UNKNOWN;
1322 #define I40E_PF_RESET_WAIT_COUNT 200
1324 * i40e_pf_reset - Reset the PF
1325 * @hw: pointer to the hardware structure
1327 * Assuming someone else has triggered a global reset,
1328 * assure the global reset is complete and then reset the PF
1330 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1337 /* Poll for Global Reset steady state in case of recent GRST.
1338 * The grst delay value is in 100ms units, and we'll wait a
1339 * couple counts longer to be sure we don't just miss the end.
1341 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1342 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1343 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1345 grst_del = grst_del * 20;
1347 for (cnt = 0; cnt < grst_del; cnt++) {
1348 reg = rd32(hw, I40E_GLGEN_RSTAT);
1349 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1351 i40e_msec_delay(100);
1353 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1354 DEBUGOUT("Global reset polling failed to complete.\n");
1355 return I40E_ERR_RESET_FAILED;
1358 /* Now Wait for the FW to be ready */
1359 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1360 reg = rd32(hw, I40E_GLNVM_ULD);
1361 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1362 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1363 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1364 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1365 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1368 i40e_msec_delay(10);
1370 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1372 DEBUGOUT("wait for FW Reset complete timedout\n");
1373 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1374 return I40E_ERR_RESET_FAILED;
1377 /* If there was a Global Reset in progress when we got here,
1378 * we don't need to do the PF Reset
1381 reg = rd32(hw, I40E_PFGEN_CTRL);
1382 wr32(hw, I40E_PFGEN_CTRL,
1383 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1384 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1385 reg = rd32(hw, I40E_PFGEN_CTRL);
1386 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1390 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1391 DEBUGOUT("PF reset polling failed to complete.\n");
1392 return I40E_ERR_RESET_FAILED;
1396 i40e_clear_pxe_mode(hw);
1399 return I40E_SUCCESS;
1403 * i40e_clear_hw - clear out any left over hw state
1404 * @hw: pointer to the hw struct
1406 * Clear queues and interrupts, typically called at init time,
1407 * but after the capabilities have been found so we know how many
1408 * queues and msix vectors have been allocated.
1410 void i40e_clear_hw(struct i40e_hw *hw)
1412 u32 num_queues, base_queue;
1420 /* get number of interrupts, queues, and vfs */
1421 val = rd32(hw, I40E_GLPCI_CNF2);
1422 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1423 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1424 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1425 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1427 val = rd32(hw, I40E_PFLAN_QALLOC);
1428 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1429 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1430 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1431 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1432 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1433 num_queues = (j - base_queue) + 1;
1437 val = rd32(hw, I40E_PF_VT_PFALLOC);
1438 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1439 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1440 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1441 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1442 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1443 num_vfs = (j - i) + 1;
1447 /* stop all the interrupts */
1448 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1449 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1450 for (i = 0; i < num_pf_int - 2; i++)
1451 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1453 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1454 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1455 wr32(hw, I40E_PFINT_LNKLST0, val);
1456 for (i = 0; i < num_pf_int - 2; i++)
1457 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1458 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1459 for (i = 0; i < num_vfs; i++)
1460 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1461 for (i = 0; i < num_vf_int - 2; i++)
1462 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1464 /* warn the HW of the coming Tx disables */
1465 for (i = 0; i < num_queues; i++) {
1466 u32 abs_queue_idx = base_queue + i;
1469 if (abs_queue_idx >= 128) {
1470 reg_block = abs_queue_idx / 128;
1471 abs_queue_idx %= 128;
1474 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1475 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1476 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1477 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1479 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1481 i40e_usec_delay(400);
1483 /* stop all the queues */
1484 for (i = 0; i < num_queues; i++) {
1485 wr32(hw, I40E_QINT_TQCTL(i), 0);
1486 wr32(hw, I40E_QTX_ENA(i), 0);
1487 wr32(hw, I40E_QINT_RQCTL(i), 0);
1488 wr32(hw, I40E_QRX_ENA(i), 0);
1491 /* short wait for all queue disables to settle */
1492 i40e_usec_delay(50);
1496 * i40e_clear_pxe_mode - clear pxe operations mode
1497 * @hw: pointer to the hw struct
1499 * Make sure all PXE mode settings are cleared, including things
1500 * like descriptor fetch/write-back mode.
1502 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1504 if (i40e_check_asq_alive(hw))
1505 i40e_aq_clear_pxe_mode(hw, NULL);
1509 * i40e_led_is_mine - helper to find matching led
1510 * @hw: pointer to the hw struct
1511 * @idx: index into GPIO registers
1513 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1515 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1520 if (!hw->func_caps.led[idx])
1523 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1524 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1525 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1527 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1528 * if it is not our port then ignore
1530 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1537 #define I40E_COMBINED_ACTIVITY 0xA
1538 #define I40E_FILTER_ACTIVITY 0xE
1539 #define I40E_LINK_ACTIVITY 0xC
1540 #define I40E_MAC_ACTIVITY 0xD
1541 #define I40E_LED0 22
1544 * i40e_led_get - return current on/off mode
1545 * @hw: pointer to the hw struct
1547 * The value returned is the 'mode' field as defined in the
1548 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1549 * values are variations of possible behaviors relating to
1550 * blink, link, and wire.
1552 u32 i40e_led_get(struct i40e_hw *hw)
1554 u32 current_mode = 0;
1558 /* as per the documentation GPIO 22-29 are the LED
1559 * GPIO pins named LED0..LED7
1561 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1562 u32 gpio_val = i40e_led_is_mine(hw, i);
1567 /* ignore gpio LED src mode entries related to the activity
1570 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1571 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1572 switch (current_mode) {
1573 case I40E_COMBINED_ACTIVITY:
1574 case I40E_FILTER_ACTIVITY:
1575 case I40E_MAC_ACTIVITY:
1581 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1582 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1590 * i40e_led_set - set new on/off mode
1591 * @hw: pointer to the hw struct
1592 * @mode: 0=off, 0xf=on (else see manual for mode details)
1593 * @blink: true if the LED should blink when on, false if steady
1595 * if this function is used to turn on the blink it should
1596 * be used to disable the blink when restoring the original state.
1598 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1600 u32 current_mode = 0;
1603 if (mode & 0xfffffff0)
1604 DEBUGOUT1("invalid mode passed in %X\n", mode);
1606 /* as per the documentation GPIO 22-29 are the LED
1607 * GPIO pins named LED0..LED7
1609 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1610 u32 gpio_val = i40e_led_is_mine(hw, i);
1615 /* ignore gpio LED src mode entries related to the activity
1618 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1619 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1620 switch (current_mode) {
1621 case I40E_COMBINED_ACTIVITY:
1622 case I40E_FILTER_ACTIVITY:
1623 case I40E_MAC_ACTIVITY:
1629 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1630 /* this & is a bit of paranoia, but serves as a range check */
1631 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1632 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1634 if (mode == I40E_LINK_ACTIVITY)
1638 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1640 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1642 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1647 /* Admin command wrappers */
1650 * i40e_aq_get_phy_capabilities
1651 * @hw: pointer to the hw struct
1652 * @abilities: structure for PHY capabilities to be filled
1653 * @qualified_modules: report Qualified Modules
1654 * @report_init: report init capabilities (active are default)
1655 * @cmd_details: pointer to command details structure or NULL
1657 * Returns the various PHY abilities supported on the Port.
1659 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1660 bool qualified_modules, bool report_init,
1661 struct i40e_aq_get_phy_abilities_resp *abilities,
1662 struct i40e_asq_cmd_details *cmd_details)
1664 struct i40e_aq_desc desc;
1665 enum i40e_status_code status;
1666 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1669 return I40E_ERR_PARAM;
1671 i40e_fill_default_direct_cmd_desc(&desc,
1672 i40e_aqc_opc_get_phy_abilities);
1674 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1675 if (abilities_size > I40E_AQ_LARGE_BUF)
1676 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1678 if (qualified_modules)
1679 desc.params.external.param0 |=
1680 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1683 desc.params.external.param0 |=
1684 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1686 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1689 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1690 status = I40E_ERR_UNKNOWN_PHY;
1693 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1694 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1701 * i40e_aq_set_phy_config
1702 * @hw: pointer to the hw struct
1703 * @config: structure with PHY configuration to be set
1704 * @cmd_details: pointer to command details structure or NULL
1706 * Set the various PHY configuration parameters
1707 * supported on the Port.One or more of the Set PHY config parameters may be
1708 * ignored in an MFP mode as the PF may not have the privilege to set some
1709 * of the PHY Config parameters. This status will be indicated by the
1712 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1713 struct i40e_aq_set_phy_config *config,
1714 struct i40e_asq_cmd_details *cmd_details)
1716 struct i40e_aq_desc desc;
1717 struct i40e_aq_set_phy_config *cmd =
1718 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1719 enum i40e_status_code status;
1722 return I40E_ERR_PARAM;
1724 i40e_fill_default_direct_cmd_desc(&desc,
1725 i40e_aqc_opc_set_phy_config);
1729 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1736 * @hw: pointer to the hw struct
1738 * Set the requested flow control mode using set_phy_config.
1740 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1741 bool atomic_restart)
1743 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1744 struct i40e_aq_get_phy_abilities_resp abilities;
1745 struct i40e_aq_set_phy_config config;
1746 enum i40e_status_code status;
1747 u8 pause_mask = 0x0;
1753 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1754 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1756 case I40E_FC_RX_PAUSE:
1757 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1759 case I40E_FC_TX_PAUSE:
1760 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1766 /* Get the current phy config */
1767 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1770 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1774 memset(&config, 0, sizeof(config));
1775 /* clear the old pause settings */
1776 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1777 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1778 /* set the new abilities */
1779 config.abilities |= pause_mask;
1780 /* If the abilities have changed, then set the new config */
1781 if (config.abilities != abilities.abilities) {
1782 /* Auto restart link so settings take effect */
1784 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1785 /* Copy over all the old settings */
1786 config.phy_type = abilities.phy_type;
1787 config.phy_type_ext = abilities.phy_type_ext;
1788 config.link_speed = abilities.link_speed;
1789 config.eee_capability = abilities.eee_capability;
1790 config.eeer = abilities.eeer_val;
1791 config.low_power_ctrl = abilities.d3_lpan;
1792 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1793 I40E_AQ_PHY_FEC_CONFIG_MASK;
1794 status = i40e_aq_set_phy_config(hw, &config, NULL);
1797 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1799 /* Update the link info */
1800 status = i40e_update_link_info(hw);
1802 /* Wait a little bit (on 40G cards it sometimes takes a really
1803 * long time for link to come back from the atomic reset)
1806 i40e_msec_delay(1000);
1807 status = i40e_update_link_info(hw);
1810 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1816 * i40e_aq_set_mac_config
1817 * @hw: pointer to the hw struct
1818 * @max_frame_size: Maximum Frame Size to be supported by the port
1819 * @crc_en: Tell HW to append a CRC to outgoing frames
1820 * @pacing: Pacing configurations
1821 * @cmd_details: pointer to command details structure or NULL
1823 * Configure MAC settings for frame size, jumbo frame support and the
1824 * addition of a CRC by the hardware.
1826 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1828 bool crc_en, u16 pacing,
1829 struct i40e_asq_cmd_details *cmd_details)
1831 struct i40e_aq_desc desc;
1832 struct i40e_aq_set_mac_config *cmd =
1833 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1834 enum i40e_status_code status;
1836 if (max_frame_size == 0)
1837 return I40E_ERR_PARAM;
1839 i40e_fill_default_direct_cmd_desc(&desc,
1840 i40e_aqc_opc_set_mac_config);
1842 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1843 cmd->params = ((u8)pacing & 0x0F) << 3;
1845 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1847 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1853 * i40e_aq_clear_pxe_mode
1854 * @hw: pointer to the hw struct
1855 * @cmd_details: pointer to command details structure or NULL
1857 * Tell the firmware that the driver is taking over from PXE
1859 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1860 struct i40e_asq_cmd_details *cmd_details)
1862 enum i40e_status_code status;
1863 struct i40e_aq_desc desc;
1864 struct i40e_aqc_clear_pxe *cmd =
1865 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1867 i40e_fill_default_direct_cmd_desc(&desc,
1868 i40e_aqc_opc_clear_pxe_mode);
1872 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1874 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1880 * i40e_aq_set_link_restart_an
1881 * @hw: pointer to the hw struct
1882 * @enable_link: if true: enable link, if false: disable link
1883 * @cmd_details: pointer to command details structure or NULL
1885 * Sets up the link and restarts the Auto-Negotiation over the link.
1887 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1888 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1890 struct i40e_aq_desc desc;
1891 struct i40e_aqc_set_link_restart_an *cmd =
1892 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1893 enum i40e_status_code status;
1895 i40e_fill_default_direct_cmd_desc(&desc,
1896 i40e_aqc_opc_set_link_restart_an);
1898 cmd->command = I40E_AQ_PHY_RESTART_AN;
1900 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1902 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1904 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1910 * i40e_aq_get_link_info
1911 * @hw: pointer to the hw struct
1912 * @enable_lse: enable/disable LinkStatusEvent reporting
1913 * @link: pointer to link status structure - optional
1914 * @cmd_details: pointer to command details structure or NULL
1916 * Returns the link status of the adapter.
1918 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1919 bool enable_lse, struct i40e_link_status *link,
1920 struct i40e_asq_cmd_details *cmd_details)
1922 struct i40e_aq_desc desc;
1923 struct i40e_aqc_get_link_status *resp =
1924 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1925 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1926 enum i40e_status_code status;
1927 bool tx_pause, rx_pause;
1930 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1933 command_flags = I40E_AQ_LSE_ENABLE;
1935 command_flags = I40E_AQ_LSE_DISABLE;
1936 resp->command_flags = CPU_TO_LE16(command_flags);
1938 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1940 if (status != I40E_SUCCESS)
1941 goto aq_get_link_info_exit;
1943 /* save off old link status information */
1944 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1945 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1947 /* update link status */
1948 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1949 hw->phy.media_type = i40e_get_media_type(hw);
1950 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1951 hw_link_info->link_info = resp->link_info;
1952 hw_link_info->an_info = resp->an_info;
1953 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1954 I40E_AQ_CONFIG_FEC_RS_ENA);
1955 hw_link_info->ext_info = resp->ext_info;
1956 hw_link_info->loopback = resp->loopback;
1957 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1958 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1960 /* update fc info */
1961 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1962 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1963 if (tx_pause & rx_pause)
1964 hw->fc.current_mode = I40E_FC_FULL;
1966 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1968 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1970 hw->fc.current_mode = I40E_FC_NONE;
1972 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1973 hw_link_info->crc_enable = true;
1975 hw_link_info->crc_enable = false;
1977 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1978 hw_link_info->lse_enable = true;
1980 hw_link_info->lse_enable = false;
1982 if ((hw->mac.type == I40E_MAC_XL710) &&
1983 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1984 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1985 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1987 /* save link status information */
1989 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1990 I40E_NONDMA_TO_NONDMA);
1992 /* flag cleared so helper functions don't call AQ again */
1993 hw->phy.get_link_info = false;
1995 aq_get_link_info_exit:
2000 * i40e_aq_set_phy_int_mask
2001 * @hw: pointer to the hw struct
2002 * @mask: interrupt mask to be set
2003 * @cmd_details: pointer to command details structure or NULL
2005 * Set link interrupt mask.
2007 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2009 struct i40e_asq_cmd_details *cmd_details)
2011 struct i40e_aq_desc desc;
2012 struct i40e_aqc_set_phy_int_mask *cmd =
2013 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2014 enum i40e_status_code status;
2016 i40e_fill_default_direct_cmd_desc(&desc,
2017 i40e_aqc_opc_set_phy_int_mask);
2019 cmd->event_mask = CPU_TO_LE16(mask);
2021 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2027 * i40e_aq_get_local_advt_reg
2028 * @hw: pointer to the hw struct
2029 * @advt_reg: local AN advertisement register value
2030 * @cmd_details: pointer to command details structure or NULL
2032 * Get the Local AN advertisement register value.
2034 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2036 struct i40e_asq_cmd_details *cmd_details)
2038 struct i40e_aq_desc desc;
2039 struct i40e_aqc_an_advt_reg *resp =
2040 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2041 enum i40e_status_code status;
2043 i40e_fill_default_direct_cmd_desc(&desc,
2044 i40e_aqc_opc_get_local_advt_reg);
2046 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2048 if (status != I40E_SUCCESS)
2049 goto aq_get_local_advt_reg_exit;
2051 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2052 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2054 aq_get_local_advt_reg_exit:
2059 * i40e_aq_set_local_advt_reg
2060 * @hw: pointer to the hw struct
2061 * @advt_reg: local AN advertisement register value
2062 * @cmd_details: pointer to command details structure or NULL
2064 * Get the Local AN advertisement register value.
2066 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2068 struct i40e_asq_cmd_details *cmd_details)
2070 struct i40e_aq_desc desc;
2071 struct i40e_aqc_an_advt_reg *cmd =
2072 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2073 enum i40e_status_code status;
2075 i40e_fill_default_direct_cmd_desc(&desc,
2076 i40e_aqc_opc_get_local_advt_reg);
2078 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2079 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2081 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2087 * i40e_aq_get_partner_advt
2088 * @hw: pointer to the hw struct
2089 * @advt_reg: AN partner advertisement register value
2090 * @cmd_details: pointer to command details structure or NULL
2092 * Get the link partner AN advertisement register value.
2094 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2096 struct i40e_asq_cmd_details *cmd_details)
2098 struct i40e_aq_desc desc;
2099 struct i40e_aqc_an_advt_reg *resp =
2100 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2101 enum i40e_status_code status;
2103 i40e_fill_default_direct_cmd_desc(&desc,
2104 i40e_aqc_opc_get_partner_advt);
2106 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2108 if (status != I40E_SUCCESS)
2109 goto aq_get_partner_advt_exit;
2111 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2112 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2114 aq_get_partner_advt_exit:
2119 * i40e_aq_set_lb_modes
2120 * @hw: pointer to the hw struct
2121 * @lb_modes: loopback mode to be set
2122 * @cmd_details: pointer to command details structure or NULL
2124 * Sets loopback modes.
2126 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2128 struct i40e_asq_cmd_details *cmd_details)
2130 struct i40e_aq_desc desc;
2131 struct i40e_aqc_set_lb_mode *cmd =
2132 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2133 enum i40e_status_code status;
2135 i40e_fill_default_direct_cmd_desc(&desc,
2136 i40e_aqc_opc_set_lb_modes);
2138 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2140 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2146 * i40e_aq_set_phy_debug
2147 * @hw: pointer to the hw struct
2148 * @cmd_flags: debug command flags
2149 * @cmd_details: pointer to command details structure or NULL
2151 * Reset the external PHY.
2153 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2154 struct i40e_asq_cmd_details *cmd_details)
2156 struct i40e_aq_desc desc;
2157 struct i40e_aqc_set_phy_debug *cmd =
2158 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2159 enum i40e_status_code status;
2161 i40e_fill_default_direct_cmd_desc(&desc,
2162 i40e_aqc_opc_set_phy_debug);
2164 cmd->command_flags = cmd_flags;
2166 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2173 * @hw: pointer to the hw struct
2174 * @vsi_ctx: pointer to a vsi context struct
2175 * @cmd_details: pointer to command details structure or NULL
2177 * Add a VSI context to the hardware.
2179 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2180 struct i40e_vsi_context *vsi_ctx,
2181 struct i40e_asq_cmd_details *cmd_details)
2183 struct i40e_aq_desc desc;
2184 struct i40e_aqc_add_get_update_vsi *cmd =
2185 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2186 struct i40e_aqc_add_get_update_vsi_completion *resp =
2187 (struct i40e_aqc_add_get_update_vsi_completion *)
2189 enum i40e_status_code status;
2191 i40e_fill_default_direct_cmd_desc(&desc,
2192 i40e_aqc_opc_add_vsi);
2194 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2195 cmd->connection_type = vsi_ctx->connection_type;
2196 cmd->vf_id = vsi_ctx->vf_num;
2197 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2199 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2201 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2202 sizeof(vsi_ctx->info), cmd_details);
2204 if (status != I40E_SUCCESS)
2205 goto aq_add_vsi_exit;
2207 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2208 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2209 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2210 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2217 * i40e_aq_set_default_vsi
2218 * @hw: pointer to the hw struct
2220 * @cmd_details: pointer to command details structure or NULL
2222 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2224 struct i40e_asq_cmd_details *cmd_details)
2226 struct i40e_aq_desc desc;
2227 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2228 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2230 enum i40e_status_code status;
2232 i40e_fill_default_direct_cmd_desc(&desc,
2233 i40e_aqc_opc_set_vsi_promiscuous_modes);
2235 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2236 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2237 cmd->seid = CPU_TO_LE16(seid);
2239 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2245 * i40e_aq_clear_default_vsi
2246 * @hw: pointer to the hw struct
2248 * @cmd_details: pointer to command details structure or NULL
2250 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2252 struct i40e_asq_cmd_details *cmd_details)
2254 struct i40e_aq_desc desc;
2255 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2256 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2258 enum i40e_status_code status;
2260 i40e_fill_default_direct_cmd_desc(&desc,
2261 i40e_aqc_opc_set_vsi_promiscuous_modes);
2263 cmd->promiscuous_flags = CPU_TO_LE16(0);
2264 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2265 cmd->seid = CPU_TO_LE16(seid);
2267 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2273 * i40e_aq_set_vsi_unicast_promiscuous
2274 * @hw: pointer to the hw struct
2276 * @set: set unicast promiscuous enable/disable
2277 * @cmd_details: pointer to command details structure or NULL
2278 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2280 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2282 struct i40e_asq_cmd_details *cmd_details,
2283 bool rx_only_promisc)
2285 struct i40e_aq_desc desc;
2286 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288 enum i40e_status_code status;
2291 i40e_fill_default_direct_cmd_desc(&desc,
2292 i40e_aqc_opc_set_vsi_promiscuous_modes);
2295 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2296 if (rx_only_promisc &&
2297 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2298 (hw->aq.api_maj_ver > 1)))
2299 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2302 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2304 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2305 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2306 (hw->aq.api_maj_ver > 1))
2307 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2309 cmd->seid = CPU_TO_LE16(seid);
2310 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2316 * i40e_aq_set_vsi_multicast_promiscuous
2317 * @hw: pointer to the hw struct
2319 * @set: set multicast promiscuous enable/disable
2320 * @cmd_details: pointer to command details structure or NULL
2322 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2323 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2325 struct i40e_aq_desc desc;
2326 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2327 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2328 enum i40e_status_code status;
2331 i40e_fill_default_direct_cmd_desc(&desc,
2332 i40e_aqc_opc_set_vsi_promiscuous_modes);
2335 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2337 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2339 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2341 cmd->seid = CPU_TO_LE16(seid);
2342 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2348 * i40e_aq_set_vsi_full_promiscuous
2349 * @hw: pointer to the hw struct
2351 * @set: set promiscuous enable/disable
2352 * @cmd_details: pointer to command details structure or NULL
2354 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2356 struct i40e_asq_cmd_details *cmd_details)
2358 struct i40e_aq_desc desc;
2359 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2360 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2361 enum i40e_status_code status;
2364 i40e_fill_default_direct_cmd_desc(&desc,
2365 i40e_aqc_opc_set_vsi_promiscuous_modes);
2368 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2369 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2370 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2372 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2374 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2375 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2376 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2378 cmd->seid = CPU_TO_LE16(seid);
2379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2385 * i40e_aq_set_vsi_mc_promisc_on_vlan
2386 * @hw: pointer to the hw struct
2388 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2389 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2390 * @cmd_details: pointer to command details structure or NULL
2392 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2393 u16 seid, bool enable, u16 vid,
2394 struct i40e_asq_cmd_details *cmd_details)
2396 struct i40e_aq_desc desc;
2397 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2398 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2399 enum i40e_status_code status;
2402 i40e_fill_default_direct_cmd_desc(&desc,
2403 i40e_aqc_opc_set_vsi_promiscuous_modes);
2406 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2408 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2409 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2410 cmd->seid = CPU_TO_LE16(seid);
2411 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2413 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2419 * i40e_aq_set_vsi_uc_promisc_on_vlan
2420 * @hw: pointer to the hw struct
2422 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2423 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2424 * @cmd_details: pointer to command details structure or NULL
2426 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2427 u16 seid, bool enable, u16 vid,
2428 struct i40e_asq_cmd_details *cmd_details)
2430 struct i40e_aq_desc desc;
2431 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2432 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2433 enum i40e_status_code status;
2436 i40e_fill_default_direct_cmd_desc(&desc,
2437 i40e_aqc_opc_set_vsi_promiscuous_modes);
2440 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2442 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2443 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2444 cmd->seid = CPU_TO_LE16(seid);
2445 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2447 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2453 * i40e_aq_set_vsi_bc_promisc_on_vlan
2454 * @hw: pointer to the hw struct
2456 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2457 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2458 * @cmd_details: pointer to command details structure or NULL
2460 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2461 u16 seid, bool enable, u16 vid,
2462 struct i40e_asq_cmd_details *cmd_details)
2464 struct i40e_aq_desc desc;
2465 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2466 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2467 enum i40e_status_code status;
2470 i40e_fill_default_direct_cmd_desc(&desc,
2471 i40e_aqc_opc_set_vsi_promiscuous_modes);
2474 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2476 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2477 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2478 cmd->seid = CPU_TO_LE16(seid);
2479 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2481 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2487 * i40e_aq_set_vsi_broadcast
2488 * @hw: pointer to the hw struct
2490 * @set_filter: true to set filter, false to clear filter
2491 * @cmd_details: pointer to command details structure or NULL
2493 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2495 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2496 u16 seid, bool set_filter,
2497 struct i40e_asq_cmd_details *cmd_details)
2499 struct i40e_aq_desc desc;
2500 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2501 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2502 enum i40e_status_code status;
2504 i40e_fill_default_direct_cmd_desc(&desc,
2505 i40e_aqc_opc_set_vsi_promiscuous_modes);
2508 cmd->promiscuous_flags
2509 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2511 cmd->promiscuous_flags
2512 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2514 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2515 cmd->seid = CPU_TO_LE16(seid);
2516 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2522 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2523 * @hw: pointer to the hw struct
2525 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2526 * @cmd_details: pointer to command details structure or NULL
2528 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2529 u16 seid, bool enable,
2530 struct i40e_asq_cmd_details *cmd_details)
2532 struct i40e_aq_desc desc;
2533 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2534 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2535 enum i40e_status_code status;
2538 i40e_fill_default_direct_cmd_desc(&desc,
2539 i40e_aqc_opc_set_vsi_promiscuous_modes);
2541 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2543 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2544 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2545 cmd->seid = CPU_TO_LE16(seid);
2547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2553 * i40e_get_vsi_params - get VSI configuration info
2554 * @hw: pointer to the hw struct
2555 * @vsi_ctx: pointer to a vsi context struct
2556 * @cmd_details: pointer to command details structure or NULL
2558 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2559 struct i40e_vsi_context *vsi_ctx,
2560 struct i40e_asq_cmd_details *cmd_details)
2562 struct i40e_aq_desc desc;
2563 struct i40e_aqc_add_get_update_vsi *cmd =
2564 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2565 struct i40e_aqc_add_get_update_vsi_completion *resp =
2566 (struct i40e_aqc_add_get_update_vsi_completion *)
2568 enum i40e_status_code status;
2570 UNREFERENCED_1PARAMETER(cmd_details);
2571 i40e_fill_default_direct_cmd_desc(&desc,
2572 i40e_aqc_opc_get_vsi_parameters);
2574 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2576 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2578 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2579 sizeof(vsi_ctx->info), NULL);
2581 if (status != I40E_SUCCESS)
2582 goto aq_get_vsi_params_exit;
2584 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2585 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2586 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2587 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2589 aq_get_vsi_params_exit:
2594 * i40e_aq_update_vsi_params
2595 * @hw: pointer to the hw struct
2596 * @vsi_ctx: pointer to a vsi context struct
2597 * @cmd_details: pointer to command details structure or NULL
2599 * Update a VSI context.
2601 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2602 struct i40e_vsi_context *vsi_ctx,
2603 struct i40e_asq_cmd_details *cmd_details)
2605 struct i40e_aq_desc desc;
2606 struct i40e_aqc_add_get_update_vsi *cmd =
2607 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2608 struct i40e_aqc_add_get_update_vsi_completion *resp =
2609 (struct i40e_aqc_add_get_update_vsi_completion *)
2611 enum i40e_status_code status;
2613 i40e_fill_default_direct_cmd_desc(&desc,
2614 i40e_aqc_opc_update_vsi_parameters);
2615 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2617 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2619 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2620 sizeof(vsi_ctx->info), cmd_details);
2622 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2623 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2629 * i40e_aq_get_switch_config
2630 * @hw: pointer to the hardware structure
2631 * @buf: pointer to the result buffer
2632 * @buf_size: length of input buffer
2633 * @start_seid: seid to start for the report, 0 == beginning
2634 * @cmd_details: pointer to command details structure or NULL
2636 * Fill the buf with switch configuration returned from AdminQ command
2638 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2639 struct i40e_aqc_get_switch_config_resp *buf,
2640 u16 buf_size, u16 *start_seid,
2641 struct i40e_asq_cmd_details *cmd_details)
2643 struct i40e_aq_desc desc;
2644 struct i40e_aqc_switch_seid *scfg =
2645 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2646 enum i40e_status_code status;
2648 i40e_fill_default_direct_cmd_desc(&desc,
2649 i40e_aqc_opc_get_switch_config);
2650 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2651 if (buf_size > I40E_AQ_LARGE_BUF)
2652 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2653 scfg->seid = CPU_TO_LE16(*start_seid);
2655 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2656 *start_seid = LE16_TO_CPU(scfg->seid);
2662 * i40e_aq_set_switch_config
2663 * @hw: pointer to the hardware structure
2664 * @flags: bit flag values to set
2665 * @valid_flags: which bit flags to set
2666 * @cmd_details: pointer to command details structure or NULL
2668 * Set switch configuration bits
2670 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2671 u16 flags, u16 valid_flags,
2672 struct i40e_asq_cmd_details *cmd_details)
2674 struct i40e_aq_desc desc;
2675 struct i40e_aqc_set_switch_config *scfg =
2676 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2677 enum i40e_status_code status;
2679 i40e_fill_default_direct_cmd_desc(&desc,
2680 i40e_aqc_opc_set_switch_config);
2681 scfg->flags = CPU_TO_LE16(flags);
2682 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2684 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2690 * i40e_aq_get_firmware_version
2691 * @hw: pointer to the hw struct
2692 * @fw_major_version: firmware major version
2693 * @fw_minor_version: firmware minor version
2694 * @fw_build: firmware build number
2695 * @api_major_version: major queue version
2696 * @api_minor_version: minor queue version
2697 * @cmd_details: pointer to command details structure or NULL
2699 * Get the firmware version from the admin queue commands
2701 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2702 u16 *fw_major_version, u16 *fw_minor_version,
2704 u16 *api_major_version, u16 *api_minor_version,
2705 struct i40e_asq_cmd_details *cmd_details)
2707 struct i40e_aq_desc desc;
2708 struct i40e_aqc_get_version *resp =
2709 (struct i40e_aqc_get_version *)&desc.params.raw;
2710 enum i40e_status_code status;
2712 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2714 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2716 if (status == I40E_SUCCESS) {
2717 if (fw_major_version != NULL)
2718 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2719 if (fw_minor_version != NULL)
2720 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2721 if (fw_build != NULL)
2722 *fw_build = LE32_TO_CPU(resp->fw_build);
2723 if (api_major_version != NULL)
2724 *api_major_version = LE16_TO_CPU(resp->api_major);
2725 if (api_minor_version != NULL)
2726 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2728 /* A workaround to fix the API version in SW */
2729 if (api_major_version && api_minor_version &&
2730 fw_major_version && fw_minor_version &&
2731 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2732 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2733 (*fw_major_version > 4)))
2734 *api_minor_version = 2;
2741 * i40e_aq_send_driver_version
2742 * @hw: pointer to the hw struct
2743 * @dv: driver's major, minor version
2744 * @cmd_details: pointer to command details structure or NULL
2746 * Send the driver version to the firmware
2748 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2749 struct i40e_driver_version *dv,
2750 struct i40e_asq_cmd_details *cmd_details)
2752 struct i40e_aq_desc desc;
2753 struct i40e_aqc_driver_version *cmd =
2754 (struct i40e_aqc_driver_version *)&desc.params.raw;
2755 enum i40e_status_code status;
2759 return I40E_ERR_PARAM;
2761 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2763 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2764 cmd->driver_major_ver = dv->major_version;
2765 cmd->driver_minor_ver = dv->minor_version;
2766 cmd->driver_build_ver = dv->build_version;
2767 cmd->driver_subbuild_ver = dv->subbuild_version;
2770 while (len < sizeof(dv->driver_string) &&
2771 (dv->driver_string[len] < 0x80) &&
2772 dv->driver_string[len])
2774 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2781 * i40e_get_link_status - get status of the HW network link
2782 * @hw: pointer to the hw struct
2783 * @link_up: pointer to bool (true/false = linkup/linkdown)
2785 * Variable link_up true if link is up, false if link is down.
2786 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2788 * Side effect: LinkStatusEvent reporting becomes enabled
2790 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2792 enum i40e_status_code status = I40E_SUCCESS;
2794 if (hw->phy.get_link_info) {
2795 status = i40e_update_link_info(hw);
2797 if (status != I40E_SUCCESS)
2798 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2802 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2808 * i40e_updatelink_status - update status of the HW network link
2809 * @hw: pointer to the hw struct
2811 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2813 struct i40e_aq_get_phy_abilities_resp abilities;
2814 enum i40e_status_code status = I40E_SUCCESS;
2816 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2820 /* extra checking needed to ensure link info to user is timely */
2821 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2822 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2823 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2824 status = i40e_aq_get_phy_capabilities(hw, false, false,
2829 hw->phy.link_info.req_fec_info =
2830 abilities.fec_cfg_curr_mod_ext_info &
2831 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2833 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2834 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2841 * i40e_get_link_speed
2842 * @hw: pointer to the hw struct
2844 * Returns the link speed of the adapter.
2846 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2848 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2849 enum i40e_status_code status = I40E_SUCCESS;
2851 if (hw->phy.get_link_info) {
2852 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2854 if (status != I40E_SUCCESS)
2855 goto i40e_link_speed_exit;
2858 speed = hw->phy.link_info.link_speed;
2860 i40e_link_speed_exit:
2865 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2866 * @hw: pointer to the hw struct
2867 * @uplink_seid: the MAC or other gizmo SEID
2868 * @downlink_seid: the VSI SEID
2869 * @enabled_tc: bitmap of TCs to be enabled
2870 * @default_port: true for default port VSI, false for control port
2871 * @veb_seid: pointer to where to put the resulting VEB SEID
2872 * @enable_stats: true to turn on VEB stats
2873 * @cmd_details: pointer to command details structure or NULL
2875 * This asks the FW to add a VEB between the uplink and downlink
2876 * elements. If the uplink SEID is 0, this will be a floating VEB.
2878 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2879 u16 downlink_seid, u8 enabled_tc,
2880 bool default_port, u16 *veb_seid,
2882 struct i40e_asq_cmd_details *cmd_details)
2884 struct i40e_aq_desc desc;
2885 struct i40e_aqc_add_veb *cmd =
2886 (struct i40e_aqc_add_veb *)&desc.params.raw;
2887 struct i40e_aqc_add_veb_completion *resp =
2888 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2889 enum i40e_status_code status;
2892 /* SEIDs need to either both be set or both be 0 for floating VEB */
2893 if (!!uplink_seid != !!downlink_seid)
2894 return I40E_ERR_PARAM;
2896 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2898 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2899 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2900 cmd->enable_tcs = enabled_tc;
2902 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2904 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2906 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2908 /* reverse logic here: set the bitflag to disable the stats */
2910 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2912 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2914 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2916 if (!status && veb_seid)
2917 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2923 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2924 * @hw: pointer to the hw struct
2925 * @veb_seid: the SEID of the VEB to query
2926 * @switch_id: the uplink switch id
2927 * @floating: set to true if the VEB is floating
2928 * @statistic_index: index of the stats counter block for this VEB
2929 * @vebs_used: number of VEB's used by function
2930 * @vebs_free: total VEB's not reserved by any function
2931 * @cmd_details: pointer to command details structure or NULL
2933 * This retrieves the parameters for a particular VEB, specified by
2934 * uplink_seid, and returns them to the caller.
2936 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2937 u16 veb_seid, u16 *switch_id,
2938 bool *floating, u16 *statistic_index,
2939 u16 *vebs_used, u16 *vebs_free,
2940 struct i40e_asq_cmd_details *cmd_details)
2942 struct i40e_aq_desc desc;
2943 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2944 (struct i40e_aqc_get_veb_parameters_completion *)
2946 enum i40e_status_code status;
2949 return I40E_ERR_PARAM;
2951 i40e_fill_default_direct_cmd_desc(&desc,
2952 i40e_aqc_opc_get_veb_parameters);
2953 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2955 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2960 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2961 if (statistic_index)
2962 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2964 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2966 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2968 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2970 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2981 * i40e_aq_add_macvlan
2982 * @hw: pointer to the hw struct
2983 * @seid: VSI for the mac address
2984 * @mv_list: list of macvlans to be added
2985 * @count: length of the list
2986 * @cmd_details: pointer to command details structure or NULL
2988 * Add MAC/VLAN addresses to the HW filtering
2990 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2991 struct i40e_aqc_add_macvlan_element_data *mv_list,
2992 u16 count, struct i40e_asq_cmd_details *cmd_details)
2994 struct i40e_aq_desc desc;
2995 struct i40e_aqc_macvlan *cmd =
2996 (struct i40e_aqc_macvlan *)&desc.params.raw;
2997 enum i40e_status_code status;
3001 if (count == 0 || !mv_list || !hw)
3002 return I40E_ERR_PARAM;
3004 buf_size = count * sizeof(*mv_list);
3006 /* prep the rest of the request */
3007 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3008 cmd->num_addresses = CPU_TO_LE16(count);
3009 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3013 for (i = 0; i < count; i++)
3014 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3016 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3018 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3019 if (buf_size > I40E_AQ_LARGE_BUF)
3020 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3022 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3029 * i40e_aq_remove_macvlan
3030 * @hw: pointer to the hw struct
3031 * @seid: VSI for the mac address
3032 * @mv_list: list of macvlans to be removed
3033 * @count: length of the list
3034 * @cmd_details: pointer to command details structure or NULL
3036 * Remove MAC/VLAN addresses from the HW filtering
3038 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3039 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3040 u16 count, struct i40e_asq_cmd_details *cmd_details)
3042 struct i40e_aq_desc desc;
3043 struct i40e_aqc_macvlan *cmd =
3044 (struct i40e_aqc_macvlan *)&desc.params.raw;
3045 enum i40e_status_code status;
3048 if (count == 0 || !mv_list || !hw)
3049 return I40E_ERR_PARAM;
3051 buf_size = count * sizeof(*mv_list);
3053 /* prep the rest of the request */
3054 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3055 cmd->num_addresses = CPU_TO_LE16(count);
3056 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3060 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3061 if (buf_size > I40E_AQ_LARGE_BUF)
3062 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3064 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3071 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3072 * @hw: pointer to the hw struct
3073 * @opcode: AQ opcode for add or delete mirror rule
3074 * @sw_seid: Switch SEID (to which rule refers)
3075 * @rule_type: Rule Type (ingress/egress/VLAN)
3076 * @id: Destination VSI SEID or Rule ID
3077 * @count: length of the list
3078 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3079 * @cmd_details: pointer to command details structure or NULL
3080 * @rule_id: Rule ID returned from FW
3081 * @rule_used: Number of rules used in internal switch
3082 * @rule_free: Number of rules free in internal switch
3084 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3085 * VEBs/VEPA elements only
3087 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3088 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3089 u16 count, __le16 *mr_list,
3090 struct i40e_asq_cmd_details *cmd_details,
3091 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3093 struct i40e_aq_desc desc;
3094 struct i40e_aqc_add_delete_mirror_rule *cmd =
3095 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3096 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3097 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3098 enum i40e_status_code status;
3101 buf_size = count * sizeof(*mr_list);
3103 /* prep the rest of the request */
3104 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3105 cmd->seid = CPU_TO_LE16(sw_seid);
3106 cmd->rule_type = CPU_TO_LE16(rule_type &
3107 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3108 cmd->num_entries = CPU_TO_LE16(count);
3109 /* Dest VSI for add, rule_id for delete */
3110 cmd->destination = CPU_TO_LE16(id);
3112 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3114 if (buf_size > I40E_AQ_LARGE_BUF)
3115 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3118 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3120 if (status == I40E_SUCCESS ||
3121 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3123 *rule_id = LE16_TO_CPU(resp->rule_id);
3125 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3127 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3133 * i40e_aq_add_mirrorrule - add a mirror rule
3134 * @hw: pointer to the hw struct
3135 * @sw_seid: Switch SEID (to which rule refers)
3136 * @rule_type: Rule Type (ingress/egress/VLAN)
3137 * @dest_vsi: SEID of VSI to which packets will be mirrored
3138 * @count: length of the list
3139 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3140 * @cmd_details: pointer to command details structure or NULL
3141 * @rule_id: Rule ID returned from FW
3142 * @rule_used: Number of rules used in internal switch
3143 * @rule_free: Number of rules free in internal switch
3145 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3147 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3148 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3149 struct i40e_asq_cmd_details *cmd_details,
3150 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3152 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3153 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3154 if (count == 0 || !mr_list)
3155 return I40E_ERR_PARAM;
3158 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3159 rule_type, dest_vsi, count, mr_list,
3160 cmd_details, rule_id, rules_used, rules_free);
3164 * i40e_aq_delete_mirrorrule - delete a mirror rule
3165 * @hw: pointer to the hw struct
3166 * @sw_seid: Switch SEID (to which rule refers)
3167 * @rule_type: Rule Type (ingress/egress/VLAN)
3168 * @count: length of the list
3169 * @rule_id: Rule ID that is returned in the receive desc as part of
3171 * @mr_list: list of mirrored VLAN IDs to be removed
3172 * @cmd_details: pointer to command details structure or NULL
3173 * @rule_used: Number of rules used in internal switch
3174 * @rule_free: Number of rules free in internal switch
3176 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3178 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3179 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3180 struct i40e_asq_cmd_details *cmd_details,
3181 u16 *rules_used, u16 *rules_free)
3183 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3184 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3185 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3186 * mirroring. For other rule_type, count and rule_type should
3189 if (count == 0 || !mr_list)
3190 return I40E_ERR_PARAM;
3193 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3194 rule_type, rule_id, count, mr_list,
3195 cmd_details, NULL, rules_used, rules_free);
3199 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3200 * @hw: pointer to the hw struct
3201 * @seid: VSI for the vlan filters
3202 * @v_list: list of vlan filters to be added
3203 * @count: length of the list
3204 * @cmd_details: pointer to command details structure or NULL
3206 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3207 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3208 u8 count, struct i40e_asq_cmd_details *cmd_details)
3210 struct i40e_aq_desc desc;
3211 struct i40e_aqc_macvlan *cmd =
3212 (struct i40e_aqc_macvlan *)&desc.params.raw;
3213 enum i40e_status_code status;
3216 if (count == 0 || !v_list || !hw)
3217 return I40E_ERR_PARAM;
3219 buf_size = count * sizeof(*v_list);
3221 /* prep the rest of the request */
3222 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3223 cmd->num_addresses = CPU_TO_LE16(count);
3224 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3228 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3229 if (buf_size > I40E_AQ_LARGE_BUF)
3230 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3232 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3239 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3240 * @hw: pointer to the hw struct
3241 * @seid: VSI for the vlan filters
3242 * @v_list: list of macvlans to be removed
3243 * @count: length of the list
3244 * @cmd_details: pointer to command details structure or NULL
3246 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3247 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3248 u8 count, struct i40e_asq_cmd_details *cmd_details)
3250 struct i40e_aq_desc desc;
3251 struct i40e_aqc_macvlan *cmd =
3252 (struct i40e_aqc_macvlan *)&desc.params.raw;
3253 enum i40e_status_code status;
3256 if (count == 0 || !v_list || !hw)
3257 return I40E_ERR_PARAM;
3259 buf_size = count * sizeof(*v_list);
3261 /* prep the rest of the request */
3262 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3263 cmd->num_addresses = CPU_TO_LE16(count);
3264 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3268 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3269 if (buf_size > I40E_AQ_LARGE_BUF)
3270 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3272 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3279 * i40e_aq_send_msg_to_vf
3280 * @hw: pointer to the hardware structure
3281 * @vfid: vf id to send msg
3282 * @v_opcode: opcodes for VF-PF communication
3283 * @v_retval: return error code
3284 * @msg: pointer to the msg buffer
3285 * @msglen: msg length
3286 * @cmd_details: pointer to command details
3290 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3291 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3292 struct i40e_asq_cmd_details *cmd_details)
3294 struct i40e_aq_desc desc;
3295 struct i40e_aqc_pf_vf_message *cmd =
3296 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3297 enum i40e_status_code status;
3299 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3300 cmd->id = CPU_TO_LE32(vfid);
3301 desc.cookie_high = CPU_TO_LE32(v_opcode);
3302 desc.cookie_low = CPU_TO_LE32(v_retval);
3303 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3305 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3307 if (msglen > I40E_AQ_LARGE_BUF)
3308 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3309 desc.datalen = CPU_TO_LE16(msglen);
3311 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3317 * i40e_aq_debug_read_register
3318 * @hw: pointer to the hw struct
3319 * @reg_addr: register address
3320 * @reg_val: register value
3321 * @cmd_details: pointer to command details structure or NULL
3323 * Read the register using the admin queue commands
3325 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3326 u32 reg_addr, u64 *reg_val,
3327 struct i40e_asq_cmd_details *cmd_details)
3329 struct i40e_aq_desc desc;
3330 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3331 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3332 enum i40e_status_code status;
3334 if (reg_val == NULL)
3335 return I40E_ERR_PARAM;
3337 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3339 cmd_resp->address = CPU_TO_LE32(reg_addr);
3341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3343 if (status == I40E_SUCCESS) {
3344 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3345 (u64)LE32_TO_CPU(cmd_resp->value_low);
3352 * i40e_aq_debug_write_register
3353 * @hw: pointer to the hw struct
3354 * @reg_addr: register address
3355 * @reg_val: register value
3356 * @cmd_details: pointer to command details structure or NULL
3358 * Write to a register using the admin queue commands
3360 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3361 u32 reg_addr, u64 reg_val,
3362 struct i40e_asq_cmd_details *cmd_details)
3364 struct i40e_aq_desc desc;
3365 struct i40e_aqc_debug_reg_read_write *cmd =
3366 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3367 enum i40e_status_code status;
3369 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3371 cmd->address = CPU_TO_LE32(reg_addr);
3372 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3373 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3375 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3381 * i40e_aq_request_resource
3382 * @hw: pointer to the hw struct
3383 * @resource: resource id
3384 * @access: access type
3385 * @sdp_number: resource number
3386 * @timeout: the maximum time in ms that the driver may hold the resource
3387 * @cmd_details: pointer to command details structure or NULL
3389 * requests common resource using the admin queue commands
3391 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3392 enum i40e_aq_resources_ids resource,
3393 enum i40e_aq_resource_access_type access,
3394 u8 sdp_number, u64 *timeout,
3395 struct i40e_asq_cmd_details *cmd_details)
3397 struct i40e_aq_desc desc;
3398 struct i40e_aqc_request_resource *cmd_resp =
3399 (struct i40e_aqc_request_resource *)&desc.params.raw;
3400 enum i40e_status_code status;
3402 DEBUGFUNC("i40e_aq_request_resource");
3404 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3406 cmd_resp->resource_id = CPU_TO_LE16(resource);
3407 cmd_resp->access_type = CPU_TO_LE16(access);
3408 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3410 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3411 /* The completion specifies the maximum time in ms that the driver
3412 * may hold the resource in the Timeout field.
3413 * If the resource is held by someone else, the command completes with
3414 * busy return value and the timeout field indicates the maximum time
3415 * the current owner of the resource has to free it.
3417 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3418 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3424 * i40e_aq_release_resource
3425 * @hw: pointer to the hw struct
3426 * @resource: resource id
3427 * @sdp_number: resource number
3428 * @cmd_details: pointer to command details structure or NULL
3430 * release common resource using the admin queue commands
3432 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3433 enum i40e_aq_resources_ids resource,
3435 struct i40e_asq_cmd_details *cmd_details)
3437 struct i40e_aq_desc desc;
3438 struct i40e_aqc_request_resource *cmd =
3439 (struct i40e_aqc_request_resource *)&desc.params.raw;
3440 enum i40e_status_code status;
3442 DEBUGFUNC("i40e_aq_release_resource");
3444 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3446 cmd->resource_id = CPU_TO_LE16(resource);
3447 cmd->resource_number = CPU_TO_LE32(sdp_number);
3449 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3456 * @hw: pointer to the hw struct
3457 * @module_pointer: module pointer location in words from the NVM beginning
3458 * @offset: byte offset from the module beginning
3459 * @length: length of the section to be read (in bytes from the offset)
3460 * @data: command buffer (size [bytes] = length)
3461 * @last_command: tells if this is the last command in a series
3462 * @cmd_details: pointer to command details structure or NULL
3464 * Read the NVM using the admin queue commands
3466 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3467 u32 offset, u16 length, void *data,
3469 struct i40e_asq_cmd_details *cmd_details)
3471 struct i40e_aq_desc desc;
3472 struct i40e_aqc_nvm_update *cmd =
3473 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3474 enum i40e_status_code status;
3476 DEBUGFUNC("i40e_aq_read_nvm");
3478 /* In offset the highest byte must be zeroed. */
3479 if (offset & 0xFF000000) {
3480 status = I40E_ERR_PARAM;
3481 goto i40e_aq_read_nvm_exit;
3484 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3486 /* If this is the last command in a series, set the proper flag. */
3488 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3489 cmd->module_pointer = module_pointer;
3490 cmd->offset = CPU_TO_LE32(offset);
3491 cmd->length = CPU_TO_LE16(length);
3493 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3494 if (length > I40E_AQ_LARGE_BUF)
3495 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3497 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3499 i40e_aq_read_nvm_exit:
3504 * i40e_aq_read_nvm_config - read an nvm config block
3505 * @hw: pointer to the hw struct
3506 * @cmd_flags: NVM access admin command bits
3507 * @field_id: field or feature id
3508 * @data: buffer for result
3509 * @buf_size: buffer size
3510 * @element_count: pointer to count of elements read by FW
3511 * @cmd_details: pointer to command details structure or NULL
3513 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3514 u8 cmd_flags, u32 field_id, void *data,
3515 u16 buf_size, u16 *element_count,
3516 struct i40e_asq_cmd_details *cmd_details)
3518 struct i40e_aq_desc desc;
3519 struct i40e_aqc_nvm_config_read *cmd =
3520 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3521 enum i40e_status_code status;
3523 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3524 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3525 if (buf_size > I40E_AQ_LARGE_BUF)
3526 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3528 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3529 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3530 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3531 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3533 cmd->element_id_msw = 0;
3535 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3537 if (!status && element_count)
3538 *element_count = LE16_TO_CPU(cmd->element_count);
3544 * i40e_aq_write_nvm_config - write an nvm config block
3545 * @hw: pointer to the hw struct
3546 * @cmd_flags: NVM access admin command bits
3547 * @data: buffer for result
3548 * @buf_size: buffer size
3549 * @element_count: count of elements to be written
3550 * @cmd_details: pointer to command details structure or NULL
3552 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3553 u8 cmd_flags, void *data, u16 buf_size,
3555 struct i40e_asq_cmd_details *cmd_details)
3557 struct i40e_aq_desc desc;
3558 struct i40e_aqc_nvm_config_write *cmd =
3559 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3560 enum i40e_status_code status;
3562 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3563 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3564 if (buf_size > I40E_AQ_LARGE_BUF)
3565 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3567 cmd->element_count = CPU_TO_LE16(element_count);
3568 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3569 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3575 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3576 * @hw: pointer to the hw struct
3577 * @cmd_details: pointer to command details structure or NULL
3579 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3580 void *buff, u16 buff_size,
3581 struct i40e_asq_cmd_details *cmd_details)
3583 struct i40e_aq_desc desc;
3584 enum i40e_status_code status;
3586 UNREFERENCED_2PARAMETER(buff, buff_size);
3588 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3589 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3590 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3591 status = I40E_ERR_NOT_IMPLEMENTED;
3598 * @hw: pointer to the hw struct
3599 * @module_pointer: module pointer location in words from the NVM beginning
3600 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3601 * @length: length of the section to be erased (expressed in 4 KB)
3602 * @last_command: tells if this is the last command in a series
3603 * @cmd_details: pointer to command details structure or NULL
3605 * Erase the NVM sector using the admin queue commands
3607 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3608 u32 offset, u16 length, bool last_command,
3609 struct i40e_asq_cmd_details *cmd_details)
3611 struct i40e_aq_desc desc;
3612 struct i40e_aqc_nvm_update *cmd =
3613 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3614 enum i40e_status_code status;
3616 DEBUGFUNC("i40e_aq_erase_nvm");
3618 /* In offset the highest byte must be zeroed. */
3619 if (offset & 0xFF000000) {
3620 status = I40E_ERR_PARAM;
3621 goto i40e_aq_erase_nvm_exit;
3624 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3626 /* If this is the last command in a series, set the proper flag. */
3628 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3629 cmd->module_pointer = module_pointer;
3630 cmd->offset = CPU_TO_LE32(offset);
3631 cmd->length = CPU_TO_LE16(length);
3633 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3635 i40e_aq_erase_nvm_exit:
3640 * i40e_parse_discover_capabilities
3641 * @hw: pointer to the hw struct
3642 * @buff: pointer to a buffer containing device/function capability records
3643 * @cap_count: number of capability records in the list
3644 * @list_type_opc: type of capabilities list to parse
3646 * Parse the device/function capabilities list.
3648 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3650 enum i40e_admin_queue_opc list_type_opc)
3652 struct i40e_aqc_list_capabilities_element_resp *cap;
3653 u32 valid_functions, num_functions;
3654 u32 number, logical_id, phys_id;
3655 struct i40e_hw_capabilities *p;
3660 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3662 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3663 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3664 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3665 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3669 for (i = 0; i < cap_count; i++, cap++) {
3670 id = LE16_TO_CPU(cap->id);
3671 number = LE32_TO_CPU(cap->number);
3672 logical_id = LE32_TO_CPU(cap->logical_id);
3673 phys_id = LE32_TO_CPU(cap->phys_id);
3674 major_rev = cap->major_rev;
3677 case I40E_AQ_CAP_ID_SWITCH_MODE:
3678 p->switch_mode = number;
3679 i40e_debug(hw, I40E_DEBUG_INIT,
3680 "HW Capability: Switch mode = %d\n",
3683 case I40E_AQ_CAP_ID_MNG_MODE:
3684 p->management_mode = number;
3685 if (major_rev > 1) {
3686 p->mng_protocols_over_mctp = logical_id;
3687 i40e_debug(hw, I40E_DEBUG_INIT,
3688 "HW Capability: Protocols over MCTP = %d\n",
3689 p->mng_protocols_over_mctp);
3691 p->mng_protocols_over_mctp = 0;
3693 i40e_debug(hw, I40E_DEBUG_INIT,
3694 "HW Capability: Management Mode = %d\n",
3695 p->management_mode);
3697 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3698 p->npar_enable = number;
3699 i40e_debug(hw, I40E_DEBUG_INIT,
3700 "HW Capability: NPAR enable = %d\n",
3703 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3705 i40e_debug(hw, I40E_DEBUG_INIT,
3706 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3708 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3709 p->valid_functions = number;
3710 i40e_debug(hw, I40E_DEBUG_INIT,
3711 "HW Capability: Valid Functions = %d\n",
3712 p->valid_functions);
3714 case I40E_AQ_CAP_ID_SRIOV:
3716 p->sr_iov_1_1 = true;
3717 i40e_debug(hw, I40E_DEBUG_INIT,
3718 "HW Capability: SR-IOV = %d\n",
3721 case I40E_AQ_CAP_ID_VF:
3722 p->num_vfs = number;
3723 p->vf_base_id = logical_id;
3724 i40e_debug(hw, I40E_DEBUG_INIT,
3725 "HW Capability: VF count = %d\n",
3727 i40e_debug(hw, I40E_DEBUG_INIT,
3728 "HW Capability: VF base_id = %d\n",
3731 case I40E_AQ_CAP_ID_VMDQ:
3734 i40e_debug(hw, I40E_DEBUG_INIT,
3735 "HW Capability: VMDQ = %d\n", p->vmdq);
3737 case I40E_AQ_CAP_ID_8021QBG:
3739 p->evb_802_1_qbg = true;
3740 i40e_debug(hw, I40E_DEBUG_INIT,
3741 "HW Capability: 802.1Qbg = %d\n", number);
3743 case I40E_AQ_CAP_ID_8021QBR:
3745 p->evb_802_1_qbh = true;
3746 i40e_debug(hw, I40E_DEBUG_INIT,
3747 "HW Capability: 802.1Qbh = %d\n", number);
3749 case I40E_AQ_CAP_ID_VSI:
3750 p->num_vsis = number;
3751 i40e_debug(hw, I40E_DEBUG_INIT,
3752 "HW Capability: VSI count = %d\n",
3755 case I40E_AQ_CAP_ID_DCB:
3758 p->enabled_tcmap = logical_id;
3761 i40e_debug(hw, I40E_DEBUG_INIT,
3762 "HW Capability: DCB = %d\n", p->dcb);
3763 i40e_debug(hw, I40E_DEBUG_INIT,
3764 "HW Capability: TC Mapping = %d\n",
3766 i40e_debug(hw, I40E_DEBUG_INIT,
3767 "HW Capability: TC Max = %d\n", p->maxtc);
3769 case I40E_AQ_CAP_ID_FCOE:
3772 i40e_debug(hw, I40E_DEBUG_INIT,
3773 "HW Capability: FCOE = %d\n", p->fcoe);
3775 case I40E_AQ_CAP_ID_ISCSI:
3778 i40e_debug(hw, I40E_DEBUG_INIT,
3779 "HW Capability: iSCSI = %d\n", p->iscsi);
3781 case I40E_AQ_CAP_ID_RSS:
3783 p->rss_table_size = number;
3784 p->rss_table_entry_width = logical_id;
3785 i40e_debug(hw, I40E_DEBUG_INIT,
3786 "HW Capability: RSS = %d\n", p->rss);
3787 i40e_debug(hw, I40E_DEBUG_INIT,
3788 "HW Capability: RSS table size = %d\n",
3790 i40e_debug(hw, I40E_DEBUG_INIT,
3791 "HW Capability: RSS table width = %d\n",
3792 p->rss_table_entry_width);
3794 case I40E_AQ_CAP_ID_RXQ:
3795 p->num_rx_qp = number;
3796 p->base_queue = phys_id;
3797 i40e_debug(hw, I40E_DEBUG_INIT,
3798 "HW Capability: Rx QP = %d\n", number);
3799 i40e_debug(hw, I40E_DEBUG_INIT,
3800 "HW Capability: base_queue = %d\n",
3803 case I40E_AQ_CAP_ID_TXQ:
3804 p->num_tx_qp = number;
3805 p->base_queue = phys_id;
3806 i40e_debug(hw, I40E_DEBUG_INIT,
3807 "HW Capability: Tx QP = %d\n", number);
3808 i40e_debug(hw, I40E_DEBUG_INIT,
3809 "HW Capability: base_queue = %d\n",
3812 case I40E_AQ_CAP_ID_MSIX:
3813 p->num_msix_vectors = number;
3814 i40e_debug(hw, I40E_DEBUG_INIT,
3815 "HW Capability: MSIX vector count = %d\n",
3816 p->num_msix_vectors);
3818 case I40E_AQ_CAP_ID_VF_MSIX:
3819 p->num_msix_vectors_vf = number;
3820 i40e_debug(hw, I40E_DEBUG_INIT,
3821 "HW Capability: MSIX VF vector count = %d\n",
3822 p->num_msix_vectors_vf);
3824 case I40E_AQ_CAP_ID_FLEX10:
3825 if (major_rev == 1) {
3827 p->flex10_enable = true;
3828 p->flex10_capable = true;
3831 /* Capability revision >= 2 */
3833 p->flex10_enable = true;
3835 p->flex10_capable = true;
3837 p->flex10_mode = logical_id;
3838 p->flex10_status = phys_id;
3839 i40e_debug(hw, I40E_DEBUG_INIT,
3840 "HW Capability: Flex10 mode = %d\n",
3842 i40e_debug(hw, I40E_DEBUG_INIT,
3843 "HW Capability: Flex10 status = %d\n",
3846 case I40E_AQ_CAP_ID_CEM:
3849 i40e_debug(hw, I40E_DEBUG_INIT,
3850 "HW Capability: CEM = %d\n", p->mgmt_cem);
3852 case I40E_AQ_CAP_ID_IWARP:
3855 i40e_debug(hw, I40E_DEBUG_INIT,
3856 "HW Capability: iWARP = %d\n", p->iwarp);
3858 case I40E_AQ_CAP_ID_LED:
3859 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3860 p->led[phys_id] = true;
3861 i40e_debug(hw, I40E_DEBUG_INIT,
3862 "HW Capability: LED - PIN %d\n", phys_id);
3864 case I40E_AQ_CAP_ID_SDP:
3865 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3866 p->sdp[phys_id] = true;
3867 i40e_debug(hw, I40E_DEBUG_INIT,
3868 "HW Capability: SDP - PIN %d\n", phys_id);
3870 case I40E_AQ_CAP_ID_MDIO:
3872 p->mdio_port_num = phys_id;
3873 p->mdio_port_mode = logical_id;
3875 i40e_debug(hw, I40E_DEBUG_INIT,
3876 "HW Capability: MDIO port number = %d\n",
3878 i40e_debug(hw, I40E_DEBUG_INIT,
3879 "HW Capability: MDIO port mode = %d\n",
3882 case I40E_AQ_CAP_ID_1588:
3884 p->ieee_1588 = true;
3885 i40e_debug(hw, I40E_DEBUG_INIT,
3886 "HW Capability: IEEE 1588 = %d\n",
3889 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3891 p->fd_filters_guaranteed = number;
3892 p->fd_filters_best_effort = logical_id;
3893 i40e_debug(hw, I40E_DEBUG_INIT,
3894 "HW Capability: Flow Director = 1\n");
3895 i40e_debug(hw, I40E_DEBUG_INIT,
3896 "HW Capability: Guaranteed FD filters = %d\n",
3897 p->fd_filters_guaranteed);
3899 case I40E_AQ_CAP_ID_WSR_PROT:
3900 p->wr_csr_prot = (u64)number;
3901 p->wr_csr_prot |= (u64)logical_id << 32;
3902 i40e_debug(hw, I40E_DEBUG_INIT,
3903 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3904 (p->wr_csr_prot & 0xffff));
3906 case I40E_AQ_CAP_ID_NVM_MGMT:
3907 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3908 p->sec_rev_disabled = true;
3909 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3910 p->update_disabled = true;
3912 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3913 hw->num_wol_proxy_filters = (u16)number;
3914 hw->wol_proxy_vsi_seid = (u16)logical_id;
3915 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3916 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3917 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3919 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3920 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3921 i40e_debug(hw, I40E_DEBUG_INIT,
3922 "HW Capability: WOL proxy filters = %d\n",
3923 hw->num_wol_proxy_filters);
3931 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3933 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3936 /* count the enabled ports (aka the "not disabled" ports) */
3938 for (i = 0; i < 4; i++) {
3939 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3942 /* use AQ read to get the physical register offset instead
3943 * of the port relative offset
3945 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3946 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3950 valid_functions = p->valid_functions;
3952 while (valid_functions) {
3953 if (valid_functions & 1)
3955 valid_functions >>= 1;
3958 /* partition id is 1-based, and functions are evenly spread
3959 * across the ports as partitions
3961 if (hw->num_ports != 0) {
3962 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3963 hw->num_partitions = num_functions / hw->num_ports;
3966 /* additional HW specific goodies that might
3967 * someday be HW version specific
3969 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3973 * i40e_aq_discover_capabilities
3974 * @hw: pointer to the hw struct
3975 * @buff: a virtual buffer to hold the capabilities
3976 * @buff_size: Size of the virtual buffer
3977 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3978 * @list_type_opc: capabilities type to discover - pass in the command opcode
3979 * @cmd_details: pointer to command details structure or NULL
3981 * Get the device capabilities descriptions from the firmware
3983 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3984 void *buff, u16 buff_size, u16 *data_size,
3985 enum i40e_admin_queue_opc list_type_opc,
3986 struct i40e_asq_cmd_details *cmd_details)
3988 struct i40e_aqc_list_capabilites *cmd;
3989 struct i40e_aq_desc desc;
3990 enum i40e_status_code status = I40E_SUCCESS;
3992 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3994 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3995 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3996 status = I40E_ERR_PARAM;
4000 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4002 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4003 if (buff_size > I40E_AQ_LARGE_BUF)
4004 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4006 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4007 *data_size = LE16_TO_CPU(desc.datalen);
4012 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4020 * i40e_aq_update_nvm
4021 * @hw: pointer to the hw struct
4022 * @module_pointer: module pointer location in words from the NVM beginning
4023 * @offset: byte offset from the module beginning
4024 * @length: length of the section to be written (in bytes from the offset)
4025 * @data: command buffer (size [bytes] = length)
4026 * @last_command: tells if this is the last command in a series
4027 * @cmd_details: pointer to command details structure or NULL
4029 * Update the NVM using the admin queue commands
4031 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4032 u32 offset, u16 length, void *data,
4034 struct i40e_asq_cmd_details *cmd_details)
4036 struct i40e_aq_desc desc;
4037 struct i40e_aqc_nvm_update *cmd =
4038 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4039 enum i40e_status_code status;
4041 DEBUGFUNC("i40e_aq_update_nvm");
4043 /* In offset the highest byte must be zeroed. */
4044 if (offset & 0xFF000000) {
4045 status = I40E_ERR_PARAM;
4046 goto i40e_aq_update_nvm_exit;
4049 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4051 /* If this is the last command in a series, set the proper flag. */
4053 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4054 cmd->module_pointer = module_pointer;
4055 cmd->offset = CPU_TO_LE32(offset);
4056 cmd->length = CPU_TO_LE16(length);
4058 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4059 if (length > I40E_AQ_LARGE_BUF)
4060 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4062 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4064 i40e_aq_update_nvm_exit:
4069 * i40e_aq_get_lldp_mib
4070 * @hw: pointer to the hw struct
4071 * @bridge_type: type of bridge requested
4072 * @mib_type: Local, Remote or both Local and Remote MIBs
4073 * @buff: pointer to a user supplied buffer to store the MIB block
4074 * @buff_size: size of the buffer (in bytes)
4075 * @local_len : length of the returned Local LLDP MIB
4076 * @remote_len: length of the returned Remote LLDP MIB
4077 * @cmd_details: pointer to command details structure or NULL
4079 * Requests the complete LLDP MIB (entire packet).
4081 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4082 u8 mib_type, void *buff, u16 buff_size,
4083 u16 *local_len, u16 *remote_len,
4084 struct i40e_asq_cmd_details *cmd_details)
4086 struct i40e_aq_desc desc;
4087 struct i40e_aqc_lldp_get_mib *cmd =
4088 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4089 struct i40e_aqc_lldp_get_mib *resp =
4090 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4091 enum i40e_status_code status;
4093 if (buff_size == 0 || !buff)
4094 return I40E_ERR_PARAM;
4096 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4097 /* Indirect Command */
4098 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4100 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4101 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4102 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4104 desc.datalen = CPU_TO_LE16(buff_size);
4106 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4107 if (buff_size > I40E_AQ_LARGE_BUF)
4108 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4110 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4112 if (local_len != NULL)
4113 *local_len = LE16_TO_CPU(resp->local_len);
4114 if (remote_len != NULL)
4115 *remote_len = LE16_TO_CPU(resp->remote_len);
4122 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4123 * @hw: pointer to the hw struct
4124 * @mib_type: Local, Remote or both Local and Remote MIBs
4125 * @buff: pointer to a user supplied buffer to store the MIB block
4126 * @buff_size: size of the buffer (in bytes)
4127 * @cmd_details: pointer to command details structure or NULL
4131 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4132 u8 mib_type, void *buff, u16 buff_size,
4133 struct i40e_asq_cmd_details *cmd_details)
4135 struct i40e_aq_desc desc;
4136 struct i40e_aqc_lldp_set_local_mib *cmd =
4137 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4138 enum i40e_status_code status;
4140 if (buff_size == 0 || !buff)
4141 return I40E_ERR_PARAM;
4143 i40e_fill_default_direct_cmd_desc(&desc,
4144 i40e_aqc_opc_lldp_set_local_mib);
4145 /* Indirect Command */
4146 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4147 if (buff_size > I40E_AQ_LARGE_BUF)
4148 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4149 desc.datalen = CPU_TO_LE16(buff_size);
4151 cmd->type = mib_type;
4152 cmd->length = CPU_TO_LE16(buff_size);
4153 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4154 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4156 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4161 * i40e_aq_cfg_lldp_mib_change_event
4162 * @hw: pointer to the hw struct
4163 * @enable_update: Enable or Disable event posting
4164 * @cmd_details: pointer to command details structure or NULL
4166 * Enable or Disable posting of an event on ARQ when LLDP MIB
4167 * associated with the interface changes
4169 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4171 struct i40e_asq_cmd_details *cmd_details)
4173 struct i40e_aq_desc desc;
4174 struct i40e_aqc_lldp_update_mib *cmd =
4175 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4176 enum i40e_status_code status;
4178 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4181 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4183 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4189 * i40e_aq_add_lldp_tlv
4190 * @hw: pointer to the hw struct
4191 * @bridge_type: type of bridge
4192 * @buff: buffer with TLV to add
4193 * @buff_size: length of the buffer
4194 * @tlv_len: length of the TLV to be added
4195 * @mib_len: length of the LLDP MIB returned in response
4196 * @cmd_details: pointer to command details structure or NULL
4198 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4199 * it is responsibility of the caller to make sure that the TLV is not
4200 * already present in the LLDPDU.
4201 * In return firmware will write the complete LLDP MIB with the newly
4202 * added TLV in the response buffer.
4204 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4205 void *buff, u16 buff_size, u16 tlv_len,
4207 struct i40e_asq_cmd_details *cmd_details)
4209 struct i40e_aq_desc desc;
4210 struct i40e_aqc_lldp_add_tlv *cmd =
4211 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4212 enum i40e_status_code status;
4214 if (buff_size == 0 || !buff || tlv_len == 0)
4215 return I40E_ERR_PARAM;
4217 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4219 /* Indirect Command */
4220 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4221 if (buff_size > I40E_AQ_LARGE_BUF)
4222 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4223 desc.datalen = CPU_TO_LE16(buff_size);
4225 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4226 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4227 cmd->len = CPU_TO_LE16(tlv_len);
4229 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4231 if (mib_len != NULL)
4232 *mib_len = LE16_TO_CPU(desc.datalen);
4239 * i40e_aq_update_lldp_tlv
4240 * @hw: pointer to the hw struct
4241 * @bridge_type: type of bridge
4242 * @buff: buffer with TLV to update
4243 * @buff_size: size of the buffer holding original and updated TLVs
4244 * @old_len: Length of the Original TLV
4245 * @new_len: Length of the Updated TLV
4246 * @offset: offset of the updated TLV in the buff
4247 * @mib_len: length of the returned LLDP MIB
4248 * @cmd_details: pointer to command details structure or NULL
4250 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4251 * Firmware will place the complete LLDP MIB in response buffer with the
4254 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4255 u8 bridge_type, void *buff, u16 buff_size,
4256 u16 old_len, u16 new_len, u16 offset,
4258 struct i40e_asq_cmd_details *cmd_details)
4260 struct i40e_aq_desc desc;
4261 struct i40e_aqc_lldp_update_tlv *cmd =
4262 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4263 enum i40e_status_code status;
4265 if (buff_size == 0 || !buff || offset == 0 ||
4266 old_len == 0 || new_len == 0)
4267 return I40E_ERR_PARAM;
4269 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4271 /* Indirect Command */
4272 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4273 if (buff_size > I40E_AQ_LARGE_BUF)
4274 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4275 desc.datalen = CPU_TO_LE16(buff_size);
4277 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4278 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4279 cmd->old_len = CPU_TO_LE16(old_len);
4280 cmd->new_offset = CPU_TO_LE16(offset);
4281 cmd->new_len = CPU_TO_LE16(new_len);
4283 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4285 if (mib_len != NULL)
4286 *mib_len = LE16_TO_CPU(desc.datalen);
4293 * i40e_aq_delete_lldp_tlv
4294 * @hw: pointer to the hw struct
4295 * @bridge_type: type of bridge
4296 * @buff: pointer to a user supplied buffer that has the TLV
4297 * @buff_size: length of the buffer
4298 * @tlv_len: length of the TLV to be deleted
4299 * @mib_len: length of the returned LLDP MIB
4300 * @cmd_details: pointer to command details structure or NULL
4302 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4303 * The firmware places the entire LLDP MIB in the response buffer.
4305 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4306 u8 bridge_type, void *buff, u16 buff_size,
4307 u16 tlv_len, u16 *mib_len,
4308 struct i40e_asq_cmd_details *cmd_details)
4310 struct i40e_aq_desc desc;
4311 struct i40e_aqc_lldp_add_tlv *cmd =
4312 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4313 enum i40e_status_code status;
4315 if (buff_size == 0 || !buff)
4316 return I40E_ERR_PARAM;
4318 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4320 /* Indirect Command */
4321 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4322 if (buff_size > I40E_AQ_LARGE_BUF)
4323 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4324 desc.datalen = CPU_TO_LE16(buff_size);
4325 cmd->len = CPU_TO_LE16(tlv_len);
4326 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4327 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4329 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4331 if (mib_len != NULL)
4332 *mib_len = LE16_TO_CPU(desc.datalen);
4340 * @hw: pointer to the hw struct
4341 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4342 * @cmd_details: pointer to command details structure or NULL
4344 * Stop or Shutdown the embedded LLDP Agent
4346 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4347 struct i40e_asq_cmd_details *cmd_details)
4349 struct i40e_aq_desc desc;
4350 struct i40e_aqc_lldp_stop *cmd =
4351 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4352 enum i40e_status_code status;
4354 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4357 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4359 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4365 * i40e_aq_start_lldp
4366 * @hw: pointer to the hw struct
4367 * @cmd_details: pointer to command details structure or NULL
4369 * Start the embedded LLDP Agent on all ports.
4371 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4372 struct i40e_asq_cmd_details *cmd_details)
4374 struct i40e_aq_desc desc;
4375 struct i40e_aqc_lldp_start *cmd =
4376 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4377 enum i40e_status_code status;
4379 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4381 cmd->command = I40E_AQ_LLDP_AGENT_START;
4383 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4389 * i40e_aq_get_cee_dcb_config
4390 * @hw: pointer to the hw struct
4391 * @buff: response buffer that stores CEE operational configuration
4392 * @buff_size: size of the buffer passed
4393 * @cmd_details: pointer to command details structure or NULL
4395 * Get CEE DCBX mode operational configuration from firmware
4397 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4398 void *buff, u16 buff_size,
4399 struct i40e_asq_cmd_details *cmd_details)
4401 struct i40e_aq_desc desc;
4402 enum i40e_status_code status;
4404 if (buff_size == 0 || !buff)
4405 return I40E_ERR_PARAM;
4407 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4409 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4410 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4417 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4418 * @hw: pointer to the hw struct
4419 * @start_agent: True if DCBx Agent needs to be Started
4420 * False if DCBx Agent needs to be Stopped
4421 * @cmd_details: pointer to command details structure or NULL
4423 * Start/Stop the embedded dcbx Agent
4425 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4427 struct i40e_asq_cmd_details *cmd_details)
4429 struct i40e_aq_desc desc;
4430 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4431 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4433 enum i40e_status_code status;
4435 i40e_fill_default_direct_cmd_desc(&desc,
4436 i40e_aqc_opc_lldp_stop_start_spec_agent);
4439 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4441 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4447 * i40e_aq_add_udp_tunnel
4448 * @hw: pointer to the hw struct
4449 * @udp_port: the UDP port to add in Host byte order
4450 * @header_len: length of the tunneling header length in DWords
4451 * @protocol_index: protocol index type
4452 * @filter_index: pointer to filter index
4453 * @cmd_details: pointer to command details structure or NULL
4455 * Note: Firmware expects the udp_port value to be in Little Endian format,
4456 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4457 * Little Endian order.
4459 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4460 u16 udp_port, u8 protocol_index,
4462 struct i40e_asq_cmd_details *cmd_details)
4464 struct i40e_aq_desc desc;
4465 struct i40e_aqc_add_udp_tunnel *cmd =
4466 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4467 struct i40e_aqc_del_udp_tunnel_completion *resp =
4468 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4469 enum i40e_status_code status;
4471 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4473 cmd->udp_port = CPU_TO_LE16(udp_port);
4474 cmd->protocol_type = protocol_index;
4476 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4478 if (!status && filter_index)
4479 *filter_index = resp->index;
4485 * i40e_aq_del_udp_tunnel
4486 * @hw: pointer to the hw struct
4487 * @index: filter index
4488 * @cmd_details: pointer to command details structure or NULL
4490 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4491 struct i40e_asq_cmd_details *cmd_details)
4493 struct i40e_aq_desc desc;
4494 struct i40e_aqc_remove_udp_tunnel *cmd =
4495 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4496 enum i40e_status_code status;
4498 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4502 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4508 * i40e_aq_get_switch_resource_alloc (0x0204)
4509 * @hw: pointer to the hw struct
4510 * @num_entries: pointer to u8 to store the number of resource entries returned
4511 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4512 * to store the resource information for all resource types. Each
4513 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4514 * @count: size, in bytes, of the buffer provided
4515 * @cmd_details: pointer to command details structure or NULL
4517 * Query the resources allocated to a function.
4519 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4521 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4523 struct i40e_asq_cmd_details *cmd_details)
4525 struct i40e_aq_desc desc;
4526 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4527 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4528 enum i40e_status_code status;
4529 u16 length = count * sizeof(*buf);
4531 i40e_fill_default_direct_cmd_desc(&desc,
4532 i40e_aqc_opc_get_switch_resource_alloc);
4534 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4535 if (length > I40E_AQ_LARGE_BUF)
4536 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4538 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4540 if (!status && num_entries)
4541 *num_entries = cmd_resp->num_entries;
4547 * i40e_aq_delete_element - Delete switch element
4548 * @hw: pointer to the hw struct
4549 * @seid: the SEID to delete from the switch
4550 * @cmd_details: pointer to command details structure or NULL
4552 * This deletes a switch element from the switch.
4554 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4555 struct i40e_asq_cmd_details *cmd_details)
4557 struct i40e_aq_desc desc;
4558 struct i40e_aqc_switch_seid *cmd =
4559 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4560 enum i40e_status_code status;
4563 return I40E_ERR_PARAM;
4565 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4567 cmd->seid = CPU_TO_LE16(seid);
4569 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4575 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4576 * @hw: pointer to the hw struct
4577 * @flags: component flags
4578 * @mac_seid: uplink seid (MAC SEID)
4579 * @vsi_seid: connected vsi seid
4580 * @ret_seid: seid of create pv component
4582 * This instantiates an i40e port virtualizer with specified flags.
4583 * Depending on specified flags the port virtualizer can act as a
4584 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4586 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4587 u16 mac_seid, u16 vsi_seid,
4590 struct i40e_aq_desc desc;
4591 struct i40e_aqc_add_update_pv *cmd =
4592 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4593 struct i40e_aqc_add_update_pv_completion *resp =
4594 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4595 enum i40e_status_code status;
4598 return I40E_ERR_PARAM;
4600 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4601 cmd->command_flags = CPU_TO_LE16(flags);
4602 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4603 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4605 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4606 if (!status && ret_seid)
4607 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4613 * i40e_aq_add_tag - Add an S/E-tag
4614 * @hw: pointer to the hw struct
4615 * @direct_to_queue: should s-tag direct flow to a specific queue
4616 * @vsi_seid: VSI SEID to use this tag
4617 * @tag: value of the tag
4618 * @queue_num: queue number, only valid is direct_to_queue is true
4619 * @tags_used: return value, number of tags in use by this PF
4620 * @tags_free: return value, number of unallocated tags
4621 * @cmd_details: pointer to command details structure or NULL
4623 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4624 * the number of tags allocated by the PF, and the number of unallocated
4627 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4628 u16 vsi_seid, u16 tag, u16 queue_num,
4629 u16 *tags_used, u16 *tags_free,
4630 struct i40e_asq_cmd_details *cmd_details)
4632 struct i40e_aq_desc desc;
4633 struct i40e_aqc_add_tag *cmd =
4634 (struct i40e_aqc_add_tag *)&desc.params.raw;
4635 struct i40e_aqc_add_remove_tag_completion *resp =
4636 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4637 enum i40e_status_code status;
4640 return I40E_ERR_PARAM;
4642 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4644 cmd->seid = CPU_TO_LE16(vsi_seid);
4645 cmd->tag = CPU_TO_LE16(tag);
4646 if (direct_to_queue) {
4647 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4648 cmd->queue_number = CPU_TO_LE16(queue_num);
4651 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4654 if (tags_used != NULL)
4655 *tags_used = LE16_TO_CPU(resp->tags_used);
4656 if (tags_free != NULL)
4657 *tags_free = LE16_TO_CPU(resp->tags_free);
4664 * i40e_aq_remove_tag - Remove an S- or E-tag
4665 * @hw: pointer to the hw struct
4666 * @vsi_seid: VSI SEID this tag is associated with
4667 * @tag: value of the S-tag to delete
4668 * @tags_used: return value, number of tags in use by this PF
4669 * @tags_free: return value, number of unallocated tags
4670 * @cmd_details: pointer to command details structure or NULL
4672 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4673 * the number of tags allocated by the PF, and the number of unallocated
4676 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4677 u16 tag, u16 *tags_used, u16 *tags_free,
4678 struct i40e_asq_cmd_details *cmd_details)
4680 struct i40e_aq_desc desc;
4681 struct i40e_aqc_remove_tag *cmd =
4682 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4683 struct i40e_aqc_add_remove_tag_completion *resp =
4684 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4685 enum i40e_status_code status;
4688 return I40E_ERR_PARAM;
4690 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4692 cmd->seid = CPU_TO_LE16(vsi_seid);
4693 cmd->tag = CPU_TO_LE16(tag);
4695 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4698 if (tags_used != NULL)
4699 *tags_used = LE16_TO_CPU(resp->tags_used);
4700 if (tags_free != NULL)
4701 *tags_free = LE16_TO_CPU(resp->tags_free);
4708 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4709 * @hw: pointer to the hw struct
4710 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4711 * @etag: value of E-tag to add
4712 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4713 * @buf: address of indirect buffer
4714 * @tags_used: return value, number of E-tags in use by this port
4715 * @tags_free: return value, number of unallocated M-tags
4716 * @cmd_details: pointer to command details structure or NULL
4718 * This associates a multicast E-tag to a port virtualizer. It will return
4719 * the number of tags allocated by the PF, and the number of unallocated
4722 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4723 * num_tags_in_buf long.
4725 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4726 u16 etag, u8 num_tags_in_buf, void *buf,
4727 u16 *tags_used, u16 *tags_free,
4728 struct i40e_asq_cmd_details *cmd_details)
4730 struct i40e_aq_desc desc;
4731 struct i40e_aqc_add_remove_mcast_etag *cmd =
4732 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4733 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4734 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4735 enum i40e_status_code status;
4736 u16 length = sizeof(u16) * num_tags_in_buf;
4738 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4739 return I40E_ERR_PARAM;
4741 i40e_fill_default_direct_cmd_desc(&desc,
4742 i40e_aqc_opc_add_multicast_etag);
4744 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4745 cmd->etag = CPU_TO_LE16(etag);
4746 cmd->num_unicast_etags = num_tags_in_buf;
4748 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4749 if (length > I40E_AQ_LARGE_BUF)
4750 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4752 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4755 if (tags_used != NULL)
4756 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4757 if (tags_free != NULL)
4758 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4765 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4766 * @hw: pointer to the hw struct
4767 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4768 * @etag: value of the E-tag to remove
4769 * @tags_used: return value, number of tags in use by this port
4770 * @tags_free: return value, number of unallocated tags
4771 * @cmd_details: pointer to command details structure or NULL
4773 * This deletes an E-tag from the port virtualizer. It will return
4774 * the number of tags allocated by the port, and the number of unallocated
4777 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4778 u16 etag, u16 *tags_used, u16 *tags_free,
4779 struct i40e_asq_cmd_details *cmd_details)
4781 struct i40e_aq_desc desc;
4782 struct i40e_aqc_add_remove_mcast_etag *cmd =
4783 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4784 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4785 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4786 enum i40e_status_code status;
4790 return I40E_ERR_PARAM;
4792 i40e_fill_default_direct_cmd_desc(&desc,
4793 i40e_aqc_opc_remove_multicast_etag);
4795 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4796 cmd->etag = CPU_TO_LE16(etag);
4798 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4801 if (tags_used != NULL)
4802 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4803 if (tags_free != NULL)
4804 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4811 * i40e_aq_update_tag - Update an S/E-tag
4812 * @hw: pointer to the hw struct
4813 * @vsi_seid: VSI SEID using this S-tag
4814 * @old_tag: old tag value
4815 * @new_tag: new tag value
4816 * @tags_used: return value, number of tags in use by this PF
4817 * @tags_free: return value, number of unallocated tags
4818 * @cmd_details: pointer to command details structure or NULL
4820 * This updates the value of the tag currently attached to this VSI
4821 * in the switch complex. It will return the number of tags allocated
4822 * by the PF, and the number of unallocated tags available.
4824 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4825 u16 old_tag, u16 new_tag, u16 *tags_used,
4827 struct i40e_asq_cmd_details *cmd_details)
4829 struct i40e_aq_desc desc;
4830 struct i40e_aqc_update_tag *cmd =
4831 (struct i40e_aqc_update_tag *)&desc.params.raw;
4832 struct i40e_aqc_update_tag_completion *resp =
4833 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4834 enum i40e_status_code status;
4837 return I40E_ERR_PARAM;
4839 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4841 cmd->seid = CPU_TO_LE16(vsi_seid);
4842 cmd->old_tag = CPU_TO_LE16(old_tag);
4843 cmd->new_tag = CPU_TO_LE16(new_tag);
4845 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4848 if (tags_used != NULL)
4849 *tags_used = LE16_TO_CPU(resp->tags_used);
4850 if (tags_free != NULL)
4851 *tags_free = LE16_TO_CPU(resp->tags_free);
4858 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4859 * @hw: pointer to the hw struct
4860 * @tcmap: TC map for request/release any ignore PFC condition
4861 * @request: request or release ignore PFC condition
4862 * @tcmap_ret: return TCs for which PFC is currently ignored
4863 * @cmd_details: pointer to command details structure or NULL
4865 * This sends out request/release to ignore PFC condition for a TC.
4866 * It will return the TCs for which PFC is currently ignored.
4868 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4869 bool request, u8 *tcmap_ret,
4870 struct i40e_asq_cmd_details *cmd_details)
4872 struct i40e_aq_desc desc;
4873 struct i40e_aqc_pfc_ignore *cmd_resp =
4874 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4875 enum i40e_status_code status;
4877 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4880 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4882 cmd_resp->tc_bitmap = tcmap;
4884 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4887 if (tcmap_ret != NULL)
4888 *tcmap_ret = cmd_resp->tc_bitmap;
4895 * i40e_aq_dcb_updated - DCB Updated Command
4896 * @hw: pointer to the hw struct
4897 * @cmd_details: pointer to command details structure or NULL
4899 * When LLDP is handled in PF this command is used by the PF
4900 * to notify EMP that a DCB setting is modified.
4901 * When LLDP is handled in EMP this command is used by the PF
4902 * to notify EMP whenever one of the following parameters get
4904 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4905 * - PCIRTT in PRTDCB_GENC.PCIRTT
4906 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4907 * EMP will return when the shared RPB settings have been
4908 * recomputed and modified. The retval field in the descriptor
4909 * will be set to 0 when RPB is modified.
4911 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4912 struct i40e_asq_cmd_details *cmd_details)
4914 struct i40e_aq_desc desc;
4915 enum i40e_status_code status;
4917 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4919 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4925 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4926 * @hw: pointer to the hw struct
4927 * @seid: defines the SEID of the switch for which the stats are requested
4928 * @vlan_id: the VLAN ID for which the statistics are requested
4929 * @stat_index: index of the statistics counters block assigned to this VLAN
4930 * @cmd_details: pointer to command details structure or NULL
4932 * XL710 supports 128 smonVlanStats counters.This command is used to
4933 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4936 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4937 u16 vlan_id, u16 *stat_index,
4938 struct i40e_asq_cmd_details *cmd_details)
4940 struct i40e_aq_desc desc;
4941 struct i40e_aqc_add_remove_statistics *cmd_resp =
4942 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4943 enum i40e_status_code status;
4945 if ((seid == 0) || (stat_index == NULL))
4946 return I40E_ERR_PARAM;
4948 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4950 cmd_resp->seid = CPU_TO_LE16(seid);
4951 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4953 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4955 if (!status && stat_index)
4956 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4962 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4963 * @hw: pointer to the hw struct
4964 * @seid: defines the SEID of the switch for which the stats are requested
4965 * @vlan_id: the VLAN ID for which the statistics are requested
4966 * @stat_index: index of the statistics counters block assigned to this VLAN
4967 * @cmd_details: pointer to command details structure or NULL
4969 * XL710 supports 128 smonVlanStats counters.This command is used to
4970 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4973 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4974 u16 vlan_id, u16 stat_index,
4975 struct i40e_asq_cmd_details *cmd_details)
4977 struct i40e_aq_desc desc;
4978 struct i40e_aqc_add_remove_statistics *cmd =
4979 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4980 enum i40e_status_code status;
4983 return I40E_ERR_PARAM;
4985 i40e_fill_default_direct_cmd_desc(&desc,
4986 i40e_aqc_opc_remove_statistics);
4988 cmd->seid = CPU_TO_LE16(seid);
4989 cmd->vlan = CPU_TO_LE16(vlan_id);
4990 cmd->stat_index = CPU_TO_LE16(stat_index);
4992 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4998 * i40e_aq_set_port_parameters - set physical port parameters.
4999 * @hw: pointer to the hw struct
5000 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5001 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5002 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5003 * @double_vlan: if set double VLAN is enabled
5004 * @cmd_details: pointer to command details structure or NULL
5006 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5007 u16 bad_frame_vsi, bool save_bad_pac,
5008 bool pad_short_pac, bool double_vlan,
5009 struct i40e_asq_cmd_details *cmd_details)
5011 struct i40e_aqc_set_port_parameters *cmd;
5012 enum i40e_status_code status;
5013 struct i40e_aq_desc desc;
5014 u16 command_flags = 0;
5016 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5018 i40e_fill_default_direct_cmd_desc(&desc,
5019 i40e_aqc_opc_set_port_parameters);
5021 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5023 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5025 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5027 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5028 cmd->command_flags = CPU_TO_LE16(command_flags);
5030 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5036 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5037 * @hw: pointer to the hw struct
5038 * @seid: seid for the physical port/switching component/vsi
5039 * @buff: Indirect buffer to hold data parameters and response
5040 * @buff_size: Indirect buffer size
5041 * @opcode: Tx scheduler AQ command opcode
5042 * @cmd_details: pointer to command details structure or NULL
5044 * Generic command handler for Tx scheduler AQ commands
5046 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5047 void *buff, u16 buff_size,
5048 enum i40e_admin_queue_opc opcode,
5049 struct i40e_asq_cmd_details *cmd_details)
5051 struct i40e_aq_desc desc;
5052 struct i40e_aqc_tx_sched_ind *cmd =
5053 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5054 enum i40e_status_code status;
5055 bool cmd_param_flag = false;
5058 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5059 case i40e_aqc_opc_configure_vsi_tc_bw:
5060 case i40e_aqc_opc_enable_switching_comp_ets:
5061 case i40e_aqc_opc_modify_switching_comp_ets:
5062 case i40e_aqc_opc_disable_switching_comp_ets:
5063 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5064 case i40e_aqc_opc_configure_switching_comp_bw_config:
5065 cmd_param_flag = true;
5067 case i40e_aqc_opc_query_vsi_bw_config:
5068 case i40e_aqc_opc_query_vsi_ets_sla_config:
5069 case i40e_aqc_opc_query_switching_comp_ets_config:
5070 case i40e_aqc_opc_query_port_ets_config:
5071 case i40e_aqc_opc_query_switching_comp_bw_config:
5072 cmd_param_flag = false;
5075 return I40E_ERR_PARAM;
5078 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5080 /* Indirect command */
5081 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5083 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5084 if (buff_size > I40E_AQ_LARGE_BUF)
5085 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5087 desc.datalen = CPU_TO_LE16(buff_size);
5089 cmd->vsi_seid = CPU_TO_LE16(seid);
5091 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5097 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5098 * @hw: pointer to the hw struct
5100 * @credit: BW limit credits (0 = disabled)
5101 * @max_credit: Max BW limit credits
5102 * @cmd_details: pointer to command details structure or NULL
5104 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5105 u16 seid, u16 credit, u8 max_credit,
5106 struct i40e_asq_cmd_details *cmd_details)
5108 struct i40e_aq_desc desc;
5109 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5110 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5111 enum i40e_status_code status;
5113 i40e_fill_default_direct_cmd_desc(&desc,
5114 i40e_aqc_opc_configure_vsi_bw_limit);
5116 cmd->vsi_seid = CPU_TO_LE16(seid);
5117 cmd->credit = CPU_TO_LE16(credit);
5118 cmd->max_credit = max_credit;
5120 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5126 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5127 * @hw: pointer to the hw struct
5128 * @seid: switching component seid
5129 * @credit: BW limit credits (0 = disabled)
5130 * @max_bw: Max BW limit credits
5131 * @cmd_details: pointer to command details structure or NULL
5133 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5134 u16 seid, u16 credit, u8 max_bw,
5135 struct i40e_asq_cmd_details *cmd_details)
5137 struct i40e_aq_desc desc;
5138 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5139 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5140 enum i40e_status_code status;
5142 i40e_fill_default_direct_cmd_desc(&desc,
5143 i40e_aqc_opc_configure_switching_comp_bw_limit);
5145 cmd->seid = CPU_TO_LE16(seid);
5146 cmd->credit = CPU_TO_LE16(credit);
5147 cmd->max_bw = max_bw;
5149 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5155 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5156 * @hw: pointer to the hw struct
5158 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5159 * @cmd_details: pointer to command details structure or NULL
5161 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5163 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5164 struct i40e_asq_cmd_details *cmd_details)
5166 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5167 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5172 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5173 * @hw: pointer to the hw struct
5175 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5176 * @cmd_details: pointer to command details structure or NULL
5178 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5180 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5181 struct i40e_asq_cmd_details *cmd_details)
5183 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5184 i40e_aqc_opc_configure_vsi_tc_bw,
5189 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5190 * @hw: pointer to the hw struct
5191 * @seid: seid of the switching component connected to Physical Port
5192 * @ets_data: Buffer holding ETS parameters
5193 * @cmd_details: pointer to command details structure or NULL
5195 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5197 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5198 enum i40e_admin_queue_opc opcode,
5199 struct i40e_asq_cmd_details *cmd_details)
5201 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5202 sizeof(*ets_data), opcode, cmd_details);
5206 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5207 * @hw: pointer to the hw struct
5208 * @seid: seid of the switching component
5209 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5210 * @cmd_details: pointer to command details structure or NULL
5212 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5214 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5215 struct i40e_asq_cmd_details *cmd_details)
5217 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5218 i40e_aqc_opc_configure_switching_comp_bw_config,
5223 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5224 * @hw: pointer to the hw struct
5225 * @seid: seid of the switching component
5226 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5227 * @cmd_details: pointer to command details structure or NULL
5229 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5230 struct i40e_hw *hw, u16 seid,
5231 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5232 struct i40e_asq_cmd_details *cmd_details)
5234 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5235 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5240 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5241 * @hw: pointer to the hw struct
5242 * @seid: seid of the VSI
5243 * @bw_data: Buffer to hold VSI BW configuration
5244 * @cmd_details: pointer to command details structure or NULL
5246 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5248 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5249 struct i40e_asq_cmd_details *cmd_details)
5251 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5252 i40e_aqc_opc_query_vsi_bw_config,
5257 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5258 * @hw: pointer to the hw struct
5259 * @seid: seid of the VSI
5260 * @bw_data: Buffer to hold VSI BW configuration per TC
5261 * @cmd_details: pointer to command details structure or NULL
5263 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5265 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5266 struct i40e_asq_cmd_details *cmd_details)
5268 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5269 i40e_aqc_opc_query_vsi_ets_sla_config,
5274 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5275 * @hw: pointer to the hw struct
5276 * @seid: seid of the switching component
5277 * @bw_data: Buffer to hold switching component's per TC BW config
5278 * @cmd_details: pointer to command details structure or NULL
5280 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5282 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5283 struct i40e_asq_cmd_details *cmd_details)
5285 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5286 i40e_aqc_opc_query_switching_comp_ets_config,
5291 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5292 * @hw: pointer to the hw struct
5293 * @seid: seid of the VSI or switching component connected to Physical Port
5294 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5295 * @cmd_details: pointer to command details structure or NULL
5297 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5299 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5300 struct i40e_asq_cmd_details *cmd_details)
5302 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5303 i40e_aqc_opc_query_port_ets_config,
5308 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5309 * @hw: pointer to the hw struct
5310 * @seid: seid of the switching component
5311 * @bw_data: Buffer to hold switching component's BW configuration
5312 * @cmd_details: pointer to command details structure or NULL
5314 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5316 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5317 struct i40e_asq_cmd_details *cmd_details)
5319 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5320 i40e_aqc_opc_query_switching_comp_bw_config,
5325 * i40e_validate_filter_settings
5326 * @hw: pointer to the hardware structure
5327 * @settings: Filter control settings
5329 * Check and validate the filter control settings passed.
5330 * The function checks for the valid filter/context sizes being
5331 * passed for FCoE and PE.
5333 * Returns I40E_SUCCESS if the values passed are valid and within
5334 * range else returns an error.
5336 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5337 struct i40e_filter_control_settings *settings)
5339 u32 fcoe_cntx_size, fcoe_filt_size;
5340 u32 pe_cntx_size, pe_filt_size;
5345 /* Validate FCoE settings passed */
5346 switch (settings->fcoe_filt_num) {
5347 case I40E_HASH_FILTER_SIZE_1K:
5348 case I40E_HASH_FILTER_SIZE_2K:
5349 case I40E_HASH_FILTER_SIZE_4K:
5350 case I40E_HASH_FILTER_SIZE_8K:
5351 case I40E_HASH_FILTER_SIZE_16K:
5352 case I40E_HASH_FILTER_SIZE_32K:
5353 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5354 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5357 return I40E_ERR_PARAM;
5360 switch (settings->fcoe_cntx_num) {
5361 case I40E_DMA_CNTX_SIZE_512:
5362 case I40E_DMA_CNTX_SIZE_1K:
5363 case I40E_DMA_CNTX_SIZE_2K:
5364 case I40E_DMA_CNTX_SIZE_4K:
5365 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5366 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5369 return I40E_ERR_PARAM;
5372 /* Validate PE settings passed */
5373 switch (settings->pe_filt_num) {
5374 case I40E_HASH_FILTER_SIZE_1K:
5375 case I40E_HASH_FILTER_SIZE_2K:
5376 case I40E_HASH_FILTER_SIZE_4K:
5377 case I40E_HASH_FILTER_SIZE_8K:
5378 case I40E_HASH_FILTER_SIZE_16K:
5379 case I40E_HASH_FILTER_SIZE_32K:
5380 case I40E_HASH_FILTER_SIZE_64K:
5381 case I40E_HASH_FILTER_SIZE_128K:
5382 case I40E_HASH_FILTER_SIZE_256K:
5383 case I40E_HASH_FILTER_SIZE_512K:
5384 case I40E_HASH_FILTER_SIZE_1M:
5385 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5386 pe_filt_size <<= (u32)settings->pe_filt_num;
5389 return I40E_ERR_PARAM;
5392 switch (settings->pe_cntx_num) {
5393 case I40E_DMA_CNTX_SIZE_512:
5394 case I40E_DMA_CNTX_SIZE_1K:
5395 case I40E_DMA_CNTX_SIZE_2K:
5396 case I40E_DMA_CNTX_SIZE_4K:
5397 case I40E_DMA_CNTX_SIZE_8K:
5398 case I40E_DMA_CNTX_SIZE_16K:
5399 case I40E_DMA_CNTX_SIZE_32K:
5400 case I40E_DMA_CNTX_SIZE_64K:
5401 case I40E_DMA_CNTX_SIZE_128K:
5402 case I40E_DMA_CNTX_SIZE_256K:
5403 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5404 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5407 return I40E_ERR_PARAM;
5410 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5411 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5412 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5413 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5414 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5415 return I40E_ERR_INVALID_SIZE;
5417 return I40E_SUCCESS;
5421 * i40e_set_filter_control
5422 * @hw: pointer to the hardware structure
5423 * @settings: Filter control settings
5425 * Set the Queue Filters for PE/FCoE and enable filters required
5426 * for a single PF. It is expected that these settings are programmed
5427 * at the driver initialization time.
5429 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5430 struct i40e_filter_control_settings *settings)
5432 enum i40e_status_code ret = I40E_SUCCESS;
5433 u32 hash_lut_size = 0;
5437 return I40E_ERR_PARAM;
5439 /* Validate the input settings */
5440 ret = i40e_validate_filter_settings(hw, settings);
5444 /* Read the PF Queue Filter control register */
5445 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5447 /* Program required PE hash buckets for the PF */
5448 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5449 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5450 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5451 /* Program required PE contexts for the PF */
5452 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5453 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5454 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5456 /* Program required FCoE hash buckets for the PF */
5457 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5458 val |= ((u32)settings->fcoe_filt_num <<
5459 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5460 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5461 /* Program required FCoE DDP contexts for the PF */
5462 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5463 val |= ((u32)settings->fcoe_cntx_num <<
5464 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5465 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5467 /* Program Hash LUT size for the PF */
5468 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5469 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5471 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5472 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5474 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5475 if (settings->enable_fdir)
5476 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5477 if (settings->enable_ethtype)
5478 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5479 if (settings->enable_macvlan)
5480 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5482 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5484 return I40E_SUCCESS;
5488 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5489 * @hw: pointer to the hw struct
5490 * @mac_addr: MAC address to use in the filter
5491 * @ethtype: Ethertype to use in the filter
5492 * @flags: Flags that needs to be applied to the filter
5493 * @vsi_seid: seid of the control VSI
5494 * @queue: VSI queue number to send the packet to
5495 * @is_add: Add control packet filter if True else remove
5496 * @stats: Structure to hold information on control filter counts
5497 * @cmd_details: pointer to command details structure or NULL
5499 * This command will Add or Remove control packet filter for a control VSI.
5500 * In return it will update the total number of perfect filter count in
5503 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5504 u8 *mac_addr, u16 ethtype, u16 flags,
5505 u16 vsi_seid, u16 queue, bool is_add,
5506 struct i40e_control_filter_stats *stats,
5507 struct i40e_asq_cmd_details *cmd_details)
5509 struct i40e_aq_desc desc;
5510 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5511 (struct i40e_aqc_add_remove_control_packet_filter *)
5513 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5514 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5516 enum i40e_status_code status;
5519 return I40E_ERR_PARAM;
5522 i40e_fill_default_direct_cmd_desc(&desc,
5523 i40e_aqc_opc_add_control_packet_filter);
5524 cmd->queue = CPU_TO_LE16(queue);
5526 i40e_fill_default_direct_cmd_desc(&desc,
5527 i40e_aqc_opc_remove_control_packet_filter);
5531 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5532 I40E_NONDMA_TO_NONDMA);
5534 cmd->etype = CPU_TO_LE16(ethtype);
5535 cmd->flags = CPU_TO_LE16(flags);
5536 cmd->seid = CPU_TO_LE16(vsi_seid);
5538 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5540 if (!status && stats) {
5541 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5542 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5543 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5544 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5551 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5552 * @hw: pointer to the hw struct
5553 * @seid: VSI seid to add ethertype filter from
5555 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5556 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5559 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5560 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5561 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5562 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5563 enum i40e_status_code status;
5565 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5566 seid, 0, true, NULL,
5569 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5573 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5574 * @filters: list of cloud filters
5575 * @filter_count: length of list
5577 * There's an issue in the device where the Geneve VNI layout needs
5578 * to be shifted 1 byte over from the VxLAN VNI
5580 STATIC void i40e_fix_up_geneve_vni(
5581 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5584 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5587 for (i = 0; i < filter_count; i++) {
5591 tnl_type = (LE16_TO_CPU(f[i].flags) &
5592 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5593 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5594 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5595 ti = LE32_TO_CPU(f[i].tenant_id);
5596 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5602 * i40e_aq_add_cloud_filters
5603 * @hw: pointer to the hardware structure
5604 * @seid: VSI seid to add cloud filters from
5605 * @filters: Buffer which contains the filters to be added
5606 * @filter_count: number of filters contained in the buffer
5608 * Set the cloud filters for a given VSI. The contents of the
5609 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5610 * in by the caller of the function.
5613 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5615 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5618 struct i40e_aq_desc desc;
5619 struct i40e_aqc_add_remove_cloud_filters *cmd =
5620 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5621 enum i40e_status_code status;
5624 i40e_fill_default_direct_cmd_desc(&desc,
5625 i40e_aqc_opc_add_cloud_filters);
5627 buff_len = filter_count * sizeof(*filters);
5628 desc.datalen = CPU_TO_LE16(buff_len);
5629 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5630 cmd->num_filters = filter_count;
5631 cmd->seid = CPU_TO_LE16(seid);
5633 i40e_fix_up_geneve_vni(filters, filter_count);
5635 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5641 * i40e_aq_add_cloud_filters_big_buffer
5642 * @hw: pointer to the hardware structure
5643 * @seid: VSI seid to add cloud filters from
5644 * @filters: Buffer which contains the filters in big buffer to be added
5645 * @filter_count: number of filters contained in the buffer
5647 * Set the cloud filters for a given VSI. The contents of the
5648 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5652 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5654 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5657 struct i40e_aq_desc desc;
5658 struct i40e_aqc_add_remove_cloud_filters *cmd =
5659 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5660 enum i40e_status_code status;
5664 i40e_fill_default_direct_cmd_desc(&desc,
5665 i40e_aqc_opc_add_cloud_filters);
5667 buff_len = filter_count * sizeof(*filters);
5668 desc.datalen = CPU_TO_LE16(buff_len);
5669 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5670 cmd->num_filters = filter_count;
5671 cmd->seid = CPU_TO_LE16(seid);
5672 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5674 /* adjust Geneve VNI for HW issue */
5675 for (i = 0; i < filter_count; i++) {
5679 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5680 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5681 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5682 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5683 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5684 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5688 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5694 * i40e_aq_remove_cloud_filters
5695 * @hw: pointer to the hardware structure
5696 * @seid: VSI seid to remove cloud filters from
5697 * @filters: Buffer which contains the filters to be removed
5698 * @filter_count: number of filters contained in the buffer
5700 * Remove the cloud filters for a given VSI. The contents of the
5701 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5702 * in by the caller of the function.
5705 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5707 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5710 struct i40e_aq_desc desc;
5711 struct i40e_aqc_add_remove_cloud_filters *cmd =
5712 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5713 enum i40e_status_code status;
5716 i40e_fill_default_direct_cmd_desc(&desc,
5717 i40e_aqc_opc_remove_cloud_filters);
5719 buff_len = filter_count * sizeof(*filters);
5720 desc.datalen = CPU_TO_LE16(buff_len);
5721 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5722 cmd->num_filters = filter_count;
5723 cmd->seid = CPU_TO_LE16(seid);
5725 i40e_fix_up_geneve_vni(filters, filter_count);
5727 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5733 * i40e_aq_remove_cloud_filters_big_buffer
5734 * @hw: pointer to the hardware structure
5735 * @seid: VSI seid to remove cloud filters from
5736 * @filters: Buffer which contains the filters in big buffer to be removed
5737 * @filter_count: number of filters contained in the buffer
5739 * Remove the cloud filters for a given VSI. The contents of the
5740 * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5744 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5747 struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5750 struct i40e_aq_desc desc;
5751 struct i40e_aqc_add_remove_cloud_filters *cmd =
5752 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5753 enum i40e_status_code status;
5757 i40e_fill_default_direct_cmd_desc(&desc,
5758 i40e_aqc_opc_remove_cloud_filters);
5760 buff_len = filter_count * sizeof(*filters);
5761 desc.datalen = CPU_TO_LE16(buff_len);
5762 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5763 cmd->num_filters = filter_count;
5764 cmd->seid = CPU_TO_LE16(seid);
5765 cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5767 /* adjust Geneve VNI for HW issue */
5768 for (i = 0; i < filter_count; i++) {
5772 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5773 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5774 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5775 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5776 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5777 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5781 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5787 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5788 * @hw: pointer to the hw struct
5789 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5790 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5794 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5795 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5796 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5798 struct i40e_aq_desc desc;
5799 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5800 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5801 enum i40e_status_code status = I40E_SUCCESS;
5804 i40e_fill_default_direct_cmd_desc(&desc,
5805 i40e_aqc_opc_replace_cloud_filters);
5807 desc.datalen = CPU_TO_LE16(32);
5808 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5809 cmd->old_filter_type = filters->old_filter_type;
5810 cmd->new_filter_type = filters->new_filter_type;
5811 cmd->valid_flags = filters->valid_flags;
5812 cmd->tr_bit = filters->tr_bit;
5814 status = i40e_asq_send_command(hw, &desc, cmd_buf,
5815 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
5817 /* for get cloud filters command */
5818 for (i = 0; i < 32; i += 4) {
5819 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5820 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5821 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5822 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5830 * i40e_aq_alternate_write
5831 * @hw: pointer to the hardware structure
5832 * @reg_addr0: address of first dword to be read
5833 * @reg_val0: value to be written under 'reg_addr0'
5834 * @reg_addr1: address of second dword to be read
5835 * @reg_val1: value to be written under 'reg_addr1'
5837 * Write one or two dwords to alternate structure. Fields are indicated
5838 * by 'reg_addr0' and 'reg_addr1' register numbers.
5841 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5842 u32 reg_addr0, u32 reg_val0,
5843 u32 reg_addr1, u32 reg_val1)
5845 struct i40e_aq_desc desc;
5846 struct i40e_aqc_alternate_write *cmd_resp =
5847 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5848 enum i40e_status_code status;
5850 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5851 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5852 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5853 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5854 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5856 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5862 * i40e_aq_alternate_write_indirect
5863 * @hw: pointer to the hardware structure
5864 * @addr: address of a first register to be modified
5865 * @dw_count: number of alternate structure fields to write
5866 * @buffer: pointer to the command buffer
5868 * Write 'dw_count' dwords from 'buffer' to alternate structure
5869 * starting at 'addr'.
5872 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5873 u32 addr, u32 dw_count, void *buffer)
5875 struct i40e_aq_desc desc;
5876 struct i40e_aqc_alternate_ind_write *cmd_resp =
5877 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5878 enum i40e_status_code status;
5881 return I40E_ERR_PARAM;
5883 /* Indirect command */
5884 i40e_fill_default_direct_cmd_desc(&desc,
5885 i40e_aqc_opc_alternate_write_indirect);
5887 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5888 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5889 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5890 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5892 cmd_resp->address = CPU_TO_LE32(addr);
5893 cmd_resp->length = CPU_TO_LE32(dw_count);
5895 status = i40e_asq_send_command(hw, &desc, buffer,
5896 I40E_LO_DWORD(4*dw_count), NULL);
5902 * i40e_aq_alternate_read
5903 * @hw: pointer to the hardware structure
5904 * @reg_addr0: address of first dword to be read
5905 * @reg_val0: pointer for data read from 'reg_addr0'
5906 * @reg_addr1: address of second dword to be read
5907 * @reg_val1: pointer for data read from 'reg_addr1'
5909 * Read one or two dwords from alternate structure. Fields are indicated
5910 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5911 * is not passed then only register at 'reg_addr0' is read.
5914 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5915 u32 reg_addr0, u32 *reg_val0,
5916 u32 reg_addr1, u32 *reg_val1)
5918 struct i40e_aq_desc desc;
5919 struct i40e_aqc_alternate_write *cmd_resp =
5920 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5921 enum i40e_status_code status;
5923 if (reg_val0 == NULL)
5924 return I40E_ERR_PARAM;
5926 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5927 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5928 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5930 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5932 if (status == I40E_SUCCESS) {
5933 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5935 if (reg_val1 != NULL)
5936 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5943 * i40e_aq_alternate_read_indirect
5944 * @hw: pointer to the hardware structure
5945 * @addr: address of the alternate structure field
5946 * @dw_count: number of alternate structure fields to read
5947 * @buffer: pointer to the command buffer
5949 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5950 * place them in 'buffer'. The buffer should be allocated by caller.
5953 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5954 u32 addr, u32 dw_count, void *buffer)
5956 struct i40e_aq_desc desc;
5957 struct i40e_aqc_alternate_ind_write *cmd_resp =
5958 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5959 enum i40e_status_code status;
5962 return I40E_ERR_PARAM;
5964 /* Indirect command */
5965 i40e_fill_default_direct_cmd_desc(&desc,
5966 i40e_aqc_opc_alternate_read_indirect);
5968 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5969 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5970 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5971 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5973 cmd_resp->address = CPU_TO_LE32(addr);
5974 cmd_resp->length = CPU_TO_LE32(dw_count);
5976 status = i40e_asq_send_command(hw, &desc, buffer,
5977 I40E_LO_DWORD(4*dw_count), NULL);
5983 * i40e_aq_alternate_clear
5984 * @hw: pointer to the HW structure.
5986 * Clear the alternate structures of the port from which the function
5990 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5992 struct i40e_aq_desc desc;
5993 enum i40e_status_code status;
5995 i40e_fill_default_direct_cmd_desc(&desc,
5996 i40e_aqc_opc_alternate_clear_port);
5998 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6004 * i40e_aq_alternate_write_done
6005 * @hw: pointer to the HW structure.
6006 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6007 * @reset_needed: indicates the SW should trigger GLOBAL reset
6009 * Indicates to the FW that alternate structures have been changed.
6012 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6013 u8 bios_mode, bool *reset_needed)
6015 struct i40e_aq_desc desc;
6016 struct i40e_aqc_alternate_write_done *cmd =
6017 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6018 enum i40e_status_code status;
6020 if (reset_needed == NULL)
6021 return I40E_ERR_PARAM;
6023 i40e_fill_default_direct_cmd_desc(&desc,
6024 i40e_aqc_opc_alternate_write_done);
6026 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6028 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6029 if (!status && reset_needed)
6030 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6031 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6037 * i40e_aq_set_oem_mode
6038 * @hw: pointer to the HW structure.
6039 * @oem_mode: the OEM mode to be used
6041 * Sets the device to a specific operating mode. Currently the only supported
6042 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6045 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6048 struct i40e_aq_desc desc;
6049 struct i40e_aqc_alternate_write_done *cmd =
6050 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6051 enum i40e_status_code status;
6053 i40e_fill_default_direct_cmd_desc(&desc,
6054 i40e_aqc_opc_alternate_set_mode);
6056 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6058 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6064 * i40e_aq_resume_port_tx
6065 * @hw: pointer to the hardware structure
6066 * @cmd_details: pointer to command details structure or NULL
6068 * Resume port's Tx traffic
6070 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6071 struct i40e_asq_cmd_details *cmd_details)
6073 struct i40e_aq_desc desc;
6074 enum i40e_status_code status;
6076 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6078 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6084 * i40e_set_pci_config_data - store PCI bus info
6085 * @hw: pointer to hardware structure
6086 * @link_status: the link status word from PCI config space
6088 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6090 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6092 hw->bus.type = i40e_bus_type_pci_express;
6094 switch (link_status & I40E_PCI_LINK_WIDTH) {
6095 case I40E_PCI_LINK_WIDTH_1:
6096 hw->bus.width = i40e_bus_width_pcie_x1;
6098 case I40E_PCI_LINK_WIDTH_2:
6099 hw->bus.width = i40e_bus_width_pcie_x2;
6101 case I40E_PCI_LINK_WIDTH_4:
6102 hw->bus.width = i40e_bus_width_pcie_x4;
6104 case I40E_PCI_LINK_WIDTH_8:
6105 hw->bus.width = i40e_bus_width_pcie_x8;
6108 hw->bus.width = i40e_bus_width_unknown;
6112 switch (link_status & I40E_PCI_LINK_SPEED) {
6113 case I40E_PCI_LINK_SPEED_2500:
6114 hw->bus.speed = i40e_bus_speed_2500;
6116 case I40E_PCI_LINK_SPEED_5000:
6117 hw->bus.speed = i40e_bus_speed_5000;
6119 case I40E_PCI_LINK_SPEED_8000:
6120 hw->bus.speed = i40e_bus_speed_8000;
6123 hw->bus.speed = i40e_bus_speed_unknown;
6129 * i40e_aq_debug_dump
6130 * @hw: pointer to the hardware structure
6131 * @cluster_id: specific cluster to dump
6132 * @table_id: table id within cluster
6133 * @start_index: index of line in the block to read
6134 * @buff_size: dump buffer size
6135 * @buff: dump buffer
6136 * @ret_buff_size: actual buffer size returned
6137 * @ret_next_table: next block to read
6138 * @ret_next_index: next index to read
6140 * Dump internal FW/HW data for debug purposes.
6143 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6144 u8 table_id, u32 start_index, u16 buff_size,
6145 void *buff, u16 *ret_buff_size,
6146 u8 *ret_next_table, u32 *ret_next_index,
6147 struct i40e_asq_cmd_details *cmd_details)
6149 struct i40e_aq_desc desc;
6150 struct i40e_aqc_debug_dump_internals *cmd =
6151 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6152 struct i40e_aqc_debug_dump_internals *resp =
6153 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6154 enum i40e_status_code status;
6156 if (buff_size == 0 || !buff)
6157 return I40E_ERR_PARAM;
6159 i40e_fill_default_direct_cmd_desc(&desc,
6160 i40e_aqc_opc_debug_dump_internals);
6161 /* Indirect Command */
6162 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6163 if (buff_size > I40E_AQ_LARGE_BUF)
6164 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6166 cmd->cluster_id = cluster_id;
6167 cmd->table_id = table_id;
6168 cmd->idx = CPU_TO_LE32(start_index);
6170 desc.datalen = CPU_TO_LE16(buff_size);
6172 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6174 if (ret_buff_size != NULL)
6175 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6176 if (ret_next_table != NULL)
6177 *ret_next_table = resp->table_id;
6178 if (ret_next_index != NULL)
6179 *ret_next_index = LE32_TO_CPU(resp->idx);
6186 * i40e_read_bw_from_alt_ram
6187 * @hw: pointer to the hardware structure
6188 * @max_bw: pointer for max_bw read
6189 * @min_bw: pointer for min_bw read
6190 * @min_valid: pointer for bool that is true if min_bw is a valid value
6191 * @max_valid: pointer for bool that is true if max_bw is a valid value
6193 * Read bw from the alternate ram for the given pf
6195 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6196 u32 *max_bw, u32 *min_bw,
6197 bool *min_valid, bool *max_valid)
6199 enum i40e_status_code status;
6200 u32 max_bw_addr, min_bw_addr;
6202 /* Calculate the address of the min/max bw registers */
6203 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6204 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6205 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6206 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6207 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6208 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6210 /* Read the bandwidths from alt ram */
6211 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6212 min_bw_addr, min_bw);
6214 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6219 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6228 * i40e_aq_configure_partition_bw
6229 * @hw: pointer to the hardware structure
6230 * @bw_data: Buffer holding valid pfs and bw limits
6231 * @cmd_details: pointer to command details
6233 * Configure partitions guaranteed/max bw
6235 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6236 struct i40e_aqc_configure_partition_bw_data *bw_data,
6237 struct i40e_asq_cmd_details *cmd_details)
6239 enum i40e_status_code status;
6240 struct i40e_aq_desc desc;
6241 u16 bwd_size = sizeof(*bw_data);
6243 i40e_fill_default_direct_cmd_desc(&desc,
6244 i40e_aqc_opc_configure_partition_bw);
6246 /* Indirect command */
6247 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6248 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6250 desc.datalen = CPU_TO_LE16(bwd_size);
6252 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6258 * i40e_read_phy_register_clause22
6259 * @hw: pointer to the HW structure
6260 * @reg: register address in the page
6261 * @phy_adr: PHY address on MDIO interface
6262 * @value: PHY register value
6264 * Reads specified PHY register value
6266 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6267 u16 reg, u8 phy_addr, u16 *value)
6269 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6270 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6274 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6275 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6276 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6277 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6278 (I40E_GLGEN_MSCA_MDICMD_MASK);
6279 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6281 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6282 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6283 status = I40E_SUCCESS;
6286 i40e_usec_delay(10);
6291 i40e_debug(hw, I40E_DEBUG_PHY,
6292 "PHY: Can't write command to external PHY.\n");
6294 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6295 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6296 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6303 * i40e_write_phy_register_clause22
6304 * @hw: pointer to the HW structure
6305 * @reg: register address in the page
6306 * @phy_adr: PHY address on MDIO interface
6307 * @value: PHY register value
6309 * Writes specified PHY register value
6311 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6312 u16 reg, u8 phy_addr, u16 value)
6314 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6315 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6319 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6320 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6322 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6323 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6324 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6325 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6326 (I40E_GLGEN_MSCA_MDICMD_MASK);
6328 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6330 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6331 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6332 status = I40E_SUCCESS;
6335 i40e_usec_delay(10);
6343 * i40e_read_phy_register_clause45
6344 * @hw: pointer to the HW structure
6345 * @page: registers page number
6346 * @reg: register address in the page
6347 * @phy_adr: PHY address on MDIO interface
6348 * @value: PHY register value
6350 * Reads specified PHY register value
6352 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6353 u8 page, u16 reg, u8 phy_addr, u16 *value)
6355 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6358 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6360 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6361 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6362 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6363 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6364 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6365 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6366 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6367 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6369 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6370 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6371 status = I40E_SUCCESS;
6374 i40e_usec_delay(10);
6379 i40e_debug(hw, I40E_DEBUG_PHY,
6380 "PHY: Can't write command to external PHY.\n");
6384 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6385 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6386 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6387 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6388 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6389 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6390 status = I40E_ERR_TIMEOUT;
6392 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6394 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6395 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6396 status = I40E_SUCCESS;
6399 i40e_usec_delay(10);
6404 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6405 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6406 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6408 i40e_debug(hw, I40E_DEBUG_PHY,
6409 "PHY: Can't read register value from external PHY.\n");
6417 * i40e_write_phy_register_clause45
6418 * @hw: pointer to the HW structure
6419 * @page: registers page number
6420 * @reg: register address in the page
6421 * @phy_adr: PHY address on MDIO interface
6422 * @value: PHY register value
6424 * Writes value to specified PHY register
6426 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6427 u8 page, u16 reg, u8 phy_addr, u16 value)
6429 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6432 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6434 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6435 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6436 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6437 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6438 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6439 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6440 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6441 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6443 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6444 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6445 status = I40E_SUCCESS;
6448 i40e_usec_delay(10);
6452 i40e_debug(hw, I40E_DEBUG_PHY,
6453 "PHY: Can't write command to external PHY.\n");
6457 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6458 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6460 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6461 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6462 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6463 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6464 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6465 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6466 status = I40E_ERR_TIMEOUT;
6468 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6470 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6471 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6472 status = I40E_SUCCESS;
6475 i40e_usec_delay(10);
6484 * i40e_write_phy_register
6485 * @hw: pointer to the HW structure
6486 * @page: registers page number
6487 * @reg: register address in the page
6488 * @phy_adr: PHY address on MDIO interface
6489 * @value: PHY register value
6491 * Writes value to specified PHY register
6493 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6494 u8 page, u16 reg, u8 phy_addr, u16 value)
6496 enum i40e_status_code status;
6498 switch (hw->device_id) {
6499 case I40E_DEV_ID_1G_BASE_T_X722:
6500 status = i40e_write_phy_register_clause22(hw,
6501 reg, phy_addr, value);
6503 case I40E_DEV_ID_10G_BASE_T:
6504 case I40E_DEV_ID_10G_BASE_T4:
6505 case I40E_DEV_ID_10G_BASE_T_X722:
6506 case I40E_DEV_ID_25G_B:
6507 case I40E_DEV_ID_25G_SFP28:
6508 status = i40e_write_phy_register_clause45(hw,
6509 page, reg, phy_addr, value);
6512 status = I40E_ERR_UNKNOWN_PHY;
6520 * i40e_read_phy_register
6521 * @hw: pointer to the HW structure
6522 * @page: registers page number
6523 * @reg: register address in the page
6524 * @phy_adr: PHY address on MDIO interface
6525 * @value: PHY register value
6527 * Reads specified PHY register value
6529 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6530 u8 page, u16 reg, u8 phy_addr, u16 *value)
6532 enum i40e_status_code status;
6534 switch (hw->device_id) {
6535 case I40E_DEV_ID_1G_BASE_T_X722:
6536 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6539 case I40E_DEV_ID_10G_BASE_T:
6540 case I40E_DEV_ID_10G_BASE_T4:
6541 case I40E_DEV_ID_10G_BASE_T_X722:
6542 case I40E_DEV_ID_25G_B:
6543 case I40E_DEV_ID_25G_SFP28:
6544 status = i40e_read_phy_register_clause45(hw, page, reg,
6548 status = I40E_ERR_UNKNOWN_PHY;
6556 * i40e_get_phy_address
6557 * @hw: pointer to the HW structure
6558 * @dev_num: PHY port num that address we want
6559 * @phy_addr: Returned PHY address
6561 * Gets PHY address for current port
6563 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6565 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6566 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6568 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6572 * i40e_blink_phy_led
6573 * @hw: pointer to the HW structure
6574 * @time: time how long led will blinks in secs
6575 * @interval: gap between LED on and off in msecs
6577 * Blinks PHY link LED
6579 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6580 u32 time, u32 interval)
6582 enum i40e_status_code status = I40E_SUCCESS;
6587 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6591 i = rd32(hw, I40E_PFGEN_PORTNUM);
6592 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6593 phy_addr = i40e_get_phy_address(hw, port_num);
6595 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6597 status = i40e_read_phy_register_clause45(hw,
6598 I40E_PHY_COM_REG_PAGE,
6602 goto phy_blinking_end;
6604 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6606 status = i40e_write_phy_register_clause45(hw,
6607 I40E_PHY_COM_REG_PAGE,
6611 goto phy_blinking_end;
6616 if (time > 0 && interval > 0) {
6617 for (i = 0; i < time * 1000; i += interval) {
6618 status = i40e_read_phy_register_clause45(hw,
6619 I40E_PHY_COM_REG_PAGE,
6620 led_addr, phy_addr, &led_reg);
6622 goto restore_config;
6623 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6626 led_reg = I40E_PHY_LED_MANUAL_ON;
6627 status = i40e_write_phy_register_clause45(hw,
6628 I40E_PHY_COM_REG_PAGE,
6629 led_addr, phy_addr, led_reg);
6631 goto restore_config;
6632 i40e_msec_delay(interval);
6637 status = i40e_write_phy_register_clause45(hw,
6638 I40E_PHY_COM_REG_PAGE,
6639 led_addr, phy_addr, led_ctl);
6646 * i40e_led_get_phy - return current on/off mode
6647 * @hw: pointer to the hw struct
6648 * @led_addr: address of led register to use
6649 * @val: original value of register to use
6652 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6655 enum i40e_status_code status = I40E_SUCCESS;
6663 temp_addr = I40E_PHY_LED_PROV_REG_1;
6664 i = rd32(hw, I40E_PFGEN_PORTNUM);
6665 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6666 phy_addr = i40e_get_phy_address(hw, port_num);
6668 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6670 status = i40e_read_phy_register_clause45(hw,
6671 I40E_PHY_COM_REG_PAGE,
6672 temp_addr, phy_addr,
6677 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6678 *led_addr = temp_addr;
6687 * @hw: pointer to the HW structure
6688 * @on: true or false
6689 * @mode: original val plus bit for set or ignore
6690 * Set led's on or off when controlled by the PHY
6693 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6694 u16 led_addr, u32 mode)
6696 enum i40e_status_code status = I40E_SUCCESS;
6703 i = rd32(hw, I40E_PFGEN_PORTNUM);
6704 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6705 phy_addr = i40e_get_phy_address(hw, port_num);
6706 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6707 led_addr, phy_addr, &led_reg);
6711 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6713 status = i40e_write_phy_register_clause45(hw,
6714 I40E_PHY_COM_REG_PAGE,
6720 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6721 led_addr, phy_addr, &led_reg);
6723 goto restore_config;
6725 led_reg = I40E_PHY_LED_MANUAL_ON;
6728 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6729 led_addr, phy_addr, led_reg);
6731 goto restore_config;
6732 if (mode & I40E_PHY_LED_MODE_ORIG) {
6733 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6734 status = i40e_write_phy_register_clause45(hw,
6735 I40E_PHY_COM_REG_PAGE,
6736 led_addr, phy_addr, led_ctl);
6740 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6741 led_addr, phy_addr, led_ctl);
6744 #endif /* PF_DRIVER */
6747 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6748 * @hw: pointer to the hw struct
6749 * @reg_addr: register address
6750 * @reg_val: ptr to register value
6751 * @cmd_details: pointer to command details structure or NULL
6753 * Use the firmware to read the Rx control register,
6754 * especially useful if the Rx unit is under heavy pressure
6756 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6757 u32 reg_addr, u32 *reg_val,
6758 struct i40e_asq_cmd_details *cmd_details)
6760 struct i40e_aq_desc desc;
6761 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6762 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6763 enum i40e_status_code status;
6765 if (reg_val == NULL)
6766 return I40E_ERR_PARAM;
6768 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6770 cmd_resp->address = CPU_TO_LE32(reg_addr);
6772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6774 if (status == I40E_SUCCESS)
6775 *reg_val = LE32_TO_CPU(cmd_resp->value);
6781 * i40e_read_rx_ctl - read from an Rx control register
6782 * @hw: pointer to the hw struct
6783 * @reg_addr: register address
6785 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6787 enum i40e_status_code status = I40E_SUCCESS;
6792 use_register = (((hw->aq.api_maj_ver == 1) &&
6793 (hw->aq.api_min_ver < 5)) ||
6794 (hw->mac.type == I40E_MAC_X722));
6795 if (!use_register) {
6797 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6798 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6805 /* if the AQ access failed, try the old-fashioned way */
6806 if (status || use_register)
6807 val = rd32(hw, reg_addr);
6813 * i40e_aq_rx_ctl_write_register
6814 * @hw: pointer to the hw struct
6815 * @reg_addr: register address
6816 * @reg_val: register value
6817 * @cmd_details: pointer to command details structure or NULL
6819 * Use the firmware to write to an Rx control register,
6820 * especially useful if the Rx unit is under heavy pressure
6822 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6823 u32 reg_addr, u32 reg_val,
6824 struct i40e_asq_cmd_details *cmd_details)
6826 struct i40e_aq_desc desc;
6827 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6828 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6829 enum i40e_status_code status;
6831 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6833 cmd->address = CPU_TO_LE32(reg_addr);
6834 cmd->value = CPU_TO_LE32(reg_val);
6836 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6842 * i40e_write_rx_ctl - write to an Rx control register
6843 * @hw: pointer to the hw struct
6844 * @reg_addr: register address
6845 * @reg_val: register value
6847 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6849 enum i40e_status_code status = I40E_SUCCESS;
6853 use_register = (((hw->aq.api_maj_ver == 1) &&
6854 (hw->aq.api_min_ver < 5)) ||
6855 (hw->mac.type == I40E_MAC_X722));
6856 if (!use_register) {
6858 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6860 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6867 /* if the AQ access failed, try the old-fashioned way */
6868 if (status || use_register)
6869 wr32(hw, reg_addr, reg_val);
6873 * i40e_aq_set_phy_register
6874 * @hw: pointer to the hw struct
6875 * @phy_select: select which phy should be accessed
6876 * @dev_addr: PHY device address
6877 * @reg_addr: PHY register address
6878 * @reg_val: new register value
6879 * @cmd_details: pointer to command details structure or NULL
6881 * Write the external PHY register.
6883 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
6884 u8 phy_select, u8 dev_addr,
6885 u32 reg_addr, u32 reg_val,
6886 struct i40e_asq_cmd_details *cmd_details)
6888 struct i40e_aq_desc desc;
6889 struct i40e_aqc_phy_register_access *cmd =
6890 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6891 enum i40e_status_code status;
6893 i40e_fill_default_direct_cmd_desc(&desc,
6894 i40e_aqc_opc_set_phy_register);
6896 cmd->phy_interface = phy_select;
6897 cmd->dev_addres = dev_addr;
6898 cmd->reg_address = reg_addr;
6899 cmd->reg_value = reg_val;
6901 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6907 * i40e_aq_get_phy_register
6908 * @hw: pointer to the hw struct
6909 * @phy_select: select which phy should be accessed
6910 * @dev_addr: PHY device address
6911 * @reg_addr: PHY register address
6912 * @reg_val: read register value
6913 * @cmd_details: pointer to command details structure or NULL
6915 * Read the external PHY register.
6917 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
6918 u8 phy_select, u8 dev_addr,
6919 u32 reg_addr, u32 *reg_val,
6920 struct i40e_asq_cmd_details *cmd_details)
6922 struct i40e_aq_desc desc;
6923 struct i40e_aqc_phy_register_access *cmd =
6924 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6925 enum i40e_status_code status;
6927 i40e_fill_default_direct_cmd_desc(&desc,
6928 i40e_aqc_opc_get_phy_register);
6930 cmd->phy_interface = phy_select;
6931 cmd->dev_addres = dev_addr;
6932 cmd->reg_address = reg_addr;
6934 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6936 *reg_val = cmd->reg_value;
6944 * i40e_aq_send_msg_to_pf
6945 * @hw: pointer to the hardware structure
6946 * @v_opcode: opcodes for VF-PF communication
6947 * @v_retval: return error code
6948 * @msg: pointer to the msg buffer
6949 * @msglen: msg length
6950 * @cmd_details: pointer to command details
6952 * Send message to PF driver using admin queue. By default, this message
6953 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6954 * completion before returning.
6956 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6957 enum virtchnl_ops v_opcode,
6958 enum i40e_status_code v_retval,
6959 u8 *msg, u16 msglen,
6960 struct i40e_asq_cmd_details *cmd_details)
6962 struct i40e_aq_desc desc;
6963 struct i40e_asq_cmd_details details;
6964 enum i40e_status_code status;
6966 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6967 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6968 desc.cookie_high = CPU_TO_LE32(v_opcode);
6969 desc.cookie_low = CPU_TO_LE32(v_retval);
6971 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6972 | I40E_AQ_FLAG_RD));
6973 if (msglen > I40E_AQ_LARGE_BUF)
6974 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6975 desc.datalen = CPU_TO_LE16(msglen);
6978 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6979 details.async = true;
6980 cmd_details = &details;
6982 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6983 msglen, cmd_details);
6988 * i40e_vf_parse_hw_config
6989 * @hw: pointer to the hardware structure
6990 * @msg: pointer to the virtual channel VF resource structure
6992 * Given a VF resource message from the PF, populate the hw struct
6993 * with appropriate information.
6995 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6996 struct virtchnl_vf_resource *msg)
6998 struct virtchnl_vsi_resource *vsi_res;
7001 vsi_res = &msg->vsi_res[0];
7003 hw->dev_caps.num_vsis = msg->num_vsis;
7004 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7005 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7006 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7007 hw->dev_caps.dcb = msg->vf_offload_flags &
7008 VIRTCHNL_VF_OFFLOAD_L2;
7009 hw->dev_caps.iwarp = (msg->vf_offload_flags &
7010 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7011 for (i = 0; i < msg->num_vsis; i++) {
7012 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7013 i40e_memcpy(hw->mac.perm_addr,
7014 vsi_res->default_mac_addr,
7016 I40E_NONDMA_TO_NONDMA);
7017 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7019 I40E_NONDMA_TO_NONDMA);
7027 * @hw: pointer to the hardware structure
7029 * Send a VF_RESET message to the PF. Does not wait for response from PF
7030 * as none will be forthcoming. Immediately after calling this function,
7031 * the admin queue should be shut down and (optionally) reinitialized.
7033 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7035 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7036 I40E_SUCCESS, NULL, 0, NULL);
7038 #endif /* VF_DRIVER */
7041 * i40e_aq_set_arp_proxy_config
7042 * @hw: pointer to the HW structure
7043 * @proxy_config - pointer to proxy config command table struct
7044 * @cmd_details: pointer to command details
7046 * Set ARP offload parameters from pre-populated
7047 * i40e_aqc_arp_proxy_data struct
7049 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7050 struct i40e_aqc_arp_proxy_data *proxy_config,
7051 struct i40e_asq_cmd_details *cmd_details)
7053 struct i40e_aq_desc desc;
7054 enum i40e_status_code status;
7057 return I40E_ERR_PARAM;
7059 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7061 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7062 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7063 desc.params.external.addr_high =
7064 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7065 desc.params.external.addr_low =
7066 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7067 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7069 status = i40e_asq_send_command(hw, &desc, proxy_config,
7070 sizeof(struct i40e_aqc_arp_proxy_data),
7077 * i40e_aq_opc_set_ns_proxy_table_entry
7078 * @hw: pointer to the HW structure
7079 * @ns_proxy_table_entry: pointer to NS table entry command struct
7080 * @cmd_details: pointer to command details
7082 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7083 * from pre-populated i40e_aqc_ns_proxy_data struct
7085 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7086 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7087 struct i40e_asq_cmd_details *cmd_details)
7089 struct i40e_aq_desc desc;
7090 enum i40e_status_code status;
7092 if (!ns_proxy_table_entry)
7093 return I40E_ERR_PARAM;
7095 i40e_fill_default_direct_cmd_desc(&desc,
7096 i40e_aqc_opc_set_ns_proxy_table_entry);
7098 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7099 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7100 desc.params.external.addr_high =
7101 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7102 desc.params.external.addr_low =
7103 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7104 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7106 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7107 sizeof(struct i40e_aqc_ns_proxy_data),
7114 * i40e_aq_set_clear_wol_filter
7115 * @hw: pointer to the hw struct
7116 * @filter_index: index of filter to modify (0-7)
7117 * @filter: buffer containing filter to be set
7118 * @set_filter: true to set filter, false to clear filter
7119 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7120 * if false, pass through packets may cause wake-up
7121 * @filter_valid: true if filter action is valid
7122 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7123 * @cmd_details: pointer to command details structure or NULL
7125 * Set or clear WoL filter for port attached to the PF
7127 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7129 struct i40e_aqc_set_wol_filter_data *filter,
7130 bool set_filter, bool no_wol_tco,
7131 bool filter_valid, bool no_wol_tco_valid,
7132 struct i40e_asq_cmd_details *cmd_details)
7134 struct i40e_aq_desc desc;
7135 struct i40e_aqc_set_wol_filter *cmd =
7136 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7137 enum i40e_status_code status;
7139 u16 valid_flags = 0;
7142 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7144 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7145 return I40E_ERR_PARAM;
7146 cmd->filter_index = CPU_TO_LE16(filter_index);
7150 return I40E_ERR_PARAM;
7152 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7153 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7157 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7158 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7161 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7162 if (no_wol_tco_valid)
7163 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7164 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7166 buff_len = sizeof(*filter);
7167 desc.datalen = CPU_TO_LE16(buff_len);
7169 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7170 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7172 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7173 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7175 status = i40e_asq_send_command(hw, &desc, filter,
7176 buff_len, cmd_details);
7182 * i40e_aq_get_wake_event_reason
7183 * @hw: pointer to the hw struct
7184 * @wake_reason: return value, index of matching filter
7185 * @cmd_details: pointer to command details structure or NULL
7187 * Get information for the reason of a Wake Up event
7189 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7191 struct i40e_asq_cmd_details *cmd_details)
7193 struct i40e_aq_desc desc;
7194 struct i40e_aqc_get_wake_reason_completion *resp =
7195 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7196 enum i40e_status_code status;
7198 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7200 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7202 if (status == I40E_SUCCESS)
7203 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7209 * i40e_aq_clear_all_wol_filters
7210 * @hw: pointer to the hw struct
7211 * @cmd_details: pointer to command details structure or NULL
7213 * Get information for the reason of a Wake Up event
7215 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7216 struct i40e_asq_cmd_details *cmd_details)
7218 struct i40e_aq_desc desc;
7219 enum i40e_status_code status;
7221 i40e_fill_default_direct_cmd_desc(&desc,
7222 i40e_aqc_opc_clear_all_wol_filters);
7224 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7231 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7232 * @hw: pointer to the hw struct
7233 * @buff: command buffer (size in bytes = buff_size)
7234 * @buff_size: buffer size in bytes
7235 * @track_id: package tracking id
7236 * @error_offset: returns error offset
7237 * @error_info: returns error information
7238 * @cmd_details: pointer to command details structure or NULL
7241 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7242 u16 buff_size, u32 track_id,
7243 u32 *error_offset, u32 *error_info,
7244 struct i40e_asq_cmd_details *cmd_details)
7246 struct i40e_aq_desc desc;
7247 struct i40e_aqc_write_personalization_profile *cmd =
7248 (struct i40e_aqc_write_personalization_profile *)
7250 struct i40e_aqc_write_ddp_resp *resp;
7251 enum i40e_status_code status;
7253 i40e_fill_default_direct_cmd_desc(&desc,
7254 i40e_aqc_opc_write_personalization_profile);
7256 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7257 if (buff_size > I40E_AQ_LARGE_BUF)
7258 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7260 desc.datalen = CPU_TO_LE16(buff_size);
7262 cmd->profile_track_id = CPU_TO_LE32(track_id);
7264 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7266 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7268 *error_offset = LE32_TO_CPU(resp->error_offset);
7270 *error_info = LE32_TO_CPU(resp->error_info);
7277 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7278 * @hw: pointer to the hw struct
7279 * @buff: command buffer (size in bytes = buff_size)
7280 * @buff_size: buffer size in bytes
7281 * @cmd_details: pointer to command details structure or NULL
7284 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7285 u16 buff_size, u8 flags,
7286 struct i40e_asq_cmd_details *cmd_details)
7288 struct i40e_aq_desc desc;
7289 struct i40e_aqc_get_applied_profiles *cmd =
7290 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7291 enum i40e_status_code status;
7293 i40e_fill_default_direct_cmd_desc(&desc,
7294 i40e_aqc_opc_get_personalization_profile_list);
7296 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7297 if (buff_size > I40E_AQ_LARGE_BUF)
7298 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7299 desc.datalen = CPU_TO_LE16(buff_size);
7303 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7309 * i40e_find_segment_in_package
7310 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7311 * @pkg_hdr: pointer to the package header to be searched
7313 * This function searches a package file for a particular segment type. On
7314 * success it returns a pointer to the segment header, otherwise it will
7317 struct i40e_generic_seg_header *
7318 i40e_find_segment_in_package(u32 segment_type,
7319 struct i40e_package_header *pkg_hdr)
7321 struct i40e_generic_seg_header *segment;
7324 /* Search all package segments for the requested segment type */
7325 for (i = 0; i < pkg_hdr->segment_count; i++) {
7327 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7328 pkg_hdr->segment_offset[i]);
7330 if (segment->type == segment_type)
7338 * i40e_write_profile
7339 * @hw: pointer to the hardware structure
7340 * @profile: pointer to the profile segment of the package to be downloaded
7341 * @track_id: package tracking id
7343 * Handles the download of a complete package.
7345 enum i40e_status_code
7346 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7349 enum i40e_status_code status = I40E_SUCCESS;
7350 struct i40e_section_table *sec_tbl;
7351 struct i40e_profile_section_header *sec = NULL;
7355 u32 section_size = 0;
7356 u32 offset = 0, info = 0;
7360 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0.");
7361 return I40E_NOT_SUPPORTED;
7364 dev_cnt = profile->device_table_count;
7366 for (i = 0; i < dev_cnt; i++) {
7367 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7368 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID)
7369 if (hw->device_id == (vendor_dev_id & 0xFFFF))
7373 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
7374 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7377 nvm = (u32 *)&profile->device_table[dev_cnt];
7378 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
7380 for (i = 0; i < sec_tbl->section_count; i++) {
7381 sec = (struct i40e_profile_section_header *)((u8 *)profile +
7382 sec_tbl->section_offset[i]);
7384 /* Skip 'AQ', 'note' and 'name' sections */
7385 if (sec->section.type != SECTION_TYPE_MMIO)
7388 section_size = sec->section.size +
7389 sizeof(struct i40e_profile_section_header);
7392 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7393 track_id, &offset, &info, NULL);
7395 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7396 "Failed to write profile: offset %d, info %d",
7405 * i40e_add_pinfo_to_list
7406 * @hw: pointer to the hardware structure
7407 * @profile: pointer to the profile segment of the package
7408 * @profile_info_sec: buffer for information section
7409 * @track_id: package tracking id
7411 * Register a profile to the list of loaded profiles.
7413 enum i40e_status_code
7414 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7415 struct i40e_profile_segment *profile,
7416 u8 *profile_info_sec, u32 track_id)
7418 enum i40e_status_code status = I40E_SUCCESS;
7419 struct i40e_profile_section_header *sec = NULL;
7420 struct i40e_profile_info *pinfo;
7421 u32 offset = 0, info = 0;
7423 sec = (struct i40e_profile_section_header *)profile_info_sec;
7425 sec->data_end = sizeof(struct i40e_profile_section_header) +
7426 sizeof(struct i40e_profile_info);
7427 sec->section.type = SECTION_TYPE_INFO;
7428 sec->section.offset = sizeof(struct i40e_profile_section_header);
7429 sec->section.size = sizeof(struct i40e_profile_info);
7430 pinfo = (struct i40e_profile_info *)(profile_info_sec +
7431 sec->section.offset);
7432 pinfo->track_id = track_id;
7433 pinfo->version = profile->version;
7434 pinfo->op = I40E_DDP_ADD_TRACKID;
7435 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
7437 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7438 track_id, &offset, &info, NULL);