drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u16 len = LE16_TO_CPU(aq_desc->datalen);
 334         u8 *buf = (u8 *)buffer;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         i40e_debug(hw, mask,
 341                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 342                    LE16_TO_CPU(aq_desc->opcode),
 343                    LE16_TO_CPU(aq_desc->flags),
 344                    LE16_TO_CPU(aq_desc->datalen),
 345                    LE16_TO_CPU(aq_desc->retval));
 346         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 347                    LE32_TO_CPU(aq_desc->cookie_high),
 348                    LE32_TO_CPU(aq_desc->cookie_low));
 349         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->params.internal.param0),
 351                    LE32_TO_CPU(aq_desc->params.internal.param1));
 352         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 354                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 355
 356         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 357                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 358                 if (buf_len < len)
 359                         len = buf_len;
 360                 /* write the full 16-byte chunks */
 361                 for (i = 0; i < (len - 16); i += 16)
 362                         i40e_debug(hw, mask,
 363                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 364                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 365                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 366                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 367                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 368                 /* the most we could have left is 16 bytes, pad with zeros */
 369                 if (i < len) {
 370                         char d_buf[16];
 371                         int j, i_sav;
 372
 373                         i_sav = i;
 374                         memset(d_buf, 0, sizeof(d_buf));
 375                         for (j = 0; i < len; j++, i++)
 376                                 d_buf[j] = buf[i];
 377                         i40e_debug(hw, mask,
 378                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 379                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 380                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 381                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 382                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 383                 }
 384         }
 385 }
 386
 387 /**
 388  * i40e_check_asq_alive
 389  * @hw: pointer to the hw struct
 390  *
 391  * Returns true if Queue is enabled else false.
 392  **/
 393 bool i40e_check_asq_alive(struct i40e_hw *hw)
 394 {
 395         if (hw->aq.asq.len)
 396 #ifdef PF_DRIVER
 397 #ifdef INTEGRATED_VF
 398                 if (!i40e_is_vf(hw))
 399                         return !!(rd32(hw, hw->aq.asq.len) &
 400                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 401 #else
 402                 return !!(rd32(hw, hw->aq.asq.len) &
 403                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 404 #endif /* INTEGRATED_VF */
 405 #endif /* PF_DRIVER */
 406 #ifdef VF_DRIVER
 407 #ifdef INTEGRATED_VF
 408                 if (i40e_is_vf(hw))
 409                         return !!(rd32(hw, hw->aq.asq.len) &
 410                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 411 #else
 412                 return !!(rd32(hw, hw->aq.asq.len) &
 413                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 414 #endif /* INTEGRATED_VF */
 415 #endif /* VF_DRIVER */
 416         return false;
 417 }
 418
 419 /**
 420  * i40e_aq_queue_shutdown
 421  * @hw: pointer to the hw struct
 422  * @unloading: is the driver unloading itself
 423  *
 424  * Tell the Firmware that we're shutting down the AdminQ and whether
 425  * or not the driver is unloading as well.
 426  **/
 427 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 428                                              bool unloading)
 429 {
 430         struct i40e_aq_desc desc;
 431         struct i40e_aqc_queue_shutdown *cmd =
 432                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 433         enum i40e_status_code status;
 434
 435         i40e_fill_default_direct_cmd_desc(&desc,
 436                                           i40e_aqc_opc_queue_shutdown);
 437
 438         if (unloading)
 439                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 440         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 441
 442         return status;
 443 }
 444
 445 /**
 446  * i40e_aq_get_set_rss_lut
 447  * @hw: pointer to the hardware structure
 448  * @vsi_id: vsi fw index
 449  * @pf_lut: for PF table set true, for VSI table set false
 450  * @lut: pointer to the lut buffer provided by the caller
 451  * @lut_size: size of the lut buffer
 452  * @set: set true to set the table, false to get the table
 453  *
 454  * Internal function to get or set RSS look up table
 455  **/
 456 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 457                                                      u16 vsi_id, bool pf_lut,
 458                                                      u8 *lut, u16 lut_size,
 459                                                      bool set)
 460 {
 461         enum i40e_status_code status;
 462         struct i40e_aq_desc desc;
 463         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 464                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 465
 466         if (set)
 467                 i40e_fill_default_direct_cmd_desc(&desc,
 468                                                   i40e_aqc_opc_set_rss_lut);
 469         else
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_get_rss_lut);
 472
 473         /* Indirect command */
 474         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 475         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 476
 477         cmd_resp->vsi_id =
 478                         CPU_TO_LE16((u16)((vsi_id <<
 479                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 480                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 481         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 482
 483         if (pf_lut)
 484                 cmd_resp->flags |= CPU_TO_LE16((u16)
 485                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 486                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 487                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 488         else
 489                 cmd_resp->flags |= CPU_TO_LE16((u16)
 490                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 491                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 492                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 493
 494         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 495
 496         return status;
 497 }
 498
 499 /**
 500  * i40e_aq_get_rss_lut
 501  * @hw: pointer to the hardware structure
 502  * @vsi_id: vsi fw index
 503  * @pf_lut: for PF table set true, for VSI table set false
 504  * @lut: pointer to the lut buffer provided by the caller
 505  * @lut_size: size of the lut buffer
 506  *
 507  * get the RSS lookup table, PF or VSI type
 508  **/
 509 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 510                                           bool pf_lut, u8 *lut, u16 lut_size)
 511 {
 512         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 513                                        false);
 514 }
 515
 516 /**
 517  * i40e_aq_set_rss_lut
 518  * @hw: pointer to the hardware structure
 519  * @vsi_id: vsi fw index
 520  * @pf_lut: for PF table set true, for VSI table set false
 521  * @lut: pointer to the lut buffer provided by the caller
 522  * @lut_size: size of the lut buffer
 523  *
 524  * set the RSS lookup table, PF or VSI type
 525  **/
 526 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 527                                           bool pf_lut, u8 *lut, u16 lut_size)
 528 {
 529         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 530 }
 531
 532 /**
 533  * i40e_aq_get_set_rss_key
 534  * @hw: pointer to the hw struct
 535  * @vsi_id: vsi fw index
 536  * @key: pointer to key info struct
 537  * @set: set true to set the key, false to get the key
 538  *
 539  * get the RSS key per VSI
 540  **/
 541 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 542                                       u16 vsi_id,
 543                                       struct i40e_aqc_get_set_rss_key_data *key,
 544                                       bool set)
 545 {
 546         enum i40e_status_code status;
 547         struct i40e_aq_desc desc;
 548         struct i40e_aqc_get_set_rss_key *cmd_resp =
 549                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 550         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 551
 552         if (set)
 553                 i40e_fill_default_direct_cmd_desc(&desc,
 554                                                   i40e_aqc_opc_set_rss_key);
 555         else
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_get_rss_key);
 558
 559         /* Indirect command */
 560         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 561         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 562
 563         cmd_resp->vsi_id =
 564                         CPU_TO_LE16((u16)((vsi_id <<
 565                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 566                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 567         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 568
 569         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 570
 571         return status;
 572 }
 573
 574 /**
 575  * i40e_aq_get_rss_key
 576  * @hw: pointer to the hw struct
 577  * @vsi_id: vsi fw index
 578  * @key: pointer to key info struct
 579  *
 580  **/
 581 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 582                                       u16 vsi_id,
 583                                       struct i40e_aqc_get_set_rss_key_data *key)
 584 {
 585         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 586 }
 587
 588 /**
 589  * i40e_aq_set_rss_key
 590  * @hw: pointer to the hw struct
 591  * @vsi_id: vsi fw index
 592  * @key: pointer to key info struct
 593  *
 594  * set the RSS key per VSI
 595  **/
 596 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 597                                       u16 vsi_id,
 598                                       struct i40e_aqc_get_set_rss_key_data *key)
 599 {
 600         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 601 }
 602
 603 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 604  * hardware to a bit-field that can be used by SW to more easily determine the
 605  * packet type.
 606  *
 607  * Macros are used to shorten the table lines and make this table human
 608  * readable.
 609  *
 610  * We store the PTYPE in the top byte of the bit field - this is just so that
 611  * we can check that the table doesn't have a row missing, as the index into
 612  * the table should be the PTYPE.
 613  *
 614  * Typical work flow:
 615  *
 616  * IF NOT i40e_ptype_lookup[ptype].known
 617  * THEN
 618  *      Packet is unknown
 619  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 620  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 621  * ELSE
 622  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 623  * ENDIF
 624  */
 625
 626 /* macro to make the table lines short */
 627 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 628         {       PTYPE, \
 629                 1, \
 630                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 631                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 632                 I40E_RX_PTYPE_##OUTER_FRAG, \
 633                 I40E_RX_PTYPE_TUNNEL_##T, \
 634                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 635                 I40E_RX_PTYPE_##TEF, \
 636                 I40E_RX_PTYPE_INNER_PROT_##I, \
 637                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 638
 639 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 640                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 641
 642 /* shorter macros makes the table fit but are terse */
 643 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 644 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 645 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 646
 647 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 648 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 649         /* L2 Packet types */
 650         I40E_PTT_UNUSED_ENTRY(0),
 651         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 652         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 653         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT_UNUSED_ENTRY(4),
 655         I40E_PTT_UNUSED_ENTRY(5),
 656         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 657         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(8),
 659         I40E_PTT_UNUSED_ENTRY(9),
 660         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 662         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 663         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 664         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672
 673         /* Non Tunneled IPv4 */
 674         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 677         I40E_PTT_UNUSED_ENTRY(25),
 678         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 679         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 680         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 681
 682         /* IPv4 --> IPv4 */
 683         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 684         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 685         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 686         I40E_PTT_UNUSED_ENTRY(32),
 687         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 688         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 689         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 690
 691         /* IPv4 --> IPv6 */
 692         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 693         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 694         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 695         I40E_PTT_UNUSED_ENTRY(39),
 696         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 697         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 698         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 699
 700         /* IPv4 --> GRE/NAT */
 701         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 702
 703         /* IPv4 --> GRE/NAT --> IPv4 */
 704         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 705         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 706         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 707         I40E_PTT_UNUSED_ENTRY(47),
 708         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 709         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 710         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 711
 712         /* IPv4 --> GRE/NAT --> IPv6 */
 713         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 714         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 715         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 716         I40E_PTT_UNUSED_ENTRY(54),
 717         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 718         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 719         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 720
 721         /* IPv4 --> GRE/NAT --> MAC */
 722         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 723
 724         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 725         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 726         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 727         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 728         I40E_PTT_UNUSED_ENTRY(62),
 729         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 730         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 731         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 732
 733         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 734         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 735         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 736         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 737         I40E_PTT_UNUSED_ENTRY(69),
 738         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 739         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 740         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 741
 742         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 743         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 744
 745         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 746         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 747         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 748         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 749         I40E_PTT_UNUSED_ENTRY(77),
 750         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 751         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 752         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 753
 754         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 755         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 756         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 757         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 758         I40E_PTT_UNUSED_ENTRY(84),
 759         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 760         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 761         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 762
 763         /* Non Tunneled IPv6 */
 764         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 765         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 766         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 767         I40E_PTT_UNUSED_ENTRY(91),
 768         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 769         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 770         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 771
 772         /* IPv6 --> IPv4 */
 773         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 774         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 775         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 776         I40E_PTT_UNUSED_ENTRY(98),
 777         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 778         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 779         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 780
 781         /* IPv6 --> IPv6 */
 782         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 783         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 784         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 785         I40E_PTT_UNUSED_ENTRY(105),
 786         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 787         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 788         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 789
 790         /* IPv6 --> GRE/NAT */
 791         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 792
 793         /* IPv6 --> GRE/NAT -> IPv4 */
 794         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 795         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 796         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 797         I40E_PTT_UNUSED_ENTRY(113),
 798         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 799         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 800         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 801
 802         /* IPv6 --> GRE/NAT -> IPv6 */
 803         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 804         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 805         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 806         I40E_PTT_UNUSED_ENTRY(120),
 807         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 808         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 809         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 810
 811         /* IPv6 --> GRE/NAT -> MAC */
 812         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 813
 814         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 815         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 816         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 817         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 818         I40E_PTT_UNUSED_ENTRY(128),
 819         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 820         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 821         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 822
 823         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 824         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 825         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 826         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 827         I40E_PTT_UNUSED_ENTRY(135),
 828         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 829         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 830         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 831
 832         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 833         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 834
 835         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 836         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 837         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 838         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 839         I40E_PTT_UNUSED_ENTRY(143),
 840         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 841         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 842         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 843
 844         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 845         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 846         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 847         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 848         I40E_PTT_UNUSED_ENTRY(150),
 849         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 850         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 851         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 852
 853         /* unused entries */
 854         I40E_PTT_UNUSED_ENTRY(154),
 855         I40E_PTT_UNUSED_ENTRY(155),
 856         I40E_PTT_UNUSED_ENTRY(156),
 857         I40E_PTT_UNUSED_ENTRY(157),
 858         I40E_PTT_UNUSED_ENTRY(158),
 859         I40E_PTT_UNUSED_ENTRY(159),
 860
 861         I40E_PTT_UNUSED_ENTRY(160),
 862         I40E_PTT_UNUSED_ENTRY(161),
 863         I40E_PTT_UNUSED_ENTRY(162),
 864         I40E_PTT_UNUSED_ENTRY(163),
 865         I40E_PTT_UNUSED_ENTRY(164),
 866         I40E_PTT_UNUSED_ENTRY(165),
 867         I40E_PTT_UNUSED_ENTRY(166),
 868         I40E_PTT_UNUSED_ENTRY(167),
 869         I40E_PTT_UNUSED_ENTRY(168),
 870         I40E_PTT_UNUSED_ENTRY(169),
 871
 872         I40E_PTT_UNUSED_ENTRY(170),
 873         I40E_PTT_UNUSED_ENTRY(171),
 874         I40E_PTT_UNUSED_ENTRY(172),
 875         I40E_PTT_UNUSED_ENTRY(173),
 876         I40E_PTT_UNUSED_ENTRY(174),
 877         I40E_PTT_UNUSED_ENTRY(175),
 878         I40E_PTT_UNUSED_ENTRY(176),
 879         I40E_PTT_UNUSED_ENTRY(177),
 880         I40E_PTT_UNUSED_ENTRY(178),
 881         I40E_PTT_UNUSED_ENTRY(179),
 882
 883         I40E_PTT_UNUSED_ENTRY(180),
 884         I40E_PTT_UNUSED_ENTRY(181),
 885         I40E_PTT_UNUSED_ENTRY(182),
 886         I40E_PTT_UNUSED_ENTRY(183),
 887         I40E_PTT_UNUSED_ENTRY(184),
 888         I40E_PTT_UNUSED_ENTRY(185),
 889         I40E_PTT_UNUSED_ENTRY(186),
 890         I40E_PTT_UNUSED_ENTRY(187),
 891         I40E_PTT_UNUSED_ENTRY(188),
 892         I40E_PTT_UNUSED_ENTRY(189),
 893
 894         I40E_PTT_UNUSED_ENTRY(190),
 895         I40E_PTT_UNUSED_ENTRY(191),
 896         I40E_PTT_UNUSED_ENTRY(192),
 897         I40E_PTT_UNUSED_ENTRY(193),
 898         I40E_PTT_UNUSED_ENTRY(194),
 899         I40E_PTT_UNUSED_ENTRY(195),
 900         I40E_PTT_UNUSED_ENTRY(196),
 901         I40E_PTT_UNUSED_ENTRY(197),
 902         I40E_PTT_UNUSED_ENTRY(198),
 903         I40E_PTT_UNUSED_ENTRY(199),
 904
 905         I40E_PTT_UNUSED_ENTRY(200),
 906         I40E_PTT_UNUSED_ENTRY(201),
 907         I40E_PTT_UNUSED_ENTRY(202),
 908         I40E_PTT_UNUSED_ENTRY(203),
 909         I40E_PTT_UNUSED_ENTRY(204),
 910         I40E_PTT_UNUSED_ENTRY(205),
 911         I40E_PTT_UNUSED_ENTRY(206),
 912         I40E_PTT_UNUSED_ENTRY(207),
 913         I40E_PTT_UNUSED_ENTRY(208),
 914         I40E_PTT_UNUSED_ENTRY(209),
 915
 916         I40E_PTT_UNUSED_ENTRY(210),
 917         I40E_PTT_UNUSED_ENTRY(211),
 918         I40E_PTT_UNUSED_ENTRY(212),
 919         I40E_PTT_UNUSED_ENTRY(213),
 920         I40E_PTT_UNUSED_ENTRY(214),
 921         I40E_PTT_UNUSED_ENTRY(215),
 922         I40E_PTT_UNUSED_ENTRY(216),
 923         I40E_PTT_UNUSED_ENTRY(217),
 924         I40E_PTT_UNUSED_ENTRY(218),
 925         I40E_PTT_UNUSED_ENTRY(219),
 926
 927         I40E_PTT_UNUSED_ENTRY(220),
 928         I40E_PTT_UNUSED_ENTRY(221),
 929         I40E_PTT_UNUSED_ENTRY(222),
 930         I40E_PTT_UNUSED_ENTRY(223),
 931         I40E_PTT_UNUSED_ENTRY(224),
 932         I40E_PTT_UNUSED_ENTRY(225),
 933         I40E_PTT_UNUSED_ENTRY(226),
 934         I40E_PTT_UNUSED_ENTRY(227),
 935         I40E_PTT_UNUSED_ENTRY(228),
 936         I40E_PTT_UNUSED_ENTRY(229),
 937
 938         I40E_PTT_UNUSED_ENTRY(230),
 939         I40E_PTT_UNUSED_ENTRY(231),
 940         I40E_PTT_UNUSED_ENTRY(232),
 941         I40E_PTT_UNUSED_ENTRY(233),
 942         I40E_PTT_UNUSED_ENTRY(234),
 943         I40E_PTT_UNUSED_ENTRY(235),
 944         I40E_PTT_UNUSED_ENTRY(236),
 945         I40E_PTT_UNUSED_ENTRY(237),
 946         I40E_PTT_UNUSED_ENTRY(238),
 947         I40E_PTT_UNUSED_ENTRY(239),
 948
 949         I40E_PTT_UNUSED_ENTRY(240),
 950         I40E_PTT_UNUSED_ENTRY(241),
 951         I40E_PTT_UNUSED_ENTRY(242),
 952         I40E_PTT_UNUSED_ENTRY(243),
 953         I40E_PTT_UNUSED_ENTRY(244),
 954         I40E_PTT_UNUSED_ENTRY(245),
 955         I40E_PTT_UNUSED_ENTRY(246),
 956         I40E_PTT_UNUSED_ENTRY(247),
 957         I40E_PTT_UNUSED_ENTRY(248),
 958         I40E_PTT_UNUSED_ENTRY(249),
 959
 960         I40E_PTT_UNUSED_ENTRY(250),
 961         I40E_PTT_UNUSED_ENTRY(251),
 962         I40E_PTT_UNUSED_ENTRY(252),
 963         I40E_PTT_UNUSED_ENTRY(253),
 964         I40E_PTT_UNUSED_ENTRY(254),
 965         I40E_PTT_UNUSED_ENTRY(255)
 966 };
 967
 968
 969 /**
 970  * i40e_validate_mac_addr - Validate unicast MAC address
 971  * @mac_addr: pointer to MAC address
 972  *
 973  * Tests a MAC address to ensure it is a valid Individual Address
 974  **/
 975 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 976 {
 977         enum i40e_status_code status = I40E_SUCCESS;
 978
 979         DEBUGFUNC("i40e_validate_mac_addr");
 980
 981         /* Broadcast addresses ARE multicast addresses
 982          * Make sure it is not a multicast address
 983          * Reject the zero address
 984          */
 985         if (I40E_IS_MULTICAST(mac_addr) ||
 986             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 987               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 988                 status = I40E_ERR_INVALID_MAC_ADDR;
 989
 990         return status;
 991 }
 992 #ifdef PF_DRIVER
 993
 994 /**
 995  * i40e_init_shared_code - Initialize the shared code
 996  * @hw: pointer to hardware structure
 997  *
 998  * This assigns the MAC type and PHY code and inits the NVM.
 999  * Does not touch the hardware. This function must be called prior to any
1000  * other function in the shared code. The i40e_hw structure should be
1001  * memset to 0 prior to calling this function.  The following fields in
1002  * hw structure should be filled in prior to calling this function:
1003  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1004  * subsystem_vendor_id, and revision_id
1005  **/
1006 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1007 {
1008         enum i40e_status_code status = I40E_SUCCESS;
1009         u32 port, ari, func_rid;
1010
1011         DEBUGFUNC("i40e_init_shared_code");
1012
1013         i40e_set_mac_type(hw);
1014
1015         switch (hw->mac.type) {
1016         case I40E_MAC_XL710:
1017         case I40E_MAC_X722:
1018                 break;
1019         default:
1020                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1021         }
1022
1023         hw->phy.get_link_info = true;
1024
1025         /* Determine port number and PF number*/
1026         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1027                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1028         hw->port = (u8)port;
1029         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1030                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1031         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1032         if (ari)
1033                 hw->pf_id = (u8)(func_rid & 0xff);
1034         else
1035                 hw->pf_id = (u8)(func_rid & 0x7);
1036
1037         if (hw->mac.type == I40E_MAC_X722)
1038                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1039
1040         status = i40e_init_nvm(hw);
1041         return status;
1042 }
1043
1044 /**
1045  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1046  * @hw: pointer to the hw struct
1047  * @flags: a return indicator of what addresses were added to the addr store
1048  * @addrs: the requestor's mac addr store
1049  * @cmd_details: pointer to command details structure or NULL
1050  **/
1051 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1052                                    u16 *flags,
1053                                    struct i40e_aqc_mac_address_read_data *addrs,
1054                                    struct i40e_asq_cmd_details *cmd_details)
1055 {
1056         struct i40e_aq_desc desc;
1057         struct i40e_aqc_mac_address_read *cmd_data =
1058                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1059         enum i40e_status_code status;
1060
1061         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1062         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1063
1064         status = i40e_asq_send_command(hw, &desc, addrs,
1065                                        sizeof(*addrs), cmd_details);
1066         *flags = LE16_TO_CPU(cmd_data->command_flags);
1067
1068         return status;
1069 }
1070
1071 /**
1072  * i40e_aq_mac_address_write - Change the MAC addresses
1073  * @hw: pointer to the hw struct
1074  * @flags: indicates which MAC to be written
1075  * @mac_addr: address to write
1076  * @cmd_details: pointer to command details structure or NULL
1077  **/
1078 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1079                                     u16 flags, u8 *mac_addr,
1080                                     struct i40e_asq_cmd_details *cmd_details)
1081 {
1082         struct i40e_aq_desc desc;
1083         struct i40e_aqc_mac_address_write *cmd_data =
1084                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1085         enum i40e_status_code status;
1086
1087         i40e_fill_default_direct_cmd_desc(&desc,
1088                                           i40e_aqc_opc_mac_address_write);
1089         cmd_data->command_flags = CPU_TO_LE16(flags);
1090         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1091         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1092                                         ((u32)mac_addr[3] << 16) |
1093                                         ((u32)mac_addr[4] << 8) |
1094                                         mac_addr[5]);
1095
1096         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1097
1098         return status;
1099 }
1100
1101 /**
1102  * i40e_get_mac_addr - get MAC address
1103  * @hw: pointer to the HW structure
1104  * @mac_addr: pointer to MAC address
1105  *
1106  * Reads the adapter's MAC address from register
1107  **/
1108 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1109 {
1110         struct i40e_aqc_mac_address_read_data addrs;
1111         enum i40e_status_code status;
1112         u16 flags = 0;
1113
1114         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1115
1116         if (flags & I40E_AQC_LAN_ADDR_VALID)
1117                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1118                         I40E_NONDMA_TO_NONDMA);
1119
1120         return status;
1121 }
1122
1123 /**
1124  * i40e_get_port_mac_addr - get Port MAC address
1125  * @hw: pointer to the HW structure
1126  * @mac_addr: pointer to Port MAC address
1127  *
1128  * Reads the adapter's Port MAC address
1129  **/
1130 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1131 {
1132         struct i40e_aqc_mac_address_read_data addrs;
1133         enum i40e_status_code status;
1134         u16 flags = 0;
1135
1136         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1137         if (status)
1138                 return status;
1139
1140         if (flags & I40E_AQC_PORT_ADDR_VALID)
1141                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1142                         I40E_NONDMA_TO_NONDMA);
1143         else
1144                 status = I40E_ERR_INVALID_MAC_ADDR;
1145
1146         return status;
1147 }
1148
1149 /**
1150  * i40e_pre_tx_queue_cfg - pre tx queue configure
1151  * @hw: pointer to the HW structure
1152  * @queue: target pf queue index
1153  * @enable: state change request
1154  *
1155  * Handles hw requirement to indicate intention to enable
1156  * or disable target queue.
1157  **/
1158 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1159 {
1160         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1161         u32 reg_block = 0;
1162         u32 reg_val;
1163
1164         if (abs_queue_idx >= 128) {
1165                 reg_block = abs_queue_idx / 128;
1166                 abs_queue_idx %= 128;
1167         }
1168
1169         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1170         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1171         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1172
1173         if (enable)
1174                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1175         else
1176                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1177
1178         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1179 }
1180
1181 /**
1182  * i40e_get_san_mac_addr - get SAN MAC address
1183  * @hw: pointer to the HW structure
1184  * @mac_addr: pointer to SAN MAC address
1185  *
1186  * Reads the adapter's SAN MAC address from NVM
1187  **/
1188 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1189                                             u8 *mac_addr)
1190 {
1191         struct i40e_aqc_mac_address_read_data addrs;
1192         enum i40e_status_code status;
1193         u16 flags = 0;
1194
1195         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1196         if (status)
1197                 return status;
1198
1199         if (flags & I40E_AQC_SAN_ADDR_VALID)
1200                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1201                         I40E_NONDMA_TO_NONDMA);
1202         else
1203                 status = I40E_ERR_INVALID_MAC_ADDR;
1204
1205         return status;
1206 }
1207
1208 /**
1209  *  i40e_read_pba_string - Reads part number string from EEPROM
1210  *  @hw: pointer to hardware structure
1211  *  @pba_num: stores the part number string from the EEPROM
1212  *  @pba_num_size: part number string buffer length
1213  *
1214  *  Reads the part number string from the EEPROM.
1215  **/
1216 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1217                                             u32 pba_num_size)
1218 {
1219         enum i40e_status_code status = I40E_SUCCESS;
1220         u16 pba_word = 0;
1221         u16 pba_size = 0;
1222         u16 pba_ptr = 0;
1223         u16 i = 0;
1224
1225         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1226         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1227                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1228                 return status;
1229         }
1230
1231         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1232         if (status != I40E_SUCCESS) {
1233                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1234                 return status;
1235         }
1236
1237         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1238         if (status != I40E_SUCCESS) {
1239                 DEBUGOUT("Failed to read PBA Block size.\n");
1240                 return status;
1241         }
1242
1243         /* Subtract one to get PBA word count (PBA Size word is included in
1244          * total size)
1245          */
1246         pba_size--;
1247         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1248                 DEBUGOUT("Buffer to small for PBA data.\n");
1249                 return I40E_ERR_PARAM;
1250         }
1251
1252         for (i = 0; i < pba_size; i++) {
1253                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1254                 if (status != I40E_SUCCESS) {
1255                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1256                         return status;
1257                 }
1258
1259                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1260                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1261         }
1262         pba_num[(pba_size * 2)] = '\0';
1263
1264         return status;
1265 }
1266
1267 /**
1268  * i40e_get_media_type - Gets media type
1269  * @hw: pointer to the hardware structure
1270  **/
1271 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1272 {
1273         enum i40e_media_type media;
1274
1275         switch (hw->phy.link_info.phy_type) {
1276         case I40E_PHY_TYPE_10GBASE_SR:
1277         case I40E_PHY_TYPE_10GBASE_LR:
1278         case I40E_PHY_TYPE_1000BASE_SX:
1279         case I40E_PHY_TYPE_1000BASE_LX:
1280         case I40E_PHY_TYPE_40GBASE_SR4:
1281         case I40E_PHY_TYPE_40GBASE_LR4:
1282         case I40E_PHY_TYPE_25GBASE_LR:
1283         case I40E_PHY_TYPE_25GBASE_SR:
1284                 media = I40E_MEDIA_TYPE_FIBER;
1285                 break;
1286         case I40E_PHY_TYPE_100BASE_TX:
1287         case I40E_PHY_TYPE_1000BASE_T:
1288         case I40E_PHY_TYPE_10GBASE_T:
1289                 media = I40E_MEDIA_TYPE_BASET;
1290                 break;
1291         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1292         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1293         case I40E_PHY_TYPE_10GBASE_CR1:
1294         case I40E_PHY_TYPE_40GBASE_CR4:
1295         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1296         case I40E_PHY_TYPE_40GBASE_AOC:
1297         case I40E_PHY_TYPE_10GBASE_AOC:
1298         case I40E_PHY_TYPE_25GBASE_CR:
1299         case I40E_PHY_TYPE_25GBASE_AOC:
1300         case I40E_PHY_TYPE_25GBASE_ACC:
1301                 media = I40E_MEDIA_TYPE_DA;
1302                 break;
1303         case I40E_PHY_TYPE_1000BASE_KX:
1304         case I40E_PHY_TYPE_10GBASE_KX4:
1305         case I40E_PHY_TYPE_10GBASE_KR:
1306         case I40E_PHY_TYPE_40GBASE_KR4:
1307         case I40E_PHY_TYPE_20GBASE_KR2:
1308         case I40E_PHY_TYPE_25GBASE_KR:
1309                 media = I40E_MEDIA_TYPE_BACKPLANE;
1310                 break;
1311         case I40E_PHY_TYPE_SGMII:
1312         case I40E_PHY_TYPE_XAUI:
1313         case I40E_PHY_TYPE_XFI:
1314         case I40E_PHY_TYPE_XLAUI:
1315         case I40E_PHY_TYPE_XLPPI:
1316         default:
1317                 media = I40E_MEDIA_TYPE_UNKNOWN;
1318                 break;
1319         }
1320
1321         return media;
1322 }
1323
1324 #define I40E_PF_RESET_WAIT_COUNT        200
1325 /**
1326  * i40e_pf_reset - Reset the PF
1327  * @hw: pointer to the hardware structure
1328  *
1329  * Assuming someone else has triggered a global reset,
1330  * assure the global reset is complete and then reset the PF
1331  **/
1332 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1333 {
1334         u32 cnt = 0;
1335         u32 cnt1 = 0;
1336         u32 reg = 0;
1337         u32 grst_del;
1338
1339         /* Poll for Global Reset steady state in case of recent GRST.
1340          * The grst delay value is in 100ms units, and we'll wait a
1341          * couple counts longer to be sure we don't just miss the end.
1342          */
1343         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1344                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1345                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1346
1347         grst_del = grst_del * 20;
1348
1349         for (cnt = 0; cnt < grst_del; cnt++) {
1350                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1351                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1352                         break;
1353                 i40e_msec_delay(100);
1354         }
1355         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1356                 DEBUGOUT("Global reset polling failed to complete.\n");
1357                 return I40E_ERR_RESET_FAILED;
1358         }
1359
1360         /* Now Wait for the FW to be ready */
1361         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1362                 reg = rd32(hw, I40E_GLNVM_ULD);
1363                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1364                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1365                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1366                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1367                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1368                         break;
1369                 }
1370                 i40e_msec_delay(10);
1371         }
1372         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1374                 DEBUGOUT("wait for FW Reset complete timedout\n");
1375                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1376                 return I40E_ERR_RESET_FAILED;
1377         }
1378
1379         /* If there was a Global Reset in progress when we got here,
1380          * we don't need to do the PF Reset
1381          */
1382         if (!cnt) {
1383                 reg = rd32(hw, I40E_PFGEN_CTRL);
1384                 wr32(hw, I40E_PFGEN_CTRL,
1385                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1386                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1387                         reg = rd32(hw, I40E_PFGEN_CTRL);
1388                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1389                                 break;
1390                         i40e_msec_delay(1);
1391                 }
1392                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1393                         DEBUGOUT("PF reset polling failed to complete.\n");
1394                         return I40E_ERR_RESET_FAILED;
1395                 }
1396         }
1397
1398         i40e_clear_pxe_mode(hw);
1399
1400
1401         return I40E_SUCCESS;
1402 }
1403
1404 /**
1405  * i40e_clear_hw - clear out any left over hw state
1406  * @hw: pointer to the hw struct
1407  *
1408  * Clear queues and interrupts, typically called at init time,
1409  * but after the capabilities have been found so we know how many
1410  * queues and msix vectors have been allocated.
1411  **/
1412 void i40e_clear_hw(struct i40e_hw *hw)
1413 {
1414         u32 num_queues, base_queue;
1415         u32 num_pf_int;
1416         u32 num_vf_int;
1417         u32 num_vfs;
1418         u32 i, j;
1419         u32 val;
1420         u32 eol = 0x7ff;
1421
1422         /* get number of interrupts, queues, and vfs */
1423         val = rd32(hw, I40E_GLPCI_CNF2);
1424         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1425                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1426         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1427                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1428
1429         val = rd32(hw, I40E_PFLAN_QALLOC);
1430         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1431                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1432         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1433                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1434         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1435                 num_queues = (j - base_queue) + 1;
1436         else
1437                 num_queues = 0;
1438
1439         val = rd32(hw, I40E_PF_VT_PFALLOC);
1440         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1441                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1442         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1443                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1444         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1445                 num_vfs = (j - i) + 1;
1446         else
1447                 num_vfs = 0;
1448
1449         /* stop all the interrupts */
1450         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1451         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1452         for (i = 0; i < num_pf_int - 2; i++)
1453                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1454
1455         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1456         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1457         wr32(hw, I40E_PFINT_LNKLST0, val);
1458         for (i = 0; i < num_pf_int - 2; i++)
1459                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1460         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1461         for (i = 0; i < num_vfs; i++)
1462                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1463         for (i = 0; i < num_vf_int - 2; i++)
1464                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1465
1466         /* warn the HW of the coming Tx disables */
1467         for (i = 0; i < num_queues; i++) {
1468                 u32 abs_queue_idx = base_queue + i;
1469                 u32 reg_block = 0;
1470
1471                 if (abs_queue_idx >= 128) {
1472                         reg_block = abs_queue_idx / 128;
1473                         abs_queue_idx %= 128;
1474                 }
1475
1476                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1477                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1478                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1479                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1480
1481                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1482         }
1483         i40e_usec_delay(400);
1484
1485         /* stop all the queues */
1486         for (i = 0; i < num_queues; i++) {
1487                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1488                 wr32(hw, I40E_QTX_ENA(i), 0);
1489                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1490                 wr32(hw, I40E_QRX_ENA(i), 0);
1491         }
1492
1493         /* short wait for all queue disables to settle */
1494         i40e_usec_delay(50);
1495 }
1496
1497 /**
1498  * i40e_clear_pxe_mode - clear pxe operations mode
1499  * @hw: pointer to the hw struct
1500  *
1501  * Make sure all PXE mode settings are cleared, including things
1502  * like descriptor fetch/write-back mode.
1503  **/
1504 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1505 {
1506         if (i40e_check_asq_alive(hw))
1507                 i40e_aq_clear_pxe_mode(hw, NULL);
1508 }
1509
1510 /**
1511  * i40e_led_is_mine - helper to find matching led
1512  * @hw: pointer to the hw struct
1513  * @idx: index into GPIO registers
1514  *
1515  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1516  */
1517 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1518 {
1519         u32 gpio_val = 0;
1520         u32 port;
1521
1522         if (!hw->func_caps.led[idx])
1523                 return 0;
1524
1525         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1526         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1527                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1528
1529         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1530          * if it is not our port then ignore
1531          */
1532         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1533             (port != hw->port))
1534                 return 0;
1535
1536         return gpio_val;
1537 }
1538
1539 #define I40E_COMBINED_ACTIVITY 0xA
1540 #define I40E_FILTER_ACTIVITY 0xE
1541 #define I40E_LINK_ACTIVITY 0xC
1542 #define I40E_MAC_ACTIVITY 0xD
1543 #define I40E_LED0 22
1544
1545 /**
1546  * i40e_led_get - return current on/off mode
1547  * @hw: pointer to the hw struct
1548  *
1549  * The value returned is the 'mode' field as defined in the
1550  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1551  * values are variations of possible behaviors relating to
1552  * blink, link, and wire.
1553  **/
1554 u32 i40e_led_get(struct i40e_hw *hw)
1555 {
1556         u32 current_mode = 0;
1557         u32 mode = 0;
1558         int i;
1559
1560         /* as per the documentation GPIO 22-29 are the LED
1561          * GPIO pins named LED0..LED7
1562          */
1563         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1564                 u32 gpio_val = i40e_led_is_mine(hw, i);
1565
1566                 if (!gpio_val)
1567                         continue;
1568
1569                 /* ignore gpio LED src mode entries related to the activity
1570                  *  LEDs
1571                  */
1572                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1573                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1574                 switch (current_mode) {
1575                 case I40E_COMBINED_ACTIVITY:
1576                 case I40E_FILTER_ACTIVITY:
1577                 case I40E_MAC_ACTIVITY:
1578                         continue;
1579                 default:
1580                         break;
1581                 }
1582
1583                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1584                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1585                 break;
1586         }
1587
1588         return mode;
1589 }
1590
1591 /**
1592  * i40e_led_set - set new on/off mode
1593  * @hw: pointer to the hw struct
1594  * @mode: 0=off, 0xf=on (else see manual for mode details)
1595  * @blink: true if the LED should blink when on, false if steady
1596  *
1597  * if this function is used to turn on the blink it should
1598  * be used to disable the blink when restoring the original state.
1599  **/
1600 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1601 {
1602         u32 current_mode = 0;
1603         int i;
1604
1605         if (mode & 0xfffffff0)
1606                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1607
1608         /* as per the documentation GPIO 22-29 are the LED
1609          * GPIO pins named LED0..LED7
1610          */
1611         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1612                 u32 gpio_val = i40e_led_is_mine(hw, i);
1613
1614                 if (!gpio_val)
1615                         continue;
1616
1617                 /* ignore gpio LED src mode entries related to the activity
1618                  * LEDs
1619                  */
1620                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1621                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1622                 switch (current_mode) {
1623                 case I40E_COMBINED_ACTIVITY:
1624                 case I40E_FILTER_ACTIVITY:
1625                 case I40E_MAC_ACTIVITY:
1626                         continue;
1627                 default:
1628                         break;
1629                 }
1630
1631                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1632                 /* this & is a bit of paranoia, but serves as a range check */
1633                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1634                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1635
1636                 if (mode == I40E_LINK_ACTIVITY)
1637                         blink = false;
1638
1639                 if (blink)
1640                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1641                 else
1642                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1643
1644                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1645                 break;
1646         }
1647 }
1648
1649 /* Admin command wrappers */
1650
1651 /**
1652  * i40e_aq_get_phy_capabilities
1653  * @hw: pointer to the hw struct
1654  * @abilities: structure for PHY capabilities to be filled
1655  * @qualified_modules: report Qualified Modules
1656  * @report_init: report init capabilities (active are default)
1657  * @cmd_details: pointer to command details structure or NULL
1658  *
1659  * Returns the various PHY abilities supported on the Port.
1660  **/
1661 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1662                         bool qualified_modules, bool report_init,
1663                         struct i40e_aq_get_phy_abilities_resp *abilities,
1664                         struct i40e_asq_cmd_details *cmd_details)
1665 {
1666         struct i40e_aq_desc desc;
1667         enum i40e_status_code status;
1668         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1669
1670         if (!abilities)
1671                 return I40E_ERR_PARAM;
1672
1673         i40e_fill_default_direct_cmd_desc(&desc,
1674                                           i40e_aqc_opc_get_phy_abilities);
1675
1676         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1677         if (abilities_size > I40E_AQ_LARGE_BUF)
1678                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1679
1680         if (qualified_modules)
1681                 desc.params.external.param0 |=
1682                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1683
1684         if (report_init)
1685                 desc.params.external.param0 |=
1686                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1687
1688         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1689                                     cmd_details);
1690
1691         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1692                 status = I40E_ERR_UNKNOWN_PHY;
1693
1694         if (report_init) {
1695                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1696                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1697                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1698                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1699                 } else {
1700                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1701                         hw->phy.phy_types |=
1702                                         ((u64)abilities->phy_type_ext << 32);
1703                 }
1704         }
1705
1706         return status;
1707 }
1708
1709 /**
1710  * i40e_aq_set_phy_config
1711  * @hw: pointer to the hw struct
1712  * @config: structure with PHY configuration to be set
1713  * @cmd_details: pointer to command details structure or NULL
1714  *
1715  * Set the various PHY configuration parameters
1716  * supported on the Port.One or more of the Set PHY config parameters may be
1717  * ignored in an MFP mode as the PF may not have the privilege to set some
1718  * of the PHY Config parameters. This status will be indicated by the
1719  * command response.
1720  **/
1721 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1722                                 struct i40e_aq_set_phy_config *config,
1723                                 struct i40e_asq_cmd_details *cmd_details)
1724 {
1725         struct i40e_aq_desc desc;
1726         struct i40e_aq_set_phy_config *cmd =
1727                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1728         enum i40e_status_code status;
1729
1730         if (!config)
1731                 return I40E_ERR_PARAM;
1732
1733         i40e_fill_default_direct_cmd_desc(&desc,
1734                                           i40e_aqc_opc_set_phy_config);
1735
1736         *cmd = *config;
1737
1738         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1739
1740         return status;
1741 }
1742
1743 /**
1744  * i40e_set_fc
1745  * @hw: pointer to the hw struct
1746  *
1747  * Set the requested flow control mode using set_phy_config.
1748  **/
1749 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1750                                   bool atomic_restart)
1751 {
1752         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1753         struct i40e_aq_get_phy_abilities_resp abilities;
1754         struct i40e_aq_set_phy_config config;
1755         enum i40e_status_code status;
1756         u8 pause_mask = 0x0;
1757
1758         *aq_failures = 0x0;
1759
1760         switch (fc_mode) {
1761         case I40E_FC_FULL:
1762                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1763                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1764                 break;
1765         case I40E_FC_RX_PAUSE:
1766                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1767                 break;
1768         case I40E_FC_TX_PAUSE:
1769                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1770                 break;
1771         default:
1772                 break;
1773         }
1774
1775         /* Get the current phy config */
1776         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1777                                               NULL);
1778         if (status) {
1779                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1780                 return status;
1781         }
1782
1783         memset(&config, 0, sizeof(config));
1784         /* clear the old pause settings */
1785         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1786                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1787         /* set the new abilities */
1788         config.abilities |= pause_mask;
1789         /* If the abilities have changed, then set the new config */
1790         if (config.abilities != abilities.abilities) {
1791                 /* Auto restart link so settings take effect */
1792                 if (atomic_restart)
1793                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794                 /* Copy over all the old settings */
1795                 config.phy_type = abilities.phy_type;
1796                 config.phy_type_ext = abilities.phy_type_ext;
1797                 config.link_speed = abilities.link_speed;
1798                 config.eee_capability = abilities.eee_capability;
1799                 config.eeer = abilities.eeer_val;
1800                 config.low_power_ctrl = abilities.d3_lpan;
1801                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1802                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1803                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1804
1805                 if (status)
1806                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1807         }
1808         /* Update the link info */
1809         status = i40e_update_link_info(hw);
1810         if (status) {
1811                 /* Wait a little bit (on 40G cards it sometimes takes a really
1812                  * long time for link to come back from the atomic reset)
1813                  * and try once more
1814                  */
1815                 i40e_msec_delay(1000);
1816                 status = i40e_update_link_info(hw);
1817         }
1818         if (status)
1819                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1820
1821         return status;
1822 }
1823
1824 /**
1825  * i40e_aq_set_mac_config
1826  * @hw: pointer to the hw struct
1827  * @max_frame_size: Maximum Frame Size to be supported by the port
1828  * @crc_en: Tell HW to append a CRC to outgoing frames
1829  * @pacing: Pacing configurations
1830  * @cmd_details: pointer to command details structure or NULL
1831  *
1832  * Configure MAC settings for frame size, jumbo frame support and the
1833  * addition of a CRC by the hardware.
1834  **/
1835 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1836                                 u16 max_frame_size,
1837                                 bool crc_en, u16 pacing,
1838                                 struct i40e_asq_cmd_details *cmd_details)
1839 {
1840         struct i40e_aq_desc desc;
1841         struct i40e_aq_set_mac_config *cmd =
1842                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1843         enum i40e_status_code status;
1844
1845         if (max_frame_size == 0)
1846                 return I40E_ERR_PARAM;
1847
1848         i40e_fill_default_direct_cmd_desc(&desc,
1849                                           i40e_aqc_opc_set_mac_config);
1850
1851         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1852         cmd->params = ((u8)pacing & 0x0F) << 3;
1853         if (crc_en)
1854                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1855
1856         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1857
1858         return status;
1859 }
1860
1861 /**
1862  * i40e_aq_clear_pxe_mode
1863  * @hw: pointer to the hw struct
1864  * @cmd_details: pointer to command details structure or NULL
1865  *
1866  * Tell the firmware that the driver is taking over from PXE
1867  **/
1868 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1869                         struct i40e_asq_cmd_details *cmd_details)
1870 {
1871         enum i40e_status_code status;
1872         struct i40e_aq_desc desc;
1873         struct i40e_aqc_clear_pxe *cmd =
1874                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1875
1876         i40e_fill_default_direct_cmd_desc(&desc,
1877                                           i40e_aqc_opc_clear_pxe_mode);
1878
1879         cmd->rx_cnt = 0x2;
1880
1881         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1882
1883         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1884
1885         return status;
1886 }
1887
1888 /**
1889  * i40e_aq_set_link_restart_an
1890  * @hw: pointer to the hw struct
1891  * @enable_link: if true: enable link, if false: disable link
1892  * @cmd_details: pointer to command details structure or NULL
1893  *
1894  * Sets up the link and restarts the Auto-Negotiation over the link.
1895  **/
1896 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1897                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1898 {
1899         struct i40e_aq_desc desc;
1900         struct i40e_aqc_set_link_restart_an *cmd =
1901                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1902         enum i40e_status_code status;
1903
1904         i40e_fill_default_direct_cmd_desc(&desc,
1905                                           i40e_aqc_opc_set_link_restart_an);
1906
1907         cmd->command = I40E_AQ_PHY_RESTART_AN;
1908         if (enable_link)
1909                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1910         else
1911                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1912
1913         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1914
1915         return status;
1916 }
1917
1918 /**
1919  * i40e_aq_get_link_info
1920  * @hw: pointer to the hw struct
1921  * @enable_lse: enable/disable LinkStatusEvent reporting
1922  * @link: pointer to link status structure - optional
1923  * @cmd_details: pointer to command details structure or NULL
1924  *
1925  * Returns the link status of the adapter.
1926  **/
1927 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1928                                 bool enable_lse, struct i40e_link_status *link,
1929                                 struct i40e_asq_cmd_details *cmd_details)
1930 {
1931         struct i40e_aq_desc desc;
1932         struct i40e_aqc_get_link_status *resp =
1933                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1934         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1935         enum i40e_status_code status;
1936         bool tx_pause, rx_pause;
1937         u16 command_flags;
1938
1939         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1940
1941         if (enable_lse)
1942                 command_flags = I40E_AQ_LSE_ENABLE;
1943         else
1944                 command_flags = I40E_AQ_LSE_DISABLE;
1945         resp->command_flags = CPU_TO_LE16(command_flags);
1946
1947         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1948
1949         if (status != I40E_SUCCESS)
1950                 goto aq_get_link_info_exit;
1951
1952         /* save off old link status information */
1953         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1954                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1955
1956         /* update link status */
1957         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1958         hw->phy.media_type = i40e_get_media_type(hw);
1959         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1960         hw_link_info->link_info = resp->link_info;
1961         hw_link_info->an_info = resp->an_info;
1962         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1963                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1964         hw_link_info->ext_info = resp->ext_info;
1965         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1966         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1967         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1968
1969         /* update fc info */
1970         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1971         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1972         if (tx_pause & rx_pause)
1973                 hw->fc.current_mode = I40E_FC_FULL;
1974         else if (tx_pause)
1975                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1976         else if (rx_pause)
1977                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1978         else
1979                 hw->fc.current_mode = I40E_FC_NONE;
1980
1981         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1982                 hw_link_info->crc_enable = true;
1983         else
1984                 hw_link_info->crc_enable = false;
1985
1986         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1987                 hw_link_info->lse_enable = true;
1988         else
1989                 hw_link_info->lse_enable = false;
1990
1991         if ((hw->mac.type == I40E_MAC_XL710) &&
1992             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1993              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1994                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1995
1996         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1997             hw->aq.api_min_ver >= 7) {
1998                 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type);
1999                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2000         }
2001
2002         /* save link status information */
2003         if (link)
2004                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2005                             I40E_NONDMA_TO_NONDMA);
2006
2007         /* flag cleared so helper functions don't call AQ again */
2008         hw->phy.get_link_info = false;
2009
2010 aq_get_link_info_exit:
2011         return status;
2012 }
2013
2014 /**
2015  * i40e_aq_set_phy_int_mask
2016  * @hw: pointer to the hw struct
2017  * @mask: interrupt mask to be set
2018  * @cmd_details: pointer to command details structure or NULL
2019  *
2020  * Set link interrupt mask.
2021  **/
2022 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2023                                 u16 mask,
2024                                 struct i40e_asq_cmd_details *cmd_details)
2025 {
2026         struct i40e_aq_desc desc;
2027         struct i40e_aqc_set_phy_int_mask *cmd =
2028                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2029         enum i40e_status_code status;
2030
2031         i40e_fill_default_direct_cmd_desc(&desc,
2032                                           i40e_aqc_opc_set_phy_int_mask);
2033
2034         cmd->event_mask = CPU_TO_LE16(mask);
2035
2036         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2037
2038         return status;
2039 }
2040
2041 /**
2042  * i40e_aq_get_local_advt_reg
2043  * @hw: pointer to the hw struct
2044  * @advt_reg: local AN advertisement register value
2045  * @cmd_details: pointer to command details structure or NULL
2046  *
2047  * Get the Local AN advertisement register value.
2048  **/
2049 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2050                                 u64 *advt_reg,
2051                                 struct i40e_asq_cmd_details *cmd_details)
2052 {
2053         struct i40e_aq_desc desc;
2054         struct i40e_aqc_an_advt_reg *resp =
2055                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2056         enum i40e_status_code status;
2057
2058         i40e_fill_default_direct_cmd_desc(&desc,
2059                                           i40e_aqc_opc_get_local_advt_reg);
2060
2061         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2062
2063         if (status != I40E_SUCCESS)
2064                 goto aq_get_local_advt_reg_exit;
2065
2066         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2067         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2068
2069 aq_get_local_advt_reg_exit:
2070         return status;
2071 }
2072
2073 /**
2074  * i40e_aq_set_local_advt_reg
2075  * @hw: pointer to the hw struct
2076  * @advt_reg: local AN advertisement register value
2077  * @cmd_details: pointer to command details structure or NULL
2078  *
2079  * Get the Local AN advertisement register value.
2080  **/
2081 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2082                                 u64 advt_reg,
2083                                 struct i40e_asq_cmd_details *cmd_details)
2084 {
2085         struct i40e_aq_desc desc;
2086         struct i40e_aqc_an_advt_reg *cmd =
2087                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2088         enum i40e_status_code status;
2089
2090         i40e_fill_default_direct_cmd_desc(&desc,
2091                                           i40e_aqc_opc_get_local_advt_reg);
2092
2093         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2094         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2095
2096         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2097
2098         return status;
2099 }
2100
2101 /**
2102  * i40e_aq_get_partner_advt
2103  * @hw: pointer to the hw struct
2104  * @advt_reg: AN partner advertisement register value
2105  * @cmd_details: pointer to command details structure or NULL
2106  *
2107  * Get the link partner AN advertisement register value.
2108  **/
2109 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2110                                 u64 *advt_reg,
2111                                 struct i40e_asq_cmd_details *cmd_details)
2112 {
2113         struct i40e_aq_desc desc;
2114         struct i40e_aqc_an_advt_reg *resp =
2115                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2116         enum i40e_status_code status;
2117
2118         i40e_fill_default_direct_cmd_desc(&desc,
2119                                           i40e_aqc_opc_get_partner_advt);
2120
2121         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2122
2123         if (status != I40E_SUCCESS)
2124                 goto aq_get_partner_advt_exit;
2125
2126         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2127         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2128
2129 aq_get_partner_advt_exit:
2130         return status;
2131 }
2132
2133 /**
2134  * i40e_aq_set_lb_modes
2135  * @hw: pointer to the hw struct
2136  * @lb_modes: loopback mode to be set
2137  * @cmd_details: pointer to command details structure or NULL
2138  *
2139  * Sets loopback modes.
2140  **/
2141 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2142                                 u16 lb_modes,
2143                                 struct i40e_asq_cmd_details *cmd_details)
2144 {
2145         struct i40e_aq_desc desc;
2146         struct i40e_aqc_set_lb_mode *cmd =
2147                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2148         enum i40e_status_code status;
2149
2150         i40e_fill_default_direct_cmd_desc(&desc,
2151                                           i40e_aqc_opc_set_lb_modes);
2152
2153         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2154
2155         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2156
2157         return status;
2158 }
2159
2160 /**
2161  * i40e_aq_set_phy_debug
2162  * @hw: pointer to the hw struct
2163  * @cmd_flags: debug command flags
2164  * @cmd_details: pointer to command details structure or NULL
2165  *
2166  * Reset the external PHY.
2167  **/
2168 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2169                                 struct i40e_asq_cmd_details *cmd_details)
2170 {
2171         struct i40e_aq_desc desc;
2172         struct i40e_aqc_set_phy_debug *cmd =
2173                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2174         enum i40e_status_code status;
2175
2176         i40e_fill_default_direct_cmd_desc(&desc,
2177                                           i40e_aqc_opc_set_phy_debug);
2178
2179         cmd->command_flags = cmd_flags;
2180
2181         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2182
2183         return status;
2184 }
2185
2186 /**
2187  * i40e_aq_add_vsi
2188  * @hw: pointer to the hw struct
2189  * @vsi_ctx: pointer to a vsi context struct
2190  * @cmd_details: pointer to command details structure or NULL
2191  *
2192  * Add a VSI context to the hardware.
2193 **/
2194 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2195                                 struct i40e_vsi_context *vsi_ctx,
2196                                 struct i40e_asq_cmd_details *cmd_details)
2197 {
2198         struct i40e_aq_desc desc;
2199         struct i40e_aqc_add_get_update_vsi *cmd =
2200                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2201         struct i40e_aqc_add_get_update_vsi_completion *resp =
2202                 (struct i40e_aqc_add_get_update_vsi_completion *)
2203                 &desc.params.raw;
2204         enum i40e_status_code status;
2205
2206         i40e_fill_default_direct_cmd_desc(&desc,
2207                                           i40e_aqc_opc_add_vsi);
2208
2209         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2210         cmd->connection_type = vsi_ctx->connection_type;
2211         cmd->vf_id = vsi_ctx->vf_num;
2212         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2213
2214         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2215
2216         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2217                                     sizeof(vsi_ctx->info), cmd_details);
2218
2219         if (status != I40E_SUCCESS)
2220                 goto aq_add_vsi_exit;
2221
2222         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2223         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2224         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2225         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2226
2227 aq_add_vsi_exit:
2228         return status;
2229 }
2230
2231 /**
2232  * i40e_aq_set_default_vsi
2233  * @hw: pointer to the hw struct
2234  * @seid: vsi number
2235  * @cmd_details: pointer to command details structure or NULL
2236  **/
2237 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2238                                 u16 seid,
2239                                 struct i40e_asq_cmd_details *cmd_details)
2240 {
2241         struct i40e_aq_desc desc;
2242         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2243                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2244                 &desc.params.raw;
2245         enum i40e_status_code status;
2246
2247         i40e_fill_default_direct_cmd_desc(&desc,
2248                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2249
2250         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2251         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2252         cmd->seid = CPU_TO_LE16(seid);
2253
2254         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2255
2256         return status;
2257 }
2258
2259 /**
2260  * i40e_aq_clear_default_vsi
2261  * @hw: pointer to the hw struct
2262  * @seid: vsi number
2263  * @cmd_details: pointer to command details structure or NULL
2264  **/
2265 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2266                                 u16 seid,
2267                                 struct i40e_asq_cmd_details *cmd_details)
2268 {
2269         struct i40e_aq_desc desc;
2270         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2271                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2272                 &desc.params.raw;
2273         enum i40e_status_code status;
2274
2275         i40e_fill_default_direct_cmd_desc(&desc,
2276                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2277
2278         cmd->promiscuous_flags = CPU_TO_LE16(0);
2279         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2280         cmd->seid = CPU_TO_LE16(seid);
2281
2282         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2283
2284         return status;
2285 }
2286
2287 /**
2288  * i40e_aq_set_vsi_unicast_promiscuous
2289  * @hw: pointer to the hw struct
2290  * @seid: vsi number
2291  * @set: set unicast promiscuous enable/disable
2292  * @cmd_details: pointer to command details structure or NULL
2293  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2294  **/
2295 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2296                                 u16 seid, bool set,
2297                                 struct i40e_asq_cmd_details *cmd_details,
2298                                 bool rx_only_promisc)
2299 {
2300         struct i40e_aq_desc desc;
2301         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2302                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2303         enum i40e_status_code status;
2304         u16 flags = 0;
2305
2306         i40e_fill_default_direct_cmd_desc(&desc,
2307                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2308
2309         if (set) {
2310                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2311                 if (rx_only_promisc &&
2312                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2313                      (hw->aq.api_maj_ver > 1)))
2314                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2315         }
2316
2317         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2318
2319         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2320         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2321              (hw->aq.api_maj_ver > 1))
2322                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2323
2324         cmd->seid = CPU_TO_LE16(seid);
2325         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2326
2327         return status;
2328 }
2329
2330 /**
2331  * i40e_aq_set_vsi_multicast_promiscuous
2332  * @hw: pointer to the hw struct
2333  * @seid: vsi number
2334  * @set: set multicast promiscuous enable/disable
2335  * @cmd_details: pointer to command details structure or NULL
2336  **/
2337 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2338                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2339 {
2340         struct i40e_aq_desc desc;
2341         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2342                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2343         enum i40e_status_code status;
2344         u16 flags = 0;
2345
2346         i40e_fill_default_direct_cmd_desc(&desc,
2347                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2348
2349         if (set)
2350                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2351
2352         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2353
2354         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2355
2356         cmd->seid = CPU_TO_LE16(seid);
2357         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2358
2359         return status;
2360 }
2361
2362 /**
2363 * i40e_aq_set_vsi_full_promiscuous
2364 * @hw: pointer to the hw struct
2365 * @seid: VSI number
2366 * @set: set promiscuous enable/disable
2367 * @cmd_details: pointer to command details structure or NULL
2368 **/
2369 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2370                                 u16 seid, bool set,
2371                                 struct i40e_asq_cmd_details *cmd_details)
2372 {
2373         struct i40e_aq_desc desc;
2374         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2375                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2376         enum i40e_status_code status;
2377         u16 flags = 0;
2378
2379         i40e_fill_default_direct_cmd_desc(&desc,
2380                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2381
2382         if (set)
2383                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2384                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2385                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2386
2387         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2388
2389         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2390                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2391                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2392
2393         cmd->seid = CPU_TO_LE16(seid);
2394         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2395
2396         return status;
2397 }
2398
2399 /**
2400  * i40e_aq_set_vsi_mc_promisc_on_vlan
2401  * @hw: pointer to the hw struct
2402  * @seid: vsi number
2403  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2404  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2405  * @cmd_details: pointer to command details structure or NULL
2406  **/
2407 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2408                                 u16 seid, bool enable, u16 vid,
2409                                 struct i40e_asq_cmd_details *cmd_details)
2410 {
2411         struct i40e_aq_desc desc;
2412         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2413                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2414         enum i40e_status_code status;
2415         u16 flags = 0;
2416
2417         i40e_fill_default_direct_cmd_desc(&desc,
2418                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2419
2420         if (enable)
2421                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2422
2423         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2424         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2425         cmd->seid = CPU_TO_LE16(seid);
2426         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2427
2428         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2429
2430         return status;
2431 }
2432
2433 /**
2434  * i40e_aq_set_vsi_uc_promisc_on_vlan
2435  * @hw: pointer to the hw struct
2436  * @seid: vsi number
2437  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2438  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2439  * @cmd_details: pointer to command details structure or NULL
2440  **/
2441 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2442                                 u16 seid, bool enable, u16 vid,
2443                                 struct i40e_asq_cmd_details *cmd_details)
2444 {
2445         struct i40e_aq_desc desc;
2446         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2447                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2448         enum i40e_status_code status;
2449         u16 flags = 0;
2450
2451         i40e_fill_default_direct_cmd_desc(&desc,
2452                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2453
2454         if (enable)
2455                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2456
2457         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2458         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2459         cmd->seid = CPU_TO_LE16(seid);
2460         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2461
2462         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2463
2464         return status;
2465 }
2466
2467 /**
2468  * i40e_aq_set_vsi_bc_promisc_on_vlan
2469  * @hw: pointer to the hw struct
2470  * @seid: vsi number
2471  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2472  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2473  * @cmd_details: pointer to command details structure or NULL
2474  **/
2475 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2476                                 u16 seid, bool enable, u16 vid,
2477                                 struct i40e_asq_cmd_details *cmd_details)
2478 {
2479         struct i40e_aq_desc desc;
2480         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2481                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2482         enum i40e_status_code status;
2483         u16 flags = 0;
2484
2485         i40e_fill_default_direct_cmd_desc(&desc,
2486                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2487
2488         if (enable)
2489                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2490
2491         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2492         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2493         cmd->seid = CPU_TO_LE16(seid);
2494         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2495
2496         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2497
2498         return status;
2499 }
2500
2501 /**
2502  * i40e_aq_set_vsi_broadcast
2503  * @hw: pointer to the hw struct
2504  * @seid: vsi number
2505  * @set_filter: true to set filter, false to clear filter
2506  * @cmd_details: pointer to command details structure or NULL
2507  *
2508  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2509  **/
2510 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2511                                 u16 seid, bool set_filter,
2512                                 struct i40e_asq_cmd_details *cmd_details)
2513 {
2514         struct i40e_aq_desc desc;
2515         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2516                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2517         enum i40e_status_code status;
2518
2519         i40e_fill_default_direct_cmd_desc(&desc,
2520                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2521
2522         if (set_filter)
2523                 cmd->promiscuous_flags
2524                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2525         else
2526                 cmd->promiscuous_flags
2527                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2528
2529         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2530         cmd->seid = CPU_TO_LE16(seid);
2531         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2532
2533         return status;
2534 }
2535
2536 /**
2537  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2538  * @hw: pointer to the hw struct
2539  * @seid: vsi number
2540  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2541  * @cmd_details: pointer to command details structure or NULL
2542  **/
2543 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2544                                 u16 seid, bool enable,
2545                                 struct i40e_asq_cmd_details *cmd_details)
2546 {
2547         struct i40e_aq_desc desc;
2548         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2549                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2550         enum i40e_status_code status;
2551         u16 flags = 0;
2552
2553         i40e_fill_default_direct_cmd_desc(&desc,
2554                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2555         if (enable)
2556                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2557
2558         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2559         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2560         cmd->seid = CPU_TO_LE16(seid);
2561
2562         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2563
2564         return status;
2565 }
2566
2567 /**
2568  * i40e_get_vsi_params - get VSI configuration info
2569  * @hw: pointer to the hw struct
2570  * @vsi_ctx: pointer to a vsi context struct
2571  * @cmd_details: pointer to command details structure or NULL
2572  **/
2573 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2574                                 struct i40e_vsi_context *vsi_ctx,
2575                                 struct i40e_asq_cmd_details *cmd_details)
2576 {
2577         struct i40e_aq_desc desc;
2578         struct i40e_aqc_add_get_update_vsi *cmd =
2579                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2580         struct i40e_aqc_add_get_update_vsi_completion *resp =
2581                 (struct i40e_aqc_add_get_update_vsi_completion *)
2582                 &desc.params.raw;
2583         enum i40e_status_code status;
2584
2585         UNREFERENCED_1PARAMETER(cmd_details);
2586         i40e_fill_default_direct_cmd_desc(&desc,
2587                                           i40e_aqc_opc_get_vsi_parameters);
2588
2589         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2590
2591         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2592
2593         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2594                                     sizeof(vsi_ctx->info), NULL);
2595
2596         if (status != I40E_SUCCESS)
2597                 goto aq_get_vsi_params_exit;
2598
2599         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2600         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2601         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2602         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2603
2604 aq_get_vsi_params_exit:
2605         return status;
2606 }
2607
2608 /**
2609  * i40e_aq_update_vsi_params
2610  * @hw: pointer to the hw struct
2611  * @vsi_ctx: pointer to a vsi context struct
2612  * @cmd_details: pointer to command details structure or NULL
2613  *
2614  * Update a VSI context.
2615  **/
2616 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2617                                 struct i40e_vsi_context *vsi_ctx,
2618                                 struct i40e_asq_cmd_details *cmd_details)
2619 {
2620         struct i40e_aq_desc desc;
2621         struct i40e_aqc_add_get_update_vsi *cmd =
2622                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2623         struct i40e_aqc_add_get_update_vsi_completion *resp =
2624                 (struct i40e_aqc_add_get_update_vsi_completion *)
2625                 &desc.params.raw;
2626         enum i40e_status_code status;
2627
2628         i40e_fill_default_direct_cmd_desc(&desc,
2629                                           i40e_aqc_opc_update_vsi_parameters);
2630         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2631
2632         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2633
2634         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2635                                     sizeof(vsi_ctx->info), cmd_details);
2636
2637         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2638         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2639
2640         return status;
2641 }
2642
2643 /**
2644  * i40e_aq_get_switch_config
2645  * @hw: pointer to the hardware structure
2646  * @buf: pointer to the result buffer
2647  * @buf_size: length of input buffer
2648  * @start_seid: seid to start for the report, 0 == beginning
2649  * @cmd_details: pointer to command details structure or NULL
2650  *
2651  * Fill the buf with switch configuration returned from AdminQ command
2652  **/
2653 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2654                                 struct i40e_aqc_get_switch_config_resp *buf,
2655                                 u16 buf_size, u16 *start_seid,
2656                                 struct i40e_asq_cmd_details *cmd_details)
2657 {
2658         struct i40e_aq_desc desc;
2659         struct i40e_aqc_switch_seid *scfg =
2660                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2661         enum i40e_status_code status;
2662
2663         i40e_fill_default_direct_cmd_desc(&desc,
2664                                           i40e_aqc_opc_get_switch_config);
2665         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2666         if (buf_size > I40E_AQ_LARGE_BUF)
2667                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2668         scfg->seid = CPU_TO_LE16(*start_seid);
2669
2670         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2671         *start_seid = LE16_TO_CPU(scfg->seid);
2672
2673         return status;
2674 }
2675
2676 /**
2677  * i40e_aq_set_switch_config
2678  * @hw: pointer to the hardware structure
2679  * @flags: bit flag values to set
2680  * @valid_flags: which bit flags to set
2681  * @cmd_details: pointer to command details structure or NULL
2682  *
2683  * Set switch configuration bits
2684  **/
2685 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2686                                 u16 flags, u16 valid_flags,
2687                                 struct i40e_asq_cmd_details *cmd_details)
2688 {
2689         struct i40e_aq_desc desc;
2690         struct i40e_aqc_set_switch_config *scfg =
2691                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2692         enum i40e_status_code status;
2693
2694         i40e_fill_default_direct_cmd_desc(&desc,
2695                                           i40e_aqc_opc_set_switch_config);
2696         scfg->flags = CPU_TO_LE16(flags);
2697         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2698         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2699                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2700                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2701                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2702         }
2703         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2704
2705         return status;
2706 }
2707
2708 /**
2709  * i40e_aq_get_firmware_version
2710  * @hw: pointer to the hw struct
2711  * @fw_major_version: firmware major version
2712  * @fw_minor_version: firmware minor version
2713  * @fw_build: firmware build number
2714  * @api_major_version: major queue version
2715  * @api_minor_version: minor queue version
2716  * @cmd_details: pointer to command details structure or NULL
2717  *
2718  * Get the firmware version from the admin queue commands
2719  **/
2720 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2721                                 u16 *fw_major_version, u16 *fw_minor_version,
2722                                 u32 *fw_build,
2723                                 u16 *api_major_version, u16 *api_minor_version,
2724                                 struct i40e_asq_cmd_details *cmd_details)
2725 {
2726         struct i40e_aq_desc desc;
2727         struct i40e_aqc_get_version *resp =
2728                 (struct i40e_aqc_get_version *)&desc.params.raw;
2729         enum i40e_status_code status;
2730
2731         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2732
2733         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2734
2735         if (status == I40E_SUCCESS) {
2736                 if (fw_major_version != NULL)
2737                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2738                 if (fw_minor_version != NULL)
2739                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2740                 if (fw_build != NULL)
2741                         *fw_build = LE32_TO_CPU(resp->fw_build);
2742                 if (api_major_version != NULL)
2743                         *api_major_version = LE16_TO_CPU(resp->api_major);
2744                 if (api_minor_version != NULL)
2745                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2746
2747                 /* A workaround to fix the API version in SW */
2748                 if (api_major_version && api_minor_version &&
2749                     fw_major_version && fw_minor_version &&
2750                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2751                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2752                      (*fw_major_version > 4)))
2753                         *api_minor_version = 2;
2754         }
2755
2756         return status;
2757 }
2758
2759 /**
2760  * i40e_aq_send_driver_version
2761  * @hw: pointer to the hw struct
2762  * @dv: driver's major, minor version
2763  * @cmd_details: pointer to command details structure or NULL
2764  *
2765  * Send the driver version to the firmware
2766  **/
2767 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2768                                 struct i40e_driver_version *dv,
2769                                 struct i40e_asq_cmd_details *cmd_details)
2770 {
2771         struct i40e_aq_desc desc;
2772         struct i40e_aqc_driver_version *cmd =
2773                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2774         enum i40e_status_code status;
2775         u16 len;
2776
2777         if (dv == NULL)
2778                 return I40E_ERR_PARAM;
2779
2780         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2781
2782         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2783         cmd->driver_major_ver = dv->major_version;
2784         cmd->driver_minor_ver = dv->minor_version;
2785         cmd->driver_build_ver = dv->build_version;
2786         cmd->driver_subbuild_ver = dv->subbuild_version;
2787
2788         len = 0;
2789         while (len < sizeof(dv->driver_string) &&
2790                (dv->driver_string[len] < 0x80) &&
2791                dv->driver_string[len])
2792                 len++;
2793         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2794                                        len, cmd_details);
2795
2796         return status;
2797 }
2798
2799 /**
2800  * i40e_get_link_status - get status of the HW network link
2801  * @hw: pointer to the hw struct
2802  * @link_up: pointer to bool (true/false = linkup/linkdown)
2803  *
2804  * Variable link_up true if link is up, false if link is down.
2805  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2806  *
2807  * Side effect: LinkStatusEvent reporting becomes enabled
2808  **/
2809 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2810 {
2811         enum i40e_status_code status = I40E_SUCCESS;
2812
2813         if (hw->phy.get_link_info) {
2814                 status = i40e_update_link_info(hw);
2815
2816                 if (status != I40E_SUCCESS)
2817                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2818                                    status);
2819         }
2820
2821         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2822
2823         return status;
2824 }
2825
2826 /**
2827  * i40e_updatelink_status - update status of the HW network link
2828  * @hw: pointer to the hw struct
2829  **/
2830 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2831 {
2832         struct i40e_aq_get_phy_abilities_resp abilities;
2833         enum i40e_status_code status = I40E_SUCCESS;
2834
2835         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2836         if (status)
2837                 return status;
2838
2839         /* extra checking needed to ensure link info to user is timely */
2840         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2841             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2842              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2843                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2844                                                       &abilities, NULL);
2845                 if (status)
2846                         return status;
2847
2848                 hw->phy.link_info.req_fec_info =
2849                         abilities.fec_cfg_curr_mod_ext_info &
2850                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2851
2852                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2853                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2854         }
2855         return status;
2856 }
2857
2858
2859 /**
2860  * i40e_get_link_speed
2861  * @hw: pointer to the hw struct
2862  *
2863  * Returns the link speed of the adapter.
2864  **/
2865 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2866 {
2867         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2868         enum i40e_status_code status = I40E_SUCCESS;
2869
2870         if (hw->phy.get_link_info) {
2871                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2872
2873                 if (status != I40E_SUCCESS)
2874                         goto i40e_link_speed_exit;
2875         }
2876
2877         speed = hw->phy.link_info.link_speed;
2878
2879 i40e_link_speed_exit:
2880         return speed;
2881 }
2882
2883 /**
2884  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2885  * @hw: pointer to the hw struct
2886  * @uplink_seid: the MAC or other gizmo SEID
2887  * @downlink_seid: the VSI SEID
2888  * @enabled_tc: bitmap of TCs to be enabled
2889  * @default_port: true for default port VSI, false for control port
2890  * @veb_seid: pointer to where to put the resulting VEB SEID
2891  * @enable_stats: true to turn on VEB stats
2892  * @cmd_details: pointer to command details structure or NULL
2893  *
2894  * This asks the FW to add a VEB between the uplink and downlink
2895  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2896  **/
2897 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2898                                 u16 downlink_seid, u8 enabled_tc,
2899                                 bool default_port, u16 *veb_seid,
2900                                 bool enable_stats,
2901                                 struct i40e_asq_cmd_details *cmd_details)
2902 {
2903         struct i40e_aq_desc desc;
2904         struct i40e_aqc_add_veb *cmd =
2905                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2906         struct i40e_aqc_add_veb_completion *resp =
2907                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2908         enum i40e_status_code status;
2909         u16 veb_flags = 0;
2910
2911         /* SEIDs need to either both be set or both be 0 for floating VEB */
2912         if (!!uplink_seid != !!downlink_seid)
2913                 return I40E_ERR_PARAM;
2914
2915         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2916
2917         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2918         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2919         cmd->enable_tcs = enabled_tc;
2920         if (!uplink_seid)
2921                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2922         if (default_port)
2923                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2924         else
2925                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2926
2927         /* reverse logic here: set the bitflag to disable the stats */
2928         if (!enable_stats)
2929                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2930
2931         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2932
2933         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2934
2935         if (!status && veb_seid)
2936                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2937
2938         return status;
2939 }
2940
2941 /**
2942  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2943  * @hw: pointer to the hw struct
2944  * @veb_seid: the SEID of the VEB to query
2945  * @switch_id: the uplink switch id
2946  * @floating: set to true if the VEB is floating
2947  * @statistic_index: index of the stats counter block for this VEB
2948  * @vebs_used: number of VEB's used by function
2949  * @vebs_free: total VEB's not reserved by any function
2950  * @cmd_details: pointer to command details structure or NULL
2951  *
2952  * This retrieves the parameters for a particular VEB, specified by
2953  * uplink_seid, and returns them to the caller.
2954  **/
2955 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2956                                 u16 veb_seid, u16 *switch_id,
2957                                 bool *floating, u16 *statistic_index,
2958                                 u16 *vebs_used, u16 *vebs_free,
2959                                 struct i40e_asq_cmd_details *cmd_details)
2960 {
2961         struct i40e_aq_desc desc;
2962         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2963                 (struct i40e_aqc_get_veb_parameters_completion *)
2964                 &desc.params.raw;
2965         enum i40e_status_code status;
2966
2967         if (veb_seid == 0)
2968                 return I40E_ERR_PARAM;
2969
2970         i40e_fill_default_direct_cmd_desc(&desc,
2971                                           i40e_aqc_opc_get_veb_parameters);
2972         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2973
2974         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2975         if (status)
2976                 goto get_veb_exit;
2977
2978         if (switch_id)
2979                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2980         if (statistic_index)
2981                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2982         if (vebs_used)
2983                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2984         if (vebs_free)
2985                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2986         if (floating) {
2987                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2988
2989                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2990                         *floating = true;
2991                 else
2992                         *floating = false;
2993         }
2994
2995 get_veb_exit:
2996         return status;
2997 }
2998
2999 /**
3000  * i40e_aq_add_macvlan
3001  * @hw: pointer to the hw struct
3002  * @seid: VSI for the mac address
3003  * @mv_list: list of macvlans to be added
3004  * @count: length of the list
3005  * @cmd_details: pointer to command details structure or NULL
3006  *
3007  * Add MAC/VLAN addresses to the HW filtering
3008  **/
3009 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3010                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3011                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3012 {
3013         struct i40e_aq_desc desc;
3014         struct i40e_aqc_macvlan *cmd =
3015                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3016         enum i40e_status_code status;
3017         u16 buf_size;
3018         int i;
3019
3020         if (count == 0 || !mv_list || !hw)
3021                 return I40E_ERR_PARAM;
3022
3023         buf_size = count * sizeof(*mv_list);
3024
3025         /* prep the rest of the request */
3026         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3027         cmd->num_addresses = CPU_TO_LE16(count);
3028         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3029         cmd->seid[1] = 0;
3030         cmd->seid[2] = 0;
3031
3032         for (i = 0; i < count; i++)
3033                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3034                         mv_list[i].flags |=
3035                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3036
3037         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3038         if (buf_size > I40E_AQ_LARGE_BUF)
3039                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3040
3041         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3042                                        cmd_details);
3043
3044         return status;
3045 }
3046
3047 /**
3048  * i40e_aq_remove_macvlan
3049  * @hw: pointer to the hw struct
3050  * @seid: VSI for the mac address
3051  * @mv_list: list of macvlans to be removed
3052  * @count: length of the list
3053  * @cmd_details: pointer to command details structure or NULL
3054  *
3055  * Remove MAC/VLAN addresses from the HW filtering
3056  **/
3057 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3058                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3059                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3060 {
3061         struct i40e_aq_desc desc;
3062         struct i40e_aqc_macvlan *cmd =
3063                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3064         enum i40e_status_code status;
3065         u16 buf_size;
3066
3067         if (count == 0 || !mv_list || !hw)
3068                 return I40E_ERR_PARAM;
3069
3070         buf_size = count * sizeof(*mv_list);
3071
3072         /* prep the rest of the request */
3073         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3074         cmd->num_addresses = CPU_TO_LE16(count);
3075         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3076         cmd->seid[1] = 0;
3077         cmd->seid[2] = 0;
3078
3079         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3080         if (buf_size > I40E_AQ_LARGE_BUF)
3081                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3082
3083         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3084                                        cmd_details);
3085
3086         return status;
3087 }
3088
3089 /**
3090  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3091  * @hw: pointer to the hw struct
3092  * @opcode: AQ opcode for add or delete mirror rule
3093  * @sw_seid: Switch SEID (to which rule refers)
3094  * @rule_type: Rule Type (ingress/egress/VLAN)
3095  * @id: Destination VSI SEID or Rule ID
3096  * @count: length of the list
3097  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3098  * @cmd_details: pointer to command details structure or NULL
3099  * @rule_id: Rule ID returned from FW
3100  * @rule_used: Number of rules used in internal switch
3101  * @rule_free: Number of rules free in internal switch
3102  *
3103  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3104  * VEBs/VEPA elements only
3105  **/
3106 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3107                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3108                         u16 count, __le16 *mr_list,
3109                         struct i40e_asq_cmd_details *cmd_details,
3110                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3111 {
3112         struct i40e_aq_desc desc;
3113         struct i40e_aqc_add_delete_mirror_rule *cmd =
3114                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3115         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3116         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3117         enum i40e_status_code status;
3118         u16 buf_size;
3119
3120         buf_size = count * sizeof(*mr_list);
3121
3122         /* prep the rest of the request */
3123         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3124         cmd->seid = CPU_TO_LE16(sw_seid);
3125         cmd->rule_type = CPU_TO_LE16(rule_type &
3126                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3127         cmd->num_entries = CPU_TO_LE16(count);
3128         /* Dest VSI for add, rule_id for delete */
3129         cmd->destination = CPU_TO_LE16(id);
3130         if (mr_list) {
3131                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3132                                                 I40E_AQ_FLAG_RD));
3133                 if (buf_size > I40E_AQ_LARGE_BUF)
3134                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3135         }
3136
3137         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3138                                        cmd_details);
3139         if (status == I40E_SUCCESS ||
3140             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3141                 if (rule_id)
3142                         *rule_id = LE16_TO_CPU(resp->rule_id);
3143                 if (rules_used)
3144                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3145                 if (rules_free)
3146                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3147         }
3148         return status;
3149 }
3150
3151 /**
3152  * i40e_aq_add_mirrorrule - add a mirror rule
3153  * @hw: pointer to the hw struct
3154  * @sw_seid: Switch SEID (to which rule refers)
3155  * @rule_type: Rule Type (ingress/egress/VLAN)
3156  * @dest_vsi: SEID of VSI to which packets will be mirrored
3157  * @count: length of the list
3158  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3159  * @cmd_details: pointer to command details structure or NULL
3160  * @rule_id: Rule ID returned from FW
3161  * @rule_used: Number of rules used in internal switch
3162  * @rule_free: Number of rules free in internal switch
3163  *
3164  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3165  **/
3166 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3167                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3168                         struct i40e_asq_cmd_details *cmd_details,
3169                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3170 {
3171         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3172             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3173                 if (count == 0 || !mr_list)
3174                         return I40E_ERR_PARAM;
3175         }
3176
3177         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3178                                   rule_type, dest_vsi, count, mr_list,
3179                                   cmd_details, rule_id, rules_used, rules_free);
3180 }
3181
3182 /**
3183  * i40e_aq_delete_mirrorrule - delete a mirror rule
3184  * @hw: pointer to the hw struct
3185  * @sw_seid: Switch SEID (to which rule refers)
3186  * @rule_type: Rule Type (ingress/egress/VLAN)
3187  * @count: length of the list
3188  * @rule_id: Rule ID that is returned in the receive desc as part of
3189  *              add_mirrorrule.
3190  * @mr_list: list of mirrored VLAN IDs to be removed
3191  * @cmd_details: pointer to command details structure or NULL
3192  * @rule_used: Number of rules used in internal switch
3193  * @rule_free: Number of rules free in internal switch
3194  *
3195  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3196  **/
3197 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3198                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3199                         struct i40e_asq_cmd_details *cmd_details,
3200                         u16 *rules_used, u16 *rules_free)
3201 {
3202         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3203         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3204                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3205                  * mirroring. For other rule_type, count and rule_type should
3206                  * not matter.
3207                  */
3208                 if (count == 0 || !mr_list)
3209                         return I40E_ERR_PARAM;
3210         }
3211
3212         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3213                                   rule_type, rule_id, count, mr_list,
3214                                   cmd_details, NULL, rules_used, rules_free);
3215 }
3216
3217 /**
3218  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3219  * @hw: pointer to the hw struct
3220  * @seid: VSI for the vlan filters
3221  * @v_list: list of vlan filters to be added
3222  * @count: length of the list
3223  * @cmd_details: pointer to command details structure or NULL
3224  **/
3225 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3226                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3227                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3228 {
3229         struct i40e_aq_desc desc;
3230         struct i40e_aqc_macvlan *cmd =
3231                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3232         enum i40e_status_code status;
3233         u16 buf_size;
3234
3235         if (count == 0 || !v_list || !hw)
3236                 return I40E_ERR_PARAM;
3237
3238         buf_size = count * sizeof(*v_list);
3239
3240         /* prep the rest of the request */
3241         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3242         cmd->num_addresses = CPU_TO_LE16(count);
3243         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3244         cmd->seid[1] = 0;
3245         cmd->seid[2] = 0;
3246
3247         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3248         if (buf_size > I40E_AQ_LARGE_BUF)
3249                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3250
3251         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3252                                        cmd_details);
3253
3254         return status;
3255 }
3256
3257 /**
3258  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3259  * @hw: pointer to the hw struct
3260  * @seid: VSI for the vlan filters
3261  * @v_list: list of macvlans to be removed
3262  * @count: length of the list
3263  * @cmd_details: pointer to command details structure or NULL
3264  **/
3265 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3266                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3267                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3268 {
3269         struct i40e_aq_desc desc;
3270         struct i40e_aqc_macvlan *cmd =
3271                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3272         enum i40e_status_code status;
3273         u16 buf_size;
3274
3275         if (count == 0 || !v_list || !hw)
3276                 return I40E_ERR_PARAM;
3277
3278         buf_size = count * sizeof(*v_list);
3279
3280         /* prep the rest of the request */
3281         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3282         cmd->num_addresses = CPU_TO_LE16(count);
3283         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3284         cmd->seid[1] = 0;
3285         cmd->seid[2] = 0;
3286
3287         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3288         if (buf_size > I40E_AQ_LARGE_BUF)
3289                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3290
3291         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3292                                        cmd_details);
3293
3294         return status;
3295 }
3296
3297 /**
3298  * i40e_aq_send_msg_to_vf
3299  * @hw: pointer to the hardware structure
3300  * @vfid: vf id to send msg
3301  * @v_opcode: opcodes for VF-PF communication
3302  * @v_retval: return error code
3303  * @msg: pointer to the msg buffer
3304  * @msglen: msg length
3305  * @cmd_details: pointer to command details
3306  *
3307  * send msg to vf
3308  **/
3309 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3310                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3311                                 struct i40e_asq_cmd_details *cmd_details)
3312 {
3313         struct i40e_aq_desc desc;
3314         struct i40e_aqc_pf_vf_message *cmd =
3315                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3316         enum i40e_status_code status;
3317
3318         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3319         cmd->id = CPU_TO_LE32(vfid);
3320         desc.cookie_high = CPU_TO_LE32(v_opcode);
3321         desc.cookie_low = CPU_TO_LE32(v_retval);
3322         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3323         if (msglen) {
3324                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3325                                                 I40E_AQ_FLAG_RD));
3326                 if (msglen > I40E_AQ_LARGE_BUF)
3327                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3328                 desc.datalen = CPU_TO_LE16(msglen);
3329         }
3330         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3331
3332         return status;
3333 }
3334
3335 /**
3336  * i40e_aq_debug_read_register
3337  * @hw: pointer to the hw struct
3338  * @reg_addr: register address
3339  * @reg_val: register value
3340  * @cmd_details: pointer to command details structure or NULL
3341  *
3342  * Read the register using the admin queue commands
3343  **/
3344 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3345                                 u32 reg_addr, u64 *reg_val,
3346                                 struct i40e_asq_cmd_details *cmd_details)
3347 {
3348         struct i40e_aq_desc desc;
3349         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3350                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3351         enum i40e_status_code status;
3352
3353         if (reg_val == NULL)
3354                 return I40E_ERR_PARAM;
3355
3356         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3357
3358         cmd_resp->address = CPU_TO_LE32(reg_addr);
3359
3360         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3361
3362         if (status == I40E_SUCCESS) {
3363                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3364                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3365         }
3366
3367         return status;
3368 }
3369
3370 /**
3371  * i40e_aq_debug_write_register
3372  * @hw: pointer to the hw struct
3373  * @reg_addr: register address
3374  * @reg_val: register value
3375  * @cmd_details: pointer to command details structure or NULL
3376  *
3377  * Write to a register using the admin queue commands
3378  **/
3379 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3380                                 u32 reg_addr, u64 reg_val,
3381                                 struct i40e_asq_cmd_details *cmd_details)
3382 {
3383         struct i40e_aq_desc desc;
3384         struct i40e_aqc_debug_reg_read_write *cmd =
3385                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3386         enum i40e_status_code status;
3387
3388         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3389
3390         cmd->address = CPU_TO_LE32(reg_addr);
3391         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3392         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3393
3394         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3395
3396         return status;
3397 }
3398
3399 /**
3400  * i40e_aq_request_resource
3401  * @hw: pointer to the hw struct
3402  * @resource: resource id
3403  * @access: access type
3404  * @sdp_number: resource number
3405  * @timeout: the maximum time in ms that the driver may hold the resource
3406  * @cmd_details: pointer to command details structure or NULL
3407  *
3408  * requests common resource using the admin queue commands
3409  **/
3410 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3411                                 enum i40e_aq_resources_ids resource,
3412                                 enum i40e_aq_resource_access_type access,
3413                                 u8 sdp_number, u64 *timeout,
3414                                 struct i40e_asq_cmd_details *cmd_details)
3415 {
3416         struct i40e_aq_desc desc;
3417         struct i40e_aqc_request_resource *cmd_resp =
3418                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3419         enum i40e_status_code status;
3420
3421         DEBUGFUNC("i40e_aq_request_resource");
3422
3423         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3424
3425         cmd_resp->resource_id = CPU_TO_LE16(resource);
3426         cmd_resp->access_type = CPU_TO_LE16(access);
3427         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3428
3429         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3430         /* The completion specifies the maximum time in ms that the driver
3431          * may hold the resource in the Timeout field.
3432          * If the resource is held by someone else, the command completes with
3433          * busy return value and the timeout field indicates the maximum time
3434          * the current owner of the resource has to free it.
3435          */
3436         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3437                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3438
3439         return status;
3440 }
3441
3442 /**
3443  * i40e_aq_release_resource
3444  * @hw: pointer to the hw struct
3445  * @resource: resource id
3446  * @sdp_number: resource number
3447  * @cmd_details: pointer to command details structure or NULL
3448  *
3449  * release common resource using the admin queue commands
3450  **/
3451 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3452                                 enum i40e_aq_resources_ids resource,
3453                                 u8 sdp_number,
3454                                 struct i40e_asq_cmd_details *cmd_details)
3455 {
3456         struct i40e_aq_desc desc;
3457         struct i40e_aqc_request_resource *cmd =
3458                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3459         enum i40e_status_code status;
3460
3461         DEBUGFUNC("i40e_aq_release_resource");
3462
3463         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3464
3465         cmd->resource_id = CPU_TO_LE16(resource);
3466         cmd->resource_number = CPU_TO_LE32(sdp_number);
3467
3468         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3469
3470         return status;
3471 }
3472
3473 /**
3474  * i40e_aq_read_nvm
3475  * @hw: pointer to the hw struct
3476  * @module_pointer: module pointer location in words from the NVM beginning
3477  * @offset: byte offset from the module beginning
3478  * @length: length of the section to be read (in bytes from the offset)
3479  * @data: command buffer (size [bytes] = length)
3480  * @last_command: tells if this is the last command in a series
3481  * @cmd_details: pointer to command details structure or NULL
3482  *
3483  * Read the NVM using the admin queue commands
3484  **/
3485 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3486                                 u32 offset, u16 length, void *data,
3487                                 bool last_command,
3488                                 struct i40e_asq_cmd_details *cmd_details)
3489 {
3490         struct i40e_aq_desc desc;
3491         struct i40e_aqc_nvm_update *cmd =
3492                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3493         enum i40e_status_code status;
3494
3495         DEBUGFUNC("i40e_aq_read_nvm");
3496
3497         /* In offset the highest byte must be zeroed. */
3498         if (offset & 0xFF000000) {
3499                 status = I40E_ERR_PARAM;
3500                 goto i40e_aq_read_nvm_exit;
3501         }
3502
3503         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3504
3505         /* If this is the last command in a series, set the proper flag. */
3506         if (last_command)
3507                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3508         cmd->module_pointer = module_pointer;
3509         cmd->offset = CPU_TO_LE32(offset);
3510         cmd->length = CPU_TO_LE16(length);
3511
3512         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3513         if (length > I40E_AQ_LARGE_BUF)
3514                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3515
3516         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3517
3518 i40e_aq_read_nvm_exit:
3519         return status;
3520 }
3521
3522 /**
3523  * i40e_aq_read_nvm_config - read an nvm config block
3524  * @hw: pointer to the hw struct
3525  * @cmd_flags: NVM access admin command bits
3526  * @field_id: field or feature id
3527  * @data: buffer for result
3528  * @buf_size: buffer size
3529  * @element_count: pointer to count of elements read by FW
3530  * @cmd_details: pointer to command details structure or NULL
3531  **/
3532 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3533                                 u8 cmd_flags, u32 field_id, void *data,
3534                                 u16 buf_size, u16 *element_count,
3535                                 struct i40e_asq_cmd_details *cmd_details)
3536 {
3537         struct i40e_aq_desc desc;
3538         struct i40e_aqc_nvm_config_read *cmd =
3539                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3540         enum i40e_status_code status;
3541
3542         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3543         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3544         if (buf_size > I40E_AQ_LARGE_BUF)
3545                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3546
3547         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3548         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3549         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3550                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3551         else
3552                 cmd->element_id_msw = 0;
3553
3554         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3555
3556         if (!status && element_count)
3557                 *element_count = LE16_TO_CPU(cmd->element_count);
3558
3559         return status;
3560 }
3561
3562 /**
3563  * i40e_aq_write_nvm_config - write an nvm config block
3564  * @hw: pointer to the hw struct
3565  * @cmd_flags: NVM access admin command bits
3566  * @data: buffer for result
3567  * @buf_size: buffer size
3568  * @element_count: count of elements to be written
3569  * @cmd_details: pointer to command details structure or NULL
3570  **/
3571 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3572                                 u8 cmd_flags, void *data, u16 buf_size,
3573                                 u16 element_count,
3574                                 struct i40e_asq_cmd_details *cmd_details)
3575 {
3576         struct i40e_aq_desc desc;
3577         struct i40e_aqc_nvm_config_write *cmd =
3578                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3579         enum i40e_status_code status;
3580
3581         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3582         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3583         if (buf_size > I40E_AQ_LARGE_BUF)
3584                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3585
3586         cmd->element_count = CPU_TO_LE16(element_count);
3587         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3588         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3589
3590         return status;
3591 }
3592
3593 /**
3594  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3595  * @hw: pointer to the hw struct
3596  * @cmd_details: pointer to command details structure or NULL
3597  **/
3598 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3599                                 void *buff, u16 buff_size,
3600                                 struct i40e_asq_cmd_details *cmd_details)
3601 {
3602         struct i40e_aq_desc desc;
3603         enum i40e_status_code status;
3604
3605         UNREFERENCED_2PARAMETER(buff, buff_size);
3606
3607         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3608         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3609         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3610                 status = I40E_ERR_NOT_IMPLEMENTED;
3611
3612         return status;
3613 }
3614
3615 /**
3616  * i40e_aq_erase_nvm
3617  * @hw: pointer to the hw struct
3618  * @module_pointer: module pointer location in words from the NVM beginning
3619  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3620  * @length: length of the section to be erased (expressed in 4 KB)
3621  * @last_command: tells if this is the last command in a series
3622  * @cmd_details: pointer to command details structure or NULL
3623  *
3624  * Erase the NVM sector using the admin queue commands
3625  **/
3626 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3627                                 u32 offset, u16 length, bool last_command,
3628                                 struct i40e_asq_cmd_details *cmd_details)
3629 {
3630         struct i40e_aq_desc desc;
3631         struct i40e_aqc_nvm_update *cmd =
3632                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3633         enum i40e_status_code status;
3634
3635         DEBUGFUNC("i40e_aq_erase_nvm");
3636
3637         /* In offset the highest byte must be zeroed. */
3638         if (offset & 0xFF000000) {
3639                 status = I40E_ERR_PARAM;
3640                 goto i40e_aq_erase_nvm_exit;
3641         }
3642
3643         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3644
3645         /* If this is the last command in a series, set the proper flag. */
3646         if (last_command)
3647                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3648         cmd->module_pointer = module_pointer;
3649         cmd->offset = CPU_TO_LE32(offset);
3650         cmd->length = CPU_TO_LE16(length);
3651
3652         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3653
3654 i40e_aq_erase_nvm_exit:
3655         return status;
3656 }
3657
3658 /**
3659  * i40e_parse_discover_capabilities
3660  * @hw: pointer to the hw struct
3661  * @buff: pointer to a buffer containing device/function capability records
3662  * @cap_count: number of capability records in the list
3663  * @list_type_opc: type of capabilities list to parse
3664  *
3665  * Parse the device/function capabilities list.
3666  **/
3667 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3668                                      u32 cap_count,
3669                                      enum i40e_admin_queue_opc list_type_opc)
3670 {
3671         struct i40e_aqc_list_capabilities_element_resp *cap;
3672         u32 valid_functions, num_functions;
3673         u32 number, logical_id, phys_id;
3674         struct i40e_hw_capabilities *p;
3675         u8 major_rev;
3676         u32 i = 0;
3677         u16 id;
3678
3679         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3680
3681         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3682                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3683         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3684                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3685         else
3686                 return;
3687
3688         for (i = 0; i < cap_count; i++, cap++) {
3689                 id = LE16_TO_CPU(cap->id);
3690                 number = LE32_TO_CPU(cap->number);
3691                 logical_id = LE32_TO_CPU(cap->logical_id);
3692                 phys_id = LE32_TO_CPU(cap->phys_id);
3693                 major_rev = cap->major_rev;
3694
3695                 switch (id) {
3696                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3697                         p->switch_mode = number;
3698                         i40e_debug(hw, I40E_DEBUG_INIT,
3699                                    "HW Capability: Switch mode = %d\n",
3700                                    p->switch_mode);
3701                         break;
3702                 case I40E_AQ_CAP_ID_MNG_MODE:
3703                         p->management_mode = number;
3704                         if (major_rev > 1) {
3705                                 p->mng_protocols_over_mctp = logical_id;
3706                                 i40e_debug(hw, I40E_DEBUG_INIT,
3707                                            "HW Capability: Protocols over MCTP = %d\n",
3708                                            p->mng_protocols_over_mctp);
3709                         } else {
3710                                 p->mng_protocols_over_mctp = 0;
3711                         }
3712                         i40e_debug(hw, I40E_DEBUG_INIT,
3713                                    "HW Capability: Management Mode = %d\n",
3714                                    p->management_mode);
3715                         break;
3716                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3717                         p->npar_enable = number;
3718                         i40e_debug(hw, I40E_DEBUG_INIT,
3719                                    "HW Capability: NPAR enable = %d\n",
3720                                    p->npar_enable);
3721                         break;
3722                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3723                         p->os2bmc = number;
3724                         i40e_debug(hw, I40E_DEBUG_INIT,
3725                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3726                         break;
3727                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3728                         p->valid_functions = number;
3729                         i40e_debug(hw, I40E_DEBUG_INIT,
3730                                    "HW Capability: Valid Functions = %d\n",
3731                                    p->valid_functions);
3732                         break;
3733                 case I40E_AQ_CAP_ID_SRIOV:
3734                         if (number == 1)
3735                                 p->sr_iov_1_1 = true;
3736                         i40e_debug(hw, I40E_DEBUG_INIT,
3737                                    "HW Capability: SR-IOV = %d\n",
3738                                    p->sr_iov_1_1);
3739                         break;
3740                 case I40E_AQ_CAP_ID_VF:
3741                         p->num_vfs = number;
3742                         p->vf_base_id = logical_id;
3743                         i40e_debug(hw, I40E_DEBUG_INIT,
3744                                    "HW Capability: VF count = %d\n",
3745                                    p->num_vfs);
3746                         i40e_debug(hw, I40E_DEBUG_INIT,
3747                                    "HW Capability: VF base_id = %d\n",
3748                                    p->vf_base_id);
3749                         break;
3750                 case I40E_AQ_CAP_ID_VMDQ:
3751                         if (number == 1)
3752                                 p->vmdq = true;
3753                         i40e_debug(hw, I40E_DEBUG_INIT,
3754                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3755                         break;
3756                 case I40E_AQ_CAP_ID_8021QBG:
3757                         if (number == 1)
3758                                 p->evb_802_1_qbg = true;
3759                         i40e_debug(hw, I40E_DEBUG_INIT,
3760                                    "HW Capability: 802.1Qbg = %d\n", number);
3761                         break;
3762                 case I40E_AQ_CAP_ID_8021QBR:
3763                         if (number == 1)
3764                                 p->evb_802_1_qbh = true;
3765                         i40e_debug(hw, I40E_DEBUG_INIT,
3766                                    "HW Capability: 802.1Qbh = %d\n", number);
3767                         break;
3768                 case I40E_AQ_CAP_ID_VSI:
3769                         p->num_vsis = number;
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: VSI count = %d\n",
3772                                    p->num_vsis);
3773                         break;
3774                 case I40E_AQ_CAP_ID_DCB:
3775                         if (number == 1) {
3776                                 p->dcb = true;
3777                                 p->enabled_tcmap = logical_id;
3778                                 p->maxtc = phys_id;
3779                         }
3780                         i40e_debug(hw, I40E_DEBUG_INIT,
3781                                    "HW Capability: DCB = %d\n", p->dcb);
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: TC Mapping = %d\n",
3784                                    logical_id);
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: TC Max = %d\n", p->maxtc);
3787                         break;
3788                 case I40E_AQ_CAP_ID_FCOE:
3789                         if (number == 1)
3790                                 p->fcoe = true;
3791                         i40e_debug(hw, I40E_DEBUG_INIT,
3792                                    "HW Capability: FCOE = %d\n", p->fcoe);
3793                         break;
3794                 case I40E_AQ_CAP_ID_ISCSI:
3795                         if (number == 1)
3796                                 p->iscsi = true;
3797                         i40e_debug(hw, I40E_DEBUG_INIT,
3798                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3799                         break;
3800                 case I40E_AQ_CAP_ID_RSS:
3801                         p->rss = true;
3802                         p->rss_table_size = number;
3803                         p->rss_table_entry_width = logical_id;
3804                         i40e_debug(hw, I40E_DEBUG_INIT,
3805                                    "HW Capability: RSS = %d\n", p->rss);
3806                         i40e_debug(hw, I40E_DEBUG_INIT,
3807                                    "HW Capability: RSS table size = %d\n",
3808                                    p->rss_table_size);
3809                         i40e_debug(hw, I40E_DEBUG_INIT,
3810                                    "HW Capability: RSS table width = %d\n",
3811                                    p->rss_table_entry_width);
3812                         break;
3813                 case I40E_AQ_CAP_ID_RXQ:
3814                         p->num_rx_qp = number;
3815                         p->base_queue = phys_id;
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: Rx QP = %d\n", number);
3818                         i40e_debug(hw, I40E_DEBUG_INIT,
3819                                    "HW Capability: base_queue = %d\n",
3820                                    p->base_queue);
3821                         break;
3822                 case I40E_AQ_CAP_ID_TXQ:
3823                         p->num_tx_qp = number;
3824                         p->base_queue = phys_id;
3825                         i40e_debug(hw, I40E_DEBUG_INIT,
3826                                    "HW Capability: Tx QP = %d\n", number);
3827                         i40e_debug(hw, I40E_DEBUG_INIT,
3828                                    "HW Capability: base_queue = %d\n",
3829                                    p->base_queue);
3830                         break;
3831                 case I40E_AQ_CAP_ID_MSIX:
3832                         p->num_msix_vectors = number;
3833                         i40e_debug(hw, I40E_DEBUG_INIT,
3834                                    "HW Capability: MSIX vector count = %d\n",
3835                                    p->num_msix_vectors);
3836                         break;
3837                 case I40E_AQ_CAP_ID_VF_MSIX:
3838                         p->num_msix_vectors_vf = number;
3839                         i40e_debug(hw, I40E_DEBUG_INIT,
3840                                    "HW Capability: MSIX VF vector count = %d\n",
3841                                    p->num_msix_vectors_vf);
3842                         break;
3843                 case I40E_AQ_CAP_ID_FLEX10:
3844                         if (major_rev == 1) {
3845                                 if (number == 1) {
3846                                         p->flex10_enable = true;
3847                                         p->flex10_capable = true;
3848                                 }
3849                         } else {
3850                                 /* Capability revision >= 2 */
3851                                 if (number & 1)
3852                                         p->flex10_enable = true;
3853                                 if (number & 2)
3854                                         p->flex10_capable = true;
3855                         }
3856                         p->flex10_mode = logical_id;
3857                         p->flex10_status = phys_id;
3858                         i40e_debug(hw, I40E_DEBUG_INIT,
3859                                    "HW Capability: Flex10 mode = %d\n",
3860                                    p->flex10_mode);
3861                         i40e_debug(hw, I40E_DEBUG_INIT,
3862                                    "HW Capability: Flex10 status = %d\n",
3863                                    p->flex10_status);
3864                         break;
3865                 case I40E_AQ_CAP_ID_CEM:
3866                         if (number == 1)
3867                                 p->mgmt_cem = true;
3868                         i40e_debug(hw, I40E_DEBUG_INIT,
3869                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3870                         break;
3871                 case I40E_AQ_CAP_ID_IWARP:
3872                         if (number == 1)
3873                                 p->iwarp = true;
3874                         i40e_debug(hw, I40E_DEBUG_INIT,
3875                                    "HW Capability: iWARP = %d\n", p->iwarp);
3876                         break;
3877                 case I40E_AQ_CAP_ID_LED:
3878                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3879                                 p->led[phys_id] = true;
3880                         i40e_debug(hw, I40E_DEBUG_INIT,
3881                                    "HW Capability: LED - PIN %d\n", phys_id);
3882                         break;
3883                 case I40E_AQ_CAP_ID_SDP:
3884                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3885                                 p->sdp[phys_id] = true;
3886                         i40e_debug(hw, I40E_DEBUG_INIT,
3887                                    "HW Capability: SDP - PIN %d\n", phys_id);
3888                         break;
3889                 case I40E_AQ_CAP_ID_MDIO:
3890                         if (number == 1) {
3891                                 p->mdio_port_num = phys_id;
3892                                 p->mdio_port_mode = logical_id;
3893                         }
3894                         i40e_debug(hw, I40E_DEBUG_INIT,
3895                                    "HW Capability: MDIO port number = %d\n",
3896                                    p->mdio_port_num);
3897                         i40e_debug(hw, I40E_DEBUG_INIT,
3898                                    "HW Capability: MDIO port mode = %d\n",
3899                                    p->mdio_port_mode);
3900                         break;
3901                 case I40E_AQ_CAP_ID_1588:
3902                         if (number == 1)
3903                                 p->ieee_1588 = true;
3904                         i40e_debug(hw, I40E_DEBUG_INIT,
3905                                    "HW Capability: IEEE 1588 = %d\n",
3906                                    p->ieee_1588);
3907                         break;
3908                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3909                         p->fd = true;
3910                         p->fd_filters_guaranteed = number;
3911                         p->fd_filters_best_effort = logical_id;
3912                         i40e_debug(hw, I40E_DEBUG_INIT,
3913                                    "HW Capability: Flow Director = 1\n");
3914                         i40e_debug(hw, I40E_DEBUG_INIT,
3915                                    "HW Capability: Guaranteed FD filters = %d\n",
3916                                    p->fd_filters_guaranteed);
3917                         break;
3918                 case I40E_AQ_CAP_ID_WSR_PROT:
3919                         p->wr_csr_prot = (u64)number;
3920                         p->wr_csr_prot |= (u64)logical_id << 32;
3921                         i40e_debug(hw, I40E_DEBUG_INIT,
3922                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3923                                    (p->wr_csr_prot & 0xffff));
3924                         break;
3925                 case I40E_AQ_CAP_ID_NVM_MGMT:
3926                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3927                                 p->sec_rev_disabled = true;
3928                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3929                                 p->update_disabled = true;
3930                         break;
3931                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3932                         hw->num_wol_proxy_filters = (u16)number;
3933                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3934                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3935                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3936                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3937                         else
3938                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3939                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3940                         i40e_debug(hw, I40E_DEBUG_INIT,
3941                                    "HW Capability: WOL proxy filters = %d\n",
3942                                    hw->num_wol_proxy_filters);
3943                         break;
3944                 default:
3945                         break;
3946                 }
3947         }
3948
3949         if (p->fcoe)
3950                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3951
3952         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3953         p->fcoe = false;
3954
3955         /* count the enabled ports (aka the "not disabled" ports) */
3956         hw->num_ports = 0;
3957         for (i = 0; i < 4; i++) {
3958                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3959                 u64 port_cfg = 0;
3960
3961                 /* use AQ read to get the physical register offset instead
3962                  * of the port relative offset
3963                  */
3964                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3965                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3966                         hw->num_ports++;
3967         }
3968
3969         valid_functions = p->valid_functions;
3970         num_functions = 0;
3971         while (valid_functions) {
3972                 if (valid_functions & 1)
3973                         num_functions++;
3974                 valid_functions >>= 1;
3975         }
3976
3977         /* partition id is 1-based, and functions are evenly spread
3978          * across the ports as partitions
3979          */
3980         if (hw->num_ports != 0) {
3981                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3982                 hw->num_partitions = num_functions / hw->num_ports;
3983         }
3984
3985         /* additional HW specific goodies that might
3986          * someday be HW version specific
3987          */
3988         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3989 }
3990
3991 /**
3992  * i40e_aq_discover_capabilities
3993  * @hw: pointer to the hw struct
3994  * @buff: a virtual buffer to hold the capabilities
3995  * @buff_size: Size of the virtual buffer
3996  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3997  * @list_type_opc: capabilities type to discover - pass in the command opcode
3998  * @cmd_details: pointer to command details structure or NULL
3999  *
4000  * Get the device capabilities descriptions from the firmware
4001  **/
4002 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4003                                 void *buff, u16 buff_size, u16 *data_size,
4004                                 enum i40e_admin_queue_opc list_type_opc,
4005                                 struct i40e_asq_cmd_details *cmd_details)
4006 {
4007         struct i40e_aqc_list_capabilites *cmd;
4008         struct i40e_aq_desc desc;
4009         enum i40e_status_code status = I40E_SUCCESS;
4010
4011         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4012
4013         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4014                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4015                 status = I40E_ERR_PARAM;
4016                 goto exit;
4017         }
4018
4019         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4020
4021         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4022         if (buff_size > I40E_AQ_LARGE_BUF)
4023                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4024
4025         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4026         *data_size = LE16_TO_CPU(desc.datalen);
4027
4028         if (status)
4029                 goto exit;
4030
4031         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4032                                          list_type_opc);
4033
4034 exit:
4035         return status;
4036 }
4037
4038 /**
4039  * i40e_aq_update_nvm
4040  * @hw: pointer to the hw struct
4041  * @module_pointer: module pointer location in words from the NVM beginning
4042  * @offset: byte offset from the module beginning
4043  * @length: length of the section to be written (in bytes from the offset)
4044  * @data: command buffer (size [bytes] = length)
4045  * @last_command: tells if this is the last command in a series
4046  * @cmd_details: pointer to command details structure or NULL
4047  *
4048  * Update the NVM using the admin queue commands
4049  **/
4050 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4051                                 u32 offset, u16 length, void *data,
4052                                 bool last_command,
4053                                 struct i40e_asq_cmd_details *cmd_details)
4054 {
4055         struct i40e_aq_desc desc;
4056         struct i40e_aqc_nvm_update *cmd =
4057                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4058         enum i40e_status_code status;
4059
4060         DEBUGFUNC("i40e_aq_update_nvm");
4061
4062         /* In offset the highest byte must be zeroed. */
4063         if (offset & 0xFF000000) {
4064                 status = I40E_ERR_PARAM;
4065                 goto i40e_aq_update_nvm_exit;
4066         }
4067
4068         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4069
4070         /* If this is the last command in a series, set the proper flag. */
4071         if (last_command)
4072                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4073         cmd->module_pointer = module_pointer;
4074         cmd->offset = CPU_TO_LE32(offset);
4075         cmd->length = CPU_TO_LE16(length);
4076
4077         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4078         if (length > I40E_AQ_LARGE_BUF)
4079                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4080
4081         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4082
4083 i40e_aq_update_nvm_exit:
4084         return status;
4085 }
4086
4087 /**
4088  * i40e_aq_get_lldp_mib
4089  * @hw: pointer to the hw struct
4090  * @bridge_type: type of bridge requested
4091  * @mib_type: Local, Remote or both Local and Remote MIBs
4092  * @buff: pointer to a user supplied buffer to store the MIB block
4093  * @buff_size: size of the buffer (in bytes)
4094  * @local_len : length of the returned Local LLDP MIB
4095  * @remote_len: length of the returned Remote LLDP MIB
4096  * @cmd_details: pointer to command details structure or NULL
4097  *
4098  * Requests the complete LLDP MIB (entire packet).
4099  **/
4100 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4101                                 u8 mib_type, void *buff, u16 buff_size,
4102                                 u16 *local_len, u16 *remote_len,
4103                                 struct i40e_asq_cmd_details *cmd_details)
4104 {
4105         struct i40e_aq_desc desc;
4106         struct i40e_aqc_lldp_get_mib *cmd =
4107                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4108         struct i40e_aqc_lldp_get_mib *resp =
4109                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4110         enum i40e_status_code status;
4111
4112         if (buff_size == 0 || !buff)
4113                 return I40E_ERR_PARAM;
4114
4115         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4116         /* Indirect Command */
4117         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4118
4119         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4120         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4121                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4122
4123         desc.datalen = CPU_TO_LE16(buff_size);
4124
4125         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4126         if (buff_size > I40E_AQ_LARGE_BUF)
4127                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4128
4129         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4130         if (!status) {
4131                 if (local_len != NULL)
4132                         *local_len = LE16_TO_CPU(resp->local_len);
4133                 if (remote_len != NULL)
4134                         *remote_len = LE16_TO_CPU(resp->remote_len);
4135         }
4136
4137         return status;
4138 }
4139
4140  /**
4141  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4142  * @hw: pointer to the hw struct
4143  * @mib_type: Local, Remote or both Local and Remote MIBs
4144  * @buff: pointer to a user supplied buffer to store the MIB block
4145  * @buff_size: size of the buffer (in bytes)
4146  * @cmd_details: pointer to command details structure or NULL
4147  *
4148  * Set the LLDP MIB.
4149  **/
4150 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4151                                 u8 mib_type, void *buff, u16 buff_size,
4152                                 struct i40e_asq_cmd_details *cmd_details)
4153 {
4154         struct i40e_aq_desc desc;
4155         struct i40e_aqc_lldp_set_local_mib *cmd =
4156                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4157         enum i40e_status_code status;
4158
4159         if (buff_size == 0 || !buff)
4160                 return I40E_ERR_PARAM;
4161
4162         i40e_fill_default_direct_cmd_desc(&desc,
4163                                 i40e_aqc_opc_lldp_set_local_mib);
4164         /* Indirect Command */
4165         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4166         if (buff_size > I40E_AQ_LARGE_BUF)
4167                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4168         desc.datalen = CPU_TO_LE16(buff_size);
4169
4170         cmd->type = mib_type;
4171         cmd->length = CPU_TO_LE16(buff_size);
4172         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4173         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4174
4175         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4176         return status;
4177 }
4178
4179 /**
4180  * i40e_aq_cfg_lldp_mib_change_event
4181  * @hw: pointer to the hw struct
4182  * @enable_update: Enable or Disable event posting
4183  * @cmd_details: pointer to command details structure or NULL
4184  *
4185  * Enable or Disable posting of an event on ARQ when LLDP MIB
4186  * associated with the interface changes
4187  **/
4188 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4189                                 bool enable_update,
4190                                 struct i40e_asq_cmd_details *cmd_details)
4191 {
4192         struct i40e_aq_desc desc;
4193         struct i40e_aqc_lldp_update_mib *cmd =
4194                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4195         enum i40e_status_code status;
4196
4197         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4198
4199         if (!enable_update)
4200                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4201
4202         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4203
4204         return status;
4205 }
4206
4207 /**
4208  * i40e_aq_add_lldp_tlv
4209  * @hw: pointer to the hw struct
4210  * @bridge_type: type of bridge
4211  * @buff: buffer with TLV to add
4212  * @buff_size: length of the buffer
4213  * @tlv_len: length of the TLV to be added
4214  * @mib_len: length of the LLDP MIB returned in response
4215  * @cmd_details: pointer to command details structure or NULL
4216  *
4217  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4218  * it is responsibility of the caller to make sure that the TLV is not
4219  * already present in the LLDPDU.
4220  * In return firmware will write the complete LLDP MIB with the newly
4221  * added TLV in the response buffer.
4222  **/
4223 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4224                                 void *buff, u16 buff_size, u16 tlv_len,
4225                                 u16 *mib_len,
4226                                 struct i40e_asq_cmd_details *cmd_details)
4227 {
4228         struct i40e_aq_desc desc;
4229         struct i40e_aqc_lldp_add_tlv *cmd =
4230                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4231         enum i40e_status_code status;
4232
4233         if (buff_size == 0 || !buff || tlv_len == 0)
4234                 return I40E_ERR_PARAM;
4235
4236         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4237
4238         /* Indirect Command */
4239         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4240         if (buff_size > I40E_AQ_LARGE_BUF)
4241                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4242         desc.datalen = CPU_TO_LE16(buff_size);
4243
4244         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4245                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4246         cmd->len = CPU_TO_LE16(tlv_len);
4247
4248         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4249         if (!status) {
4250                 if (mib_len != NULL)
4251                         *mib_len = LE16_TO_CPU(desc.datalen);
4252         }
4253
4254         return status;
4255 }
4256
4257 /**
4258  * i40e_aq_update_lldp_tlv
4259  * @hw: pointer to the hw struct
4260  * @bridge_type: type of bridge
4261  * @buff: buffer with TLV to update
4262  * @buff_size: size of the buffer holding original and updated TLVs
4263  * @old_len: Length of the Original TLV
4264  * @new_len: Length of the Updated TLV
4265  * @offset: offset of the updated TLV in the buff
4266  * @mib_len: length of the returned LLDP MIB
4267  * @cmd_details: pointer to command details structure or NULL
4268  *
4269  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4270  * Firmware will place the complete LLDP MIB in response buffer with the
4271  * updated TLV.
4272  **/
4273 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4274                                 u8 bridge_type, void *buff, u16 buff_size,
4275                                 u16 old_len, u16 new_len, u16 offset,
4276                                 u16 *mib_len,
4277                                 struct i40e_asq_cmd_details *cmd_details)
4278 {
4279         struct i40e_aq_desc desc;
4280         struct i40e_aqc_lldp_update_tlv *cmd =
4281                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4282         enum i40e_status_code status;
4283
4284         if (buff_size == 0 || !buff || offset == 0 ||
4285             old_len == 0 || new_len == 0)
4286                 return I40E_ERR_PARAM;
4287
4288         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4289
4290         /* Indirect Command */
4291         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4292         if (buff_size > I40E_AQ_LARGE_BUF)
4293                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4294         desc.datalen = CPU_TO_LE16(buff_size);
4295
4296         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4297                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4298         cmd->old_len = CPU_TO_LE16(old_len);
4299         cmd->new_offset = CPU_TO_LE16(offset);
4300         cmd->new_len = CPU_TO_LE16(new_len);
4301
4302         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4303         if (!status) {
4304                 if (mib_len != NULL)
4305                         *mib_len = LE16_TO_CPU(desc.datalen);
4306         }
4307
4308         return status;
4309 }
4310
4311 /**
4312  * i40e_aq_delete_lldp_tlv
4313  * @hw: pointer to the hw struct
4314  * @bridge_type: type of bridge
4315  * @buff: pointer to a user supplied buffer that has the TLV
4316  * @buff_size: length of the buffer
4317  * @tlv_len: length of the TLV to be deleted
4318  * @mib_len: length of the returned LLDP MIB
4319  * @cmd_details: pointer to command details structure or NULL
4320  *
4321  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4322  * The firmware places the entire LLDP MIB in the response buffer.
4323  **/
4324 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4325                                 u8 bridge_type, void *buff, u16 buff_size,
4326                                 u16 tlv_len, u16 *mib_len,
4327                                 struct i40e_asq_cmd_details *cmd_details)
4328 {
4329         struct i40e_aq_desc desc;
4330         struct i40e_aqc_lldp_add_tlv *cmd =
4331                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4332         enum i40e_status_code status;
4333
4334         if (buff_size == 0 || !buff)
4335                 return I40E_ERR_PARAM;
4336
4337         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4338
4339         /* Indirect Command */
4340         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4341         if (buff_size > I40E_AQ_LARGE_BUF)
4342                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4343         desc.datalen = CPU_TO_LE16(buff_size);
4344         cmd->len = CPU_TO_LE16(tlv_len);
4345         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4346                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4347
4348         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4349         if (!status) {
4350                 if (mib_len != NULL)
4351                         *mib_len = LE16_TO_CPU(desc.datalen);
4352         }
4353
4354         return status;
4355 }
4356
4357 /**
4358  * i40e_aq_stop_lldp
4359  * @hw: pointer to the hw struct
4360  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4361  * @cmd_details: pointer to command details structure or NULL
4362  *
4363  * Stop or Shutdown the embedded LLDP Agent
4364  **/
4365 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4366                                 struct i40e_asq_cmd_details *cmd_details)
4367 {
4368         struct i40e_aq_desc desc;
4369         struct i40e_aqc_lldp_stop *cmd =
4370                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4371         enum i40e_status_code status;
4372
4373         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4374
4375         if (shutdown_agent)
4376                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4377
4378         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4379
4380         return status;
4381 }
4382
4383 /**
4384  * i40e_aq_start_lldp
4385  * @hw: pointer to the hw struct
4386  * @cmd_details: pointer to command details structure or NULL
4387  *
4388  * Start the embedded LLDP Agent on all ports.
4389  **/
4390 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4391                                 struct i40e_asq_cmd_details *cmd_details)
4392 {
4393         struct i40e_aq_desc desc;
4394         struct i40e_aqc_lldp_start *cmd =
4395                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4396         enum i40e_status_code status;
4397
4398         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4399
4400         cmd->command = I40E_AQ_LLDP_AGENT_START;
4401
4402         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4403
4404         return status;
4405 }
4406
4407 /**
4408  * i40e_aq_get_cee_dcb_config
4409  * @hw: pointer to the hw struct
4410  * @buff: response buffer that stores CEE operational configuration
4411  * @buff_size: size of the buffer passed
4412  * @cmd_details: pointer to command details structure or NULL
4413  *
4414  * Get CEE DCBX mode operational configuration from firmware
4415  **/
4416 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4417                                 void *buff, u16 buff_size,
4418                                 struct i40e_asq_cmd_details *cmd_details)
4419 {
4420         struct i40e_aq_desc desc;
4421         enum i40e_status_code status;
4422
4423         if (buff_size == 0 || !buff)
4424                 return I40E_ERR_PARAM;
4425
4426         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4427
4428         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4429         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4430                                        cmd_details);
4431
4432         return status;
4433 }
4434
4435 /**
4436  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4437  * @hw: pointer to the hw struct
4438  * @start_agent: True if DCBx Agent needs to be Started
4439  *                              False if DCBx Agent needs to be Stopped
4440  * @cmd_details: pointer to command details structure or NULL
4441  *
4442  * Start/Stop the embedded dcbx Agent
4443  **/
4444 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4445                                 bool start_agent,
4446                                 struct i40e_asq_cmd_details *cmd_details)
4447 {
4448         struct i40e_aq_desc desc;
4449         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4450                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4451                                 &desc.params.raw;
4452         enum i40e_status_code status;
4453
4454         i40e_fill_default_direct_cmd_desc(&desc,
4455                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4456
4457         if (start_agent)
4458                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4459
4460         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4461
4462         return status;
4463 }
4464
4465 /**
4466  * i40e_aq_add_udp_tunnel
4467  * @hw: pointer to the hw struct
4468  * @udp_port: the UDP port to add in Host byte order
4469  * @header_len: length of the tunneling header length in DWords
4470  * @protocol_index: protocol index type
4471  * @filter_index: pointer to filter index
4472  * @cmd_details: pointer to command details structure or NULL
4473  *
4474  * Note: Firmware expects the udp_port value to be in Little Endian format,
4475  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4476  * Little Endian order.
4477  **/
4478 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4479                                 u16 udp_port, u8 protocol_index,
4480                                 u8 *filter_index,
4481                                 struct i40e_asq_cmd_details *cmd_details)
4482 {
4483         struct i40e_aq_desc desc;
4484         struct i40e_aqc_add_udp_tunnel *cmd =
4485                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4486         struct i40e_aqc_del_udp_tunnel_completion *resp =
4487                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4488         enum i40e_status_code status;
4489
4490         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4491
4492         cmd->udp_port = CPU_TO_LE16(udp_port);
4493         cmd->protocol_type = protocol_index;
4494
4495         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4496
4497         if (!status && filter_index)
4498                 *filter_index = resp->index;
4499
4500         return status;
4501 }
4502
4503 /**
4504  * i40e_aq_del_udp_tunnel
4505  * @hw: pointer to the hw struct
4506  * @index: filter index
4507  * @cmd_details: pointer to command details structure or NULL
4508  **/
4509 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4510                                 struct i40e_asq_cmd_details *cmd_details)
4511 {
4512         struct i40e_aq_desc desc;
4513         struct i40e_aqc_remove_udp_tunnel *cmd =
4514                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4515         enum i40e_status_code status;
4516
4517         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4518
4519         cmd->index = index;
4520
4521         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4522
4523         return status;
4524 }
4525
4526 /**
4527  * i40e_aq_get_switch_resource_alloc (0x0204)
4528  * @hw: pointer to the hw struct
4529  * @num_entries: pointer to u8 to store the number of resource entries returned
4530  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4531  *        to store the resource information for all resource types.  Each
4532  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4533  * @count: size, in bytes, of the buffer provided
4534  * @cmd_details: pointer to command details structure or NULL
4535  *
4536  * Query the resources allocated to a function.
4537  **/
4538 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4539                         u8 *num_entries,
4540                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4541                         u16 count,
4542                         struct i40e_asq_cmd_details *cmd_details)
4543 {
4544         struct i40e_aq_desc desc;
4545         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4546                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4547         enum i40e_status_code status;
4548         u16 length = count * sizeof(*buf);
4549
4550         i40e_fill_default_direct_cmd_desc(&desc,
4551                                         i40e_aqc_opc_get_switch_resource_alloc);
4552
4553         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4554         if (length > I40E_AQ_LARGE_BUF)
4555                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4556
4557         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4558
4559         if (!status && num_entries)
4560                 *num_entries = cmd_resp->num_entries;
4561
4562         return status;
4563 }
4564
4565 /**
4566  * i40e_aq_delete_element - Delete switch element
4567  * @hw: pointer to the hw struct
4568  * @seid: the SEID to delete from the switch
4569  * @cmd_details: pointer to command details structure or NULL
4570  *
4571  * This deletes a switch element from the switch.
4572  **/
4573 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4574                                 struct i40e_asq_cmd_details *cmd_details)
4575 {
4576         struct i40e_aq_desc desc;
4577         struct i40e_aqc_switch_seid *cmd =
4578                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4579         enum i40e_status_code status;
4580
4581         if (seid == 0)
4582                 return I40E_ERR_PARAM;
4583
4584         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4585
4586         cmd->seid = CPU_TO_LE16(seid);
4587
4588         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4589
4590         return status;
4591 }
4592
4593 /**
4594  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4595  * @hw: pointer to the hw struct
4596  * @flags: component flags
4597  * @mac_seid: uplink seid (MAC SEID)
4598  * @vsi_seid: connected vsi seid
4599  * @ret_seid: seid of create pv component
4600  *
4601  * This instantiates an i40e port virtualizer with specified flags.
4602  * Depending on specified flags the port virtualizer can act as a
4603  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4604  */
4605 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4606                                        u16 mac_seid, u16 vsi_seid,
4607                                        u16 *ret_seid)
4608 {
4609         struct i40e_aq_desc desc;
4610         struct i40e_aqc_add_update_pv *cmd =
4611                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4612         struct i40e_aqc_add_update_pv_completion *resp =
4613                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4614         enum i40e_status_code status;
4615
4616         if (vsi_seid == 0)
4617                 return I40E_ERR_PARAM;
4618
4619         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4620         cmd->command_flags = CPU_TO_LE16(flags);
4621         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4622         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4623
4624         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4625         if (!status && ret_seid)
4626                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4627
4628         return status;
4629 }
4630
4631 /**
4632  * i40e_aq_add_tag - Add an S/E-tag
4633  * @hw: pointer to the hw struct
4634  * @direct_to_queue: should s-tag direct flow to a specific queue
4635  * @vsi_seid: VSI SEID to use this tag
4636  * @tag: value of the tag
4637  * @queue_num: queue number, only valid is direct_to_queue is true
4638  * @tags_used: return value, number of tags in use by this PF
4639  * @tags_free: return value, number of unallocated tags
4640  * @cmd_details: pointer to command details structure or NULL
4641  *
4642  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4643  * the number of tags allocated by the PF, and the number of unallocated
4644  * tags available.
4645  **/
4646 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4647                                 u16 vsi_seid, u16 tag, u16 queue_num,
4648                                 u16 *tags_used, u16 *tags_free,
4649                                 struct i40e_asq_cmd_details *cmd_details)
4650 {
4651         struct i40e_aq_desc desc;
4652         struct i40e_aqc_add_tag *cmd =
4653                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4654         struct i40e_aqc_add_remove_tag_completion *resp =
4655                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4656         enum i40e_status_code status;
4657
4658         if (vsi_seid == 0)
4659                 return I40E_ERR_PARAM;
4660
4661         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4662
4663         cmd->seid = CPU_TO_LE16(vsi_seid);
4664         cmd->tag = CPU_TO_LE16(tag);
4665         if (direct_to_queue) {
4666                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4667                 cmd->queue_number = CPU_TO_LE16(queue_num);
4668         }
4669
4670         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4671
4672         if (!status) {
4673                 if (tags_used != NULL)
4674                         *tags_used = LE16_TO_CPU(resp->tags_used);
4675                 if (tags_free != NULL)
4676                         *tags_free = LE16_TO_CPU(resp->tags_free);
4677         }
4678
4679         return status;
4680 }
4681
4682 /**
4683  * i40e_aq_remove_tag - Remove an S- or E-tag
4684  * @hw: pointer to the hw struct
4685  * @vsi_seid: VSI SEID this tag is associated with
4686  * @tag: value of the S-tag to delete
4687  * @tags_used: return value, number of tags in use by this PF
4688  * @tags_free: return value, number of unallocated tags
4689  * @cmd_details: pointer to command details structure or NULL
4690  *
4691  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4692  * the number of tags allocated by the PF, and the number of unallocated
4693  * tags available.
4694  **/
4695 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4696                                 u16 tag, u16 *tags_used, u16 *tags_free,
4697                                 struct i40e_asq_cmd_details *cmd_details)
4698 {
4699         struct i40e_aq_desc desc;
4700         struct i40e_aqc_remove_tag *cmd =
4701                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4702         struct i40e_aqc_add_remove_tag_completion *resp =
4703                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4704         enum i40e_status_code status;
4705
4706         if (vsi_seid == 0)
4707                 return I40E_ERR_PARAM;
4708
4709         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4710
4711         cmd->seid = CPU_TO_LE16(vsi_seid);
4712         cmd->tag = CPU_TO_LE16(tag);
4713
4714         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4715
4716         if (!status) {
4717                 if (tags_used != NULL)
4718                         *tags_used = LE16_TO_CPU(resp->tags_used);
4719                 if (tags_free != NULL)
4720                         *tags_free = LE16_TO_CPU(resp->tags_free);
4721         }
4722
4723         return status;
4724 }
4725
4726 /**
4727  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4728  * @hw: pointer to the hw struct
4729  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4730  * @etag: value of E-tag to add
4731  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4732  * @buf: address of indirect buffer
4733  * @tags_used: return value, number of E-tags in use by this port
4734  * @tags_free: return value, number of unallocated M-tags
4735  * @cmd_details: pointer to command details structure or NULL
4736  *
4737  * This associates a multicast E-tag to a port virtualizer.  It will return
4738  * the number of tags allocated by the PF, and the number of unallocated
4739  * tags available.
4740  *
4741  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4742  * num_tags_in_buf long.
4743  **/
4744 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4745                                 u16 etag, u8 num_tags_in_buf, void *buf,
4746                                 u16 *tags_used, u16 *tags_free,
4747                                 struct i40e_asq_cmd_details *cmd_details)
4748 {
4749         struct i40e_aq_desc desc;
4750         struct i40e_aqc_add_remove_mcast_etag *cmd =
4751                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4752         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4753            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4754         enum i40e_status_code status;
4755         u16 length = sizeof(u16) * num_tags_in_buf;
4756
4757         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4758                 return I40E_ERR_PARAM;
4759
4760         i40e_fill_default_direct_cmd_desc(&desc,
4761                                           i40e_aqc_opc_add_multicast_etag);
4762
4763         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4764         cmd->etag = CPU_TO_LE16(etag);
4765         cmd->num_unicast_etags = num_tags_in_buf;
4766
4767         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4768         if (length > I40E_AQ_LARGE_BUF)
4769                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4770
4771         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4772
4773         if (!status) {
4774                 if (tags_used != NULL)
4775                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4776                 if (tags_free != NULL)
4777                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4778         }
4779
4780         return status;
4781 }
4782
4783 /**
4784  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4785  * @hw: pointer to the hw struct
4786  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4787  * @etag: value of the E-tag to remove
4788  * @tags_used: return value, number of tags in use by this port
4789  * @tags_free: return value, number of unallocated tags
4790  * @cmd_details: pointer to command details structure or NULL
4791  *
4792  * This deletes an E-tag from the port virtualizer.  It will return
4793  * the number of tags allocated by the port, and the number of unallocated
4794  * tags available.
4795  **/
4796 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4797                                 u16 etag, u16 *tags_used, u16 *tags_free,
4798                                 struct i40e_asq_cmd_details *cmd_details)
4799 {
4800         struct i40e_aq_desc desc;
4801         struct i40e_aqc_add_remove_mcast_etag *cmd =
4802                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4803         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4804            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4805         enum i40e_status_code status;
4806
4807
4808         if (pv_seid == 0)
4809                 return I40E_ERR_PARAM;
4810
4811         i40e_fill_default_direct_cmd_desc(&desc,
4812                                           i40e_aqc_opc_remove_multicast_etag);
4813
4814         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4815         cmd->etag = CPU_TO_LE16(etag);
4816
4817         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4818
4819         if (!status) {
4820                 if (tags_used != NULL)
4821                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4822                 if (tags_free != NULL)
4823                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4824         }
4825
4826         return status;
4827 }
4828
4829 /**
4830  * i40e_aq_update_tag - Update an S/E-tag
4831  * @hw: pointer to the hw struct
4832  * @vsi_seid: VSI SEID using this S-tag
4833  * @old_tag: old tag value
4834  * @new_tag: new tag value
4835  * @tags_used: return value, number of tags in use by this PF
4836  * @tags_free: return value, number of unallocated tags
4837  * @cmd_details: pointer to command details structure or NULL
4838  *
4839  * This updates the value of the tag currently attached to this VSI
4840  * in the switch complex.  It will return the number of tags allocated
4841  * by the PF, and the number of unallocated tags available.
4842  **/
4843 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4844                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4845                                 u16 *tags_free,
4846                                 struct i40e_asq_cmd_details *cmd_details)
4847 {
4848         struct i40e_aq_desc desc;
4849         struct i40e_aqc_update_tag *cmd =
4850                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4851         struct i40e_aqc_update_tag_completion *resp =
4852                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4853         enum i40e_status_code status;
4854
4855         if (vsi_seid == 0)
4856                 return I40E_ERR_PARAM;
4857
4858         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4859
4860         cmd->seid = CPU_TO_LE16(vsi_seid);
4861         cmd->old_tag = CPU_TO_LE16(old_tag);
4862         cmd->new_tag = CPU_TO_LE16(new_tag);
4863
4864         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4865
4866         if (!status) {
4867                 if (tags_used != NULL)
4868                         *tags_used = LE16_TO_CPU(resp->tags_used);
4869                 if (tags_free != NULL)
4870                         *tags_free = LE16_TO_CPU(resp->tags_free);
4871         }
4872
4873         return status;
4874 }
4875
4876 /**
4877  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4878  * @hw: pointer to the hw struct
4879  * @tcmap: TC map for request/release any ignore PFC condition
4880  * @request: request or release ignore PFC condition
4881  * @tcmap_ret: return TCs for which PFC is currently ignored
4882  * @cmd_details: pointer to command details structure or NULL
4883  *
4884  * This sends out request/release to ignore PFC condition for a TC.
4885  * It will return the TCs for which PFC is currently ignored.
4886  **/
4887 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4888                                 bool request, u8 *tcmap_ret,
4889                                 struct i40e_asq_cmd_details *cmd_details)
4890 {
4891         struct i40e_aq_desc desc;
4892         struct i40e_aqc_pfc_ignore *cmd_resp =
4893                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4894         enum i40e_status_code status;
4895
4896         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4897
4898         if (request)
4899                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4900
4901         cmd_resp->tc_bitmap = tcmap;
4902
4903         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4904
4905         if (!status) {
4906                 if (tcmap_ret != NULL)
4907                         *tcmap_ret = cmd_resp->tc_bitmap;
4908         }
4909
4910         return status;
4911 }
4912
4913 /**
4914  * i40e_aq_dcb_updated - DCB Updated Command
4915  * @hw: pointer to the hw struct
4916  * @cmd_details: pointer to command details structure or NULL
4917  *
4918  * When LLDP is handled in PF this command is used by the PF
4919  * to notify EMP that a DCB setting is modified.
4920  * When LLDP is handled in EMP this command is used by the PF
4921  * to notify EMP whenever one of the following parameters get
4922  * modified:
4923  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4924  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4925  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4926  * EMP will return when the shared RPB settings have been
4927  * recomputed and modified. The retval field in the descriptor
4928  * will be set to 0 when RPB is modified.
4929  **/
4930 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4931                                 struct i40e_asq_cmd_details *cmd_details)
4932 {
4933         struct i40e_aq_desc desc;
4934         enum i40e_status_code status;
4935
4936         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4937
4938         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4939
4940         return status;
4941 }
4942
4943 /**
4944  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4945  * @hw: pointer to the hw struct
4946  * @seid: defines the SEID of the switch for which the stats are requested
4947  * @vlan_id: the VLAN ID for which the statistics are requested
4948  * @stat_index: index of the statistics counters block assigned to this VLAN
4949  * @cmd_details: pointer to command details structure or NULL
4950  *
4951  * XL710 supports 128 smonVlanStats counters.This command is used to
4952  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4953  * switch.
4954  **/
4955 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4956                                 u16 vlan_id, u16 *stat_index,
4957                                 struct i40e_asq_cmd_details *cmd_details)
4958 {
4959         struct i40e_aq_desc desc;
4960         struct i40e_aqc_add_remove_statistics *cmd_resp =
4961                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4962         enum i40e_status_code status;
4963
4964         if ((seid == 0) || (stat_index == NULL))
4965                 return I40E_ERR_PARAM;
4966
4967         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4968
4969         cmd_resp->seid = CPU_TO_LE16(seid);
4970         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4971
4972         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4973
4974         if (!status && stat_index)
4975                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4976
4977         return status;
4978 }
4979
4980 /**
4981  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4982  * @hw: pointer to the hw struct
4983  * @seid: defines the SEID of the switch for which the stats are requested
4984  * @vlan_id: the VLAN ID for which the statistics are requested
4985  * @stat_index: index of the statistics counters block assigned to this VLAN
4986  * @cmd_details: pointer to command details structure or NULL
4987  *
4988  * XL710 supports 128 smonVlanStats counters.This command is used to
4989  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4990  * switch.
4991  **/
4992 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4993                                 u16 vlan_id, u16 stat_index,
4994                                 struct i40e_asq_cmd_details *cmd_details)
4995 {
4996         struct i40e_aq_desc desc;
4997         struct i40e_aqc_add_remove_statistics *cmd =
4998                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4999         enum i40e_status_code status;
5000
5001         if (seid == 0)
5002                 return I40E_ERR_PARAM;
5003
5004         i40e_fill_default_direct_cmd_desc(&desc,
5005                                           i40e_aqc_opc_remove_statistics);
5006
5007         cmd->seid = CPU_TO_LE16(seid);
5008         cmd->vlan  = CPU_TO_LE16(vlan_id);
5009         cmd->stat_index = CPU_TO_LE16(stat_index);
5010
5011         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5012
5013         return status;
5014 }
5015
5016 /**
5017  * i40e_aq_set_port_parameters - set physical port parameters.
5018  * @hw: pointer to the hw struct
5019  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5020  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5021  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5022  * @double_vlan: if set double VLAN is enabled
5023  * @cmd_details: pointer to command details structure or NULL
5024  **/
5025 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5026                                 u16 bad_frame_vsi, bool save_bad_pac,
5027                                 bool pad_short_pac, bool double_vlan,
5028                                 struct i40e_asq_cmd_details *cmd_details)
5029 {
5030         struct i40e_aqc_set_port_parameters *cmd;
5031         enum i40e_status_code status;
5032         struct i40e_aq_desc desc;
5033         u16 command_flags = 0;
5034
5035         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5036
5037         i40e_fill_default_direct_cmd_desc(&desc,
5038                                           i40e_aqc_opc_set_port_parameters);
5039
5040         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5041         if (save_bad_pac)
5042                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5043         if (pad_short_pac)
5044                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5045         if (double_vlan)
5046                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5047         cmd->command_flags = CPU_TO_LE16(command_flags);
5048
5049         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5050
5051         return status;
5052 }
5053
5054 /**
5055  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5056  * @hw: pointer to the hw struct
5057  * @seid: seid for the physical port/switching component/vsi
5058  * @buff: Indirect buffer to hold data parameters and response
5059  * @buff_size: Indirect buffer size
5060  * @opcode: Tx scheduler AQ command opcode
5061  * @cmd_details: pointer to command details structure or NULL
5062  *
5063  * Generic command handler for Tx scheduler AQ commands
5064  **/
5065 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5066                                 void *buff, u16 buff_size,
5067                                  enum i40e_admin_queue_opc opcode,
5068                                 struct i40e_asq_cmd_details *cmd_details)
5069 {
5070         struct i40e_aq_desc desc;
5071         struct i40e_aqc_tx_sched_ind *cmd =
5072                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5073         enum i40e_status_code status;
5074         bool cmd_param_flag = false;
5075
5076         switch (opcode) {
5077         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5078         case i40e_aqc_opc_configure_vsi_tc_bw:
5079         case i40e_aqc_opc_enable_switching_comp_ets:
5080         case i40e_aqc_opc_modify_switching_comp_ets:
5081         case i40e_aqc_opc_disable_switching_comp_ets:
5082         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5083         case i40e_aqc_opc_configure_switching_comp_bw_config:
5084                 cmd_param_flag = true;
5085                 break;
5086         case i40e_aqc_opc_query_vsi_bw_config:
5087         case i40e_aqc_opc_query_vsi_ets_sla_config:
5088         case i40e_aqc_opc_query_switching_comp_ets_config:
5089         case i40e_aqc_opc_query_port_ets_config:
5090         case i40e_aqc_opc_query_switching_comp_bw_config:
5091                 cmd_param_flag = false;
5092                 break;
5093         default:
5094                 return I40E_ERR_PARAM;
5095         }
5096
5097         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5098
5099         /* Indirect command */
5100         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5101         if (cmd_param_flag)
5102                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5103         if (buff_size > I40E_AQ_LARGE_BUF)
5104                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5105
5106         desc.datalen = CPU_TO_LE16(buff_size);
5107
5108         cmd->vsi_seid = CPU_TO_LE16(seid);
5109
5110         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5111
5112         return status;
5113 }
5114
5115 /**
5116  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5117  * @hw: pointer to the hw struct
5118  * @seid: VSI seid
5119  * @credit: BW limit credits (0 = disabled)
5120  * @max_credit: Max BW limit credits
5121  * @cmd_details: pointer to command details structure or NULL
5122  **/
5123 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5124                                 u16 seid, u16 credit, u8 max_credit,
5125                                 struct i40e_asq_cmd_details *cmd_details)
5126 {
5127         struct i40e_aq_desc desc;
5128         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5129                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5130         enum i40e_status_code status;
5131
5132         i40e_fill_default_direct_cmd_desc(&desc,
5133                                           i40e_aqc_opc_configure_vsi_bw_limit);
5134
5135         cmd->vsi_seid = CPU_TO_LE16(seid);
5136         cmd->credit = CPU_TO_LE16(credit);
5137         cmd->max_credit = max_credit;
5138
5139         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5140
5141         return status;
5142 }
5143
5144 /**
5145  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5146  * @hw: pointer to the hw struct
5147  * @seid: switching component seid
5148  * @credit: BW limit credits (0 = disabled)
5149  * @max_bw: Max BW limit credits
5150  * @cmd_details: pointer to command details structure or NULL
5151  **/
5152 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5153                                 u16 seid, u16 credit, u8 max_bw,
5154                                 struct i40e_asq_cmd_details *cmd_details)
5155 {
5156         struct i40e_aq_desc desc;
5157         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5158           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5159         enum i40e_status_code status;
5160
5161         i40e_fill_default_direct_cmd_desc(&desc,
5162                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5163
5164         cmd->seid = CPU_TO_LE16(seid);
5165         cmd->credit = CPU_TO_LE16(credit);
5166         cmd->max_bw = max_bw;
5167
5168         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5169
5170         return status;
5171 }
5172
5173 /**
5174  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5175  * @hw: pointer to the hw struct
5176  * @seid: VSI seid
5177  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5178  * @cmd_details: pointer to command details structure or NULL
5179  **/
5180 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5181                         u16 seid,
5182                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5183                         struct i40e_asq_cmd_details *cmd_details)
5184 {
5185         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5186                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5187                                     cmd_details);
5188 }
5189
5190 /**
5191  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5192  * @hw: pointer to the hw struct
5193  * @seid: VSI seid
5194  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5195  * @cmd_details: pointer to command details structure or NULL
5196  **/
5197 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5198                         u16 seid,
5199                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5200                         struct i40e_asq_cmd_details *cmd_details)
5201 {
5202         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5203                                     i40e_aqc_opc_configure_vsi_tc_bw,
5204                                     cmd_details);
5205 }
5206
5207 /**
5208  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5209  * @hw: pointer to the hw struct
5210  * @seid: seid of the switching component connected to Physical Port
5211  * @ets_data: Buffer holding ETS parameters
5212  * @cmd_details: pointer to command details structure or NULL
5213  **/
5214 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5215                 u16 seid,
5216                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5217                 enum i40e_admin_queue_opc opcode,
5218                 struct i40e_asq_cmd_details *cmd_details)
5219 {
5220         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5221                                     sizeof(*ets_data), opcode, cmd_details);
5222 }
5223
5224 /**
5225  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5226  * @hw: pointer to the hw struct
5227  * @seid: seid of the switching component
5228  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5229  * @cmd_details: pointer to command details structure or NULL
5230  **/
5231 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5232         u16 seid,
5233         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5234         struct i40e_asq_cmd_details *cmd_details)
5235 {
5236         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5237                             i40e_aqc_opc_configure_switching_comp_bw_config,
5238                             cmd_details);
5239 }
5240
5241 /**
5242  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5243  * @hw: pointer to the hw struct
5244  * @seid: seid of the switching component
5245  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5246  * @cmd_details: pointer to command details structure or NULL
5247  **/
5248 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5249         struct i40e_hw *hw, u16 seid,
5250         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5251         struct i40e_asq_cmd_details *cmd_details)
5252 {
5253         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5254                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5255                             cmd_details);
5256 }
5257
5258 /**
5259  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5260  * @hw: pointer to the hw struct
5261  * @seid: seid of the VSI
5262  * @bw_data: Buffer to hold VSI BW configuration
5263  * @cmd_details: pointer to command details structure or NULL
5264  **/
5265 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5266                         u16 seid,
5267                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5268                         struct i40e_asq_cmd_details *cmd_details)
5269 {
5270         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5271                                     i40e_aqc_opc_query_vsi_bw_config,
5272                                     cmd_details);
5273 }
5274
5275 /**
5276  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5277  * @hw: pointer to the hw struct
5278  * @seid: seid of the VSI
5279  * @bw_data: Buffer to hold VSI BW configuration per TC
5280  * @cmd_details: pointer to command details structure or NULL
5281  **/
5282 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5283                         u16 seid,
5284                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5285                         struct i40e_asq_cmd_details *cmd_details)
5286 {
5287         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5288                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5289                                     cmd_details);
5290 }
5291
5292 /**
5293  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5294  * @hw: pointer to the hw struct
5295  * @seid: seid of the switching component
5296  * @bw_data: Buffer to hold switching component's per TC BW config
5297  * @cmd_details: pointer to command details structure or NULL
5298  **/
5299 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5300                 u16 seid,
5301                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5302                 struct i40e_asq_cmd_details *cmd_details)
5303 {
5304         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5305                                    i40e_aqc_opc_query_switching_comp_ets_config,
5306                                    cmd_details);
5307 }
5308
5309 /**
5310  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5311  * @hw: pointer to the hw struct
5312  * @seid: seid of the VSI or switching component connected to Physical Port
5313  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5314  * @cmd_details: pointer to command details structure or NULL
5315  **/
5316 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5317                         u16 seid,
5318                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5319                         struct i40e_asq_cmd_details *cmd_details)
5320 {
5321         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5322                                     i40e_aqc_opc_query_port_ets_config,
5323                                     cmd_details);
5324 }
5325
5326 /**
5327  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5328  * @hw: pointer to the hw struct
5329  * @seid: seid of the switching component
5330  * @bw_data: Buffer to hold switching component's BW configuration
5331  * @cmd_details: pointer to command details structure or NULL
5332  **/
5333 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5334                 u16 seid,
5335                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5336                 struct i40e_asq_cmd_details *cmd_details)
5337 {
5338         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5339                                     i40e_aqc_opc_query_switching_comp_bw_config,
5340                                     cmd_details);
5341 }
5342
5343 /**
5344  * i40e_validate_filter_settings
5345  * @hw: pointer to the hardware structure
5346  * @settings: Filter control settings
5347  *
5348  * Check and validate the filter control settings passed.
5349  * The function checks for the valid filter/context sizes being
5350  * passed for FCoE and PE.
5351  *
5352  * Returns I40E_SUCCESS if the values passed are valid and within
5353  * range else returns an error.
5354  **/
5355 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5356                                 struct i40e_filter_control_settings *settings)
5357 {
5358         u32 fcoe_cntx_size, fcoe_filt_size;
5359         u32 pe_cntx_size, pe_filt_size;
5360         u32 fcoe_fmax;
5361
5362         u32 val;
5363
5364         /* Validate FCoE settings passed */
5365         switch (settings->fcoe_filt_num) {
5366         case I40E_HASH_FILTER_SIZE_1K:
5367         case I40E_HASH_FILTER_SIZE_2K:
5368         case I40E_HASH_FILTER_SIZE_4K:
5369         case I40E_HASH_FILTER_SIZE_8K:
5370         case I40E_HASH_FILTER_SIZE_16K:
5371         case I40E_HASH_FILTER_SIZE_32K:
5372                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5373                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5374                 break;
5375         default:
5376                 return I40E_ERR_PARAM;
5377         }
5378
5379         switch (settings->fcoe_cntx_num) {
5380         case I40E_DMA_CNTX_SIZE_512:
5381         case I40E_DMA_CNTX_SIZE_1K:
5382         case I40E_DMA_CNTX_SIZE_2K:
5383         case I40E_DMA_CNTX_SIZE_4K:
5384                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5385                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5386                 break;
5387         default:
5388                 return I40E_ERR_PARAM;
5389         }
5390
5391         /* Validate PE settings passed */
5392         switch (settings->pe_filt_num) {
5393         case I40E_HASH_FILTER_SIZE_1K:
5394         case I40E_HASH_FILTER_SIZE_2K:
5395         case I40E_HASH_FILTER_SIZE_4K:
5396         case I40E_HASH_FILTER_SIZE_8K:
5397         case I40E_HASH_FILTER_SIZE_16K:
5398         case I40E_HASH_FILTER_SIZE_32K:
5399         case I40E_HASH_FILTER_SIZE_64K:
5400         case I40E_HASH_FILTER_SIZE_128K:
5401         case I40E_HASH_FILTER_SIZE_256K:
5402         case I40E_HASH_FILTER_SIZE_512K:
5403         case I40E_HASH_FILTER_SIZE_1M:
5404                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5405                 pe_filt_size <<= (u32)settings->pe_filt_num;
5406                 break;
5407         default:
5408                 return I40E_ERR_PARAM;
5409         }
5410
5411         switch (settings->pe_cntx_num) {
5412         case I40E_DMA_CNTX_SIZE_512:
5413         case I40E_DMA_CNTX_SIZE_1K:
5414         case I40E_DMA_CNTX_SIZE_2K:
5415         case I40E_DMA_CNTX_SIZE_4K:
5416         case I40E_DMA_CNTX_SIZE_8K:
5417         case I40E_DMA_CNTX_SIZE_16K:
5418         case I40E_DMA_CNTX_SIZE_32K:
5419         case I40E_DMA_CNTX_SIZE_64K:
5420         case I40E_DMA_CNTX_SIZE_128K:
5421         case I40E_DMA_CNTX_SIZE_256K:
5422                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5423                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5424                 break;
5425         default:
5426                 return I40E_ERR_PARAM;
5427         }
5428
5429         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5430         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5431         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5432                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5433         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5434                 return I40E_ERR_INVALID_SIZE;
5435
5436         return I40E_SUCCESS;
5437 }
5438
5439 /**
5440  * i40e_set_filter_control
5441  * @hw: pointer to the hardware structure
5442  * @settings: Filter control settings
5443  *
5444  * Set the Queue Filters for PE/FCoE and enable filters required
5445  * for a single PF. It is expected that these settings are programmed
5446  * at the driver initialization time.
5447  **/
5448 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5449                                 struct i40e_filter_control_settings *settings)
5450 {
5451         enum i40e_status_code ret = I40E_SUCCESS;
5452         u32 hash_lut_size = 0;
5453         u32 val;
5454
5455         if (!settings)
5456                 return I40E_ERR_PARAM;
5457
5458         /* Validate the input settings */
5459         ret = i40e_validate_filter_settings(hw, settings);
5460         if (ret)
5461                 return ret;
5462
5463         /* Read the PF Queue Filter control register */
5464         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5465
5466         /* Program required PE hash buckets for the PF */
5467         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5468         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5469                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5470         /* Program required PE contexts for the PF */
5471         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5472         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5473                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5474
5475         /* Program required FCoE hash buckets for the PF */
5476         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5477         val |= ((u32)settings->fcoe_filt_num <<
5478                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5479                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5480         /* Program required FCoE DDP contexts for the PF */
5481         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5482         val |= ((u32)settings->fcoe_cntx_num <<
5483                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5484                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5485
5486         /* Program Hash LUT size for the PF */
5487         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5488         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5489                 hash_lut_size = 1;
5490         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5491                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5492
5493         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5494         if (settings->enable_fdir)
5495                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5496         if (settings->enable_ethtype)
5497                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5498         if (settings->enable_macvlan)
5499                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5500
5501         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5502
5503         return I40E_SUCCESS;
5504 }
5505
5506 /**
5507  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5508  * @hw: pointer to the hw struct
5509  * @mac_addr: MAC address to use in the filter
5510  * @ethtype: Ethertype to use in the filter
5511  * @flags: Flags that needs to be applied to the filter
5512  * @vsi_seid: seid of the control VSI
5513  * @queue: VSI queue number to send the packet to
5514  * @is_add: Add control packet filter if True else remove
5515  * @stats: Structure to hold information on control filter counts
5516  * @cmd_details: pointer to command details structure or NULL
5517  *
5518  * This command will Add or Remove control packet filter for a control VSI.
5519  * In return it will update the total number of perfect filter count in
5520  * the stats member.
5521  **/
5522 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5523                                 u8 *mac_addr, u16 ethtype, u16 flags,
5524                                 u16 vsi_seid, u16 queue, bool is_add,
5525                                 struct i40e_control_filter_stats *stats,
5526                                 struct i40e_asq_cmd_details *cmd_details)
5527 {
5528         struct i40e_aq_desc desc;
5529         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5530                 (struct i40e_aqc_add_remove_control_packet_filter *)
5531                 &desc.params.raw;
5532         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5533                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5534                 &desc.params.raw;
5535         enum i40e_status_code status;
5536
5537         if (vsi_seid == 0)
5538                 return I40E_ERR_PARAM;
5539
5540         if (is_add) {
5541                 i40e_fill_default_direct_cmd_desc(&desc,
5542                                 i40e_aqc_opc_add_control_packet_filter);
5543                 cmd->queue = CPU_TO_LE16(queue);
5544         } else {
5545                 i40e_fill_default_direct_cmd_desc(&desc,
5546                                 i40e_aqc_opc_remove_control_packet_filter);
5547         }
5548
5549         if (mac_addr)
5550                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5551                             I40E_NONDMA_TO_NONDMA);
5552
5553         cmd->etype = CPU_TO_LE16(ethtype);
5554         cmd->flags = CPU_TO_LE16(flags);
5555         cmd->seid = CPU_TO_LE16(vsi_seid);
5556
5557         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5558
5559         if (!status && stats) {
5560                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5561                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5562                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5563                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5564         }
5565
5566         return status;
5567 }
5568
5569 /**
5570  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5571  * @hw: pointer to the hw struct
5572  * @seid: VSI seid to add ethertype filter from
5573  **/
5574 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5575 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5576                                                     u16 seid)
5577 {
5578         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5579                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5580                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5581         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5582         enum i40e_status_code status;
5583
5584         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5585                                                        seid, 0, true, NULL,
5586                                                        NULL);
5587         if (status)
5588                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5589 }
5590
5591 /**
5592  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5593  * @filters: list of cloud filters
5594  * @filter_count: length of list
5595  *
5596  * There's an issue in the device where the Geneve VNI layout needs
5597  * to be shifted 1 byte over from the VxLAN VNI
5598  **/
5599 STATIC void i40e_fix_up_geneve_vni(
5600         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5601         u8 filter_count)
5602 {
5603         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5604         int i;
5605
5606         for (i = 0; i < filter_count; i++) {
5607                 u16 tnl_type;
5608                 u32 ti;
5609
5610                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5611                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5612                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5613                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5614                         ti = LE32_TO_CPU(f[i].tenant_id);
5615                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5616                 }
5617         }
5618 }
5619
5620 /**
5621  * i40e_aq_add_cloud_filters
5622  * @hw: pointer to the hardware structure
5623  * @seid: VSI seid to add cloud filters from
5624  * @filters: Buffer which contains the filters to be added
5625  * @filter_count: number of filters contained in the buffer
5626  *
5627  * Set the cloud filters for a given VSI.  The contents of the
5628  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5629  * in by the caller of the function.
5630  *
5631  **/
5632 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5633         u16 seid,
5634         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5635         u8 filter_count)
5636 {
5637         struct i40e_aq_desc desc;
5638         struct i40e_aqc_add_remove_cloud_filters *cmd =
5639         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5640         enum i40e_status_code status;
5641         u16 buff_len;
5642
5643         i40e_fill_default_direct_cmd_desc(&desc,
5644                                           i40e_aqc_opc_add_cloud_filters);
5645
5646         buff_len = filter_count * sizeof(*filters);
5647         desc.datalen = CPU_TO_LE16(buff_len);
5648         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5649         cmd->num_filters = filter_count;
5650         cmd->seid = CPU_TO_LE16(seid);
5651
5652         i40e_fix_up_geneve_vni(filters, filter_count);
5653
5654         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5655
5656         return status;
5657 }
5658
5659 /**
5660  * i40e_aq_add_cloud_filters_big_buffer
5661  * @hw: pointer to the hardware structure
5662  * @seid: VSI seid to add cloud filters from
5663  * @filters: Buffer which contains the filters in big buffer to be added
5664  * @filter_count: number of filters contained in the buffer
5665  *
5666  * Set the cloud filters for a given VSI.  The contents of the
5667  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5668  * the function.
5669  *
5670  **/
5671 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5672         u16 seid,
5673         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5674         u8 filter_count)
5675 {
5676         struct i40e_aq_desc desc;
5677         struct i40e_aqc_add_remove_cloud_filters *cmd =
5678         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5679         enum i40e_status_code status;
5680         u16 buff_len;
5681         int i;
5682
5683         i40e_fill_default_direct_cmd_desc(&desc,
5684                                           i40e_aqc_opc_add_cloud_filters);
5685
5686         buff_len = filter_count * sizeof(*filters);
5687         desc.datalen = CPU_TO_LE16(buff_len);
5688         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5689         cmd->num_filters = filter_count;
5690         cmd->seid = CPU_TO_LE16(seid);
5691         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5692
5693         /* adjust Geneve VNI for HW issue */
5694         for (i = 0; i < filter_count; i++) {
5695                 u16 tnl_type;
5696                 u32 ti;
5697
5698                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5699                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5700                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5701                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5702                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5703                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5704                 }
5705         }
5706
5707         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5708
5709         return status;
5710 }
5711
5712 /**
5713  * i40e_aq_remove_cloud_filters
5714  * @hw: pointer to the hardware structure
5715  * @seid: VSI seid to remove cloud filters from
5716  * @filters: Buffer which contains the filters to be removed
5717  * @filter_count: number of filters contained in the buffer
5718  *
5719  * Remove the cloud filters for a given VSI.  The contents of the
5720  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5721  * in by the caller of the function.
5722  *
5723  **/
5724 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5725         u16 seid,
5726         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5727         u8 filter_count)
5728 {
5729         struct i40e_aq_desc desc;
5730         struct i40e_aqc_add_remove_cloud_filters *cmd =
5731         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5732         enum i40e_status_code status;
5733         u16 buff_len;
5734
5735         i40e_fill_default_direct_cmd_desc(&desc,
5736                                           i40e_aqc_opc_remove_cloud_filters);
5737
5738         buff_len = filter_count * sizeof(*filters);
5739         desc.datalen = CPU_TO_LE16(buff_len);
5740         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5741         cmd->num_filters = filter_count;
5742         cmd->seid = CPU_TO_LE16(seid);
5743
5744         i40e_fix_up_geneve_vni(filters, filter_count);
5745
5746         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5747
5748         return status;
5749 }
5750
5751 /**
5752  * i40e_aq_remove_cloud_filters_big_buffer
5753  * @hw: pointer to the hardware structure
5754  * @seid: VSI seid to remove cloud filters from
5755  * @filters: Buffer which contains the filters in big buffer to be removed
5756  * @filter_count: number of filters contained in the buffer
5757  *
5758  * Remove the cloud filters for a given VSI.  The contents of the
5759  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5760  * the function.
5761  *
5762  **/
5763 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5764         struct i40e_hw *hw,
5765         u16 seid,
5766         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5767         u8 filter_count)
5768 {
5769         struct i40e_aq_desc desc;
5770         struct i40e_aqc_add_remove_cloud_filters *cmd =
5771         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5772         enum i40e_status_code status;
5773         u16 buff_len;
5774         int i;
5775
5776         i40e_fill_default_direct_cmd_desc(&desc,
5777                                           i40e_aqc_opc_remove_cloud_filters);
5778
5779         buff_len = filter_count * sizeof(*filters);
5780         desc.datalen = CPU_TO_LE16(buff_len);
5781         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5782         cmd->num_filters = filter_count;
5783         cmd->seid = CPU_TO_LE16(seid);
5784         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5785
5786         /* adjust Geneve VNI for HW issue */
5787         for (i = 0; i < filter_count; i++) {
5788                 u16 tnl_type;
5789                 u32 ti;
5790
5791                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5792                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5793                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5794                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5795                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5796                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5797                 }
5798         }
5799
5800         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5801
5802         return status;
5803 }
5804
5805 /**
5806  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5807  * @hw: pointer to the hw struct
5808  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5809  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5810  *
5811  **/
5812 enum
5813 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5814         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5815         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5816 {
5817         struct i40e_aq_desc desc;
5818         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5819                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5820         enum i40e_status_code status = I40E_SUCCESS;
5821         int i = 0;
5822
5823         i40e_fill_default_direct_cmd_desc(&desc,
5824                                           i40e_aqc_opc_replace_cloud_filters);
5825
5826         desc.datalen = CPU_TO_LE16(32);
5827         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5828         cmd->old_filter_type = filters->old_filter_type;
5829         cmd->new_filter_type = filters->new_filter_type;
5830         cmd->valid_flags = filters->valid_flags;
5831         cmd->tr_bit = filters->tr_bit;
5832
5833         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5834                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5835
5836         /* for get cloud filters command */
5837         for (i = 0; i < 32; i += 4) {
5838                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5839                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5840                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5841                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5842         }
5843
5844         return status;
5845 }
5846
5847
5848 /**
5849  * i40e_aq_alternate_write
5850  * @hw: pointer to the hardware structure
5851  * @reg_addr0: address of first dword to be read
5852  * @reg_val0: value to be written under 'reg_addr0'
5853  * @reg_addr1: address of second dword to be read
5854  * @reg_val1: value to be written under 'reg_addr1'
5855  *
5856  * Write one or two dwords to alternate structure. Fields are indicated
5857  * by 'reg_addr0' and 'reg_addr1' register numbers.
5858  *
5859  **/
5860 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5861                                 u32 reg_addr0, u32 reg_val0,
5862                                 u32 reg_addr1, u32 reg_val1)
5863 {
5864         struct i40e_aq_desc desc;
5865         struct i40e_aqc_alternate_write *cmd_resp =
5866                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5867         enum i40e_status_code status;
5868
5869         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5870         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5871         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5872         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5873         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5874
5875         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5876
5877         return status;
5878 }
5879
5880 /**
5881  * i40e_aq_alternate_write_indirect
5882  * @hw: pointer to the hardware structure
5883  * @addr: address of a first register to be modified
5884  * @dw_count: number of alternate structure fields to write
5885  * @buffer: pointer to the command buffer
5886  *
5887  * Write 'dw_count' dwords from 'buffer' to alternate structure
5888  * starting at 'addr'.
5889  *
5890  **/
5891 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5892                                 u32 addr, u32 dw_count, void *buffer)
5893 {
5894         struct i40e_aq_desc desc;
5895         struct i40e_aqc_alternate_ind_write *cmd_resp =
5896                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5897         enum i40e_status_code status;
5898
5899         if (buffer == NULL)
5900                 return I40E_ERR_PARAM;
5901
5902         /* Indirect command */
5903         i40e_fill_default_direct_cmd_desc(&desc,
5904                                          i40e_aqc_opc_alternate_write_indirect);
5905
5906         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5907         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5908         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5909                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5910
5911         cmd_resp->address = CPU_TO_LE32(addr);
5912         cmd_resp->length = CPU_TO_LE32(dw_count);
5913
5914         status = i40e_asq_send_command(hw, &desc, buffer,
5915                                        I40E_LO_DWORD(4*dw_count), NULL);
5916
5917         return status;
5918 }
5919
5920 /**
5921  * i40e_aq_alternate_read
5922  * @hw: pointer to the hardware structure
5923  * @reg_addr0: address of first dword to be read
5924  * @reg_val0: pointer for data read from 'reg_addr0'
5925  * @reg_addr1: address of second dword to be read
5926  * @reg_val1: pointer for data read from 'reg_addr1'
5927  *
5928  * Read one or two dwords from alternate structure. Fields are indicated
5929  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5930  * is not passed then only register at 'reg_addr0' is read.
5931  *
5932  **/
5933 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5934                                 u32 reg_addr0, u32 *reg_val0,
5935                                 u32 reg_addr1, u32 *reg_val1)
5936 {
5937         struct i40e_aq_desc desc;
5938         struct i40e_aqc_alternate_write *cmd_resp =
5939                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5940         enum i40e_status_code status;
5941
5942         if (reg_val0 == NULL)
5943                 return I40E_ERR_PARAM;
5944
5945         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5946         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5947         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5948
5949         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5950
5951         if (status == I40E_SUCCESS) {
5952                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5953
5954                 if (reg_val1 != NULL)
5955                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5956         }
5957
5958         return status;
5959 }
5960
5961 /**
5962  * i40e_aq_alternate_read_indirect
5963  * @hw: pointer to the hardware structure
5964  * @addr: address of the alternate structure field
5965  * @dw_count: number of alternate structure fields to read
5966  * @buffer: pointer to the command buffer
5967  *
5968  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5969  * place them in 'buffer'. The buffer should be allocated by caller.
5970  *
5971  **/
5972 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5973                                 u32 addr, u32 dw_count, void *buffer)
5974 {
5975         struct i40e_aq_desc desc;
5976         struct i40e_aqc_alternate_ind_write *cmd_resp =
5977                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5978         enum i40e_status_code status;
5979
5980         if (buffer == NULL)
5981                 return I40E_ERR_PARAM;
5982
5983         /* Indirect command */
5984         i40e_fill_default_direct_cmd_desc(&desc,
5985                 i40e_aqc_opc_alternate_read_indirect);
5986
5987         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5988         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5989         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5990                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5991
5992         cmd_resp->address = CPU_TO_LE32(addr);
5993         cmd_resp->length = CPU_TO_LE32(dw_count);
5994
5995         status = i40e_asq_send_command(hw, &desc, buffer,
5996                                        I40E_LO_DWORD(4*dw_count), NULL);
5997
5998         return status;
5999 }
6000
6001 /**
6002  *  i40e_aq_alternate_clear
6003  *  @hw: pointer to the HW structure.
6004  *
6005  *  Clear the alternate structures of the port from which the function
6006  *  is called.
6007  *
6008  **/
6009 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6010 {
6011         struct i40e_aq_desc desc;
6012         enum i40e_status_code status;
6013
6014         i40e_fill_default_direct_cmd_desc(&desc,
6015                                           i40e_aqc_opc_alternate_clear_port);
6016
6017         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6018
6019         return status;
6020 }
6021
6022 /**
6023  *  i40e_aq_alternate_write_done
6024  *  @hw: pointer to the HW structure.
6025  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6026  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6027  *
6028  *  Indicates to the FW that alternate structures have been changed.
6029  *
6030  **/
6031 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6032                 u8 bios_mode, bool *reset_needed)
6033 {
6034         struct i40e_aq_desc desc;
6035         struct i40e_aqc_alternate_write_done *cmd =
6036                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6037         enum i40e_status_code status;
6038
6039         if (reset_needed == NULL)
6040                 return I40E_ERR_PARAM;
6041
6042         i40e_fill_default_direct_cmd_desc(&desc,
6043                                           i40e_aqc_opc_alternate_write_done);
6044
6045         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6046
6047         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6048         if (!status && reset_needed)
6049                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6050                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6051
6052         return status;
6053 }
6054
6055 /**
6056  *  i40e_aq_set_oem_mode
6057  *  @hw: pointer to the HW structure.
6058  *  @oem_mode: the OEM mode to be used
6059  *
6060  *  Sets the device to a specific operating mode. Currently the only supported
6061  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6062  *
6063  **/
6064 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6065                 u8 oem_mode)
6066 {
6067         struct i40e_aq_desc desc;
6068         struct i40e_aqc_alternate_write_done *cmd =
6069                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6070         enum i40e_status_code status;
6071
6072         i40e_fill_default_direct_cmd_desc(&desc,
6073                                           i40e_aqc_opc_alternate_set_mode);
6074
6075         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6076
6077         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6078
6079         return status;
6080 }
6081
6082 /**
6083  * i40e_aq_resume_port_tx
6084  * @hw: pointer to the hardware structure
6085  * @cmd_details: pointer to command details structure or NULL
6086  *
6087  * Resume port's Tx traffic
6088  **/
6089 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6090                                 struct i40e_asq_cmd_details *cmd_details)
6091 {
6092         struct i40e_aq_desc desc;
6093         enum i40e_status_code status;
6094
6095         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6096
6097         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6098
6099         return status;
6100 }
6101
6102 /**
6103  * i40e_set_pci_config_data - store PCI bus info
6104  * @hw: pointer to hardware structure
6105  * @link_status: the link status word from PCI config space
6106  *
6107  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6108  **/
6109 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6110 {
6111         hw->bus.type = i40e_bus_type_pci_express;
6112
6113         switch (link_status & I40E_PCI_LINK_WIDTH) {
6114         case I40E_PCI_LINK_WIDTH_1:
6115                 hw->bus.width = i40e_bus_width_pcie_x1;
6116                 break;
6117         case I40E_PCI_LINK_WIDTH_2:
6118                 hw->bus.width = i40e_bus_width_pcie_x2;
6119                 break;
6120         case I40E_PCI_LINK_WIDTH_4:
6121                 hw->bus.width = i40e_bus_width_pcie_x4;
6122                 break;
6123         case I40E_PCI_LINK_WIDTH_8:
6124                 hw->bus.width = i40e_bus_width_pcie_x8;
6125                 break;
6126         default:
6127                 hw->bus.width = i40e_bus_width_unknown;
6128                 break;
6129         }
6130
6131         switch (link_status & I40E_PCI_LINK_SPEED) {
6132         case I40E_PCI_LINK_SPEED_2500:
6133                 hw->bus.speed = i40e_bus_speed_2500;
6134                 break;
6135         case I40E_PCI_LINK_SPEED_5000:
6136                 hw->bus.speed = i40e_bus_speed_5000;
6137                 break;
6138         case I40E_PCI_LINK_SPEED_8000:
6139                 hw->bus.speed = i40e_bus_speed_8000;
6140                 break;
6141         default:
6142                 hw->bus.speed = i40e_bus_speed_unknown;
6143                 break;
6144         }
6145 }
6146
6147 /**
6148  * i40e_aq_debug_dump
6149  * @hw: pointer to the hardware structure
6150  * @cluster_id: specific cluster to dump
6151  * @table_id: table id within cluster
6152  * @start_index: index of line in the block to read
6153  * @buff_size: dump buffer size
6154  * @buff: dump buffer
6155  * @ret_buff_size: actual buffer size returned
6156  * @ret_next_table: next block to read
6157  * @ret_next_index: next index to read
6158  *
6159  * Dump internal FW/HW data for debug purposes.
6160  *
6161  **/
6162 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6163                                 u8 table_id, u32 start_index, u16 buff_size,
6164                                 void *buff, u16 *ret_buff_size,
6165                                 u8 *ret_next_table, u32 *ret_next_index,
6166                                 struct i40e_asq_cmd_details *cmd_details)
6167 {
6168         struct i40e_aq_desc desc;
6169         struct i40e_aqc_debug_dump_internals *cmd =
6170                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6171         struct i40e_aqc_debug_dump_internals *resp =
6172                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6173         enum i40e_status_code status;
6174
6175         if (buff_size == 0 || !buff)
6176                 return I40E_ERR_PARAM;
6177
6178         i40e_fill_default_direct_cmd_desc(&desc,
6179                                           i40e_aqc_opc_debug_dump_internals);
6180         /* Indirect Command */
6181         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6182         if (buff_size > I40E_AQ_LARGE_BUF)
6183                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6184
6185         cmd->cluster_id = cluster_id;
6186         cmd->table_id = table_id;
6187         cmd->idx = CPU_TO_LE32(start_index);
6188
6189         desc.datalen = CPU_TO_LE16(buff_size);
6190
6191         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6192         if (!status) {
6193                 if (ret_buff_size != NULL)
6194                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6195                 if (ret_next_table != NULL)
6196                         *ret_next_table = resp->table_id;
6197                 if (ret_next_index != NULL)
6198                         *ret_next_index = LE32_TO_CPU(resp->idx);
6199         }
6200
6201         return status;
6202 }
6203
6204 /**
6205  * i40e_read_bw_from_alt_ram
6206  * @hw: pointer to the hardware structure
6207  * @max_bw: pointer for max_bw read
6208  * @min_bw: pointer for min_bw read
6209  * @min_valid: pointer for bool that is true if min_bw is a valid value
6210  * @max_valid: pointer for bool that is true if max_bw is a valid value
6211  *
6212  * Read bw from the alternate ram for the given pf
6213  **/
6214 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6215                                         u32 *max_bw, u32 *min_bw,
6216                                         bool *min_valid, bool *max_valid)
6217 {
6218         enum i40e_status_code status;
6219         u32 max_bw_addr, min_bw_addr;
6220
6221         /* Calculate the address of the min/max bw registers */
6222         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6223                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6224                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6225         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6226                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6227                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6228
6229         /* Read the bandwidths from alt ram */
6230         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6231                                         min_bw_addr, min_bw);
6232
6233         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6234                 *min_valid = true;
6235         else
6236                 *min_valid = false;
6237
6238         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6239                 *max_valid = true;
6240         else
6241                 *max_valid = false;
6242
6243         return status;
6244 }
6245
6246 /**
6247  * i40e_aq_configure_partition_bw
6248  * @hw: pointer to the hardware structure
6249  * @bw_data: Buffer holding valid pfs and bw limits
6250  * @cmd_details: pointer to command details
6251  *
6252  * Configure partitions guaranteed/max bw
6253  **/
6254 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6255                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6256                         struct i40e_asq_cmd_details *cmd_details)
6257 {
6258         enum i40e_status_code status;
6259         struct i40e_aq_desc desc;
6260         u16 bwd_size = sizeof(*bw_data);
6261
6262         i40e_fill_default_direct_cmd_desc(&desc,
6263                                 i40e_aqc_opc_configure_partition_bw);
6264
6265         /* Indirect command */
6266         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6267         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6268
6269         desc.datalen = CPU_TO_LE16(bwd_size);
6270
6271         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6272
6273         return status;
6274 }
6275
6276 /**
6277  * i40e_read_phy_register_clause22
6278  * @hw: pointer to the HW structure
6279  * @reg: register address in the page
6280  * @phy_adr: PHY address on MDIO interface
6281  * @value: PHY register value
6282  *
6283  * Reads specified PHY register value
6284  **/
6285 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6286                                         u16 reg, u8 phy_addr, u16 *value)
6287 {
6288         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6289         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6290         u32 command = 0;
6291         u16 retry = 1000;
6292
6293         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6294                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6295                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6296                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6297                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6298         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6299         do {
6300                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6301                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6302                         status = I40E_SUCCESS;
6303                         break;
6304                 }
6305                 i40e_usec_delay(10);
6306                 retry--;
6307         } while (retry);
6308
6309         if (status) {
6310                 i40e_debug(hw, I40E_DEBUG_PHY,
6311                            "PHY: Can't write command to external PHY.\n");
6312         } else {
6313                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6314                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6315                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6316         }
6317
6318         return status;
6319 }
6320
6321 /**
6322  * i40e_write_phy_register_clause22
6323  * @hw: pointer to the HW structure
6324  * @reg: register address in the page
6325  * @phy_adr: PHY address on MDIO interface
6326  * @value: PHY register value
6327  *
6328  * Writes specified PHY register value
6329  **/
6330 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6331                                         u16 reg, u8 phy_addr, u16 value)
6332 {
6333         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6334         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6335         u32 command  = 0;
6336         u16 retry = 1000;
6337
6338         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6339         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6340
6341         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6342                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6343                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6344                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6345                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6346
6347         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6348         do {
6349                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6350                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6351                         status = I40E_SUCCESS;
6352                         break;
6353                 }
6354                 i40e_usec_delay(10);
6355                 retry--;
6356         } while (retry);
6357
6358         return status;
6359 }
6360
6361 /**
6362  * i40e_read_phy_register_clause45
6363  * @hw: pointer to the HW structure
6364  * @page: registers page number
6365  * @reg: register address in the page
6366  * @phy_adr: PHY address on MDIO interface
6367  * @value: PHY register value
6368  *
6369  * Reads specified PHY register value
6370  **/
6371 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6372                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6373 {
6374         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6375         u32 command  = 0;
6376         u16 retry = 1000;
6377         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6378
6379         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6380                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6381                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6382                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6383                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6384                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6385                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6386         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6387         do {
6388                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6389                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6390                         status = I40E_SUCCESS;
6391                         break;
6392                 }
6393                 i40e_usec_delay(10);
6394                 retry--;
6395         } while (retry);
6396
6397         if (status) {
6398                 i40e_debug(hw, I40E_DEBUG_PHY,
6399                            "PHY: Can't write command to external PHY.\n");
6400                 goto phy_read_end;
6401         }
6402
6403         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6404                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6405                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6406                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6407                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6408                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6409         status = I40E_ERR_TIMEOUT;
6410         retry = 1000;
6411         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6412         do {
6413                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6414                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6415                         status = I40E_SUCCESS;
6416                         break;
6417                 }
6418                 i40e_usec_delay(10);
6419                 retry--;
6420         } while (retry);
6421
6422         if (!status) {
6423                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6424                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6425                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6426         } else {
6427                 i40e_debug(hw, I40E_DEBUG_PHY,
6428                            "PHY: Can't read register value from external PHY.\n");
6429         }
6430
6431 phy_read_end:
6432         return status;
6433 }
6434
6435 /**
6436  * i40e_write_phy_register_clause45
6437  * @hw: pointer to the HW structure
6438  * @page: registers page number
6439  * @reg: register address in the page
6440  * @phy_adr: PHY address on MDIO interface
6441  * @value: PHY register value
6442  *
6443  * Writes value to specified PHY register
6444  **/
6445 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6446                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6447 {
6448         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6449         u32 command  = 0;
6450         u16 retry = 1000;
6451         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6452
6453         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6454                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6455                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6456                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6457                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6458                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6459                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6460         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6461         do {
6462                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6463                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6464                         status = I40E_SUCCESS;
6465                         break;
6466                 }
6467                 i40e_usec_delay(10);
6468                 retry--;
6469         } while (retry);
6470         if (status) {
6471                 i40e_debug(hw, I40E_DEBUG_PHY,
6472                            "PHY: Can't write command to external PHY.\n");
6473                 goto phy_write_end;
6474         }
6475
6476         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6477         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6478
6479         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6480                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6481                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6482                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6483                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6484                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6485         status = I40E_ERR_TIMEOUT;
6486         retry = 1000;
6487         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6488         do {
6489                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6490                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6491                         status = I40E_SUCCESS;
6492                         break;
6493                 }
6494                 i40e_usec_delay(10);
6495                 retry--;
6496         } while (retry);
6497
6498 phy_write_end:
6499         return status;
6500 }
6501
6502 /**
6503  * i40e_write_phy_register
6504  * @hw: pointer to the HW structure
6505  * @page: registers page number
6506  * @reg: register address in the page
6507  * @phy_adr: PHY address on MDIO interface
6508  * @value: PHY register value
6509  *
6510  * Writes value to specified PHY register
6511  **/
6512 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6513                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6514 {
6515         enum i40e_status_code status;
6516
6517         switch (hw->device_id) {
6518         case I40E_DEV_ID_1G_BASE_T_X722:
6519                 status = i40e_write_phy_register_clause22(hw,
6520                         reg, phy_addr, value);
6521                 break;
6522         case I40E_DEV_ID_10G_BASE_T:
6523         case I40E_DEV_ID_10G_BASE_T4:
6524         case I40E_DEV_ID_10G_BASE_T_X722:
6525         case I40E_DEV_ID_25G_B:
6526         case I40E_DEV_ID_25G_SFP28:
6527                 status = i40e_write_phy_register_clause45(hw,
6528                         page, reg, phy_addr, value);
6529                 break;
6530         default:
6531                 status = I40E_ERR_UNKNOWN_PHY;
6532                 break;
6533         }
6534
6535         return status;
6536 }
6537
6538 /**
6539  * i40e_read_phy_register
6540  * @hw: pointer to the HW structure
6541  * @page: registers page number
6542  * @reg: register address in the page
6543  * @phy_adr: PHY address on MDIO interface
6544  * @value: PHY register value
6545  *
6546  * Reads specified PHY register value
6547  **/
6548 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6549                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6550 {
6551         enum i40e_status_code status;
6552
6553         switch (hw->device_id) {
6554         case I40E_DEV_ID_1G_BASE_T_X722:
6555                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6556                                                          value);
6557                 break;
6558         case I40E_DEV_ID_10G_BASE_T:
6559         case I40E_DEV_ID_10G_BASE_T4:
6560         case I40E_DEV_ID_10G_BASE_T_X722:
6561         case I40E_DEV_ID_25G_B:
6562         case I40E_DEV_ID_25G_SFP28:
6563                 status = i40e_read_phy_register_clause45(hw, page, reg,
6564                                                          phy_addr, value);
6565                 break;
6566         default:
6567                 status = I40E_ERR_UNKNOWN_PHY;
6568                 break;
6569         }
6570
6571         return status;
6572 }
6573
6574 /**
6575  * i40e_get_phy_address
6576  * @hw: pointer to the HW structure
6577  * @dev_num: PHY port num that address we want
6578  * @phy_addr: Returned PHY address
6579  *
6580  * Gets PHY address for current port
6581  **/
6582 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6583 {
6584         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6585         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6586
6587         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6588 }
6589
6590 /**
6591  * i40e_blink_phy_led
6592  * @hw: pointer to the HW structure
6593  * @time: time how long led will blinks in secs
6594  * @interval: gap between LED on and off in msecs
6595  *
6596  * Blinks PHY link LED
6597  **/
6598 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6599                                               u32 time, u32 interval)
6600 {
6601         enum i40e_status_code status = I40E_SUCCESS;
6602         u32 i;
6603         u16 led_ctl = 0;
6604         u16 gpio_led_port;
6605         u16 led_reg;
6606         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6607         u8 phy_addr = 0;
6608         u8 port_num;
6609
6610         i = rd32(hw, I40E_PFGEN_PORTNUM);
6611         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6612         phy_addr = i40e_get_phy_address(hw, port_num);
6613
6614         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6615              led_addr++) {
6616                 status = i40e_read_phy_register_clause45(hw,
6617                                                          I40E_PHY_COM_REG_PAGE,
6618                                                          led_addr, phy_addr,
6619                                                          &led_reg);
6620                 if (status)
6621                         goto phy_blinking_end;
6622                 led_ctl = led_reg;
6623                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6624                         led_reg = 0;
6625                         status = i40e_write_phy_register_clause45(hw,
6626                                                          I40E_PHY_COM_REG_PAGE,
6627                                                          led_addr, phy_addr,
6628                                                          led_reg);
6629                         if (status)
6630                                 goto phy_blinking_end;
6631                         break;
6632                 }
6633         }
6634
6635         if (time > 0 && interval > 0) {
6636                 for (i = 0; i < time * 1000; i += interval) {
6637                         status = i40e_read_phy_register_clause45(hw,
6638                                                 I40E_PHY_COM_REG_PAGE,
6639                                                 led_addr, phy_addr, &led_reg);
6640                         if (status)
6641                                 goto restore_config;
6642                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6643                                 led_reg = 0;
6644                         else
6645                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6646                         status = i40e_write_phy_register_clause45(hw,
6647                                                 I40E_PHY_COM_REG_PAGE,
6648                                                 led_addr, phy_addr, led_reg);
6649                         if (status)
6650                                 goto restore_config;
6651                         i40e_msec_delay(interval);
6652                 }
6653         }
6654
6655 restore_config:
6656         status = i40e_write_phy_register_clause45(hw,
6657                                                   I40E_PHY_COM_REG_PAGE,
6658                                                   led_addr, phy_addr, led_ctl);
6659
6660 phy_blinking_end:
6661         return status;
6662 }
6663
6664 /**
6665  * i40e_led_get_phy - return current on/off mode
6666  * @hw: pointer to the hw struct
6667  * @led_addr: address of led register to use
6668  * @val: original value of register to use
6669  *
6670  **/
6671 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6672                                        u16 *val)
6673 {
6674         enum i40e_status_code status = I40E_SUCCESS;
6675         u16 gpio_led_port;
6676         u8 phy_addr = 0;
6677         u16 reg_val;
6678         u16 temp_addr;
6679         u8 port_num;
6680         u32 i;
6681
6682         temp_addr = I40E_PHY_LED_PROV_REG_1;
6683         i = rd32(hw, I40E_PFGEN_PORTNUM);
6684         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6685         phy_addr = i40e_get_phy_address(hw, port_num);
6686
6687         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6688              temp_addr++) {
6689                 status = i40e_read_phy_register_clause45(hw,
6690                                                          I40E_PHY_COM_REG_PAGE,
6691                                                          temp_addr, phy_addr,
6692                                                          &reg_val);
6693                 if (status)
6694                         return status;
6695                 *val = reg_val;
6696                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6697                         *led_addr = temp_addr;
6698                         break;
6699                 }
6700         }
6701         return status;
6702 }
6703
6704 /**
6705  * i40e_led_set_phy
6706  * @hw: pointer to the HW structure
6707  * @on: true or false
6708  * @mode: original val plus bit for set or ignore
6709  * Set led's on or off when controlled by the PHY
6710  *
6711  **/
6712 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6713                                        u16 led_addr, u32 mode)
6714 {
6715         enum i40e_status_code status = I40E_SUCCESS;
6716         u16 led_ctl = 0;
6717         u16 led_reg = 0;
6718         u8 phy_addr = 0;
6719         u8 port_num;
6720         u32 i;
6721
6722         i = rd32(hw, I40E_PFGEN_PORTNUM);
6723         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6724         phy_addr = i40e_get_phy_address(hw, port_num);
6725         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6726                                                  led_addr, phy_addr, &led_reg);
6727         if (status)
6728                 return status;
6729         led_ctl = led_reg;
6730         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6731                 led_reg = 0;
6732                 status = i40e_write_phy_register_clause45(hw,
6733                                                           I40E_PHY_COM_REG_PAGE,
6734                                                           led_addr, phy_addr,
6735                                                           led_reg);
6736                 if (status)
6737                         return status;
6738         }
6739         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6740                                                  led_addr, phy_addr, &led_reg);
6741         if (status)
6742                 goto restore_config;
6743         if (on)
6744                 led_reg = I40E_PHY_LED_MANUAL_ON;
6745         else
6746                 led_reg = 0;
6747         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6748                                                   led_addr, phy_addr, led_reg);
6749         if (status)
6750                 goto restore_config;
6751         if (mode & I40E_PHY_LED_MODE_ORIG) {
6752                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6753                 status = i40e_write_phy_register_clause45(hw,
6754                                                  I40E_PHY_COM_REG_PAGE,
6755                                                  led_addr, phy_addr, led_ctl);
6756         }
6757         return status;
6758 restore_config:
6759         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6760                                                   led_addr, phy_addr, led_ctl);
6761         return status;
6762 }
6763 #endif /* PF_DRIVER */
6764
6765 /**
6766  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6767  * @hw: pointer to the hw struct
6768  * @reg_addr: register address
6769  * @reg_val: ptr to register value
6770  * @cmd_details: pointer to command details structure or NULL
6771  *
6772  * Use the firmware to read the Rx control register,
6773  * especially useful if the Rx unit is under heavy pressure
6774  **/
6775 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6776                                 u32 reg_addr, u32 *reg_val,
6777                                 struct i40e_asq_cmd_details *cmd_details)
6778 {
6779         struct i40e_aq_desc desc;
6780         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6781                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6782         enum i40e_status_code status;
6783
6784         if (reg_val == NULL)
6785                 return I40E_ERR_PARAM;
6786
6787         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6788
6789         cmd_resp->address = CPU_TO_LE32(reg_addr);
6790
6791         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6792
6793         if (status == I40E_SUCCESS)
6794                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6795
6796         return status;
6797 }
6798
6799 /**
6800  * i40e_read_rx_ctl - read from an Rx control register
6801  * @hw: pointer to the hw struct
6802  * @reg_addr: register address
6803  **/
6804 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6805 {
6806         enum i40e_status_code status = I40E_SUCCESS;
6807         bool use_register;
6808         int retry = 5;
6809         u32 val = 0;
6810
6811         use_register = (((hw->aq.api_maj_ver == 1) &&
6812                         (hw->aq.api_min_ver < 5)) ||
6813                         (hw->mac.type == I40E_MAC_X722));
6814         if (!use_register) {
6815 do_retry:
6816                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6817                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6818                         i40e_msec_delay(1);
6819                         retry--;
6820                         goto do_retry;
6821                 }
6822         }
6823
6824         /* if the AQ access failed, try the old-fashioned way */
6825         if (status || use_register)
6826                 val = rd32(hw, reg_addr);
6827
6828         return val;
6829 }
6830
6831 /**
6832  * i40e_aq_rx_ctl_write_register
6833  * @hw: pointer to the hw struct
6834  * @reg_addr: register address
6835  * @reg_val: register value
6836  * @cmd_details: pointer to command details structure or NULL
6837  *
6838  * Use the firmware to write to an Rx control register,
6839  * especially useful if the Rx unit is under heavy pressure
6840  **/
6841 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6842                                 u32 reg_addr, u32 reg_val,
6843                                 struct i40e_asq_cmd_details *cmd_details)
6844 {
6845         struct i40e_aq_desc desc;
6846         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6847                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6848         enum i40e_status_code status;
6849
6850         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6851
6852         cmd->address = CPU_TO_LE32(reg_addr);
6853         cmd->value = CPU_TO_LE32(reg_val);
6854
6855         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6856
6857         return status;
6858 }
6859
6860 /**
6861  * i40e_write_rx_ctl - write to an Rx control register
6862  * @hw: pointer to the hw struct
6863  * @reg_addr: register address
6864  * @reg_val: register value
6865  **/
6866 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6867 {
6868         enum i40e_status_code status = I40E_SUCCESS;
6869         bool use_register;
6870         int retry = 5;
6871
6872         use_register = (((hw->aq.api_maj_ver == 1) &&
6873                         (hw->aq.api_min_ver < 5)) ||
6874                         (hw->mac.type == I40E_MAC_X722));
6875         if (!use_register) {
6876 do_retry:
6877                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6878                                                        reg_val, NULL);
6879                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6880                         i40e_msec_delay(1);
6881                         retry--;
6882                         goto do_retry;
6883                 }
6884         }
6885
6886         /* if the AQ access failed, try the old-fashioned way */
6887         if (status || use_register)
6888                 wr32(hw, reg_addr, reg_val);
6889 }
6890
6891 /**
6892  * i40e_aq_set_phy_register
6893  * @hw: pointer to the hw struct
6894  * @phy_select: select which phy should be accessed
6895  * @dev_addr: PHY device address
6896  * @reg_addr: PHY register address
6897  * @reg_val: new register value
6898  * @cmd_details: pointer to command details structure or NULL
6899  *
6900  * Write the external PHY register.
6901  **/
6902 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
6903                                 u8 phy_select, u8 dev_addr,
6904                                 u32 reg_addr, u32 reg_val,
6905                                 struct i40e_asq_cmd_details *cmd_details)
6906 {
6907         struct i40e_aq_desc desc;
6908         struct i40e_aqc_phy_register_access *cmd =
6909                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6910         enum i40e_status_code status;
6911
6912         i40e_fill_default_direct_cmd_desc(&desc,
6913                                           i40e_aqc_opc_set_phy_register);
6914
6915         cmd->phy_interface = phy_select;
6916         cmd->dev_addres = dev_addr;
6917         cmd->reg_address = reg_addr;
6918         cmd->reg_value = reg_val;
6919
6920         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6921
6922         return status;
6923 }
6924
6925 /**
6926  * i40e_aq_get_phy_register
6927  * @hw: pointer to the hw struct
6928  * @phy_select: select which phy should be accessed
6929  * @dev_addr: PHY device address
6930  * @reg_addr: PHY register address
6931  * @reg_val: read register value
6932  * @cmd_details: pointer to command details structure or NULL
6933  *
6934  * Read the external PHY register.
6935  **/
6936 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
6937                                 u8 phy_select, u8 dev_addr,
6938                                 u32 reg_addr, u32 *reg_val,
6939                                 struct i40e_asq_cmd_details *cmd_details)
6940 {
6941         struct i40e_aq_desc desc;
6942         struct i40e_aqc_phy_register_access *cmd =
6943                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6944         enum i40e_status_code status;
6945
6946         i40e_fill_default_direct_cmd_desc(&desc,
6947                                           i40e_aqc_opc_get_phy_register);
6948
6949         cmd->phy_interface = phy_select;
6950         cmd->dev_addres = dev_addr;
6951         cmd->reg_address = reg_addr;
6952
6953         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6954         if (!status)
6955                 *reg_val = cmd->reg_value;
6956
6957         return status;
6958 }
6959
6960 #ifdef VF_DRIVER
6961
6962 /**
6963  * i40e_aq_send_msg_to_pf
6964  * @hw: pointer to the hardware structure
6965  * @v_opcode: opcodes for VF-PF communication
6966  * @v_retval: return error code
6967  * @msg: pointer to the msg buffer
6968  * @msglen: msg length
6969  * @cmd_details: pointer to command details
6970  *
6971  * Send message to PF driver using admin queue. By default, this message
6972  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6973  * completion before returning.
6974  **/
6975 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6976                                 enum virtchnl_ops v_opcode,
6977                                 enum i40e_status_code v_retval,
6978                                 u8 *msg, u16 msglen,
6979                                 struct i40e_asq_cmd_details *cmd_details)
6980 {
6981         struct i40e_aq_desc desc;
6982         struct i40e_asq_cmd_details details;
6983         enum i40e_status_code status;
6984
6985         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6986         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6987         desc.cookie_high = CPU_TO_LE32(v_opcode);
6988         desc.cookie_low = CPU_TO_LE32(v_retval);
6989         if (msglen) {
6990                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6991                                                 | I40E_AQ_FLAG_RD));
6992                 if (msglen > I40E_AQ_LARGE_BUF)
6993                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6994                 desc.datalen = CPU_TO_LE16(msglen);
6995         }
6996         if (!cmd_details) {
6997                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6998                 details.async = true;
6999                 cmd_details = &details;
7000         }
7001         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7002                                        msglen, cmd_details);
7003         return status;
7004 }
7005
7006 /**
7007  * i40e_vf_parse_hw_config
7008  * @hw: pointer to the hardware structure
7009  * @msg: pointer to the virtual channel VF resource structure
7010  *
7011  * Given a VF resource message from the PF, populate the hw struct
7012  * with appropriate information.
7013  **/
7014 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7015                              struct virtchnl_vf_resource *msg)
7016 {
7017         struct virtchnl_vsi_resource *vsi_res;
7018         int i;
7019
7020         vsi_res = &msg->vsi_res[0];
7021
7022         hw->dev_caps.num_vsis = msg->num_vsis;
7023         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7024         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7025         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7026         hw->dev_caps.dcb = msg->vf_offload_flags &
7027                            VIRTCHNL_VF_OFFLOAD_L2;
7028         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7029                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7030         for (i = 0; i < msg->num_vsis; i++) {
7031                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7032                         i40e_memcpy(hw->mac.perm_addr,
7033                                     vsi_res->default_mac_addr,
7034                                     ETH_ALEN,
7035                                     I40E_NONDMA_TO_NONDMA);
7036                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7037                                     ETH_ALEN,
7038                                     I40E_NONDMA_TO_NONDMA);
7039                 }
7040                 vsi_res++;
7041         }
7042 }
7043
7044 /**
7045  * i40e_vf_reset
7046  * @hw: pointer to the hardware structure
7047  *
7048  * Send a VF_RESET message to the PF. Does not wait for response from PF
7049  * as none will be forthcoming. Immediately after calling this function,
7050  * the admin queue should be shut down and (optionally) reinitialized.
7051  **/
7052 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7053 {
7054         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7055                                       I40E_SUCCESS, NULL, 0, NULL);
7056 }
7057 #endif /* VF_DRIVER */
7058
7059 /**
7060  * i40e_aq_set_arp_proxy_config
7061  * @hw: pointer to the HW structure
7062  * @proxy_config - pointer to proxy config command table struct
7063  * @cmd_details: pointer to command details
7064  *
7065  * Set ARP offload parameters from pre-populated
7066  * i40e_aqc_arp_proxy_data struct
7067  **/
7068 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7069                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7070                                 struct i40e_asq_cmd_details *cmd_details)
7071 {
7072         struct i40e_aq_desc desc;
7073         enum i40e_status_code status;
7074
7075         if (!proxy_config)
7076                 return I40E_ERR_PARAM;
7077
7078         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7079
7080         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7081         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7082         desc.params.external.addr_high =
7083                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7084         desc.params.external.addr_low =
7085                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7086         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7087
7088         status = i40e_asq_send_command(hw, &desc, proxy_config,
7089                                        sizeof(struct i40e_aqc_arp_proxy_data),
7090                                        cmd_details);
7091
7092         return status;
7093 }
7094
7095 /**
7096  * i40e_aq_opc_set_ns_proxy_table_entry
7097  * @hw: pointer to the HW structure
7098  * @ns_proxy_table_entry: pointer to NS table entry command struct
7099  * @cmd_details: pointer to command details
7100  *
7101  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7102  * from pre-populated i40e_aqc_ns_proxy_data struct
7103  **/
7104 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7105                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7106                         struct i40e_asq_cmd_details *cmd_details)
7107 {
7108         struct i40e_aq_desc desc;
7109         enum i40e_status_code status;
7110
7111         if (!ns_proxy_table_entry)
7112                 return I40E_ERR_PARAM;
7113
7114         i40e_fill_default_direct_cmd_desc(&desc,
7115                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7116
7117         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7118         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7119         desc.params.external.addr_high =
7120                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7121         desc.params.external.addr_low =
7122                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7123         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7124
7125         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7126                                        sizeof(struct i40e_aqc_ns_proxy_data),
7127                                        cmd_details);
7128
7129         return status;
7130 }
7131
7132 /**
7133  * i40e_aq_set_clear_wol_filter
7134  * @hw: pointer to the hw struct
7135  * @filter_index: index of filter to modify (0-7)
7136  * @filter: buffer containing filter to be set
7137  * @set_filter: true to set filter, false to clear filter
7138  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7139  *              if false, pass through packets may cause wake-up
7140  * @filter_valid: true if filter action is valid
7141  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7142  * @cmd_details: pointer to command details structure or NULL
7143  *
7144  * Set or clear WoL filter for port attached to the PF
7145  **/
7146 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7147                                 u8 filter_index,
7148                                 struct i40e_aqc_set_wol_filter_data *filter,
7149                                 bool set_filter, bool no_wol_tco,
7150                                 bool filter_valid, bool no_wol_tco_valid,
7151                                 struct i40e_asq_cmd_details *cmd_details)
7152 {
7153         struct i40e_aq_desc desc;
7154         struct i40e_aqc_set_wol_filter *cmd =
7155                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7156         enum i40e_status_code status;
7157         u16 cmd_flags = 0;
7158         u16 valid_flags = 0;
7159         u16 buff_len = 0;
7160
7161         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7162
7163         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7164                 return  I40E_ERR_PARAM;
7165         cmd->filter_index = CPU_TO_LE16(filter_index);
7166
7167         if (set_filter) {
7168                 if (!filter)
7169                         return  I40E_ERR_PARAM;
7170
7171                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7172                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7173         }
7174
7175         if (no_wol_tco)
7176                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7177         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7178
7179         if (filter_valid)
7180                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7181         if (no_wol_tco_valid)
7182                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7183         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7184
7185         buff_len = sizeof(*filter);
7186         desc.datalen = CPU_TO_LE16(buff_len);
7187
7188         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7189         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7190
7191         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7192         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7193
7194         status = i40e_asq_send_command(hw, &desc, filter,
7195                                        buff_len, cmd_details);
7196
7197         return status;
7198 }
7199
7200 /**
7201  * i40e_aq_get_wake_event_reason
7202  * @hw: pointer to the hw struct
7203  * @wake_reason: return value, index of matching filter
7204  * @cmd_details: pointer to command details structure or NULL
7205  *
7206  * Get information for the reason of a Wake Up event
7207  **/
7208 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7209                                 u16 *wake_reason,
7210                                 struct i40e_asq_cmd_details *cmd_details)
7211 {
7212         struct i40e_aq_desc desc;
7213         struct i40e_aqc_get_wake_reason_completion *resp =
7214                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7215         enum i40e_status_code status;
7216
7217         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7218
7219         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7220
7221         if (status == I40E_SUCCESS)
7222                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7223
7224         return status;
7225 }
7226
7227 /**
7228 * i40e_aq_clear_all_wol_filters
7229 * @hw: pointer to the hw struct
7230 * @cmd_details: pointer to command details structure or NULL
7231 *
7232 * Get information for the reason of a Wake Up event
7233 **/
7234 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7235         struct i40e_asq_cmd_details *cmd_details)
7236 {
7237         struct i40e_aq_desc desc;
7238         enum i40e_status_code status;
7239
7240         i40e_fill_default_direct_cmd_desc(&desc,
7241                                           i40e_aqc_opc_clear_all_wol_filters);
7242
7243         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7244
7245         return status;
7246 }
7247
7248
7249 /**
7250  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7251  * @hw: pointer to the hw struct
7252  * @buff: command buffer (size in bytes = buff_size)
7253  * @buff_size: buffer size in bytes
7254  * @track_id: package tracking id
7255  * @error_offset: returns error offset
7256  * @error_info: returns error information
7257  * @cmd_details: pointer to command details structure or NULL
7258  **/
7259 enum
7260 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7261                                    u16 buff_size, u32 track_id,
7262                                    u32 *error_offset, u32 *error_info,
7263                                    struct i40e_asq_cmd_details *cmd_details)
7264 {
7265         struct i40e_aq_desc desc;
7266         struct i40e_aqc_write_personalization_profile *cmd =
7267                 (struct i40e_aqc_write_personalization_profile *)
7268                 &desc.params.raw;
7269         struct i40e_aqc_write_ddp_resp *resp;
7270         enum i40e_status_code status;
7271
7272         i40e_fill_default_direct_cmd_desc(&desc,
7273                                   i40e_aqc_opc_write_personalization_profile);
7274
7275         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7276         if (buff_size > I40E_AQ_LARGE_BUF)
7277                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7278
7279         desc.datalen = CPU_TO_LE16(buff_size);
7280
7281         cmd->profile_track_id = CPU_TO_LE32(track_id);
7282
7283         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7284         if (!status) {
7285                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7286                 if (error_offset)
7287                         *error_offset = LE32_TO_CPU(resp->error_offset);
7288                 if (error_info)
7289                         *error_info = LE32_TO_CPU(resp->error_info);
7290         }
7291
7292         return status;
7293 }
7294
7295 /**
7296  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7297  * @hw: pointer to the hw struct
7298  * @buff: command buffer (size in bytes = buff_size)
7299  * @buff_size: buffer size in bytes
7300  * @cmd_details: pointer to command details structure or NULL
7301  **/
7302 enum
7303 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7304                                       u16 buff_size, u8 flags,
7305                                       struct i40e_asq_cmd_details *cmd_details)
7306 {
7307         struct i40e_aq_desc desc;
7308         struct i40e_aqc_get_applied_profiles *cmd =
7309                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7310         enum i40e_status_code status;
7311
7312         i40e_fill_default_direct_cmd_desc(&desc,
7313                           i40e_aqc_opc_get_personalization_profile_list);
7314
7315         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7316         if (buff_size > I40E_AQ_LARGE_BUF)
7317                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7318         desc.datalen = CPU_TO_LE16(buff_size);
7319
7320         cmd->flags = flags;
7321
7322         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7323
7324         return status;
7325 }
7326
7327 /**
7328  * i40e_find_segment_in_package
7329  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7330  * @pkg_hdr: pointer to the package header to be searched
7331  *
7332  * This function searches a package file for a particular segment type. On
7333  * success it returns a pointer to the segment header, otherwise it will
7334  * return NULL.
7335  **/
7336 struct i40e_generic_seg_header *
7337 i40e_find_segment_in_package(u32 segment_type,
7338                              struct i40e_package_header *pkg_hdr)
7339 {
7340         struct i40e_generic_seg_header *segment;
7341         u32 i;
7342
7343         /* Search all package segments for the requested segment type */
7344         for (i = 0; i < pkg_hdr->segment_count; i++) {
7345                 segment =
7346                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7347                          pkg_hdr->segment_offset[i]);
7348
7349                 if (segment->type == segment_type)
7350                         return segment;
7351         }
7352
7353         return NULL;
7354 }
7355
7356 /**
7357  * i40e_write_profile
7358  * @hw: pointer to the hardware structure
7359  * @profile: pointer to the profile segment of the package to be downloaded
7360  * @track_id: package tracking id
7361  *
7362  * Handles the download of a complete package.
7363  */
7364 enum i40e_status_code
7365 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7366                    u32 track_id)
7367 {
7368         enum i40e_status_code status = I40E_SUCCESS;
7369         struct i40e_section_table *sec_tbl;
7370         struct i40e_profile_section_header *sec = NULL;
7371         u32 dev_cnt;
7372         u32 vendor_dev_id;
7373         u32 *nvm;
7374         u32 section_size = 0;
7375         u32 offset = 0, info = 0;
7376         u32 i;
7377
7378         dev_cnt = profile->device_table_count;
7379
7380         for (i = 0; i < dev_cnt; i++) {
7381                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7382                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID)
7383                         if (hw->device_id == (vendor_dev_id & 0xFFFF))
7384                                 break;
7385         }
7386         if (i == dev_cnt) {
7387                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
7388                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7389         }
7390
7391         nvm = (u32 *)&profile->device_table[dev_cnt];
7392         sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
7393
7394         for (i = 0; i < sec_tbl->section_count; i++) {
7395                 sec = (struct i40e_profile_section_header *)((u8 *)profile +
7396                                              sec_tbl->section_offset[i]);
7397
7398                 /* Skip 'AQ', 'note' and 'name' sections */
7399                 if (sec->section.type != SECTION_TYPE_MMIO)
7400                         continue;
7401
7402                 section_size = sec->section.size +
7403                         sizeof(struct i40e_profile_section_header);
7404
7405                 /* Write profile */
7406                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7407                                            track_id, &offset, &info, NULL);
7408                 if (status) {
7409                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7410                                    "Failed to write profile: offset %d, info %d",
7411                                    offset, info);
7412                         break;
7413                 }
7414         }
7415         return status;
7416 }
7417
7418 /**
7419  * i40e_add_pinfo_to_list
7420  * @hw: pointer to the hardware structure
7421  * @profile: pointer to the profile segment of the package
7422  * @profile_info_sec: buffer for information section
7423  * @track_id: package tracking id
7424  *
7425  * Register a profile to the list of loaded profiles.
7426  */
7427 enum i40e_status_code
7428 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7429                        struct i40e_profile_segment *profile,
7430                        u8 *profile_info_sec, u32 track_id)
7431 {
7432         enum i40e_status_code status = I40E_SUCCESS;
7433         struct i40e_profile_section_header *sec = NULL;
7434         struct i40e_profile_info *pinfo;
7435         u32 offset = 0, info = 0;
7436
7437         sec = (struct i40e_profile_section_header *)profile_info_sec;
7438         sec->tbl_size = 1;
7439         sec->data_end = sizeof(struct i40e_profile_section_header) +
7440                         sizeof(struct i40e_profile_info);
7441         sec->section.type = SECTION_TYPE_INFO;
7442         sec->section.offset = sizeof(struct i40e_profile_section_header);
7443         sec->section.size = sizeof(struct i40e_profile_info);
7444         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7445                                              sec->section.offset);
7446         pinfo->track_id = track_id;
7447         pinfo->version = profile->version;
7448         pinfo->op = I40E_DDP_ADD_TRACKID;
7449         memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
7450
7451         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7452                                    track_id, &offset, &info, NULL);
7453         return status;
7454 }