1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 hw->mac.type = I40E_MAC_X722;
88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
89 case I40E_DEV_ID_X722_VF:
90 #ifdef X722_A0_SUPPORT
91 case I40E_DEV_ID_X722_A0_VF:
93 hw->mac.type = I40E_MAC_X722_VF;
95 #endif /* INTEGRATED_VF || VF_DRIVER */
96 #endif /* X722_SUPPORT */
97 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
99 case I40E_DEV_ID_VF_HV:
100 hw->mac.type = I40E_MAC_VF;
104 hw->mac.type = I40E_MAC_GENERIC;
108 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
111 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
112 hw->mac.type, status);
116 #ifndef I40E_NDIS_SUPPORT
118 * i40e_aq_str - convert AQ err code to a string
119 * @hw: pointer to the HW structure
120 * @aq_err: the AQ error code to convert
122 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
127 case I40E_AQ_RC_EPERM:
128 return "I40E_AQ_RC_EPERM";
129 case I40E_AQ_RC_ENOENT:
130 return "I40E_AQ_RC_ENOENT";
131 case I40E_AQ_RC_ESRCH:
132 return "I40E_AQ_RC_ESRCH";
133 case I40E_AQ_RC_EINTR:
134 return "I40E_AQ_RC_EINTR";
136 return "I40E_AQ_RC_EIO";
137 case I40E_AQ_RC_ENXIO:
138 return "I40E_AQ_RC_ENXIO";
139 case I40E_AQ_RC_E2BIG:
140 return "I40E_AQ_RC_E2BIG";
141 case I40E_AQ_RC_EAGAIN:
142 return "I40E_AQ_RC_EAGAIN";
143 case I40E_AQ_RC_ENOMEM:
144 return "I40E_AQ_RC_ENOMEM";
145 case I40E_AQ_RC_EACCES:
146 return "I40E_AQ_RC_EACCES";
147 case I40E_AQ_RC_EFAULT:
148 return "I40E_AQ_RC_EFAULT";
149 case I40E_AQ_RC_EBUSY:
150 return "I40E_AQ_RC_EBUSY";
151 case I40E_AQ_RC_EEXIST:
152 return "I40E_AQ_RC_EEXIST";
153 case I40E_AQ_RC_EINVAL:
154 return "I40E_AQ_RC_EINVAL";
155 case I40E_AQ_RC_ENOTTY:
156 return "I40E_AQ_RC_ENOTTY";
157 case I40E_AQ_RC_ENOSPC:
158 return "I40E_AQ_RC_ENOSPC";
159 case I40E_AQ_RC_ENOSYS:
160 return "I40E_AQ_RC_ENOSYS";
161 case I40E_AQ_RC_ERANGE:
162 return "I40E_AQ_RC_ERANGE";
163 case I40E_AQ_RC_EFLUSHED:
164 return "I40E_AQ_RC_EFLUSHED";
165 case I40E_AQ_RC_BAD_ADDR:
166 return "I40E_AQ_RC_BAD_ADDR";
167 case I40E_AQ_RC_EMODE:
168 return "I40E_AQ_RC_EMODE";
169 case I40E_AQ_RC_EFBIG:
170 return "I40E_AQ_RC_EFBIG";
173 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
178 * i40e_stat_str - convert status err code to a string
179 * @hw: pointer to the HW structure
180 * @stat_err: the status error code to convert
182 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
188 return "I40E_ERR_NVM";
189 case I40E_ERR_NVM_CHECKSUM:
190 return "I40E_ERR_NVM_CHECKSUM";
192 return "I40E_ERR_PHY";
193 case I40E_ERR_CONFIG:
194 return "I40E_ERR_CONFIG";
196 return "I40E_ERR_PARAM";
197 case I40E_ERR_MAC_TYPE:
198 return "I40E_ERR_MAC_TYPE";
199 case I40E_ERR_UNKNOWN_PHY:
200 return "I40E_ERR_UNKNOWN_PHY";
201 case I40E_ERR_LINK_SETUP:
202 return "I40E_ERR_LINK_SETUP";
203 case I40E_ERR_ADAPTER_STOPPED:
204 return "I40E_ERR_ADAPTER_STOPPED";
205 case I40E_ERR_INVALID_MAC_ADDR:
206 return "I40E_ERR_INVALID_MAC_ADDR";
207 case I40E_ERR_DEVICE_NOT_SUPPORTED:
208 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
209 case I40E_ERR_MASTER_REQUESTS_PENDING:
210 return "I40E_ERR_MASTER_REQUESTS_PENDING";
211 case I40E_ERR_INVALID_LINK_SETTINGS:
212 return "I40E_ERR_INVALID_LINK_SETTINGS";
213 case I40E_ERR_AUTONEG_NOT_COMPLETE:
214 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
215 case I40E_ERR_RESET_FAILED:
216 return "I40E_ERR_RESET_FAILED";
217 case I40E_ERR_SWFW_SYNC:
218 return "I40E_ERR_SWFW_SYNC";
219 case I40E_ERR_NO_AVAILABLE_VSI:
220 return "I40E_ERR_NO_AVAILABLE_VSI";
221 case I40E_ERR_NO_MEMORY:
222 return "I40E_ERR_NO_MEMORY";
223 case I40E_ERR_BAD_PTR:
224 return "I40E_ERR_BAD_PTR";
225 case I40E_ERR_RING_FULL:
226 return "I40E_ERR_RING_FULL";
227 case I40E_ERR_INVALID_PD_ID:
228 return "I40E_ERR_INVALID_PD_ID";
229 case I40E_ERR_INVALID_QP_ID:
230 return "I40E_ERR_INVALID_QP_ID";
231 case I40E_ERR_INVALID_CQ_ID:
232 return "I40E_ERR_INVALID_CQ_ID";
233 case I40E_ERR_INVALID_CEQ_ID:
234 return "I40E_ERR_INVALID_CEQ_ID";
235 case I40E_ERR_INVALID_AEQ_ID:
236 return "I40E_ERR_INVALID_AEQ_ID";
237 case I40E_ERR_INVALID_SIZE:
238 return "I40E_ERR_INVALID_SIZE";
239 case I40E_ERR_INVALID_ARP_INDEX:
240 return "I40E_ERR_INVALID_ARP_INDEX";
241 case I40E_ERR_INVALID_FPM_FUNC_ID:
242 return "I40E_ERR_INVALID_FPM_FUNC_ID";
243 case I40E_ERR_QP_INVALID_MSG_SIZE:
244 return "I40E_ERR_QP_INVALID_MSG_SIZE";
245 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
246 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
247 case I40E_ERR_INVALID_FRAG_COUNT:
248 return "I40E_ERR_INVALID_FRAG_COUNT";
249 case I40E_ERR_QUEUE_EMPTY:
250 return "I40E_ERR_QUEUE_EMPTY";
251 case I40E_ERR_INVALID_ALIGNMENT:
252 return "I40E_ERR_INVALID_ALIGNMENT";
253 case I40E_ERR_FLUSHED_QUEUE:
254 return "I40E_ERR_FLUSHED_QUEUE";
255 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
256 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
257 case I40E_ERR_INVALID_IMM_DATA_SIZE:
258 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
259 case I40E_ERR_TIMEOUT:
260 return "I40E_ERR_TIMEOUT";
261 case I40E_ERR_OPCODE_MISMATCH:
262 return "I40E_ERR_OPCODE_MISMATCH";
263 case I40E_ERR_CQP_COMPL_ERROR:
264 return "I40E_ERR_CQP_COMPL_ERROR";
265 case I40E_ERR_INVALID_VF_ID:
266 return "I40E_ERR_INVALID_VF_ID";
267 case I40E_ERR_INVALID_HMCFN_ID:
268 return "I40E_ERR_INVALID_HMCFN_ID";
269 case I40E_ERR_BACKING_PAGE_ERROR:
270 return "I40E_ERR_BACKING_PAGE_ERROR";
271 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
272 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
273 case I40E_ERR_INVALID_PBLE_INDEX:
274 return "I40E_ERR_INVALID_PBLE_INDEX";
275 case I40E_ERR_INVALID_SD_INDEX:
276 return "I40E_ERR_INVALID_SD_INDEX";
277 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
278 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
279 case I40E_ERR_INVALID_SD_TYPE:
280 return "I40E_ERR_INVALID_SD_TYPE";
281 case I40E_ERR_MEMCPY_FAILED:
282 return "I40E_ERR_MEMCPY_FAILED";
283 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
284 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
285 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
286 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
287 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
288 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
289 case I40E_ERR_SRQ_ENABLED:
290 return "I40E_ERR_SRQ_ENABLED";
291 case I40E_ERR_ADMIN_QUEUE_ERROR:
292 return "I40E_ERR_ADMIN_QUEUE_ERROR";
293 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
294 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
295 case I40E_ERR_BUF_TOO_SHORT:
296 return "I40E_ERR_BUF_TOO_SHORT";
297 case I40E_ERR_ADMIN_QUEUE_FULL:
298 return "I40E_ERR_ADMIN_QUEUE_FULL";
299 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
300 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
301 case I40E_ERR_BAD_IWARP_CQE:
302 return "I40E_ERR_BAD_IWARP_CQE";
303 case I40E_ERR_NVM_BLANK_MODE:
304 return "I40E_ERR_NVM_BLANK_MODE";
305 case I40E_ERR_NOT_IMPLEMENTED:
306 return "I40E_ERR_NOT_IMPLEMENTED";
307 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
308 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
309 case I40E_ERR_DIAG_TEST_FAILED:
310 return "I40E_ERR_DIAG_TEST_FAILED";
311 case I40E_ERR_NOT_READY:
312 return "I40E_ERR_NOT_READY";
313 case I40E_NOT_SUPPORTED:
314 return "I40E_NOT_SUPPORTED";
315 case I40E_ERR_FIRMWARE_API_VERSION:
316 return "I40E_ERR_FIRMWARE_API_VERSION";
319 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
323 #endif /* I40E_NDIS_SUPPORT */
326 * @hw: debug mask related to admin queue
328 * @desc: pointer to admin queue descriptor
329 * @buffer: pointer to command buffer
330 * @buf_len: max length of buffer
332 * Dumps debug log about adminq command with descriptor contents.
334 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
335 void *buffer, u16 buf_len)
337 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
338 u16 len = LE16_TO_CPU(aq_desc->datalen);
339 u8 *buf = (u8 *)buffer;
342 if ((!(mask & hw->debug_mask)) || (desc == NULL))
346 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
347 LE16_TO_CPU(aq_desc->opcode),
348 LE16_TO_CPU(aq_desc->flags),
349 LE16_TO_CPU(aq_desc->datalen),
350 LE16_TO_CPU(aq_desc->retval));
351 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
352 LE32_TO_CPU(aq_desc->cookie_high),
353 LE32_TO_CPU(aq_desc->cookie_low));
354 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
355 LE32_TO_CPU(aq_desc->params.internal.param0),
356 LE32_TO_CPU(aq_desc->params.internal.param1));
357 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
358 LE32_TO_CPU(aq_desc->params.external.addr_high),
359 LE32_TO_CPU(aq_desc->params.external.addr_low));
361 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
362 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
365 /* write the full 16-byte chunks */
366 for (i = 0; i < (len - 16); i += 16)
368 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
369 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
370 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
371 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
372 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
373 /* the most we could have left is 16 bytes, pad with zeros */
379 memset(d_buf, 0, sizeof(d_buf));
380 for (j = 0; i < len; j++, i++)
383 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
384 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
385 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
386 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
387 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
393 * i40e_check_asq_alive
394 * @hw: pointer to the hw struct
396 * Returns true if Queue is enabled else false.
398 bool i40e_check_asq_alive(struct i40e_hw *hw)
404 return !!(rd32(hw, hw->aq.asq.len) &
405 I40E_PF_ATQLEN_ATQENABLE_MASK);
407 return !!(rd32(hw, hw->aq.asq.len) &
408 I40E_PF_ATQLEN_ATQENABLE_MASK);
409 #endif /* INTEGRATED_VF */
410 #endif /* PF_DRIVER */
414 return !!(rd32(hw, hw->aq.asq.len) &
415 I40E_VF_ATQLEN1_ATQENABLE_MASK);
417 return !!(rd32(hw, hw->aq.asq.len) &
418 I40E_VF_ATQLEN1_ATQENABLE_MASK);
419 #endif /* INTEGRATED_VF */
420 #endif /* VF_DRIVER */
425 * i40e_aq_queue_shutdown
426 * @hw: pointer to the hw struct
427 * @unloading: is the driver unloading itself
429 * Tell the Firmware that we're shutting down the AdminQ and whether
430 * or not the driver is unloading as well.
432 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
435 struct i40e_aq_desc desc;
436 struct i40e_aqc_queue_shutdown *cmd =
437 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
438 enum i40e_status_code status;
440 i40e_fill_default_direct_cmd_desc(&desc,
441 i40e_aqc_opc_queue_shutdown);
444 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
445 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
452 * i40e_aq_get_set_rss_lut
453 * @hw: pointer to the hardware structure
454 * @vsi_id: vsi fw index
455 * @pf_lut: for PF table set true, for VSI table set false
456 * @lut: pointer to the lut buffer provided by the caller
457 * @lut_size: size of the lut buffer
458 * @set: set true to set the table, false to get the table
460 * Internal function to get or set RSS look up table
462 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
463 u16 vsi_id, bool pf_lut,
464 u8 *lut, u16 lut_size,
467 enum i40e_status_code status;
468 struct i40e_aq_desc desc;
469 struct i40e_aqc_get_set_rss_lut *cmd_resp =
470 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
473 i40e_fill_default_direct_cmd_desc(&desc,
474 i40e_aqc_opc_set_rss_lut);
476 i40e_fill_default_direct_cmd_desc(&desc,
477 i40e_aqc_opc_get_rss_lut);
479 /* Indirect command */
480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
484 CPU_TO_LE16((u16)((vsi_id <<
485 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
486 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
487 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
490 cmd_resp->flags |= CPU_TO_LE16((u16)
491 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
492 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
493 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
495 cmd_resp->flags |= CPU_TO_LE16((u16)
496 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
497 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
498 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
500 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
506 * i40e_aq_get_rss_lut
507 * @hw: pointer to the hardware structure
508 * @vsi_id: vsi fw index
509 * @pf_lut: for PF table set true, for VSI table set false
510 * @lut: pointer to the lut buffer provided by the caller
511 * @lut_size: size of the lut buffer
513 * get the RSS lookup table, PF or VSI type
515 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
516 bool pf_lut, u8 *lut, u16 lut_size)
518 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
523 * i40e_aq_set_rss_lut
524 * @hw: pointer to the hardware structure
525 * @vsi_id: vsi fw index
526 * @pf_lut: for PF table set true, for VSI table set false
527 * @lut: pointer to the lut buffer provided by the caller
528 * @lut_size: size of the lut buffer
530 * set the RSS lookup table, PF or VSI type
532 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
533 bool pf_lut, u8 *lut, u16 lut_size)
535 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
539 * i40e_aq_get_set_rss_key
540 * @hw: pointer to the hw struct
541 * @vsi_id: vsi fw index
542 * @key: pointer to key info struct
543 * @set: set true to set the key, false to get the key
545 * get the RSS key per VSI
547 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
549 struct i40e_aqc_get_set_rss_key_data *key,
552 enum i40e_status_code status;
553 struct i40e_aq_desc desc;
554 struct i40e_aqc_get_set_rss_key *cmd_resp =
555 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
556 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
559 i40e_fill_default_direct_cmd_desc(&desc,
560 i40e_aqc_opc_set_rss_key);
562 i40e_fill_default_direct_cmd_desc(&desc,
563 i40e_aqc_opc_get_rss_key);
565 /* Indirect command */
566 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
567 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
570 CPU_TO_LE16((u16)((vsi_id <<
571 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
572 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
573 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
575 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
581 * i40e_aq_get_rss_key
582 * @hw: pointer to the hw struct
583 * @vsi_id: vsi fw index
584 * @key: pointer to key info struct
587 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
589 struct i40e_aqc_get_set_rss_key_data *key)
591 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
595 * i40e_aq_set_rss_key
596 * @hw: pointer to the hw struct
597 * @vsi_id: vsi fw index
598 * @key: pointer to key info struct
600 * set the RSS key per VSI
602 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
604 struct i40e_aqc_get_set_rss_key_data *key)
606 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
608 #endif /* X722_SUPPORT */
610 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
611 * hardware to a bit-field that can be used by SW to more easily determine the
614 * Macros are used to shorten the table lines and make this table human
617 * We store the PTYPE in the top byte of the bit field - this is just so that
618 * we can check that the table doesn't have a row missing, as the index into
619 * the table should be the PTYPE.
623 * IF NOT i40e_ptype_lookup[ptype].known
626 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
627 * Use the rest of the fields to look at the tunnels, inner protocols, etc
629 * Use the enum i40e_rx_l2_ptype to decode the packet type
633 /* macro to make the table lines short */
634 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
637 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
638 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
639 I40E_RX_PTYPE_##OUTER_FRAG, \
640 I40E_RX_PTYPE_TUNNEL_##T, \
641 I40E_RX_PTYPE_TUNNEL_END_##TE, \
642 I40E_RX_PTYPE_##TEF, \
643 I40E_RX_PTYPE_INNER_PROT_##I, \
644 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
646 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
647 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
649 /* shorter macros makes the table fit but are terse */
650 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
651 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
652 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
654 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
655 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
656 /* L2 Packet types */
657 I40E_PTT_UNUSED_ENTRY(0),
658 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
659 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
660 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
661 I40E_PTT_UNUSED_ENTRY(4),
662 I40E_PTT_UNUSED_ENTRY(5),
663 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
664 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT_UNUSED_ENTRY(8),
666 I40E_PTT_UNUSED_ENTRY(9),
667 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
668 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
669 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
670 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
680 /* Non Tunneled IPv4 */
681 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
682 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
683 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
684 I40E_PTT_UNUSED_ENTRY(25),
685 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
686 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
687 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
690 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
691 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
692 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
693 I40E_PTT_UNUSED_ENTRY(32),
694 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
695 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
696 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
699 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
700 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
701 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
702 I40E_PTT_UNUSED_ENTRY(39),
703 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
704 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
705 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
707 /* IPv4 --> GRE/NAT */
708 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
710 /* IPv4 --> GRE/NAT --> IPv4 */
711 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
712 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
713 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
714 I40E_PTT_UNUSED_ENTRY(47),
715 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
716 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
717 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
719 /* IPv4 --> GRE/NAT --> IPv6 */
720 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
721 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
722 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
723 I40E_PTT_UNUSED_ENTRY(54),
724 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
725 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
726 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
728 /* IPv4 --> GRE/NAT --> MAC */
729 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
731 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
732 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
733 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
734 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
735 I40E_PTT_UNUSED_ENTRY(62),
736 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
737 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
738 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
740 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
741 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
742 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
743 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
744 I40E_PTT_UNUSED_ENTRY(69),
745 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
746 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
747 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
749 /* IPv4 --> GRE/NAT --> MAC/VLAN */
750 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
752 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
753 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
754 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
755 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
756 I40E_PTT_UNUSED_ENTRY(77),
757 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
758 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
759 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
761 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
762 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
763 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
764 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
765 I40E_PTT_UNUSED_ENTRY(84),
766 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
767 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
768 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
770 /* Non Tunneled IPv6 */
771 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
772 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
773 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
774 I40E_PTT_UNUSED_ENTRY(91),
775 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
776 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
777 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
780 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
781 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
782 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
783 I40E_PTT_UNUSED_ENTRY(98),
784 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
785 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
786 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
789 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
790 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
791 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
792 I40E_PTT_UNUSED_ENTRY(105),
793 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
794 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
795 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
797 /* IPv6 --> GRE/NAT */
798 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
800 /* IPv6 --> GRE/NAT -> IPv4 */
801 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
802 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
803 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
804 I40E_PTT_UNUSED_ENTRY(113),
805 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
806 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
807 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
809 /* IPv6 --> GRE/NAT -> IPv6 */
810 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
811 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
812 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
813 I40E_PTT_UNUSED_ENTRY(120),
814 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
815 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
816 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
818 /* IPv6 --> GRE/NAT -> MAC */
819 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
821 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
822 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
823 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
824 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
825 I40E_PTT_UNUSED_ENTRY(128),
826 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
827 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
828 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
830 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
831 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
832 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
833 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
834 I40E_PTT_UNUSED_ENTRY(135),
835 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
836 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
837 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
839 /* IPv6 --> GRE/NAT -> MAC/VLAN */
840 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
842 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
843 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
844 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
845 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
846 I40E_PTT_UNUSED_ENTRY(143),
847 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
848 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
849 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
851 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
852 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
853 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
854 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
855 I40E_PTT_UNUSED_ENTRY(150),
856 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
857 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
858 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
861 I40E_PTT_UNUSED_ENTRY(154),
862 I40E_PTT_UNUSED_ENTRY(155),
863 I40E_PTT_UNUSED_ENTRY(156),
864 I40E_PTT_UNUSED_ENTRY(157),
865 I40E_PTT_UNUSED_ENTRY(158),
866 I40E_PTT_UNUSED_ENTRY(159),
868 I40E_PTT_UNUSED_ENTRY(160),
869 I40E_PTT_UNUSED_ENTRY(161),
870 I40E_PTT_UNUSED_ENTRY(162),
871 I40E_PTT_UNUSED_ENTRY(163),
872 I40E_PTT_UNUSED_ENTRY(164),
873 I40E_PTT_UNUSED_ENTRY(165),
874 I40E_PTT_UNUSED_ENTRY(166),
875 I40E_PTT_UNUSED_ENTRY(167),
876 I40E_PTT_UNUSED_ENTRY(168),
877 I40E_PTT_UNUSED_ENTRY(169),
879 I40E_PTT_UNUSED_ENTRY(170),
880 I40E_PTT_UNUSED_ENTRY(171),
881 I40E_PTT_UNUSED_ENTRY(172),
882 I40E_PTT_UNUSED_ENTRY(173),
883 I40E_PTT_UNUSED_ENTRY(174),
884 I40E_PTT_UNUSED_ENTRY(175),
885 I40E_PTT_UNUSED_ENTRY(176),
886 I40E_PTT_UNUSED_ENTRY(177),
887 I40E_PTT_UNUSED_ENTRY(178),
888 I40E_PTT_UNUSED_ENTRY(179),
890 I40E_PTT_UNUSED_ENTRY(180),
891 I40E_PTT_UNUSED_ENTRY(181),
892 I40E_PTT_UNUSED_ENTRY(182),
893 I40E_PTT_UNUSED_ENTRY(183),
894 I40E_PTT_UNUSED_ENTRY(184),
895 I40E_PTT_UNUSED_ENTRY(185),
896 I40E_PTT_UNUSED_ENTRY(186),
897 I40E_PTT_UNUSED_ENTRY(187),
898 I40E_PTT_UNUSED_ENTRY(188),
899 I40E_PTT_UNUSED_ENTRY(189),
901 I40E_PTT_UNUSED_ENTRY(190),
902 I40E_PTT_UNUSED_ENTRY(191),
903 I40E_PTT_UNUSED_ENTRY(192),
904 I40E_PTT_UNUSED_ENTRY(193),
905 I40E_PTT_UNUSED_ENTRY(194),
906 I40E_PTT_UNUSED_ENTRY(195),
907 I40E_PTT_UNUSED_ENTRY(196),
908 I40E_PTT_UNUSED_ENTRY(197),
909 I40E_PTT_UNUSED_ENTRY(198),
910 I40E_PTT_UNUSED_ENTRY(199),
912 I40E_PTT_UNUSED_ENTRY(200),
913 I40E_PTT_UNUSED_ENTRY(201),
914 I40E_PTT_UNUSED_ENTRY(202),
915 I40E_PTT_UNUSED_ENTRY(203),
916 I40E_PTT_UNUSED_ENTRY(204),
917 I40E_PTT_UNUSED_ENTRY(205),
918 I40E_PTT_UNUSED_ENTRY(206),
919 I40E_PTT_UNUSED_ENTRY(207),
920 I40E_PTT_UNUSED_ENTRY(208),
921 I40E_PTT_UNUSED_ENTRY(209),
923 I40E_PTT_UNUSED_ENTRY(210),
924 I40E_PTT_UNUSED_ENTRY(211),
925 I40E_PTT_UNUSED_ENTRY(212),
926 I40E_PTT_UNUSED_ENTRY(213),
927 I40E_PTT_UNUSED_ENTRY(214),
928 I40E_PTT_UNUSED_ENTRY(215),
929 I40E_PTT_UNUSED_ENTRY(216),
930 I40E_PTT_UNUSED_ENTRY(217),
931 I40E_PTT_UNUSED_ENTRY(218),
932 I40E_PTT_UNUSED_ENTRY(219),
934 I40E_PTT_UNUSED_ENTRY(220),
935 I40E_PTT_UNUSED_ENTRY(221),
936 I40E_PTT_UNUSED_ENTRY(222),
937 I40E_PTT_UNUSED_ENTRY(223),
938 I40E_PTT_UNUSED_ENTRY(224),
939 I40E_PTT_UNUSED_ENTRY(225),
940 I40E_PTT_UNUSED_ENTRY(226),
941 I40E_PTT_UNUSED_ENTRY(227),
942 I40E_PTT_UNUSED_ENTRY(228),
943 I40E_PTT_UNUSED_ENTRY(229),
945 I40E_PTT_UNUSED_ENTRY(230),
946 I40E_PTT_UNUSED_ENTRY(231),
947 I40E_PTT_UNUSED_ENTRY(232),
948 I40E_PTT_UNUSED_ENTRY(233),
949 I40E_PTT_UNUSED_ENTRY(234),
950 I40E_PTT_UNUSED_ENTRY(235),
951 I40E_PTT_UNUSED_ENTRY(236),
952 I40E_PTT_UNUSED_ENTRY(237),
953 I40E_PTT_UNUSED_ENTRY(238),
954 I40E_PTT_UNUSED_ENTRY(239),
956 I40E_PTT_UNUSED_ENTRY(240),
957 I40E_PTT_UNUSED_ENTRY(241),
958 I40E_PTT_UNUSED_ENTRY(242),
959 I40E_PTT_UNUSED_ENTRY(243),
960 I40E_PTT_UNUSED_ENTRY(244),
961 I40E_PTT_UNUSED_ENTRY(245),
962 I40E_PTT_UNUSED_ENTRY(246),
963 I40E_PTT_UNUSED_ENTRY(247),
964 I40E_PTT_UNUSED_ENTRY(248),
965 I40E_PTT_UNUSED_ENTRY(249),
967 I40E_PTT_UNUSED_ENTRY(250),
968 I40E_PTT_UNUSED_ENTRY(251),
969 I40E_PTT_UNUSED_ENTRY(252),
970 I40E_PTT_UNUSED_ENTRY(253),
971 I40E_PTT_UNUSED_ENTRY(254),
972 I40E_PTT_UNUSED_ENTRY(255)
977 * i40e_validate_mac_addr - Validate unicast MAC address
978 * @mac_addr: pointer to MAC address
980 * Tests a MAC address to ensure it is a valid Individual Address
982 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
984 enum i40e_status_code status = I40E_SUCCESS;
986 DEBUGFUNC("i40e_validate_mac_addr");
988 /* Broadcast addresses ARE multicast addresses
989 * Make sure it is not a multicast address
990 * Reject the zero address
992 if (I40E_IS_MULTICAST(mac_addr) ||
993 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
994 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
995 status = I40E_ERR_INVALID_MAC_ADDR;
1002 * i40e_init_shared_code - Initialize the shared code
1003 * @hw: pointer to hardware structure
1005 * This assigns the MAC type and PHY code and inits the NVM.
1006 * Does not touch the hardware. This function must be called prior to any
1007 * other function in the shared code. The i40e_hw structure should be
1008 * memset to 0 prior to calling this function. The following fields in
1009 * hw structure should be filled in prior to calling this function:
1010 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1011 * subsystem_vendor_id, and revision_id
1013 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1015 enum i40e_status_code status = I40E_SUCCESS;
1016 u32 port, ari, func_rid;
1018 DEBUGFUNC("i40e_init_shared_code");
1020 i40e_set_mac_type(hw);
1022 switch (hw->mac.type) {
1023 case I40E_MAC_XL710:
1029 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1032 hw->phy.get_link_info = true;
1034 /* Determine port number and PF number*/
1035 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1036 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1037 hw->port = (u8)port;
1038 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1039 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1040 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1042 hw->pf_id = (u8)(func_rid & 0xff);
1044 hw->pf_id = (u8)(func_rid & 0x7);
1047 if (hw->mac.type == I40E_MAC_X722)
1048 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1051 status = i40e_init_nvm(hw);
1056 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1057 * @hw: pointer to the hw struct
1058 * @flags: a return indicator of what addresses were added to the addr store
1059 * @addrs: the requestor's mac addr store
1060 * @cmd_details: pointer to command details structure or NULL
1062 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1064 struct i40e_aqc_mac_address_read_data *addrs,
1065 struct i40e_asq_cmd_details *cmd_details)
1067 struct i40e_aq_desc desc;
1068 struct i40e_aqc_mac_address_read *cmd_data =
1069 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1070 enum i40e_status_code status;
1072 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1073 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1075 status = i40e_asq_send_command(hw, &desc, addrs,
1076 sizeof(*addrs), cmd_details);
1077 *flags = LE16_TO_CPU(cmd_data->command_flags);
1083 * i40e_aq_mac_address_write - Change the MAC addresses
1084 * @hw: pointer to the hw struct
1085 * @flags: indicates which MAC to be written
1086 * @mac_addr: address to write
1087 * @cmd_details: pointer to command details structure or NULL
1089 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1090 u16 flags, u8 *mac_addr,
1091 struct i40e_asq_cmd_details *cmd_details)
1093 struct i40e_aq_desc desc;
1094 struct i40e_aqc_mac_address_write *cmd_data =
1095 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1096 enum i40e_status_code status;
1098 i40e_fill_default_direct_cmd_desc(&desc,
1099 i40e_aqc_opc_mac_address_write);
1100 cmd_data->command_flags = CPU_TO_LE16(flags);
1101 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1102 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1103 ((u32)mac_addr[3] << 16) |
1104 ((u32)mac_addr[4] << 8) |
1107 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1113 * i40e_get_mac_addr - get MAC address
1114 * @hw: pointer to the HW structure
1115 * @mac_addr: pointer to MAC address
1117 * Reads the adapter's MAC address from register
1119 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1121 struct i40e_aqc_mac_address_read_data addrs;
1122 enum i40e_status_code status;
1125 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1127 if (flags & I40E_AQC_LAN_ADDR_VALID)
1128 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1129 I40E_NONDMA_TO_NONDMA);
1135 * i40e_get_port_mac_addr - get Port MAC address
1136 * @hw: pointer to the HW structure
1137 * @mac_addr: pointer to Port MAC address
1139 * Reads the adapter's Port MAC address
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1143 struct i40e_aqc_mac_address_read_data addrs;
1144 enum i40e_status_code status;
1147 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1151 if (flags & I40E_AQC_PORT_ADDR_VALID)
1152 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1153 I40E_NONDMA_TO_NONDMA);
1155 status = I40E_ERR_INVALID_MAC_ADDR;
1161 * i40e_pre_tx_queue_cfg - pre tx queue configure
1162 * @hw: pointer to the HW structure
1163 * @queue: target pf queue index
1164 * @enable: state change request
1166 * Handles hw requirement to indicate intention to enable
1167 * or disable target queue.
1169 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1171 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1175 if (abs_queue_idx >= 128) {
1176 reg_block = abs_queue_idx / 128;
1177 abs_queue_idx %= 128;
1180 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1181 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1182 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1185 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1187 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1189 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1193 * i40e_get_san_mac_addr - get SAN MAC address
1194 * @hw: pointer to the HW structure
1195 * @mac_addr: pointer to SAN MAC address
1197 * Reads the adapter's SAN MAC address from NVM
1199 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1202 struct i40e_aqc_mac_address_read_data addrs;
1203 enum i40e_status_code status;
1206 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1210 if (flags & I40E_AQC_SAN_ADDR_VALID)
1211 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1212 I40E_NONDMA_TO_NONDMA);
1214 status = I40E_ERR_INVALID_MAC_ADDR;
1220 * i40e_read_pba_string - Reads part number string from EEPROM
1221 * @hw: pointer to hardware structure
1222 * @pba_num: stores the part number string from the EEPROM
1223 * @pba_num_size: part number string buffer length
1225 * Reads the part number string from the EEPROM.
1227 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1230 enum i40e_status_code status = I40E_SUCCESS;
1236 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1237 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1238 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1242 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1243 if (status != I40E_SUCCESS) {
1244 DEBUGOUT("Failed to read PBA Block pointer.\n");
1248 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1249 if (status != I40E_SUCCESS) {
1250 DEBUGOUT("Failed to read PBA Block size.\n");
1254 /* Subtract one to get PBA word count (PBA Size word is included in
1258 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1259 DEBUGOUT("Buffer to small for PBA data.\n");
1260 return I40E_ERR_PARAM;
1263 for (i = 0; i < pba_size; i++) {
1264 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1265 if (status != I40E_SUCCESS) {
1266 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1270 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1271 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1273 pba_num[(pba_size * 2)] = '\0';
1279 * i40e_get_media_type - Gets media type
1280 * @hw: pointer to the hardware structure
1282 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1284 enum i40e_media_type media;
1286 switch (hw->phy.link_info.phy_type) {
1287 case I40E_PHY_TYPE_10GBASE_SR:
1288 case I40E_PHY_TYPE_10GBASE_LR:
1289 case I40E_PHY_TYPE_1000BASE_SX:
1290 case I40E_PHY_TYPE_1000BASE_LX:
1291 case I40E_PHY_TYPE_40GBASE_SR4:
1292 case I40E_PHY_TYPE_40GBASE_LR4:
1293 case I40E_PHY_TYPE_25GBASE_LR:
1294 case I40E_PHY_TYPE_25GBASE_SR:
1295 media = I40E_MEDIA_TYPE_FIBER;
1297 case I40E_PHY_TYPE_100BASE_TX:
1298 case I40E_PHY_TYPE_1000BASE_T:
1299 case I40E_PHY_TYPE_10GBASE_T:
1300 media = I40E_MEDIA_TYPE_BASET;
1302 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1303 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1304 case I40E_PHY_TYPE_10GBASE_CR1:
1305 case I40E_PHY_TYPE_40GBASE_CR4:
1306 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1307 case I40E_PHY_TYPE_40GBASE_AOC:
1308 case I40E_PHY_TYPE_10GBASE_AOC:
1309 case I40E_PHY_TYPE_25GBASE_CR:
1310 media = I40E_MEDIA_TYPE_DA;
1312 case I40E_PHY_TYPE_1000BASE_KX:
1313 case I40E_PHY_TYPE_10GBASE_KX4:
1314 case I40E_PHY_TYPE_10GBASE_KR:
1315 case I40E_PHY_TYPE_40GBASE_KR4:
1316 case I40E_PHY_TYPE_20GBASE_KR2:
1317 case I40E_PHY_TYPE_25GBASE_KR:
1318 media = I40E_MEDIA_TYPE_BACKPLANE;
1320 case I40E_PHY_TYPE_SGMII:
1321 case I40E_PHY_TYPE_XAUI:
1322 case I40E_PHY_TYPE_XFI:
1323 case I40E_PHY_TYPE_XLAUI:
1324 case I40E_PHY_TYPE_XLPPI:
1326 media = I40E_MEDIA_TYPE_UNKNOWN;
1333 #define I40E_PF_RESET_WAIT_COUNT 200
1335 * i40e_pf_reset - Reset the PF
1336 * @hw: pointer to the hardware structure
1338 * Assuming someone else has triggered a global reset,
1339 * assure the global reset is complete and then reset the PF
1341 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1348 /* Poll for Global Reset steady state in case of recent GRST.
1349 * The grst delay value is in 100ms units, and we'll wait a
1350 * couple counts longer to be sure we don't just miss the end.
1352 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1353 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1354 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1356 grst_del = grst_del * 20;
1358 for (cnt = 0; cnt < grst_del; cnt++) {
1359 reg = rd32(hw, I40E_GLGEN_RSTAT);
1360 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1362 i40e_msec_delay(100);
1364 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1365 DEBUGOUT("Global reset polling failed to complete.\n");
1366 return I40E_ERR_RESET_FAILED;
1369 /* Now Wait for the FW to be ready */
1370 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1371 reg = rd32(hw, I40E_GLNVM_ULD);
1372 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1374 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1375 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1376 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1379 i40e_msec_delay(10);
1381 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1383 DEBUGOUT("wait for FW Reset complete timedout\n");
1384 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1385 return I40E_ERR_RESET_FAILED;
1388 /* If there was a Global Reset in progress when we got here,
1389 * we don't need to do the PF Reset
1392 reg = rd32(hw, I40E_PFGEN_CTRL);
1393 wr32(hw, I40E_PFGEN_CTRL,
1394 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1395 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1396 reg = rd32(hw, I40E_PFGEN_CTRL);
1397 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1401 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1402 DEBUGOUT("PF reset polling failed to complete.\n");
1403 return I40E_ERR_RESET_FAILED;
1407 i40e_clear_pxe_mode(hw);
1410 return I40E_SUCCESS;
1414 * i40e_clear_hw - clear out any left over hw state
1415 * @hw: pointer to the hw struct
1417 * Clear queues and interrupts, typically called at init time,
1418 * but after the capabilities have been found so we know how many
1419 * queues and msix vectors have been allocated.
1421 void i40e_clear_hw(struct i40e_hw *hw)
1423 u32 num_queues, base_queue;
1431 /* get number of interrupts, queues, and vfs */
1432 val = rd32(hw, I40E_GLPCI_CNF2);
1433 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1434 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1435 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1436 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1438 val = rd32(hw, I40E_PFLAN_QALLOC);
1439 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1440 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1441 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1442 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1443 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1444 num_queues = (j - base_queue) + 1;
1448 val = rd32(hw, I40E_PF_VT_PFALLOC);
1449 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1450 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1451 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1452 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1453 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1454 num_vfs = (j - i) + 1;
1458 /* stop all the interrupts */
1459 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1460 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1461 for (i = 0; i < num_pf_int - 2; i++)
1462 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1464 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1465 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1466 wr32(hw, I40E_PFINT_LNKLST0, val);
1467 for (i = 0; i < num_pf_int - 2; i++)
1468 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1469 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1470 for (i = 0; i < num_vfs; i++)
1471 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1472 for (i = 0; i < num_vf_int - 2; i++)
1473 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1475 /* warn the HW of the coming Tx disables */
1476 for (i = 0; i < num_queues; i++) {
1477 u32 abs_queue_idx = base_queue + i;
1480 if (abs_queue_idx >= 128) {
1481 reg_block = abs_queue_idx / 128;
1482 abs_queue_idx %= 128;
1485 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1486 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1487 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1488 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1490 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1492 i40e_usec_delay(400);
1494 /* stop all the queues */
1495 for (i = 0; i < num_queues; i++) {
1496 wr32(hw, I40E_QINT_TQCTL(i), 0);
1497 wr32(hw, I40E_QTX_ENA(i), 0);
1498 wr32(hw, I40E_QINT_RQCTL(i), 0);
1499 wr32(hw, I40E_QRX_ENA(i), 0);
1502 /* short wait for all queue disables to settle */
1503 i40e_usec_delay(50);
1507 * i40e_clear_pxe_mode - clear pxe operations mode
1508 * @hw: pointer to the hw struct
1510 * Make sure all PXE mode settings are cleared, including things
1511 * like descriptor fetch/write-back mode.
1513 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1515 if (i40e_check_asq_alive(hw))
1516 i40e_aq_clear_pxe_mode(hw, NULL);
1520 * i40e_led_is_mine - helper to find matching led
1521 * @hw: pointer to the hw struct
1522 * @idx: index into GPIO registers
1524 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1526 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1531 if (!hw->func_caps.led[idx])
1534 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1535 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1536 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1538 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1539 * if it is not our port then ignore
1541 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1548 #define I40E_COMBINED_ACTIVITY 0xA
1549 #define I40E_FILTER_ACTIVITY 0xE
1550 #define I40E_LINK_ACTIVITY 0xC
1551 #define I40E_MAC_ACTIVITY 0xD
1552 #define I40E_LED0 22
1555 * i40e_led_get - return current on/off mode
1556 * @hw: pointer to the hw struct
1558 * The value returned is the 'mode' field as defined in the
1559 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1560 * values are variations of possible behaviors relating to
1561 * blink, link, and wire.
1563 u32 i40e_led_get(struct i40e_hw *hw)
1565 u32 current_mode = 0;
1569 /* as per the documentation GPIO 22-29 are the LED
1570 * GPIO pins named LED0..LED7
1572 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1573 u32 gpio_val = i40e_led_is_mine(hw, i);
1578 /* ignore gpio LED src mode entries related to the activity
1581 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1582 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1583 switch (current_mode) {
1584 case I40E_COMBINED_ACTIVITY:
1585 case I40E_FILTER_ACTIVITY:
1586 case I40E_MAC_ACTIVITY:
1592 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1593 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1601 * i40e_led_set - set new on/off mode
1602 * @hw: pointer to the hw struct
1603 * @mode: 0=off, 0xf=on (else see manual for mode details)
1604 * @blink: true if the LED should blink when on, false if steady
1606 * if this function is used to turn on the blink it should
1607 * be used to disable the blink when restoring the original state.
1609 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1611 u32 current_mode = 0;
1614 if (mode & 0xfffffff0)
1615 DEBUGOUT1("invalid mode passed in %X\n", mode);
1617 /* as per the documentation GPIO 22-29 are the LED
1618 * GPIO pins named LED0..LED7
1620 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1621 u32 gpio_val = i40e_led_is_mine(hw, i);
1626 /* ignore gpio LED src mode entries related to the activity
1629 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1630 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1631 switch (current_mode) {
1632 case I40E_COMBINED_ACTIVITY:
1633 case I40E_FILTER_ACTIVITY:
1634 case I40E_MAC_ACTIVITY:
1640 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1641 /* this & is a bit of paranoia, but serves as a range check */
1642 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1643 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1645 if (mode == I40E_LINK_ACTIVITY)
1649 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1651 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1653 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1658 /* Admin command wrappers */
1661 * i40e_aq_get_phy_capabilities
1662 * @hw: pointer to the hw struct
1663 * @abilities: structure for PHY capabilities to be filled
1664 * @qualified_modules: report Qualified Modules
1665 * @report_init: report init capabilities (active are default)
1666 * @cmd_details: pointer to command details structure or NULL
1668 * Returns the various PHY abilities supported on the Port.
1670 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1671 bool qualified_modules, bool report_init,
1672 struct i40e_aq_get_phy_abilities_resp *abilities,
1673 struct i40e_asq_cmd_details *cmd_details)
1675 struct i40e_aq_desc desc;
1676 enum i40e_status_code status;
1677 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1680 return I40E_ERR_PARAM;
1682 i40e_fill_default_direct_cmd_desc(&desc,
1683 i40e_aqc_opc_get_phy_abilities);
1685 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1686 if (abilities_size > I40E_AQ_LARGE_BUF)
1687 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1689 if (qualified_modules)
1690 desc.params.external.param0 |=
1691 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1694 desc.params.external.param0 |=
1695 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1697 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1700 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1701 status = I40E_ERR_UNKNOWN_PHY;
1704 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1705 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1712 * i40e_aq_set_phy_config
1713 * @hw: pointer to the hw struct
1714 * @config: structure with PHY configuration to be set
1715 * @cmd_details: pointer to command details structure or NULL
1717 * Set the various PHY configuration parameters
1718 * supported on the Port.One or more of the Set PHY config parameters may be
1719 * ignored in an MFP mode as the PF may not have the privilege to set some
1720 * of the PHY Config parameters. This status will be indicated by the
1723 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1724 struct i40e_aq_set_phy_config *config,
1725 struct i40e_asq_cmd_details *cmd_details)
1727 struct i40e_aq_desc desc;
1728 struct i40e_aq_set_phy_config *cmd =
1729 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1730 enum i40e_status_code status;
1733 return I40E_ERR_PARAM;
1735 i40e_fill_default_direct_cmd_desc(&desc,
1736 i40e_aqc_opc_set_phy_config);
1740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1747 * @hw: pointer to the hw struct
1749 * Set the requested flow control mode using set_phy_config.
1751 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1752 bool atomic_restart)
1754 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1755 struct i40e_aq_get_phy_abilities_resp abilities;
1756 struct i40e_aq_set_phy_config config;
1757 enum i40e_status_code status;
1758 u8 pause_mask = 0x0;
1764 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1765 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1767 case I40E_FC_RX_PAUSE:
1768 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1770 case I40E_FC_TX_PAUSE:
1771 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1777 /* Get the current phy config */
1778 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1781 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1785 memset(&config, 0, sizeof(config));
1786 /* clear the old pause settings */
1787 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1788 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1789 /* set the new abilities */
1790 config.abilities |= pause_mask;
1791 /* If the abilities have changed, then set the new config */
1792 if (config.abilities != abilities.abilities) {
1793 /* Auto restart link so settings take effect */
1795 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1796 /* Copy over all the old settings */
1797 config.phy_type = abilities.phy_type;
1798 config.phy_type_ext = abilities.phy_type_ext;
1799 config.link_speed = abilities.link_speed;
1800 config.eee_capability = abilities.eee_capability;
1801 config.eeer = abilities.eeer_val;
1802 config.low_power_ctrl = abilities.d3_lpan;
1803 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1804 I40E_AQ_PHY_FEC_CONFIG_MASK;
1805 status = i40e_aq_set_phy_config(hw, &config, NULL);
1808 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1810 /* Update the link info */
1811 status = i40e_update_link_info(hw);
1813 /* Wait a little bit (on 40G cards it sometimes takes a really
1814 * long time for link to come back from the atomic reset)
1817 i40e_msec_delay(1000);
1818 status = i40e_update_link_info(hw);
1821 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1827 * i40e_aq_set_mac_config
1828 * @hw: pointer to the hw struct
1829 * @max_frame_size: Maximum Frame Size to be supported by the port
1830 * @crc_en: Tell HW to append a CRC to outgoing frames
1831 * @pacing: Pacing configurations
1832 * @cmd_details: pointer to command details structure or NULL
1834 * Configure MAC settings for frame size, jumbo frame support and the
1835 * addition of a CRC by the hardware.
1837 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1839 bool crc_en, u16 pacing,
1840 struct i40e_asq_cmd_details *cmd_details)
1842 struct i40e_aq_desc desc;
1843 struct i40e_aq_set_mac_config *cmd =
1844 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1845 enum i40e_status_code status;
1847 if (max_frame_size == 0)
1848 return I40E_ERR_PARAM;
1850 i40e_fill_default_direct_cmd_desc(&desc,
1851 i40e_aqc_opc_set_mac_config);
1853 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1854 cmd->params = ((u8)pacing & 0x0F) << 3;
1856 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1858 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1864 * i40e_aq_clear_pxe_mode
1865 * @hw: pointer to the hw struct
1866 * @cmd_details: pointer to command details structure or NULL
1868 * Tell the firmware that the driver is taking over from PXE
1870 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1871 struct i40e_asq_cmd_details *cmd_details)
1873 enum i40e_status_code status;
1874 struct i40e_aq_desc desc;
1875 struct i40e_aqc_clear_pxe *cmd =
1876 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1878 i40e_fill_default_direct_cmd_desc(&desc,
1879 i40e_aqc_opc_clear_pxe_mode);
1883 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1885 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1891 * i40e_aq_set_link_restart_an
1892 * @hw: pointer to the hw struct
1893 * @enable_link: if true: enable link, if false: disable link
1894 * @cmd_details: pointer to command details structure or NULL
1896 * Sets up the link and restarts the Auto-Negotiation over the link.
1898 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1899 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1901 struct i40e_aq_desc desc;
1902 struct i40e_aqc_set_link_restart_an *cmd =
1903 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1904 enum i40e_status_code status;
1906 i40e_fill_default_direct_cmd_desc(&desc,
1907 i40e_aqc_opc_set_link_restart_an);
1909 cmd->command = I40E_AQ_PHY_RESTART_AN;
1911 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1913 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1915 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1921 * i40e_aq_get_link_info
1922 * @hw: pointer to the hw struct
1923 * @enable_lse: enable/disable LinkStatusEvent reporting
1924 * @link: pointer to link status structure - optional
1925 * @cmd_details: pointer to command details structure or NULL
1927 * Returns the link status of the adapter.
1929 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1930 bool enable_lse, struct i40e_link_status *link,
1931 struct i40e_asq_cmd_details *cmd_details)
1933 struct i40e_aq_desc desc;
1934 struct i40e_aqc_get_link_status *resp =
1935 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1936 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1937 enum i40e_status_code status;
1938 bool tx_pause, rx_pause;
1941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1944 command_flags = I40E_AQ_LSE_ENABLE;
1946 command_flags = I40E_AQ_LSE_DISABLE;
1947 resp->command_flags = CPU_TO_LE16(command_flags);
1949 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1951 if (status != I40E_SUCCESS)
1952 goto aq_get_link_info_exit;
1954 /* save off old link status information */
1955 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1956 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1958 /* update link status */
1959 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1960 hw->phy.media_type = i40e_get_media_type(hw);
1961 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1962 hw_link_info->link_info = resp->link_info;
1963 hw_link_info->an_info = resp->an_info;
1964 hw_link_info->ext_info = resp->ext_info;
1965 hw_link_info->loopback = resp->loopback;
1966 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1967 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1969 /* update fc info */
1970 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1971 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1972 if (tx_pause & rx_pause)
1973 hw->fc.current_mode = I40E_FC_FULL;
1975 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1977 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1979 hw->fc.current_mode = I40E_FC_NONE;
1981 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1982 hw_link_info->crc_enable = true;
1984 hw_link_info->crc_enable = false;
1986 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1987 hw_link_info->lse_enable = true;
1989 hw_link_info->lse_enable = false;
1991 if ((hw->mac.type == I40E_MAC_XL710) &&
1992 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1993 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1994 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1996 /* save link status information */
1998 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1999 I40E_NONDMA_TO_NONDMA);
2001 /* flag cleared so helper functions don't call AQ again */
2002 hw->phy.get_link_info = false;
2004 aq_get_link_info_exit:
2009 * i40e_aq_set_phy_int_mask
2010 * @hw: pointer to the hw struct
2011 * @mask: interrupt mask to be set
2012 * @cmd_details: pointer to command details structure or NULL
2014 * Set link interrupt mask.
2016 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2018 struct i40e_asq_cmd_details *cmd_details)
2020 struct i40e_aq_desc desc;
2021 struct i40e_aqc_set_phy_int_mask *cmd =
2022 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2023 enum i40e_status_code status;
2025 i40e_fill_default_direct_cmd_desc(&desc,
2026 i40e_aqc_opc_set_phy_int_mask);
2028 cmd->event_mask = CPU_TO_LE16(mask);
2030 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2036 * i40e_aq_get_local_advt_reg
2037 * @hw: pointer to the hw struct
2038 * @advt_reg: local AN advertisement register value
2039 * @cmd_details: pointer to command details structure or NULL
2041 * Get the Local AN advertisement register value.
2043 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2045 struct i40e_asq_cmd_details *cmd_details)
2047 struct i40e_aq_desc desc;
2048 struct i40e_aqc_an_advt_reg *resp =
2049 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2050 enum i40e_status_code status;
2052 i40e_fill_default_direct_cmd_desc(&desc,
2053 i40e_aqc_opc_get_local_advt_reg);
2055 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2057 if (status != I40E_SUCCESS)
2058 goto aq_get_local_advt_reg_exit;
2060 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2061 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2063 aq_get_local_advt_reg_exit:
2068 * i40e_aq_set_local_advt_reg
2069 * @hw: pointer to the hw struct
2070 * @advt_reg: local AN advertisement register value
2071 * @cmd_details: pointer to command details structure or NULL
2073 * Get the Local AN advertisement register value.
2075 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2077 struct i40e_asq_cmd_details *cmd_details)
2079 struct i40e_aq_desc desc;
2080 struct i40e_aqc_an_advt_reg *cmd =
2081 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2082 enum i40e_status_code status;
2084 i40e_fill_default_direct_cmd_desc(&desc,
2085 i40e_aqc_opc_get_local_advt_reg);
2087 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2088 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2090 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2096 * i40e_aq_get_partner_advt
2097 * @hw: pointer to the hw struct
2098 * @advt_reg: AN partner advertisement register value
2099 * @cmd_details: pointer to command details structure or NULL
2101 * Get the link partner AN advertisement register value.
2103 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2105 struct i40e_asq_cmd_details *cmd_details)
2107 struct i40e_aq_desc desc;
2108 struct i40e_aqc_an_advt_reg *resp =
2109 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2110 enum i40e_status_code status;
2112 i40e_fill_default_direct_cmd_desc(&desc,
2113 i40e_aqc_opc_get_partner_advt);
2115 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2117 if (status != I40E_SUCCESS)
2118 goto aq_get_partner_advt_exit;
2120 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2121 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2123 aq_get_partner_advt_exit:
2128 * i40e_aq_set_lb_modes
2129 * @hw: pointer to the hw struct
2130 * @lb_modes: loopback mode to be set
2131 * @cmd_details: pointer to command details structure or NULL
2133 * Sets loopback modes.
2135 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2137 struct i40e_asq_cmd_details *cmd_details)
2139 struct i40e_aq_desc desc;
2140 struct i40e_aqc_set_lb_mode *cmd =
2141 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2142 enum i40e_status_code status;
2144 i40e_fill_default_direct_cmd_desc(&desc,
2145 i40e_aqc_opc_set_lb_modes);
2147 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2149 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2155 * i40e_aq_set_phy_debug
2156 * @hw: pointer to the hw struct
2157 * @cmd_flags: debug command flags
2158 * @cmd_details: pointer to command details structure or NULL
2160 * Reset the external PHY.
2162 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2163 struct i40e_asq_cmd_details *cmd_details)
2165 struct i40e_aq_desc desc;
2166 struct i40e_aqc_set_phy_debug *cmd =
2167 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2168 enum i40e_status_code status;
2170 i40e_fill_default_direct_cmd_desc(&desc,
2171 i40e_aqc_opc_set_phy_debug);
2173 cmd->command_flags = cmd_flags;
2175 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2182 * @hw: pointer to the hw struct
2183 * @vsi_ctx: pointer to a vsi context struct
2184 * @cmd_details: pointer to command details structure or NULL
2186 * Add a VSI context to the hardware.
2188 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2189 struct i40e_vsi_context *vsi_ctx,
2190 struct i40e_asq_cmd_details *cmd_details)
2192 struct i40e_aq_desc desc;
2193 struct i40e_aqc_add_get_update_vsi *cmd =
2194 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2195 struct i40e_aqc_add_get_update_vsi_completion *resp =
2196 (struct i40e_aqc_add_get_update_vsi_completion *)
2198 enum i40e_status_code status;
2200 i40e_fill_default_direct_cmd_desc(&desc,
2201 i40e_aqc_opc_add_vsi);
2203 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2204 cmd->connection_type = vsi_ctx->connection_type;
2205 cmd->vf_id = vsi_ctx->vf_num;
2206 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2208 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2210 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2211 sizeof(vsi_ctx->info), cmd_details);
2213 if (status != I40E_SUCCESS)
2214 goto aq_add_vsi_exit;
2216 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2217 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2218 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2219 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2226 * i40e_aq_set_default_vsi
2227 * @hw: pointer to the hw struct
2229 * @cmd_details: pointer to command details structure or NULL
2231 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2233 struct i40e_asq_cmd_details *cmd_details)
2235 struct i40e_aq_desc desc;
2236 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2237 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2239 enum i40e_status_code status;
2241 i40e_fill_default_direct_cmd_desc(&desc,
2242 i40e_aqc_opc_set_vsi_promiscuous_modes);
2244 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2245 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2246 cmd->seid = CPU_TO_LE16(seid);
2248 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2254 * i40e_aq_clear_default_vsi
2255 * @hw: pointer to the hw struct
2257 * @cmd_details: pointer to command details structure or NULL
2259 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2261 struct i40e_asq_cmd_details *cmd_details)
2263 struct i40e_aq_desc desc;
2264 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2265 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2267 enum i40e_status_code status;
2269 i40e_fill_default_direct_cmd_desc(&desc,
2270 i40e_aqc_opc_set_vsi_promiscuous_modes);
2272 cmd->promiscuous_flags = CPU_TO_LE16(0);
2273 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2274 cmd->seid = CPU_TO_LE16(seid);
2276 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2282 * i40e_aq_set_vsi_unicast_promiscuous
2283 * @hw: pointer to the hw struct
2285 * @set: set unicast promiscuous enable/disable
2286 * @cmd_details: pointer to command details structure or NULL
2287 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2289 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2291 struct i40e_asq_cmd_details *cmd_details,
2292 bool rx_only_promisc)
2294 struct i40e_aq_desc desc;
2295 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2296 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2297 enum i40e_status_code status;
2300 i40e_fill_default_direct_cmd_desc(&desc,
2301 i40e_aqc_opc_set_vsi_promiscuous_modes);
2304 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2305 if (rx_only_promisc &&
2306 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2307 (hw->aq.api_maj_ver > 1)))
2308 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2311 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2313 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2314 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2315 (hw->aq.api_maj_ver > 1))
2316 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2318 cmd->seid = CPU_TO_LE16(seid);
2319 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2325 * i40e_aq_set_vsi_multicast_promiscuous
2326 * @hw: pointer to the hw struct
2328 * @set: set multicast promiscuous enable/disable
2329 * @cmd_details: pointer to command details structure or NULL
2331 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2332 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2334 struct i40e_aq_desc desc;
2335 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2336 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2337 enum i40e_status_code status;
2340 i40e_fill_default_direct_cmd_desc(&desc,
2341 i40e_aqc_opc_set_vsi_promiscuous_modes);
2344 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2346 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2348 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2350 cmd->seid = CPU_TO_LE16(seid);
2351 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2357 * i40e_aq_set_vsi_mc_promisc_on_vlan
2358 * @hw: pointer to the hw struct
2360 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2361 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2362 * @cmd_details: pointer to command details structure or NULL
2364 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2365 u16 seid, bool enable, u16 vid,
2366 struct i40e_asq_cmd_details *cmd_details)
2368 struct i40e_aq_desc desc;
2369 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2370 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2371 enum i40e_status_code status;
2374 i40e_fill_default_direct_cmd_desc(&desc,
2375 i40e_aqc_opc_set_vsi_promiscuous_modes);
2378 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2380 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2381 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2382 cmd->seid = CPU_TO_LE16(seid);
2383 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2391 * i40e_aq_set_vsi_uc_promisc_on_vlan
2392 * @hw: pointer to the hw struct
2394 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2395 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2396 * @cmd_details: pointer to command details structure or NULL
2398 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2399 u16 seid, bool enable, u16 vid,
2400 struct i40e_asq_cmd_details *cmd_details)
2402 struct i40e_aq_desc desc;
2403 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2404 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2405 enum i40e_status_code status;
2408 i40e_fill_default_direct_cmd_desc(&desc,
2409 i40e_aqc_opc_set_vsi_promiscuous_modes);
2412 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2414 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2415 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2416 cmd->seid = CPU_TO_LE16(seid);
2417 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2419 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2425 * i40e_aq_set_vsi_broadcast
2426 * @hw: pointer to the hw struct
2428 * @set_filter: true to set filter, false to clear filter
2429 * @cmd_details: pointer to command details structure or NULL
2431 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2433 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2434 u16 seid, bool set_filter,
2435 struct i40e_asq_cmd_details *cmd_details)
2437 struct i40e_aq_desc desc;
2438 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2439 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2440 enum i40e_status_code status;
2442 i40e_fill_default_direct_cmd_desc(&desc,
2443 i40e_aqc_opc_set_vsi_promiscuous_modes);
2446 cmd->promiscuous_flags
2447 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2449 cmd->promiscuous_flags
2450 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2452 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2453 cmd->seid = CPU_TO_LE16(seid);
2454 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2460 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2461 * @hw: pointer to the hw struct
2463 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2464 * @cmd_details: pointer to command details structure or NULL
2466 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2467 u16 seid, bool enable,
2468 struct i40e_asq_cmd_details *cmd_details)
2470 struct i40e_aq_desc desc;
2471 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2472 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2473 enum i40e_status_code status;
2476 i40e_fill_default_direct_cmd_desc(&desc,
2477 i40e_aqc_opc_set_vsi_promiscuous_modes);
2479 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2481 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2482 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2483 cmd->seid = CPU_TO_LE16(seid);
2485 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2491 * i40e_get_vsi_params - get VSI configuration info
2492 * @hw: pointer to the hw struct
2493 * @vsi_ctx: pointer to a vsi context struct
2494 * @cmd_details: pointer to command details structure or NULL
2496 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2497 struct i40e_vsi_context *vsi_ctx,
2498 struct i40e_asq_cmd_details *cmd_details)
2500 struct i40e_aq_desc desc;
2501 struct i40e_aqc_add_get_update_vsi *cmd =
2502 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2503 struct i40e_aqc_add_get_update_vsi_completion *resp =
2504 (struct i40e_aqc_add_get_update_vsi_completion *)
2506 enum i40e_status_code status;
2508 UNREFERENCED_1PARAMETER(cmd_details);
2509 i40e_fill_default_direct_cmd_desc(&desc,
2510 i40e_aqc_opc_get_vsi_parameters);
2512 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2514 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2516 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2517 sizeof(vsi_ctx->info), NULL);
2519 if (status != I40E_SUCCESS)
2520 goto aq_get_vsi_params_exit;
2522 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2523 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2524 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2525 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2527 aq_get_vsi_params_exit:
2532 * i40e_aq_update_vsi_params
2533 * @hw: pointer to the hw struct
2534 * @vsi_ctx: pointer to a vsi context struct
2535 * @cmd_details: pointer to command details structure or NULL
2537 * Update a VSI context.
2539 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2540 struct i40e_vsi_context *vsi_ctx,
2541 struct i40e_asq_cmd_details *cmd_details)
2543 struct i40e_aq_desc desc;
2544 struct i40e_aqc_add_get_update_vsi *cmd =
2545 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2546 struct i40e_aqc_add_get_update_vsi_completion *resp =
2547 (struct i40e_aqc_add_get_update_vsi_completion *)
2549 enum i40e_status_code status;
2551 i40e_fill_default_direct_cmd_desc(&desc,
2552 i40e_aqc_opc_update_vsi_parameters);
2553 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2555 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2557 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2558 sizeof(vsi_ctx->info), cmd_details);
2560 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2561 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2567 * i40e_aq_get_switch_config
2568 * @hw: pointer to the hardware structure
2569 * @buf: pointer to the result buffer
2570 * @buf_size: length of input buffer
2571 * @start_seid: seid to start for the report, 0 == beginning
2572 * @cmd_details: pointer to command details structure or NULL
2574 * Fill the buf with switch configuration returned from AdminQ command
2576 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2577 struct i40e_aqc_get_switch_config_resp *buf,
2578 u16 buf_size, u16 *start_seid,
2579 struct i40e_asq_cmd_details *cmd_details)
2581 struct i40e_aq_desc desc;
2582 struct i40e_aqc_switch_seid *scfg =
2583 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2584 enum i40e_status_code status;
2586 i40e_fill_default_direct_cmd_desc(&desc,
2587 i40e_aqc_opc_get_switch_config);
2588 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2589 if (buf_size > I40E_AQ_LARGE_BUF)
2590 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2591 scfg->seid = CPU_TO_LE16(*start_seid);
2593 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2594 *start_seid = LE16_TO_CPU(scfg->seid);
2600 * i40e_aq_set_switch_config
2601 * @hw: pointer to the hardware structure
2602 * @flags: bit flag values to set
2603 * @valid_flags: which bit flags to set
2604 * @cmd_details: pointer to command details structure or NULL
2606 * Set switch configuration bits
2608 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2609 u16 flags, u16 valid_flags,
2610 struct i40e_asq_cmd_details *cmd_details)
2612 struct i40e_aq_desc desc;
2613 struct i40e_aqc_set_switch_config *scfg =
2614 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2615 enum i40e_status_code status;
2617 i40e_fill_default_direct_cmd_desc(&desc,
2618 i40e_aqc_opc_set_switch_config);
2619 scfg->flags = CPU_TO_LE16(flags);
2620 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2628 * i40e_aq_get_firmware_version
2629 * @hw: pointer to the hw struct
2630 * @fw_major_version: firmware major version
2631 * @fw_minor_version: firmware minor version
2632 * @fw_build: firmware build number
2633 * @api_major_version: major queue version
2634 * @api_minor_version: minor queue version
2635 * @cmd_details: pointer to command details structure or NULL
2637 * Get the firmware version from the admin queue commands
2639 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2640 u16 *fw_major_version, u16 *fw_minor_version,
2642 u16 *api_major_version, u16 *api_minor_version,
2643 struct i40e_asq_cmd_details *cmd_details)
2645 struct i40e_aq_desc desc;
2646 struct i40e_aqc_get_version *resp =
2647 (struct i40e_aqc_get_version *)&desc.params.raw;
2648 enum i40e_status_code status;
2650 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2652 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2654 if (status == I40E_SUCCESS) {
2655 if (fw_major_version != NULL)
2656 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2657 if (fw_minor_version != NULL)
2658 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2659 if (fw_build != NULL)
2660 *fw_build = LE32_TO_CPU(resp->fw_build);
2661 if (api_major_version != NULL)
2662 *api_major_version = LE16_TO_CPU(resp->api_major);
2663 if (api_minor_version != NULL)
2664 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2666 /* A workaround to fix the API version in SW */
2667 if (api_major_version && api_minor_version &&
2668 fw_major_version && fw_minor_version &&
2669 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2670 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2671 (*fw_major_version > 4)))
2672 *api_minor_version = 2;
2679 * i40e_aq_send_driver_version
2680 * @hw: pointer to the hw struct
2681 * @dv: driver's major, minor version
2682 * @cmd_details: pointer to command details structure or NULL
2684 * Send the driver version to the firmware
2686 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2687 struct i40e_driver_version *dv,
2688 struct i40e_asq_cmd_details *cmd_details)
2690 struct i40e_aq_desc desc;
2691 struct i40e_aqc_driver_version *cmd =
2692 (struct i40e_aqc_driver_version *)&desc.params.raw;
2693 enum i40e_status_code status;
2697 return I40E_ERR_PARAM;
2699 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2701 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2702 cmd->driver_major_ver = dv->major_version;
2703 cmd->driver_minor_ver = dv->minor_version;
2704 cmd->driver_build_ver = dv->build_version;
2705 cmd->driver_subbuild_ver = dv->subbuild_version;
2708 while (len < sizeof(dv->driver_string) &&
2709 (dv->driver_string[len] < 0x80) &&
2710 dv->driver_string[len])
2712 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2719 * i40e_get_link_status - get status of the HW network link
2720 * @hw: pointer to the hw struct
2721 * @link_up: pointer to bool (true/false = linkup/linkdown)
2723 * Variable link_up true if link is up, false if link is down.
2724 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2726 * Side effect: LinkStatusEvent reporting becomes enabled
2728 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2730 enum i40e_status_code status = I40E_SUCCESS;
2732 if (hw->phy.get_link_info) {
2733 status = i40e_update_link_info(hw);
2735 if (status != I40E_SUCCESS)
2736 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2740 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2746 * i40e_updatelink_status - update status of the HW network link
2747 * @hw: pointer to the hw struct
2749 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2751 struct i40e_aq_get_phy_abilities_resp abilities;
2752 enum i40e_status_code status = I40E_SUCCESS;
2754 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2758 /* extra checking needed to ensure link info to user is timely */
2759 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2760 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2761 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2762 status = i40e_aq_get_phy_capabilities(hw, false, false,
2767 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2768 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2775 * i40e_get_link_speed
2776 * @hw: pointer to the hw struct
2778 * Returns the link speed of the adapter.
2780 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2782 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2783 enum i40e_status_code status = I40E_SUCCESS;
2785 if (hw->phy.get_link_info) {
2786 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2788 if (status != I40E_SUCCESS)
2789 goto i40e_link_speed_exit;
2792 speed = hw->phy.link_info.link_speed;
2794 i40e_link_speed_exit:
2799 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2800 * @hw: pointer to the hw struct
2801 * @uplink_seid: the MAC or other gizmo SEID
2802 * @downlink_seid: the VSI SEID
2803 * @enabled_tc: bitmap of TCs to be enabled
2804 * @default_port: true for default port VSI, false for control port
2805 * @veb_seid: pointer to where to put the resulting VEB SEID
2806 * @enable_stats: true to turn on VEB stats
2807 * @cmd_details: pointer to command details structure or NULL
2809 * This asks the FW to add a VEB between the uplink and downlink
2810 * elements. If the uplink SEID is 0, this will be a floating VEB.
2812 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2813 u16 downlink_seid, u8 enabled_tc,
2814 bool default_port, u16 *veb_seid,
2816 struct i40e_asq_cmd_details *cmd_details)
2818 struct i40e_aq_desc desc;
2819 struct i40e_aqc_add_veb *cmd =
2820 (struct i40e_aqc_add_veb *)&desc.params.raw;
2821 struct i40e_aqc_add_veb_completion *resp =
2822 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2823 enum i40e_status_code status;
2826 /* SEIDs need to either both be set or both be 0 for floating VEB */
2827 if (!!uplink_seid != !!downlink_seid)
2828 return I40E_ERR_PARAM;
2830 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2832 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2833 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2834 cmd->enable_tcs = enabled_tc;
2836 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2838 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2840 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2842 /* reverse logic here: set the bitflag to disable the stats */
2844 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2846 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2848 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2850 if (!status && veb_seid)
2851 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2857 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2858 * @hw: pointer to the hw struct
2859 * @veb_seid: the SEID of the VEB to query
2860 * @switch_id: the uplink switch id
2861 * @floating: set to true if the VEB is floating
2862 * @statistic_index: index of the stats counter block for this VEB
2863 * @vebs_used: number of VEB's used by function
2864 * @vebs_free: total VEB's not reserved by any function
2865 * @cmd_details: pointer to command details structure or NULL
2867 * This retrieves the parameters for a particular VEB, specified by
2868 * uplink_seid, and returns them to the caller.
2870 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2871 u16 veb_seid, u16 *switch_id,
2872 bool *floating, u16 *statistic_index,
2873 u16 *vebs_used, u16 *vebs_free,
2874 struct i40e_asq_cmd_details *cmd_details)
2876 struct i40e_aq_desc desc;
2877 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2878 (struct i40e_aqc_get_veb_parameters_completion *)
2880 enum i40e_status_code status;
2883 return I40E_ERR_PARAM;
2885 i40e_fill_default_direct_cmd_desc(&desc,
2886 i40e_aqc_opc_get_veb_parameters);
2887 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2889 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2894 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2895 if (statistic_index)
2896 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2898 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2900 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2902 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2904 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2915 * i40e_aq_add_macvlan
2916 * @hw: pointer to the hw struct
2917 * @seid: VSI for the mac address
2918 * @mv_list: list of macvlans to be added
2919 * @count: length of the list
2920 * @cmd_details: pointer to command details structure or NULL
2922 * Add MAC/VLAN addresses to the HW filtering
2924 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2925 struct i40e_aqc_add_macvlan_element_data *mv_list,
2926 u16 count, struct i40e_asq_cmd_details *cmd_details)
2928 struct i40e_aq_desc desc;
2929 struct i40e_aqc_macvlan *cmd =
2930 (struct i40e_aqc_macvlan *)&desc.params.raw;
2931 enum i40e_status_code status;
2935 if (count == 0 || !mv_list || !hw)
2936 return I40E_ERR_PARAM;
2938 buf_size = count * sizeof(*mv_list);
2940 /* prep the rest of the request */
2941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2942 cmd->num_addresses = CPU_TO_LE16(count);
2943 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2947 for (i = 0; i < count; i++)
2948 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2950 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2952 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2953 if (buf_size > I40E_AQ_LARGE_BUF)
2954 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2956 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2963 * i40e_aq_remove_macvlan
2964 * @hw: pointer to the hw struct
2965 * @seid: VSI for the mac address
2966 * @mv_list: list of macvlans to be removed
2967 * @count: length of the list
2968 * @cmd_details: pointer to command details structure or NULL
2970 * Remove MAC/VLAN addresses from the HW filtering
2972 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2973 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2974 u16 count, struct i40e_asq_cmd_details *cmd_details)
2976 struct i40e_aq_desc desc;
2977 struct i40e_aqc_macvlan *cmd =
2978 (struct i40e_aqc_macvlan *)&desc.params.raw;
2979 enum i40e_status_code status;
2982 if (count == 0 || !mv_list || !hw)
2983 return I40E_ERR_PARAM;
2985 buf_size = count * sizeof(*mv_list);
2987 /* prep the rest of the request */
2988 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2989 cmd->num_addresses = CPU_TO_LE16(count);
2990 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2994 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2995 if (buf_size > I40E_AQ_LARGE_BUF)
2996 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2998 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3005 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3006 * @hw: pointer to the hw struct
3007 * @opcode: AQ opcode for add or delete mirror rule
3008 * @sw_seid: Switch SEID (to which rule refers)
3009 * @rule_type: Rule Type (ingress/egress/VLAN)
3010 * @id: Destination VSI SEID or Rule ID
3011 * @count: length of the list
3012 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3013 * @cmd_details: pointer to command details structure or NULL
3014 * @rule_id: Rule ID returned from FW
3015 * @rule_used: Number of rules used in internal switch
3016 * @rule_free: Number of rules free in internal switch
3018 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3019 * VEBs/VEPA elements only
3021 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3022 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3023 u16 count, __le16 *mr_list,
3024 struct i40e_asq_cmd_details *cmd_details,
3025 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3027 struct i40e_aq_desc desc;
3028 struct i40e_aqc_add_delete_mirror_rule *cmd =
3029 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3030 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3031 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3032 enum i40e_status_code status;
3035 buf_size = count * sizeof(*mr_list);
3037 /* prep the rest of the request */
3038 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3039 cmd->seid = CPU_TO_LE16(sw_seid);
3040 cmd->rule_type = CPU_TO_LE16(rule_type &
3041 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3042 cmd->num_entries = CPU_TO_LE16(count);
3043 /* Dest VSI for add, rule_id for delete */
3044 cmd->destination = CPU_TO_LE16(id);
3046 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3048 if (buf_size > I40E_AQ_LARGE_BUF)
3049 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3052 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3054 if (status == I40E_SUCCESS ||
3055 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3057 *rule_id = LE16_TO_CPU(resp->rule_id);
3059 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3061 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3067 * i40e_aq_add_mirrorrule - add a mirror rule
3068 * @hw: pointer to the hw struct
3069 * @sw_seid: Switch SEID (to which rule refers)
3070 * @rule_type: Rule Type (ingress/egress/VLAN)
3071 * @dest_vsi: SEID of VSI to which packets will be mirrored
3072 * @count: length of the list
3073 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3074 * @cmd_details: pointer to command details structure or NULL
3075 * @rule_id: Rule ID returned from FW
3076 * @rule_used: Number of rules used in internal switch
3077 * @rule_free: Number of rules free in internal switch
3079 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3081 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3082 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3083 struct i40e_asq_cmd_details *cmd_details,
3084 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3086 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3087 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3088 if (count == 0 || !mr_list)
3089 return I40E_ERR_PARAM;
3092 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3093 rule_type, dest_vsi, count, mr_list,
3094 cmd_details, rule_id, rules_used, rules_free);
3098 * i40e_aq_delete_mirrorrule - delete a mirror rule
3099 * @hw: pointer to the hw struct
3100 * @sw_seid: Switch SEID (to which rule refers)
3101 * @rule_type: Rule Type (ingress/egress/VLAN)
3102 * @count: length of the list
3103 * @rule_id: Rule ID that is returned in the receive desc as part of
3105 * @mr_list: list of mirrored VLAN IDs to be removed
3106 * @cmd_details: pointer to command details structure or NULL
3107 * @rule_used: Number of rules used in internal switch
3108 * @rule_free: Number of rules free in internal switch
3110 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3112 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3113 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3114 struct i40e_asq_cmd_details *cmd_details,
3115 u16 *rules_used, u16 *rules_free)
3117 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3118 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3119 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3120 * mirroring. For other rule_type, count and rule_type should
3123 if (count == 0 || !mr_list)
3124 return I40E_ERR_PARAM;
3127 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3128 rule_type, rule_id, count, mr_list,
3129 cmd_details, NULL, rules_used, rules_free);
3133 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3134 * @hw: pointer to the hw struct
3135 * @seid: VSI for the vlan filters
3136 * @v_list: list of vlan filters to be added
3137 * @count: length of the list
3138 * @cmd_details: pointer to command details structure or NULL
3140 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3141 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3142 u8 count, struct i40e_asq_cmd_details *cmd_details)
3144 struct i40e_aq_desc desc;
3145 struct i40e_aqc_macvlan *cmd =
3146 (struct i40e_aqc_macvlan *)&desc.params.raw;
3147 enum i40e_status_code status;
3150 if (count == 0 || !v_list || !hw)
3151 return I40E_ERR_PARAM;
3153 buf_size = count * sizeof(*v_list);
3155 /* prep the rest of the request */
3156 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3157 cmd->num_addresses = CPU_TO_LE16(count);
3158 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3162 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3163 if (buf_size > I40E_AQ_LARGE_BUF)
3164 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3166 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3173 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3174 * @hw: pointer to the hw struct
3175 * @seid: VSI for the vlan filters
3176 * @v_list: list of macvlans to be removed
3177 * @count: length of the list
3178 * @cmd_details: pointer to command details structure or NULL
3180 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3181 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3182 u8 count, struct i40e_asq_cmd_details *cmd_details)
3184 struct i40e_aq_desc desc;
3185 struct i40e_aqc_macvlan *cmd =
3186 (struct i40e_aqc_macvlan *)&desc.params.raw;
3187 enum i40e_status_code status;
3190 if (count == 0 || !v_list || !hw)
3191 return I40E_ERR_PARAM;
3193 buf_size = count * sizeof(*v_list);
3195 /* prep the rest of the request */
3196 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3197 cmd->num_addresses = CPU_TO_LE16(count);
3198 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3202 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3203 if (buf_size > I40E_AQ_LARGE_BUF)
3204 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3206 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3213 * i40e_aq_send_msg_to_vf
3214 * @hw: pointer to the hardware structure
3215 * @vfid: vf id to send msg
3216 * @v_opcode: opcodes for VF-PF communication
3217 * @v_retval: return error code
3218 * @msg: pointer to the msg buffer
3219 * @msglen: msg length
3220 * @cmd_details: pointer to command details
3224 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3225 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3226 struct i40e_asq_cmd_details *cmd_details)
3228 struct i40e_aq_desc desc;
3229 struct i40e_aqc_pf_vf_message *cmd =
3230 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3231 enum i40e_status_code status;
3233 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3234 cmd->id = CPU_TO_LE32(vfid);
3235 desc.cookie_high = CPU_TO_LE32(v_opcode);
3236 desc.cookie_low = CPU_TO_LE32(v_retval);
3237 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3239 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3241 if (msglen > I40E_AQ_LARGE_BUF)
3242 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3243 desc.datalen = CPU_TO_LE16(msglen);
3245 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3251 * i40e_aq_debug_read_register
3252 * @hw: pointer to the hw struct
3253 * @reg_addr: register address
3254 * @reg_val: register value
3255 * @cmd_details: pointer to command details structure or NULL
3257 * Read the register using the admin queue commands
3259 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3260 u32 reg_addr, u64 *reg_val,
3261 struct i40e_asq_cmd_details *cmd_details)
3263 struct i40e_aq_desc desc;
3264 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3265 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3266 enum i40e_status_code status;
3268 if (reg_val == NULL)
3269 return I40E_ERR_PARAM;
3271 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3273 cmd_resp->address = CPU_TO_LE32(reg_addr);
3275 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3277 if (status == I40E_SUCCESS) {
3278 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3279 (u64)LE32_TO_CPU(cmd_resp->value_low);
3286 * i40e_aq_debug_write_register
3287 * @hw: pointer to the hw struct
3288 * @reg_addr: register address
3289 * @reg_val: register value
3290 * @cmd_details: pointer to command details structure or NULL
3292 * Write to a register using the admin queue commands
3294 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3295 u32 reg_addr, u64 reg_val,
3296 struct i40e_asq_cmd_details *cmd_details)
3298 struct i40e_aq_desc desc;
3299 struct i40e_aqc_debug_reg_read_write *cmd =
3300 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3301 enum i40e_status_code status;
3303 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3305 cmd->address = CPU_TO_LE32(reg_addr);
3306 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3307 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3309 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3315 * i40e_aq_request_resource
3316 * @hw: pointer to the hw struct
3317 * @resource: resource id
3318 * @access: access type
3319 * @sdp_number: resource number
3320 * @timeout: the maximum time in ms that the driver may hold the resource
3321 * @cmd_details: pointer to command details structure or NULL
3323 * requests common resource using the admin queue commands
3325 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3326 enum i40e_aq_resources_ids resource,
3327 enum i40e_aq_resource_access_type access,
3328 u8 sdp_number, u64 *timeout,
3329 struct i40e_asq_cmd_details *cmd_details)
3331 struct i40e_aq_desc desc;
3332 struct i40e_aqc_request_resource *cmd_resp =
3333 (struct i40e_aqc_request_resource *)&desc.params.raw;
3334 enum i40e_status_code status;
3336 DEBUGFUNC("i40e_aq_request_resource");
3338 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3340 cmd_resp->resource_id = CPU_TO_LE16(resource);
3341 cmd_resp->access_type = CPU_TO_LE16(access);
3342 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3344 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3345 /* The completion specifies the maximum time in ms that the driver
3346 * may hold the resource in the Timeout field.
3347 * If the resource is held by someone else, the command completes with
3348 * busy return value and the timeout field indicates the maximum time
3349 * the current owner of the resource has to free it.
3351 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3352 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3358 * i40e_aq_release_resource
3359 * @hw: pointer to the hw struct
3360 * @resource: resource id
3361 * @sdp_number: resource number
3362 * @cmd_details: pointer to command details structure or NULL
3364 * release common resource using the admin queue commands
3366 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3367 enum i40e_aq_resources_ids resource,
3369 struct i40e_asq_cmd_details *cmd_details)
3371 struct i40e_aq_desc desc;
3372 struct i40e_aqc_request_resource *cmd =
3373 (struct i40e_aqc_request_resource *)&desc.params.raw;
3374 enum i40e_status_code status;
3376 DEBUGFUNC("i40e_aq_release_resource");
3378 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3380 cmd->resource_id = CPU_TO_LE16(resource);
3381 cmd->resource_number = CPU_TO_LE32(sdp_number);
3383 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3390 * @hw: pointer to the hw struct
3391 * @module_pointer: module pointer location in words from the NVM beginning
3392 * @offset: byte offset from the module beginning
3393 * @length: length of the section to be read (in bytes from the offset)
3394 * @data: command buffer (size [bytes] = length)
3395 * @last_command: tells if this is the last command in a series
3396 * @cmd_details: pointer to command details structure or NULL
3398 * Read the NVM using the admin queue commands
3400 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3401 u32 offset, u16 length, void *data,
3403 struct i40e_asq_cmd_details *cmd_details)
3405 struct i40e_aq_desc desc;
3406 struct i40e_aqc_nvm_update *cmd =
3407 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3408 enum i40e_status_code status;
3410 DEBUGFUNC("i40e_aq_read_nvm");
3412 /* In offset the highest byte must be zeroed. */
3413 if (offset & 0xFF000000) {
3414 status = I40E_ERR_PARAM;
3415 goto i40e_aq_read_nvm_exit;
3418 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3420 /* If this is the last command in a series, set the proper flag. */
3422 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3423 cmd->module_pointer = module_pointer;
3424 cmd->offset = CPU_TO_LE32(offset);
3425 cmd->length = CPU_TO_LE16(length);
3427 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3428 if (length > I40E_AQ_LARGE_BUF)
3429 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3431 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3433 i40e_aq_read_nvm_exit:
3438 * i40e_aq_read_nvm_config - read an nvm config block
3439 * @hw: pointer to the hw struct
3440 * @cmd_flags: NVM access admin command bits
3441 * @field_id: field or feature id
3442 * @data: buffer for result
3443 * @buf_size: buffer size
3444 * @element_count: pointer to count of elements read by FW
3445 * @cmd_details: pointer to command details structure or NULL
3447 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3448 u8 cmd_flags, u32 field_id, void *data,
3449 u16 buf_size, u16 *element_count,
3450 struct i40e_asq_cmd_details *cmd_details)
3452 struct i40e_aq_desc desc;
3453 struct i40e_aqc_nvm_config_read *cmd =
3454 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3455 enum i40e_status_code status;
3457 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3458 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3459 if (buf_size > I40E_AQ_LARGE_BUF)
3460 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3462 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3463 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3464 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3465 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3467 cmd->element_id_msw = 0;
3469 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3471 if (!status && element_count)
3472 *element_count = LE16_TO_CPU(cmd->element_count);
3478 * i40e_aq_write_nvm_config - write an nvm config block
3479 * @hw: pointer to the hw struct
3480 * @cmd_flags: NVM access admin command bits
3481 * @data: buffer for result
3482 * @buf_size: buffer size
3483 * @element_count: count of elements to be written
3484 * @cmd_details: pointer to command details structure or NULL
3486 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3487 u8 cmd_flags, void *data, u16 buf_size,
3489 struct i40e_asq_cmd_details *cmd_details)
3491 struct i40e_aq_desc desc;
3492 struct i40e_aqc_nvm_config_write *cmd =
3493 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3494 enum i40e_status_code status;
3496 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3497 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3498 if (buf_size > I40E_AQ_LARGE_BUF)
3499 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3501 cmd->element_count = CPU_TO_LE16(element_count);
3502 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3503 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3509 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3510 * @hw: pointer to the hw struct
3511 * @cmd_details: pointer to command details structure or NULL
3513 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3514 void *buff, u16 buff_size,
3515 struct i40e_asq_cmd_details *cmd_details)
3517 struct i40e_aq_desc desc;
3518 enum i40e_status_code status;
3520 UNREFERENCED_2PARAMETER(buff, buff_size);
3522 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3523 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3524 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3525 status = I40E_ERR_NOT_IMPLEMENTED;
3532 * @hw: pointer to the hw struct
3533 * @module_pointer: module pointer location in words from the NVM beginning
3534 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3535 * @length: length of the section to be erased (expressed in 4 KB)
3536 * @last_command: tells if this is the last command in a series
3537 * @cmd_details: pointer to command details structure or NULL
3539 * Erase the NVM sector using the admin queue commands
3541 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3542 u32 offset, u16 length, bool last_command,
3543 struct i40e_asq_cmd_details *cmd_details)
3545 struct i40e_aq_desc desc;
3546 struct i40e_aqc_nvm_update *cmd =
3547 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3548 enum i40e_status_code status;
3550 DEBUGFUNC("i40e_aq_erase_nvm");
3552 /* In offset the highest byte must be zeroed. */
3553 if (offset & 0xFF000000) {
3554 status = I40E_ERR_PARAM;
3555 goto i40e_aq_erase_nvm_exit;
3558 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3560 /* If this is the last command in a series, set the proper flag. */
3562 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3563 cmd->module_pointer = module_pointer;
3564 cmd->offset = CPU_TO_LE32(offset);
3565 cmd->length = CPU_TO_LE16(length);
3567 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3569 i40e_aq_erase_nvm_exit:
3574 * i40e_parse_discover_capabilities
3575 * @hw: pointer to the hw struct
3576 * @buff: pointer to a buffer containing device/function capability records
3577 * @cap_count: number of capability records in the list
3578 * @list_type_opc: type of capabilities list to parse
3580 * Parse the device/function capabilities list.
3582 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3584 enum i40e_admin_queue_opc list_type_opc)
3586 struct i40e_aqc_list_capabilities_element_resp *cap;
3587 u32 valid_functions, num_functions;
3588 u32 number, logical_id, phys_id;
3589 struct i40e_hw_capabilities *p;
3594 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3596 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3597 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3598 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3599 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3603 for (i = 0; i < cap_count; i++, cap++) {
3604 id = LE16_TO_CPU(cap->id);
3605 number = LE32_TO_CPU(cap->number);
3606 logical_id = LE32_TO_CPU(cap->logical_id);
3607 phys_id = LE32_TO_CPU(cap->phys_id);
3608 major_rev = cap->major_rev;
3611 case I40E_AQ_CAP_ID_SWITCH_MODE:
3612 p->switch_mode = number;
3613 i40e_debug(hw, I40E_DEBUG_INIT,
3614 "HW Capability: Switch mode = %d\n",
3617 case I40E_AQ_CAP_ID_MNG_MODE:
3618 p->management_mode = number;
3619 if (major_rev > 1) {
3620 p->mng_protocols_over_mctp = logical_id;
3621 i40e_debug(hw, I40E_DEBUG_INIT,
3622 "HW Capability: Protocols over MCTP = %d\n",
3623 p->mng_protocols_over_mctp);
3625 p->mng_protocols_over_mctp = 0;
3627 i40e_debug(hw, I40E_DEBUG_INIT,
3628 "HW Capability: Management Mode = %d\n",
3629 p->management_mode);
3631 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3632 p->npar_enable = number;
3633 i40e_debug(hw, I40E_DEBUG_INIT,
3634 "HW Capability: NPAR enable = %d\n",
3637 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3639 i40e_debug(hw, I40E_DEBUG_INIT,
3640 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3642 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3643 p->valid_functions = number;
3644 i40e_debug(hw, I40E_DEBUG_INIT,
3645 "HW Capability: Valid Functions = %d\n",
3646 p->valid_functions);
3648 case I40E_AQ_CAP_ID_SRIOV:
3650 p->sr_iov_1_1 = true;
3651 i40e_debug(hw, I40E_DEBUG_INIT,
3652 "HW Capability: SR-IOV = %d\n",
3655 case I40E_AQ_CAP_ID_VF:
3656 p->num_vfs = number;
3657 p->vf_base_id = logical_id;
3658 i40e_debug(hw, I40E_DEBUG_INIT,
3659 "HW Capability: VF count = %d\n",
3661 i40e_debug(hw, I40E_DEBUG_INIT,
3662 "HW Capability: VF base_id = %d\n",
3665 case I40E_AQ_CAP_ID_VMDQ:
3668 i40e_debug(hw, I40E_DEBUG_INIT,
3669 "HW Capability: VMDQ = %d\n", p->vmdq);
3671 case I40E_AQ_CAP_ID_8021QBG:
3673 p->evb_802_1_qbg = true;
3674 i40e_debug(hw, I40E_DEBUG_INIT,
3675 "HW Capability: 802.1Qbg = %d\n", number);
3677 case I40E_AQ_CAP_ID_8021QBR:
3679 p->evb_802_1_qbh = true;
3680 i40e_debug(hw, I40E_DEBUG_INIT,
3681 "HW Capability: 802.1Qbh = %d\n", number);
3683 case I40E_AQ_CAP_ID_VSI:
3684 p->num_vsis = number;
3685 i40e_debug(hw, I40E_DEBUG_INIT,
3686 "HW Capability: VSI count = %d\n",
3689 case I40E_AQ_CAP_ID_DCB:
3692 p->enabled_tcmap = logical_id;
3695 i40e_debug(hw, I40E_DEBUG_INIT,
3696 "HW Capability: DCB = %d\n", p->dcb);
3697 i40e_debug(hw, I40E_DEBUG_INIT,
3698 "HW Capability: TC Mapping = %d\n",
3700 i40e_debug(hw, I40E_DEBUG_INIT,
3701 "HW Capability: TC Max = %d\n", p->maxtc);
3703 case I40E_AQ_CAP_ID_FCOE:
3706 i40e_debug(hw, I40E_DEBUG_INIT,
3707 "HW Capability: FCOE = %d\n", p->fcoe);
3709 case I40E_AQ_CAP_ID_ISCSI:
3712 i40e_debug(hw, I40E_DEBUG_INIT,
3713 "HW Capability: iSCSI = %d\n", p->iscsi);
3715 case I40E_AQ_CAP_ID_RSS:
3717 p->rss_table_size = number;
3718 p->rss_table_entry_width = logical_id;
3719 i40e_debug(hw, I40E_DEBUG_INIT,
3720 "HW Capability: RSS = %d\n", p->rss);
3721 i40e_debug(hw, I40E_DEBUG_INIT,
3722 "HW Capability: RSS table size = %d\n",
3724 i40e_debug(hw, I40E_DEBUG_INIT,
3725 "HW Capability: RSS table width = %d\n",
3726 p->rss_table_entry_width);
3728 case I40E_AQ_CAP_ID_RXQ:
3729 p->num_rx_qp = number;
3730 p->base_queue = phys_id;
3731 i40e_debug(hw, I40E_DEBUG_INIT,
3732 "HW Capability: Rx QP = %d\n", number);
3733 i40e_debug(hw, I40E_DEBUG_INIT,
3734 "HW Capability: base_queue = %d\n",
3737 case I40E_AQ_CAP_ID_TXQ:
3738 p->num_tx_qp = number;
3739 p->base_queue = phys_id;
3740 i40e_debug(hw, I40E_DEBUG_INIT,
3741 "HW Capability: Tx QP = %d\n", number);
3742 i40e_debug(hw, I40E_DEBUG_INIT,
3743 "HW Capability: base_queue = %d\n",
3746 case I40E_AQ_CAP_ID_MSIX:
3747 p->num_msix_vectors = number;
3748 i40e_debug(hw, I40E_DEBUG_INIT,
3749 "HW Capability: MSIX vector count = %d\n",
3750 p->num_msix_vectors);
3752 case I40E_AQ_CAP_ID_VF_MSIX:
3753 p->num_msix_vectors_vf = number;
3754 i40e_debug(hw, I40E_DEBUG_INIT,
3755 "HW Capability: MSIX VF vector count = %d\n",
3756 p->num_msix_vectors_vf);
3758 case I40E_AQ_CAP_ID_FLEX10:
3759 if (major_rev == 1) {
3761 p->flex10_enable = true;
3762 p->flex10_capable = true;
3765 /* Capability revision >= 2 */
3767 p->flex10_enable = true;
3769 p->flex10_capable = true;
3771 p->flex10_mode = logical_id;
3772 p->flex10_status = phys_id;
3773 i40e_debug(hw, I40E_DEBUG_INIT,
3774 "HW Capability: Flex10 mode = %d\n",
3776 i40e_debug(hw, I40E_DEBUG_INIT,
3777 "HW Capability: Flex10 status = %d\n",
3780 case I40E_AQ_CAP_ID_CEM:
3783 i40e_debug(hw, I40E_DEBUG_INIT,
3784 "HW Capability: CEM = %d\n", p->mgmt_cem);
3786 case I40E_AQ_CAP_ID_IWARP:
3789 i40e_debug(hw, I40E_DEBUG_INIT,
3790 "HW Capability: iWARP = %d\n", p->iwarp);
3792 case I40E_AQ_CAP_ID_LED:
3793 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3794 p->led[phys_id] = true;
3795 i40e_debug(hw, I40E_DEBUG_INIT,
3796 "HW Capability: LED - PIN %d\n", phys_id);
3798 case I40E_AQ_CAP_ID_SDP:
3799 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3800 p->sdp[phys_id] = true;
3801 i40e_debug(hw, I40E_DEBUG_INIT,
3802 "HW Capability: SDP - PIN %d\n", phys_id);
3804 case I40E_AQ_CAP_ID_MDIO:
3806 p->mdio_port_num = phys_id;
3807 p->mdio_port_mode = logical_id;
3809 i40e_debug(hw, I40E_DEBUG_INIT,
3810 "HW Capability: MDIO port number = %d\n",
3812 i40e_debug(hw, I40E_DEBUG_INIT,
3813 "HW Capability: MDIO port mode = %d\n",
3816 case I40E_AQ_CAP_ID_1588:
3818 p->ieee_1588 = true;
3819 i40e_debug(hw, I40E_DEBUG_INIT,
3820 "HW Capability: IEEE 1588 = %d\n",
3823 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3825 p->fd_filters_guaranteed = number;
3826 p->fd_filters_best_effort = logical_id;
3827 i40e_debug(hw, I40E_DEBUG_INIT,
3828 "HW Capability: Flow Director = 1\n");
3829 i40e_debug(hw, I40E_DEBUG_INIT,
3830 "HW Capability: Guaranteed FD filters = %d\n",
3831 p->fd_filters_guaranteed);
3833 case I40E_AQ_CAP_ID_WSR_PROT:
3834 p->wr_csr_prot = (u64)number;
3835 p->wr_csr_prot |= (u64)logical_id << 32;
3836 i40e_debug(hw, I40E_DEBUG_INIT,
3837 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3838 (p->wr_csr_prot & 0xffff));
3840 case I40E_AQ_CAP_ID_NVM_MGMT:
3841 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3842 p->sec_rev_disabled = true;
3843 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3844 p->update_disabled = true;
3847 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3848 hw->num_wol_proxy_filters = (u16)number;
3849 hw->wol_proxy_vsi_seid = (u16)logical_id;
3850 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3851 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3852 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3854 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3855 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3856 i40e_debug(hw, I40E_DEBUG_INIT,
3857 "HW Capability: WOL proxy filters = %d\n",
3858 hw->num_wol_proxy_filters);
3867 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3869 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3872 /* count the enabled ports (aka the "not disabled" ports) */
3874 for (i = 0; i < 4; i++) {
3875 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3878 /* use AQ read to get the physical register offset instead
3879 * of the port relative offset
3881 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3882 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3886 valid_functions = p->valid_functions;
3888 while (valid_functions) {
3889 if (valid_functions & 1)
3891 valid_functions >>= 1;
3894 /* partition id is 1-based, and functions are evenly spread
3895 * across the ports as partitions
3897 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3898 hw->num_partitions = num_functions / hw->num_ports;
3900 /* additional HW specific goodies that might
3901 * someday be HW version specific
3903 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3907 * i40e_aq_discover_capabilities
3908 * @hw: pointer to the hw struct
3909 * @buff: a virtual buffer to hold the capabilities
3910 * @buff_size: Size of the virtual buffer
3911 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3912 * @list_type_opc: capabilities type to discover - pass in the command opcode
3913 * @cmd_details: pointer to command details structure or NULL
3915 * Get the device capabilities descriptions from the firmware
3917 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3918 void *buff, u16 buff_size, u16 *data_size,
3919 enum i40e_admin_queue_opc list_type_opc,
3920 struct i40e_asq_cmd_details *cmd_details)
3922 struct i40e_aqc_list_capabilites *cmd;
3923 struct i40e_aq_desc desc;
3924 enum i40e_status_code status = I40E_SUCCESS;
3926 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3928 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3929 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3930 status = I40E_ERR_PARAM;
3934 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3936 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3937 if (buff_size > I40E_AQ_LARGE_BUF)
3938 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3940 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3941 *data_size = LE16_TO_CPU(desc.datalen);
3946 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3954 * i40e_aq_update_nvm
3955 * @hw: pointer to the hw struct
3956 * @module_pointer: module pointer location in words from the NVM beginning
3957 * @offset: byte offset from the module beginning
3958 * @length: length of the section to be written (in bytes from the offset)
3959 * @data: command buffer (size [bytes] = length)
3960 * @last_command: tells if this is the last command in a series
3961 * @cmd_details: pointer to command details structure or NULL
3963 * Update the NVM using the admin queue commands
3965 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3966 u32 offset, u16 length, void *data,
3968 struct i40e_asq_cmd_details *cmd_details)
3970 struct i40e_aq_desc desc;
3971 struct i40e_aqc_nvm_update *cmd =
3972 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3973 enum i40e_status_code status;
3975 DEBUGFUNC("i40e_aq_update_nvm");
3977 /* In offset the highest byte must be zeroed. */
3978 if (offset & 0xFF000000) {
3979 status = I40E_ERR_PARAM;
3980 goto i40e_aq_update_nvm_exit;
3983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3985 /* If this is the last command in a series, set the proper flag. */
3987 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3988 cmd->module_pointer = module_pointer;
3989 cmd->offset = CPU_TO_LE32(offset);
3990 cmd->length = CPU_TO_LE16(length);
3992 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3993 if (length > I40E_AQ_LARGE_BUF)
3994 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3996 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3998 i40e_aq_update_nvm_exit:
4003 * i40e_aq_get_lldp_mib
4004 * @hw: pointer to the hw struct
4005 * @bridge_type: type of bridge requested
4006 * @mib_type: Local, Remote or both Local and Remote MIBs
4007 * @buff: pointer to a user supplied buffer to store the MIB block
4008 * @buff_size: size of the buffer (in bytes)
4009 * @local_len : length of the returned Local LLDP MIB
4010 * @remote_len: length of the returned Remote LLDP MIB
4011 * @cmd_details: pointer to command details structure or NULL
4013 * Requests the complete LLDP MIB (entire packet).
4015 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4016 u8 mib_type, void *buff, u16 buff_size,
4017 u16 *local_len, u16 *remote_len,
4018 struct i40e_asq_cmd_details *cmd_details)
4020 struct i40e_aq_desc desc;
4021 struct i40e_aqc_lldp_get_mib *cmd =
4022 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4023 struct i40e_aqc_lldp_get_mib *resp =
4024 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4025 enum i40e_status_code status;
4027 if (buff_size == 0 || !buff)
4028 return I40E_ERR_PARAM;
4030 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4031 /* Indirect Command */
4032 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4034 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4035 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4036 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4038 desc.datalen = CPU_TO_LE16(buff_size);
4040 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4041 if (buff_size > I40E_AQ_LARGE_BUF)
4042 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4044 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4046 if (local_len != NULL)
4047 *local_len = LE16_TO_CPU(resp->local_len);
4048 if (remote_len != NULL)
4049 *remote_len = LE16_TO_CPU(resp->remote_len);
4056 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4057 * @hw: pointer to the hw struct
4058 * @mib_type: Local, Remote or both Local and Remote MIBs
4059 * @buff: pointer to a user supplied buffer to store the MIB block
4060 * @buff_size: size of the buffer (in bytes)
4061 * @cmd_details: pointer to command details structure or NULL
4065 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4066 u8 mib_type, void *buff, u16 buff_size,
4067 struct i40e_asq_cmd_details *cmd_details)
4069 struct i40e_aq_desc desc;
4070 struct i40e_aqc_lldp_set_local_mib *cmd =
4071 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4072 enum i40e_status_code status;
4074 if (buff_size == 0 || !buff)
4075 return I40E_ERR_PARAM;
4077 i40e_fill_default_direct_cmd_desc(&desc,
4078 i40e_aqc_opc_lldp_set_local_mib);
4079 /* Indirect Command */
4080 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4081 if (buff_size > I40E_AQ_LARGE_BUF)
4082 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4083 desc.datalen = CPU_TO_LE16(buff_size);
4085 cmd->type = mib_type;
4086 cmd->length = CPU_TO_LE16(buff_size);
4087 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4088 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4090 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4095 * i40e_aq_cfg_lldp_mib_change_event
4096 * @hw: pointer to the hw struct
4097 * @enable_update: Enable or Disable event posting
4098 * @cmd_details: pointer to command details structure or NULL
4100 * Enable or Disable posting of an event on ARQ when LLDP MIB
4101 * associated with the interface changes
4103 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4105 struct i40e_asq_cmd_details *cmd_details)
4107 struct i40e_aq_desc desc;
4108 struct i40e_aqc_lldp_update_mib *cmd =
4109 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4110 enum i40e_status_code status;
4112 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4115 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4117 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4123 * i40e_aq_add_lldp_tlv
4124 * @hw: pointer to the hw struct
4125 * @bridge_type: type of bridge
4126 * @buff: buffer with TLV to add
4127 * @buff_size: length of the buffer
4128 * @tlv_len: length of the TLV to be added
4129 * @mib_len: length of the LLDP MIB returned in response
4130 * @cmd_details: pointer to command details structure or NULL
4132 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4133 * it is responsibility of the caller to make sure that the TLV is not
4134 * already present in the LLDPDU.
4135 * In return firmware will write the complete LLDP MIB with the newly
4136 * added TLV in the response buffer.
4138 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4139 void *buff, u16 buff_size, u16 tlv_len,
4141 struct i40e_asq_cmd_details *cmd_details)
4143 struct i40e_aq_desc desc;
4144 struct i40e_aqc_lldp_add_tlv *cmd =
4145 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4146 enum i40e_status_code status;
4148 if (buff_size == 0 || !buff || tlv_len == 0)
4149 return I40E_ERR_PARAM;
4151 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4153 /* Indirect Command */
4154 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4155 if (buff_size > I40E_AQ_LARGE_BUF)
4156 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4157 desc.datalen = CPU_TO_LE16(buff_size);
4159 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4160 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4161 cmd->len = CPU_TO_LE16(tlv_len);
4163 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4165 if (mib_len != NULL)
4166 *mib_len = LE16_TO_CPU(desc.datalen);
4173 * i40e_aq_update_lldp_tlv
4174 * @hw: pointer to the hw struct
4175 * @bridge_type: type of bridge
4176 * @buff: buffer with TLV to update
4177 * @buff_size: size of the buffer holding original and updated TLVs
4178 * @old_len: Length of the Original TLV
4179 * @new_len: Length of the Updated TLV
4180 * @offset: offset of the updated TLV in the buff
4181 * @mib_len: length of the returned LLDP MIB
4182 * @cmd_details: pointer to command details structure or NULL
4184 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4185 * Firmware will place the complete LLDP MIB in response buffer with the
4188 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4189 u8 bridge_type, void *buff, u16 buff_size,
4190 u16 old_len, u16 new_len, u16 offset,
4192 struct i40e_asq_cmd_details *cmd_details)
4194 struct i40e_aq_desc desc;
4195 struct i40e_aqc_lldp_update_tlv *cmd =
4196 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4197 enum i40e_status_code status;
4199 if (buff_size == 0 || !buff || offset == 0 ||
4200 old_len == 0 || new_len == 0)
4201 return I40E_ERR_PARAM;
4203 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4205 /* Indirect Command */
4206 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4207 if (buff_size > I40E_AQ_LARGE_BUF)
4208 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4209 desc.datalen = CPU_TO_LE16(buff_size);
4211 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4212 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4213 cmd->old_len = CPU_TO_LE16(old_len);
4214 cmd->new_offset = CPU_TO_LE16(offset);
4215 cmd->new_len = CPU_TO_LE16(new_len);
4217 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4219 if (mib_len != NULL)
4220 *mib_len = LE16_TO_CPU(desc.datalen);
4227 * i40e_aq_delete_lldp_tlv
4228 * @hw: pointer to the hw struct
4229 * @bridge_type: type of bridge
4230 * @buff: pointer to a user supplied buffer that has the TLV
4231 * @buff_size: length of the buffer
4232 * @tlv_len: length of the TLV to be deleted
4233 * @mib_len: length of the returned LLDP MIB
4234 * @cmd_details: pointer to command details structure or NULL
4236 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4237 * The firmware places the entire LLDP MIB in the response buffer.
4239 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4240 u8 bridge_type, void *buff, u16 buff_size,
4241 u16 tlv_len, u16 *mib_len,
4242 struct i40e_asq_cmd_details *cmd_details)
4244 struct i40e_aq_desc desc;
4245 struct i40e_aqc_lldp_add_tlv *cmd =
4246 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4247 enum i40e_status_code status;
4249 if (buff_size == 0 || !buff)
4250 return I40E_ERR_PARAM;
4252 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4254 /* Indirect Command */
4255 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4256 if (buff_size > I40E_AQ_LARGE_BUF)
4257 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4258 desc.datalen = CPU_TO_LE16(buff_size);
4259 cmd->len = CPU_TO_LE16(tlv_len);
4260 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4261 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4263 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4265 if (mib_len != NULL)
4266 *mib_len = LE16_TO_CPU(desc.datalen);
4274 * @hw: pointer to the hw struct
4275 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4276 * @cmd_details: pointer to command details structure or NULL
4278 * Stop or Shutdown the embedded LLDP Agent
4280 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4281 struct i40e_asq_cmd_details *cmd_details)
4283 struct i40e_aq_desc desc;
4284 struct i40e_aqc_lldp_stop *cmd =
4285 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4286 enum i40e_status_code status;
4288 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4291 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4293 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4299 * i40e_aq_start_lldp
4300 * @hw: pointer to the hw struct
4301 * @cmd_details: pointer to command details structure or NULL
4303 * Start the embedded LLDP Agent on all ports.
4305 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4306 struct i40e_asq_cmd_details *cmd_details)
4308 struct i40e_aq_desc desc;
4309 struct i40e_aqc_lldp_start *cmd =
4310 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4311 enum i40e_status_code status;
4313 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4315 cmd->command = I40E_AQ_LLDP_AGENT_START;
4317 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4323 * i40e_aq_get_cee_dcb_config
4324 * @hw: pointer to the hw struct
4325 * @buff: response buffer that stores CEE operational configuration
4326 * @buff_size: size of the buffer passed
4327 * @cmd_details: pointer to command details structure or NULL
4329 * Get CEE DCBX mode operational configuration from firmware
4331 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4332 void *buff, u16 buff_size,
4333 struct i40e_asq_cmd_details *cmd_details)
4335 struct i40e_aq_desc desc;
4336 enum i40e_status_code status;
4338 if (buff_size == 0 || !buff)
4339 return I40E_ERR_PARAM;
4341 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4343 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4344 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4351 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4352 * @hw: pointer to the hw struct
4353 * @start_agent: True if DCBx Agent needs to be Started
4354 * False if DCBx Agent needs to be Stopped
4355 * @cmd_details: pointer to command details structure or NULL
4357 * Start/Stop the embedded dcbx Agent
4359 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4361 struct i40e_asq_cmd_details *cmd_details)
4363 struct i40e_aq_desc desc;
4364 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4365 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4367 enum i40e_status_code status;
4369 i40e_fill_default_direct_cmd_desc(&desc,
4370 i40e_aqc_opc_lldp_stop_start_spec_agent);
4373 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4375 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4381 * i40e_aq_add_udp_tunnel
4382 * @hw: pointer to the hw struct
4383 * @udp_port: the UDP port to add
4384 * @header_len: length of the tunneling header length in DWords
4385 * @protocol_index: protocol index type
4386 * @filter_index: pointer to filter index
4387 * @cmd_details: pointer to command details structure or NULL
4389 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4390 u16 udp_port, u8 protocol_index,
4392 struct i40e_asq_cmd_details *cmd_details)
4394 struct i40e_aq_desc desc;
4395 struct i40e_aqc_add_udp_tunnel *cmd =
4396 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4397 struct i40e_aqc_del_udp_tunnel_completion *resp =
4398 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4399 enum i40e_status_code status;
4401 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4403 cmd->udp_port = CPU_TO_LE16(udp_port);
4404 cmd->protocol_type = protocol_index;
4406 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4408 if (!status && filter_index)
4409 *filter_index = resp->index;
4415 * i40e_aq_del_udp_tunnel
4416 * @hw: pointer to the hw struct
4417 * @index: filter index
4418 * @cmd_details: pointer to command details structure or NULL
4420 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4421 struct i40e_asq_cmd_details *cmd_details)
4423 struct i40e_aq_desc desc;
4424 struct i40e_aqc_remove_udp_tunnel *cmd =
4425 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4426 enum i40e_status_code status;
4428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4438 * i40e_aq_get_switch_resource_alloc (0x0204)
4439 * @hw: pointer to the hw struct
4440 * @num_entries: pointer to u8 to store the number of resource entries returned
4441 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4442 * to store the resource information for all resource types. Each
4443 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4444 * @count: size, in bytes, of the buffer provided
4445 * @cmd_details: pointer to command details structure or NULL
4447 * Query the resources allocated to a function.
4449 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4451 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4453 struct i40e_asq_cmd_details *cmd_details)
4455 struct i40e_aq_desc desc;
4456 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4457 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4458 enum i40e_status_code status;
4459 u16 length = count * sizeof(*buf);
4461 i40e_fill_default_direct_cmd_desc(&desc,
4462 i40e_aqc_opc_get_switch_resource_alloc);
4464 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4465 if (length > I40E_AQ_LARGE_BUF)
4466 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4468 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4470 if (!status && num_entries)
4471 *num_entries = cmd_resp->num_entries;
4477 * i40e_aq_delete_element - Delete switch element
4478 * @hw: pointer to the hw struct
4479 * @seid: the SEID to delete from the switch
4480 * @cmd_details: pointer to command details structure or NULL
4482 * This deletes a switch element from the switch.
4484 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4485 struct i40e_asq_cmd_details *cmd_details)
4487 struct i40e_aq_desc desc;
4488 struct i40e_aqc_switch_seid *cmd =
4489 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4490 enum i40e_status_code status;
4493 return I40E_ERR_PARAM;
4495 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4497 cmd->seid = CPU_TO_LE16(seid);
4499 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4505 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4506 * @hw: pointer to the hw struct
4507 * @flags: component flags
4508 * @mac_seid: uplink seid (MAC SEID)
4509 * @vsi_seid: connected vsi seid
4510 * @ret_seid: seid of create pv component
4512 * This instantiates an i40e port virtualizer with specified flags.
4513 * Depending on specified flags the port virtualizer can act as a
4514 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4516 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4517 u16 mac_seid, u16 vsi_seid,
4520 struct i40e_aq_desc desc;
4521 struct i40e_aqc_add_update_pv *cmd =
4522 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4523 struct i40e_aqc_add_update_pv_completion *resp =
4524 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4525 enum i40e_status_code status;
4528 return I40E_ERR_PARAM;
4530 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4531 cmd->command_flags = CPU_TO_LE16(flags);
4532 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4533 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4535 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4536 if (!status && ret_seid)
4537 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4543 * i40e_aq_add_tag - Add an S/E-tag
4544 * @hw: pointer to the hw struct
4545 * @direct_to_queue: should s-tag direct flow to a specific queue
4546 * @vsi_seid: VSI SEID to use this tag
4547 * @tag: value of the tag
4548 * @queue_num: queue number, only valid is direct_to_queue is true
4549 * @tags_used: return value, number of tags in use by this PF
4550 * @tags_free: return value, number of unallocated tags
4551 * @cmd_details: pointer to command details structure or NULL
4553 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4554 * the number of tags allocated by the PF, and the number of unallocated
4557 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4558 u16 vsi_seid, u16 tag, u16 queue_num,
4559 u16 *tags_used, u16 *tags_free,
4560 struct i40e_asq_cmd_details *cmd_details)
4562 struct i40e_aq_desc desc;
4563 struct i40e_aqc_add_tag *cmd =
4564 (struct i40e_aqc_add_tag *)&desc.params.raw;
4565 struct i40e_aqc_add_remove_tag_completion *resp =
4566 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4567 enum i40e_status_code status;
4570 return I40E_ERR_PARAM;
4572 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4574 cmd->seid = CPU_TO_LE16(vsi_seid);
4575 cmd->tag = CPU_TO_LE16(tag);
4576 if (direct_to_queue) {
4577 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4578 cmd->queue_number = CPU_TO_LE16(queue_num);
4581 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4584 if (tags_used != NULL)
4585 *tags_used = LE16_TO_CPU(resp->tags_used);
4586 if (tags_free != NULL)
4587 *tags_free = LE16_TO_CPU(resp->tags_free);
4594 * i40e_aq_remove_tag - Remove an S- or E-tag
4595 * @hw: pointer to the hw struct
4596 * @vsi_seid: VSI SEID this tag is associated with
4597 * @tag: value of the S-tag to delete
4598 * @tags_used: return value, number of tags in use by this PF
4599 * @tags_free: return value, number of unallocated tags
4600 * @cmd_details: pointer to command details structure or NULL
4602 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4603 * the number of tags allocated by the PF, and the number of unallocated
4606 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4607 u16 tag, u16 *tags_used, u16 *tags_free,
4608 struct i40e_asq_cmd_details *cmd_details)
4610 struct i40e_aq_desc desc;
4611 struct i40e_aqc_remove_tag *cmd =
4612 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4613 struct i40e_aqc_add_remove_tag_completion *resp =
4614 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4615 enum i40e_status_code status;
4618 return I40E_ERR_PARAM;
4620 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4622 cmd->seid = CPU_TO_LE16(vsi_seid);
4623 cmd->tag = CPU_TO_LE16(tag);
4625 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4628 if (tags_used != NULL)
4629 *tags_used = LE16_TO_CPU(resp->tags_used);
4630 if (tags_free != NULL)
4631 *tags_free = LE16_TO_CPU(resp->tags_free);
4638 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4639 * @hw: pointer to the hw struct
4640 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4641 * @etag: value of E-tag to add
4642 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4643 * @buf: address of indirect buffer
4644 * @tags_used: return value, number of E-tags in use by this port
4645 * @tags_free: return value, number of unallocated M-tags
4646 * @cmd_details: pointer to command details structure or NULL
4648 * This associates a multicast E-tag to a port virtualizer. It will return
4649 * the number of tags allocated by the PF, and the number of unallocated
4652 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4653 * num_tags_in_buf long.
4655 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4656 u16 etag, u8 num_tags_in_buf, void *buf,
4657 u16 *tags_used, u16 *tags_free,
4658 struct i40e_asq_cmd_details *cmd_details)
4660 struct i40e_aq_desc desc;
4661 struct i40e_aqc_add_remove_mcast_etag *cmd =
4662 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4663 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4664 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4665 enum i40e_status_code status;
4666 u16 length = sizeof(u16) * num_tags_in_buf;
4668 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4669 return I40E_ERR_PARAM;
4671 i40e_fill_default_direct_cmd_desc(&desc,
4672 i40e_aqc_opc_add_multicast_etag);
4674 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4675 cmd->etag = CPU_TO_LE16(etag);
4676 cmd->num_unicast_etags = num_tags_in_buf;
4678 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4679 if (length > I40E_AQ_LARGE_BUF)
4680 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4682 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4685 if (tags_used != NULL)
4686 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4687 if (tags_free != NULL)
4688 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4695 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4696 * @hw: pointer to the hw struct
4697 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4698 * @etag: value of the E-tag to remove
4699 * @tags_used: return value, number of tags in use by this port
4700 * @tags_free: return value, number of unallocated tags
4701 * @cmd_details: pointer to command details structure or NULL
4703 * This deletes an E-tag from the port virtualizer. It will return
4704 * the number of tags allocated by the port, and the number of unallocated
4707 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4708 u16 etag, u16 *tags_used, u16 *tags_free,
4709 struct i40e_asq_cmd_details *cmd_details)
4711 struct i40e_aq_desc desc;
4712 struct i40e_aqc_add_remove_mcast_etag *cmd =
4713 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4714 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4715 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4716 enum i40e_status_code status;
4720 return I40E_ERR_PARAM;
4722 i40e_fill_default_direct_cmd_desc(&desc,
4723 i40e_aqc_opc_remove_multicast_etag);
4725 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4726 cmd->etag = CPU_TO_LE16(etag);
4728 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4731 if (tags_used != NULL)
4732 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4733 if (tags_free != NULL)
4734 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4741 * i40e_aq_update_tag - Update an S/E-tag
4742 * @hw: pointer to the hw struct
4743 * @vsi_seid: VSI SEID using this S-tag
4744 * @old_tag: old tag value
4745 * @new_tag: new tag value
4746 * @tags_used: return value, number of tags in use by this PF
4747 * @tags_free: return value, number of unallocated tags
4748 * @cmd_details: pointer to command details structure or NULL
4750 * This updates the value of the tag currently attached to this VSI
4751 * in the switch complex. It will return the number of tags allocated
4752 * by the PF, and the number of unallocated tags available.
4754 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4755 u16 old_tag, u16 new_tag, u16 *tags_used,
4757 struct i40e_asq_cmd_details *cmd_details)
4759 struct i40e_aq_desc desc;
4760 struct i40e_aqc_update_tag *cmd =
4761 (struct i40e_aqc_update_tag *)&desc.params.raw;
4762 struct i40e_aqc_update_tag_completion *resp =
4763 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4764 enum i40e_status_code status;
4767 return I40E_ERR_PARAM;
4769 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4771 cmd->seid = CPU_TO_LE16(vsi_seid);
4772 cmd->old_tag = CPU_TO_LE16(old_tag);
4773 cmd->new_tag = CPU_TO_LE16(new_tag);
4775 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4778 if (tags_used != NULL)
4779 *tags_used = LE16_TO_CPU(resp->tags_used);
4780 if (tags_free != NULL)
4781 *tags_free = LE16_TO_CPU(resp->tags_free);
4788 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4789 * @hw: pointer to the hw struct
4790 * @tcmap: TC map for request/release any ignore PFC condition
4791 * @request: request or release ignore PFC condition
4792 * @tcmap_ret: return TCs for which PFC is currently ignored
4793 * @cmd_details: pointer to command details structure or NULL
4795 * This sends out request/release to ignore PFC condition for a TC.
4796 * It will return the TCs for which PFC is currently ignored.
4798 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4799 bool request, u8 *tcmap_ret,
4800 struct i40e_asq_cmd_details *cmd_details)
4802 struct i40e_aq_desc desc;
4803 struct i40e_aqc_pfc_ignore *cmd_resp =
4804 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4805 enum i40e_status_code status;
4807 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4810 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4812 cmd_resp->tc_bitmap = tcmap;
4814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4817 if (tcmap_ret != NULL)
4818 *tcmap_ret = cmd_resp->tc_bitmap;
4825 * i40e_aq_dcb_updated - DCB Updated Command
4826 * @hw: pointer to the hw struct
4827 * @cmd_details: pointer to command details structure or NULL
4829 * When LLDP is handled in PF this command is used by the PF
4830 * to notify EMP that a DCB setting is modified.
4831 * When LLDP is handled in EMP this command is used by the PF
4832 * to notify EMP whenever one of the following parameters get
4834 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4835 * - PCIRTT in PRTDCB_GENC.PCIRTT
4836 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4837 * EMP will return when the shared RPB settings have been
4838 * recomputed and modified. The retval field in the descriptor
4839 * will be set to 0 when RPB is modified.
4841 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4842 struct i40e_asq_cmd_details *cmd_details)
4844 struct i40e_aq_desc desc;
4845 enum i40e_status_code status;
4847 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4849 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4855 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4856 * @hw: pointer to the hw struct
4857 * @seid: defines the SEID of the switch for which the stats are requested
4858 * @vlan_id: the VLAN ID for which the statistics are requested
4859 * @stat_index: index of the statistics counters block assigned to this VLAN
4860 * @cmd_details: pointer to command details structure or NULL
4862 * XL710 supports 128 smonVlanStats counters.This command is used to
4863 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4866 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4867 u16 vlan_id, u16 *stat_index,
4868 struct i40e_asq_cmd_details *cmd_details)
4870 struct i40e_aq_desc desc;
4871 struct i40e_aqc_add_remove_statistics *cmd_resp =
4872 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4873 enum i40e_status_code status;
4875 if ((seid == 0) || (stat_index == NULL))
4876 return I40E_ERR_PARAM;
4878 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4880 cmd_resp->seid = CPU_TO_LE16(seid);
4881 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4883 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4885 if (!status && stat_index)
4886 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4892 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4893 * @hw: pointer to the hw struct
4894 * @seid: defines the SEID of the switch for which the stats are requested
4895 * @vlan_id: the VLAN ID for which the statistics are requested
4896 * @stat_index: index of the statistics counters block assigned to this VLAN
4897 * @cmd_details: pointer to command details structure or NULL
4899 * XL710 supports 128 smonVlanStats counters.This command is used to
4900 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4903 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4904 u16 vlan_id, u16 stat_index,
4905 struct i40e_asq_cmd_details *cmd_details)
4907 struct i40e_aq_desc desc;
4908 struct i40e_aqc_add_remove_statistics *cmd =
4909 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4910 enum i40e_status_code status;
4913 return I40E_ERR_PARAM;
4915 i40e_fill_default_direct_cmd_desc(&desc,
4916 i40e_aqc_opc_remove_statistics);
4918 cmd->seid = CPU_TO_LE16(seid);
4919 cmd->vlan = CPU_TO_LE16(vlan_id);
4920 cmd->stat_index = CPU_TO_LE16(stat_index);
4922 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4928 * i40e_aq_set_port_parameters - set physical port parameters.
4929 * @hw: pointer to the hw struct
4930 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4931 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4932 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4933 * @double_vlan: if set double VLAN is enabled
4934 * @cmd_details: pointer to command details structure or NULL
4936 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4937 u16 bad_frame_vsi, bool save_bad_pac,
4938 bool pad_short_pac, bool double_vlan,
4939 struct i40e_asq_cmd_details *cmd_details)
4941 struct i40e_aqc_set_port_parameters *cmd;
4942 enum i40e_status_code status;
4943 struct i40e_aq_desc desc;
4944 u16 command_flags = 0;
4946 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4948 i40e_fill_default_direct_cmd_desc(&desc,
4949 i40e_aqc_opc_set_port_parameters);
4951 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4953 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4955 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4957 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4958 cmd->command_flags = CPU_TO_LE16(command_flags);
4960 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4966 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4967 * @hw: pointer to the hw struct
4968 * @seid: seid for the physical port/switching component/vsi
4969 * @buff: Indirect buffer to hold data parameters and response
4970 * @buff_size: Indirect buffer size
4971 * @opcode: Tx scheduler AQ command opcode
4972 * @cmd_details: pointer to command details structure or NULL
4974 * Generic command handler for Tx scheduler AQ commands
4976 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4977 void *buff, u16 buff_size,
4978 enum i40e_admin_queue_opc opcode,
4979 struct i40e_asq_cmd_details *cmd_details)
4981 struct i40e_aq_desc desc;
4982 struct i40e_aqc_tx_sched_ind *cmd =
4983 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4984 enum i40e_status_code status;
4985 bool cmd_param_flag = false;
4988 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4989 case i40e_aqc_opc_configure_vsi_tc_bw:
4990 case i40e_aqc_opc_enable_switching_comp_ets:
4991 case i40e_aqc_opc_modify_switching_comp_ets:
4992 case i40e_aqc_opc_disable_switching_comp_ets:
4993 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4994 case i40e_aqc_opc_configure_switching_comp_bw_config:
4995 cmd_param_flag = true;
4997 case i40e_aqc_opc_query_vsi_bw_config:
4998 case i40e_aqc_opc_query_vsi_ets_sla_config:
4999 case i40e_aqc_opc_query_switching_comp_ets_config:
5000 case i40e_aqc_opc_query_port_ets_config:
5001 case i40e_aqc_opc_query_switching_comp_bw_config:
5002 cmd_param_flag = false;
5005 return I40E_ERR_PARAM;
5008 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5010 /* Indirect command */
5011 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5013 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5014 if (buff_size > I40E_AQ_LARGE_BUF)
5015 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5017 desc.datalen = CPU_TO_LE16(buff_size);
5019 cmd->vsi_seid = CPU_TO_LE16(seid);
5021 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5027 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5028 * @hw: pointer to the hw struct
5030 * @credit: BW limit credits (0 = disabled)
5031 * @max_credit: Max BW limit credits
5032 * @cmd_details: pointer to command details structure or NULL
5034 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5035 u16 seid, u16 credit, u8 max_credit,
5036 struct i40e_asq_cmd_details *cmd_details)
5038 struct i40e_aq_desc desc;
5039 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5040 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5041 enum i40e_status_code status;
5043 i40e_fill_default_direct_cmd_desc(&desc,
5044 i40e_aqc_opc_configure_vsi_bw_limit);
5046 cmd->vsi_seid = CPU_TO_LE16(seid);
5047 cmd->credit = CPU_TO_LE16(credit);
5048 cmd->max_credit = max_credit;
5050 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5056 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5057 * @hw: pointer to the hw struct
5058 * @seid: switching component seid
5059 * @credit: BW limit credits (0 = disabled)
5060 * @max_bw: Max BW limit credits
5061 * @cmd_details: pointer to command details structure or NULL
5063 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5064 u16 seid, u16 credit, u8 max_bw,
5065 struct i40e_asq_cmd_details *cmd_details)
5067 struct i40e_aq_desc desc;
5068 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5069 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5070 enum i40e_status_code status;
5072 i40e_fill_default_direct_cmd_desc(&desc,
5073 i40e_aqc_opc_configure_switching_comp_bw_limit);
5075 cmd->seid = CPU_TO_LE16(seid);
5076 cmd->credit = CPU_TO_LE16(credit);
5077 cmd->max_bw = max_bw;
5079 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5085 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5086 * @hw: pointer to the hw struct
5088 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5089 * @cmd_details: pointer to command details structure or NULL
5091 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5093 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5094 struct i40e_asq_cmd_details *cmd_details)
5096 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5097 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5102 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5103 * @hw: pointer to the hw struct
5105 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5106 * @cmd_details: pointer to command details structure or NULL
5108 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5110 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5111 struct i40e_asq_cmd_details *cmd_details)
5113 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5114 i40e_aqc_opc_configure_vsi_tc_bw,
5119 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5120 * @hw: pointer to the hw struct
5121 * @seid: seid of the switching component connected to Physical Port
5122 * @ets_data: Buffer holding ETS parameters
5123 * @cmd_details: pointer to command details structure or NULL
5125 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5127 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5128 enum i40e_admin_queue_opc opcode,
5129 struct i40e_asq_cmd_details *cmd_details)
5131 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5132 sizeof(*ets_data), opcode, cmd_details);
5136 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5137 * @hw: pointer to the hw struct
5138 * @seid: seid of the switching component
5139 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5140 * @cmd_details: pointer to command details structure or NULL
5142 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5144 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5145 struct i40e_asq_cmd_details *cmd_details)
5147 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5148 i40e_aqc_opc_configure_switching_comp_bw_config,
5153 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5154 * @hw: pointer to the hw struct
5155 * @seid: seid of the switching component
5156 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5157 * @cmd_details: pointer to command details structure or NULL
5159 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5160 struct i40e_hw *hw, u16 seid,
5161 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5162 struct i40e_asq_cmd_details *cmd_details)
5164 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5165 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5170 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5171 * @hw: pointer to the hw struct
5172 * @seid: seid of the VSI
5173 * @bw_data: Buffer to hold VSI BW configuration
5174 * @cmd_details: pointer to command details structure or NULL
5176 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5178 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5179 struct i40e_asq_cmd_details *cmd_details)
5181 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5182 i40e_aqc_opc_query_vsi_bw_config,
5187 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5188 * @hw: pointer to the hw struct
5189 * @seid: seid of the VSI
5190 * @bw_data: Buffer to hold VSI BW configuration per TC
5191 * @cmd_details: pointer to command details structure or NULL
5193 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5195 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5196 struct i40e_asq_cmd_details *cmd_details)
5198 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5199 i40e_aqc_opc_query_vsi_ets_sla_config,
5204 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5205 * @hw: pointer to the hw struct
5206 * @seid: seid of the switching component
5207 * @bw_data: Buffer to hold switching component's per TC BW config
5208 * @cmd_details: pointer to command details structure or NULL
5210 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5212 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5213 struct i40e_asq_cmd_details *cmd_details)
5215 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5216 i40e_aqc_opc_query_switching_comp_ets_config,
5221 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5222 * @hw: pointer to the hw struct
5223 * @seid: seid of the VSI or switching component connected to Physical Port
5224 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5225 * @cmd_details: pointer to command details structure or NULL
5227 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5229 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5230 struct i40e_asq_cmd_details *cmd_details)
5232 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5233 i40e_aqc_opc_query_port_ets_config,
5238 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5239 * @hw: pointer to the hw struct
5240 * @seid: seid of the switching component
5241 * @bw_data: Buffer to hold switching component's BW configuration
5242 * @cmd_details: pointer to command details structure or NULL
5244 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5246 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5247 struct i40e_asq_cmd_details *cmd_details)
5249 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5250 i40e_aqc_opc_query_switching_comp_bw_config,
5255 * i40e_validate_filter_settings
5256 * @hw: pointer to the hardware structure
5257 * @settings: Filter control settings
5259 * Check and validate the filter control settings passed.
5260 * The function checks for the valid filter/context sizes being
5261 * passed for FCoE and PE.
5263 * Returns I40E_SUCCESS if the values passed are valid and within
5264 * range else returns an error.
5266 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5267 struct i40e_filter_control_settings *settings)
5269 u32 fcoe_cntx_size, fcoe_filt_size;
5270 u32 pe_cntx_size, pe_filt_size;
5275 /* Validate FCoE settings passed */
5276 switch (settings->fcoe_filt_num) {
5277 case I40E_HASH_FILTER_SIZE_1K:
5278 case I40E_HASH_FILTER_SIZE_2K:
5279 case I40E_HASH_FILTER_SIZE_4K:
5280 case I40E_HASH_FILTER_SIZE_8K:
5281 case I40E_HASH_FILTER_SIZE_16K:
5282 case I40E_HASH_FILTER_SIZE_32K:
5283 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5284 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5287 return I40E_ERR_PARAM;
5290 switch (settings->fcoe_cntx_num) {
5291 case I40E_DMA_CNTX_SIZE_512:
5292 case I40E_DMA_CNTX_SIZE_1K:
5293 case I40E_DMA_CNTX_SIZE_2K:
5294 case I40E_DMA_CNTX_SIZE_4K:
5295 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5296 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5299 return I40E_ERR_PARAM;
5302 /* Validate PE settings passed */
5303 switch (settings->pe_filt_num) {
5304 case I40E_HASH_FILTER_SIZE_1K:
5305 case I40E_HASH_FILTER_SIZE_2K:
5306 case I40E_HASH_FILTER_SIZE_4K:
5307 case I40E_HASH_FILTER_SIZE_8K:
5308 case I40E_HASH_FILTER_SIZE_16K:
5309 case I40E_HASH_FILTER_SIZE_32K:
5310 case I40E_HASH_FILTER_SIZE_64K:
5311 case I40E_HASH_FILTER_SIZE_128K:
5312 case I40E_HASH_FILTER_SIZE_256K:
5313 case I40E_HASH_FILTER_SIZE_512K:
5314 case I40E_HASH_FILTER_SIZE_1M:
5315 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5316 pe_filt_size <<= (u32)settings->pe_filt_num;
5319 return I40E_ERR_PARAM;
5322 switch (settings->pe_cntx_num) {
5323 case I40E_DMA_CNTX_SIZE_512:
5324 case I40E_DMA_CNTX_SIZE_1K:
5325 case I40E_DMA_CNTX_SIZE_2K:
5326 case I40E_DMA_CNTX_SIZE_4K:
5327 case I40E_DMA_CNTX_SIZE_8K:
5328 case I40E_DMA_CNTX_SIZE_16K:
5329 case I40E_DMA_CNTX_SIZE_32K:
5330 case I40E_DMA_CNTX_SIZE_64K:
5331 case I40E_DMA_CNTX_SIZE_128K:
5332 case I40E_DMA_CNTX_SIZE_256K:
5333 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5334 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5337 return I40E_ERR_PARAM;
5340 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5341 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5342 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5343 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5344 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5345 return I40E_ERR_INVALID_SIZE;
5347 return I40E_SUCCESS;
5351 * i40e_set_filter_control
5352 * @hw: pointer to the hardware structure
5353 * @settings: Filter control settings
5355 * Set the Queue Filters for PE/FCoE and enable filters required
5356 * for a single PF. It is expected that these settings are programmed
5357 * at the driver initialization time.
5359 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5360 struct i40e_filter_control_settings *settings)
5362 enum i40e_status_code ret = I40E_SUCCESS;
5363 u32 hash_lut_size = 0;
5367 return I40E_ERR_PARAM;
5369 /* Validate the input settings */
5370 ret = i40e_validate_filter_settings(hw, settings);
5374 /* Read the PF Queue Filter control register */
5375 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5377 /* Program required PE hash buckets for the PF */
5378 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5379 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5380 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5381 /* Program required PE contexts for the PF */
5382 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5383 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5384 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5386 /* Program required FCoE hash buckets for the PF */
5387 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5388 val |= ((u32)settings->fcoe_filt_num <<
5389 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5390 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5391 /* Program required FCoE DDP contexts for the PF */
5392 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5393 val |= ((u32)settings->fcoe_cntx_num <<
5394 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5395 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5397 /* Program Hash LUT size for the PF */
5398 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5399 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5401 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5402 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5404 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5405 if (settings->enable_fdir)
5406 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5407 if (settings->enable_ethtype)
5408 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5409 if (settings->enable_macvlan)
5410 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5412 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5414 return I40E_SUCCESS;
5418 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5419 * @hw: pointer to the hw struct
5420 * @mac_addr: MAC address to use in the filter
5421 * @ethtype: Ethertype to use in the filter
5422 * @flags: Flags that needs to be applied to the filter
5423 * @vsi_seid: seid of the control VSI
5424 * @queue: VSI queue number to send the packet to
5425 * @is_add: Add control packet filter if True else remove
5426 * @stats: Structure to hold information on control filter counts
5427 * @cmd_details: pointer to command details structure or NULL
5429 * This command will Add or Remove control packet filter for a control VSI.
5430 * In return it will update the total number of perfect filter count in
5433 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5434 u8 *mac_addr, u16 ethtype, u16 flags,
5435 u16 vsi_seid, u16 queue, bool is_add,
5436 struct i40e_control_filter_stats *stats,
5437 struct i40e_asq_cmd_details *cmd_details)
5439 struct i40e_aq_desc desc;
5440 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5441 (struct i40e_aqc_add_remove_control_packet_filter *)
5443 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5444 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5446 enum i40e_status_code status;
5449 return I40E_ERR_PARAM;
5452 i40e_fill_default_direct_cmd_desc(&desc,
5453 i40e_aqc_opc_add_control_packet_filter);
5454 cmd->queue = CPU_TO_LE16(queue);
5456 i40e_fill_default_direct_cmd_desc(&desc,
5457 i40e_aqc_opc_remove_control_packet_filter);
5461 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5462 I40E_NONDMA_TO_NONDMA);
5464 cmd->etype = CPU_TO_LE16(ethtype);
5465 cmd->flags = CPU_TO_LE16(flags);
5466 cmd->seid = CPU_TO_LE16(vsi_seid);
5468 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5470 if (!status && stats) {
5471 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5472 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5473 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5474 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5481 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5482 * @hw: pointer to the hw struct
5483 * @seid: VSI seid to add ethertype filter from
5485 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5486 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5489 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5490 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5491 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5492 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5493 enum i40e_status_code status;
5495 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5496 seid, 0, true, NULL,
5499 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5503 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5504 * @filters: list of cloud filters
5505 * @filter_count: length of list
5507 * There's an issue in the device where the Geneve VNI layout needs
5508 * to be shifted 1 byte over from the VxLAN VNI
5510 STATIC void i40e_fix_up_geneve_vni(
5511 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5514 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5517 for (i = 0; i < filter_count; i++) {
5521 tnl_type = (LE16_TO_CPU(f[i].flags) &
5522 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5523 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5524 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5525 ti = LE32_TO_CPU(f[i].tenant_id);
5526 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5532 * i40e_aq_add_cloud_filters
5533 * @hw: pointer to the hardware structure
5534 * @seid: VSI seid to add cloud filters from
5535 * @filters: Buffer which contains the filters to be added
5536 * @filter_count: number of filters contained in the buffer
5538 * Set the cloud filters for a given VSI. The contents of the
5539 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5540 * in by the caller of the function.
5543 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5545 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5548 struct i40e_aq_desc desc;
5549 struct i40e_aqc_add_remove_cloud_filters *cmd =
5550 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5551 enum i40e_status_code status;
5554 i40e_fill_default_direct_cmd_desc(&desc,
5555 i40e_aqc_opc_add_cloud_filters);
5557 buff_len = filter_count * sizeof(*filters);
5558 desc.datalen = CPU_TO_LE16(buff_len);
5559 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5560 cmd->num_filters = filter_count;
5561 cmd->seid = CPU_TO_LE16(seid);
5563 i40e_fix_up_geneve_vni(filters, filter_count);
5565 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5571 * i40e_aq_remove_cloud_filters
5572 * @hw: pointer to the hardware structure
5573 * @seid: VSI seid to remove cloud filters from
5574 * @filters: Buffer which contains the filters to be removed
5575 * @filter_count: number of filters contained in the buffer
5577 * Remove the cloud filters for a given VSI. The contents of the
5578 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5579 * in by the caller of the function.
5582 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5584 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5587 struct i40e_aq_desc desc;
5588 struct i40e_aqc_add_remove_cloud_filters *cmd =
5589 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5590 enum i40e_status_code status;
5593 i40e_fill_default_direct_cmd_desc(&desc,
5594 i40e_aqc_opc_remove_cloud_filters);
5596 buff_len = filter_count * sizeof(*filters);
5597 desc.datalen = CPU_TO_LE16(buff_len);
5598 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5599 cmd->num_filters = filter_count;
5600 cmd->seid = CPU_TO_LE16(seid);
5602 i40e_fix_up_geneve_vni(filters, filter_count);
5604 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5610 * i40e_aq_alternate_write
5611 * @hw: pointer to the hardware structure
5612 * @reg_addr0: address of first dword to be read
5613 * @reg_val0: value to be written under 'reg_addr0'
5614 * @reg_addr1: address of second dword to be read
5615 * @reg_val1: value to be written under 'reg_addr1'
5617 * Write one or two dwords to alternate structure. Fields are indicated
5618 * by 'reg_addr0' and 'reg_addr1' register numbers.
5621 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5622 u32 reg_addr0, u32 reg_val0,
5623 u32 reg_addr1, u32 reg_val1)
5625 struct i40e_aq_desc desc;
5626 struct i40e_aqc_alternate_write *cmd_resp =
5627 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5628 enum i40e_status_code status;
5630 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5631 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5632 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5633 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5634 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5636 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5642 * i40e_aq_alternate_write_indirect
5643 * @hw: pointer to the hardware structure
5644 * @addr: address of a first register to be modified
5645 * @dw_count: number of alternate structure fields to write
5646 * @buffer: pointer to the command buffer
5648 * Write 'dw_count' dwords from 'buffer' to alternate structure
5649 * starting at 'addr'.
5652 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5653 u32 addr, u32 dw_count, void *buffer)
5655 struct i40e_aq_desc desc;
5656 struct i40e_aqc_alternate_ind_write *cmd_resp =
5657 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5658 enum i40e_status_code status;
5661 return I40E_ERR_PARAM;
5663 /* Indirect command */
5664 i40e_fill_default_direct_cmd_desc(&desc,
5665 i40e_aqc_opc_alternate_write_indirect);
5667 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5668 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5669 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5670 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5672 cmd_resp->address = CPU_TO_LE32(addr);
5673 cmd_resp->length = CPU_TO_LE32(dw_count);
5675 status = i40e_asq_send_command(hw, &desc, buffer,
5676 I40E_LO_DWORD(4*dw_count), NULL);
5682 * i40e_aq_alternate_read
5683 * @hw: pointer to the hardware structure
5684 * @reg_addr0: address of first dword to be read
5685 * @reg_val0: pointer for data read from 'reg_addr0'
5686 * @reg_addr1: address of second dword to be read
5687 * @reg_val1: pointer for data read from 'reg_addr1'
5689 * Read one or two dwords from alternate structure. Fields are indicated
5690 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5691 * is not passed then only register at 'reg_addr0' is read.
5694 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5695 u32 reg_addr0, u32 *reg_val0,
5696 u32 reg_addr1, u32 *reg_val1)
5698 struct i40e_aq_desc desc;
5699 struct i40e_aqc_alternate_write *cmd_resp =
5700 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5701 enum i40e_status_code status;
5703 if (reg_val0 == NULL)
5704 return I40E_ERR_PARAM;
5706 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5707 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5708 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5710 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5712 if (status == I40E_SUCCESS) {
5713 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5715 if (reg_val1 != NULL)
5716 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5723 * i40e_aq_alternate_read_indirect
5724 * @hw: pointer to the hardware structure
5725 * @addr: address of the alternate structure field
5726 * @dw_count: number of alternate structure fields to read
5727 * @buffer: pointer to the command buffer
5729 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5730 * place them in 'buffer'. The buffer should be allocated by caller.
5733 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5734 u32 addr, u32 dw_count, void *buffer)
5736 struct i40e_aq_desc desc;
5737 struct i40e_aqc_alternate_ind_write *cmd_resp =
5738 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5739 enum i40e_status_code status;
5742 return I40E_ERR_PARAM;
5744 /* Indirect command */
5745 i40e_fill_default_direct_cmd_desc(&desc,
5746 i40e_aqc_opc_alternate_read_indirect);
5748 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5749 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5750 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5751 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5753 cmd_resp->address = CPU_TO_LE32(addr);
5754 cmd_resp->length = CPU_TO_LE32(dw_count);
5756 status = i40e_asq_send_command(hw, &desc, buffer,
5757 I40E_LO_DWORD(4*dw_count), NULL);
5763 * i40e_aq_alternate_clear
5764 * @hw: pointer to the HW structure.
5766 * Clear the alternate structures of the port from which the function
5770 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5772 struct i40e_aq_desc desc;
5773 enum i40e_status_code status;
5775 i40e_fill_default_direct_cmd_desc(&desc,
5776 i40e_aqc_opc_alternate_clear_port);
5778 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5784 * i40e_aq_alternate_write_done
5785 * @hw: pointer to the HW structure.
5786 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5787 * @reset_needed: indicates the SW should trigger GLOBAL reset
5789 * Indicates to the FW that alternate structures have been changed.
5792 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5793 u8 bios_mode, bool *reset_needed)
5795 struct i40e_aq_desc desc;
5796 struct i40e_aqc_alternate_write_done *cmd =
5797 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5798 enum i40e_status_code status;
5800 if (reset_needed == NULL)
5801 return I40E_ERR_PARAM;
5803 i40e_fill_default_direct_cmd_desc(&desc,
5804 i40e_aqc_opc_alternate_write_done);
5806 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5808 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5809 if (!status && reset_needed)
5810 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5811 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5817 * i40e_aq_set_oem_mode
5818 * @hw: pointer to the HW structure.
5819 * @oem_mode: the OEM mode to be used
5821 * Sets the device to a specific operating mode. Currently the only supported
5822 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5825 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5828 struct i40e_aq_desc desc;
5829 struct i40e_aqc_alternate_write_done *cmd =
5830 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5831 enum i40e_status_code status;
5833 i40e_fill_default_direct_cmd_desc(&desc,
5834 i40e_aqc_opc_alternate_set_mode);
5836 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5838 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5844 * i40e_aq_resume_port_tx
5845 * @hw: pointer to the hardware structure
5846 * @cmd_details: pointer to command details structure or NULL
5848 * Resume port's Tx traffic
5850 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5851 struct i40e_asq_cmd_details *cmd_details)
5853 struct i40e_aq_desc desc;
5854 enum i40e_status_code status;
5856 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5858 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5864 * i40e_set_pci_config_data - store PCI bus info
5865 * @hw: pointer to hardware structure
5866 * @link_status: the link status word from PCI config space
5868 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5870 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5872 hw->bus.type = i40e_bus_type_pci_express;
5874 switch (link_status & I40E_PCI_LINK_WIDTH) {
5875 case I40E_PCI_LINK_WIDTH_1:
5876 hw->bus.width = i40e_bus_width_pcie_x1;
5878 case I40E_PCI_LINK_WIDTH_2:
5879 hw->bus.width = i40e_bus_width_pcie_x2;
5881 case I40E_PCI_LINK_WIDTH_4:
5882 hw->bus.width = i40e_bus_width_pcie_x4;
5884 case I40E_PCI_LINK_WIDTH_8:
5885 hw->bus.width = i40e_bus_width_pcie_x8;
5888 hw->bus.width = i40e_bus_width_unknown;
5892 switch (link_status & I40E_PCI_LINK_SPEED) {
5893 case I40E_PCI_LINK_SPEED_2500:
5894 hw->bus.speed = i40e_bus_speed_2500;
5896 case I40E_PCI_LINK_SPEED_5000:
5897 hw->bus.speed = i40e_bus_speed_5000;
5899 case I40E_PCI_LINK_SPEED_8000:
5900 hw->bus.speed = i40e_bus_speed_8000;
5903 hw->bus.speed = i40e_bus_speed_unknown;
5909 * i40e_aq_debug_dump
5910 * @hw: pointer to the hardware structure
5911 * @cluster_id: specific cluster to dump
5912 * @table_id: table id within cluster
5913 * @start_index: index of line in the block to read
5914 * @buff_size: dump buffer size
5915 * @buff: dump buffer
5916 * @ret_buff_size: actual buffer size returned
5917 * @ret_next_table: next block to read
5918 * @ret_next_index: next index to read
5920 * Dump internal FW/HW data for debug purposes.
5923 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5924 u8 table_id, u32 start_index, u16 buff_size,
5925 void *buff, u16 *ret_buff_size,
5926 u8 *ret_next_table, u32 *ret_next_index,
5927 struct i40e_asq_cmd_details *cmd_details)
5929 struct i40e_aq_desc desc;
5930 struct i40e_aqc_debug_dump_internals *cmd =
5931 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5932 struct i40e_aqc_debug_dump_internals *resp =
5933 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5934 enum i40e_status_code status;
5936 if (buff_size == 0 || !buff)
5937 return I40E_ERR_PARAM;
5939 i40e_fill_default_direct_cmd_desc(&desc,
5940 i40e_aqc_opc_debug_dump_internals);
5941 /* Indirect Command */
5942 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5943 if (buff_size > I40E_AQ_LARGE_BUF)
5944 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5946 cmd->cluster_id = cluster_id;
5947 cmd->table_id = table_id;
5948 cmd->idx = CPU_TO_LE32(start_index);
5950 desc.datalen = CPU_TO_LE16(buff_size);
5952 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5954 if (ret_buff_size != NULL)
5955 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5956 if (ret_next_table != NULL)
5957 *ret_next_table = resp->table_id;
5958 if (ret_next_index != NULL)
5959 *ret_next_index = LE32_TO_CPU(resp->idx);
5966 * i40e_read_bw_from_alt_ram
5967 * @hw: pointer to the hardware structure
5968 * @max_bw: pointer for max_bw read
5969 * @min_bw: pointer for min_bw read
5970 * @min_valid: pointer for bool that is true if min_bw is a valid value
5971 * @max_valid: pointer for bool that is true if max_bw is a valid value
5973 * Read bw from the alternate ram for the given pf
5975 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5976 u32 *max_bw, u32 *min_bw,
5977 bool *min_valid, bool *max_valid)
5979 enum i40e_status_code status;
5980 u32 max_bw_addr, min_bw_addr;
5982 /* Calculate the address of the min/max bw registers */
5983 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5984 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5985 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5986 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5987 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5988 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5990 /* Read the bandwidths from alt ram */
5991 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5992 min_bw_addr, min_bw);
5994 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5999 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6008 * i40e_aq_configure_partition_bw
6009 * @hw: pointer to the hardware structure
6010 * @bw_data: Buffer holding valid pfs and bw limits
6011 * @cmd_details: pointer to command details
6013 * Configure partitions guaranteed/max bw
6015 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6016 struct i40e_aqc_configure_partition_bw_data *bw_data,
6017 struct i40e_asq_cmd_details *cmd_details)
6019 enum i40e_status_code status;
6020 struct i40e_aq_desc desc;
6021 u16 bwd_size = sizeof(*bw_data);
6023 i40e_fill_default_direct_cmd_desc(&desc,
6024 i40e_aqc_opc_configure_partition_bw);
6026 /* Indirect command */
6027 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6028 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6030 desc.datalen = CPU_TO_LE16(bwd_size);
6032 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6038 * i40e_read_phy_register_clause22
6039 * @hw: pointer to the HW structure
6040 * @reg: register address in the page
6041 * @phy_adr: PHY address on MDIO interface
6042 * @value: PHY register value
6044 * Reads specified PHY register value
6046 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6047 u16 reg, u8 phy_addr, u16 *value)
6049 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6050 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6054 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6055 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6056 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6057 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6058 (I40E_GLGEN_MSCA_MDICMD_MASK);
6059 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6061 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6062 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6063 status = I40E_SUCCESS;
6066 i40e_usec_delay(10);
6071 i40e_debug(hw, I40E_DEBUG_PHY,
6072 "PHY: Can't write command to external PHY.\n");
6074 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6075 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6076 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6083 * i40e_write_phy_register_clause22
6084 * @hw: pointer to the HW structure
6085 * @reg: register address in the page
6086 * @phy_adr: PHY address on MDIO interface
6087 * @value: PHY register value
6089 * Writes specified PHY register value
6091 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6092 u16 reg, u8 phy_addr, u16 value)
6094 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6095 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6099 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6100 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6102 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6103 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6104 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6105 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6106 (I40E_GLGEN_MSCA_MDICMD_MASK);
6108 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6110 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6111 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6112 status = I40E_SUCCESS;
6115 i40e_usec_delay(10);
6123 * i40e_read_phy_register_clause45
6124 * @hw: pointer to the HW structure
6125 * @page: registers page number
6126 * @reg: register address in the page
6127 * @phy_adr: PHY address on MDIO interface
6128 * @value: PHY register value
6130 * Reads specified PHY register value
6132 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6133 u8 page, u16 reg, u8 phy_addr, u16 *value)
6135 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6138 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6140 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6141 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6142 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6143 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6144 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6145 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6146 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6147 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6149 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6150 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6151 status = I40E_SUCCESS;
6154 i40e_usec_delay(10);
6159 i40e_debug(hw, I40E_DEBUG_PHY,
6160 "PHY: Can't write command to external PHY.\n");
6164 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6165 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6166 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6167 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6168 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6169 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6170 status = I40E_ERR_TIMEOUT;
6172 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6174 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6175 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6176 status = I40E_SUCCESS;
6179 i40e_usec_delay(10);
6184 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6185 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6186 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6188 i40e_debug(hw, I40E_DEBUG_PHY,
6189 "PHY: Can't read register value from external PHY.\n");
6197 * i40e_write_phy_register_clause45
6198 * @hw: pointer to the HW structure
6199 * @page: registers page number
6200 * @reg: register address in the page
6201 * @phy_adr: PHY address on MDIO interface
6202 * @value: PHY register value
6204 * Writes value to specified PHY register
6206 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6207 u8 page, u16 reg, u8 phy_addr, u16 value)
6209 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6212 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6214 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6215 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6216 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6217 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6218 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6219 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6220 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6221 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6223 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6224 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6225 status = I40E_SUCCESS;
6228 i40e_usec_delay(10);
6232 i40e_debug(hw, I40E_DEBUG_PHY,
6233 "PHY: Can't write command to external PHY.\n");
6237 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6238 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6240 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6241 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6242 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6243 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6244 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6245 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6246 status = I40E_ERR_TIMEOUT;
6248 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6250 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6251 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6252 status = I40E_SUCCESS;
6255 i40e_usec_delay(10);
6264 * i40e_write_phy_register
6265 * @hw: pointer to the HW structure
6266 * @page: registers page number
6267 * @reg: register address in the page
6268 * @phy_adr: PHY address on MDIO interface
6269 * @value: PHY register value
6271 * Writes value to specified PHY register
6273 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6274 u8 page, u16 reg, u8 phy_addr, u16 value)
6276 enum i40e_status_code status;
6278 switch (hw->device_id) {
6279 case I40E_DEV_ID_1G_BASE_T_X722:
6280 status = i40e_write_phy_register_clause22(hw,
6281 reg, phy_addr, value);
6283 case I40E_DEV_ID_10G_BASE_T:
6284 case I40E_DEV_ID_10G_BASE_T4:
6285 case I40E_DEV_ID_10G_BASE_T_X722:
6286 case I40E_DEV_ID_25G_B:
6287 case I40E_DEV_ID_25G_SFP28:
6288 status = i40e_write_phy_register_clause45(hw,
6289 page, reg, phy_addr, value);
6292 status = I40E_ERR_UNKNOWN_PHY;
6300 * i40e_read_phy_register
6301 * @hw: pointer to the HW structure
6302 * @page: registers page number
6303 * @reg: register address in the page
6304 * @phy_adr: PHY address on MDIO interface
6305 * @value: PHY register value
6307 * Reads specified PHY register value
6309 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6310 u8 page, u16 reg, u8 phy_addr, u16 *value)
6312 enum i40e_status_code status;
6314 switch (hw->device_id) {
6315 case I40E_DEV_ID_1G_BASE_T_X722:
6316 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6319 case I40E_DEV_ID_10G_BASE_T:
6320 case I40E_DEV_ID_10G_BASE_T4:
6321 case I40E_DEV_ID_10G_BASE_T_X722:
6322 case I40E_DEV_ID_25G_B:
6323 case I40E_DEV_ID_25G_SFP28:
6324 status = i40e_read_phy_register_clause45(hw, page, reg,
6328 status = I40E_ERR_UNKNOWN_PHY;
6336 * i40e_get_phy_address
6337 * @hw: pointer to the HW structure
6338 * @dev_num: PHY port num that address we want
6339 * @phy_addr: Returned PHY address
6341 * Gets PHY address for current port
6343 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6345 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6346 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6348 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6352 * i40e_blink_phy_led
6353 * @hw: pointer to the HW structure
6354 * @time: time how long led will blinks in secs
6355 * @interval: gap between LED on and off in msecs
6357 * Blinks PHY link LED
6359 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6360 u32 time, u32 interval)
6362 enum i40e_status_code status = I40E_SUCCESS;
6367 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6371 i = rd32(hw, I40E_PFGEN_PORTNUM);
6372 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6373 phy_addr = i40e_get_phy_address(hw, port_num);
6375 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6377 status = i40e_read_phy_register_clause45(hw,
6378 I40E_PHY_COM_REG_PAGE,
6382 goto phy_blinking_end;
6384 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6386 status = i40e_write_phy_register_clause45(hw,
6387 I40E_PHY_COM_REG_PAGE,
6391 goto phy_blinking_end;
6396 if (time > 0 && interval > 0) {
6397 for (i = 0; i < time * 1000; i += interval) {
6398 status = i40e_read_phy_register_clause45(hw,
6399 I40E_PHY_COM_REG_PAGE,
6400 led_addr, phy_addr, &led_reg);
6402 goto restore_config;
6403 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6406 led_reg = I40E_PHY_LED_MANUAL_ON;
6407 status = i40e_write_phy_register_clause45(hw,
6408 I40E_PHY_COM_REG_PAGE,
6409 led_addr, phy_addr, led_reg);
6411 goto restore_config;
6412 i40e_msec_delay(interval);
6417 status = i40e_write_phy_register_clause45(hw,
6418 I40E_PHY_COM_REG_PAGE,
6419 led_addr, phy_addr, led_ctl);
6426 * i40e_led_get_phy - return current on/off mode
6427 * @hw: pointer to the hw struct
6428 * @led_addr: address of led register to use
6429 * @val: original value of register to use
6432 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6435 enum i40e_status_code status = I40E_SUCCESS;
6443 temp_addr = I40E_PHY_LED_PROV_REG_1;
6444 i = rd32(hw, I40E_PFGEN_PORTNUM);
6445 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6446 phy_addr = i40e_get_phy_address(hw, port_num);
6448 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6450 status = i40e_read_phy_register_clause45(hw,
6451 I40E_PHY_COM_REG_PAGE,
6452 temp_addr, phy_addr,
6457 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6458 *led_addr = temp_addr;
6467 * @hw: pointer to the HW structure
6468 * @on: true or false
6469 * @mode: original val plus bit for set or ignore
6470 * Set led's on or off when controlled by the PHY
6473 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6474 u16 led_addr, u32 mode)
6476 enum i40e_status_code status = I40E_SUCCESS;
6483 i = rd32(hw, I40E_PFGEN_PORTNUM);
6484 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6485 phy_addr = i40e_get_phy_address(hw, port_num);
6486 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6487 led_addr, phy_addr, &led_reg);
6491 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6493 status = i40e_write_phy_register_clause45(hw,
6494 I40E_PHY_COM_REG_PAGE,
6500 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6501 led_addr, phy_addr, &led_reg);
6503 goto restore_config;
6505 led_reg = I40E_PHY_LED_MANUAL_ON;
6508 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6509 led_addr, phy_addr, led_reg);
6511 goto restore_config;
6512 if (mode & I40E_PHY_LED_MODE_ORIG) {
6513 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6514 status = i40e_write_phy_register_clause45(hw,
6515 I40E_PHY_COM_REG_PAGE,
6516 led_addr, phy_addr, led_ctl);
6520 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6521 led_addr, phy_addr, led_ctl);
6524 #endif /* PF_DRIVER */
6527 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6528 * @hw: pointer to the hw struct
6529 * @reg_addr: register address
6530 * @reg_val: ptr to register value
6531 * @cmd_details: pointer to command details structure or NULL
6533 * Use the firmware to read the Rx control register,
6534 * especially useful if the Rx unit is under heavy pressure
6536 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6537 u32 reg_addr, u32 *reg_val,
6538 struct i40e_asq_cmd_details *cmd_details)
6540 struct i40e_aq_desc desc;
6541 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6542 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6543 enum i40e_status_code status;
6545 if (reg_val == NULL)
6546 return I40E_ERR_PARAM;
6548 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6550 cmd_resp->address = CPU_TO_LE32(reg_addr);
6552 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6554 if (status == I40E_SUCCESS)
6555 *reg_val = LE32_TO_CPU(cmd_resp->value);
6561 * i40e_read_rx_ctl - read from an Rx control register
6562 * @hw: pointer to the hw struct
6563 * @reg_addr: register address
6565 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6567 enum i40e_status_code status = I40E_SUCCESS;
6572 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6573 if (!use_register) {
6575 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6576 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6583 /* if the AQ access failed, try the old-fashioned way */
6584 if (status || use_register)
6585 val = rd32(hw, reg_addr);
6591 * i40e_aq_rx_ctl_write_register
6592 * @hw: pointer to the hw struct
6593 * @reg_addr: register address
6594 * @reg_val: register value
6595 * @cmd_details: pointer to command details structure or NULL
6597 * Use the firmware to write to an Rx control register,
6598 * especially useful if the Rx unit is under heavy pressure
6600 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6601 u32 reg_addr, u32 reg_val,
6602 struct i40e_asq_cmd_details *cmd_details)
6604 struct i40e_aq_desc desc;
6605 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6606 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6607 enum i40e_status_code status;
6609 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6611 cmd->address = CPU_TO_LE32(reg_addr);
6612 cmd->value = CPU_TO_LE32(reg_val);
6614 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6620 * i40e_write_rx_ctl - write to an Rx control register
6621 * @hw: pointer to the hw struct
6622 * @reg_addr: register address
6623 * @reg_val: register value
6625 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6627 enum i40e_status_code status = I40E_SUCCESS;
6631 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6632 if (!use_register) {
6634 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6636 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6643 /* if the AQ access failed, try the old-fashioned way */
6644 if (status || use_register)
6645 wr32(hw, reg_addr, reg_val);
6650 * i40e_aq_send_msg_to_pf
6651 * @hw: pointer to the hardware structure
6652 * @v_opcode: opcodes for VF-PF communication
6653 * @v_retval: return error code
6654 * @msg: pointer to the msg buffer
6655 * @msglen: msg length
6656 * @cmd_details: pointer to command details
6658 * Send message to PF driver using admin queue. By default, this message
6659 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6660 * completion before returning.
6662 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6663 enum i40e_virtchnl_ops v_opcode,
6664 enum i40e_status_code v_retval,
6665 u8 *msg, u16 msglen,
6666 struct i40e_asq_cmd_details *cmd_details)
6668 struct i40e_aq_desc desc;
6669 struct i40e_asq_cmd_details details;
6670 enum i40e_status_code status;
6672 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6673 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6674 desc.cookie_high = CPU_TO_LE32(v_opcode);
6675 desc.cookie_low = CPU_TO_LE32(v_retval);
6677 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6678 | I40E_AQ_FLAG_RD));
6679 if (msglen > I40E_AQ_LARGE_BUF)
6680 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6681 desc.datalen = CPU_TO_LE16(msglen);
6684 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6685 details.async = true;
6686 cmd_details = &details;
6688 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6689 msglen, cmd_details);
6694 * i40e_vf_parse_hw_config
6695 * @hw: pointer to the hardware structure
6696 * @msg: pointer to the virtual channel VF resource structure
6698 * Given a VF resource message from the PF, populate the hw struct
6699 * with appropriate information.
6701 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6702 struct i40e_virtchnl_vf_resource *msg)
6704 struct i40e_virtchnl_vsi_resource *vsi_res;
6707 vsi_res = &msg->vsi_res[0];
6709 hw->dev_caps.num_vsis = msg->num_vsis;
6710 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6711 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6712 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6713 hw->dev_caps.dcb = msg->vf_offload_flags &
6714 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6715 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6716 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6717 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6718 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6719 for (i = 0; i < msg->num_vsis; i++) {
6720 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6721 i40e_memcpy(hw->mac.perm_addr,
6722 vsi_res->default_mac_addr,
6723 I40E_ETH_LENGTH_OF_ADDRESS,
6724 I40E_NONDMA_TO_NONDMA);
6725 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6726 I40E_ETH_LENGTH_OF_ADDRESS,
6727 I40E_NONDMA_TO_NONDMA);
6735 * @hw: pointer to the hardware structure
6737 * Send a VF_RESET message to the PF. Does not wait for response from PF
6738 * as none will be forthcoming. Immediately after calling this function,
6739 * the admin queue should be shut down and (optionally) reinitialized.
6741 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6743 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6744 I40E_SUCCESS, NULL, 0, NULL);
6746 #endif /* VF_DRIVER */
6750 * i40e_aq_set_arp_proxy_config
6751 * @hw: pointer to the HW structure
6752 * @proxy_config - pointer to proxy config command table struct
6753 * @cmd_details: pointer to command details
6755 * Set ARP offload parameters from pre-populated
6756 * i40e_aqc_arp_proxy_data struct
6758 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6759 struct i40e_aqc_arp_proxy_data *proxy_config,
6760 struct i40e_asq_cmd_details *cmd_details)
6762 struct i40e_aq_desc desc;
6763 enum i40e_status_code status;
6766 return I40E_ERR_PARAM;
6768 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6770 desc.params.external.addr_high =
6771 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6772 desc.params.external.addr_low =
6773 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6775 status = i40e_asq_send_command(hw, &desc, proxy_config,
6776 sizeof(struct i40e_aqc_arp_proxy_data),
6783 * i40e_aq_opc_set_ns_proxy_table_entry
6784 * @hw: pointer to the HW structure
6785 * @ns_proxy_table_entry: pointer to NS table entry command struct
6786 * @cmd_details: pointer to command details
6788 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6789 * from pre-populated i40e_aqc_ns_proxy_data struct
6791 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6792 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6793 struct i40e_asq_cmd_details *cmd_details)
6795 struct i40e_aq_desc desc;
6796 enum i40e_status_code status;
6798 if (!ns_proxy_table_entry)
6799 return I40E_ERR_PARAM;
6801 i40e_fill_default_direct_cmd_desc(&desc,
6802 i40e_aqc_opc_set_ns_proxy_table_entry);
6804 desc.params.external.addr_high =
6805 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6806 desc.params.external.addr_low =
6807 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6809 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6810 sizeof(struct i40e_aqc_ns_proxy_data),
6817 * i40e_aq_set_clear_wol_filter
6818 * @hw: pointer to the hw struct
6819 * @filter_index: index of filter to modify (0-7)
6820 * @filter: buffer containing filter to be set
6821 * @set_filter: true to set filter, false to clear filter
6822 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6823 * if false, pass through packets may cause wake-up
6824 * @filter_valid: true if filter action is valid
6825 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6826 * @cmd_details: pointer to command details structure or NULL
6828 * Set or clear WoL filter for port attached to the PF
6830 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6832 struct i40e_aqc_set_wol_filter_data *filter,
6833 bool set_filter, bool no_wol_tco,
6834 bool filter_valid, bool no_wol_tco_valid,
6835 struct i40e_asq_cmd_details *cmd_details)
6837 struct i40e_aq_desc desc;
6838 struct i40e_aqc_set_wol_filter *cmd =
6839 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6840 enum i40e_status_code status;
6842 u16 valid_flags = 0;
6845 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6847 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6848 return I40E_ERR_PARAM;
6849 cmd->filter_index = CPU_TO_LE16(filter_index);
6853 return I40E_ERR_PARAM;
6854 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6855 buff_len = sizeof(*filter);
6858 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6859 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6862 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6863 if (no_wol_tco_valid)
6864 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6865 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6867 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6868 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6870 status = i40e_asq_send_command(hw, &desc, filter,
6871 buff_len, cmd_details);
6877 * i40e_aq_get_wake_event_reason
6878 * @hw: pointer to the hw struct
6879 * @wake_reason: return value, index of matching filter
6880 * @cmd_details: pointer to command details structure or NULL
6882 * Get information for the reason of a Wake Up event
6884 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6886 struct i40e_asq_cmd_details *cmd_details)
6888 struct i40e_aq_desc desc;
6889 struct i40e_aqc_get_wake_reason_completion *resp =
6890 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6891 enum i40e_status_code status;
6893 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6895 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6897 if (status == I40E_SUCCESS)
6898 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6904 * i40e_aq_clear_all_wol_filters
6905 * @hw: pointer to the hw struct
6906 * @cmd_details: pointer to command details structure or NULL
6908 * Get information for the reason of a Wake Up event
6910 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
6911 struct i40e_asq_cmd_details *cmd_details)
6913 struct i40e_aq_desc desc;
6914 enum i40e_status_code status;
6916 i40e_fill_default_direct_cmd_desc(&desc,
6917 i40e_aqc_opc_clear_all_wol_filters);
6919 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6923 #endif /* X722_SUPPORT */