drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  19 #else
  20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  21 #endif
  22 {
  23         enum i40e_status_code status = I40E_SUCCESS;
  24
  25         DEBUGFUNC("i40e_set_mac_type\n");
  26
  27         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  28                 switch (hw->device_id) {
  29                 case I40E_DEV_ID_SFP_XL710:
  30                 case I40E_DEV_ID_QEMU:
  31                 case I40E_DEV_ID_KX_B:
  32                 case I40E_DEV_ID_KX_C:
  33                 case I40E_DEV_ID_QSFP_A:
  34                 case I40E_DEV_ID_QSFP_B:
  35                 case I40E_DEV_ID_QSFP_C:
  36                 case I40E_DEV_ID_10G_BASE_T:
  37                 case I40E_DEV_ID_10G_BASE_T4:
  38                 case I40E_DEV_ID_10G_BASE_T_BC:
  39                 case I40E_DEV_ID_10G_B:
  40                 case I40E_DEV_ID_10G_SFP:
  41                 case I40E_DEV_ID_20G_KR2:
  42                 case I40E_DEV_ID_20G_KR2_A:
  43                 case I40E_DEV_ID_25G_B:
  44                 case I40E_DEV_ID_25G_SFP28:
  45                 case I40E_DEV_ID_X710_N3000:
  46                 case I40E_DEV_ID_XXV710_N3000:
  47                         hw->mac.type = I40E_MAC_XL710;
  48                         break;
  49 #ifdef X722_A0_SUPPORT
  50                 case I40E_DEV_ID_X722_A0:
  51 #endif
  52                 case I40E_DEV_ID_KX_X722:
  53                 case I40E_DEV_ID_QSFP_X722:
  54                 case I40E_DEV_ID_SFP_X722:
  55                 case I40E_DEV_ID_1G_BASE_T_X722:
  56                 case I40E_DEV_ID_10G_BASE_T_X722:
  57                 case I40E_DEV_ID_SFP_I_X722:
  58                         hw->mac.type = I40E_MAC_X722;
  59                         break;
  60 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  61                 case I40E_DEV_ID_X722_VF:
  62 #ifdef X722_A0_SUPPORT
  63                 case I40E_DEV_ID_X722_A0_VF:
  64 #endif
  65                         hw->mac.type = I40E_MAC_X722_VF;
  66                         break;
  67 #endif /* INTEGRATED_VF || VF_DRIVER */
  68 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  69                 case I40E_DEV_ID_VF:
  70                 case I40E_DEV_ID_VF_HV:
  71                 case I40E_DEV_ID_ADAPTIVE_VF:
  72                         hw->mac.type = I40E_MAC_VF;
  73                         break;
  74 #endif
  75                 default:
  76                         hw->mac.type = I40E_MAC_GENERIC;
  77                         break;
  78                 }
  79         } else {
  80                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  81         }
  82
  83         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  84                   hw->mac.type, status);
  85         return status;
  86 }
  87
  88 /**
  89  * i40e_aq_str - convert AQ err code to a string
  90  * @hw: pointer to the HW structure
  91  * @aq_err: the AQ error code to convert
  92  **/
  93 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  94 {
  95         switch (aq_err) {
  96         case I40E_AQ_RC_OK:
  97                 return "OK";
  98         case I40E_AQ_RC_EPERM:
  99                 return "I40E_AQ_RC_EPERM";
 100         case I40E_AQ_RC_ENOENT:
 101                 return "I40E_AQ_RC_ENOENT";
 102         case I40E_AQ_RC_ESRCH:
 103                 return "I40E_AQ_RC_ESRCH";
 104         case I40E_AQ_RC_EINTR:
 105                 return "I40E_AQ_RC_EINTR";
 106         case I40E_AQ_RC_EIO:
 107                 return "I40E_AQ_RC_EIO";
 108         case I40E_AQ_RC_ENXIO:
 109                 return "I40E_AQ_RC_ENXIO";
 110         case I40E_AQ_RC_E2BIG:
 111                 return "I40E_AQ_RC_E2BIG";
 112         case I40E_AQ_RC_EAGAIN:
 113                 return "I40E_AQ_RC_EAGAIN";
 114         case I40E_AQ_RC_ENOMEM:
 115                 return "I40E_AQ_RC_ENOMEM";
 116         case I40E_AQ_RC_EACCES:
 117                 return "I40E_AQ_RC_EACCES";
 118         case I40E_AQ_RC_EFAULT:
 119                 return "I40E_AQ_RC_EFAULT";
 120         case I40E_AQ_RC_EBUSY:
 121                 return "I40E_AQ_RC_EBUSY";
 122         case I40E_AQ_RC_EEXIST:
 123                 return "I40E_AQ_RC_EEXIST";
 124         case I40E_AQ_RC_EINVAL:
 125                 return "I40E_AQ_RC_EINVAL";
 126         case I40E_AQ_RC_ENOTTY:
 127                 return "I40E_AQ_RC_ENOTTY";
 128         case I40E_AQ_RC_ENOSPC:
 129                 return "I40E_AQ_RC_ENOSPC";
 130         case I40E_AQ_RC_ENOSYS:
 131                 return "I40E_AQ_RC_ENOSYS";
 132         case I40E_AQ_RC_ERANGE:
 133                 return "I40E_AQ_RC_ERANGE";
 134         case I40E_AQ_RC_EFLUSHED:
 135                 return "I40E_AQ_RC_EFLUSHED";
 136         case I40E_AQ_RC_BAD_ADDR:
 137                 return "I40E_AQ_RC_BAD_ADDR";
 138         case I40E_AQ_RC_EMODE:
 139                 return "I40E_AQ_RC_EMODE";
 140         case I40E_AQ_RC_EFBIG:
 141                 return "I40E_AQ_RC_EFBIG";
 142         }
 143
 144         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 145         return hw->err_str;
 146 }
 147
 148 /**
 149  * i40e_stat_str - convert status err code to a string
 150  * @hw: pointer to the HW structure
 151  * @stat_err: the status error code to convert
 152  **/
 153 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 154 {
 155         switch (stat_err) {
 156         case I40E_SUCCESS:
 157                 return "OK";
 158         case I40E_ERR_NVM:
 159                 return "I40E_ERR_NVM";
 160         case I40E_ERR_NVM_CHECKSUM:
 161                 return "I40E_ERR_NVM_CHECKSUM";
 162         case I40E_ERR_PHY:
 163                 return "I40E_ERR_PHY";
 164         case I40E_ERR_CONFIG:
 165                 return "I40E_ERR_CONFIG";
 166         case I40E_ERR_PARAM:
 167                 return "I40E_ERR_PARAM";
 168         case I40E_ERR_MAC_TYPE:
 169                 return "I40E_ERR_MAC_TYPE";
 170         case I40E_ERR_UNKNOWN_PHY:
 171                 return "I40E_ERR_UNKNOWN_PHY";
 172         case I40E_ERR_LINK_SETUP:
 173                 return "I40E_ERR_LINK_SETUP";
 174         case I40E_ERR_ADAPTER_STOPPED:
 175                 return "I40E_ERR_ADAPTER_STOPPED";
 176         case I40E_ERR_INVALID_MAC_ADDR:
 177                 return "I40E_ERR_INVALID_MAC_ADDR";
 178         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 179                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 180         case I40E_ERR_MASTER_REQUESTS_PENDING:
 181                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 182         case I40E_ERR_INVALID_LINK_SETTINGS:
 183                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 184         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 185                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 186         case I40E_ERR_RESET_FAILED:
 187                 return "I40E_ERR_RESET_FAILED";
 188         case I40E_ERR_SWFW_SYNC:
 189                 return "I40E_ERR_SWFW_SYNC";
 190         case I40E_ERR_NO_AVAILABLE_VSI:
 191                 return "I40E_ERR_NO_AVAILABLE_VSI";
 192         case I40E_ERR_NO_MEMORY:
 193                 return "I40E_ERR_NO_MEMORY";
 194         case I40E_ERR_BAD_PTR:
 195                 return "I40E_ERR_BAD_PTR";
 196         case I40E_ERR_RING_FULL:
 197                 return "I40E_ERR_RING_FULL";
 198         case I40E_ERR_INVALID_PD_ID:
 199                 return "I40E_ERR_INVALID_PD_ID";
 200         case I40E_ERR_INVALID_QP_ID:
 201                 return "I40E_ERR_INVALID_QP_ID";
 202         case I40E_ERR_INVALID_CQ_ID:
 203                 return "I40E_ERR_INVALID_CQ_ID";
 204         case I40E_ERR_INVALID_CEQ_ID:
 205                 return "I40E_ERR_INVALID_CEQ_ID";
 206         case I40E_ERR_INVALID_AEQ_ID:
 207                 return "I40E_ERR_INVALID_AEQ_ID";
 208         case I40E_ERR_INVALID_SIZE:
 209                 return "I40E_ERR_INVALID_SIZE";
 210         case I40E_ERR_INVALID_ARP_INDEX:
 211                 return "I40E_ERR_INVALID_ARP_INDEX";
 212         case I40E_ERR_INVALID_FPM_FUNC_ID:
 213                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 214         case I40E_ERR_QP_INVALID_MSG_SIZE:
 215                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 216         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 217                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 218         case I40E_ERR_INVALID_FRAG_COUNT:
 219                 return "I40E_ERR_INVALID_FRAG_COUNT";
 220         case I40E_ERR_QUEUE_EMPTY:
 221                 return "I40E_ERR_QUEUE_EMPTY";
 222         case I40E_ERR_INVALID_ALIGNMENT:
 223                 return "I40E_ERR_INVALID_ALIGNMENT";
 224         case I40E_ERR_FLUSHED_QUEUE:
 225                 return "I40E_ERR_FLUSHED_QUEUE";
 226         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 227                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 228         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 229                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 230         case I40E_ERR_TIMEOUT:
 231                 return "I40E_ERR_TIMEOUT";
 232         case I40E_ERR_OPCODE_MISMATCH:
 233                 return "I40E_ERR_OPCODE_MISMATCH";
 234         case I40E_ERR_CQP_COMPL_ERROR:
 235                 return "I40E_ERR_CQP_COMPL_ERROR";
 236         case I40E_ERR_INVALID_VF_ID:
 237                 return "I40E_ERR_INVALID_VF_ID";
 238         case I40E_ERR_INVALID_HMCFN_ID:
 239                 return "I40E_ERR_INVALID_HMCFN_ID";
 240         case I40E_ERR_BACKING_PAGE_ERROR:
 241                 return "I40E_ERR_BACKING_PAGE_ERROR";
 242         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 243                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 244         case I40E_ERR_INVALID_PBLE_INDEX:
 245                 return "I40E_ERR_INVALID_PBLE_INDEX";
 246         case I40E_ERR_INVALID_SD_INDEX:
 247                 return "I40E_ERR_INVALID_SD_INDEX";
 248         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 249                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 250         case I40E_ERR_INVALID_SD_TYPE:
 251                 return "I40E_ERR_INVALID_SD_TYPE";
 252         case I40E_ERR_MEMCPY_FAILED:
 253                 return "I40E_ERR_MEMCPY_FAILED";
 254         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 255                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 256         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 257                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 258         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 259                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 260         case I40E_ERR_SRQ_ENABLED:
 261                 return "I40E_ERR_SRQ_ENABLED";
 262         case I40E_ERR_ADMIN_QUEUE_ERROR:
 263                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 264         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 265                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 266         case I40E_ERR_BUF_TOO_SHORT:
 267                 return "I40E_ERR_BUF_TOO_SHORT";
 268         case I40E_ERR_ADMIN_QUEUE_FULL:
 269                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 270         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 271                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 272         case I40E_ERR_BAD_IWARP_CQE:
 273                 return "I40E_ERR_BAD_IWARP_CQE";
 274         case I40E_ERR_NVM_BLANK_MODE:
 275                 return "I40E_ERR_NVM_BLANK_MODE";
 276         case I40E_ERR_NOT_IMPLEMENTED:
 277                 return "I40E_ERR_NOT_IMPLEMENTED";
 278         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 279                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 280         case I40E_ERR_DIAG_TEST_FAILED:
 281                 return "I40E_ERR_DIAG_TEST_FAILED";
 282         case I40E_ERR_NOT_READY:
 283                 return "I40E_ERR_NOT_READY";
 284         case I40E_NOT_SUPPORTED:
 285                 return "I40E_NOT_SUPPORTED";
 286         case I40E_ERR_FIRMWARE_API_VERSION:
 287                 return "I40E_ERR_FIRMWARE_API_VERSION";
 288         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 289                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 290         }
 291
 292         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 293         return hw->err_str;
 294 }
 295
 296 /**
 297  * i40e_debug_aq
 298  * @hw: debug mask related to admin queue
 299  * @mask: debug mask
 300  * @desc: pointer to admin queue descriptor
 301  * @buffer: pointer to command buffer
 302  * @buf_len: max length of buffer
 303  *
 304  * Dumps debug log about adminq command with descriptor contents.
 305  **/
 306 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 307                    void *buffer, u16 buf_len)
 308 {
 309         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 310         u32 effective_mask = hw->debug_mask & mask;
 311         u8 *buf = (u8 *)buffer;
 312         u16 len;
 313         u16 i;
 314
 315         if (!effective_mask || !desc)
 316                 return;
 317
 318         len = LE16_TO_CPU(aq_desc->datalen);
 319
 320         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 321                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 322                    LE16_TO_CPU(aq_desc->opcode),
 323                    LE16_TO_CPU(aq_desc->flags),
 324                    LE16_TO_CPU(aq_desc->datalen),
 325                    LE16_TO_CPU(aq_desc->retval));
 326         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 327                    "\tcookie (h,l) 0x%08X 0x%08X\n",
 328                    LE32_TO_CPU(aq_desc->cookie_high),
 329                    LE32_TO_CPU(aq_desc->cookie_low));
 330         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 331                    "\tparam (0,1)  0x%08X 0x%08X\n",
 332                    LE32_TO_CPU(aq_desc->params.internal.param0),
 333                    LE32_TO_CPU(aq_desc->params.internal.param1));
 334         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 335                    "\taddr (h,l)   0x%08X 0x%08X\n",
 336                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 337                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 338
 339         if (buffer && (buf_len != 0) && (len != 0) &&
 340             (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
 341                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 342                 if (buf_len < len)
 343                         len = buf_len;
 344                 /* write the full 16-byte chunks */
 345                 for (i = 0; i < (len - 16); i += 16)
 346                         i40e_debug(hw, mask,
 347                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 348                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 349                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 350                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 351                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 352                 /* the most we could have left is 16 bytes, pad with zeros */
 353                 if (i < len) {
 354                         char d_buf[16];
 355                         int j, i_sav;
 356
 357                         i_sav = i;
 358                         memset(d_buf, 0, sizeof(d_buf));
 359                         for (j = 0; i < len; j++, i++)
 360                                 d_buf[j] = buf[i];
 361                         i40e_debug(hw, mask,
 362                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 363                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 364                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 365                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 366                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 367                 }
 368         }
 369 }
 370
 371 /**
 372  * i40e_check_asq_alive
 373  * @hw: pointer to the hw struct
 374  *
 375  * Returns true if Queue is enabled else false.
 376  **/
 377 bool i40e_check_asq_alive(struct i40e_hw *hw)
 378 {
 379         if (hw->aq.asq.len)
 380 #ifdef PF_DRIVER
 381 #ifdef INTEGRATED_VF
 382                 if (!i40e_is_vf(hw))
 383                         return !!(rd32(hw, hw->aq.asq.len) &
 384                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 385 #else
 386                 return !!(rd32(hw, hw->aq.asq.len) &
 387                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 388 #endif /* INTEGRATED_VF */
 389 #endif /* PF_DRIVER */
 390 #ifdef VF_DRIVER
 391 #ifdef INTEGRATED_VF
 392                 if (i40e_is_vf(hw))
 393                         return !!(rd32(hw, hw->aq.asq.len) &
 394                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 395 #else
 396                 return !!(rd32(hw, hw->aq.asq.len) &
 397                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 398 #endif /* INTEGRATED_VF */
 399 #endif /* VF_DRIVER */
 400         return false;
 401 }
 402
 403 /**
 404  * i40e_aq_queue_shutdown
 405  * @hw: pointer to the hw struct
 406  * @unloading: is the driver unloading itself
 407  *
 408  * Tell the Firmware that we're shutting down the AdminQ and whether
 409  * or not the driver is unloading as well.
 410  **/
 411 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 412                                              bool unloading)
 413 {
 414         struct i40e_aq_desc desc;
 415         struct i40e_aqc_queue_shutdown *cmd =
 416                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 417         enum i40e_status_code status;
 418
 419         i40e_fill_default_direct_cmd_desc(&desc,
 420                                           i40e_aqc_opc_queue_shutdown);
 421
 422         if (unloading)
 423                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 424         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 425
 426         return status;
 427 }
 428
 429 /**
 430  * i40e_aq_get_set_rss_lut
 431  * @hw: pointer to the hardware structure
 432  * @vsi_id: vsi fw index
 433  * @pf_lut: for PF table set true, for VSI table set false
 434  * @lut: pointer to the lut buffer provided by the caller
 435  * @lut_size: size of the lut buffer
 436  * @set: set true to set the table, false to get the table
 437  *
 438  * Internal function to get or set RSS look up table
 439  **/
 440 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 441                                                      u16 vsi_id, bool pf_lut,
 442                                                      u8 *lut, u16 lut_size,
 443                                                      bool set)
 444 {
 445         enum i40e_status_code status;
 446         struct i40e_aq_desc desc;
 447         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 448                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 449
 450         if (set)
 451                 i40e_fill_default_direct_cmd_desc(&desc,
 452                                                   i40e_aqc_opc_set_rss_lut);
 453         else
 454                 i40e_fill_default_direct_cmd_desc(&desc,
 455                                                   i40e_aqc_opc_get_rss_lut);
 456
 457         /* Indirect command */
 458         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 459         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 460
 461         cmd_resp->vsi_id =
 462                         CPU_TO_LE16((u16)((vsi_id <<
 463                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 464                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 465         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 466
 467         if (pf_lut)
 468                 cmd_resp->flags |= CPU_TO_LE16((u16)
 469                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 470                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 471                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 472         else
 473                 cmd_resp->flags |= CPU_TO_LE16((u16)
 474                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 475                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 476                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 477
 478         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 479
 480         return status;
 481 }
 482
 483 /**
 484  * i40e_aq_get_rss_lut
 485  * @hw: pointer to the hardware structure
 486  * @vsi_id: vsi fw index
 487  * @pf_lut: for PF table set true, for VSI table set false
 488  * @lut: pointer to the lut buffer provided by the caller
 489  * @lut_size: size of the lut buffer
 490  *
 491  * get the RSS lookup table, PF or VSI type
 492  **/
 493 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 494                                           bool pf_lut, u8 *lut, u16 lut_size)
 495 {
 496         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 497                                        false);
 498 }
 499
 500 /**
 501  * i40e_aq_set_rss_lut
 502  * @hw: pointer to the hardware structure
 503  * @vsi_id: vsi fw index
 504  * @pf_lut: for PF table set true, for VSI table set false
 505  * @lut: pointer to the lut buffer provided by the caller
 506  * @lut_size: size of the lut buffer
 507  *
 508  * set the RSS lookup table, PF or VSI type
 509  **/
 510 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 511                                           bool pf_lut, u8 *lut, u16 lut_size)
 512 {
 513         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 514 }
 515
 516 /**
 517  * i40e_aq_get_set_rss_key
 518  * @hw: pointer to the hw struct
 519  * @vsi_id: vsi fw index
 520  * @key: pointer to key info struct
 521  * @set: set true to set the key, false to get the key
 522  *
 523  * get the RSS key per VSI
 524  **/
 525 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 526                                       u16 vsi_id,
 527                                       struct i40e_aqc_get_set_rss_key_data *key,
 528                                       bool set)
 529 {
 530         enum i40e_status_code status;
 531         struct i40e_aq_desc desc;
 532         struct i40e_aqc_get_set_rss_key *cmd_resp =
 533                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 534         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 535
 536         if (set)
 537                 i40e_fill_default_direct_cmd_desc(&desc,
 538                                                   i40e_aqc_opc_set_rss_key);
 539         else
 540                 i40e_fill_default_direct_cmd_desc(&desc,
 541                                                   i40e_aqc_opc_get_rss_key);
 542
 543         /* Indirect command */
 544         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 545         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 546
 547         cmd_resp->vsi_id =
 548                         CPU_TO_LE16((u16)((vsi_id <<
 549                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 550                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 551         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 552
 553         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 554
 555         return status;
 556 }
 557
 558 /**
 559  * i40e_aq_get_rss_key
 560  * @hw: pointer to the hw struct
 561  * @vsi_id: vsi fw index
 562  * @key: pointer to key info struct
 563  *
 564  **/
 565 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 566                                       u16 vsi_id,
 567                                       struct i40e_aqc_get_set_rss_key_data *key)
 568 {
 569         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 570 }
 571
 572 /**
 573  * i40e_aq_set_rss_key
 574  * @hw: pointer to the hw struct
 575  * @vsi_id: vsi fw index
 576  * @key: pointer to key info struct
 577  *
 578  * set the RSS key per VSI
 579  **/
 580 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 581                                       u16 vsi_id,
 582                                       struct i40e_aqc_get_set_rss_key_data *key)
 583 {
 584         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 585 }
 586
 587 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 588  * hardware to a bit-field that can be used by SW to more easily determine the
 589  * packet type.
 590  *
 591  * Macros are used to shorten the table lines and make this table human
 592  * readable.
 593  *
 594  * We store the PTYPE in the top byte of the bit field - this is just so that
 595  * we can check that the table doesn't have a row missing, as the index into
 596  * the table should be the PTYPE.
 597  *
 598  * Typical work flow:
 599  *
 600  * IF NOT i40e_ptype_lookup[ptype].known
 601  * THEN
 602  *      Packet is unknown
 603  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 604  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 605  * ELSE
 606  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 607  * ENDIF
 608  */
 609
 610 /* macro to make the table lines short */
 611 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 612         {       PTYPE, \
 613                 1, \
 614                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 615                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 616                 I40E_RX_PTYPE_##OUTER_FRAG, \
 617                 I40E_RX_PTYPE_TUNNEL_##T, \
 618                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 619                 I40E_RX_PTYPE_##TEF, \
 620                 I40E_RX_PTYPE_INNER_PROT_##I, \
 621                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 622
 623 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 624                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 625
 626 /* shorter macros makes the table fit but are terse */
 627 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 628 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 629 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 630
 631 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 632 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 633         /* L2 Packet types */
 634         I40E_PTT_UNUSED_ENTRY(0),
 635         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 636         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 637         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 638         I40E_PTT_UNUSED_ENTRY(4),
 639         I40E_PTT_UNUSED_ENTRY(5),
 640         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 641         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 642         I40E_PTT_UNUSED_ENTRY(8),
 643         I40E_PTT_UNUSED_ENTRY(9),
 644         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 645         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 646         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 651         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 652         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 653         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 654         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 655         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 656
 657         /* Non Tunneled IPv4 */
 658         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 659         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 660         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 661         I40E_PTT_UNUSED_ENTRY(25),
 662         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 663         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 664         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 665
 666         /* IPv4 --> IPv4 */
 667         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 668         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 669         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 670         I40E_PTT_UNUSED_ENTRY(32),
 671         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 672         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 673         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 674
 675         /* IPv4 --> IPv6 */
 676         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 677         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 678         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 679         I40E_PTT_UNUSED_ENTRY(39),
 680         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 681         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 682         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 683
 684         /* IPv4 --> GRE/NAT */
 685         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 686
 687         /* IPv4 --> GRE/NAT --> IPv4 */
 688         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 689         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 690         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 691         I40E_PTT_UNUSED_ENTRY(47),
 692         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 693         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 694         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 695
 696         /* IPv4 --> GRE/NAT --> IPv6 */
 697         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 698         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 699         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 700         I40E_PTT_UNUSED_ENTRY(54),
 701         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 702         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 703         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 704
 705         /* IPv4 --> GRE/NAT --> MAC */
 706         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 707
 708         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 709         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 710         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 711         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 712         I40E_PTT_UNUSED_ENTRY(62),
 713         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 714         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 715         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 716
 717         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 718         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 719         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 720         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 721         I40E_PTT_UNUSED_ENTRY(69),
 722         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 723         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 724         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 725
 726         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 727         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 728
 729         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 730         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 731         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 732         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 733         I40E_PTT_UNUSED_ENTRY(77),
 734         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 735         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 736         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 737
 738         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 739         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 740         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 741         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 742         I40E_PTT_UNUSED_ENTRY(84),
 743         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 744         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 745         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 746
 747         /* Non Tunneled IPv6 */
 748         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 749         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 750         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 751         I40E_PTT_UNUSED_ENTRY(91),
 752         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 753         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 754         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 755
 756         /* IPv6 --> IPv4 */
 757         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 758         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 759         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 760         I40E_PTT_UNUSED_ENTRY(98),
 761         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 762         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 763         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 764
 765         /* IPv6 --> IPv6 */
 766         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 767         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 768         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 769         I40E_PTT_UNUSED_ENTRY(105),
 770         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 771         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 772         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 773
 774         /* IPv6 --> GRE/NAT */
 775         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 776
 777         /* IPv6 --> GRE/NAT -> IPv4 */
 778         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 779         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 780         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 781         I40E_PTT_UNUSED_ENTRY(113),
 782         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 783         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 784         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 785
 786         /* IPv6 --> GRE/NAT -> IPv6 */
 787         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 788         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 789         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 790         I40E_PTT_UNUSED_ENTRY(120),
 791         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 792         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 793         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 794
 795         /* IPv6 --> GRE/NAT -> MAC */
 796         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 797
 798         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 799         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 800         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 801         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 802         I40E_PTT_UNUSED_ENTRY(128),
 803         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 804         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 805         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 806
 807         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 808         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 809         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 810         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 811         I40E_PTT_UNUSED_ENTRY(135),
 812         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 813         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 814         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 815
 816         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 817         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 818
 819         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 820         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 821         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 822         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 823         I40E_PTT_UNUSED_ENTRY(143),
 824         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 825         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 826         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 827
 828         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 829         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 830         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 831         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 832         I40E_PTT_UNUSED_ENTRY(150),
 833         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 834         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 835         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 836
 837         /* unused entries */
 838         I40E_PTT_UNUSED_ENTRY(154),
 839         I40E_PTT_UNUSED_ENTRY(155),
 840         I40E_PTT_UNUSED_ENTRY(156),
 841         I40E_PTT_UNUSED_ENTRY(157),
 842         I40E_PTT_UNUSED_ENTRY(158),
 843         I40E_PTT_UNUSED_ENTRY(159),
 844
 845         I40E_PTT_UNUSED_ENTRY(160),
 846         I40E_PTT_UNUSED_ENTRY(161),
 847         I40E_PTT_UNUSED_ENTRY(162),
 848         I40E_PTT_UNUSED_ENTRY(163),
 849         I40E_PTT_UNUSED_ENTRY(164),
 850         I40E_PTT_UNUSED_ENTRY(165),
 851         I40E_PTT_UNUSED_ENTRY(166),
 852         I40E_PTT_UNUSED_ENTRY(167),
 853         I40E_PTT_UNUSED_ENTRY(168),
 854         I40E_PTT_UNUSED_ENTRY(169),
 855
 856         I40E_PTT_UNUSED_ENTRY(170),
 857         I40E_PTT_UNUSED_ENTRY(171),
 858         I40E_PTT_UNUSED_ENTRY(172),
 859         I40E_PTT_UNUSED_ENTRY(173),
 860         I40E_PTT_UNUSED_ENTRY(174),
 861         I40E_PTT_UNUSED_ENTRY(175),
 862         I40E_PTT_UNUSED_ENTRY(176),
 863         I40E_PTT_UNUSED_ENTRY(177),
 864         I40E_PTT_UNUSED_ENTRY(178),
 865         I40E_PTT_UNUSED_ENTRY(179),
 866
 867         I40E_PTT_UNUSED_ENTRY(180),
 868         I40E_PTT_UNUSED_ENTRY(181),
 869         I40E_PTT_UNUSED_ENTRY(182),
 870         I40E_PTT_UNUSED_ENTRY(183),
 871         I40E_PTT_UNUSED_ENTRY(184),
 872         I40E_PTT_UNUSED_ENTRY(185),
 873         I40E_PTT_UNUSED_ENTRY(186),
 874         I40E_PTT_UNUSED_ENTRY(187),
 875         I40E_PTT_UNUSED_ENTRY(188),
 876         I40E_PTT_UNUSED_ENTRY(189),
 877
 878         I40E_PTT_UNUSED_ENTRY(190),
 879         I40E_PTT_UNUSED_ENTRY(191),
 880         I40E_PTT_UNUSED_ENTRY(192),
 881         I40E_PTT_UNUSED_ENTRY(193),
 882         I40E_PTT_UNUSED_ENTRY(194),
 883         I40E_PTT_UNUSED_ENTRY(195),
 884         I40E_PTT_UNUSED_ENTRY(196),
 885         I40E_PTT_UNUSED_ENTRY(197),
 886         I40E_PTT_UNUSED_ENTRY(198),
 887         I40E_PTT_UNUSED_ENTRY(199),
 888
 889         I40E_PTT_UNUSED_ENTRY(200),
 890         I40E_PTT_UNUSED_ENTRY(201),
 891         I40E_PTT_UNUSED_ENTRY(202),
 892         I40E_PTT_UNUSED_ENTRY(203),
 893         I40E_PTT_UNUSED_ENTRY(204),
 894         I40E_PTT_UNUSED_ENTRY(205),
 895         I40E_PTT_UNUSED_ENTRY(206),
 896         I40E_PTT_UNUSED_ENTRY(207),
 897         I40E_PTT_UNUSED_ENTRY(208),
 898         I40E_PTT_UNUSED_ENTRY(209),
 899
 900         I40E_PTT_UNUSED_ENTRY(210),
 901         I40E_PTT_UNUSED_ENTRY(211),
 902         I40E_PTT_UNUSED_ENTRY(212),
 903         I40E_PTT_UNUSED_ENTRY(213),
 904         I40E_PTT_UNUSED_ENTRY(214),
 905         I40E_PTT_UNUSED_ENTRY(215),
 906         I40E_PTT_UNUSED_ENTRY(216),
 907         I40E_PTT_UNUSED_ENTRY(217),
 908         I40E_PTT_UNUSED_ENTRY(218),
 909         I40E_PTT_UNUSED_ENTRY(219),
 910
 911         I40E_PTT_UNUSED_ENTRY(220),
 912         I40E_PTT_UNUSED_ENTRY(221),
 913         I40E_PTT_UNUSED_ENTRY(222),
 914         I40E_PTT_UNUSED_ENTRY(223),
 915         I40E_PTT_UNUSED_ENTRY(224),
 916         I40E_PTT_UNUSED_ENTRY(225),
 917         I40E_PTT_UNUSED_ENTRY(226),
 918         I40E_PTT_UNUSED_ENTRY(227),
 919         I40E_PTT_UNUSED_ENTRY(228),
 920         I40E_PTT_UNUSED_ENTRY(229),
 921
 922         I40E_PTT_UNUSED_ENTRY(230),
 923         I40E_PTT_UNUSED_ENTRY(231),
 924         I40E_PTT_UNUSED_ENTRY(232),
 925         I40E_PTT_UNUSED_ENTRY(233),
 926         I40E_PTT_UNUSED_ENTRY(234),
 927         I40E_PTT_UNUSED_ENTRY(235),
 928         I40E_PTT_UNUSED_ENTRY(236),
 929         I40E_PTT_UNUSED_ENTRY(237),
 930         I40E_PTT_UNUSED_ENTRY(238),
 931         I40E_PTT_UNUSED_ENTRY(239),
 932
 933         I40E_PTT_UNUSED_ENTRY(240),
 934         I40E_PTT_UNUSED_ENTRY(241),
 935         I40E_PTT_UNUSED_ENTRY(242),
 936         I40E_PTT_UNUSED_ENTRY(243),
 937         I40E_PTT_UNUSED_ENTRY(244),
 938         I40E_PTT_UNUSED_ENTRY(245),
 939         I40E_PTT_UNUSED_ENTRY(246),
 940         I40E_PTT_UNUSED_ENTRY(247),
 941         I40E_PTT_UNUSED_ENTRY(248),
 942         I40E_PTT_UNUSED_ENTRY(249),
 943
 944         I40E_PTT_UNUSED_ENTRY(250),
 945         I40E_PTT_UNUSED_ENTRY(251),
 946         I40E_PTT_UNUSED_ENTRY(252),
 947         I40E_PTT_UNUSED_ENTRY(253),
 948         I40E_PTT_UNUSED_ENTRY(254),
 949         I40E_PTT_UNUSED_ENTRY(255)
 950 };
 951
 952
 953 /**
 954  * i40e_validate_mac_addr - Validate unicast MAC address
 955  * @mac_addr: pointer to MAC address
 956  *
 957  * Tests a MAC address to ensure it is a valid Individual Address
 958  **/
 959 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 960 {
 961         enum i40e_status_code status = I40E_SUCCESS;
 962
 963         DEBUGFUNC("i40e_validate_mac_addr");
 964
 965         /* Broadcast addresses ARE multicast addresses
 966          * Make sure it is not a multicast address
 967          * Reject the zero address
 968          */
 969         if (I40E_IS_MULTICAST(mac_addr) ||
 970             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 971               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 972                 status = I40E_ERR_INVALID_MAC_ADDR;
 973
 974         return status;
 975 }
 976 #ifdef PF_DRIVER
 977
 978 /**
 979  * i40e_init_shared_code - Initialize the shared code
 980  * @hw: pointer to hardware structure
 981  *
 982  * This assigns the MAC type and PHY code and inits the NVM.
 983  * Does not touch the hardware. This function must be called prior to any
 984  * other function in the shared code. The i40e_hw structure should be
 985  * memset to 0 prior to calling this function.  The following fields in
 986  * hw structure should be filled in prior to calling this function:
 987  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 988  * subsystem_vendor_id, and revision_id
 989  **/
 990 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 991 {
 992         enum i40e_status_code status = I40E_SUCCESS;
 993         u32 port, ari, func_rid;
 994
 995         DEBUGFUNC("i40e_init_shared_code");
 996
 997         i40e_set_mac_type(hw);
 998
 999         switch (hw->mac.type) {
1000         case I40E_MAC_XL710:
1001         case I40E_MAC_X722:
1002                 break;
1003         default:
1004                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1005         }
1006
1007         hw->phy.get_link_info = true;
1008
1009         /* Determine port number and PF number*/
1010         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1011                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1012         hw->port = (u8)port;
1013         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1014                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1015         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1016         if (ari)
1017                 hw->pf_id = (u8)(func_rid & 0xff);
1018         else
1019                 hw->pf_id = (u8)(func_rid & 0x7);
1020
1021         if (hw->mac.type == I40E_MAC_X722)
1022                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1023                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1024         /* NVMUpdate features structure initialization */
1025         hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1026         hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1027         hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1028         i40e_memset(hw->nvmupd_features.features, 0x0,
1029                     I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1030                     sizeof(*hw->nvmupd_features.features),
1031                     I40E_NONDMA_MEM);
1032
1033         /* No features supported at the moment */
1034         hw->nvmupd_features.features[0] = 0;
1035
1036         status = i40e_init_nvm(hw);
1037         return status;
1038 }
1039
1040 /**
1041  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1042  * @hw: pointer to the hw struct
1043  * @flags: a return indicator of what addresses were added to the addr store
1044  * @addrs: the requestor's mac addr store
1045  * @cmd_details: pointer to command details structure or NULL
1046  **/
1047 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1048                                    u16 *flags,
1049                                    struct i40e_aqc_mac_address_read_data *addrs,
1050                                    struct i40e_asq_cmd_details *cmd_details)
1051 {
1052         struct i40e_aq_desc desc;
1053         struct i40e_aqc_mac_address_read *cmd_data =
1054                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1055         enum i40e_status_code status;
1056
1057         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1058         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1059
1060         status = i40e_asq_send_command(hw, &desc, addrs,
1061                                        sizeof(*addrs), cmd_details);
1062         *flags = LE16_TO_CPU(cmd_data->command_flags);
1063
1064         return status;
1065 }
1066
1067 /**
1068  * i40e_aq_mac_address_write - Change the MAC addresses
1069  * @hw: pointer to the hw struct
1070  * @flags: indicates which MAC to be written
1071  * @mac_addr: address to write
1072  * @cmd_details: pointer to command details structure or NULL
1073  **/
1074 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1075                                     u16 flags, u8 *mac_addr,
1076                                     struct i40e_asq_cmd_details *cmd_details)
1077 {
1078         struct i40e_aq_desc desc;
1079         struct i40e_aqc_mac_address_write *cmd_data =
1080                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1081         enum i40e_status_code status;
1082
1083         i40e_fill_default_direct_cmd_desc(&desc,
1084                                           i40e_aqc_opc_mac_address_write);
1085         cmd_data->command_flags = CPU_TO_LE16(flags);
1086         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1087         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1088                                         ((u32)mac_addr[3] << 16) |
1089                                         ((u32)mac_addr[4] << 8) |
1090                                         mac_addr[5]);
1091
1092         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1093
1094         return status;
1095 }
1096
1097 /**
1098  * i40e_get_mac_addr - get MAC address
1099  * @hw: pointer to the HW structure
1100  * @mac_addr: pointer to MAC address
1101  *
1102  * Reads the adapter's MAC address from register
1103  **/
1104 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1105 {
1106         struct i40e_aqc_mac_address_read_data addrs;
1107         enum i40e_status_code status;
1108         u16 flags = 0;
1109
1110         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1111
1112         if (flags & I40E_AQC_LAN_ADDR_VALID)
1113                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1114                         I40E_NONDMA_TO_NONDMA);
1115
1116         return status;
1117 }
1118
1119 /**
1120  * i40e_get_port_mac_addr - get Port MAC address
1121  * @hw: pointer to the HW structure
1122  * @mac_addr: pointer to Port MAC address
1123  *
1124  * Reads the adapter's Port MAC address
1125  **/
1126 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1127 {
1128         struct i40e_aqc_mac_address_read_data addrs;
1129         enum i40e_status_code status;
1130         u16 flags = 0;
1131
1132         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1133         if (status)
1134                 return status;
1135
1136         if (flags & I40E_AQC_PORT_ADDR_VALID)
1137                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1138                         I40E_NONDMA_TO_NONDMA);
1139         else
1140                 status = I40E_ERR_INVALID_MAC_ADDR;
1141
1142         return status;
1143 }
1144
1145 /**
1146  * i40e_pre_tx_queue_cfg - pre tx queue configure
1147  * @hw: pointer to the HW structure
1148  * @queue: target pf queue index
1149  * @enable: state change request
1150  *
1151  * Handles hw requirement to indicate intention to enable
1152  * or disable target queue.
1153  **/
1154 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1155 {
1156         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1157         u32 reg_block = 0;
1158         u32 reg_val;
1159
1160         if (abs_queue_idx >= 128) {
1161                 reg_block = abs_queue_idx / 128;
1162                 abs_queue_idx %= 128;
1163         }
1164
1165         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1166         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1167         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1168
1169         if (enable)
1170                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1171         else
1172                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1173
1174         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1175 }
1176
1177 /**
1178  * i40e_get_san_mac_addr - get SAN MAC address
1179  * @hw: pointer to the HW structure
1180  * @mac_addr: pointer to SAN MAC address
1181  *
1182  * Reads the adapter's SAN MAC address from NVM
1183  **/
1184 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1185                                             u8 *mac_addr)
1186 {
1187         struct i40e_aqc_mac_address_read_data addrs;
1188         enum i40e_status_code status;
1189         u16 flags = 0;
1190
1191         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1192         if (status)
1193                 return status;
1194
1195         if (flags & I40E_AQC_SAN_ADDR_VALID)
1196                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1197                         I40E_NONDMA_TO_NONDMA);
1198         else
1199                 status = I40E_ERR_INVALID_MAC_ADDR;
1200
1201         return status;
1202 }
1203
1204 /**
1205  *  i40e_read_pba_string - Reads part number string from EEPROM
1206  *  @hw: pointer to hardware structure
1207  *  @pba_num: stores the part number string from the EEPROM
1208  *  @pba_num_size: part number string buffer length
1209  *
1210  *  Reads the part number string from the EEPROM.
1211  **/
1212 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1213                                             u32 pba_num_size)
1214 {
1215         enum i40e_status_code status = I40E_SUCCESS;
1216         u16 pba_word = 0;
1217         u16 pba_size = 0;
1218         u16 pba_ptr = 0;
1219         u16 i = 0;
1220
1221         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1222         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1223                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1224                 return status;
1225         }
1226
1227         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1228         if (status != I40E_SUCCESS) {
1229                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1230                 return status;
1231         }
1232
1233         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1234         if (status != I40E_SUCCESS) {
1235                 DEBUGOUT("Failed to read PBA Block size.\n");
1236                 return status;
1237         }
1238
1239         /* Subtract one to get PBA word count (PBA Size word is included in
1240          * total size)
1241          */
1242         pba_size--;
1243         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1244                 DEBUGOUT("Buffer to small for PBA data.\n");
1245                 return I40E_ERR_PARAM;
1246         }
1247
1248         for (i = 0; i < pba_size; i++) {
1249                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1250                 if (status != I40E_SUCCESS) {
1251                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1252                         return status;
1253                 }
1254
1255                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1256                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1257         }
1258         pba_num[(pba_size * 2)] = '\0';
1259
1260         return status;
1261 }
1262
1263 /**
1264  * i40e_get_media_type - Gets media type
1265  * @hw: pointer to the hardware structure
1266  **/
1267 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1268 {
1269         enum i40e_media_type media;
1270
1271         switch (hw->phy.link_info.phy_type) {
1272         case I40E_PHY_TYPE_10GBASE_SR:
1273         case I40E_PHY_TYPE_10GBASE_LR:
1274         case I40E_PHY_TYPE_1000BASE_SX:
1275         case I40E_PHY_TYPE_1000BASE_LX:
1276         case I40E_PHY_TYPE_40GBASE_SR4:
1277         case I40E_PHY_TYPE_40GBASE_LR4:
1278         case I40E_PHY_TYPE_25GBASE_LR:
1279         case I40E_PHY_TYPE_25GBASE_SR:
1280                 media = I40E_MEDIA_TYPE_FIBER;
1281                 break;
1282         case I40E_PHY_TYPE_100BASE_TX:
1283         case I40E_PHY_TYPE_1000BASE_T:
1284         case I40E_PHY_TYPE_2_5GBASE_T:
1285         case I40E_PHY_TYPE_5GBASE_T:
1286         case I40E_PHY_TYPE_10GBASE_T:
1287                 media = I40E_MEDIA_TYPE_BASET;
1288                 break;
1289         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1290         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1291         case I40E_PHY_TYPE_10GBASE_CR1:
1292         case I40E_PHY_TYPE_40GBASE_CR4:
1293         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1294         case I40E_PHY_TYPE_40GBASE_AOC:
1295         case I40E_PHY_TYPE_10GBASE_AOC:
1296         case I40E_PHY_TYPE_25GBASE_CR:
1297         case I40E_PHY_TYPE_25GBASE_AOC:
1298         case I40E_PHY_TYPE_25GBASE_ACC:
1299                 media = I40E_MEDIA_TYPE_DA;
1300                 break;
1301         case I40E_PHY_TYPE_1000BASE_KX:
1302         case I40E_PHY_TYPE_10GBASE_KX4:
1303         case I40E_PHY_TYPE_10GBASE_KR:
1304         case I40E_PHY_TYPE_40GBASE_KR4:
1305         case I40E_PHY_TYPE_20GBASE_KR2:
1306         case I40E_PHY_TYPE_25GBASE_KR:
1307                 media = I40E_MEDIA_TYPE_BACKPLANE;
1308                 break;
1309         case I40E_PHY_TYPE_SGMII:
1310         case I40E_PHY_TYPE_XAUI:
1311         case I40E_PHY_TYPE_XFI:
1312         case I40E_PHY_TYPE_XLAUI:
1313         case I40E_PHY_TYPE_XLPPI:
1314         default:
1315                 media = I40E_MEDIA_TYPE_UNKNOWN;
1316                 break;
1317         }
1318
1319         return media;
1320 }
1321
1322 /**
1323  * i40e_poll_globr - Poll for Global Reset completion
1324  * @hw: pointer to the hardware structure
1325  * @retry_limit: how many times to retry before failure
1326  **/
1327 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1328                                              u32 retry_limit)
1329 {
1330         u32 cnt, reg = 0;
1331
1332         for (cnt = 0; cnt < retry_limit; cnt++) {
1333                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1334                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1335                         return I40E_SUCCESS;
1336                 i40e_msec_delay(100);
1337         }
1338
1339         DEBUGOUT("Global reset failed.\n");
1340         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1341
1342         return I40E_ERR_RESET_FAILED;
1343 }
1344
1345 #define I40E_PF_RESET_WAIT_COUNT        200
1346 /**
1347  * i40e_pf_reset - Reset the PF
1348  * @hw: pointer to the hardware structure
1349  *
1350  * Assuming someone else has triggered a global reset,
1351  * assure the global reset is complete and then reset the PF
1352  **/
1353 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1354 {
1355         u32 cnt = 0;
1356         u32 cnt1 = 0;
1357         u32 reg = 0;
1358         u32 grst_del;
1359
1360         /* Poll for Global Reset steady state in case of recent GRST.
1361          * The grst delay value is in 100ms units, and we'll wait a
1362          * couple counts longer to be sure we don't just miss the end.
1363          */
1364         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1365                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1366                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1367
1368         grst_del = min(grst_del * 20, 160U);
1369
1370         for (cnt = 0; cnt < grst_del; cnt++) {
1371                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1372                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1373                         break;
1374                 i40e_msec_delay(100);
1375         }
1376         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1377                 DEBUGOUT("Global reset polling failed to complete.\n");
1378                 return I40E_ERR_RESET_FAILED;
1379         }
1380
1381         /* Now Wait for the FW to be ready */
1382         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1383                 reg = rd32(hw, I40E_GLNVM_ULD);
1384                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1385                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1386                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1387                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1388                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1389                         break;
1390                 }
1391                 i40e_msec_delay(10);
1392         }
1393         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1394                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1395                 DEBUGOUT("wait for FW Reset complete timedout\n");
1396                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1397                 return I40E_ERR_RESET_FAILED;
1398         }
1399
1400         /* If there was a Global Reset in progress when we got here,
1401          * we don't need to do the PF Reset
1402          */
1403         if (!cnt) {
1404                 u32 reg2 = 0;
1405
1406                 reg = rd32(hw, I40E_PFGEN_CTRL);
1407                 wr32(hw, I40E_PFGEN_CTRL,
1408                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1409                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1410                         reg = rd32(hw, I40E_PFGEN_CTRL);
1411                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1412                                 break;
1413                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1414                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1415                                 break;
1416                         i40e_msec_delay(1);
1417                 }
1418                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1419                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1420                                 return I40E_ERR_RESET_FAILED;
1421                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1422                         DEBUGOUT("PF reset polling failed to complete.\n");
1423                         return I40E_ERR_RESET_FAILED;
1424                 }
1425         }
1426
1427         i40e_clear_pxe_mode(hw);
1428
1429
1430         return I40E_SUCCESS;
1431 }
1432
1433 /**
1434  * i40e_clear_hw - clear out any left over hw state
1435  * @hw: pointer to the hw struct
1436  *
1437  * Clear queues and interrupts, typically called at init time,
1438  * but after the capabilities have been found so we know how many
1439  * queues and msix vectors have been allocated.
1440  **/
1441 void i40e_clear_hw(struct i40e_hw *hw)
1442 {
1443         u32 num_queues, base_queue;
1444         u32 num_pf_int;
1445         u32 num_vf_int;
1446         u32 num_vfs;
1447         u32 i, j;
1448         u32 val;
1449         u32 eol = 0x7ff;
1450
1451         /* get number of interrupts, queues, and vfs */
1452         val = rd32(hw, I40E_GLPCI_CNF2);
1453         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1454                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1455         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1456                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1457
1458         val = rd32(hw, I40E_PFLAN_QALLOC);
1459         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1460                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1461         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1462                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1463         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1464                 num_queues = (j - base_queue) + 1;
1465         else
1466                 num_queues = 0;
1467
1468         val = rd32(hw, I40E_PF_VT_PFALLOC);
1469         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1470                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1471         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1472                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1473         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1474                 num_vfs = (j - i) + 1;
1475         else
1476                 num_vfs = 0;
1477
1478         /* stop all the interrupts */
1479         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1480         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1481         for (i = 0; i < num_pf_int - 2; i++)
1482                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1483
1484         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1485         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1486         wr32(hw, I40E_PFINT_LNKLST0, val);
1487         for (i = 0; i < num_pf_int - 2; i++)
1488                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1489         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1490         for (i = 0; i < num_vfs; i++)
1491                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1492         for (i = 0; i < num_vf_int - 2; i++)
1493                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1494
1495         /* warn the HW of the coming Tx disables */
1496         for (i = 0; i < num_queues; i++) {
1497                 u32 abs_queue_idx = base_queue + i;
1498                 u32 reg_block = 0;
1499
1500                 if (abs_queue_idx >= 128) {
1501                         reg_block = abs_queue_idx / 128;
1502                         abs_queue_idx %= 128;
1503                 }
1504
1505                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1506                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1507                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1508                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1509
1510                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1511         }
1512         i40e_usec_delay(400);
1513
1514         /* stop all the queues */
1515         for (i = 0; i < num_queues; i++) {
1516                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1517                 wr32(hw, I40E_QTX_ENA(i), 0);
1518                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1519                 wr32(hw, I40E_QRX_ENA(i), 0);
1520         }
1521
1522         /* short wait for all queue disables to settle */
1523         i40e_usec_delay(50);
1524 }
1525
1526 /**
1527  * i40e_clear_pxe_mode - clear pxe operations mode
1528  * @hw: pointer to the hw struct
1529  *
1530  * Make sure all PXE mode settings are cleared, including things
1531  * like descriptor fetch/write-back mode.
1532  **/
1533 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1534 {
1535         if (i40e_check_asq_alive(hw))
1536                 i40e_aq_clear_pxe_mode(hw, NULL);
1537 }
1538
1539 /**
1540  * i40e_led_is_mine - helper to find matching led
1541  * @hw: pointer to the hw struct
1542  * @idx: index into GPIO registers
1543  *
1544  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1545  */
1546 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1547 {
1548         u32 gpio_val = 0;
1549         u32 port;
1550
1551         if (!hw->func_caps.led[idx])
1552                 return 0;
1553
1554         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1555         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1556                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1557
1558         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1559          * if it is not our port then ignore
1560          */
1561         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1562             (port != hw->port))
1563                 return 0;
1564
1565         return gpio_val;
1566 }
1567
1568 #define I40E_COMBINED_ACTIVITY 0xA
1569 #define I40E_FILTER_ACTIVITY 0xE
1570 #define I40E_LINK_ACTIVITY 0xC
1571 #define I40E_MAC_ACTIVITY 0xD
1572 #define I40E_LED0 22
1573
1574 /**
1575  * i40e_led_get - return current on/off mode
1576  * @hw: pointer to the hw struct
1577  *
1578  * The value returned is the 'mode' field as defined in the
1579  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1580  * values are variations of possible behaviors relating to
1581  * blink, link, and wire.
1582  **/
1583 u32 i40e_led_get(struct i40e_hw *hw)
1584 {
1585         u32 current_mode = 0;
1586         u32 mode = 0;
1587         int i;
1588
1589         /* as per the documentation GPIO 22-29 are the LED
1590          * GPIO pins named LED0..LED7
1591          */
1592         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1593                 u32 gpio_val = i40e_led_is_mine(hw, i);
1594
1595                 if (!gpio_val)
1596                         continue;
1597
1598                 /* ignore gpio LED src mode entries related to the activity
1599                  *  LEDs
1600                  */
1601                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1602                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1603                 switch (current_mode) {
1604                 case I40E_COMBINED_ACTIVITY:
1605                 case I40E_FILTER_ACTIVITY:
1606                 case I40E_MAC_ACTIVITY:
1607                 case I40E_LINK_ACTIVITY:
1608                         continue;
1609                 default:
1610                         break;
1611                 }
1612
1613                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1614                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1615                 break;
1616         }
1617
1618         return mode;
1619 }
1620
1621 /**
1622  * i40e_led_set - set new on/off mode
1623  * @hw: pointer to the hw struct
1624  * @mode: 0=off, 0xf=on (else see manual for mode details)
1625  * @blink: true if the LED should blink when on, false if steady
1626  *
1627  * if this function is used to turn on the blink it should
1628  * be used to disable the blink when restoring the original state.
1629  **/
1630 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1631 {
1632         u32 current_mode = 0;
1633         int i;
1634
1635         if (mode & 0xfffffff0)
1636                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1637
1638         /* as per the documentation GPIO 22-29 are the LED
1639          * GPIO pins named LED0..LED7
1640          */
1641         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1642                 u32 gpio_val = i40e_led_is_mine(hw, i);
1643
1644                 if (!gpio_val)
1645                         continue;
1646
1647                 /* ignore gpio LED src mode entries related to the activity
1648                  * LEDs
1649                  */
1650                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1651                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1652                 switch (current_mode) {
1653                 case I40E_COMBINED_ACTIVITY:
1654                 case I40E_FILTER_ACTIVITY:
1655                 case I40E_MAC_ACTIVITY:
1656                 case I40E_LINK_ACTIVITY:
1657                         continue;
1658                 default:
1659                         break;
1660                 }
1661
1662                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1663                 /* this & is a bit of paranoia, but serves as a range check */
1664                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1665                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1666
1667                 if (blink)
1668                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1669                 else
1670                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1671
1672                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1673                 break;
1674         }
1675 }
1676
1677 /* Admin command wrappers */
1678
1679 /**
1680  * i40e_aq_get_phy_capabilities
1681  * @hw: pointer to the hw struct
1682  * @abilities: structure for PHY capabilities to be filled
1683  * @qualified_modules: report Qualified Modules
1684  * @report_init: report init capabilities (active are default)
1685  * @cmd_details: pointer to command details structure or NULL
1686  *
1687  * Returns the various PHY abilities supported on the Port.
1688  **/
1689 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1690                         bool qualified_modules, bool report_init,
1691                         struct i40e_aq_get_phy_abilities_resp *abilities,
1692                         struct i40e_asq_cmd_details *cmd_details)
1693 {
1694         struct i40e_aq_desc desc;
1695         enum i40e_status_code status;
1696         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1697         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1698
1699         if (!abilities)
1700                 return I40E_ERR_PARAM;
1701
1702         do {
1703                 i40e_fill_default_direct_cmd_desc(&desc,
1704                                                i40e_aqc_opc_get_phy_abilities);
1705
1706                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1707                 if (abilities_size > I40E_AQ_LARGE_BUF)
1708                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1709
1710                 if (qualified_modules)
1711                         desc.params.external.param0 |=
1712                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1713
1714                 if (report_init)
1715                         desc.params.external.param0 |=
1716                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1717
1718                 status = i40e_asq_send_command(hw, &desc, abilities,
1719                                                abilities_size, cmd_details);
1720
1721                 if (status != I40E_SUCCESS)
1722                         break;
1723
1724                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1725                         status = I40E_ERR_UNKNOWN_PHY;
1726                         break;
1727                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1728                         i40e_msec_delay(1);
1729                         total_delay++;
1730                         status = I40E_ERR_TIMEOUT;
1731                 }
1732         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1733                  (total_delay < max_delay));
1734
1735         if (status != I40E_SUCCESS)
1736                 return status;
1737
1738         if (report_init) {
1739                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1740                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1741                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1742                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1743                 } else {
1744                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1745                         hw->phy.phy_types |=
1746                                         ((u64)abilities->phy_type_ext << 32);
1747                 }
1748         }
1749
1750         return status;
1751 }
1752
1753 /**
1754  * i40e_aq_set_phy_config
1755  * @hw: pointer to the hw struct
1756  * @config: structure with PHY configuration to be set
1757  * @cmd_details: pointer to command details structure or NULL
1758  *
1759  * Set the various PHY configuration parameters
1760  * supported on the Port.One or more of the Set PHY config parameters may be
1761  * ignored in an MFP mode as the PF may not have the privilege to set some
1762  * of the PHY Config parameters. This status will be indicated by the
1763  * command response.
1764  **/
1765 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1766                                 struct i40e_aq_set_phy_config *config,
1767                                 struct i40e_asq_cmd_details *cmd_details)
1768 {
1769         struct i40e_aq_desc desc;
1770         struct i40e_aq_set_phy_config *cmd =
1771                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1772         enum i40e_status_code status;
1773
1774         if (!config)
1775                 return I40E_ERR_PARAM;
1776
1777         i40e_fill_default_direct_cmd_desc(&desc,
1778                                           i40e_aqc_opc_set_phy_config);
1779
1780         *cmd = *config;
1781
1782         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1783
1784         return status;
1785 }
1786
1787 /**
1788  * i40e_set_fc
1789  * @hw: pointer to the hw struct
1790  * @aq_failures: buffer to return AdminQ failure information
1791  * @atomic_restart: whether to enable atomic link restart
1792  *
1793  * Set the requested flow control mode using set_phy_config.
1794  **/
1795 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1796                                   bool atomic_restart)
1797 {
1798         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1799         struct i40e_aq_get_phy_abilities_resp abilities;
1800         struct i40e_aq_set_phy_config config;
1801         enum i40e_status_code status;
1802         u8 pause_mask = 0x0;
1803
1804         *aq_failures = 0x0;
1805
1806         switch (fc_mode) {
1807         case I40E_FC_FULL:
1808                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1809                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1810                 break;
1811         case I40E_FC_RX_PAUSE:
1812                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1813                 break;
1814         case I40E_FC_TX_PAUSE:
1815                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1816                 break;
1817         default:
1818                 break;
1819         }
1820
1821         /* Get the current phy config */
1822         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1823                                               NULL);
1824         if (status) {
1825                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1826                 return status;
1827         }
1828
1829         memset(&config, 0, sizeof(config));
1830         /* clear the old pause settings */
1831         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1832                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1833         /* set the new abilities */
1834         config.abilities |= pause_mask;
1835         /* If the abilities have changed, then set the new config */
1836         if (config.abilities != abilities.abilities) {
1837                 /* Auto restart link so settings take effect */
1838                 if (atomic_restart)
1839                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1840                 /* Copy over all the old settings */
1841                 config.phy_type = abilities.phy_type;
1842                 config.phy_type_ext = abilities.phy_type_ext;
1843                 config.link_speed = abilities.link_speed;
1844                 config.eee_capability = abilities.eee_capability;
1845                 config.eeer = abilities.eeer_val;
1846                 config.low_power_ctrl = abilities.d3_lpan;
1847                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1848                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1849                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1850
1851                 if (status)
1852                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1853         }
1854         /* Update the link info */
1855         status = i40e_update_link_info(hw);
1856         if (status) {
1857                 /* Wait a little bit (on 40G cards it sometimes takes a really
1858                  * long time for link to come back from the atomic reset)
1859                  * and try once more
1860                  */
1861                 i40e_msec_delay(1000);
1862                 status = i40e_update_link_info(hw);
1863         }
1864         if (status)
1865                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1866
1867         return status;
1868 }
1869
1870 /**
1871  * i40e_aq_set_mac_config
1872  * @hw: pointer to the hw struct
1873  * @max_frame_size: Maximum Frame Size to be supported by the port
1874  * @crc_en: Tell HW to append a CRC to outgoing frames
1875  * @pacing: Pacing configurations
1876  * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1877  * @cmd_details: pointer to command details structure or NULL
1878  *
1879  * Configure MAC settings for frame size, jumbo frame support and the
1880  * addition of a CRC by the hardware.
1881  **/
1882 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1883                                 u16 max_frame_size,
1884                                 bool crc_en, u16 pacing,
1885                                 bool auto_drop_blocking_packets,
1886                                 struct i40e_asq_cmd_details *cmd_details)
1887 {
1888         struct i40e_aq_desc desc;
1889         struct i40e_aq_set_mac_config *cmd =
1890                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1891         enum i40e_status_code status;
1892
1893         if (max_frame_size == 0)
1894                 return I40E_ERR_PARAM;
1895
1896         i40e_fill_default_direct_cmd_desc(&desc,
1897                                           i40e_aqc_opc_set_mac_config);
1898
1899         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1900         cmd->params = ((u8)pacing & 0x0F) << 3;
1901         if (crc_en)
1902                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1903
1904         if (auto_drop_blocking_packets) {
1905                 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1906                         cmd->params |=
1907                                 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1908                 else
1909                         i40e_debug(hw, I40E_DEBUG_ALL,
1910                                    "This FW api version does not support drop mode.\n");
1911         }
1912
1913 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1914         cmd->fc_refresh_threshold =
1915                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1916
1917         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1918
1919         return status;
1920 }
1921
1922 /**
1923  * i40e_aq_clear_pxe_mode
1924  * @hw: pointer to the hw struct
1925  * @cmd_details: pointer to command details structure or NULL
1926  *
1927  * Tell the firmware that the driver is taking over from PXE
1928  **/
1929 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1930                         struct i40e_asq_cmd_details *cmd_details)
1931 {
1932         enum i40e_status_code status;
1933         struct i40e_aq_desc desc;
1934         struct i40e_aqc_clear_pxe *cmd =
1935                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1936
1937         i40e_fill_default_direct_cmd_desc(&desc,
1938                                           i40e_aqc_opc_clear_pxe_mode);
1939
1940         cmd->rx_cnt = 0x2;
1941
1942         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1943
1944         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1945
1946         return status;
1947 }
1948
1949 /**
1950  * i40e_aq_set_link_restart_an
1951  * @hw: pointer to the hw struct
1952  * @enable_link: if true: enable link, if false: disable link
1953  * @cmd_details: pointer to command details structure or NULL
1954  *
1955  * Sets up the link and restarts the Auto-Negotiation over the link.
1956  **/
1957 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1958                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1959 {
1960         struct i40e_aq_desc desc;
1961         struct i40e_aqc_set_link_restart_an *cmd =
1962                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1963         enum i40e_status_code status;
1964
1965         i40e_fill_default_direct_cmd_desc(&desc,
1966                                           i40e_aqc_opc_set_link_restart_an);
1967
1968         cmd->command = I40E_AQ_PHY_RESTART_AN;
1969         if (enable_link)
1970                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1971         else
1972                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1973
1974         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1975
1976         return status;
1977 }
1978
1979 /**
1980  * i40e_aq_get_link_info
1981  * @hw: pointer to the hw struct
1982  * @enable_lse: enable/disable LinkStatusEvent reporting
1983  * @link: pointer to link status structure - optional
1984  * @cmd_details: pointer to command details structure or NULL
1985  *
1986  * Returns the link status of the adapter.
1987  **/
1988 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1989                                 bool enable_lse, struct i40e_link_status *link,
1990                                 struct i40e_asq_cmd_details *cmd_details)
1991 {
1992         struct i40e_aq_desc desc;
1993         struct i40e_aqc_get_link_status *resp =
1994                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1995         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1996         enum i40e_status_code status;
1997         bool tx_pause, rx_pause;
1998         u16 command_flags;
1999
2000         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2001
2002         if (enable_lse)
2003                 command_flags = I40E_AQ_LSE_ENABLE;
2004         else
2005                 command_flags = I40E_AQ_LSE_DISABLE;
2006         resp->command_flags = CPU_TO_LE16(command_flags);
2007
2008         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2009
2010         if (status != I40E_SUCCESS)
2011                 goto aq_get_link_info_exit;
2012
2013         /* save off old link status information */
2014         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2015                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2016
2017         /* update link status */
2018         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2019         hw->phy.media_type = i40e_get_media_type(hw);
2020         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2021         hw_link_info->link_info = resp->link_info;
2022         hw_link_info->an_info = resp->an_info;
2023         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2024                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
2025         hw_link_info->ext_info = resp->ext_info;
2026         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2027         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2028         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2029
2030         /* update fc info */
2031         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2032         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2033         if (tx_pause & rx_pause)
2034                 hw->fc.current_mode = I40E_FC_FULL;
2035         else if (tx_pause)
2036                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2037         else if (rx_pause)
2038                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2039         else
2040                 hw->fc.current_mode = I40E_FC_NONE;
2041
2042         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2043                 hw_link_info->crc_enable = true;
2044         else
2045                 hw_link_info->crc_enable = false;
2046
2047         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2048                 hw_link_info->lse_enable = true;
2049         else
2050                 hw_link_info->lse_enable = false;
2051
2052         if ((hw->mac.type == I40E_MAC_XL710) &&
2053             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2054              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2055                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2056
2057         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2058             hw->mac.type != I40E_MAC_X722) {
2059                 __le32 tmp;
2060
2061                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2062                             I40E_NONDMA_TO_NONDMA);
2063                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2064                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2065         }
2066
2067         /* save link status information */
2068         if (link)
2069                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2070                             I40E_NONDMA_TO_NONDMA);
2071
2072         /* flag cleared so helper functions don't call AQ again */
2073         hw->phy.get_link_info = false;
2074
2075 aq_get_link_info_exit:
2076         return status;
2077 }
2078
2079 /**
2080  * i40e_aq_set_phy_int_mask
2081  * @hw: pointer to the hw struct
2082  * @mask: interrupt mask to be set
2083  * @cmd_details: pointer to command details structure or NULL
2084  *
2085  * Set link interrupt mask.
2086  **/
2087 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2088                                 u16 mask,
2089                                 struct i40e_asq_cmd_details *cmd_details)
2090 {
2091         struct i40e_aq_desc desc;
2092         struct i40e_aqc_set_phy_int_mask *cmd =
2093                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2094         enum i40e_status_code status;
2095
2096         i40e_fill_default_direct_cmd_desc(&desc,
2097                                           i40e_aqc_opc_set_phy_int_mask);
2098
2099         cmd->event_mask = CPU_TO_LE16(mask);
2100
2101         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2102
2103         return status;
2104 }
2105
2106 /**
2107  * i40e_aq_get_local_advt_reg
2108  * @hw: pointer to the hw struct
2109  * @advt_reg: local AN advertisement register value
2110  * @cmd_details: pointer to command details structure or NULL
2111  *
2112  * Get the Local AN advertisement register value.
2113  **/
2114 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2115                                 u64 *advt_reg,
2116                                 struct i40e_asq_cmd_details *cmd_details)
2117 {
2118         struct i40e_aq_desc desc;
2119         struct i40e_aqc_an_advt_reg *resp =
2120                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2121         enum i40e_status_code status;
2122
2123         i40e_fill_default_direct_cmd_desc(&desc,
2124                                           i40e_aqc_opc_get_local_advt_reg);
2125
2126         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2127
2128         if (status != I40E_SUCCESS)
2129                 goto aq_get_local_advt_reg_exit;
2130
2131         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2132         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2133
2134 aq_get_local_advt_reg_exit:
2135         return status;
2136 }
2137
2138 /**
2139  * i40e_aq_set_local_advt_reg
2140  * @hw: pointer to the hw struct
2141  * @advt_reg: local AN advertisement register value
2142  * @cmd_details: pointer to command details structure or NULL
2143  *
2144  * Get the Local AN advertisement register value.
2145  **/
2146 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2147                                 u64 advt_reg,
2148                                 struct i40e_asq_cmd_details *cmd_details)
2149 {
2150         struct i40e_aq_desc desc;
2151         struct i40e_aqc_an_advt_reg *cmd =
2152                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2153         enum i40e_status_code status;
2154
2155         i40e_fill_default_direct_cmd_desc(&desc,
2156                                           i40e_aqc_opc_get_local_advt_reg);
2157
2158         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2159         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2160
2161         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2162
2163         return status;
2164 }
2165
2166 /**
2167  * i40e_aq_get_partner_advt
2168  * @hw: pointer to the hw struct
2169  * @advt_reg: AN partner advertisement register value
2170  * @cmd_details: pointer to command details structure or NULL
2171  *
2172  * Get the link partner AN advertisement register value.
2173  **/
2174 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2175                                 u64 *advt_reg,
2176                                 struct i40e_asq_cmd_details *cmd_details)
2177 {
2178         struct i40e_aq_desc desc;
2179         struct i40e_aqc_an_advt_reg *resp =
2180                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2181         enum i40e_status_code status;
2182
2183         i40e_fill_default_direct_cmd_desc(&desc,
2184                                           i40e_aqc_opc_get_partner_advt);
2185
2186         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2187
2188         if (status != I40E_SUCCESS)
2189                 goto aq_get_partner_advt_exit;
2190
2191         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2192         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2193
2194 aq_get_partner_advt_exit:
2195         return status;
2196 }
2197
2198 /**
2199  * i40e_aq_set_lb_modes
2200  * @hw: pointer to the hw struct
2201  * @lb_modes: loopback mode to be set
2202  * @cmd_details: pointer to command details structure or NULL
2203  *
2204  * Sets loopback modes.
2205  **/
2206 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2207                                 u16 lb_modes,
2208                                 struct i40e_asq_cmd_details *cmd_details)
2209 {
2210         struct i40e_aq_desc desc;
2211         struct i40e_aqc_set_lb_mode *cmd =
2212                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2213         enum i40e_status_code status;
2214
2215         i40e_fill_default_direct_cmd_desc(&desc,
2216                                           i40e_aqc_opc_set_lb_modes);
2217
2218         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2219
2220         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2221
2222         return status;
2223 }
2224
2225 /**
2226  * i40e_aq_set_phy_debug
2227  * @hw: pointer to the hw struct
2228  * @cmd_flags: debug command flags
2229  * @cmd_details: pointer to command details structure or NULL
2230  *
2231  * Reset the external PHY.
2232  **/
2233 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2234                                 struct i40e_asq_cmd_details *cmd_details)
2235 {
2236         struct i40e_aq_desc desc;
2237         struct i40e_aqc_set_phy_debug *cmd =
2238                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2239         enum i40e_status_code status;
2240
2241         i40e_fill_default_direct_cmd_desc(&desc,
2242                                           i40e_aqc_opc_set_phy_debug);
2243
2244         cmd->command_flags = cmd_flags;
2245
2246         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2247
2248         return status;
2249 }
2250
2251 /**
2252  * i40e_aq_add_vsi
2253  * @hw: pointer to the hw struct
2254  * @vsi_ctx: pointer to a vsi context struct
2255  * @cmd_details: pointer to command details structure or NULL
2256  *
2257  * Add a VSI context to the hardware.
2258 **/
2259 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2260                                 struct i40e_vsi_context *vsi_ctx,
2261                                 struct i40e_asq_cmd_details *cmd_details)
2262 {
2263         struct i40e_aq_desc desc;
2264         struct i40e_aqc_add_get_update_vsi *cmd =
2265                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2266         struct i40e_aqc_add_get_update_vsi_completion *resp =
2267                 (struct i40e_aqc_add_get_update_vsi_completion *)
2268                 &desc.params.raw;
2269         enum i40e_status_code status;
2270
2271         i40e_fill_default_direct_cmd_desc(&desc,
2272                                           i40e_aqc_opc_add_vsi);
2273
2274         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2275         cmd->connection_type = vsi_ctx->connection_type;
2276         cmd->vf_id = vsi_ctx->vf_num;
2277         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2278
2279         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2280
2281         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2282                                     sizeof(vsi_ctx->info), cmd_details);
2283
2284         if (status != I40E_SUCCESS)
2285                 goto aq_add_vsi_exit;
2286
2287         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2288         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2289         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2290         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2291
2292 aq_add_vsi_exit:
2293         return status;
2294 }
2295
2296 /**
2297  * i40e_aq_set_default_vsi
2298  * @hw: pointer to the hw struct
2299  * @seid: vsi number
2300  * @cmd_details: pointer to command details structure or NULL
2301  **/
2302 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2303                                 u16 seid,
2304                                 struct i40e_asq_cmd_details *cmd_details)
2305 {
2306         struct i40e_aq_desc desc;
2307         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2308                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2309                 &desc.params.raw;
2310         enum i40e_status_code status;
2311
2312         i40e_fill_default_direct_cmd_desc(&desc,
2313                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2314
2315         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2316         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2317         cmd->seid = CPU_TO_LE16(seid);
2318
2319         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2320
2321         return status;
2322 }
2323
2324 /**
2325  * i40e_aq_clear_default_vsi
2326  * @hw: pointer to the hw struct
2327  * @seid: vsi number
2328  * @cmd_details: pointer to command details structure or NULL
2329  **/
2330 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2331                                 u16 seid,
2332                                 struct i40e_asq_cmd_details *cmd_details)
2333 {
2334         struct i40e_aq_desc desc;
2335         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2336                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2337                 &desc.params.raw;
2338         enum i40e_status_code status;
2339
2340         i40e_fill_default_direct_cmd_desc(&desc,
2341                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2342
2343         cmd->promiscuous_flags = CPU_TO_LE16(0);
2344         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2345         cmd->seid = CPU_TO_LE16(seid);
2346
2347         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2348
2349         return status;
2350 }
2351
2352 /**
2353  * i40e_aq_set_vsi_unicast_promiscuous
2354  * @hw: pointer to the hw struct
2355  * @seid: vsi number
2356  * @set: set unicast promiscuous enable/disable
2357  * @cmd_details: pointer to command details structure or NULL
2358  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2359  **/
2360 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2361                                 u16 seid, bool set,
2362                                 struct i40e_asq_cmd_details *cmd_details,
2363                                 bool rx_only_promisc)
2364 {
2365         struct i40e_aq_desc desc;
2366         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2367                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2368         enum i40e_status_code status;
2369         u16 flags = 0;
2370
2371         i40e_fill_default_direct_cmd_desc(&desc,
2372                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2373
2374         if (set) {
2375                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2376                 if (rx_only_promisc &&
2377                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2378                      (hw->aq.api_maj_ver > 1)))
2379                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2380         }
2381
2382         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2383
2384         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2385         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2386              (hw->aq.api_maj_ver > 1))
2387                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2388
2389         cmd->seid = CPU_TO_LE16(seid);
2390         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2391
2392         return status;
2393 }
2394
2395 /**
2396  * i40e_aq_set_vsi_multicast_promiscuous
2397  * @hw: pointer to the hw struct
2398  * @seid: vsi number
2399  * @set: set multicast promiscuous enable/disable
2400  * @cmd_details: pointer to command details structure or NULL
2401  **/
2402 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2403                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2404 {
2405         struct i40e_aq_desc desc;
2406         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2407                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2408         enum i40e_status_code status;
2409         u16 flags = 0;
2410
2411         i40e_fill_default_direct_cmd_desc(&desc,
2412                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2413
2414         if (set)
2415                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2416
2417         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2418
2419         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2420
2421         cmd->seid = CPU_TO_LE16(seid);
2422         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2423
2424         return status;
2425 }
2426
2427 /**
2428 * i40e_aq_set_vsi_full_promiscuous
2429 * @hw: pointer to the hw struct
2430 * @seid: VSI number
2431 * @set: set promiscuous enable/disable
2432 * @cmd_details: pointer to command details structure or NULL
2433 **/
2434 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2435                                 u16 seid, bool set,
2436                                 struct i40e_asq_cmd_details *cmd_details)
2437 {
2438         struct i40e_aq_desc desc;
2439         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2440                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2441         enum i40e_status_code status;
2442         u16 flags = 0;
2443
2444         i40e_fill_default_direct_cmd_desc(&desc,
2445                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2446
2447         if (set)
2448                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2449                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2450                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2451
2452         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2453
2454         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2455                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2456                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2457
2458         cmd->seid = CPU_TO_LE16(seid);
2459         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2460
2461         return status;
2462 }
2463
2464 /**
2465  * i40e_aq_set_vsi_mc_promisc_on_vlan
2466  * @hw: pointer to the hw struct
2467  * @seid: vsi number
2468  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2469  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2470  * @cmd_details: pointer to command details structure or NULL
2471  **/
2472 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2473                                 u16 seid, bool enable, u16 vid,
2474                                 struct i40e_asq_cmd_details *cmd_details)
2475 {
2476         struct i40e_aq_desc desc;
2477         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2478                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2479         enum i40e_status_code status;
2480         u16 flags = 0;
2481
2482         i40e_fill_default_direct_cmd_desc(&desc,
2483                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2484
2485         if (enable)
2486                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2487
2488         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2489         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2490         cmd->seid = CPU_TO_LE16(seid);
2491         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2492
2493         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2494
2495         return status;
2496 }
2497
2498 /**
2499  * i40e_aq_set_vsi_uc_promisc_on_vlan
2500  * @hw: pointer to the hw struct
2501  * @seid: vsi number
2502  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2503  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2504  * @cmd_details: pointer to command details structure or NULL
2505  **/
2506 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2507                                 u16 seid, bool enable, u16 vid,
2508                                 struct i40e_asq_cmd_details *cmd_details)
2509 {
2510         struct i40e_aq_desc desc;
2511         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2512                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2513         enum i40e_status_code status;
2514         u16 flags = 0;
2515
2516         i40e_fill_default_direct_cmd_desc(&desc,
2517                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2518
2519         if (enable)
2520                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2521
2522         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2523         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2524         cmd->seid = CPU_TO_LE16(seid);
2525         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2526
2527         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2528
2529         return status;
2530 }
2531
2532 /**
2533  * i40e_aq_set_vsi_bc_promisc_on_vlan
2534  * @hw: pointer to the hw struct
2535  * @seid: vsi number
2536  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2537  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2538  * @cmd_details: pointer to command details structure or NULL
2539  **/
2540 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2541                                 u16 seid, bool enable, u16 vid,
2542                                 struct i40e_asq_cmd_details *cmd_details)
2543 {
2544         struct i40e_aq_desc desc;
2545         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2546                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2547         enum i40e_status_code status;
2548         u16 flags = 0;
2549
2550         i40e_fill_default_direct_cmd_desc(&desc,
2551                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2552
2553         if (enable)
2554                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2555
2556         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2557         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2558         cmd->seid = CPU_TO_LE16(seid);
2559         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2560
2561         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2562
2563         return status;
2564 }
2565
2566 /**
2567  * i40e_aq_set_vsi_broadcast
2568  * @hw: pointer to the hw struct
2569  * @seid: vsi number
2570  * @set_filter: true to set filter, false to clear filter
2571  * @cmd_details: pointer to command details structure or NULL
2572  *
2573  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2574  **/
2575 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2576                                 u16 seid, bool set_filter,
2577                                 struct i40e_asq_cmd_details *cmd_details)
2578 {
2579         struct i40e_aq_desc desc;
2580         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2581                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2582         enum i40e_status_code status;
2583
2584         i40e_fill_default_direct_cmd_desc(&desc,
2585                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2586
2587         if (set_filter)
2588                 cmd->promiscuous_flags
2589                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2590         else
2591                 cmd->promiscuous_flags
2592                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2593
2594         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2595         cmd->seid = CPU_TO_LE16(seid);
2596         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2597
2598         return status;
2599 }
2600
2601 /**
2602  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2603  * @hw: pointer to the hw struct
2604  * @seid: vsi number
2605  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2606  * @cmd_details: pointer to command details structure or NULL
2607  **/
2608 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2609                                 u16 seid, bool enable,
2610                                 struct i40e_asq_cmd_details *cmd_details)
2611 {
2612         struct i40e_aq_desc desc;
2613         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2614                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2615         enum i40e_status_code status;
2616         u16 flags = 0;
2617
2618         i40e_fill_default_direct_cmd_desc(&desc,
2619                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2620         if (enable)
2621                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2622
2623         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2624         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2625         cmd->seid = CPU_TO_LE16(seid);
2626
2627         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2628
2629         return status;
2630 }
2631
2632 /**
2633  * i40e_get_vsi_params - get VSI configuration info
2634  * @hw: pointer to the hw struct
2635  * @vsi_ctx: pointer to a vsi context struct
2636  * @cmd_details: pointer to command details structure or NULL
2637  **/
2638 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2639                                 struct i40e_vsi_context *vsi_ctx,
2640                                 struct i40e_asq_cmd_details *cmd_details)
2641 {
2642         struct i40e_aq_desc desc;
2643         struct i40e_aqc_add_get_update_vsi *cmd =
2644                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2645         struct i40e_aqc_add_get_update_vsi_completion *resp =
2646                 (struct i40e_aqc_add_get_update_vsi_completion *)
2647                 &desc.params.raw;
2648         enum i40e_status_code status;
2649
2650         UNREFERENCED_1PARAMETER(cmd_details);
2651         i40e_fill_default_direct_cmd_desc(&desc,
2652                                           i40e_aqc_opc_get_vsi_parameters);
2653
2654         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2655
2656         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2657
2658         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2659                                     sizeof(vsi_ctx->info), NULL);
2660
2661         if (status != I40E_SUCCESS)
2662                 goto aq_get_vsi_params_exit;
2663
2664         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2665         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2666         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2667         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2668
2669 aq_get_vsi_params_exit:
2670         return status;
2671 }
2672
2673 /**
2674  * i40e_aq_update_vsi_params
2675  * @hw: pointer to the hw struct
2676  * @vsi_ctx: pointer to a vsi context struct
2677  * @cmd_details: pointer to command details structure or NULL
2678  *
2679  * Update a VSI context.
2680  **/
2681 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2682                                 struct i40e_vsi_context *vsi_ctx,
2683                                 struct i40e_asq_cmd_details *cmd_details)
2684 {
2685         struct i40e_aq_desc desc;
2686         struct i40e_aqc_add_get_update_vsi *cmd =
2687                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2688         struct i40e_aqc_add_get_update_vsi_completion *resp =
2689                 (struct i40e_aqc_add_get_update_vsi_completion *)
2690                 &desc.params.raw;
2691         enum i40e_status_code status;
2692
2693         i40e_fill_default_direct_cmd_desc(&desc,
2694                                           i40e_aqc_opc_update_vsi_parameters);
2695         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2696
2697         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2698
2699         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2700                                     sizeof(vsi_ctx->info), cmd_details);
2701
2702         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2703         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2704
2705         return status;
2706 }
2707
2708 /**
2709  * i40e_aq_get_switch_config
2710  * @hw: pointer to the hardware structure
2711  * @buf: pointer to the result buffer
2712  * @buf_size: length of input buffer
2713  * @start_seid: seid to start for the report, 0 == beginning
2714  * @cmd_details: pointer to command details structure or NULL
2715  *
2716  * Fill the buf with switch configuration returned from AdminQ command
2717  **/
2718 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2719                                 struct i40e_aqc_get_switch_config_resp *buf,
2720                                 u16 buf_size, u16 *start_seid,
2721                                 struct i40e_asq_cmd_details *cmd_details)
2722 {
2723         struct i40e_aq_desc desc;
2724         struct i40e_aqc_switch_seid *scfg =
2725                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2726         enum i40e_status_code status;
2727
2728         i40e_fill_default_direct_cmd_desc(&desc,
2729                                           i40e_aqc_opc_get_switch_config);
2730         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2731         if (buf_size > I40E_AQ_LARGE_BUF)
2732                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2733         scfg->seid = CPU_TO_LE16(*start_seid);
2734
2735         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2736         *start_seid = LE16_TO_CPU(scfg->seid);
2737
2738         return status;
2739 }
2740
2741 /**
2742  * i40e_aq_set_switch_config
2743  * @hw: pointer to the hardware structure
2744  * @flags: bit flag values to set
2745  * @mode: cloud filter mode
2746  * @valid_flags: which bit flags to set
2747  * @cmd_details: pointer to command details structure or NULL
2748  *
2749  * Set switch configuration bits
2750  **/
2751 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2752                                 u16 flags, u16 valid_flags, u8 mode,
2753                                 struct i40e_asq_cmd_details *cmd_details)
2754 {
2755         struct i40e_aq_desc desc;
2756         struct i40e_aqc_set_switch_config *scfg =
2757                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2758         enum i40e_status_code status;
2759
2760         i40e_fill_default_direct_cmd_desc(&desc,
2761                                           i40e_aqc_opc_set_switch_config);
2762         scfg->flags = CPU_TO_LE16(flags);
2763         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2764         scfg->mode = mode;
2765         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2766                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2767                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2768                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2769         }
2770         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2771
2772         return status;
2773 }
2774
2775 /**
2776  * i40e_aq_get_firmware_version
2777  * @hw: pointer to the hw struct
2778  * @fw_major_version: firmware major version
2779  * @fw_minor_version: firmware minor version
2780  * @fw_build: firmware build number
2781  * @api_major_version: major queue version
2782  * @api_minor_version: minor queue version
2783  * @cmd_details: pointer to command details structure or NULL
2784  *
2785  * Get the firmware version from the admin queue commands
2786  **/
2787 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2788                                 u16 *fw_major_version, u16 *fw_minor_version,
2789                                 u32 *fw_build,
2790                                 u16 *api_major_version, u16 *api_minor_version,
2791                                 struct i40e_asq_cmd_details *cmd_details)
2792 {
2793         struct i40e_aq_desc desc;
2794         struct i40e_aqc_get_version *resp =
2795                 (struct i40e_aqc_get_version *)&desc.params.raw;
2796         enum i40e_status_code status;
2797
2798         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2799
2800         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2801
2802         if (status == I40E_SUCCESS) {
2803                 if (fw_major_version != NULL)
2804                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2805                 if (fw_minor_version != NULL)
2806                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2807                 if (fw_build != NULL)
2808                         *fw_build = LE32_TO_CPU(resp->fw_build);
2809                 if (api_major_version != NULL)
2810                         *api_major_version = LE16_TO_CPU(resp->api_major);
2811                 if (api_minor_version != NULL)
2812                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2813
2814                 /* A workaround to fix the API version in SW */
2815                 if (api_major_version && api_minor_version &&
2816                     fw_major_version && fw_minor_version &&
2817                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2818                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2819                      (*fw_major_version > 4)))
2820                         *api_minor_version = 2;
2821         }
2822
2823         return status;
2824 }
2825
2826 /**
2827  * i40e_aq_send_driver_version
2828  * @hw: pointer to the hw struct
2829  * @dv: driver's major, minor version
2830  * @cmd_details: pointer to command details structure or NULL
2831  *
2832  * Send the driver version to the firmware
2833  **/
2834 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2835                                 struct i40e_driver_version *dv,
2836                                 struct i40e_asq_cmd_details *cmd_details)
2837 {
2838         struct i40e_aq_desc desc;
2839         struct i40e_aqc_driver_version *cmd =
2840                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2841         enum i40e_status_code status;
2842         u16 len;
2843
2844         if (dv == NULL)
2845                 return I40E_ERR_PARAM;
2846
2847         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2848
2849         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2850         cmd->driver_major_ver = dv->major_version;
2851         cmd->driver_minor_ver = dv->minor_version;
2852         cmd->driver_build_ver = dv->build_version;
2853         cmd->driver_subbuild_ver = dv->subbuild_version;
2854
2855         len = 0;
2856         while (len < sizeof(dv->driver_string) &&
2857                (dv->driver_string[len] < 0x80) &&
2858                dv->driver_string[len])
2859                 len++;
2860         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2861                                        len, cmd_details);
2862
2863         return status;
2864 }
2865
2866 /**
2867  * i40e_get_link_status - get status of the HW network link
2868  * @hw: pointer to the hw struct
2869  * @link_up: pointer to bool (true/false = linkup/linkdown)
2870  *
2871  * Variable link_up true if link is up, false if link is down.
2872  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2873  *
2874  * Side effect: LinkStatusEvent reporting becomes enabled
2875  **/
2876 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2877 {
2878         enum i40e_status_code status = I40E_SUCCESS;
2879
2880         if (hw->phy.get_link_info) {
2881                 status = i40e_update_link_info(hw);
2882
2883                 if (status != I40E_SUCCESS)
2884                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2885                                    status);
2886         }
2887
2888         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2889
2890         return status;
2891 }
2892
2893 /**
2894  * i40e_updatelink_status - update status of the HW network link
2895  * @hw: pointer to the hw struct
2896  **/
2897 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2898 {
2899         struct i40e_aq_get_phy_abilities_resp abilities;
2900         enum i40e_status_code status = I40E_SUCCESS;
2901
2902         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2903         if (status)
2904                 return status;
2905
2906         /* extra checking needed to ensure link info to user is timely */
2907         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2908             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2909              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2910                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2911                                                       &abilities, NULL);
2912                 if (status)
2913                         return status;
2914
2915                 hw->phy.link_info.req_fec_info =
2916                         abilities.fec_cfg_curr_mod_ext_info &
2917                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2918
2919                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2920                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2921         }
2922         return status;
2923 }
2924
2925
2926 /**
2927  * i40e_get_link_speed
2928  * @hw: pointer to the hw struct
2929  *
2930  * Returns the link speed of the adapter.
2931  **/
2932 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2933 {
2934         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2935         enum i40e_status_code status = I40E_SUCCESS;
2936
2937         if (hw->phy.get_link_info) {
2938                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2939
2940                 if (status != I40E_SUCCESS)
2941                         goto i40e_link_speed_exit;
2942         }
2943
2944         speed = hw->phy.link_info.link_speed;
2945
2946 i40e_link_speed_exit:
2947         return speed;
2948 }
2949
2950 /**
2951  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2952  * @hw: pointer to the hw struct
2953  * @uplink_seid: the MAC or other gizmo SEID
2954  * @downlink_seid: the VSI SEID
2955  * @enabled_tc: bitmap of TCs to be enabled
2956  * @default_port: true for default port VSI, false for control port
2957  * @veb_seid: pointer to where to put the resulting VEB SEID
2958  * @enable_stats: true to turn on VEB stats
2959  * @cmd_details: pointer to command details structure or NULL
2960  *
2961  * This asks the FW to add a VEB between the uplink and downlink
2962  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2963  **/
2964 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2965                                 u16 downlink_seid, u8 enabled_tc,
2966                                 bool default_port, u16 *veb_seid,
2967                                 bool enable_stats,
2968                                 struct i40e_asq_cmd_details *cmd_details)
2969 {
2970         struct i40e_aq_desc desc;
2971         struct i40e_aqc_add_veb *cmd =
2972                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2973         struct i40e_aqc_add_veb_completion *resp =
2974                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2975         enum i40e_status_code status;
2976         u16 veb_flags = 0;
2977
2978         /* SEIDs need to either both be set or both be 0 for floating VEB */
2979         if (!!uplink_seid != !!downlink_seid)
2980                 return I40E_ERR_PARAM;
2981
2982         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2983
2984         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2985         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2986         cmd->enable_tcs = enabled_tc;
2987         if (!uplink_seid)
2988                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2989         if (default_port)
2990                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2991         else
2992                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2993
2994         /* reverse logic here: set the bitflag to disable the stats */
2995         if (!enable_stats)
2996                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2997
2998         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2999
3000         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3001
3002         if (!status && veb_seid)
3003                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
3004
3005         return status;
3006 }
3007
3008 /**
3009  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
3010  * @hw: pointer to the hw struct
3011  * @veb_seid: the SEID of the VEB to query
3012  * @switch_id: the uplink switch id
3013  * @floating: set to true if the VEB is floating
3014  * @statistic_index: index of the stats counter block for this VEB
3015  * @vebs_used: number of VEB's used by function
3016  * @vebs_free: total VEB's not reserved by any function
3017  * @cmd_details: pointer to command details structure or NULL
3018  *
3019  * This retrieves the parameters for a particular VEB, specified by
3020  * uplink_seid, and returns them to the caller.
3021  **/
3022 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3023                                 u16 veb_seid, u16 *switch_id,
3024                                 bool *floating, u16 *statistic_index,
3025                                 u16 *vebs_used, u16 *vebs_free,
3026                                 struct i40e_asq_cmd_details *cmd_details)
3027 {
3028         struct i40e_aq_desc desc;
3029         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3030                 (struct i40e_aqc_get_veb_parameters_completion *)
3031                 &desc.params.raw;
3032         enum i40e_status_code status;
3033
3034         if (veb_seid == 0)
3035                 return I40E_ERR_PARAM;
3036
3037         i40e_fill_default_direct_cmd_desc(&desc,
3038                                           i40e_aqc_opc_get_veb_parameters);
3039         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3040
3041         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3042         if (status)
3043                 goto get_veb_exit;
3044
3045         if (switch_id)
3046                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3047         if (statistic_index)
3048                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3049         if (vebs_used)
3050                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3051         if (vebs_free)
3052                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3053         if (floating) {
3054                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3055
3056                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3057                         *floating = true;
3058                 else
3059                         *floating = false;
3060         }
3061
3062 get_veb_exit:
3063         return status;
3064 }
3065
3066 /**
3067  * i40e_aq_add_macvlan
3068  * @hw: pointer to the hw struct
3069  * @seid: VSI for the mac address
3070  * @mv_list: list of macvlans to be added
3071  * @count: length of the list
3072  * @cmd_details: pointer to command details structure or NULL
3073  *
3074  * Add MAC/VLAN addresses to the HW filtering
3075  **/
3076 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3077                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3078                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3079 {
3080         struct i40e_aq_desc desc;
3081         struct i40e_aqc_macvlan *cmd =
3082                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3083         enum i40e_status_code status;
3084         u16 buf_size;
3085         int i;
3086
3087         if (count == 0 || !mv_list || !hw)
3088                 return I40E_ERR_PARAM;
3089
3090         buf_size = count * sizeof(*mv_list);
3091
3092         /* prep the rest of the request */
3093         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3094         cmd->num_addresses = CPU_TO_LE16(count);
3095         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3096         cmd->seid[1] = 0;
3097         cmd->seid[2] = 0;
3098
3099         for (i = 0; i < count; i++)
3100                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3101                         mv_list[i].flags |=
3102                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3103
3104         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3105         if (buf_size > I40E_AQ_LARGE_BUF)
3106                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3107
3108         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3109                                        cmd_details);
3110
3111         return status;
3112 }
3113
3114 /**
3115  * i40e_aq_remove_macvlan
3116  * @hw: pointer to the hw struct
3117  * @seid: VSI for the mac address
3118  * @mv_list: list of macvlans to be removed
3119  * @count: length of the list
3120  * @cmd_details: pointer to command details structure or NULL
3121  *
3122  * Remove MAC/VLAN addresses from the HW filtering
3123  **/
3124 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3125                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3126                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3127 {
3128         struct i40e_aq_desc desc;
3129         struct i40e_aqc_macvlan *cmd =
3130                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3131         enum i40e_status_code status;
3132         u16 buf_size;
3133
3134         if (count == 0 || !mv_list || !hw)
3135                 return I40E_ERR_PARAM;
3136
3137         buf_size = count * sizeof(*mv_list);
3138
3139         /* prep the rest of the request */
3140         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3141         cmd->num_addresses = CPU_TO_LE16(count);
3142         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3143         cmd->seid[1] = 0;
3144         cmd->seid[2] = 0;
3145
3146         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3147         if (buf_size > I40E_AQ_LARGE_BUF)
3148                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3149
3150         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3151                                        cmd_details);
3152
3153         return status;
3154 }
3155
3156 /**
3157  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3158  * @hw: pointer to the hw struct
3159  * @opcode: AQ opcode for add or delete mirror rule
3160  * @sw_seid: Switch SEID (to which rule refers)
3161  * @rule_type: Rule Type (ingress/egress/VLAN)
3162  * @id: Destination VSI SEID or Rule ID
3163  * @count: length of the list
3164  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3165  * @cmd_details: pointer to command details structure or NULL
3166  * @rule_id: Rule ID returned from FW
3167  * @rules_used: Number of rules used in internal switch
3168  * @rules_free: Number of rules free in internal switch
3169  *
3170  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3171  * VEBs/VEPA elements only
3172  **/
3173 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3174                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3175                         u16 count, __le16 *mr_list,
3176                         struct i40e_asq_cmd_details *cmd_details,
3177                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3178 {
3179         struct i40e_aq_desc desc;
3180         struct i40e_aqc_add_delete_mirror_rule *cmd =
3181                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3182         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3183         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3184         enum i40e_status_code status;
3185         u16 buf_size;
3186
3187         buf_size = count * sizeof(*mr_list);
3188
3189         /* prep the rest of the request */
3190         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3191         cmd->seid = CPU_TO_LE16(sw_seid);
3192         cmd->rule_type = CPU_TO_LE16(rule_type &
3193                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3194         cmd->num_entries = CPU_TO_LE16(count);
3195         /* Dest VSI for add, rule_id for delete */
3196         cmd->destination = CPU_TO_LE16(id);
3197         if (mr_list) {
3198                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3199                                                 I40E_AQ_FLAG_RD));
3200                 if (buf_size > I40E_AQ_LARGE_BUF)
3201                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3202         }
3203
3204         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3205                                        cmd_details);
3206         if (status == I40E_SUCCESS ||
3207             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3208                 if (rule_id)
3209                         *rule_id = LE16_TO_CPU(resp->rule_id);
3210                 if (rules_used)
3211                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3212                 if (rules_free)
3213                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3214         }
3215         return status;
3216 }
3217
3218 /**
3219  * i40e_aq_add_mirrorrule - add a mirror rule
3220  * @hw: pointer to the hw struct
3221  * @sw_seid: Switch SEID (to which rule refers)
3222  * @rule_type: Rule Type (ingress/egress/VLAN)
3223  * @dest_vsi: SEID of VSI to which packets will be mirrored
3224  * @count: length of the list
3225  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3226  * @cmd_details: pointer to command details structure or NULL
3227  * @rule_id: Rule ID returned from FW
3228  * @rules_used: Number of rules used in internal switch
3229  * @rules_free: Number of rules free in internal switch
3230  *
3231  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3232  **/
3233 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3234                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3235                         struct i40e_asq_cmd_details *cmd_details,
3236                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3237 {
3238         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3239             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3240                 if (count == 0 || !mr_list)
3241                         return I40E_ERR_PARAM;
3242         }
3243
3244         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3245                                   rule_type, dest_vsi, count, mr_list,
3246                                   cmd_details, rule_id, rules_used, rules_free);
3247 }
3248
3249 /**
3250  * i40e_aq_delete_mirrorrule - delete a mirror rule
3251  * @hw: pointer to the hw struct
3252  * @sw_seid: Switch SEID (to which rule refers)
3253  * @rule_type: Rule Type (ingress/egress/VLAN)
3254  * @count: length of the list
3255  * @rule_id: Rule ID that is returned in the receive desc as part of
3256  *              add_mirrorrule.
3257  * @mr_list: list of mirrored VLAN IDs to be removed
3258  * @cmd_details: pointer to command details structure or NULL
3259  * @rules_used: Number of rules used in internal switch
3260  * @rules_free: Number of rules free in internal switch
3261  *
3262  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3263  **/
3264 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3265                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3266                         struct i40e_asq_cmd_details *cmd_details,
3267                         u16 *rules_used, u16 *rules_free)
3268 {
3269         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3270         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3271                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3272                  * mirroring. For other rule_type, count and rule_type should
3273                  * not matter.
3274                  */
3275                 if (count == 0 || !mr_list)
3276                         return I40E_ERR_PARAM;
3277         }
3278
3279         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3280                                   rule_type, rule_id, count, mr_list,
3281                                   cmd_details, NULL, rules_used, rules_free);
3282 }
3283
3284 /**
3285  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3286  * @hw: pointer to the hw struct
3287  * @seid: VSI for the vlan filters
3288  * @v_list: list of vlan filters to be added
3289  * @count: length of the list
3290  * @cmd_details: pointer to command details structure or NULL
3291  **/
3292 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3293                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3294                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3295 {
3296         struct i40e_aq_desc desc;
3297         struct i40e_aqc_macvlan *cmd =
3298                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3299         enum i40e_status_code status;
3300         u16 buf_size;
3301
3302         if (count == 0 || !v_list || !hw)
3303                 return I40E_ERR_PARAM;
3304
3305         buf_size = count * sizeof(*v_list);
3306
3307         /* prep the rest of the request */
3308         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3309         cmd->num_addresses = CPU_TO_LE16(count);
3310         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3311         cmd->seid[1] = 0;
3312         cmd->seid[2] = 0;
3313
3314         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3315         if (buf_size > I40E_AQ_LARGE_BUF)
3316                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3317
3318         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3319                                        cmd_details);
3320
3321         return status;
3322 }
3323
3324 /**
3325  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3326  * @hw: pointer to the hw struct
3327  * @seid: VSI for the vlan filters
3328  * @v_list: list of macvlans to be removed
3329  * @count: length of the list
3330  * @cmd_details: pointer to command details structure or NULL
3331  **/
3332 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3333                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3334                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3335 {
3336         struct i40e_aq_desc desc;
3337         struct i40e_aqc_macvlan *cmd =
3338                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3339         enum i40e_status_code status;
3340         u16 buf_size;
3341
3342         if (count == 0 || !v_list || !hw)
3343                 return I40E_ERR_PARAM;
3344
3345         buf_size = count * sizeof(*v_list);
3346
3347         /* prep the rest of the request */
3348         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3349         cmd->num_addresses = CPU_TO_LE16(count);
3350         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3351         cmd->seid[1] = 0;
3352         cmd->seid[2] = 0;
3353
3354         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3355         if (buf_size > I40E_AQ_LARGE_BUF)
3356                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3357
3358         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3359                                        cmd_details);
3360
3361         return status;
3362 }
3363
3364 /**
3365  * i40e_aq_send_msg_to_vf
3366  * @hw: pointer to the hardware structure
3367  * @vfid: vf id to send msg
3368  * @v_opcode: opcodes for VF-PF communication
3369  * @v_retval: return error code
3370  * @msg: pointer to the msg buffer
3371  * @msglen: msg length
3372  * @cmd_details: pointer to command details
3373  *
3374  * send msg to vf
3375  **/
3376 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3377                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3378                                 struct i40e_asq_cmd_details *cmd_details)
3379 {
3380         struct i40e_aq_desc desc;
3381         struct i40e_aqc_pf_vf_message *cmd =
3382                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3383         enum i40e_status_code status;
3384
3385         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3386         cmd->id = CPU_TO_LE32(vfid);
3387         desc.cookie_high = CPU_TO_LE32(v_opcode);
3388         desc.cookie_low = CPU_TO_LE32(v_retval);
3389         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3390         if (msglen) {
3391                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3392                                                 I40E_AQ_FLAG_RD));
3393                 if (msglen > I40E_AQ_LARGE_BUF)
3394                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3395                 desc.datalen = CPU_TO_LE16(msglen);
3396         }
3397         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3398
3399         return status;
3400 }
3401
3402 /**
3403  * i40e_aq_debug_read_register
3404  * @hw: pointer to the hw struct
3405  * @reg_addr: register address
3406  * @reg_val: register value
3407  * @cmd_details: pointer to command details structure or NULL
3408  *
3409  * Read the register using the admin queue commands
3410  **/
3411 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3412                                 u32 reg_addr, u64 *reg_val,
3413                                 struct i40e_asq_cmd_details *cmd_details)
3414 {
3415         struct i40e_aq_desc desc;
3416         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3417                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3418         enum i40e_status_code status;
3419
3420         if (reg_val == NULL)
3421                 return I40E_ERR_PARAM;
3422
3423         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3424
3425         cmd_resp->address = CPU_TO_LE32(reg_addr);
3426
3427         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3428
3429         if (status == I40E_SUCCESS) {
3430                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3431                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3432         }
3433
3434         return status;
3435 }
3436
3437 /**
3438  * i40e_aq_debug_write_register
3439  * @hw: pointer to the hw struct
3440  * @reg_addr: register address
3441  * @reg_val: register value
3442  * @cmd_details: pointer to command details structure or NULL
3443  *
3444  * Write to a register using the admin queue commands
3445  **/
3446 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3447                                 u32 reg_addr, u64 reg_val,
3448                                 struct i40e_asq_cmd_details *cmd_details)
3449 {
3450         struct i40e_aq_desc desc;
3451         struct i40e_aqc_debug_reg_read_write *cmd =
3452                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3453         enum i40e_status_code status;
3454
3455         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3456
3457         cmd->address = CPU_TO_LE32(reg_addr);
3458         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3459         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3460
3461         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3462
3463         return status;
3464 }
3465
3466 /**
3467  * i40e_aq_request_resource
3468  * @hw: pointer to the hw struct
3469  * @resource: resource id
3470  * @access: access type
3471  * @sdp_number: resource number
3472  * @timeout: the maximum time in ms that the driver may hold the resource
3473  * @cmd_details: pointer to command details structure or NULL
3474  *
3475  * requests common resource using the admin queue commands
3476  **/
3477 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3478                                 enum i40e_aq_resources_ids resource,
3479                                 enum i40e_aq_resource_access_type access,
3480                                 u8 sdp_number, u64 *timeout,
3481                                 struct i40e_asq_cmd_details *cmd_details)
3482 {
3483         struct i40e_aq_desc desc;
3484         struct i40e_aqc_request_resource *cmd_resp =
3485                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3486         enum i40e_status_code status;
3487
3488         DEBUGFUNC("i40e_aq_request_resource");
3489
3490         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3491
3492         cmd_resp->resource_id = CPU_TO_LE16(resource);
3493         cmd_resp->access_type = CPU_TO_LE16(access);
3494         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3495
3496         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3497         /* The completion specifies the maximum time in ms that the driver
3498          * may hold the resource in the Timeout field.
3499          * If the resource is held by someone else, the command completes with
3500          * busy return value and the timeout field indicates the maximum time
3501          * the current owner of the resource has to free it.
3502          */
3503         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3504                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3505
3506         return status;
3507 }
3508
3509 /**
3510  * i40e_aq_release_resource
3511  * @hw: pointer to the hw struct
3512  * @resource: resource id
3513  * @sdp_number: resource number
3514  * @cmd_details: pointer to command details structure or NULL
3515  *
3516  * release common resource using the admin queue commands
3517  **/
3518 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3519                                 enum i40e_aq_resources_ids resource,
3520                                 u8 sdp_number,
3521                                 struct i40e_asq_cmd_details *cmd_details)
3522 {
3523         struct i40e_aq_desc desc;
3524         struct i40e_aqc_request_resource *cmd =
3525                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3526         enum i40e_status_code status;
3527
3528         DEBUGFUNC("i40e_aq_release_resource");
3529
3530         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3531
3532         cmd->resource_id = CPU_TO_LE16(resource);
3533         cmd->resource_number = CPU_TO_LE32(sdp_number);
3534
3535         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3536
3537         return status;
3538 }
3539
3540 /**
3541  * i40e_aq_read_nvm
3542  * @hw: pointer to the hw struct
3543  * @module_pointer: module pointer location in words from the NVM beginning
3544  * @offset: byte offset from the module beginning
3545  * @length: length of the section to be read (in bytes from the offset)
3546  * @data: command buffer (size [bytes] = length)
3547  * @last_command: tells if this is the last command in a series
3548  * @cmd_details: pointer to command details structure or NULL
3549  *
3550  * Read the NVM using the admin queue commands
3551  **/
3552 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3553                                 u32 offset, u16 length, void *data,
3554                                 bool last_command,
3555                                 struct i40e_asq_cmd_details *cmd_details)
3556 {
3557         struct i40e_aq_desc desc;
3558         struct i40e_aqc_nvm_update *cmd =
3559                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3560         enum i40e_status_code status;
3561
3562         DEBUGFUNC("i40e_aq_read_nvm");
3563
3564         /* In offset the highest byte must be zeroed. */
3565         if (offset & 0xFF000000) {
3566                 status = I40E_ERR_PARAM;
3567                 goto i40e_aq_read_nvm_exit;
3568         }
3569
3570         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3571
3572         /* If this is the last command in a series, set the proper flag. */
3573         if (last_command)
3574                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3575         cmd->module_pointer = module_pointer;
3576         cmd->offset = CPU_TO_LE32(offset);
3577         cmd->length = CPU_TO_LE16(length);
3578
3579         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3580         if (length > I40E_AQ_LARGE_BUF)
3581                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3582
3583         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3584
3585 i40e_aq_read_nvm_exit:
3586         return status;
3587 }
3588
3589 /**
3590  * i40e_aq_read_nvm_config - read an nvm config block
3591  * @hw: pointer to the hw struct
3592  * @cmd_flags: NVM access admin command bits
3593  * @field_id: field or feature id
3594  * @data: buffer for result
3595  * @buf_size: buffer size
3596  * @element_count: pointer to count of elements read by FW
3597  * @cmd_details: pointer to command details structure or NULL
3598  **/
3599 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3600                                 u8 cmd_flags, u32 field_id, void *data,
3601                                 u16 buf_size, u16 *element_count,
3602                                 struct i40e_asq_cmd_details *cmd_details)
3603 {
3604         struct i40e_aq_desc desc;
3605         struct i40e_aqc_nvm_config_read *cmd =
3606                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3607         enum i40e_status_code status;
3608
3609         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3610         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3611         if (buf_size > I40E_AQ_LARGE_BUF)
3612                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3613
3614         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3615         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3616         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3617                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3618         else
3619                 cmd->element_id_msw = 0;
3620
3621         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3622
3623         if (!status && element_count)
3624                 *element_count = LE16_TO_CPU(cmd->element_count);
3625
3626         return status;
3627 }
3628
3629 /**
3630  * i40e_aq_write_nvm_config - write an nvm config block
3631  * @hw: pointer to the hw struct
3632  * @cmd_flags: NVM access admin command bits
3633  * @data: buffer for result
3634  * @buf_size: buffer size
3635  * @element_count: count of elements to be written
3636  * @cmd_details: pointer to command details structure or NULL
3637  **/
3638 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3639                                 u8 cmd_flags, void *data, u16 buf_size,
3640                                 u16 element_count,
3641                                 struct i40e_asq_cmd_details *cmd_details)
3642 {
3643         struct i40e_aq_desc desc;
3644         struct i40e_aqc_nvm_config_write *cmd =
3645                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3646         enum i40e_status_code status;
3647
3648         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3649         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3650         if (buf_size > I40E_AQ_LARGE_BUF)
3651                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3652
3653         cmd->element_count = CPU_TO_LE16(element_count);
3654         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3655         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3656
3657         return status;
3658 }
3659
3660 /**
3661  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3662  * @hw: pointer to the hw struct
3663  * @buff: buffer for result
3664  * @buff_size: buffer size
3665  * @cmd_details: pointer to command details structure or NULL
3666  **/
3667 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3668                                 void *buff, u16 buff_size,
3669                                 struct i40e_asq_cmd_details *cmd_details)
3670 {
3671         struct i40e_aq_desc desc;
3672         enum i40e_status_code status;
3673
3674         UNREFERENCED_2PARAMETER(buff, buff_size);
3675
3676         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3677         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3678         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3679                 status = I40E_ERR_NOT_IMPLEMENTED;
3680
3681         return status;
3682 }
3683
3684 /**
3685  * i40e_aq_erase_nvm
3686  * @hw: pointer to the hw struct
3687  * @module_pointer: module pointer location in words from the NVM beginning
3688  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3689  * @length: length of the section to be erased (expressed in 4 KB)
3690  * @last_command: tells if this is the last command in a series
3691  * @cmd_details: pointer to command details structure or NULL
3692  *
3693  * Erase the NVM sector using the admin queue commands
3694  **/
3695 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3696                                 u32 offset, u16 length, bool last_command,
3697                                 struct i40e_asq_cmd_details *cmd_details)
3698 {
3699         struct i40e_aq_desc desc;
3700         struct i40e_aqc_nvm_update *cmd =
3701                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3702         enum i40e_status_code status;
3703
3704         DEBUGFUNC("i40e_aq_erase_nvm");
3705
3706         /* In offset the highest byte must be zeroed. */
3707         if (offset & 0xFF000000) {
3708                 status = I40E_ERR_PARAM;
3709                 goto i40e_aq_erase_nvm_exit;
3710         }
3711
3712         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3713
3714         /* If this is the last command in a series, set the proper flag. */
3715         if (last_command)
3716                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3717         cmd->module_pointer = module_pointer;
3718         cmd->offset = CPU_TO_LE32(offset);
3719         cmd->length = CPU_TO_LE16(length);
3720
3721         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3722
3723 i40e_aq_erase_nvm_exit:
3724         return status;
3725 }
3726
3727 /**
3728  * i40e_parse_discover_capabilities
3729  * @hw: pointer to the hw struct
3730  * @buff: pointer to a buffer containing device/function capability records
3731  * @cap_count: number of capability records in the list
3732  * @list_type_opc: type of capabilities list to parse
3733  *
3734  * Parse the device/function capabilities list.
3735  **/
3736 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3737                                      u32 cap_count,
3738                                      enum i40e_admin_queue_opc list_type_opc)
3739 {
3740         struct i40e_aqc_list_capabilities_element_resp *cap;
3741         u32 valid_functions, num_functions;
3742         u32 number, logical_id, phys_id;
3743         struct i40e_hw_capabilities *p;
3744         enum i40e_status_code status;
3745         u16 id, ocp_cfg_word0;
3746         u8 major_rev;
3747         u32 i = 0;
3748
3749         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3750
3751         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3752                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3753         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3754                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3755         else
3756                 return;
3757
3758         for (i = 0; i < cap_count; i++, cap++) {
3759                 id = LE16_TO_CPU(cap->id);
3760                 number = LE32_TO_CPU(cap->number);
3761                 logical_id = LE32_TO_CPU(cap->logical_id);
3762                 phys_id = LE32_TO_CPU(cap->phys_id);
3763                 major_rev = cap->major_rev;
3764
3765                 switch (id) {
3766                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3767                         p->switch_mode = number;
3768                         i40e_debug(hw, I40E_DEBUG_INIT,
3769                                    "HW Capability: Switch mode = %d\n",
3770                                    p->switch_mode);
3771                         break;
3772                 case I40E_AQ_CAP_ID_MNG_MODE:
3773                         p->management_mode = number;
3774                         if (major_rev > 1) {
3775                                 p->mng_protocols_over_mctp = logical_id;
3776                                 i40e_debug(hw, I40E_DEBUG_INIT,
3777                                            "HW Capability: Protocols over MCTP = %d\n",
3778                                            p->mng_protocols_over_mctp);
3779                         } else {
3780                                 p->mng_protocols_over_mctp = 0;
3781                         }
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: Management Mode = %d\n",
3784                                    p->management_mode);
3785                         break;
3786                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3787                         p->npar_enable = number;
3788                         i40e_debug(hw, I40E_DEBUG_INIT,
3789                                    "HW Capability: NPAR enable = %d\n",
3790                                    p->npar_enable);
3791                         break;
3792                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3793                         p->os2bmc = number;
3794                         i40e_debug(hw, I40E_DEBUG_INIT,
3795                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3796                         break;
3797                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3798                         p->valid_functions = number;
3799                         i40e_debug(hw, I40E_DEBUG_INIT,
3800                                    "HW Capability: Valid Functions = %d\n",
3801                                    p->valid_functions);
3802                         break;
3803                 case I40E_AQ_CAP_ID_SRIOV:
3804                         if (number == 1)
3805                                 p->sr_iov_1_1 = true;
3806                         i40e_debug(hw, I40E_DEBUG_INIT,
3807                                    "HW Capability: SR-IOV = %d\n",
3808                                    p->sr_iov_1_1);
3809                         break;
3810                 case I40E_AQ_CAP_ID_VF:
3811                         p->num_vfs = number;
3812                         p->vf_base_id = logical_id;
3813                         i40e_debug(hw, I40E_DEBUG_INIT,
3814                                    "HW Capability: VF count = %d\n",
3815                                    p->num_vfs);
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: VF base_id = %d\n",
3818                                    p->vf_base_id);
3819                         break;
3820                 case I40E_AQ_CAP_ID_VMDQ:
3821                         if (number == 1)
3822                                 p->vmdq = true;
3823                         i40e_debug(hw, I40E_DEBUG_INIT,
3824                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3825                         break;
3826                 case I40E_AQ_CAP_ID_8021QBG:
3827                         if (number == 1)
3828                                 p->evb_802_1_qbg = true;
3829                         i40e_debug(hw, I40E_DEBUG_INIT,
3830                                    "HW Capability: 802.1Qbg = %d\n", number);
3831                         break;
3832                 case I40E_AQ_CAP_ID_8021QBR:
3833                         if (number == 1)
3834                                 p->evb_802_1_qbh = true;
3835                         i40e_debug(hw, I40E_DEBUG_INIT,
3836                                    "HW Capability: 802.1Qbh = %d\n", number);
3837                         break;
3838                 case I40E_AQ_CAP_ID_VSI:
3839                         p->num_vsis = number;
3840                         i40e_debug(hw, I40E_DEBUG_INIT,
3841                                    "HW Capability: VSI count = %d\n",
3842                                    p->num_vsis);
3843                         break;
3844                 case I40E_AQ_CAP_ID_DCB:
3845                         if (number == 1) {
3846                                 p->dcb = true;
3847                                 p->enabled_tcmap = logical_id;
3848                                 p->maxtc = phys_id;
3849                         }
3850                         i40e_debug(hw, I40E_DEBUG_INIT,
3851                                    "HW Capability: DCB = %d\n", p->dcb);
3852                         i40e_debug(hw, I40E_DEBUG_INIT,
3853                                    "HW Capability: TC Mapping = %d\n",
3854                                    logical_id);
3855                         i40e_debug(hw, I40E_DEBUG_INIT,
3856                                    "HW Capability: TC Max = %d\n", p->maxtc);
3857                         break;
3858                 case I40E_AQ_CAP_ID_FCOE:
3859                         if (number == 1)
3860                                 p->fcoe = true;
3861                         i40e_debug(hw, I40E_DEBUG_INIT,
3862                                    "HW Capability: FCOE = %d\n", p->fcoe);
3863                         break;
3864                 case I40E_AQ_CAP_ID_ISCSI:
3865                         if (number == 1)
3866                                 p->iscsi = true;
3867                         i40e_debug(hw, I40E_DEBUG_INIT,
3868                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3869                         break;
3870                 case I40E_AQ_CAP_ID_RSS:
3871                         p->rss = true;
3872                         p->rss_table_size = number;
3873                         p->rss_table_entry_width = logical_id;
3874                         i40e_debug(hw, I40E_DEBUG_INIT,
3875                                    "HW Capability: RSS = %d\n", p->rss);
3876                         i40e_debug(hw, I40E_DEBUG_INIT,
3877                                    "HW Capability: RSS table size = %d\n",
3878                                    p->rss_table_size);
3879                         i40e_debug(hw, I40E_DEBUG_INIT,
3880                                    "HW Capability: RSS table width = %d\n",
3881                                    p->rss_table_entry_width);
3882                         break;
3883                 case I40E_AQ_CAP_ID_RXQ:
3884                         p->num_rx_qp = number;
3885                         p->base_queue = phys_id;
3886                         i40e_debug(hw, I40E_DEBUG_INIT,
3887                                    "HW Capability: Rx QP = %d\n", number);
3888                         i40e_debug(hw, I40E_DEBUG_INIT,
3889                                    "HW Capability: base_queue = %d\n",
3890                                    p->base_queue);
3891                         break;
3892                 case I40E_AQ_CAP_ID_TXQ:
3893                         p->num_tx_qp = number;
3894                         p->base_queue = phys_id;
3895                         i40e_debug(hw, I40E_DEBUG_INIT,
3896                                    "HW Capability: Tx QP = %d\n", number);
3897                         i40e_debug(hw, I40E_DEBUG_INIT,
3898                                    "HW Capability: base_queue = %d\n",
3899                                    p->base_queue);
3900                         break;
3901                 case I40E_AQ_CAP_ID_MSIX:
3902                         p->num_msix_vectors = number;
3903                         i40e_debug(hw, I40E_DEBUG_INIT,
3904                                    "HW Capability: MSIX vector count = %d\n",
3905                                    p->num_msix_vectors);
3906                         break;
3907                 case I40E_AQ_CAP_ID_VF_MSIX:
3908                         p->num_msix_vectors_vf = number;
3909                         i40e_debug(hw, I40E_DEBUG_INIT,
3910                                    "HW Capability: MSIX VF vector count = %d\n",
3911                                    p->num_msix_vectors_vf);
3912                         break;
3913                 case I40E_AQ_CAP_ID_FLEX10:
3914                         if (major_rev == 1) {
3915                                 if (number == 1) {
3916                                         p->flex10_enable = true;
3917                                         p->flex10_capable = true;
3918                                 }
3919                         } else {
3920                                 /* Capability revision >= 2 */
3921                                 if (number & 1)
3922                                         p->flex10_enable = true;
3923                                 if (number & 2)
3924                                         p->flex10_capable = true;
3925                         }
3926                         p->flex10_mode = logical_id;
3927                         p->flex10_status = phys_id;
3928                         i40e_debug(hw, I40E_DEBUG_INIT,
3929                                    "HW Capability: Flex10 mode = %d\n",
3930                                    p->flex10_mode);
3931                         i40e_debug(hw, I40E_DEBUG_INIT,
3932                                    "HW Capability: Flex10 status = %d\n",
3933                                    p->flex10_status);
3934                         break;
3935                 case I40E_AQ_CAP_ID_CEM:
3936                         if (number == 1)
3937                                 p->mgmt_cem = true;
3938                         i40e_debug(hw, I40E_DEBUG_INIT,
3939                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3940                         break;
3941                 case I40E_AQ_CAP_ID_IWARP:
3942                         if (number == 1)
3943                                 p->iwarp = true;
3944                         i40e_debug(hw, I40E_DEBUG_INIT,
3945                                    "HW Capability: iWARP = %d\n", p->iwarp);
3946                         break;
3947                 case I40E_AQ_CAP_ID_LED:
3948                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3949                                 p->led[phys_id] = true;
3950                         i40e_debug(hw, I40E_DEBUG_INIT,
3951                                    "HW Capability: LED - PIN %d\n", phys_id);
3952                         break;
3953                 case I40E_AQ_CAP_ID_SDP:
3954                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3955                                 p->sdp[phys_id] = true;
3956                         i40e_debug(hw, I40E_DEBUG_INIT,
3957                                    "HW Capability: SDP - PIN %d\n", phys_id);
3958                         break;
3959                 case I40E_AQ_CAP_ID_MDIO:
3960                         if (number == 1) {
3961                                 p->mdio_port_num = phys_id;
3962                                 p->mdio_port_mode = logical_id;
3963                         }
3964                         i40e_debug(hw, I40E_DEBUG_INIT,
3965                                    "HW Capability: MDIO port number = %d\n",
3966                                    p->mdio_port_num);
3967                         i40e_debug(hw, I40E_DEBUG_INIT,
3968                                    "HW Capability: MDIO port mode = %d\n",
3969                                    p->mdio_port_mode);
3970                         break;
3971                 case I40E_AQ_CAP_ID_1588:
3972                         if (number == 1)
3973                                 p->ieee_1588 = true;
3974                         i40e_debug(hw, I40E_DEBUG_INIT,
3975                                    "HW Capability: IEEE 1588 = %d\n",
3976                                    p->ieee_1588);
3977                         break;
3978                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3979                         p->fd = true;
3980                         p->fd_filters_guaranteed = number;
3981                         p->fd_filters_best_effort = logical_id;
3982                         i40e_debug(hw, I40E_DEBUG_INIT,
3983                                    "HW Capability: Flow Director = 1\n");
3984                         i40e_debug(hw, I40E_DEBUG_INIT,
3985                                    "HW Capability: Guaranteed FD filters = %d\n",
3986                                    p->fd_filters_guaranteed);
3987                         break;
3988                 case I40E_AQ_CAP_ID_WSR_PROT:
3989                         p->wr_csr_prot = (u64)number;
3990                         p->wr_csr_prot |= (u64)logical_id << 32;
3991                         i40e_debug(hw, I40E_DEBUG_INIT,
3992                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3993                                    (p->wr_csr_prot & 0xffff));
3994                         break;
3995                 case I40E_AQ_CAP_ID_NVM_MGMT:
3996                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3997                                 p->sec_rev_disabled = true;
3998                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3999                                 p->update_disabled = true;
4000                         break;
4001                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
4002                         hw->num_wol_proxy_filters = (u16)number;
4003                         hw->wol_proxy_vsi_seid = (u16)logical_id;
4004                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
4005                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
4006                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
4007                         else
4008                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
4009                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
4010                         i40e_debug(hw, I40E_DEBUG_INIT,
4011                                    "HW Capability: WOL proxy filters = %d\n",
4012                                    hw->num_wol_proxy_filters);
4013                         break;
4014                 default:
4015                         break;
4016                 }
4017         }
4018
4019         if (p->fcoe)
4020                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4021
4022         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4023         p->fcoe = false;
4024
4025         /* count the enabled ports (aka the "not disabled" ports) */
4026         hw->num_ports = 0;
4027         for (i = 0; i < 4; i++) {
4028                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4029                 u64 port_cfg = 0;
4030
4031                 /* use AQ read to get the physical register offset instead
4032                  * of the port relative offset
4033                  */
4034                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4035                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4036                         hw->num_ports++;
4037         }
4038
4039         /* OCP cards case: if a mezz is removed the ethernet port is at
4040          * disabled state in PRTGEN_CNF register. Additional NVM read is
4041          * needed in order to check if we are dealing with OCP card.
4042          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4043          * physical ports results in wrong partition id calculation and thus
4044          * not supporting WoL.
4045          */
4046         if (hw->mac.type == I40E_MAC_X722) {
4047                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4048                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4049                                                   2 * I40E_SR_OCP_CFG_WORD0,
4050                                                   sizeof(ocp_cfg_word0),
4051                                                   &ocp_cfg_word0, true, NULL);
4052                         if (status == I40E_SUCCESS &&
4053                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4054                                 hw->num_ports = 4;
4055                         i40e_release_nvm(hw);
4056                 }
4057         }
4058
4059         valid_functions = p->valid_functions;
4060         num_functions = 0;
4061         while (valid_functions) {
4062                 if (valid_functions & 1)
4063                         num_functions++;
4064                 valid_functions >>= 1;
4065         }
4066
4067         /* partition id is 1-based, and functions are evenly spread
4068          * across the ports as partitions
4069          */
4070         if (hw->num_ports != 0) {
4071                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4072                 hw->num_partitions = num_functions / hw->num_ports;
4073         }
4074
4075         /* additional HW specific goodies that might
4076          * someday be HW version specific
4077          */
4078         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4079 }
4080
4081 /**
4082  * i40e_aq_discover_capabilities
4083  * @hw: pointer to the hw struct
4084  * @buff: a virtual buffer to hold the capabilities
4085  * @buff_size: Size of the virtual buffer
4086  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4087  * @list_type_opc: capabilities type to discover - pass in the command opcode
4088  * @cmd_details: pointer to command details structure or NULL
4089  *
4090  * Get the device capabilities descriptions from the firmware
4091  **/
4092 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4093                                 void *buff, u16 buff_size, u16 *data_size,
4094                                 enum i40e_admin_queue_opc list_type_opc,
4095                                 struct i40e_asq_cmd_details *cmd_details)
4096 {
4097         struct i40e_aqc_list_capabilites *cmd;
4098         struct i40e_aq_desc desc;
4099         enum i40e_status_code status = I40E_SUCCESS;
4100
4101         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4102
4103         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4104                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4105                 status = I40E_ERR_PARAM;
4106                 goto exit;
4107         }
4108
4109         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4110
4111         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4112         if (buff_size > I40E_AQ_LARGE_BUF)
4113                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4114
4115         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4116         *data_size = LE16_TO_CPU(desc.datalen);
4117
4118         if (status)
4119                 goto exit;
4120
4121         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4122                                          list_type_opc);
4123
4124 exit:
4125         return status;
4126 }
4127
4128 /**
4129  * i40e_aq_update_nvm
4130  * @hw: pointer to the hw struct
4131  * @module_pointer: module pointer location in words from the NVM beginning
4132  * @offset: byte offset from the module beginning
4133  * @length: length of the section to be written (in bytes from the offset)
4134  * @data: command buffer (size [bytes] = length)
4135  * @last_command: tells if this is the last command in a series
4136  * @preservation_flags: Preservation mode flags
4137  * @cmd_details: pointer to command details structure or NULL
4138  *
4139  * Update the NVM using the admin queue commands
4140  **/
4141 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4142                                 u32 offset, u16 length, void *data,
4143                                 bool last_command, u8 preservation_flags,
4144                                 struct i40e_asq_cmd_details *cmd_details)
4145 {
4146         struct i40e_aq_desc desc;
4147         struct i40e_aqc_nvm_update *cmd =
4148                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4149         enum i40e_status_code status;
4150
4151         DEBUGFUNC("i40e_aq_update_nvm");
4152
4153         /* In offset the highest byte must be zeroed. */
4154         if (offset & 0xFF000000) {
4155                 status = I40E_ERR_PARAM;
4156                 goto i40e_aq_update_nvm_exit;
4157         }
4158
4159         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4160
4161         /* If this is the last command in a series, set the proper flag. */
4162         if (last_command)
4163                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4164         if (hw->mac.type == I40E_MAC_X722) {
4165                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4166                         cmd->command_flags |=
4167                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4168                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4169                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4170                         cmd->command_flags |=
4171                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4172                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4173         }
4174         cmd->module_pointer = module_pointer;
4175         cmd->offset = CPU_TO_LE32(offset);
4176         cmd->length = CPU_TO_LE16(length);
4177
4178         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4179         if (length > I40E_AQ_LARGE_BUF)
4180                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4181
4182         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4183
4184 i40e_aq_update_nvm_exit:
4185         return status;
4186 }
4187
4188 /**
4189  * i40e_aq_rearrange_nvm
4190  * @hw: pointer to the hw struct
4191  * @rearrange_nvm: defines direction of rearrangement
4192  * @cmd_details: pointer to command details structure or NULL
4193  *
4194  * Rearrange NVM structure, available only for transition FW
4195  **/
4196 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4197                                 u8 rearrange_nvm,
4198                                 struct i40e_asq_cmd_details *cmd_details)
4199 {
4200         struct i40e_aqc_nvm_update *cmd;
4201         enum i40e_status_code status;
4202         struct i40e_aq_desc desc;
4203
4204         DEBUGFUNC("i40e_aq_rearrange_nvm");
4205
4206         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4207
4208         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4209
4210         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4211                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4212
4213         if (!rearrange_nvm) {
4214                 status = I40E_ERR_PARAM;
4215                 goto i40e_aq_rearrange_nvm_exit;
4216         }
4217
4218         cmd->command_flags |= rearrange_nvm;
4219         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4220
4221 i40e_aq_rearrange_nvm_exit:
4222         return status;
4223 }
4224
4225 /**
4226  * i40e_aq_nvm_progress
4227  * @hw: pointer to the hw struct
4228  * @progress: pointer to progress returned from AQ
4229  * @cmd_details: pointer to command details structure or NULL
4230  *
4231  * Gets progress of flash rearrangement process
4232  **/
4233 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4234                                 struct i40e_asq_cmd_details *cmd_details)
4235 {
4236         enum i40e_status_code status;
4237         struct i40e_aq_desc desc;
4238
4239         DEBUGFUNC("i40e_aq_nvm_progress");
4240
4241         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4242         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4243         *progress = desc.params.raw[0];
4244         return status;
4245 }
4246
4247 /**
4248  * i40e_aq_get_lldp_mib
4249  * @hw: pointer to the hw struct
4250  * @bridge_type: type of bridge requested
4251  * @mib_type: Local, Remote or both Local and Remote MIBs
4252  * @buff: pointer to a user supplied buffer to store the MIB block
4253  * @buff_size: size of the buffer (in bytes)
4254  * @local_len : length of the returned Local LLDP MIB
4255  * @remote_len: length of the returned Remote LLDP MIB
4256  * @cmd_details: pointer to command details structure or NULL
4257  *
4258  * Requests the complete LLDP MIB (entire packet).
4259  **/
4260 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4261                                 u8 mib_type, void *buff, u16 buff_size,
4262                                 u16 *local_len, u16 *remote_len,
4263                                 struct i40e_asq_cmd_details *cmd_details)
4264 {
4265         struct i40e_aq_desc desc;
4266         struct i40e_aqc_lldp_get_mib *cmd =
4267                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4268         struct i40e_aqc_lldp_get_mib *resp =
4269                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4270         enum i40e_status_code status;
4271
4272         if (buff_size == 0 || !buff)
4273                 return I40E_ERR_PARAM;
4274
4275         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4276         /* Indirect Command */
4277         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4278
4279         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4280         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4281                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4282
4283         desc.datalen = CPU_TO_LE16(buff_size);
4284
4285         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4286         if (buff_size > I40E_AQ_LARGE_BUF)
4287                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4288
4289         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4290         if (!status) {
4291                 if (local_len != NULL)
4292                         *local_len = LE16_TO_CPU(resp->local_len);
4293                 if (remote_len != NULL)
4294                         *remote_len = LE16_TO_CPU(resp->remote_len);
4295         }
4296
4297         return status;
4298 }
4299
4300  /**
4301  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4302  * @hw: pointer to the hw struct
4303  * @mib_type: Local, Remote or both Local and Remote MIBs
4304  * @buff: pointer to a user supplied buffer to store the MIB block
4305  * @buff_size: size of the buffer (in bytes)
4306  * @cmd_details: pointer to command details structure or NULL
4307  *
4308  * Set the LLDP MIB.
4309  **/
4310 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4311                                 u8 mib_type, void *buff, u16 buff_size,
4312                                 struct i40e_asq_cmd_details *cmd_details)
4313 {
4314         struct i40e_aq_desc desc;
4315         struct i40e_aqc_lldp_set_local_mib *cmd =
4316                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4317         enum i40e_status_code status;
4318
4319         if (buff_size == 0 || !buff)
4320                 return I40E_ERR_PARAM;
4321
4322         i40e_fill_default_direct_cmd_desc(&desc,
4323                                 i40e_aqc_opc_lldp_set_local_mib);
4324         /* Indirect Command */
4325         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4326         if (buff_size > I40E_AQ_LARGE_BUF)
4327                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4328         desc.datalen = CPU_TO_LE16(buff_size);
4329
4330         cmd->type = mib_type;
4331         cmd->length = CPU_TO_LE16(buff_size);
4332         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4333         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4334
4335         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4336         return status;
4337 }
4338
4339 /**
4340  * i40e_aq_cfg_lldp_mib_change_event
4341  * @hw: pointer to the hw struct
4342  * @enable_update: Enable or Disable event posting
4343  * @cmd_details: pointer to command details structure or NULL
4344  *
4345  * Enable or Disable posting of an event on ARQ when LLDP MIB
4346  * associated with the interface changes
4347  **/
4348 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4349                                 bool enable_update,
4350                                 struct i40e_asq_cmd_details *cmd_details)
4351 {
4352         struct i40e_aq_desc desc;
4353         struct i40e_aqc_lldp_update_mib *cmd =
4354                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4355         enum i40e_status_code status;
4356
4357         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4358
4359         if (!enable_update)
4360                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4361
4362         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4363
4364         return status;
4365 }
4366
4367 /**
4368  * i40e_aq_restore_lldp
4369  * @hw: pointer to the hw struct
4370  * @setting: pointer to factory setting variable or NULL
4371  * @restore: True if factory settings should be restored
4372  * @cmd_details: pointer to command details structure or NULL
4373  *
4374  * Restore LLDP Agent factory settings if @restore set to True. In other case
4375  * only returns factory setting in AQ response.
4376  **/
4377 enum i40e_status_code
4378 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4379                      struct i40e_asq_cmd_details *cmd_details)
4380 {
4381         struct i40e_aq_desc desc;
4382         struct i40e_aqc_lldp_restore *cmd =
4383                 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4384         enum i40e_status_code status;
4385
4386         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4387                 i40e_debug(hw, I40E_DEBUG_ALL,
4388                            "Restore LLDP not supported by current FW version.\n");
4389                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4390         }
4391
4392         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4393
4394         if (restore)
4395                 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4396
4397         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4398
4399         if (setting)
4400                 *setting = cmd->command & 1;
4401
4402         return status;
4403 }
4404
4405 /**
4406  * i40e_aq_stop_lldp
4407  * @hw: pointer to the hw struct
4408  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4409  * @persist: True if stop of LLDP should be persistent across power cycles
4410  * @cmd_details: pointer to command details structure or NULL
4411  *
4412  * Stop or Shutdown the embedded LLDP Agent
4413  **/
4414 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4415                                 bool persist,
4416                                 struct i40e_asq_cmd_details *cmd_details)
4417 {
4418         struct i40e_aq_desc desc;
4419         struct i40e_aqc_lldp_stop *cmd =
4420                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4421         enum i40e_status_code status;
4422
4423         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4424
4425         if (shutdown_agent)
4426                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4427
4428         if (persist) {
4429                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4430                         cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4431                 else
4432                         i40e_debug(hw, I40E_DEBUG_ALL,
4433                                    "Persistent Stop LLDP not supported by current FW version.\n");
4434         }
4435
4436         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4437
4438         return status;
4439 }
4440
4441 /**
4442  * i40e_aq_start_lldp
4443  * @hw: pointer to the hw struct
4444  * @persist: True if start of LLDP should be persistent across power cycles
4445  * @cmd_details: pointer to command details structure or NULL
4446  *
4447  * Start the embedded LLDP Agent on all ports.
4448  **/
4449 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4450                                 bool persist,
4451                                 struct i40e_asq_cmd_details *cmd_details)
4452 {
4453         struct i40e_aq_desc desc;
4454         struct i40e_aqc_lldp_start *cmd =
4455                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4456         enum i40e_status_code status;
4457
4458         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4459
4460         cmd->command = I40E_AQ_LLDP_AGENT_START;
4461
4462         if (persist) {
4463                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4464                         cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4465                 else
4466                         i40e_debug(hw, I40E_DEBUG_ALL,
4467                                    "Persistent Start LLDP not supported by current FW version.\n");
4468         }
4469
4470         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4471
4472         return status;
4473 }
4474
4475 /**
4476  * i40e_aq_set_dcb_parameters
4477  * @hw: pointer to the hw struct
4478  * @cmd_details: pointer to command details structure or NULL
4479  * @dcb_enable: True if DCB configuration needs to be applied
4480  *
4481  **/
4482 enum i40e_status_code
4483 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4484                            struct i40e_asq_cmd_details *cmd_details)
4485 {
4486         struct i40e_aq_desc desc;
4487         struct i40e_aqc_set_dcb_parameters *cmd =
4488                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4489         enum i40e_status_code status;
4490
4491         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4492                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4493
4494         i40e_fill_default_direct_cmd_desc(&desc,
4495                                           i40e_aqc_opc_set_dcb_parameters);
4496
4497         if (dcb_enable) {
4498                 cmd->valid_flags = I40E_DCB_VALID;
4499                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4500         }
4501         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4502
4503         return status;
4504 }
4505
4506 /**
4507  * i40e_aq_get_cee_dcb_config
4508  * @hw: pointer to the hw struct
4509  * @buff: response buffer that stores CEE operational configuration
4510  * @buff_size: size of the buffer passed
4511  * @cmd_details: pointer to command details structure or NULL
4512  *
4513  * Get CEE DCBX mode operational configuration from firmware
4514  **/
4515 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4516                                 void *buff, u16 buff_size,
4517                                 struct i40e_asq_cmd_details *cmd_details)
4518 {
4519         struct i40e_aq_desc desc;
4520         enum i40e_status_code status;
4521
4522         if (buff_size == 0 || !buff)
4523                 return I40E_ERR_PARAM;
4524
4525         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4526
4527         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4528         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4529                                        cmd_details);
4530
4531         return status;
4532 }
4533
4534 /**
4535  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4536  * @hw: pointer to the hw struct
4537  * @start_agent: True if DCBx Agent needs to be Started
4538  *                              False if DCBx Agent needs to be Stopped
4539  * @cmd_details: pointer to command details structure or NULL
4540  *
4541  * Start/Stop the embedded dcbx Agent
4542  **/
4543 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4544                                 bool start_agent,
4545                                 struct i40e_asq_cmd_details *cmd_details)
4546 {
4547         struct i40e_aq_desc desc;
4548         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4549                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4550                                 &desc.params.raw;
4551         enum i40e_status_code status;
4552
4553         i40e_fill_default_direct_cmd_desc(&desc,
4554                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4555
4556         if (start_agent)
4557                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4558
4559         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4560
4561         return status;
4562 }
4563
4564 /**
4565  * i40e_aq_add_udp_tunnel
4566  * @hw: pointer to the hw struct
4567  * @udp_port: the UDP port to add in Host byte order
4568  * @protocol_index: protocol index type
4569  * @filter_index: pointer to filter index
4570  * @cmd_details: pointer to command details structure or NULL
4571  *
4572  * Note: Firmware expects the udp_port value to be in Little Endian format,
4573  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4574  * Little Endian order.
4575  **/
4576 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4577                                 u16 udp_port, u8 protocol_index,
4578                                 u8 *filter_index,
4579                                 struct i40e_asq_cmd_details *cmd_details)
4580 {
4581         struct i40e_aq_desc desc;
4582         struct i40e_aqc_add_udp_tunnel *cmd =
4583                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4584         struct i40e_aqc_del_udp_tunnel_completion *resp =
4585                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4586         enum i40e_status_code status;
4587
4588         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4589
4590         cmd->udp_port = CPU_TO_LE16(udp_port);
4591         cmd->protocol_type = protocol_index;
4592
4593         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4594
4595         if (!status && filter_index)
4596                 *filter_index = resp->index;
4597
4598         return status;
4599 }
4600
4601 /**
4602  * i40e_aq_del_udp_tunnel
4603  * @hw: pointer to the hw struct
4604  * @index: filter index
4605  * @cmd_details: pointer to command details structure or NULL
4606  **/
4607 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4608                                 struct i40e_asq_cmd_details *cmd_details)
4609 {
4610         struct i40e_aq_desc desc;
4611         struct i40e_aqc_remove_udp_tunnel *cmd =
4612                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4613         enum i40e_status_code status;
4614
4615         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4616
4617         cmd->index = index;
4618
4619         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4620
4621         return status;
4622 }
4623
4624 /**
4625  * i40e_aq_get_switch_resource_alloc (0x0204)
4626  * @hw: pointer to the hw struct
4627  * @num_entries: pointer to u8 to store the number of resource entries returned
4628  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4629  *        to store the resource information for all resource types.  Each
4630  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4631  * @count: size, in bytes, of the buffer provided
4632  * @cmd_details: pointer to command details structure or NULL
4633  *
4634  * Query the resources allocated to a function.
4635  **/
4636 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4637                         u8 *num_entries,
4638                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4639                         u16 count,
4640                         struct i40e_asq_cmd_details *cmd_details)
4641 {
4642         struct i40e_aq_desc desc;
4643         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4644                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4645         enum i40e_status_code status;
4646         u16 length = count * sizeof(*buf);
4647
4648         i40e_fill_default_direct_cmd_desc(&desc,
4649                                         i40e_aqc_opc_get_switch_resource_alloc);
4650
4651         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4652         if (length > I40E_AQ_LARGE_BUF)
4653                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4654
4655         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4656
4657         if (!status && num_entries)
4658                 *num_entries = cmd_resp->num_entries;
4659
4660         return status;
4661 }
4662
4663 /**
4664  * i40e_aq_delete_element - Delete switch element
4665  * @hw: pointer to the hw struct
4666  * @seid: the SEID to delete from the switch
4667  * @cmd_details: pointer to command details structure or NULL
4668  *
4669  * This deletes a switch element from the switch.
4670  **/
4671 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4672                                 struct i40e_asq_cmd_details *cmd_details)
4673 {
4674         struct i40e_aq_desc desc;
4675         struct i40e_aqc_switch_seid *cmd =
4676                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4677         enum i40e_status_code status;
4678
4679         if (seid == 0)
4680                 return I40E_ERR_PARAM;
4681
4682         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4683
4684         cmd->seid = CPU_TO_LE16(seid);
4685
4686         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4687
4688         return status;
4689 }
4690
4691 /**
4692  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4693  * @hw: pointer to the hw struct
4694  * @flags: component flags
4695  * @mac_seid: uplink seid (MAC SEID)
4696  * @vsi_seid: connected vsi seid
4697  * @ret_seid: seid of create pv component
4698  *
4699  * This instantiates an i40e port virtualizer with specified flags.
4700  * Depending on specified flags the port virtualizer can act as a
4701  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4702  */
4703 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4704                                        u16 mac_seid, u16 vsi_seid,
4705                                        u16 *ret_seid)
4706 {
4707         struct i40e_aq_desc desc;
4708         struct i40e_aqc_add_update_pv *cmd =
4709                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4710         struct i40e_aqc_add_update_pv_completion *resp =
4711                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4712         enum i40e_status_code status;
4713
4714         if (vsi_seid == 0)
4715                 return I40E_ERR_PARAM;
4716
4717         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4718         cmd->command_flags = CPU_TO_LE16(flags);
4719         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4720         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4721
4722         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4723         if (!status && ret_seid)
4724                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4725
4726         return status;
4727 }
4728
4729 /**
4730  * i40e_aq_add_tag - Add an S/E-tag
4731  * @hw: pointer to the hw struct
4732  * @direct_to_queue: should s-tag direct flow to a specific queue
4733  * @vsi_seid: VSI SEID to use this tag
4734  * @tag: value of the tag
4735  * @queue_num: queue number, only valid is direct_to_queue is true
4736  * @tags_used: return value, number of tags in use by this PF
4737  * @tags_free: return value, number of unallocated tags
4738  * @cmd_details: pointer to command details structure or NULL
4739  *
4740  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4741  * the number of tags allocated by the PF, and the number of unallocated
4742  * tags available.
4743  **/
4744 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4745                                 u16 vsi_seid, u16 tag, u16 queue_num,
4746                                 u16 *tags_used, u16 *tags_free,
4747                                 struct i40e_asq_cmd_details *cmd_details)
4748 {
4749         struct i40e_aq_desc desc;
4750         struct i40e_aqc_add_tag *cmd =
4751                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4752         struct i40e_aqc_add_remove_tag_completion *resp =
4753                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4754         enum i40e_status_code status;
4755
4756         if (vsi_seid == 0)
4757                 return I40E_ERR_PARAM;
4758
4759         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4760
4761         cmd->seid = CPU_TO_LE16(vsi_seid);
4762         cmd->tag = CPU_TO_LE16(tag);
4763         if (direct_to_queue) {
4764                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4765                 cmd->queue_number = CPU_TO_LE16(queue_num);
4766         }
4767
4768         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4769
4770         if (!status) {
4771                 if (tags_used != NULL)
4772                         *tags_used = LE16_TO_CPU(resp->tags_used);
4773                 if (tags_free != NULL)
4774                         *tags_free = LE16_TO_CPU(resp->tags_free);
4775         }
4776
4777         return status;
4778 }
4779
4780 /**
4781  * i40e_aq_remove_tag - Remove an S- or E-tag
4782  * @hw: pointer to the hw struct
4783  * @vsi_seid: VSI SEID this tag is associated with
4784  * @tag: value of the S-tag to delete
4785  * @tags_used: return value, number of tags in use by this PF
4786  * @tags_free: return value, number of unallocated tags
4787  * @cmd_details: pointer to command details structure or NULL
4788  *
4789  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4790  * the number of tags allocated by the PF, and the number of unallocated
4791  * tags available.
4792  **/
4793 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4794                                 u16 tag, u16 *tags_used, u16 *tags_free,
4795                                 struct i40e_asq_cmd_details *cmd_details)
4796 {
4797         struct i40e_aq_desc desc;
4798         struct i40e_aqc_remove_tag *cmd =
4799                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4800         struct i40e_aqc_add_remove_tag_completion *resp =
4801                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4802         enum i40e_status_code status;
4803
4804         if (vsi_seid == 0)
4805                 return I40E_ERR_PARAM;
4806
4807         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4808
4809         cmd->seid = CPU_TO_LE16(vsi_seid);
4810         cmd->tag = CPU_TO_LE16(tag);
4811
4812         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4813
4814         if (!status) {
4815                 if (tags_used != NULL)
4816                         *tags_used = LE16_TO_CPU(resp->tags_used);
4817                 if (tags_free != NULL)
4818                         *tags_free = LE16_TO_CPU(resp->tags_free);
4819         }
4820
4821         return status;
4822 }
4823
4824 /**
4825  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4826  * @hw: pointer to the hw struct
4827  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4828  * @etag: value of E-tag to add
4829  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4830  * @buf: address of indirect buffer
4831  * @tags_used: return value, number of E-tags in use by this port
4832  * @tags_free: return value, number of unallocated M-tags
4833  * @cmd_details: pointer to command details structure or NULL
4834  *
4835  * This associates a multicast E-tag to a port virtualizer.  It will return
4836  * the number of tags allocated by the PF, and the number of unallocated
4837  * tags available.
4838  *
4839  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4840  * num_tags_in_buf long.
4841  **/
4842 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4843                                 u16 etag, u8 num_tags_in_buf, void *buf,
4844                                 u16 *tags_used, u16 *tags_free,
4845                                 struct i40e_asq_cmd_details *cmd_details)
4846 {
4847         struct i40e_aq_desc desc;
4848         struct i40e_aqc_add_remove_mcast_etag *cmd =
4849                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4850         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4851            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4852         enum i40e_status_code status;
4853         u16 length = sizeof(u16) * num_tags_in_buf;
4854
4855         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4856                 return I40E_ERR_PARAM;
4857
4858         i40e_fill_default_direct_cmd_desc(&desc,
4859                                           i40e_aqc_opc_add_multicast_etag);
4860
4861         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4862         cmd->etag = CPU_TO_LE16(etag);
4863         cmd->num_unicast_etags = num_tags_in_buf;
4864
4865         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4866         if (length > I40E_AQ_LARGE_BUF)
4867                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4868
4869         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4870
4871         if (!status) {
4872                 if (tags_used != NULL)
4873                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4874                 if (tags_free != NULL)
4875                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4876         }
4877
4878         return status;
4879 }
4880
4881 /**
4882  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4883  * @hw: pointer to the hw struct
4884  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4885  * @etag: value of the E-tag to remove
4886  * @tags_used: return value, number of tags in use by this port
4887  * @tags_free: return value, number of unallocated tags
4888  * @cmd_details: pointer to command details structure or NULL
4889  *
4890  * This deletes an E-tag from the port virtualizer.  It will return
4891  * the number of tags allocated by the port, and the number of unallocated
4892  * tags available.
4893  **/
4894 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4895                                 u16 etag, u16 *tags_used, u16 *tags_free,
4896                                 struct i40e_asq_cmd_details *cmd_details)
4897 {
4898         struct i40e_aq_desc desc;
4899         struct i40e_aqc_add_remove_mcast_etag *cmd =
4900                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4901         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4902            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4903         enum i40e_status_code status;
4904
4905
4906         if (pv_seid == 0)
4907                 return I40E_ERR_PARAM;
4908
4909         i40e_fill_default_direct_cmd_desc(&desc,
4910                                           i40e_aqc_opc_remove_multicast_etag);
4911
4912         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4913         cmd->etag = CPU_TO_LE16(etag);
4914
4915         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4916
4917         if (!status) {
4918                 if (tags_used != NULL)
4919                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4920                 if (tags_free != NULL)
4921                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4922         }
4923
4924         return status;
4925 }
4926
4927 /**
4928  * i40e_aq_update_tag - Update an S/E-tag
4929  * @hw: pointer to the hw struct
4930  * @vsi_seid: VSI SEID using this S-tag
4931  * @old_tag: old tag value
4932  * @new_tag: new tag value
4933  * @tags_used: return value, number of tags in use by this PF
4934  * @tags_free: return value, number of unallocated tags
4935  * @cmd_details: pointer to command details structure or NULL
4936  *
4937  * This updates the value of the tag currently attached to this VSI
4938  * in the switch complex.  It will return the number of tags allocated
4939  * by the PF, and the number of unallocated tags available.
4940  **/
4941 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4942                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4943                                 u16 *tags_free,
4944                                 struct i40e_asq_cmd_details *cmd_details)
4945 {
4946         struct i40e_aq_desc desc;
4947         struct i40e_aqc_update_tag *cmd =
4948                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4949         struct i40e_aqc_update_tag_completion *resp =
4950                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4951         enum i40e_status_code status;
4952
4953         if (vsi_seid == 0)
4954                 return I40E_ERR_PARAM;
4955
4956         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4957
4958         cmd->seid = CPU_TO_LE16(vsi_seid);
4959         cmd->old_tag = CPU_TO_LE16(old_tag);
4960         cmd->new_tag = CPU_TO_LE16(new_tag);
4961
4962         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4963
4964         if (!status) {
4965                 if (tags_used != NULL)
4966                         *tags_used = LE16_TO_CPU(resp->tags_used);
4967                 if (tags_free != NULL)
4968                         *tags_free = LE16_TO_CPU(resp->tags_free);
4969         }
4970
4971         return status;
4972 }
4973
4974 /**
4975  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4976  * @hw: pointer to the hw struct
4977  * @tcmap: TC map for request/release any ignore PFC condition
4978  * @request: request or release ignore PFC condition
4979  * @tcmap_ret: return TCs for which PFC is currently ignored
4980  * @cmd_details: pointer to command details structure or NULL
4981  *
4982  * This sends out request/release to ignore PFC condition for a TC.
4983  * It will return the TCs for which PFC is currently ignored.
4984  **/
4985 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4986                                 bool request, u8 *tcmap_ret,
4987                                 struct i40e_asq_cmd_details *cmd_details)
4988 {
4989         struct i40e_aq_desc desc;
4990         struct i40e_aqc_pfc_ignore *cmd_resp =
4991                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4992         enum i40e_status_code status;
4993
4994         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4995
4996         if (request)
4997                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4998
4999         cmd_resp->tc_bitmap = tcmap;
5000
5001         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5002
5003         if (!status) {
5004                 if (tcmap_ret != NULL)
5005                         *tcmap_ret = cmd_resp->tc_bitmap;
5006         }
5007
5008         return status;
5009 }
5010
5011 /**
5012  * i40e_aq_dcb_updated - DCB Updated Command
5013  * @hw: pointer to the hw struct
5014  * @cmd_details: pointer to command details structure or NULL
5015  *
5016  * When LLDP is handled in PF this command is used by the PF
5017  * to notify EMP that a DCB setting is modified.
5018  * When LLDP is handled in EMP this command is used by the PF
5019  * to notify EMP whenever one of the following parameters get
5020  * modified:
5021  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5022  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5023  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5024  * EMP will return when the shared RPB settings have been
5025  * recomputed and modified. The retval field in the descriptor
5026  * will be set to 0 when RPB is modified.
5027  **/
5028 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5029                                 struct i40e_asq_cmd_details *cmd_details)
5030 {
5031         struct i40e_aq_desc desc;
5032         enum i40e_status_code status;
5033
5034         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5035
5036         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5037
5038         return status;
5039 }
5040
5041 /**
5042  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5043  * @hw: pointer to the hw struct
5044  * @seid: defines the SEID of the switch for which the stats are requested
5045  * @vlan_id: the VLAN ID for which the statistics are requested
5046  * @stat_index: index of the statistics counters block assigned to this VLAN
5047  * @cmd_details: pointer to command details structure or NULL
5048  *
5049  * XL710 supports 128 smonVlanStats counters.This command is used to
5050  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5051  * switch.
5052  **/
5053 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5054                                 u16 vlan_id, u16 *stat_index,
5055                                 struct i40e_asq_cmd_details *cmd_details)
5056 {
5057         struct i40e_aq_desc desc;
5058         struct i40e_aqc_add_remove_statistics *cmd_resp =
5059                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5060         enum i40e_status_code status;
5061
5062         if ((seid == 0) || (stat_index == NULL))
5063                 return I40E_ERR_PARAM;
5064
5065         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5066
5067         cmd_resp->seid = CPU_TO_LE16(seid);
5068         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5069
5070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5071
5072         if (!status && stat_index)
5073                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5074
5075         return status;
5076 }
5077
5078 /**
5079  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5080  * @hw: pointer to the hw struct
5081  * @seid: defines the SEID of the switch for which the stats are requested
5082  * @vlan_id: the VLAN ID for which the statistics are requested
5083  * @stat_index: index of the statistics counters block assigned to this VLAN
5084  * @cmd_details: pointer to command details structure or NULL
5085  *
5086  * XL710 supports 128 smonVlanStats counters.This command is used to
5087  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5088  * switch.
5089  **/
5090 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5091                                 u16 vlan_id, u16 stat_index,
5092                                 struct i40e_asq_cmd_details *cmd_details)
5093 {
5094         struct i40e_aq_desc desc;
5095         struct i40e_aqc_add_remove_statistics *cmd =
5096                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5097         enum i40e_status_code status;
5098
5099         if (seid == 0)
5100                 return I40E_ERR_PARAM;
5101
5102         i40e_fill_default_direct_cmd_desc(&desc,
5103                                           i40e_aqc_opc_remove_statistics);
5104
5105         cmd->seid = CPU_TO_LE16(seid);
5106         cmd->vlan  = CPU_TO_LE16(vlan_id);
5107         cmd->stat_index = CPU_TO_LE16(stat_index);
5108
5109         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5110
5111         return status;
5112 }
5113
5114 /**
5115  * i40e_aq_set_port_parameters - set physical port parameters.
5116  * @hw: pointer to the hw struct
5117  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5118  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5119  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5120  * @double_vlan: if set double VLAN is enabled
5121  * @cmd_details: pointer to command details structure or NULL
5122  **/
5123 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5124                                 u16 bad_frame_vsi, bool save_bad_pac,
5125                                 bool pad_short_pac, bool double_vlan,
5126                                 struct i40e_asq_cmd_details *cmd_details)
5127 {
5128         struct i40e_aqc_set_port_parameters *cmd;
5129         enum i40e_status_code status;
5130         struct i40e_aq_desc desc;
5131         u16 command_flags = 0;
5132
5133         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5134
5135         i40e_fill_default_direct_cmd_desc(&desc,
5136                                           i40e_aqc_opc_set_port_parameters);
5137
5138         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5139         if (save_bad_pac)
5140                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5141         if (pad_short_pac)
5142                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5143         if (double_vlan)
5144                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5145         cmd->command_flags = CPU_TO_LE16(command_flags);
5146
5147         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5148
5149         return status;
5150 }
5151
5152 /**
5153  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5154  * @hw: pointer to the hw struct
5155  * @seid: seid for the physical port/switching component/vsi
5156  * @buff: Indirect buffer to hold data parameters and response
5157  * @buff_size: Indirect buffer size
5158  * @opcode: Tx scheduler AQ command opcode
5159  * @cmd_details: pointer to command details structure or NULL
5160  *
5161  * Generic command handler for Tx scheduler AQ commands
5162  **/
5163 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5164                                 void *buff, u16 buff_size,
5165                                  enum i40e_admin_queue_opc opcode,
5166                                 struct i40e_asq_cmd_details *cmd_details)
5167 {
5168         struct i40e_aq_desc desc;
5169         struct i40e_aqc_tx_sched_ind *cmd =
5170                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5171         enum i40e_status_code status;
5172         bool cmd_param_flag = false;
5173
5174         switch (opcode) {
5175         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5176         case i40e_aqc_opc_configure_vsi_tc_bw:
5177         case i40e_aqc_opc_enable_switching_comp_ets:
5178         case i40e_aqc_opc_modify_switching_comp_ets:
5179         case i40e_aqc_opc_disable_switching_comp_ets:
5180         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5181         case i40e_aqc_opc_configure_switching_comp_bw_config:
5182                 cmd_param_flag = true;
5183                 break;
5184         case i40e_aqc_opc_query_vsi_bw_config:
5185         case i40e_aqc_opc_query_vsi_ets_sla_config:
5186         case i40e_aqc_opc_query_switching_comp_ets_config:
5187         case i40e_aqc_opc_query_port_ets_config:
5188         case i40e_aqc_opc_query_switching_comp_bw_config:
5189                 cmd_param_flag = false;
5190                 break;
5191         default:
5192                 return I40E_ERR_PARAM;
5193         }
5194
5195         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5196
5197         /* Indirect command */
5198         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5199         if (cmd_param_flag)
5200                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5201         if (buff_size > I40E_AQ_LARGE_BUF)
5202                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5203
5204         desc.datalen = CPU_TO_LE16(buff_size);
5205
5206         cmd->vsi_seid = CPU_TO_LE16(seid);
5207
5208         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5209
5210         return status;
5211 }
5212
5213 /**
5214  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5215  * @hw: pointer to the hw struct
5216  * @seid: VSI seid
5217  * @credit: BW limit credits (0 = disabled)
5218  * @max_credit: Max BW limit credits
5219  * @cmd_details: pointer to command details structure or NULL
5220  **/
5221 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5222                                 u16 seid, u16 credit, u8 max_credit,
5223                                 struct i40e_asq_cmd_details *cmd_details)
5224 {
5225         struct i40e_aq_desc desc;
5226         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5227                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5228         enum i40e_status_code status;
5229
5230         i40e_fill_default_direct_cmd_desc(&desc,
5231                                           i40e_aqc_opc_configure_vsi_bw_limit);
5232
5233         cmd->vsi_seid = CPU_TO_LE16(seid);
5234         cmd->credit = CPU_TO_LE16(credit);
5235         cmd->max_credit = max_credit;
5236
5237         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5238
5239         return status;
5240 }
5241
5242 /**
5243  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5244  * @hw: pointer to the hw struct
5245  * @seid: switching component seid
5246  * @credit: BW limit credits (0 = disabled)
5247  * @max_bw: Max BW limit credits
5248  * @cmd_details: pointer to command details structure or NULL
5249  **/
5250 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5251                                 u16 seid, u16 credit, u8 max_bw,
5252                                 struct i40e_asq_cmd_details *cmd_details)
5253 {
5254         struct i40e_aq_desc desc;
5255         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5256           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5257         enum i40e_status_code status;
5258
5259         i40e_fill_default_direct_cmd_desc(&desc,
5260                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5261
5262         cmd->seid = CPU_TO_LE16(seid);
5263         cmd->credit = CPU_TO_LE16(credit);
5264         cmd->max_bw = max_bw;
5265
5266         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5267
5268         return status;
5269 }
5270
5271 /**
5272  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5273  * @hw: pointer to the hw struct
5274  * @seid: VSI seid
5275  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5276  * @cmd_details: pointer to command details structure or NULL
5277  **/
5278 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5279                         u16 seid,
5280                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5281                         struct i40e_asq_cmd_details *cmd_details)
5282 {
5283         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5284                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5285                                     cmd_details);
5286 }
5287
5288 /**
5289  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5290  * @hw: pointer to the hw struct
5291  * @seid: VSI seid
5292  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5293  * @cmd_details: pointer to command details structure or NULL
5294  **/
5295 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5296                         u16 seid,
5297                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5298                         struct i40e_asq_cmd_details *cmd_details)
5299 {
5300         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5301                                     i40e_aqc_opc_configure_vsi_tc_bw,
5302                                     cmd_details);
5303 }
5304
5305 /**
5306  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5307  * @hw: pointer to the hw struct
5308  * @seid: seid of the switching component connected to Physical Port
5309  * @ets_data: Buffer holding ETS parameters
5310  * @opcode: Tx scheduler AQ command opcode
5311  * @cmd_details: pointer to command details structure or NULL
5312  **/
5313 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5314                 u16 seid,
5315                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5316                 enum i40e_admin_queue_opc opcode,
5317                 struct i40e_asq_cmd_details *cmd_details)
5318 {
5319         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5320                                     sizeof(*ets_data), opcode, cmd_details);
5321 }
5322
5323 /**
5324  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5325  * @hw: pointer to the hw struct
5326  * @seid: seid of the switching component
5327  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5328  * @cmd_details: pointer to command details structure or NULL
5329  **/
5330 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5331         u16 seid,
5332         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5333         struct i40e_asq_cmd_details *cmd_details)
5334 {
5335         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5336                             i40e_aqc_opc_configure_switching_comp_bw_config,
5337                             cmd_details);
5338 }
5339
5340 /**
5341  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5342  * @hw: pointer to the hw struct
5343  * @seid: seid of the switching component
5344  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5345  * @cmd_details: pointer to command details structure or NULL
5346  **/
5347 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5348         struct i40e_hw *hw, u16 seid,
5349         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5350         struct i40e_asq_cmd_details *cmd_details)
5351 {
5352         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5353                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5354                             cmd_details);
5355 }
5356
5357 /**
5358  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5359  * @hw: pointer to the hw struct
5360  * @seid: seid of the VSI
5361  * @bw_data: Buffer to hold VSI BW configuration
5362  * @cmd_details: pointer to command details structure or NULL
5363  **/
5364 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5365                         u16 seid,
5366                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5367                         struct i40e_asq_cmd_details *cmd_details)
5368 {
5369         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5370                                     i40e_aqc_opc_query_vsi_bw_config,
5371                                     cmd_details);
5372 }
5373
5374 /**
5375  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5376  * @hw: pointer to the hw struct
5377  * @seid: seid of the VSI
5378  * @bw_data: Buffer to hold VSI BW configuration per TC
5379  * @cmd_details: pointer to command details structure or NULL
5380  **/
5381 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5382                         u16 seid,
5383                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5384                         struct i40e_asq_cmd_details *cmd_details)
5385 {
5386         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5387                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5388                                     cmd_details);
5389 }
5390
5391 /**
5392  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5393  * @hw: pointer to the hw struct
5394  * @seid: seid of the switching component
5395  * @bw_data: Buffer to hold switching component's per TC BW config
5396  * @cmd_details: pointer to command details structure or NULL
5397  **/
5398 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5399                 u16 seid,
5400                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5401                 struct i40e_asq_cmd_details *cmd_details)
5402 {
5403         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5404                                    i40e_aqc_opc_query_switching_comp_ets_config,
5405                                    cmd_details);
5406 }
5407
5408 /**
5409  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5410  * @hw: pointer to the hw struct
5411  * @seid: seid of the VSI or switching component connected to Physical Port
5412  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5413  * @cmd_details: pointer to command details structure or NULL
5414  **/
5415 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5416                         u16 seid,
5417                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5418                         struct i40e_asq_cmd_details *cmd_details)
5419 {
5420         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5421                                     i40e_aqc_opc_query_port_ets_config,
5422                                     cmd_details);
5423 }
5424
5425 /**
5426  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5427  * @hw: pointer to the hw struct
5428  * @seid: seid of the switching component
5429  * @bw_data: Buffer to hold switching component's BW configuration
5430  * @cmd_details: pointer to command details structure or NULL
5431  **/
5432 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5433                 u16 seid,
5434                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5435                 struct i40e_asq_cmd_details *cmd_details)
5436 {
5437         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5438                                     i40e_aqc_opc_query_switching_comp_bw_config,
5439                                     cmd_details);
5440 }
5441
5442 /**
5443  * i40e_validate_filter_settings
5444  * @hw: pointer to the hardware structure
5445  * @settings: Filter control settings
5446  *
5447  * Check and validate the filter control settings passed.
5448  * The function checks for the valid filter/context sizes being
5449  * passed for FCoE and PE.
5450  *
5451  * Returns I40E_SUCCESS if the values passed are valid and within
5452  * range else returns an error.
5453  **/
5454 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5455                                 struct i40e_filter_control_settings *settings)
5456 {
5457         u32 fcoe_cntx_size, fcoe_filt_size;
5458         u32 pe_cntx_size, pe_filt_size;
5459         u32 fcoe_fmax;
5460
5461         u32 val;
5462
5463         /* Validate FCoE settings passed */
5464         switch (settings->fcoe_filt_num) {
5465         case I40E_HASH_FILTER_SIZE_1K:
5466         case I40E_HASH_FILTER_SIZE_2K:
5467         case I40E_HASH_FILTER_SIZE_4K:
5468         case I40E_HASH_FILTER_SIZE_8K:
5469         case I40E_HASH_FILTER_SIZE_16K:
5470         case I40E_HASH_FILTER_SIZE_32K:
5471                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5472                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5473                 break;
5474         default:
5475                 return I40E_ERR_PARAM;
5476         }
5477
5478         switch (settings->fcoe_cntx_num) {
5479         case I40E_DMA_CNTX_SIZE_512:
5480         case I40E_DMA_CNTX_SIZE_1K:
5481         case I40E_DMA_CNTX_SIZE_2K:
5482         case I40E_DMA_CNTX_SIZE_4K:
5483                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5484                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5485                 break;
5486         default:
5487                 return I40E_ERR_PARAM;
5488         }
5489
5490         /* Validate PE settings passed */
5491         switch (settings->pe_filt_num) {
5492         case I40E_HASH_FILTER_SIZE_1K:
5493         case I40E_HASH_FILTER_SIZE_2K:
5494         case I40E_HASH_FILTER_SIZE_4K:
5495         case I40E_HASH_FILTER_SIZE_8K:
5496         case I40E_HASH_FILTER_SIZE_16K:
5497         case I40E_HASH_FILTER_SIZE_32K:
5498         case I40E_HASH_FILTER_SIZE_64K:
5499         case I40E_HASH_FILTER_SIZE_128K:
5500         case I40E_HASH_FILTER_SIZE_256K:
5501         case I40E_HASH_FILTER_SIZE_512K:
5502         case I40E_HASH_FILTER_SIZE_1M:
5503                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5504                 pe_filt_size <<= (u32)settings->pe_filt_num;
5505                 break;
5506         default:
5507                 return I40E_ERR_PARAM;
5508         }
5509
5510         switch (settings->pe_cntx_num) {
5511         case I40E_DMA_CNTX_SIZE_512:
5512         case I40E_DMA_CNTX_SIZE_1K:
5513         case I40E_DMA_CNTX_SIZE_2K:
5514         case I40E_DMA_CNTX_SIZE_4K:
5515         case I40E_DMA_CNTX_SIZE_8K:
5516         case I40E_DMA_CNTX_SIZE_16K:
5517         case I40E_DMA_CNTX_SIZE_32K:
5518         case I40E_DMA_CNTX_SIZE_64K:
5519         case I40E_DMA_CNTX_SIZE_128K:
5520         case I40E_DMA_CNTX_SIZE_256K:
5521                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5522                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5523                 break;
5524         default:
5525                 return I40E_ERR_PARAM;
5526         }
5527
5528         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5529         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5530         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5531                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5532         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5533                 return I40E_ERR_INVALID_SIZE;
5534
5535         return I40E_SUCCESS;
5536 }
5537
5538 /**
5539  * i40e_set_filter_control
5540  * @hw: pointer to the hardware structure
5541  * @settings: Filter control settings
5542  *
5543  * Set the Queue Filters for PE/FCoE and enable filters required
5544  * for a single PF. It is expected that these settings are programmed
5545  * at the driver initialization time.
5546  **/
5547 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5548                                 struct i40e_filter_control_settings *settings)
5549 {
5550         enum i40e_status_code ret = I40E_SUCCESS;
5551         u32 hash_lut_size = 0;
5552         u32 val;
5553
5554         if (!settings)
5555                 return I40E_ERR_PARAM;
5556
5557         /* Validate the input settings */
5558         ret = i40e_validate_filter_settings(hw, settings);
5559         if (ret)
5560                 return ret;
5561
5562         /* Read the PF Queue Filter control register */
5563         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5564
5565         /* Program required PE hash buckets for the PF */
5566         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5567         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5568                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5569         /* Program required PE contexts for the PF */
5570         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5571         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5572                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5573
5574         /* Program required FCoE hash buckets for the PF */
5575         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5576         val |= ((u32)settings->fcoe_filt_num <<
5577                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5578                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5579         /* Program required FCoE DDP contexts for the PF */
5580         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5581         val |= ((u32)settings->fcoe_cntx_num <<
5582                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5583                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5584
5585         /* Program Hash LUT size for the PF */
5586         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5587         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5588                 hash_lut_size = 1;
5589         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5590                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5591
5592         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5593         if (settings->enable_fdir)
5594                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5595         if (settings->enable_ethtype)
5596                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5597         if (settings->enable_macvlan)
5598                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5599
5600         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5601
5602         return I40E_SUCCESS;
5603 }
5604
5605 /**
5606  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5607  * @hw: pointer to the hw struct
5608  * @mac_addr: MAC address to use in the filter
5609  * @ethtype: Ethertype to use in the filter
5610  * @flags: Flags that needs to be applied to the filter
5611  * @vsi_seid: seid of the control VSI
5612  * @queue: VSI queue number to send the packet to
5613  * @is_add: Add control packet filter if True else remove
5614  * @stats: Structure to hold information on control filter counts
5615  * @cmd_details: pointer to command details structure or NULL
5616  *
5617  * This command will Add or Remove control packet filter for a control VSI.
5618  * In return it will update the total number of perfect filter count in
5619  * the stats member.
5620  **/
5621 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5622                                 u8 *mac_addr, u16 ethtype, u16 flags,
5623                                 u16 vsi_seid, u16 queue, bool is_add,
5624                                 struct i40e_control_filter_stats *stats,
5625                                 struct i40e_asq_cmd_details *cmd_details)
5626 {
5627         struct i40e_aq_desc desc;
5628         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5629                 (struct i40e_aqc_add_remove_control_packet_filter *)
5630                 &desc.params.raw;
5631         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5632                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5633                 &desc.params.raw;
5634         enum i40e_status_code status;
5635
5636         if (vsi_seid == 0)
5637                 return I40E_ERR_PARAM;
5638
5639         if (is_add) {
5640                 i40e_fill_default_direct_cmd_desc(&desc,
5641                                 i40e_aqc_opc_add_control_packet_filter);
5642                 cmd->queue = CPU_TO_LE16(queue);
5643         } else {
5644                 i40e_fill_default_direct_cmd_desc(&desc,
5645                                 i40e_aqc_opc_remove_control_packet_filter);
5646         }
5647
5648         if (mac_addr)
5649                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5650                             I40E_NONDMA_TO_NONDMA);
5651
5652         cmd->etype = CPU_TO_LE16(ethtype);
5653         cmd->flags = CPU_TO_LE16(flags);
5654         cmd->seid = CPU_TO_LE16(vsi_seid);
5655
5656         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5657
5658         if (!status && stats) {
5659                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5660                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5661                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5662                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5663         }
5664
5665         return status;
5666 }
5667
5668 /**
5669  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5670  * @hw: pointer to the hw struct
5671  * @seid: VSI seid to add ethertype filter from
5672  **/
5673 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5674                                                     u16 seid)
5675 {
5676 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5677         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5678                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5679                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5680         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5681         enum i40e_status_code status;
5682
5683         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5684                                                        seid, 0, true, NULL,
5685                                                        NULL);
5686         if (status)
5687                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5688 }
5689
5690 /**
5691  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5692  * @filters: list of cloud filters
5693  * @filter_count: length of list
5694  *
5695  * There's an issue in the device where the Geneve VNI layout needs
5696  * to be shifted 1 byte over from the VxLAN VNI
5697  **/
5698 STATIC void i40e_fix_up_geneve_vni(
5699         struct i40e_aqc_cloud_filters_element_data *filters,
5700         u8 filter_count)
5701 {
5702         struct i40e_aqc_cloud_filters_element_data *f = filters;
5703         int i;
5704
5705         for (i = 0; i < filter_count; i++) {
5706                 u16 tnl_type;
5707                 u32 ti;
5708
5709                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5710                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5711                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5712                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5713                         ti = LE32_TO_CPU(f[i].tenant_id);
5714                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5715                 }
5716         }
5717 }
5718
5719 /**
5720  * i40e_aq_add_cloud_filters
5721  * @hw: pointer to the hardware structure
5722  * @seid: VSI seid to add cloud filters from
5723  * @filters: Buffer which contains the filters to be added
5724  * @filter_count: number of filters contained in the buffer
5725  *
5726  * Set the cloud filters for a given VSI.  The contents of the
5727  * i40e_aqc_cloud_filters_element_data are filled
5728  * in by the caller of the function.
5729  *
5730  **/
5731 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5732         u16 seid,
5733         struct i40e_aqc_cloud_filters_element_data *filters,
5734         u8 filter_count)
5735 {
5736         struct i40e_aq_desc desc;
5737         struct i40e_aqc_add_remove_cloud_filters *cmd =
5738         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5739         enum i40e_status_code status;
5740         u16 buff_len;
5741
5742         i40e_fill_default_direct_cmd_desc(&desc,
5743                                           i40e_aqc_opc_add_cloud_filters);
5744
5745         buff_len = filter_count * sizeof(*filters);
5746         desc.datalen = CPU_TO_LE16(buff_len);
5747         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5748         cmd->num_filters = filter_count;
5749         cmd->seid = CPU_TO_LE16(seid);
5750
5751         i40e_fix_up_geneve_vni(filters, filter_count);
5752
5753         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5754
5755         return status;
5756 }
5757
5758 /**
5759  * i40e_aq_add_cloud_filters_bb
5760  * @hw: pointer to the hardware structure
5761  * @seid: VSI seid to add cloud filters from
5762  * @filters: Buffer which contains the filters in big buffer to be added
5763  * @filter_count: number of filters contained in the buffer
5764  *
5765  * Set the cloud filters for a given VSI.  The contents of the
5766  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5767  * the function.
5768  *
5769  **/
5770 enum i40e_status_code
5771 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5772                              struct i40e_aqc_cloud_filters_element_bb *filters,
5773                              u8 filter_count)
5774 {
5775         struct i40e_aq_desc desc;
5776         struct i40e_aqc_add_remove_cloud_filters *cmd =
5777         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5778         enum i40e_status_code status;
5779         u16 buff_len;
5780         int i;
5781
5782         i40e_fill_default_direct_cmd_desc(&desc,
5783                                           i40e_aqc_opc_add_cloud_filters);
5784
5785         buff_len = filter_count * sizeof(*filters);
5786         desc.datalen = CPU_TO_LE16(buff_len);
5787         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5788         cmd->num_filters = filter_count;
5789         cmd->seid = CPU_TO_LE16(seid);
5790         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5791
5792         for (i = 0; i < filter_count; i++) {
5793                 u16 tnl_type;
5794                 u32 ti;
5795
5796                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5797                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5798                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5799
5800                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5801                  * one more byte further than normally used for Tenant ID in
5802                  * other tunnel types.
5803                  */
5804                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5805                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5806                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5807                 }
5808         }
5809
5810         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5811
5812         return status;
5813 }
5814
5815 /**
5816  * i40e_aq_rem_cloud_filters
5817  * @hw: pointer to the hardware structure
5818  * @seid: VSI seid to remove cloud filters from
5819  * @filters: Buffer which contains the filters to be removed
5820  * @filter_count: number of filters contained in the buffer
5821  *
5822  * Remove the cloud filters for a given VSI.  The contents of the
5823  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5824  * of the function.
5825  *
5826  **/
5827 enum i40e_status_code
5828 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5829                           struct i40e_aqc_cloud_filters_element_data *filters,
5830                           u8 filter_count)
5831 {
5832         struct i40e_aq_desc desc;
5833         struct i40e_aqc_add_remove_cloud_filters *cmd =
5834         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5835         enum i40e_status_code status;
5836         u16 buff_len;
5837
5838         i40e_fill_default_direct_cmd_desc(&desc,
5839                                           i40e_aqc_opc_remove_cloud_filters);
5840
5841         buff_len = filter_count * sizeof(*filters);
5842         desc.datalen = CPU_TO_LE16(buff_len);
5843         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5844         cmd->num_filters = filter_count;
5845         cmd->seid = CPU_TO_LE16(seid);
5846
5847         i40e_fix_up_geneve_vni(filters, filter_count);
5848
5849         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5850
5851         return status;
5852 }
5853
5854 /**
5855  * i40e_aq_rem_cloud_filters_bb
5856  * @hw: pointer to the hardware structure
5857  * @seid: VSI seid to remove cloud filters from
5858  * @filters: Buffer which contains the filters in big buffer to be removed
5859  * @filter_count: number of filters contained in the buffer
5860  *
5861  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5862  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5863  * function.
5864  *
5865  **/
5866 enum i40e_status_code
5867 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5868                              struct i40e_aqc_cloud_filters_element_bb *filters,
5869                              u8 filter_count)
5870 {
5871         struct i40e_aq_desc desc;
5872         struct i40e_aqc_add_remove_cloud_filters *cmd =
5873         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5874         enum i40e_status_code status;
5875         u16 buff_len;
5876         int i;
5877
5878         i40e_fill_default_direct_cmd_desc(&desc,
5879                                           i40e_aqc_opc_remove_cloud_filters);
5880
5881         buff_len = filter_count * sizeof(*filters);
5882         desc.datalen = CPU_TO_LE16(buff_len);
5883         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5884         cmd->num_filters = filter_count;
5885         cmd->seid = CPU_TO_LE16(seid);
5886         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5887
5888         for (i = 0; i < filter_count; i++) {
5889                 u16 tnl_type;
5890                 u32 ti;
5891
5892                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5893                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5894                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5895
5896                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5897                  * one more byte further than normally used for Tenant ID in
5898                  * other tunnel types.
5899                  */
5900                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5901                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5902                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5903                 }
5904         }
5905
5906         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5907
5908         return status;
5909 }
5910
5911 /**
5912  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5913  * @hw: pointer to the hw struct
5914  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5915  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5916  *
5917  **/
5918 enum
5919 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5920         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5921         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5922 {
5923         struct i40e_aq_desc desc;
5924         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5925                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5926         enum i40e_status_code status = I40E_SUCCESS;
5927         int i = 0;
5928
5929         /* X722 doesn't support this command */
5930         if (hw->mac.type == I40E_MAC_X722)
5931                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5932
5933         /* need FW version greater than 6.00 */
5934         if (hw->aq.fw_maj_ver < 6)
5935                 return I40E_NOT_SUPPORTED;
5936
5937         i40e_fill_default_direct_cmd_desc(&desc,
5938                                           i40e_aqc_opc_replace_cloud_filters);
5939
5940         desc.datalen = CPU_TO_LE16(32);
5941         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5942         cmd->old_filter_type = filters->old_filter_type;
5943         cmd->new_filter_type = filters->new_filter_type;
5944         cmd->valid_flags = filters->valid_flags;
5945         cmd->tr_bit = filters->tr_bit;
5946         cmd->tr_bit2 = filters->tr_bit2;
5947
5948         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5949                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5950
5951         /* for get cloud filters command */
5952         for (i = 0; i < 32; i += 4) {
5953                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5954                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5955                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5956                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5957         }
5958
5959         return status;
5960 }
5961
5962
5963 /**
5964  * i40e_aq_alternate_write
5965  * @hw: pointer to the hardware structure
5966  * @reg_addr0: address of first dword to be read
5967  * @reg_val0: value to be written under 'reg_addr0'
5968  * @reg_addr1: address of second dword to be read
5969  * @reg_val1: value to be written under 'reg_addr1'
5970  *
5971  * Write one or two dwords to alternate structure. Fields are indicated
5972  * by 'reg_addr0' and 'reg_addr1' register numbers.
5973  *
5974  **/
5975 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5976                                 u32 reg_addr0, u32 reg_val0,
5977                                 u32 reg_addr1, u32 reg_val1)
5978 {
5979         struct i40e_aq_desc desc;
5980         struct i40e_aqc_alternate_write *cmd_resp =
5981                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5982         enum i40e_status_code status;
5983
5984         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5985         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5986         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5987         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5988         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5989
5990         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5991
5992         return status;
5993 }
5994
5995 /**
5996  * i40e_aq_alternate_write_indirect
5997  * @hw: pointer to the hardware structure
5998  * @addr: address of a first register to be modified
5999  * @dw_count: number of alternate structure fields to write
6000  * @buffer: pointer to the command buffer
6001  *
6002  * Write 'dw_count' dwords from 'buffer' to alternate structure
6003  * starting at 'addr'.
6004  *
6005  **/
6006 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6007                                 u32 addr, u32 dw_count, void *buffer)
6008 {
6009         struct i40e_aq_desc desc;
6010         struct i40e_aqc_alternate_ind_write *cmd_resp =
6011                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6012         enum i40e_status_code status;
6013
6014         if (buffer == NULL)
6015                 return I40E_ERR_PARAM;
6016
6017         /* Indirect command */
6018         i40e_fill_default_direct_cmd_desc(&desc,
6019                                          i40e_aqc_opc_alternate_write_indirect);
6020
6021         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6022         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6023         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6024                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6025
6026         cmd_resp->address = CPU_TO_LE32(addr);
6027         cmd_resp->length = CPU_TO_LE32(dw_count);
6028
6029         status = i40e_asq_send_command(hw, &desc, buffer,
6030                                        I40E_LO_DWORD(4*dw_count), NULL);
6031
6032         return status;
6033 }
6034
6035 /**
6036  * i40e_aq_alternate_read
6037  * @hw: pointer to the hardware structure
6038  * @reg_addr0: address of first dword to be read
6039  * @reg_val0: pointer for data read from 'reg_addr0'
6040  * @reg_addr1: address of second dword to be read
6041  * @reg_val1: pointer for data read from 'reg_addr1'
6042  *
6043  * Read one or two dwords from alternate structure. Fields are indicated
6044  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6045  * is not passed then only register at 'reg_addr0' is read.
6046  *
6047  **/
6048 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6049                                 u32 reg_addr0, u32 *reg_val0,
6050                                 u32 reg_addr1, u32 *reg_val1)
6051 {
6052         struct i40e_aq_desc desc;
6053         struct i40e_aqc_alternate_write *cmd_resp =
6054                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6055         enum i40e_status_code status;
6056
6057         if (reg_val0 == NULL)
6058                 return I40E_ERR_PARAM;
6059
6060         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6061         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6062         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6063
6064         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6065
6066         if (status == I40E_SUCCESS) {
6067                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6068
6069                 if (reg_val1 != NULL)
6070                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6071         }
6072
6073         return status;
6074 }
6075
6076 /**
6077  * i40e_aq_alternate_read_indirect
6078  * @hw: pointer to the hardware structure
6079  * @addr: address of the alternate structure field
6080  * @dw_count: number of alternate structure fields to read
6081  * @buffer: pointer to the command buffer
6082  *
6083  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6084  * place them in 'buffer'. The buffer should be allocated by caller.
6085  *
6086  **/
6087 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6088                                 u32 addr, u32 dw_count, void *buffer)
6089 {
6090         struct i40e_aq_desc desc;
6091         struct i40e_aqc_alternate_ind_write *cmd_resp =
6092                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6093         enum i40e_status_code status;
6094
6095         if (buffer == NULL)
6096                 return I40E_ERR_PARAM;
6097
6098         /* Indirect command */
6099         i40e_fill_default_direct_cmd_desc(&desc,
6100                 i40e_aqc_opc_alternate_read_indirect);
6101
6102         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6103         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6104         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6105                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6106
6107         cmd_resp->address = CPU_TO_LE32(addr);
6108         cmd_resp->length = CPU_TO_LE32(dw_count);
6109
6110         status = i40e_asq_send_command(hw, &desc, buffer,
6111                                        I40E_LO_DWORD(4*dw_count), NULL);
6112
6113         return status;
6114 }
6115
6116 /**
6117  *  i40e_aq_alternate_clear
6118  *  @hw: pointer to the HW structure.
6119  *
6120  *  Clear the alternate structures of the port from which the function
6121  *  is called.
6122  *
6123  **/
6124 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6125 {
6126         struct i40e_aq_desc desc;
6127         enum i40e_status_code status;
6128
6129         i40e_fill_default_direct_cmd_desc(&desc,
6130                                           i40e_aqc_opc_alternate_clear_port);
6131
6132         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6133
6134         return status;
6135 }
6136
6137 /**
6138  *  i40e_aq_alternate_write_done
6139  *  @hw: pointer to the HW structure.
6140  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6141  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6142  *
6143  *  Indicates to the FW that alternate structures have been changed.
6144  *
6145  **/
6146 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6147                 u8 bios_mode, bool *reset_needed)
6148 {
6149         struct i40e_aq_desc desc;
6150         struct i40e_aqc_alternate_write_done *cmd =
6151                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6152         enum i40e_status_code status;
6153
6154         if (reset_needed == NULL)
6155                 return I40E_ERR_PARAM;
6156
6157         i40e_fill_default_direct_cmd_desc(&desc,
6158                                           i40e_aqc_opc_alternate_write_done);
6159
6160         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6161
6162         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6163         if (!status && reset_needed)
6164                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6165                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6166
6167         return status;
6168 }
6169
6170 /**
6171  *  i40e_aq_set_oem_mode
6172  *  @hw: pointer to the HW structure.
6173  *  @oem_mode: the OEM mode to be used
6174  *
6175  *  Sets the device to a specific operating mode. Currently the only supported
6176  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6177  *
6178  **/
6179 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6180                 u8 oem_mode)
6181 {
6182         struct i40e_aq_desc desc;
6183         struct i40e_aqc_alternate_write_done *cmd =
6184                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6185         enum i40e_status_code status;
6186
6187         i40e_fill_default_direct_cmd_desc(&desc,
6188                                           i40e_aqc_opc_alternate_set_mode);
6189
6190         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6191
6192         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6193
6194         return status;
6195 }
6196
6197 /**
6198  * i40e_aq_resume_port_tx
6199  * @hw: pointer to the hardware structure
6200  * @cmd_details: pointer to command details structure or NULL
6201  *
6202  * Resume port's Tx traffic
6203  **/
6204 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6205                                 struct i40e_asq_cmd_details *cmd_details)
6206 {
6207         struct i40e_aq_desc desc;
6208         enum i40e_status_code status;
6209
6210         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6211
6212         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6213
6214         return status;
6215 }
6216
6217 /**
6218  * i40e_set_pci_config_data - store PCI bus info
6219  * @hw: pointer to hardware structure
6220  * @link_status: the link status word from PCI config space
6221  *
6222  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6223  **/
6224 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6225 {
6226         hw->bus.type = i40e_bus_type_pci_express;
6227
6228         switch (link_status & I40E_PCI_LINK_WIDTH) {
6229         case I40E_PCI_LINK_WIDTH_1:
6230                 hw->bus.width = i40e_bus_width_pcie_x1;
6231                 break;
6232         case I40E_PCI_LINK_WIDTH_2:
6233                 hw->bus.width = i40e_bus_width_pcie_x2;
6234                 break;
6235         case I40E_PCI_LINK_WIDTH_4:
6236                 hw->bus.width = i40e_bus_width_pcie_x4;
6237                 break;
6238         case I40E_PCI_LINK_WIDTH_8:
6239                 hw->bus.width = i40e_bus_width_pcie_x8;
6240                 break;
6241         default:
6242                 hw->bus.width = i40e_bus_width_unknown;
6243                 break;
6244         }
6245
6246         switch (link_status & I40E_PCI_LINK_SPEED) {
6247         case I40E_PCI_LINK_SPEED_2500:
6248                 hw->bus.speed = i40e_bus_speed_2500;
6249                 break;
6250         case I40E_PCI_LINK_SPEED_5000:
6251                 hw->bus.speed = i40e_bus_speed_5000;
6252                 break;
6253         case I40E_PCI_LINK_SPEED_8000:
6254                 hw->bus.speed = i40e_bus_speed_8000;
6255                 break;
6256         default:
6257                 hw->bus.speed = i40e_bus_speed_unknown;
6258                 break;
6259         }
6260 }
6261
6262 /**
6263  * i40e_aq_debug_dump
6264  * @hw: pointer to the hardware structure
6265  * @cluster_id: specific cluster to dump
6266  * @table_id: table id within cluster
6267  * @start_index: index of line in the block to read
6268  * @buff_size: dump buffer size
6269  * @buff: dump buffer
6270  * @ret_buff_size: actual buffer size returned
6271  * @ret_next_table: next block to read
6272  * @ret_next_index: next index to read
6273  * @cmd_details: pointer to command details structure or NULL
6274  *
6275  * Dump internal FW/HW data for debug purposes.
6276  *
6277  **/
6278 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6279                                 u8 table_id, u32 start_index, u16 buff_size,
6280                                 void *buff, u16 *ret_buff_size,
6281                                 u8 *ret_next_table, u32 *ret_next_index,
6282                                 struct i40e_asq_cmd_details *cmd_details)
6283 {
6284         struct i40e_aq_desc desc;
6285         struct i40e_aqc_debug_dump_internals *cmd =
6286                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6287         struct i40e_aqc_debug_dump_internals *resp =
6288                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6289         enum i40e_status_code status;
6290
6291         if (buff_size == 0 || !buff)
6292                 return I40E_ERR_PARAM;
6293
6294         i40e_fill_default_direct_cmd_desc(&desc,
6295                                           i40e_aqc_opc_debug_dump_internals);
6296         /* Indirect Command */
6297         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6298         if (buff_size > I40E_AQ_LARGE_BUF)
6299                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6300
6301         cmd->cluster_id = cluster_id;
6302         cmd->table_id = table_id;
6303         cmd->idx = CPU_TO_LE32(start_index);
6304
6305         desc.datalen = CPU_TO_LE16(buff_size);
6306
6307         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6308         if (!status) {
6309                 if (ret_buff_size != NULL)
6310                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6311                 if (ret_next_table != NULL)
6312                         *ret_next_table = resp->table_id;
6313                 if (ret_next_index != NULL)
6314                         *ret_next_index = LE32_TO_CPU(resp->idx);
6315         }
6316
6317         return status;
6318 }
6319
6320
6321 /**
6322  * i40e_enable_eee
6323  * @hw: pointer to the hardware structure
6324  * @enable: state of Energy Efficient Ethernet mode to be set
6325  *
6326  * Enables or disables Energy Efficient Ethernet (EEE) mode
6327  * accordingly to @enable parameter.
6328  **/
6329 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6330 {
6331         struct i40e_aq_get_phy_abilities_resp abilities;
6332         struct i40e_aq_set_phy_config config;
6333         enum i40e_status_code status;
6334         __le16 eee_capability;
6335
6336         /* Get initial PHY capabilities */
6337         status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6338                                               NULL);
6339         if (status)
6340                 goto err;
6341
6342         /* Check whether NIC configuration is compatible with Energy Efficient
6343          * Ethernet (EEE) mode.
6344          */
6345         if (abilities.eee_capability == 0) {
6346                 status = I40E_ERR_CONFIG;
6347                 goto err;
6348         }
6349
6350         /* Cache initial EEE capability */
6351         eee_capability = abilities.eee_capability;
6352
6353         /* Get current configuration */
6354         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6355                                               NULL);
6356         if (status)
6357                 goto err;
6358
6359         /* Cache current configuration */
6360         config.phy_type = abilities.phy_type;
6361         config.link_speed = abilities.link_speed;
6362         config.abilities = abilities.abilities |
6363                            I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6364         config.eeer = abilities.eeer_val;
6365         config.low_power_ctrl = abilities.d3_lpan;
6366         config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6367                             I40E_AQ_PHY_FEC_CONFIG_MASK;
6368
6369         /* Set desired EEE state */
6370         if (enable) {
6371                 config.eee_capability = eee_capability;
6372                 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6373         } else {
6374                 config.eee_capability = 0;
6375                 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6376         }
6377
6378         /* Save modified config */
6379         status = i40e_aq_set_phy_config(hw, &config, NULL);
6380 err:
6381         return status;
6382 }
6383
6384 /**
6385  * i40e_read_bw_from_alt_ram
6386  * @hw: pointer to the hardware structure
6387  * @max_bw: pointer for max_bw read
6388  * @min_bw: pointer for min_bw read
6389  * @min_valid: pointer for bool that is true if min_bw is a valid value
6390  * @max_valid: pointer for bool that is true if max_bw is a valid value
6391  *
6392  * Read bw from the alternate ram for the given pf
6393  **/
6394 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6395                                         u32 *max_bw, u32 *min_bw,
6396                                         bool *min_valid, bool *max_valid)
6397 {
6398         enum i40e_status_code status;
6399         u32 max_bw_addr, min_bw_addr;
6400
6401         /* Calculate the address of the min/max bw registers */
6402         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6403                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6404                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6405         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6406                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6407                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6408
6409         /* Read the bandwidths from alt ram */
6410         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6411                                         min_bw_addr, min_bw);
6412
6413         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6414                 *min_valid = true;
6415         else
6416                 *min_valid = false;
6417
6418         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6419                 *max_valid = true;
6420         else
6421                 *max_valid = false;
6422
6423         return status;
6424 }
6425
6426 /**
6427  * i40e_aq_configure_partition_bw
6428  * @hw: pointer to the hardware structure
6429  * @bw_data: Buffer holding valid pfs and bw limits
6430  * @cmd_details: pointer to command details
6431  *
6432  * Configure partitions guaranteed/max bw
6433  **/
6434 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6435                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6436                         struct i40e_asq_cmd_details *cmd_details)
6437 {
6438         enum i40e_status_code status;
6439         struct i40e_aq_desc desc;
6440         u16 bwd_size = sizeof(*bw_data);
6441
6442         i40e_fill_default_direct_cmd_desc(&desc,
6443                                 i40e_aqc_opc_configure_partition_bw);
6444
6445         /* Indirect command */
6446         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6447         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6448
6449         desc.datalen = CPU_TO_LE16(bwd_size);
6450
6451         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6452
6453         return status;
6454 }
6455
6456 /**
6457  * i40e_read_phy_register_clause22
6458  * @hw: pointer to the HW structure
6459  * @reg: register address in the page
6460  * @phy_addr: PHY address on MDIO interface
6461  * @value: PHY register value
6462  *
6463  * Reads specified PHY register value
6464  **/
6465 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6466                                         u16 reg, u8 phy_addr, u16 *value)
6467 {
6468         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6469         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6470         u32 command = 0;
6471         u16 retry = 1000;
6472
6473         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6474                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6475                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6476                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6477                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6478         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6479         do {
6480                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6481                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6482                         status = I40E_SUCCESS;
6483                         break;
6484                 }
6485                 i40e_usec_delay(10);
6486                 retry--;
6487         } while (retry);
6488
6489         if (status) {
6490                 i40e_debug(hw, I40E_DEBUG_PHY,
6491                            "PHY: Can't write command to external PHY.\n");
6492         } else {
6493                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6494                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6495                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6496         }
6497
6498         return status;
6499 }
6500
6501 /**
6502  * i40e_write_phy_register_clause22
6503  * @hw: pointer to the HW structure
6504  * @reg: register address in the page
6505  * @phy_addr: PHY address on MDIO interface
6506  * @value: PHY register value
6507  *
6508  * Writes specified PHY register value
6509  **/
6510 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6511                                         u16 reg, u8 phy_addr, u16 value)
6512 {
6513         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6514         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6515         u32 command  = 0;
6516         u16 retry = 1000;
6517
6518         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6519         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6520
6521         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6522                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6523                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6524                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6525                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6526
6527         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6528         do {
6529                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6530                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6531                         status = I40E_SUCCESS;
6532                         break;
6533                 }
6534                 i40e_usec_delay(10);
6535                 retry--;
6536         } while (retry);
6537
6538         return status;
6539 }
6540
6541 /**
6542  * i40e_read_phy_register_clause45
6543  * @hw: pointer to the HW structure
6544  * @page: registers page number
6545  * @reg: register address in the page
6546  * @phy_addr: PHY address on MDIO interface
6547  * @value: PHY register value
6548  *
6549  * Reads specified PHY register value
6550  **/
6551 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6552                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6553 {
6554         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6555         u32 command  = 0;
6556         u16 retry = 1000;
6557         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6558
6559         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6560                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6561                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6562                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6563                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6564                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6565                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6566         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6567         do {
6568                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6569                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6570                         status = I40E_SUCCESS;
6571                         break;
6572                 }
6573                 i40e_usec_delay(10);
6574                 retry--;
6575         } while (retry);
6576
6577         if (status) {
6578                 i40e_debug(hw, I40E_DEBUG_PHY,
6579                            "PHY: Can't write command to external PHY.\n");
6580                 goto phy_read_end;
6581         }
6582
6583         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6584                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6585                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6586                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6587                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6588                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6589         status = I40E_ERR_TIMEOUT;
6590         retry = 1000;
6591         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6592         do {
6593                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6594                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6595                         status = I40E_SUCCESS;
6596                         break;
6597                 }
6598                 i40e_usec_delay(10);
6599                 retry--;
6600         } while (retry);
6601
6602         if (!status) {
6603                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6604                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6605                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6606         } else {
6607                 i40e_debug(hw, I40E_DEBUG_PHY,
6608                            "PHY: Can't read register value from external PHY.\n");
6609         }
6610
6611 phy_read_end:
6612         return status;
6613 }
6614
6615 /**
6616  * i40e_write_phy_register_clause45
6617  * @hw: pointer to the HW structure
6618  * @page: registers page number
6619  * @reg: register address in the page
6620  * @phy_addr: PHY address on MDIO interface
6621  * @value: PHY register value
6622  *
6623  * Writes value to specified PHY register
6624  **/
6625 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6626                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6627 {
6628         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6629         u32 command  = 0;
6630         u16 retry = 1000;
6631         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6632
6633         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6634                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6635                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6636                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6637                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6638                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6639                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6640         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6641         do {
6642                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6643                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6644                         status = I40E_SUCCESS;
6645                         break;
6646                 }
6647                 i40e_usec_delay(10);
6648                 retry--;
6649         } while (retry);
6650         if (status) {
6651                 i40e_debug(hw, I40E_DEBUG_PHY,
6652                            "PHY: Can't write command to external PHY.\n");
6653                 goto phy_write_end;
6654         }
6655
6656         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6657         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6658
6659         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6660                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6661                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6662                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6663                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6664                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6665         status = I40E_ERR_TIMEOUT;
6666         retry = 1000;
6667         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6668         do {
6669                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6670                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6671                         status = I40E_SUCCESS;
6672                         break;
6673                 }
6674                 i40e_usec_delay(10);
6675                 retry--;
6676         } while (retry);
6677
6678 phy_write_end:
6679         return status;
6680 }
6681
6682 /**
6683  * i40e_write_phy_register
6684  * @hw: pointer to the HW structure
6685  * @page: registers page number
6686  * @reg: register address in the page
6687  * @phy_addr: PHY address on MDIO interface
6688  * @value: PHY register value
6689  *
6690  * Writes value to specified PHY register
6691  **/
6692 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6693                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6694 {
6695         enum i40e_status_code status;
6696
6697         switch (hw->device_id) {
6698         case I40E_DEV_ID_1G_BASE_T_X722:
6699                 status = i40e_write_phy_register_clause22(hw,
6700                         reg, phy_addr, value);
6701                 break;
6702         case I40E_DEV_ID_10G_BASE_T:
6703         case I40E_DEV_ID_10G_BASE_T4:
6704         case I40E_DEV_ID_10G_BASE_T_BC:
6705         case I40E_DEV_ID_10G_BASE_T_X722:
6706         case I40E_DEV_ID_25G_B:
6707         case I40E_DEV_ID_25G_SFP28:
6708                 status = i40e_write_phy_register_clause45(hw,
6709                         page, reg, phy_addr, value);
6710                 break;
6711         default:
6712                 status = I40E_ERR_UNKNOWN_PHY;
6713                 break;
6714         }
6715
6716         return status;
6717 }
6718
6719 /**
6720  * i40e_read_phy_register
6721  * @hw: pointer to the HW structure
6722  * @page: registers page number
6723  * @reg: register address in the page
6724  * @phy_addr: PHY address on MDIO interface
6725  * @value: PHY register value
6726  *
6727  * Reads specified PHY register value
6728  **/
6729 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6730                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6731 {
6732         enum i40e_status_code status;
6733
6734         switch (hw->device_id) {
6735         case I40E_DEV_ID_1G_BASE_T_X722:
6736                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6737                                                          value);
6738                 break;
6739         case I40E_DEV_ID_10G_BASE_T:
6740         case I40E_DEV_ID_10G_BASE_T4:
6741         case I40E_DEV_ID_10G_BASE_T_X722:
6742         case I40E_DEV_ID_25G_B:
6743         case I40E_DEV_ID_25G_SFP28:
6744                 status = i40e_read_phy_register_clause45(hw, page, reg,
6745                                                          phy_addr, value);
6746                 break;
6747         default:
6748                 status = I40E_ERR_UNKNOWN_PHY;
6749                 break;
6750         }
6751
6752         return status;
6753 }
6754
6755 /**
6756  * i40e_get_phy_address
6757  * @hw: pointer to the HW structure
6758  * @dev_num: PHY port num that address we want
6759  *
6760  * Gets PHY address for current port
6761  **/
6762 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6763 {
6764         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6765         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6766
6767         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6768 }
6769
6770 /**
6771  * i40e_blink_phy_led
6772  * @hw: pointer to the HW structure
6773  * @time: time how long led will blinks in secs
6774  * @interval: gap between LED on and off in msecs
6775  *
6776  * Blinks PHY link LED
6777  **/
6778 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6779                                               u32 time, u32 interval)
6780 {
6781         enum i40e_status_code status = I40E_SUCCESS;
6782         u32 i;
6783         u16 led_ctl = 0;
6784         u16 gpio_led_port;
6785         u16 led_reg;
6786         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6787         u8 phy_addr = 0;
6788         u8 port_num;
6789
6790         i = rd32(hw, I40E_PFGEN_PORTNUM);
6791         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6792         phy_addr = i40e_get_phy_address(hw, port_num);
6793
6794         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6795              led_addr++) {
6796                 status = i40e_read_phy_register_clause45(hw,
6797                                                          I40E_PHY_COM_REG_PAGE,
6798                                                          led_addr, phy_addr,
6799                                                          &led_reg);
6800                 if (status)
6801                         goto phy_blinking_end;
6802                 led_ctl = led_reg;
6803                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6804                         led_reg = 0;
6805                         status = i40e_write_phy_register_clause45(hw,
6806                                                          I40E_PHY_COM_REG_PAGE,
6807                                                          led_addr, phy_addr,
6808                                                          led_reg);
6809                         if (status)
6810                                 goto phy_blinking_end;
6811                         break;
6812                 }
6813         }
6814
6815         if (time > 0 && interval > 0) {
6816                 for (i = 0; i < time * 1000; i += interval) {
6817                         status = i40e_read_phy_register_clause45(hw,
6818                                                 I40E_PHY_COM_REG_PAGE,
6819                                                 led_addr, phy_addr, &led_reg);
6820                         if (status)
6821                                 goto restore_config;
6822                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6823                                 led_reg = 0;
6824                         else
6825                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6826                         status = i40e_write_phy_register_clause45(hw,
6827                                                 I40E_PHY_COM_REG_PAGE,
6828                                                 led_addr, phy_addr, led_reg);
6829                         if (status)
6830                                 goto restore_config;
6831                         i40e_msec_delay(interval);
6832                 }
6833         }
6834
6835 restore_config:
6836         status = i40e_write_phy_register_clause45(hw,
6837                                                   I40E_PHY_COM_REG_PAGE,
6838                                                   led_addr, phy_addr, led_ctl);
6839
6840 phy_blinking_end:
6841         return status;
6842 }
6843
6844 /**
6845  * i40e_led_get_reg - read LED register
6846  * @hw: pointer to the HW structure
6847  * @led_addr: LED register address
6848  * @reg_val: read register value
6849  **/
6850 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6851                                               u32 *reg_val)
6852 {
6853         enum i40e_status_code status;
6854         u8 phy_addr = 0;
6855
6856         *reg_val = 0;
6857         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6858                 status = i40e_aq_get_phy_register(hw,
6859                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6860                                                 I40E_PHY_COM_REG_PAGE, true,
6861                                                 I40E_PHY_LED_PROV_REG_1,
6862                                                 reg_val, NULL);
6863         } else {
6864                 phy_addr = i40e_get_phy_address(hw, hw->port);
6865                 status = i40e_read_phy_register_clause45(hw,
6866                                                          I40E_PHY_COM_REG_PAGE,
6867                                                          led_addr, phy_addr,
6868                                                          (u16 *)reg_val);
6869         }
6870         return status;
6871 }
6872
6873 /**
6874  * i40e_led_set_reg - write LED register
6875  * @hw: pointer to the HW structure
6876  * @led_addr: LED register address
6877  * @reg_val: register value to write
6878  **/
6879 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6880                                               u32 reg_val)
6881 {
6882         enum i40e_status_code status;
6883         u8 phy_addr = 0;
6884
6885         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6886                 status = i40e_aq_set_phy_register(hw,
6887                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6888                                                 I40E_PHY_COM_REG_PAGE, true,
6889                                                 I40E_PHY_LED_PROV_REG_1,
6890                                                 reg_val, NULL);
6891         } else {
6892                 phy_addr = i40e_get_phy_address(hw, hw->port);
6893                 status = i40e_write_phy_register_clause45(hw,
6894                                                           I40E_PHY_COM_REG_PAGE,
6895                                                           led_addr, phy_addr,
6896                                                           (u16)reg_val);
6897         }
6898
6899         return status;
6900 }
6901
6902 /**
6903  * i40e_led_get_phy - return current on/off mode
6904  * @hw: pointer to the hw struct
6905  * @led_addr: address of led register to use
6906  * @val: original value of register to use
6907  *
6908  **/
6909 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6910                                        u16 *val)
6911 {
6912         enum i40e_status_code status = I40E_SUCCESS;
6913         u16 gpio_led_port;
6914         u32 reg_val_aq;
6915         u16 temp_addr;
6916         u8 phy_addr = 0;
6917         u16 reg_val;
6918
6919         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6920                 status = i40e_aq_get_phy_register(hw,
6921                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6922                                                 I40E_PHY_COM_REG_PAGE, true,
6923                                                 I40E_PHY_LED_PROV_REG_1,
6924                                                 &reg_val_aq, NULL);
6925                 if (status == I40E_SUCCESS)
6926                         *val = (u16)reg_val_aq;
6927                 return status;
6928         }
6929         temp_addr = I40E_PHY_LED_PROV_REG_1;
6930         phy_addr = i40e_get_phy_address(hw, hw->port);
6931         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6932              temp_addr++) {
6933                 status = i40e_read_phy_register_clause45(hw,
6934                                                          I40E_PHY_COM_REG_PAGE,
6935                                                          temp_addr, phy_addr,
6936                                                          &reg_val);
6937                 if (status)
6938                         return status;
6939                 *val = reg_val;
6940                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6941                         *led_addr = temp_addr;
6942                         break;
6943                 }
6944         }
6945         return status;
6946 }
6947
6948 /**
6949  * i40e_led_set_phy
6950  * @hw: pointer to the HW structure
6951  * @on: true or false
6952  * @led_addr: address of led register to use
6953  * @mode: original val plus bit for set or ignore
6954  *
6955  * Set led's on or off when controlled by the PHY
6956  *
6957  **/
6958 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6959                                        u16 led_addr, u32 mode)
6960 {
6961         enum i40e_status_code status = I40E_SUCCESS;
6962         u32 led_ctl = 0;
6963         u32 led_reg = 0;
6964
6965         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6966         if (status)
6967                 return status;
6968         led_ctl = led_reg;
6969         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6970                 led_reg = 0;
6971                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6972                 if (status)
6973                         return status;
6974         }
6975         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6976         if (status)
6977                 goto restore_config;
6978         if (on)
6979                 led_reg = I40E_PHY_LED_MANUAL_ON;
6980         else
6981                 led_reg = 0;
6982         status = i40e_led_set_reg(hw, led_addr, led_reg);
6983         if (status)
6984                 goto restore_config;
6985         if (mode & I40E_PHY_LED_MODE_ORIG) {
6986                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6987                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6988         }
6989         return status;
6990
6991 restore_config:
6992         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6993         return status;
6994 }
6995 #endif /* PF_DRIVER */
6996 /**
6997  * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
6998  * @hw: pointer to the hw struct
6999  * @stat: pointer to structure with status of rx and tx lpi
7000  *
7001  * Read LPI state directly from external PHY register or from MAC
7002  * register, depending on device ID and current link speed.
7003  */
7004 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
7005                                               struct i40e_hw_port_stats *stat)
7006 {
7007         enum i40e_status_code ret = I40E_SUCCESS;
7008         u32 val;
7009
7010         stat->rx_lpi_status = 0;
7011         stat->tx_lpi_status = 0;
7012
7013         if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7014             (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7015              hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
7016                 ret = i40e_aq_get_phy_register(hw,
7017                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7018                                                I40E_BCM_PHY_PCS_STATUS1_PAGE,
7019                                                true,
7020                                                I40E_BCM_PHY_PCS_STATUS1_REG,
7021                                                &val, NULL);
7022
7023                 if (ret != I40E_SUCCESS)
7024                         return ret;
7025
7026                 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7027                 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7028
7029                 return ret;
7030         }
7031
7032         val = rd32(hw, I40E_PRTPM_EEE_STAT);
7033         stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7034                                I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7035         stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7036                                I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7037
7038         return ret;
7039 }
7040
7041 /**
7042  * i40e_get_lpi_counters - read LPI counters from EEE statistics
7043  * @hw: pointer to the hw struct
7044  * @tx_counter: pointer to memory for TX LPI counter
7045  * @rx_counter: pointer to memory for RX LPI counter
7046  * @is_clear:   returns true if counters are clear after read
7047  *
7048  * Read Low Power Idle (LPI) mode counters from Energy Efficient
7049  * Ethernet (EEE) statistics.
7050  **/
7051 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7052                                             u32 *tx_counter, u32 *rx_counter,
7053                                             bool *is_clear)
7054 {
7055         /* only X710-T*L requires special handling of counters
7056          * for other devices we just read the MAC registers
7057          */
7058         if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7059             hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7060                 enum i40e_status_code retval;
7061                 u32 cmd_status = 0;
7062
7063                 *is_clear = false;
7064                 retval = i40e_aq_run_phy_activity(hw,
7065                                 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7066                                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7067                                 &cmd_status, tx_counter, rx_counter, NULL);
7068
7069                 if (cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7070                         retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7071
7072                 return retval;
7073         }
7074
7075         *is_clear = true;
7076         *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7077         *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7078
7079         return I40E_SUCCESS;
7080 }
7081
7082 /**
7083  * i40e_lpi_stat_update - update LPI counters with values relative to offset
7084  * @hw: pointer to the hw struct
7085  * @offset_loaded: flag indicating need of writing current value to offset
7086  * @tx_offset: pointer to offset of TX LPI counter
7087  * @tx_stat: pointer to value of TX LPI counter
7088  * @rx_offset: pointer to offset of RX LPI counter
7089  * @rx_stat: pointer to value of RX LPI counter
7090  *
7091  * Update Low Power Idle (LPI) mode counters while having regard to passed
7092  * offsets.
7093  **/
7094 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7095                                            bool offset_loaded, u64 *tx_offset,
7096                                            u64 *tx_stat, u64 *rx_offset,
7097                                            u64 *rx_stat)
7098 {
7099         enum i40e_status_code retval;
7100         u32 tx_counter, rx_counter;
7101         bool is_clear;
7102
7103         retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7104         if (retval)
7105                 goto err;
7106
7107         if (is_clear) {
7108                 *tx_stat += tx_counter;
7109                 *rx_stat += rx_counter;
7110         } else {
7111                 if (!offset_loaded) {
7112                         *tx_offset = tx_counter;
7113                         *rx_offset = rx_counter;
7114                 }
7115
7116                 *tx_stat = (tx_counter >= *tx_offset) ?
7117                         (u32)(tx_counter - *tx_offset) :
7118                         (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7119                 *rx_stat = (rx_counter >= *rx_offset) ?
7120                         (u32)(rx_counter - *rx_offset) :
7121                         (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7122         }
7123 err:
7124         return retval;
7125 }
7126
7127 /**
7128  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7129  * @hw: pointer to the hw struct
7130  * @reg_addr: register address
7131  * @reg_val: ptr to register value
7132  * @cmd_details: pointer to command details structure or NULL
7133  *
7134  * Use the firmware to read the Rx control register,
7135  * especially useful if the Rx unit is under heavy pressure
7136  **/
7137 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7138                                 u32 reg_addr, u32 *reg_val,
7139                                 struct i40e_asq_cmd_details *cmd_details)
7140 {
7141         struct i40e_aq_desc desc;
7142         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7143                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7144         enum i40e_status_code status;
7145
7146         if (reg_val == NULL)
7147                 return I40E_ERR_PARAM;
7148
7149         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7150
7151         cmd_resp->address = CPU_TO_LE32(reg_addr);
7152
7153         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7154
7155         if (status == I40E_SUCCESS)
7156                 *reg_val = LE32_TO_CPU(cmd_resp->value);
7157
7158         return status;
7159 }
7160
7161 /**
7162  * i40e_read_rx_ctl - read from an Rx control register
7163  * @hw: pointer to the hw struct
7164  * @reg_addr: register address
7165  **/
7166 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7167 {
7168         enum i40e_status_code status = I40E_SUCCESS;
7169         bool use_register;
7170         int retry = 5;
7171         u32 val = 0;
7172
7173         use_register = (((hw->aq.api_maj_ver == 1) &&
7174                         (hw->aq.api_min_ver < 5)) ||
7175                         (hw->mac.type == I40E_MAC_X722));
7176         if (!use_register) {
7177 do_retry:
7178                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7179                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7180                         i40e_msec_delay(1);
7181                         retry--;
7182                         goto do_retry;
7183                 }
7184         }
7185
7186         /* if the AQ access failed, try the old-fashioned way */
7187         if (status || use_register)
7188                 val = rd32(hw, reg_addr);
7189
7190         return val;
7191 }
7192
7193 /**
7194  * i40e_aq_rx_ctl_write_register
7195  * @hw: pointer to the hw struct
7196  * @reg_addr: register address
7197  * @reg_val: register value
7198  * @cmd_details: pointer to command details structure or NULL
7199  *
7200  * Use the firmware to write to an Rx control register,
7201  * especially useful if the Rx unit is under heavy pressure
7202  **/
7203 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7204                                 u32 reg_addr, u32 reg_val,
7205                                 struct i40e_asq_cmd_details *cmd_details)
7206 {
7207         struct i40e_aq_desc desc;
7208         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7209                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7210         enum i40e_status_code status;
7211
7212         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7213
7214         cmd->address = CPU_TO_LE32(reg_addr);
7215         cmd->value = CPU_TO_LE32(reg_val);
7216
7217         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7218
7219         return status;
7220 }
7221
7222 /**
7223  * i40e_write_rx_ctl - write to an Rx control register
7224  * @hw: pointer to the hw struct
7225  * @reg_addr: register address
7226  * @reg_val: register value
7227  **/
7228 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7229 {
7230         enum i40e_status_code status = I40E_SUCCESS;
7231         bool use_register;
7232         int retry = 5;
7233
7234         use_register = (((hw->aq.api_maj_ver == 1) &&
7235                         (hw->aq.api_min_ver < 5)) ||
7236                         (hw->mac.type == I40E_MAC_X722));
7237         if (!use_register) {
7238 do_retry:
7239                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7240                                                        reg_val, NULL);
7241                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7242                         i40e_msec_delay(1);
7243                         retry--;
7244                         goto do_retry;
7245                 }
7246         }
7247
7248         /* if the AQ access failed, try the old-fashioned way */
7249         if (status || use_register)
7250                 wr32(hw, reg_addr, reg_val);
7251 }
7252
7253 /**
7254  * i40e_mdio_if_number_selection - MDIO I/F number selection
7255  * @hw: pointer to the hw struct
7256  * @set_mdio: use MDIO I/F number specified by mdio_num
7257  * @mdio_num: MDIO I/F number
7258  * @cmd: pointer to PHY Register command structure
7259  **/
7260 static void
7261 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7262                               struct i40e_aqc_phy_register_access *cmd)
7263 {
7264         if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7265                 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7266                         cmd->cmd_flags |=
7267                                 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7268                                 ((mdio_num <<
7269                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7270                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7271                 else
7272                         i40e_debug(hw, I40E_DEBUG_PHY,
7273                                    "MDIO I/F number selection not supported by current FW version.\n");
7274         }
7275 }
7276
7277 /**
7278  * i40e_aq_set_phy_register_ext
7279  * @hw: pointer to the hw struct
7280  * @phy_select: select which phy should be accessed
7281  * @dev_addr: PHY device address
7282  * @page_change: enable auto page change
7283  * @set_mdio: use MDIO I/F number specified by mdio_num
7284  * @mdio_num: MDIO I/F number
7285  * @reg_addr: PHY register address
7286  * @reg_val: new register value
7287  * @cmd_details: pointer to command details structure or NULL
7288  *
7289  * Write the external PHY register.
7290  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7291  * may use simple wrapper i40e_aq_set_phy_register.
7292  **/
7293 enum i40e_status_code
7294 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7295                              u8 phy_select, u8 dev_addr, bool page_change,
7296                              bool set_mdio, u8 mdio_num,
7297                              u32 reg_addr, u32 reg_val,
7298                              struct i40e_asq_cmd_details *cmd_details)
7299 {
7300         struct i40e_aq_desc desc;
7301         struct i40e_aqc_phy_register_access *cmd =
7302                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7303         enum i40e_status_code status;
7304
7305         i40e_fill_default_direct_cmd_desc(&desc,
7306                                           i40e_aqc_opc_set_phy_register);
7307
7308         cmd->phy_interface = phy_select;
7309         cmd->dev_addres = dev_addr;
7310         cmd->reg_address = CPU_TO_LE32(reg_addr);
7311         cmd->reg_value = CPU_TO_LE32(reg_val);
7312
7313         if (!page_change)
7314                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7315
7316         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7317
7318         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7319
7320         return status;
7321 }
7322
7323 /**
7324  * i40e_aq_get_phy_register_ext
7325  * @hw: pointer to the hw struct
7326  * @phy_select: select which phy should be accessed
7327  * @dev_addr: PHY device address
7328  * @page_change: enable auto page change
7329  * @set_mdio: use MDIO I/F number specified by mdio_num
7330  * @mdio_num: MDIO I/F number
7331  * @reg_addr: PHY register address
7332  * @reg_val: read register value
7333  * @cmd_details: pointer to command details structure or NULL
7334  *
7335  * Read the external PHY register.
7336  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7337  * may use simple wrapper i40e_aq_get_phy_register.
7338  **/
7339 enum i40e_status_code
7340 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7341                              u8 phy_select, u8 dev_addr, bool page_change,
7342                              bool set_mdio, u8 mdio_num,
7343                              u32 reg_addr, u32 *reg_val,
7344                              struct i40e_asq_cmd_details *cmd_details)
7345 {
7346         struct i40e_aq_desc desc;
7347         struct i40e_aqc_phy_register_access *cmd =
7348                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7349         enum i40e_status_code status;
7350
7351         i40e_fill_default_direct_cmd_desc(&desc,
7352                                           i40e_aqc_opc_get_phy_register);
7353
7354         cmd->phy_interface = phy_select;
7355         cmd->dev_addres = dev_addr;
7356         cmd->reg_address = CPU_TO_LE32(reg_addr);
7357
7358         if (!page_change)
7359                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7360
7361         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7362
7363         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7364         if (!status)
7365                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7366
7367         return status;
7368 }
7369
7370 /**
7371  * i40e_aq_run_phy_activity
7372  * @hw: pointer to the hw struct
7373  * @activity_id: ID of DNL activity to run
7374  * @dnl_opcode: opcode passed to DNL script
7375  * @cmd_status: pointer to memory to write return value of DNL script
7376  * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7377  * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7378  * @cmd_details: pointer to command details structure or NULL
7379  *
7380  * Run DNL admin command.
7381  **/
7382 enum i40e_status_code
7383 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7384                          u32 *cmd_status, u32 *data0, u32 *data1,
7385                          struct i40e_asq_cmd_details *cmd_details)
7386 {
7387         struct i40e_aqc_run_phy_activity *cmd;
7388         enum i40e_status_code retval;
7389         struct i40e_aq_desc desc;
7390
7391         cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7392
7393         if (!cmd_status || !data0 || !data1) {
7394                 retval = I40E_ERR_PARAM;
7395                 goto err;
7396         }
7397
7398         i40e_fill_default_direct_cmd_desc(&desc,
7399                                           i40e_aqc_opc_run_phy_activity);
7400
7401         cmd->activity_id = CPU_TO_LE16(activity_id);
7402         cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7403
7404         retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7405         if (retval)
7406                 goto err;
7407
7408         *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7409         *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7410         *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7411 err:
7412         return retval;
7413 }
7414
7415 #ifdef VF_DRIVER
7416
7417 /**
7418  * i40e_aq_send_msg_to_pf
7419  * @hw: pointer to the hardware structure
7420  * @v_opcode: opcodes for VF-PF communication
7421  * @v_retval: return error code
7422  * @msg: pointer to the msg buffer
7423  * @msglen: msg length
7424  * @cmd_details: pointer to command details
7425  *
7426  * Send message to PF driver using admin queue. By default, this message
7427  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7428  * completion before returning.
7429  **/
7430 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7431                                 enum virtchnl_ops v_opcode,
7432                                 enum i40e_status_code v_retval,
7433                                 u8 *msg, u16 msglen,
7434                                 struct i40e_asq_cmd_details *cmd_details)
7435 {
7436         struct i40e_aq_desc desc;
7437         struct i40e_asq_cmd_details details;
7438         enum i40e_status_code status;
7439
7440         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7441         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7442         desc.cookie_high = CPU_TO_LE32(v_opcode);
7443         desc.cookie_low = CPU_TO_LE32(v_retval);
7444         if (msglen) {
7445                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7446                                                 | I40E_AQ_FLAG_RD));
7447                 if (msglen > I40E_AQ_LARGE_BUF)
7448                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7449                 desc.datalen = CPU_TO_LE16(msglen);
7450         }
7451         if (!cmd_details) {
7452                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7453                 details.async = true;
7454                 cmd_details = &details;
7455         }
7456         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7457                                        msglen, cmd_details);
7458         return status;
7459 }
7460
7461 /**
7462  * i40e_vf_parse_hw_config
7463  * @hw: pointer to the hardware structure
7464  * @msg: pointer to the virtual channel VF resource structure
7465  *
7466  * Given a VF resource message from the PF, populate the hw struct
7467  * with appropriate information.
7468  **/
7469 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7470                              struct virtchnl_vf_resource *msg)
7471 {
7472         struct virtchnl_vsi_resource *vsi_res;
7473         int i;
7474
7475         vsi_res = &msg->vsi_res[0];
7476
7477         hw->dev_caps.num_vsis = msg->num_vsis;
7478         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7479         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7480         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7481         hw->dev_caps.dcb = msg->vf_cap_flags &
7482                            VIRTCHNL_VF_OFFLOAD_L2;
7483         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7484                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7485         for (i = 0; i < msg->num_vsis; i++) {
7486                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7487                         i40e_memcpy(hw->mac.perm_addr,
7488                                     vsi_res->default_mac_addr,
7489                                     ETH_ALEN,
7490                                     I40E_NONDMA_TO_NONDMA);
7491                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7492                                     ETH_ALEN,
7493                                     I40E_NONDMA_TO_NONDMA);
7494                 }
7495                 vsi_res++;
7496         }
7497 }
7498
7499 /**
7500  * i40e_vf_reset
7501  * @hw: pointer to the hardware structure
7502  *
7503  * Send a VF_RESET message to the PF. Does not wait for response from PF
7504  * as none will be forthcoming. Immediately after calling this function,
7505  * the admin queue should be shut down and (optionally) reinitialized.
7506  **/
7507 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7508 {
7509         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7510                                       I40E_SUCCESS, NULL, 0, NULL);
7511 }
7512 #endif /* VF_DRIVER */
7513
7514 /**
7515  * i40e_aq_set_arp_proxy_config
7516  * @hw: pointer to the HW structure
7517  * @proxy_config: pointer to proxy config command table struct
7518  * @cmd_details: pointer to command details
7519  *
7520  * Set ARP offload parameters from pre-populated
7521  * i40e_aqc_arp_proxy_data struct
7522  **/
7523 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7524                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7525                                 struct i40e_asq_cmd_details *cmd_details)
7526 {
7527         struct i40e_aq_desc desc;
7528         enum i40e_status_code status;
7529
7530         if (!proxy_config)
7531                 return I40E_ERR_PARAM;
7532
7533         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7534
7535         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7536         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7537         desc.params.external.addr_high =
7538                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7539         desc.params.external.addr_low =
7540                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7541         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7542
7543         status = i40e_asq_send_command(hw, &desc, proxy_config,
7544                                        sizeof(struct i40e_aqc_arp_proxy_data),
7545                                        cmd_details);
7546
7547         return status;
7548 }
7549
7550 /**
7551  * i40e_aq_opc_set_ns_proxy_table_entry
7552  * @hw: pointer to the HW structure
7553  * @ns_proxy_table_entry: pointer to NS table entry command struct
7554  * @cmd_details: pointer to command details
7555  *
7556  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7557  * from pre-populated i40e_aqc_ns_proxy_data struct
7558  **/
7559 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7560                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7561                         struct i40e_asq_cmd_details *cmd_details)
7562 {
7563         struct i40e_aq_desc desc;
7564         enum i40e_status_code status;
7565
7566         if (!ns_proxy_table_entry)
7567                 return I40E_ERR_PARAM;
7568
7569         i40e_fill_default_direct_cmd_desc(&desc,
7570                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7571
7572         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7573         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7574         desc.params.external.addr_high =
7575                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7576         desc.params.external.addr_low =
7577                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7578         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7579
7580         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7581                                        sizeof(struct i40e_aqc_ns_proxy_data),
7582                                        cmd_details);
7583
7584         return status;
7585 }
7586
7587 /**
7588  * i40e_aq_set_clear_wol_filter
7589  * @hw: pointer to the hw struct
7590  * @filter_index: index of filter to modify (0-7)
7591  * @filter: buffer containing filter to be set
7592  * @set_filter: true to set filter, false to clear filter
7593  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7594  *              if false, pass through packets may cause wake-up
7595  * @filter_valid: true if filter action is valid
7596  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7597  * @cmd_details: pointer to command details structure or NULL
7598  *
7599  * Set or clear WoL filter for port attached to the PF
7600  **/
7601 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7602                                 u8 filter_index,
7603                                 struct i40e_aqc_set_wol_filter_data *filter,
7604                                 bool set_filter, bool no_wol_tco,
7605                                 bool filter_valid, bool no_wol_tco_valid,
7606                                 struct i40e_asq_cmd_details *cmd_details)
7607 {
7608         struct i40e_aq_desc desc;
7609         struct i40e_aqc_set_wol_filter *cmd =
7610                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7611         enum i40e_status_code status;
7612         u16 cmd_flags = 0;
7613         u16 valid_flags = 0;
7614         u16 buff_len = 0;
7615
7616         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7617
7618         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7619                 return  I40E_ERR_PARAM;
7620         cmd->filter_index = CPU_TO_LE16(filter_index);
7621
7622         if (set_filter) {
7623                 if (!filter)
7624                         return  I40E_ERR_PARAM;
7625
7626                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7627                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7628         }
7629
7630         if (no_wol_tco)
7631                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7632         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7633
7634         if (filter_valid)
7635                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7636         if (no_wol_tco_valid)
7637                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7638         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7639
7640         buff_len = sizeof(*filter);
7641         desc.datalen = CPU_TO_LE16(buff_len);
7642
7643         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7644         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7645
7646         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7647         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7648
7649         status = i40e_asq_send_command(hw, &desc, filter,
7650                                        buff_len, cmd_details);
7651
7652         return status;
7653 }
7654
7655 /**
7656  * i40e_aq_get_wake_event_reason
7657  * @hw: pointer to the hw struct
7658  * @wake_reason: return value, index of matching filter
7659  * @cmd_details: pointer to command details structure or NULL
7660  *
7661  * Get information for the reason of a Wake Up event
7662  **/
7663 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7664                                 u16 *wake_reason,
7665                                 struct i40e_asq_cmd_details *cmd_details)
7666 {
7667         struct i40e_aq_desc desc;
7668         struct i40e_aqc_get_wake_reason_completion *resp =
7669                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7670         enum i40e_status_code status;
7671
7672         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7673
7674         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7675
7676         if (status == I40E_SUCCESS)
7677                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7678
7679         return status;
7680 }
7681
7682 /**
7683 * i40e_aq_clear_all_wol_filters
7684 * @hw: pointer to the hw struct
7685 * @cmd_details: pointer to command details structure or NULL
7686 *
7687 * Get information for the reason of a Wake Up event
7688 **/
7689 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7690         struct i40e_asq_cmd_details *cmd_details)
7691 {
7692         struct i40e_aq_desc desc;
7693         enum i40e_status_code status;
7694
7695         i40e_fill_default_direct_cmd_desc(&desc,
7696                                           i40e_aqc_opc_clear_all_wol_filters);
7697
7698         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7699
7700         return status;
7701 }
7702
7703 /**
7704  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7705  * @hw: pointer to the hw struct
7706  * @buff: command buffer (size in bytes = buff_size)
7707  * @buff_size: buffer size in bytes
7708  * @track_id: package tracking id
7709  * @error_offset: returns error offset
7710  * @error_info: returns error information
7711  * @cmd_details: pointer to command details structure or NULL
7712  **/
7713 enum
7714 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7715                                    u16 buff_size, u32 track_id,
7716                                    u32 *error_offset, u32 *error_info,
7717                                    struct i40e_asq_cmd_details *cmd_details)
7718 {
7719         struct i40e_aq_desc desc;
7720         struct i40e_aqc_write_personalization_profile *cmd =
7721                 (struct i40e_aqc_write_personalization_profile *)
7722                 &desc.params.raw;
7723         struct i40e_aqc_write_ddp_resp *resp;
7724         enum i40e_status_code status;
7725
7726         i40e_fill_default_direct_cmd_desc(&desc,
7727                                   i40e_aqc_opc_write_personalization_profile);
7728
7729         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7730         if (buff_size > I40E_AQ_LARGE_BUF)
7731                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7732
7733         desc.datalen = CPU_TO_LE16(buff_size);
7734
7735         cmd->profile_track_id = CPU_TO_LE32(track_id);
7736
7737         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7738         if (!status) {
7739                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7740                 if (error_offset)
7741                         *error_offset = LE32_TO_CPU(resp->error_offset);
7742                 if (error_info)
7743                         *error_info = LE32_TO_CPU(resp->error_info);
7744         }
7745
7746         return status;
7747 }
7748
7749 /**
7750  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7751  * @hw: pointer to the hw struct
7752  * @buff: command buffer (size in bytes = buff_size)
7753  * @buff_size: buffer size in bytes
7754  * @flags: AdminQ command flags
7755  * @cmd_details: pointer to command details structure or NULL
7756  **/
7757 enum
7758 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7759                                       u16 buff_size, u8 flags,
7760                                       struct i40e_asq_cmd_details *cmd_details)
7761 {
7762         struct i40e_aq_desc desc;
7763         struct i40e_aqc_get_applied_profiles *cmd =
7764                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7765         enum i40e_status_code status;
7766
7767         i40e_fill_default_direct_cmd_desc(&desc,
7768                           i40e_aqc_opc_get_personalization_profile_list);
7769
7770         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7771         if (buff_size > I40E_AQ_LARGE_BUF)
7772                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7773         desc.datalen = CPU_TO_LE16(buff_size);
7774
7775         cmd->flags = flags;
7776
7777         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7778
7779         return status;
7780 }
7781
7782 /**
7783  * i40e_find_segment_in_package
7784  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7785  * @pkg_hdr: pointer to the package header to be searched
7786  *
7787  * This function searches a package file for a particular segment type. On
7788  * success it returns a pointer to the segment header, otherwise it will
7789  * return NULL.
7790  **/
7791 struct i40e_generic_seg_header *
7792 i40e_find_segment_in_package(u32 segment_type,
7793                              struct i40e_package_header *pkg_hdr)
7794 {
7795         struct i40e_generic_seg_header *segment;
7796         u32 i;
7797
7798         /* Search all package segments for the requested segment type */
7799         for (i = 0; i < pkg_hdr->segment_count; i++) {
7800                 segment =
7801                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7802                          pkg_hdr->segment_offset[i]);
7803
7804                 if (segment->type == segment_type)
7805                         return segment;
7806         }
7807
7808         return NULL;
7809 }
7810
7811 /* Get section table in profile */
7812 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7813         do {                                                            \
7814                 struct i40e_profile_segment *p = (profile);             \
7815                 u32 count;                                              \
7816                 u32 *nvm;                                               \
7817                 count = p->device_table_count;                          \
7818                 nvm = (u32 *)&p->device_table[count];                   \
7819                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7820         } while (0)
7821
7822 /* Get section header in profile */
7823 #define I40E_SECTION_HEADER(profile, offset)                            \
7824         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7825
7826 /**
7827  * i40e_find_section_in_profile
7828  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7829  * @profile: pointer to the i40e segment header to be searched
7830  *
7831  * This function searches i40e segment for a particular section type. On
7832  * success it returns a pointer to the section header, otherwise it will
7833  * return NULL.
7834  **/
7835 struct i40e_profile_section_header *
7836 i40e_find_section_in_profile(u32 section_type,
7837                              struct i40e_profile_segment *profile)
7838 {
7839         struct i40e_profile_section_header *sec;
7840         struct i40e_section_table *sec_tbl;
7841         u32 sec_off;
7842         u32 i;
7843
7844         if (profile->header.type != SEGMENT_TYPE_I40E)
7845                 return NULL;
7846
7847         I40E_SECTION_TABLE(profile, sec_tbl);
7848
7849         for (i = 0; i < sec_tbl->section_count; i++) {
7850                 sec_off = sec_tbl->section_offset[i];
7851                 sec = I40E_SECTION_HEADER(profile, sec_off);
7852                 if (sec->section.type == section_type)
7853                         return sec;
7854         }
7855
7856         return NULL;
7857 }
7858
7859 /**
7860  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7861  * @hw: pointer to the hw struct
7862  * @aq: command buffer containing all data to execute AQ
7863  **/
7864 STATIC enum
7865 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7866                                           struct i40e_profile_aq_section *aq)
7867 {
7868         enum i40e_status_code status;
7869         struct i40e_aq_desc desc;
7870         u8 *msg = NULL;
7871         u16 msglen;
7872
7873         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7874         desc.flags |= CPU_TO_LE16(aq->flags);
7875         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7876                     I40E_NONDMA_TO_NONDMA);
7877
7878         msglen = aq->datalen;
7879         if (msglen) {
7880                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7881                                                 I40E_AQ_FLAG_RD));
7882                 if (msglen > I40E_AQ_LARGE_BUF)
7883                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7884                 desc.datalen = CPU_TO_LE16(msglen);
7885                 msg = &aq->data[0];
7886         }
7887
7888         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7889
7890         if (status != I40E_SUCCESS) {
7891                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7892                            "unable to exec DDP AQ opcode %u, error %d\n",
7893                            aq->opcode, status);
7894                 return status;
7895         }
7896
7897         /* copy returned desc to aq_buf */
7898         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7899                     I40E_NONDMA_TO_NONDMA);
7900
7901         return I40E_SUCCESS;
7902 }
7903
7904 /**
7905  * i40e_validate_profile
7906  * @hw: pointer to the hardware structure
7907  * @profile: pointer to the profile segment of the package to be validated
7908  * @track_id: package tracking id
7909  * @rollback: flag if the profile is for rollback.
7910  *
7911  * Validates supported devices and profile's sections.
7912  */
7913 STATIC enum i40e_status_code
7914 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7915                       u32 track_id, bool rollback)
7916 {
7917         struct i40e_profile_section_header *sec = NULL;
7918         enum i40e_status_code status = I40E_SUCCESS;
7919         struct i40e_section_table *sec_tbl;
7920         u32 vendor_dev_id;
7921         u32 dev_cnt;
7922         u32 sec_off;
7923         u32 i;
7924
7925         if (track_id == I40E_DDP_TRACKID_INVALID) {
7926                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7927                 return I40E_NOT_SUPPORTED;
7928         }
7929
7930         dev_cnt = profile->device_table_count;
7931         for (i = 0; i < dev_cnt; i++) {
7932                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7933                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7934                     hw->device_id == (vendor_dev_id & 0xFFFF))
7935                         break;
7936         }
7937         if (dev_cnt && (i == dev_cnt)) {
7938                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7939                            "Device doesn't support DDP\n");
7940                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7941         }
7942
7943         I40E_SECTION_TABLE(profile, sec_tbl);
7944
7945         /* Validate sections types */
7946         for (i = 0; i < sec_tbl->section_count; i++) {
7947                 sec_off = sec_tbl->section_offset[i];
7948                 sec = I40E_SECTION_HEADER(profile, sec_off);
7949                 if (rollback) {
7950                         if (sec->section.type == SECTION_TYPE_MMIO ||
7951                             sec->section.type == SECTION_TYPE_AQ ||
7952                             sec->section.type == SECTION_TYPE_RB_AQ) {
7953                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7954                                            "Not a roll-back package\n");
7955                                 return I40E_NOT_SUPPORTED;
7956                         }
7957                 } else {
7958                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7959                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7960                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7961                                            "Not an original package\n");
7962                                 return I40E_NOT_SUPPORTED;
7963                         }
7964                 }
7965         }
7966
7967         return status;
7968 }
7969
7970 /**
7971  * i40e_write_profile
7972  * @hw: pointer to the hardware structure
7973  * @profile: pointer to the profile segment of the package to be downloaded
7974  * @track_id: package tracking id
7975  *
7976  * Handles the download of a complete package.
7977  */
7978 enum i40e_status_code
7979 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7980                    u32 track_id)
7981 {
7982         enum i40e_status_code status = I40E_SUCCESS;
7983         struct i40e_section_table *sec_tbl;
7984         struct i40e_profile_section_header *sec = NULL;
7985         struct i40e_profile_aq_section *ddp_aq;
7986         u32 section_size = 0;
7987         u32 offset = 0, info = 0;
7988         u32 sec_off;
7989         u32 i;
7990
7991         status = i40e_validate_profile(hw, profile, track_id, false);
7992         if (status)
7993                 return status;
7994
7995         I40E_SECTION_TABLE(profile, sec_tbl);
7996
7997         for (i = 0; i < sec_tbl->section_count; i++) {
7998                 sec_off = sec_tbl->section_offset[i];
7999                 sec = I40E_SECTION_HEADER(profile, sec_off);
8000                 /* Process generic admin command */
8001                 if (sec->section.type == SECTION_TYPE_AQ) {
8002                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
8003                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
8004                         if (status) {
8005                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8006                                            "Failed to execute aq: section %d, opcode %u\n",
8007                                            i, ddp_aq->opcode);
8008                                 break;
8009                         }
8010                         sec->section.type = SECTION_TYPE_RB_AQ;
8011                 }
8012
8013                 /* Skip any non-mmio sections */
8014                 if (sec->section.type != SECTION_TYPE_MMIO)
8015                         continue;
8016
8017                 section_size = sec->section.size +
8018                         sizeof(struct i40e_profile_section_header);
8019
8020                 /* Write MMIO section */
8021                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8022                                            track_id, &offset, &info, NULL);
8023                 if (status) {
8024                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8025                                    "Failed to write profile: section %d, offset %d, info %d\n",
8026                                    i, offset, info);
8027                         break;
8028                 }
8029         }
8030         return status;
8031 }
8032
8033 /**
8034  * i40e_rollback_profile
8035  * @hw: pointer to the hardware structure
8036  * @profile: pointer to the profile segment of the package to be removed
8037  * @track_id: package tracking id
8038  *
8039  * Rolls back previously loaded package.
8040  */
8041 enum i40e_status_code
8042 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8043                       u32 track_id)
8044 {
8045         struct i40e_profile_section_header *sec = NULL;
8046         enum i40e_status_code status = I40E_SUCCESS;
8047         struct i40e_section_table *sec_tbl;
8048         u32 offset = 0, info = 0;
8049         u32 section_size = 0;
8050         u32 sec_off;
8051         int i;
8052
8053         status = i40e_validate_profile(hw, profile, track_id, true);
8054         if (status)
8055                 return status;
8056
8057         I40E_SECTION_TABLE(profile, sec_tbl);
8058
8059         /* For rollback write sections in reverse */
8060         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8061                 sec_off = sec_tbl->section_offset[i];
8062                 sec = I40E_SECTION_HEADER(profile, sec_off);
8063
8064                 /* Skip any non-rollback sections */
8065                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8066                         continue;
8067
8068                 section_size = sec->section.size +
8069                         sizeof(struct i40e_profile_section_header);
8070
8071                 /* Write roll-back MMIO section */
8072                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8073                                            track_id, &offset, &info, NULL);
8074                 if (status) {
8075                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8076                                    "Failed to write profile: section %d, offset %d, info %d\n",
8077                                    i, offset, info);
8078                         break;
8079                 }
8080         }
8081         return status;
8082 }
8083
8084 /**
8085  * i40e_add_pinfo_to_list
8086  * @hw: pointer to the hardware structure
8087  * @profile: pointer to the profile segment of the package
8088  * @profile_info_sec: buffer for information section
8089  * @track_id: package tracking id
8090  *
8091  * Register a profile to the list of loaded profiles.
8092  */
8093 enum i40e_status_code
8094 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8095                        struct i40e_profile_segment *profile,
8096                        u8 *profile_info_sec, u32 track_id)
8097 {
8098         enum i40e_status_code status = I40E_SUCCESS;
8099         struct i40e_profile_section_header *sec = NULL;
8100         struct i40e_profile_info *pinfo;
8101         u32 offset = 0, info = 0;
8102
8103         sec = (struct i40e_profile_section_header *)profile_info_sec;
8104         sec->tbl_size = 1;
8105         sec->data_end = sizeof(struct i40e_profile_section_header) +
8106                         sizeof(struct i40e_profile_info);
8107         sec->section.type = SECTION_TYPE_INFO;
8108         sec->section.offset = sizeof(struct i40e_profile_section_header);
8109         sec->section.size = sizeof(struct i40e_profile_info);
8110         pinfo = (struct i40e_profile_info *)(profile_info_sec +
8111                                              sec->section.offset);
8112         pinfo->track_id = track_id;
8113         pinfo->version = profile->version;
8114         pinfo->op = I40E_DDP_ADD_TRACKID;
8115         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8116                     I40E_NONDMA_TO_NONDMA);
8117
8118         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8119                                    track_id, &offset, &info, NULL);
8120         return status;
8121 }