drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  19 #else
  20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  21 #endif
  22 {
  23         enum i40e_status_code status = I40E_SUCCESS;
  24
  25         DEBUGFUNC("i40e_set_mac_type\n");
  26
  27         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  28                 switch (hw->device_id) {
  29                 case I40E_DEV_ID_SFP_XL710:
  30                 case I40E_DEV_ID_QEMU:
  31                 case I40E_DEV_ID_KX_B:
  32                 case I40E_DEV_ID_KX_C:
  33                 case I40E_DEV_ID_QSFP_A:
  34                 case I40E_DEV_ID_QSFP_B:
  35                 case I40E_DEV_ID_QSFP_C:
  36                 case I40E_DEV_ID_10G_BASE_T:
  37                 case I40E_DEV_ID_10G_BASE_T4:
  38                 case I40E_DEV_ID_10G_BASE_T_BC:
  39                 case I40E_DEV_ID_10G_B:
  40                 case I40E_DEV_ID_10G_SFP:
  41                 case I40E_DEV_ID_20G_KR2:
  42                 case I40E_DEV_ID_20G_KR2_A:
  43                 case I40E_DEV_ID_25G_B:
  44                 case I40E_DEV_ID_25G_SFP28:
  45                 case I40E_DEV_ID_X710_N3000:
  46                 case I40E_DEV_ID_XXV710_N3000:
  47                         hw->mac.type = I40E_MAC_XL710;
  48                         break;
  49 #ifdef X722_A0_SUPPORT
  50                 case I40E_DEV_ID_X722_A0:
  51 #endif
  52                 case I40E_DEV_ID_KX_X722:
  53                 case I40E_DEV_ID_QSFP_X722:
  54                 case I40E_DEV_ID_SFP_X722:
  55                 case I40E_DEV_ID_1G_BASE_T_X722:
  56                 case I40E_DEV_ID_10G_BASE_T_X722:
  57                 case I40E_DEV_ID_SFP_I_X722:
  58                         hw->mac.type = I40E_MAC_X722;
  59                         break;
  60 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  61                 case I40E_DEV_ID_X722_VF:
  62 #ifdef X722_A0_SUPPORT
  63                 case I40E_DEV_ID_X722_A0_VF:
  64 #endif
  65                         hw->mac.type = I40E_MAC_X722_VF;
  66                         break;
  67 #endif /* INTEGRATED_VF || VF_DRIVER */
  68 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  69                 case I40E_DEV_ID_VF:
  70                 case I40E_DEV_ID_VF_HV:
  71                 case I40E_DEV_ID_ADAPTIVE_VF:
  72                         hw->mac.type = I40E_MAC_VF;
  73                         break;
  74 #endif
  75                 default:
  76                         hw->mac.type = I40E_MAC_GENERIC;
  77                         break;
  78                 }
  79         } else {
  80                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  81         }
  82
  83         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  84                   hw->mac.type, status);
  85         return status;
  86 }
  87
  88 /**
  89  * i40e_aq_str - convert AQ err code to a string
  90  * @hw: pointer to the HW structure
  91  * @aq_err: the AQ error code to convert
  92  **/
  93 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  94 {
  95         switch (aq_err) {
  96         case I40E_AQ_RC_OK:
  97                 return "OK";
  98         case I40E_AQ_RC_EPERM:
  99                 return "I40E_AQ_RC_EPERM";
 100         case I40E_AQ_RC_ENOENT:
 101                 return "I40E_AQ_RC_ENOENT";
 102         case I40E_AQ_RC_ESRCH:
 103                 return "I40E_AQ_RC_ESRCH";
 104         case I40E_AQ_RC_EINTR:
 105                 return "I40E_AQ_RC_EINTR";
 106         case I40E_AQ_RC_EIO:
 107                 return "I40E_AQ_RC_EIO";
 108         case I40E_AQ_RC_ENXIO:
 109                 return "I40E_AQ_RC_ENXIO";
 110         case I40E_AQ_RC_E2BIG:
 111                 return "I40E_AQ_RC_E2BIG";
 112         case I40E_AQ_RC_EAGAIN:
 113                 return "I40E_AQ_RC_EAGAIN";
 114         case I40E_AQ_RC_ENOMEM:
 115                 return "I40E_AQ_RC_ENOMEM";
 116         case I40E_AQ_RC_EACCES:
 117                 return "I40E_AQ_RC_EACCES";
 118         case I40E_AQ_RC_EFAULT:
 119                 return "I40E_AQ_RC_EFAULT";
 120         case I40E_AQ_RC_EBUSY:
 121                 return "I40E_AQ_RC_EBUSY";
 122         case I40E_AQ_RC_EEXIST:
 123                 return "I40E_AQ_RC_EEXIST";
 124         case I40E_AQ_RC_EINVAL:
 125                 return "I40E_AQ_RC_EINVAL";
 126         case I40E_AQ_RC_ENOTTY:
 127                 return "I40E_AQ_RC_ENOTTY";
 128         case I40E_AQ_RC_ENOSPC:
 129                 return "I40E_AQ_RC_ENOSPC";
 130         case I40E_AQ_RC_ENOSYS:
 131                 return "I40E_AQ_RC_ENOSYS";
 132         case I40E_AQ_RC_ERANGE:
 133                 return "I40E_AQ_RC_ERANGE";
 134         case I40E_AQ_RC_EFLUSHED:
 135                 return "I40E_AQ_RC_EFLUSHED";
 136         case I40E_AQ_RC_BAD_ADDR:
 137                 return "I40E_AQ_RC_BAD_ADDR";
 138         case I40E_AQ_RC_EMODE:
 139                 return "I40E_AQ_RC_EMODE";
 140         case I40E_AQ_RC_EFBIG:
 141                 return "I40E_AQ_RC_EFBIG";
 142         }
 143
 144         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 145         return hw->err_str;
 146 }
 147
 148 /**
 149  * i40e_stat_str - convert status err code to a string
 150  * @hw: pointer to the HW structure
 151  * @stat_err: the status error code to convert
 152  **/
 153 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 154 {
 155         switch (stat_err) {
 156         case I40E_SUCCESS:
 157                 return "OK";
 158         case I40E_ERR_NVM:
 159                 return "I40E_ERR_NVM";
 160         case I40E_ERR_NVM_CHECKSUM:
 161                 return "I40E_ERR_NVM_CHECKSUM";
 162         case I40E_ERR_PHY:
 163                 return "I40E_ERR_PHY";
 164         case I40E_ERR_CONFIG:
 165                 return "I40E_ERR_CONFIG";
 166         case I40E_ERR_PARAM:
 167                 return "I40E_ERR_PARAM";
 168         case I40E_ERR_MAC_TYPE:
 169                 return "I40E_ERR_MAC_TYPE";
 170         case I40E_ERR_UNKNOWN_PHY:
 171                 return "I40E_ERR_UNKNOWN_PHY";
 172         case I40E_ERR_LINK_SETUP:
 173                 return "I40E_ERR_LINK_SETUP";
 174         case I40E_ERR_ADAPTER_STOPPED:
 175                 return "I40E_ERR_ADAPTER_STOPPED";
 176         case I40E_ERR_INVALID_MAC_ADDR:
 177                 return "I40E_ERR_INVALID_MAC_ADDR";
 178         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 179                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 180         case I40E_ERR_MASTER_REQUESTS_PENDING:
 181                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 182         case I40E_ERR_INVALID_LINK_SETTINGS:
 183                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 184         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 185                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 186         case I40E_ERR_RESET_FAILED:
 187                 return "I40E_ERR_RESET_FAILED";
 188         case I40E_ERR_SWFW_SYNC:
 189                 return "I40E_ERR_SWFW_SYNC";
 190         case I40E_ERR_NO_AVAILABLE_VSI:
 191                 return "I40E_ERR_NO_AVAILABLE_VSI";
 192         case I40E_ERR_NO_MEMORY:
 193                 return "I40E_ERR_NO_MEMORY";
 194         case I40E_ERR_BAD_PTR:
 195                 return "I40E_ERR_BAD_PTR";
 196         case I40E_ERR_RING_FULL:
 197                 return "I40E_ERR_RING_FULL";
 198         case I40E_ERR_INVALID_PD_ID:
 199                 return "I40E_ERR_INVALID_PD_ID";
 200         case I40E_ERR_INVALID_QP_ID:
 201                 return "I40E_ERR_INVALID_QP_ID";
 202         case I40E_ERR_INVALID_CQ_ID:
 203                 return "I40E_ERR_INVALID_CQ_ID";
 204         case I40E_ERR_INVALID_CEQ_ID:
 205                 return "I40E_ERR_INVALID_CEQ_ID";
 206         case I40E_ERR_INVALID_AEQ_ID:
 207                 return "I40E_ERR_INVALID_AEQ_ID";
 208         case I40E_ERR_INVALID_SIZE:
 209                 return "I40E_ERR_INVALID_SIZE";
 210         case I40E_ERR_INVALID_ARP_INDEX:
 211                 return "I40E_ERR_INVALID_ARP_INDEX";
 212         case I40E_ERR_INVALID_FPM_FUNC_ID:
 213                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 214         case I40E_ERR_QP_INVALID_MSG_SIZE:
 215                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 216         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 217                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 218         case I40E_ERR_INVALID_FRAG_COUNT:
 219                 return "I40E_ERR_INVALID_FRAG_COUNT";
 220         case I40E_ERR_QUEUE_EMPTY:
 221                 return "I40E_ERR_QUEUE_EMPTY";
 222         case I40E_ERR_INVALID_ALIGNMENT:
 223                 return "I40E_ERR_INVALID_ALIGNMENT";
 224         case I40E_ERR_FLUSHED_QUEUE:
 225                 return "I40E_ERR_FLUSHED_QUEUE";
 226         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 227                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 228         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 229                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 230         case I40E_ERR_TIMEOUT:
 231                 return "I40E_ERR_TIMEOUT";
 232         case I40E_ERR_OPCODE_MISMATCH:
 233                 return "I40E_ERR_OPCODE_MISMATCH";
 234         case I40E_ERR_CQP_COMPL_ERROR:
 235                 return "I40E_ERR_CQP_COMPL_ERROR";
 236         case I40E_ERR_INVALID_VF_ID:
 237                 return "I40E_ERR_INVALID_VF_ID";
 238         case I40E_ERR_INVALID_HMCFN_ID:
 239                 return "I40E_ERR_INVALID_HMCFN_ID";
 240         case I40E_ERR_BACKING_PAGE_ERROR:
 241                 return "I40E_ERR_BACKING_PAGE_ERROR";
 242         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 243                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 244         case I40E_ERR_INVALID_PBLE_INDEX:
 245                 return "I40E_ERR_INVALID_PBLE_INDEX";
 246         case I40E_ERR_INVALID_SD_INDEX:
 247                 return "I40E_ERR_INVALID_SD_INDEX";
 248         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 249                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 250         case I40E_ERR_INVALID_SD_TYPE:
 251                 return "I40E_ERR_INVALID_SD_TYPE";
 252         case I40E_ERR_MEMCPY_FAILED:
 253                 return "I40E_ERR_MEMCPY_FAILED";
 254         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 255                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 256         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 257                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 258         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 259                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 260         case I40E_ERR_SRQ_ENABLED:
 261                 return "I40E_ERR_SRQ_ENABLED";
 262         case I40E_ERR_ADMIN_QUEUE_ERROR:
 263                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 264         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 265                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 266         case I40E_ERR_BUF_TOO_SHORT:
 267                 return "I40E_ERR_BUF_TOO_SHORT";
 268         case I40E_ERR_ADMIN_QUEUE_FULL:
 269                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 270         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 271                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 272         case I40E_ERR_BAD_IWARP_CQE:
 273                 return "I40E_ERR_BAD_IWARP_CQE";
 274         case I40E_ERR_NVM_BLANK_MODE:
 275                 return "I40E_ERR_NVM_BLANK_MODE";
 276         case I40E_ERR_NOT_IMPLEMENTED:
 277                 return "I40E_ERR_NOT_IMPLEMENTED";
 278         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 279                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 280         case I40E_ERR_DIAG_TEST_FAILED:
 281                 return "I40E_ERR_DIAG_TEST_FAILED";
 282         case I40E_ERR_NOT_READY:
 283                 return "I40E_ERR_NOT_READY";
 284         case I40E_NOT_SUPPORTED:
 285                 return "I40E_NOT_SUPPORTED";
 286         case I40E_ERR_FIRMWARE_API_VERSION:
 287                 return "I40E_ERR_FIRMWARE_API_VERSION";
 288         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 289                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 290         }
 291
 292         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 293         return hw->err_str;
 294 }
 295
 296 /**
 297  * i40e_debug_aq
 298  * @hw: debug mask related to admin queue
 299  * @mask: debug mask
 300  * @desc: pointer to admin queue descriptor
 301  * @buffer: pointer to command buffer
 302  * @buf_len: max length of buffer
 303  *
 304  * Dumps debug log about adminq command with descriptor contents.
 305  **/
 306 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 307                    void *buffer, u16 buf_len)
 308 {
 309         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 310         u32 effective_mask = hw->debug_mask & mask;
 311         u8 *buf = (u8 *)buffer;
 312         u16 len;
 313         u16 i;
 314
 315         if (!effective_mask || !desc)
 316                 return;
 317
 318         len = LE16_TO_CPU(aq_desc->datalen);
 319
 320         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 321                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 322                    LE16_TO_CPU(aq_desc->opcode),
 323                    LE16_TO_CPU(aq_desc->flags),
 324                    LE16_TO_CPU(aq_desc->datalen),
 325                    LE16_TO_CPU(aq_desc->retval));
 326         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 327                    "\tcookie (h,l) 0x%08X 0x%08X\n",
 328                    LE32_TO_CPU(aq_desc->cookie_high),
 329                    LE32_TO_CPU(aq_desc->cookie_low));
 330         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 331                    "\tparam (0,1)  0x%08X 0x%08X\n",
 332                    LE32_TO_CPU(aq_desc->params.internal.param0),
 333                    LE32_TO_CPU(aq_desc->params.internal.param1));
 334         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 335                    "\taddr (h,l)   0x%08X 0x%08X\n",
 336                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 337                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 338
 339         if (buffer && (buf_len != 0) && (len != 0) &&
 340             (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
 341                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 342                 if (buf_len < len)
 343                         len = buf_len;
 344                 /* write the full 16-byte chunks */
 345                 for (i = 0; i < (len - 16); i += 16)
 346                         i40e_debug(hw, mask,
 347                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 348                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 349                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 350                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 351                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 352                 /* the most we could have left is 16 bytes, pad with zeros */
 353                 if (i < len) {
 354                         char d_buf[16];
 355                         int j, i_sav;
 356
 357                         i_sav = i;
 358                         memset(d_buf, 0, sizeof(d_buf));
 359                         for (j = 0; i < len; j++, i++)
 360                                 d_buf[j] = buf[i];
 361                         i40e_debug(hw, mask,
 362                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 363                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 364                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 365                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 366                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 367                 }
 368         }
 369 }
 370
 371 /**
 372  * i40e_check_asq_alive
 373  * @hw: pointer to the hw struct
 374  *
 375  * Returns true if Queue is enabled else false.
 376  **/
 377 bool i40e_check_asq_alive(struct i40e_hw *hw)
 378 {
 379         if (hw->aq.asq.len)
 380 #ifdef PF_DRIVER
 381 #ifdef INTEGRATED_VF
 382                 if (!i40e_is_vf(hw))
 383                         return !!(rd32(hw, hw->aq.asq.len) &
 384                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 385 #else
 386                 return !!(rd32(hw, hw->aq.asq.len) &
 387                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 388 #endif /* INTEGRATED_VF */
 389 #endif /* PF_DRIVER */
 390 #ifdef VF_DRIVER
 391 #ifdef INTEGRATED_VF
 392                 if (i40e_is_vf(hw))
 393                         return !!(rd32(hw, hw->aq.asq.len) &
 394                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 395 #else
 396                 return !!(rd32(hw, hw->aq.asq.len) &
 397                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 398 #endif /* INTEGRATED_VF */
 399 #endif /* VF_DRIVER */
 400         return false;
 401 }
 402
 403 /**
 404  * i40e_aq_queue_shutdown
 405  * @hw: pointer to the hw struct
 406  * @unloading: is the driver unloading itself
 407  *
 408  * Tell the Firmware that we're shutting down the AdminQ and whether
 409  * or not the driver is unloading as well.
 410  **/
 411 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 412                                              bool unloading)
 413 {
 414         struct i40e_aq_desc desc;
 415         struct i40e_aqc_queue_shutdown *cmd =
 416                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 417         enum i40e_status_code status;
 418
 419         i40e_fill_default_direct_cmd_desc(&desc,
 420                                           i40e_aqc_opc_queue_shutdown);
 421
 422         if (unloading)
 423                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 424         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 425
 426         return status;
 427 }
 428
 429 /**
 430  * i40e_aq_get_set_rss_lut
 431  * @hw: pointer to the hardware structure
 432  * @vsi_id: vsi fw index
 433  * @pf_lut: for PF table set true, for VSI table set false
 434  * @lut: pointer to the lut buffer provided by the caller
 435  * @lut_size: size of the lut buffer
 436  * @set: set true to set the table, false to get the table
 437  *
 438  * Internal function to get or set RSS look up table
 439  **/
 440 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 441                                                      u16 vsi_id, bool pf_lut,
 442                                                      u8 *lut, u16 lut_size,
 443                                                      bool set)
 444 {
 445         enum i40e_status_code status;
 446         struct i40e_aq_desc desc;
 447         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 448                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 449
 450         if (set)
 451                 i40e_fill_default_direct_cmd_desc(&desc,
 452                                                   i40e_aqc_opc_set_rss_lut);
 453         else
 454                 i40e_fill_default_direct_cmd_desc(&desc,
 455                                                   i40e_aqc_opc_get_rss_lut);
 456
 457         /* Indirect command */
 458         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 459         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 460
 461         cmd_resp->vsi_id =
 462                         CPU_TO_LE16((u16)((vsi_id <<
 463                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 464                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 465         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 466
 467         if (pf_lut)
 468                 cmd_resp->flags |= CPU_TO_LE16((u16)
 469                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 470                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 471                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 472         else
 473                 cmd_resp->flags |= CPU_TO_LE16((u16)
 474                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 475                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 476                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 477
 478         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 479
 480         return status;
 481 }
 482
 483 /**
 484  * i40e_aq_get_rss_lut
 485  * @hw: pointer to the hardware structure
 486  * @vsi_id: vsi fw index
 487  * @pf_lut: for PF table set true, for VSI table set false
 488  * @lut: pointer to the lut buffer provided by the caller
 489  * @lut_size: size of the lut buffer
 490  *
 491  * get the RSS lookup table, PF or VSI type
 492  **/
 493 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 494                                           bool pf_lut, u8 *lut, u16 lut_size)
 495 {
 496         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 497                                        false);
 498 }
 499
 500 /**
 501  * i40e_aq_set_rss_lut
 502  * @hw: pointer to the hardware structure
 503  * @vsi_id: vsi fw index
 504  * @pf_lut: for PF table set true, for VSI table set false
 505  * @lut: pointer to the lut buffer provided by the caller
 506  * @lut_size: size of the lut buffer
 507  *
 508  * set the RSS lookup table, PF or VSI type
 509  **/
 510 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 511                                           bool pf_lut, u8 *lut, u16 lut_size)
 512 {
 513         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 514 }
 515
 516 /**
 517  * i40e_aq_get_set_rss_key
 518  * @hw: pointer to the hw struct
 519  * @vsi_id: vsi fw index
 520  * @key: pointer to key info struct
 521  * @set: set true to set the key, false to get the key
 522  *
 523  * get the RSS key per VSI
 524  **/
 525 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 526                                       u16 vsi_id,
 527                                       struct i40e_aqc_get_set_rss_key_data *key,
 528                                       bool set)
 529 {
 530         enum i40e_status_code status;
 531         struct i40e_aq_desc desc;
 532         struct i40e_aqc_get_set_rss_key *cmd_resp =
 533                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 534         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 535
 536         if (set)
 537                 i40e_fill_default_direct_cmd_desc(&desc,
 538                                                   i40e_aqc_opc_set_rss_key);
 539         else
 540                 i40e_fill_default_direct_cmd_desc(&desc,
 541                                                   i40e_aqc_opc_get_rss_key);
 542
 543         /* Indirect command */
 544         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 545         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 546
 547         cmd_resp->vsi_id =
 548                         CPU_TO_LE16((u16)((vsi_id <<
 549                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 550                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 551         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 552
 553         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 554
 555         return status;
 556 }
 557
 558 /**
 559  * i40e_aq_get_rss_key
 560  * @hw: pointer to the hw struct
 561  * @vsi_id: vsi fw index
 562  * @key: pointer to key info struct
 563  *
 564  **/
 565 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 566                                       u16 vsi_id,
 567                                       struct i40e_aqc_get_set_rss_key_data *key)
 568 {
 569         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 570 }
 571
 572 /**
 573  * i40e_aq_set_rss_key
 574  * @hw: pointer to the hw struct
 575  * @vsi_id: vsi fw index
 576  * @key: pointer to key info struct
 577  *
 578  * set the RSS key per VSI
 579  **/
 580 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 581                                       u16 vsi_id,
 582                                       struct i40e_aqc_get_set_rss_key_data *key)
 583 {
 584         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 585 }
 586
 587 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 588  * hardware to a bit-field that can be used by SW to more easily determine the
 589  * packet type.
 590  *
 591  * Macros are used to shorten the table lines and make this table human
 592  * readable.
 593  *
 594  * We store the PTYPE in the top byte of the bit field - this is just so that
 595  * we can check that the table doesn't have a row missing, as the index into
 596  * the table should be the PTYPE.
 597  *
 598  * Typical work flow:
 599  *
 600  * IF NOT i40e_ptype_lookup[ptype].known
 601  * THEN
 602  *      Packet is unknown
 603  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 604  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 605  * ELSE
 606  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 607  * ENDIF
 608  */
 609
 610 /* macro to make the table lines short */
 611 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 612         {       PTYPE, \
 613                 1, \
 614                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 615                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 616                 I40E_RX_PTYPE_##OUTER_FRAG, \
 617                 I40E_RX_PTYPE_TUNNEL_##T, \
 618                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 619                 I40E_RX_PTYPE_##TEF, \
 620                 I40E_RX_PTYPE_INNER_PROT_##I, \
 621                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 622
 623 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 624                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 625
 626 /* shorter macros makes the table fit but are terse */
 627 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 628 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 629 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 630
 631 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 632 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 633         /* L2 Packet types */
 634         I40E_PTT_UNUSED_ENTRY(0),
 635         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 636         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 637         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 638         I40E_PTT_UNUSED_ENTRY(4),
 639         I40E_PTT_UNUSED_ENTRY(5),
 640         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 641         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 642         I40E_PTT_UNUSED_ENTRY(8),
 643         I40E_PTT_UNUSED_ENTRY(9),
 644         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 645         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 646         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 651         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 652         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 653         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 654         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 655         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 656
 657         /* Non Tunneled IPv4 */
 658         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 659         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 660         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 661         I40E_PTT_UNUSED_ENTRY(25),
 662         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 663         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 664         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 665
 666         /* IPv4 --> IPv4 */
 667         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 668         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 669         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 670         I40E_PTT_UNUSED_ENTRY(32),
 671         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 672         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 673         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 674
 675         /* IPv4 --> IPv6 */
 676         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 677         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 678         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 679         I40E_PTT_UNUSED_ENTRY(39),
 680         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 681         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 682         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 683
 684         /* IPv4 --> GRE/NAT */
 685         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 686
 687         /* IPv4 --> GRE/NAT --> IPv4 */
 688         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 689         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 690         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 691         I40E_PTT_UNUSED_ENTRY(47),
 692         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 693         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 694         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 695
 696         /* IPv4 --> GRE/NAT --> IPv6 */
 697         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 698         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 699         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 700         I40E_PTT_UNUSED_ENTRY(54),
 701         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 702         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 703         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 704
 705         /* IPv4 --> GRE/NAT --> MAC */
 706         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 707
 708         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 709         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 710         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 711         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 712         I40E_PTT_UNUSED_ENTRY(62),
 713         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 714         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 715         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 716
 717         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 718         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 719         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 720         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 721         I40E_PTT_UNUSED_ENTRY(69),
 722         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 723         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 724         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 725
 726         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 727         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 728
 729         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 730         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 731         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 732         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 733         I40E_PTT_UNUSED_ENTRY(77),
 734         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 735         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 736         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 737
 738         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 739         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 740         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 741         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 742         I40E_PTT_UNUSED_ENTRY(84),
 743         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 744         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 745         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 746
 747         /* Non Tunneled IPv6 */
 748         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 749         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 750         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 751         I40E_PTT_UNUSED_ENTRY(91),
 752         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 753         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 754         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 755
 756         /* IPv6 --> IPv4 */
 757         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 758         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 759         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 760         I40E_PTT_UNUSED_ENTRY(98),
 761         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 762         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 763         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 764
 765         /* IPv6 --> IPv6 */
 766         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 767         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 768         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 769         I40E_PTT_UNUSED_ENTRY(105),
 770         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 771         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 772         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 773
 774         /* IPv6 --> GRE/NAT */
 775         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 776
 777         /* IPv6 --> GRE/NAT -> IPv4 */
 778         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 779         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 780         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 781         I40E_PTT_UNUSED_ENTRY(113),
 782         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 783         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 784         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 785
 786         /* IPv6 --> GRE/NAT -> IPv6 */
 787         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 788         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 789         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 790         I40E_PTT_UNUSED_ENTRY(120),
 791         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 792         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 793         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 794
 795         /* IPv6 --> GRE/NAT -> MAC */
 796         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 797
 798         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 799         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 800         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 801         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 802         I40E_PTT_UNUSED_ENTRY(128),
 803         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 804         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 805         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 806
 807         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 808         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 809         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 810         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 811         I40E_PTT_UNUSED_ENTRY(135),
 812         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 813         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 814         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 815
 816         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 817         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 818
 819         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 820         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 821         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 822         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 823         I40E_PTT_UNUSED_ENTRY(143),
 824         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 825         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 826         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 827
 828         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 829         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 830         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 831         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 832         I40E_PTT_UNUSED_ENTRY(150),
 833         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 834         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 835         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 836
 837         /* unused entries */
 838         I40E_PTT_UNUSED_ENTRY(154),
 839         I40E_PTT_UNUSED_ENTRY(155),
 840         I40E_PTT_UNUSED_ENTRY(156),
 841         I40E_PTT_UNUSED_ENTRY(157),
 842         I40E_PTT_UNUSED_ENTRY(158),
 843         I40E_PTT_UNUSED_ENTRY(159),
 844
 845         I40E_PTT_UNUSED_ENTRY(160),
 846         I40E_PTT_UNUSED_ENTRY(161),
 847         I40E_PTT_UNUSED_ENTRY(162),
 848         I40E_PTT_UNUSED_ENTRY(163),
 849         I40E_PTT_UNUSED_ENTRY(164),
 850         I40E_PTT_UNUSED_ENTRY(165),
 851         I40E_PTT_UNUSED_ENTRY(166),
 852         I40E_PTT_UNUSED_ENTRY(167),
 853         I40E_PTT_UNUSED_ENTRY(168),
 854         I40E_PTT_UNUSED_ENTRY(169),
 855
 856         I40E_PTT_UNUSED_ENTRY(170),
 857         I40E_PTT_UNUSED_ENTRY(171),
 858         I40E_PTT_UNUSED_ENTRY(172),
 859         I40E_PTT_UNUSED_ENTRY(173),
 860         I40E_PTT_UNUSED_ENTRY(174),
 861         I40E_PTT_UNUSED_ENTRY(175),
 862         I40E_PTT_UNUSED_ENTRY(176),
 863         I40E_PTT_UNUSED_ENTRY(177),
 864         I40E_PTT_UNUSED_ENTRY(178),
 865         I40E_PTT_UNUSED_ENTRY(179),
 866
 867         I40E_PTT_UNUSED_ENTRY(180),
 868         I40E_PTT_UNUSED_ENTRY(181),
 869         I40E_PTT_UNUSED_ENTRY(182),
 870         I40E_PTT_UNUSED_ENTRY(183),
 871         I40E_PTT_UNUSED_ENTRY(184),
 872         I40E_PTT_UNUSED_ENTRY(185),
 873         I40E_PTT_UNUSED_ENTRY(186),
 874         I40E_PTT_UNUSED_ENTRY(187),
 875         I40E_PTT_UNUSED_ENTRY(188),
 876         I40E_PTT_UNUSED_ENTRY(189),
 877
 878         I40E_PTT_UNUSED_ENTRY(190),
 879         I40E_PTT_UNUSED_ENTRY(191),
 880         I40E_PTT_UNUSED_ENTRY(192),
 881         I40E_PTT_UNUSED_ENTRY(193),
 882         I40E_PTT_UNUSED_ENTRY(194),
 883         I40E_PTT_UNUSED_ENTRY(195),
 884         I40E_PTT_UNUSED_ENTRY(196),
 885         I40E_PTT_UNUSED_ENTRY(197),
 886         I40E_PTT_UNUSED_ENTRY(198),
 887         I40E_PTT_UNUSED_ENTRY(199),
 888
 889         I40E_PTT_UNUSED_ENTRY(200),
 890         I40E_PTT_UNUSED_ENTRY(201),
 891         I40E_PTT_UNUSED_ENTRY(202),
 892         I40E_PTT_UNUSED_ENTRY(203),
 893         I40E_PTT_UNUSED_ENTRY(204),
 894         I40E_PTT_UNUSED_ENTRY(205),
 895         I40E_PTT_UNUSED_ENTRY(206),
 896         I40E_PTT_UNUSED_ENTRY(207),
 897         I40E_PTT_UNUSED_ENTRY(208),
 898         I40E_PTT_UNUSED_ENTRY(209),
 899
 900         I40E_PTT_UNUSED_ENTRY(210),
 901         I40E_PTT_UNUSED_ENTRY(211),
 902         I40E_PTT_UNUSED_ENTRY(212),
 903         I40E_PTT_UNUSED_ENTRY(213),
 904         I40E_PTT_UNUSED_ENTRY(214),
 905         I40E_PTT_UNUSED_ENTRY(215),
 906         I40E_PTT_UNUSED_ENTRY(216),
 907         I40E_PTT_UNUSED_ENTRY(217),
 908         I40E_PTT_UNUSED_ENTRY(218),
 909         I40E_PTT_UNUSED_ENTRY(219),
 910
 911         I40E_PTT_UNUSED_ENTRY(220),
 912         I40E_PTT_UNUSED_ENTRY(221),
 913         I40E_PTT_UNUSED_ENTRY(222),
 914         I40E_PTT_UNUSED_ENTRY(223),
 915         I40E_PTT_UNUSED_ENTRY(224),
 916         I40E_PTT_UNUSED_ENTRY(225),
 917         I40E_PTT_UNUSED_ENTRY(226),
 918         I40E_PTT_UNUSED_ENTRY(227),
 919         I40E_PTT_UNUSED_ENTRY(228),
 920         I40E_PTT_UNUSED_ENTRY(229),
 921
 922         I40E_PTT_UNUSED_ENTRY(230),
 923         I40E_PTT_UNUSED_ENTRY(231),
 924         I40E_PTT_UNUSED_ENTRY(232),
 925         I40E_PTT_UNUSED_ENTRY(233),
 926         I40E_PTT_UNUSED_ENTRY(234),
 927         I40E_PTT_UNUSED_ENTRY(235),
 928         I40E_PTT_UNUSED_ENTRY(236),
 929         I40E_PTT_UNUSED_ENTRY(237),
 930         I40E_PTT_UNUSED_ENTRY(238),
 931         I40E_PTT_UNUSED_ENTRY(239),
 932
 933         I40E_PTT_UNUSED_ENTRY(240),
 934         I40E_PTT_UNUSED_ENTRY(241),
 935         I40E_PTT_UNUSED_ENTRY(242),
 936         I40E_PTT_UNUSED_ENTRY(243),
 937         I40E_PTT_UNUSED_ENTRY(244),
 938         I40E_PTT_UNUSED_ENTRY(245),
 939         I40E_PTT_UNUSED_ENTRY(246),
 940         I40E_PTT_UNUSED_ENTRY(247),
 941         I40E_PTT_UNUSED_ENTRY(248),
 942         I40E_PTT_UNUSED_ENTRY(249),
 943
 944         I40E_PTT_UNUSED_ENTRY(250),
 945         I40E_PTT_UNUSED_ENTRY(251),
 946         I40E_PTT_UNUSED_ENTRY(252),
 947         I40E_PTT_UNUSED_ENTRY(253),
 948         I40E_PTT_UNUSED_ENTRY(254),
 949         I40E_PTT_UNUSED_ENTRY(255)
 950 };
 951
 952
 953 /**
 954  * i40e_validate_mac_addr - Validate unicast MAC address
 955  * @mac_addr: pointer to MAC address
 956  *
 957  * Tests a MAC address to ensure it is a valid Individual Address
 958  **/
 959 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 960 {
 961         enum i40e_status_code status = I40E_SUCCESS;
 962
 963         DEBUGFUNC("i40e_validate_mac_addr");
 964
 965         /* Broadcast addresses ARE multicast addresses
 966          * Make sure it is not a multicast address
 967          * Reject the zero address
 968          */
 969         if (I40E_IS_MULTICAST(mac_addr) ||
 970             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 971               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 972                 status = I40E_ERR_INVALID_MAC_ADDR;
 973
 974         return status;
 975 }
 976 #ifdef PF_DRIVER
 977
 978 /**
 979  * i40e_init_shared_code - Initialize the shared code
 980  * @hw: pointer to hardware structure
 981  *
 982  * This assigns the MAC type and PHY code and inits the NVM.
 983  * Does not touch the hardware. This function must be called prior to any
 984  * other function in the shared code. The i40e_hw structure should be
 985  * memset to 0 prior to calling this function.  The following fields in
 986  * hw structure should be filled in prior to calling this function:
 987  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 988  * subsystem_vendor_id, and revision_id
 989  **/
 990 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 991 {
 992         enum i40e_status_code status = I40E_SUCCESS;
 993         u32 port, ari, func_rid;
 994
 995         DEBUGFUNC("i40e_init_shared_code");
 996
 997         i40e_set_mac_type(hw);
 998
 999         switch (hw->mac.type) {
1000         case I40E_MAC_XL710:
1001         case I40E_MAC_X722:
1002                 break;
1003         default:
1004                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1005         }
1006
1007         hw->phy.get_link_info = true;
1008
1009         /* Determine port number and PF number*/
1010         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1011                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1012         hw->port = (u8)port;
1013         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1014                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1015         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1016         if (ari)
1017                 hw->pf_id = (u8)(func_rid & 0xff);
1018         else
1019                 hw->pf_id = (u8)(func_rid & 0x7);
1020
1021         if (hw->mac.type == I40E_MAC_X722)
1022                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1023                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1024         /* NVMUpdate features structure initialization */
1025         hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1026         hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1027         hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1028         i40e_memset(hw->nvmupd_features.features, 0x0,
1029                     I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1030                     sizeof(*hw->nvmupd_features.features),
1031                     I40E_NONDMA_MEM);
1032
1033         /* No features supported at the moment */
1034         hw->nvmupd_features.features[0] = 0;
1035
1036         status = i40e_init_nvm(hw);
1037         return status;
1038 }
1039
1040 /**
1041  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1042  * @hw: pointer to the hw struct
1043  * @flags: a return indicator of what addresses were added to the addr store
1044  * @addrs: the requestor's mac addr store
1045  * @cmd_details: pointer to command details structure or NULL
1046  **/
1047 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1048                                    u16 *flags,
1049                                    struct i40e_aqc_mac_address_read_data *addrs,
1050                                    struct i40e_asq_cmd_details *cmd_details)
1051 {
1052         struct i40e_aq_desc desc;
1053         struct i40e_aqc_mac_address_read *cmd_data =
1054                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1055         enum i40e_status_code status;
1056
1057         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1058         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1059
1060         status = i40e_asq_send_command(hw, &desc, addrs,
1061                                        sizeof(*addrs), cmd_details);
1062         *flags = LE16_TO_CPU(cmd_data->command_flags);
1063
1064         return status;
1065 }
1066
1067 /**
1068  * i40e_aq_mac_address_write - Change the MAC addresses
1069  * @hw: pointer to the hw struct
1070  * @flags: indicates which MAC to be written
1071  * @mac_addr: address to write
1072  * @cmd_details: pointer to command details structure or NULL
1073  **/
1074 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1075                                     u16 flags, u8 *mac_addr,
1076                                     struct i40e_asq_cmd_details *cmd_details)
1077 {
1078         struct i40e_aq_desc desc;
1079         struct i40e_aqc_mac_address_write *cmd_data =
1080                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1081         enum i40e_status_code status;
1082
1083         i40e_fill_default_direct_cmd_desc(&desc,
1084                                           i40e_aqc_opc_mac_address_write);
1085         cmd_data->command_flags = CPU_TO_LE16(flags);
1086         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1087         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1088                                         ((u32)mac_addr[3] << 16) |
1089                                         ((u32)mac_addr[4] << 8) |
1090                                         mac_addr[5]);
1091
1092         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1093
1094         return status;
1095 }
1096
1097 /**
1098  * i40e_get_mac_addr - get MAC address
1099  * @hw: pointer to the HW structure
1100  * @mac_addr: pointer to MAC address
1101  *
1102  * Reads the adapter's MAC address from register
1103  **/
1104 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1105 {
1106         struct i40e_aqc_mac_address_read_data addrs;
1107         enum i40e_status_code status;
1108         u16 flags = 0;
1109
1110         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1111
1112         if (flags & I40E_AQC_LAN_ADDR_VALID)
1113                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1114                         I40E_NONDMA_TO_NONDMA);
1115
1116         return status;
1117 }
1118
1119 /**
1120  * i40e_get_port_mac_addr - get Port MAC address
1121  * @hw: pointer to the HW structure
1122  * @mac_addr: pointer to Port MAC address
1123  *
1124  * Reads the adapter's Port MAC address
1125  **/
1126 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1127 {
1128         struct i40e_aqc_mac_address_read_data addrs;
1129         enum i40e_status_code status;
1130         u16 flags = 0;
1131
1132         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1133         if (status)
1134                 return status;
1135
1136         if (flags & I40E_AQC_PORT_ADDR_VALID)
1137                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1138                         I40E_NONDMA_TO_NONDMA);
1139         else
1140                 status = I40E_ERR_INVALID_MAC_ADDR;
1141
1142         return status;
1143 }
1144
1145 /**
1146  * i40e_pre_tx_queue_cfg - pre tx queue configure
1147  * @hw: pointer to the HW structure
1148  * @queue: target pf queue index
1149  * @enable: state change request
1150  *
1151  * Handles hw requirement to indicate intention to enable
1152  * or disable target queue.
1153  **/
1154 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1155 {
1156         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1157         u32 reg_block = 0;
1158         u32 reg_val;
1159
1160         if (abs_queue_idx >= 128) {
1161                 reg_block = abs_queue_idx / 128;
1162                 abs_queue_idx %= 128;
1163         }
1164
1165         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1166         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1167         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1168
1169         if (enable)
1170                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1171         else
1172                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1173
1174         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1175 }
1176
1177 /**
1178  * i40e_get_san_mac_addr - get SAN MAC address
1179  * @hw: pointer to the HW structure
1180  * @mac_addr: pointer to SAN MAC address
1181  *
1182  * Reads the adapter's SAN MAC address from NVM
1183  **/
1184 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1185                                             u8 *mac_addr)
1186 {
1187         struct i40e_aqc_mac_address_read_data addrs;
1188         enum i40e_status_code status;
1189         u16 flags = 0;
1190
1191         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1192         if (status)
1193                 return status;
1194
1195         if (flags & I40E_AQC_SAN_ADDR_VALID)
1196                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1197                         I40E_NONDMA_TO_NONDMA);
1198         else
1199                 status = I40E_ERR_INVALID_MAC_ADDR;
1200
1201         return status;
1202 }
1203
1204 /**
1205  *  i40e_read_pba_string - Reads part number string from EEPROM
1206  *  @hw: pointer to hardware structure
1207  *  @pba_num: stores the part number string from the EEPROM
1208  *  @pba_num_size: part number string buffer length
1209  *
1210  *  Reads the part number string from the EEPROM.
1211  **/
1212 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1213                                             u32 pba_num_size)
1214 {
1215         enum i40e_status_code status = I40E_SUCCESS;
1216         u16 pba_word = 0;
1217         u16 pba_size = 0;
1218         u16 pba_ptr = 0;
1219         u16 i = 0;
1220
1221         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1222         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1223                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1224                 return status;
1225         }
1226
1227         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1228         if (status != I40E_SUCCESS) {
1229                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1230                 return status;
1231         }
1232
1233         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1234         if (status != I40E_SUCCESS) {
1235                 DEBUGOUT("Failed to read PBA Block size.\n");
1236                 return status;
1237         }
1238
1239         /* Subtract one to get PBA word count (PBA Size word is included in
1240          * total size)
1241          */
1242         pba_size--;
1243         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1244                 DEBUGOUT("Buffer to small for PBA data.\n");
1245                 return I40E_ERR_PARAM;
1246         }
1247
1248         for (i = 0; i < pba_size; i++) {
1249                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1250                 if (status != I40E_SUCCESS) {
1251                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1252                         return status;
1253                 }
1254
1255                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1256                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1257         }
1258         pba_num[(pba_size * 2)] = '\0';
1259
1260         return status;
1261 }
1262
1263 /**
1264  * i40e_get_media_type - Gets media type
1265  * @hw: pointer to the hardware structure
1266  **/
1267 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1268 {
1269         enum i40e_media_type media;
1270
1271         switch (hw->phy.link_info.phy_type) {
1272         case I40E_PHY_TYPE_10GBASE_SR:
1273         case I40E_PHY_TYPE_10GBASE_LR:
1274         case I40E_PHY_TYPE_1000BASE_SX:
1275         case I40E_PHY_TYPE_1000BASE_LX:
1276         case I40E_PHY_TYPE_40GBASE_SR4:
1277         case I40E_PHY_TYPE_40GBASE_LR4:
1278         case I40E_PHY_TYPE_25GBASE_LR:
1279         case I40E_PHY_TYPE_25GBASE_SR:
1280                 media = I40E_MEDIA_TYPE_FIBER;
1281                 break;
1282         case I40E_PHY_TYPE_100BASE_TX:
1283         case I40E_PHY_TYPE_1000BASE_T:
1284         case I40E_PHY_TYPE_2_5GBASE_T:
1285         case I40E_PHY_TYPE_5GBASE_T:
1286         case I40E_PHY_TYPE_10GBASE_T:
1287                 media = I40E_MEDIA_TYPE_BASET;
1288                 break;
1289         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1290         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1291         case I40E_PHY_TYPE_10GBASE_CR1:
1292         case I40E_PHY_TYPE_40GBASE_CR4:
1293         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1294         case I40E_PHY_TYPE_40GBASE_AOC:
1295         case I40E_PHY_TYPE_10GBASE_AOC:
1296         case I40E_PHY_TYPE_25GBASE_CR:
1297         case I40E_PHY_TYPE_25GBASE_AOC:
1298         case I40E_PHY_TYPE_25GBASE_ACC:
1299                 media = I40E_MEDIA_TYPE_DA;
1300                 break;
1301         case I40E_PHY_TYPE_1000BASE_KX:
1302         case I40E_PHY_TYPE_10GBASE_KX4:
1303         case I40E_PHY_TYPE_10GBASE_KR:
1304         case I40E_PHY_TYPE_40GBASE_KR4:
1305         case I40E_PHY_TYPE_20GBASE_KR2:
1306         case I40E_PHY_TYPE_25GBASE_KR:
1307                 media = I40E_MEDIA_TYPE_BACKPLANE;
1308                 break;
1309         case I40E_PHY_TYPE_SGMII:
1310         case I40E_PHY_TYPE_XAUI:
1311         case I40E_PHY_TYPE_XFI:
1312         case I40E_PHY_TYPE_XLAUI:
1313         case I40E_PHY_TYPE_XLPPI:
1314         default:
1315                 media = I40E_MEDIA_TYPE_UNKNOWN;
1316                 break;
1317         }
1318
1319         return media;
1320 }
1321
1322 /**
1323  * i40e_poll_globr - Poll for Global Reset completion
1324  * @hw: pointer to the hardware structure
1325  * @retry_limit: how many times to retry before failure
1326  **/
1327 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1328                                              u32 retry_limit)
1329 {
1330         u32 cnt, reg = 0;
1331
1332         for (cnt = 0; cnt < retry_limit; cnt++) {
1333                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1334                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1335                         return I40E_SUCCESS;
1336                 i40e_msec_delay(100);
1337         }
1338
1339         DEBUGOUT("Global reset failed.\n");
1340         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1341
1342         return I40E_ERR_RESET_FAILED;
1343 }
1344
1345 #define I40E_PF_RESET_WAIT_COUNT        200
1346 /**
1347  * i40e_pf_reset - Reset the PF
1348  * @hw: pointer to the hardware structure
1349  *
1350  * Assuming someone else has triggered a global reset,
1351  * assure the global reset is complete and then reset the PF
1352  **/
1353 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1354 {
1355         u32 cnt = 0;
1356         u32 cnt1 = 0;
1357         u32 reg = 0;
1358         u32 grst_del;
1359
1360         /* Poll for Global Reset steady state in case of recent GRST.
1361          * The grst delay value is in 100ms units, and we'll wait a
1362          * couple counts longer to be sure we don't just miss the end.
1363          */
1364         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1365                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1366                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1367
1368         grst_del = min(grst_del * 20, 160U);
1369
1370         for (cnt = 0; cnt < grst_del; cnt++) {
1371                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1372                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1373                         break;
1374                 i40e_msec_delay(100);
1375         }
1376         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1377                 DEBUGOUT("Global reset polling failed to complete.\n");
1378                 return I40E_ERR_RESET_FAILED;
1379         }
1380
1381         /* Now Wait for the FW to be ready */
1382         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1383                 reg = rd32(hw, I40E_GLNVM_ULD);
1384                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1385                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1386                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1387                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1388                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1389                         break;
1390                 }
1391                 i40e_msec_delay(10);
1392         }
1393         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1394                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1395                 DEBUGOUT("wait for FW Reset complete timedout\n");
1396                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1397                 return I40E_ERR_RESET_FAILED;
1398         }
1399
1400         /* If there was a Global Reset in progress when we got here,
1401          * we don't need to do the PF Reset
1402          */
1403         if (!cnt) {
1404                 u32 reg2 = 0;
1405
1406                 reg = rd32(hw, I40E_PFGEN_CTRL);
1407                 wr32(hw, I40E_PFGEN_CTRL,
1408                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1409                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1410                         reg = rd32(hw, I40E_PFGEN_CTRL);
1411                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1412                                 break;
1413                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1414                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1415                                 break;
1416                         i40e_msec_delay(1);
1417                 }
1418                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1419                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1420                                 return I40E_ERR_RESET_FAILED;
1421                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1422                         DEBUGOUT("PF reset polling failed to complete.\n");
1423                         return I40E_ERR_RESET_FAILED;
1424                 }
1425         }
1426
1427         i40e_clear_pxe_mode(hw);
1428
1429
1430         return I40E_SUCCESS;
1431 }
1432
1433 /**
1434  * i40e_clear_hw - clear out any left over hw state
1435  * @hw: pointer to the hw struct
1436  *
1437  * Clear queues and interrupts, typically called at init time,
1438  * but after the capabilities have been found so we know how many
1439  * queues and msix vectors have been allocated.
1440  **/
1441 void i40e_clear_hw(struct i40e_hw *hw)
1442 {
1443         u32 num_queues, base_queue;
1444         u32 num_pf_int;
1445         u32 num_vf_int;
1446         u32 num_vfs;
1447         u32 i, j;
1448         u32 val;
1449         u32 eol = 0x7ff;
1450
1451         /* get number of interrupts, queues, and vfs */
1452         val = rd32(hw, I40E_GLPCI_CNF2);
1453         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1454                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1455         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1456                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1457
1458         val = rd32(hw, I40E_PFLAN_QALLOC);
1459         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1460                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1461         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1462                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1463         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1464                 num_queues = (j - base_queue) + 1;
1465         else
1466                 num_queues = 0;
1467
1468         val = rd32(hw, I40E_PF_VT_PFALLOC);
1469         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1470                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1471         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1472                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1473         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1474                 num_vfs = (j - i) + 1;
1475         else
1476                 num_vfs = 0;
1477
1478         /* stop all the interrupts */
1479         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1480         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1481         for (i = 0; i < num_pf_int - 2; i++)
1482                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1483
1484         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1485         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1486         wr32(hw, I40E_PFINT_LNKLST0, val);
1487         for (i = 0; i < num_pf_int - 2; i++)
1488                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1489         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1490         for (i = 0; i < num_vfs; i++)
1491                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1492         for (i = 0; i < num_vf_int - 2; i++)
1493                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1494
1495         /* warn the HW of the coming Tx disables */
1496         for (i = 0; i < num_queues; i++) {
1497                 u32 abs_queue_idx = base_queue + i;
1498                 u32 reg_block = 0;
1499
1500                 if (abs_queue_idx >= 128) {
1501                         reg_block = abs_queue_idx / 128;
1502                         abs_queue_idx %= 128;
1503                 }
1504
1505                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1506                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1507                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1508                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1509
1510                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1511         }
1512         i40e_usec_delay(400);
1513
1514         /* stop all the queues */
1515         for (i = 0; i < num_queues; i++) {
1516                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1517                 wr32(hw, I40E_QTX_ENA(i), 0);
1518                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1519                 wr32(hw, I40E_QRX_ENA(i), 0);
1520         }
1521
1522         /* short wait for all queue disables to settle */
1523         i40e_usec_delay(50);
1524 }
1525
1526 /**
1527  * i40e_clear_pxe_mode - clear pxe operations mode
1528  * @hw: pointer to the hw struct
1529  *
1530  * Make sure all PXE mode settings are cleared, including things
1531  * like descriptor fetch/write-back mode.
1532  **/
1533 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1534 {
1535         if (i40e_check_asq_alive(hw))
1536                 i40e_aq_clear_pxe_mode(hw, NULL);
1537 }
1538
1539 /**
1540  * i40e_led_is_mine - helper to find matching led
1541  * @hw: pointer to the hw struct
1542  * @idx: index into GPIO registers
1543  *
1544  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1545  */
1546 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1547 {
1548         u32 gpio_val = 0;
1549         u32 port;
1550
1551         if (!hw->func_caps.led[idx])
1552                 return 0;
1553
1554         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1555         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1556                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1557
1558         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1559          * if it is not our port then ignore
1560          */
1561         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1562             (port != hw->port))
1563                 return 0;
1564
1565         return gpio_val;
1566 }
1567
1568 #define I40E_COMBINED_ACTIVITY 0xA
1569 #define I40E_FILTER_ACTIVITY 0xE
1570 #define I40E_LINK_ACTIVITY 0xC
1571 #define I40E_MAC_ACTIVITY 0xD
1572 #define I40E_LED0 22
1573
1574 /**
1575  * i40e_led_get - return current on/off mode
1576  * @hw: pointer to the hw struct
1577  *
1578  * The value returned is the 'mode' field as defined in the
1579  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1580  * values are variations of possible behaviors relating to
1581  * blink, link, and wire.
1582  **/
1583 u32 i40e_led_get(struct i40e_hw *hw)
1584 {
1585         u32 current_mode = 0;
1586         u32 mode = 0;
1587         int i;
1588
1589         /* as per the documentation GPIO 22-29 are the LED
1590          * GPIO pins named LED0..LED7
1591          */
1592         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1593                 u32 gpio_val = i40e_led_is_mine(hw, i);
1594
1595                 if (!gpio_val)
1596                         continue;
1597
1598                 /* ignore gpio LED src mode entries related to the activity
1599                  *  LEDs
1600                  */
1601                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1602                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1603                 switch (current_mode) {
1604                 case I40E_COMBINED_ACTIVITY:
1605                 case I40E_FILTER_ACTIVITY:
1606                 case I40E_MAC_ACTIVITY:
1607                 case I40E_LINK_ACTIVITY:
1608                         continue;
1609                 default:
1610                         break;
1611                 }
1612
1613                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1614                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1615                 break;
1616         }
1617
1618         return mode;
1619 }
1620
1621 /**
1622  * i40e_led_set - set new on/off mode
1623  * @hw: pointer to the hw struct
1624  * @mode: 0=off, 0xf=on (else see manual for mode details)
1625  * @blink: true if the LED should blink when on, false if steady
1626  *
1627  * if this function is used to turn on the blink it should
1628  * be used to disable the blink when restoring the original state.
1629  **/
1630 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1631 {
1632         u32 current_mode = 0;
1633         int i;
1634
1635         if (mode & 0xfffffff0)
1636                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1637
1638         /* as per the documentation GPIO 22-29 are the LED
1639          * GPIO pins named LED0..LED7
1640          */
1641         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1642                 u32 gpio_val = i40e_led_is_mine(hw, i);
1643
1644                 if (!gpio_val)
1645                         continue;
1646
1647                 /* ignore gpio LED src mode entries related to the activity
1648                  * LEDs
1649                  */
1650                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1651                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1652                 switch (current_mode) {
1653                 case I40E_COMBINED_ACTIVITY:
1654                 case I40E_FILTER_ACTIVITY:
1655                 case I40E_MAC_ACTIVITY:
1656                 case I40E_LINK_ACTIVITY:
1657                         continue;
1658                 default:
1659                         break;
1660                 }
1661
1662                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1663                 /* this & is a bit of paranoia, but serves as a range check */
1664                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1665                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1666
1667                 if (blink)
1668                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1669                 else
1670                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1671
1672                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1673                 break;
1674         }
1675 }
1676
1677 /* Admin command wrappers */
1678
1679 /**
1680  * i40e_aq_get_phy_capabilities
1681  * @hw: pointer to the hw struct
1682  * @abilities: structure for PHY capabilities to be filled
1683  * @qualified_modules: report Qualified Modules
1684  * @report_init: report init capabilities (active are default)
1685  * @cmd_details: pointer to command details structure or NULL
1686  *
1687  * Returns the various PHY abilities supported on the Port.
1688  **/
1689 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1690                         bool qualified_modules, bool report_init,
1691                         struct i40e_aq_get_phy_abilities_resp *abilities,
1692                         struct i40e_asq_cmd_details *cmd_details)
1693 {
1694         struct i40e_aq_desc desc;
1695         enum i40e_status_code status;
1696         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1697         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1698
1699         if (!abilities)
1700                 return I40E_ERR_PARAM;
1701
1702         do {
1703                 i40e_fill_default_direct_cmd_desc(&desc,
1704                                                i40e_aqc_opc_get_phy_abilities);
1705
1706                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1707                 if (abilities_size > I40E_AQ_LARGE_BUF)
1708                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1709
1710                 if (qualified_modules)
1711                         desc.params.external.param0 |=
1712                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1713
1714                 if (report_init)
1715                         desc.params.external.param0 |=
1716                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1717
1718                 status = i40e_asq_send_command(hw, &desc, abilities,
1719                                                abilities_size, cmd_details);
1720
1721                 if (status != I40E_SUCCESS)
1722                         break;
1723
1724                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1725                         status = I40E_ERR_UNKNOWN_PHY;
1726                         break;
1727                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1728                         i40e_msec_delay(1);
1729                         total_delay++;
1730                         status = I40E_ERR_TIMEOUT;
1731                 }
1732         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1733                  (total_delay < max_delay));
1734
1735         if (status != I40E_SUCCESS)
1736                 return status;
1737
1738         if (report_init) {
1739                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1740                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1741                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1742                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1743                 } else {
1744                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1745                         hw->phy.phy_types |=
1746                                         ((u64)abilities->phy_type_ext << 32);
1747                 }
1748         }
1749
1750         return status;
1751 }
1752
1753 /**
1754  * i40e_aq_set_phy_config
1755  * @hw: pointer to the hw struct
1756  * @config: structure with PHY configuration to be set
1757  * @cmd_details: pointer to command details structure or NULL
1758  *
1759  * Set the various PHY configuration parameters
1760  * supported on the Port.One or more of the Set PHY config parameters may be
1761  * ignored in an MFP mode as the PF may not have the privilege to set some
1762  * of the PHY Config parameters. This status will be indicated by the
1763  * command response.
1764  **/
1765 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1766                                 struct i40e_aq_set_phy_config *config,
1767                                 struct i40e_asq_cmd_details *cmd_details)
1768 {
1769         struct i40e_aq_desc desc;
1770         struct i40e_aq_set_phy_config *cmd =
1771                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1772         enum i40e_status_code status;
1773
1774         if (!config)
1775                 return I40E_ERR_PARAM;
1776
1777         i40e_fill_default_direct_cmd_desc(&desc,
1778                                           i40e_aqc_opc_set_phy_config);
1779
1780         *cmd = *config;
1781
1782         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1783
1784         return status;
1785 }
1786
1787 /**
1788  * i40e_set_fc
1789  * @hw: pointer to the hw struct
1790  * @aq_failures: buffer to return AdminQ failure information
1791  * @atomic_restart: whether to enable atomic link restart
1792  *
1793  * Set the requested flow control mode using set_phy_config.
1794  **/
1795 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1796                                   bool atomic_restart)
1797 {
1798         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1799         struct i40e_aq_get_phy_abilities_resp abilities;
1800         struct i40e_aq_set_phy_config config;
1801         enum i40e_status_code status;
1802         u8 pause_mask = 0x0;
1803
1804         *aq_failures = 0x0;
1805
1806         switch (fc_mode) {
1807         case I40E_FC_FULL:
1808                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1809                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1810                 break;
1811         case I40E_FC_RX_PAUSE:
1812                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1813                 break;
1814         case I40E_FC_TX_PAUSE:
1815                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1816                 break;
1817         default:
1818                 break;
1819         }
1820
1821         /* Get the current phy config */
1822         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1823                                               NULL);
1824         if (status) {
1825                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1826                 return status;
1827         }
1828
1829         memset(&config, 0, sizeof(config));
1830         /* clear the old pause settings */
1831         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1832                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1833         /* set the new abilities */
1834         config.abilities |= pause_mask;
1835         /* If the abilities have changed, then set the new config */
1836         if (config.abilities != abilities.abilities) {
1837                 /* Auto restart link so settings take effect */
1838                 if (atomic_restart)
1839                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1840                 /* Copy over all the old settings */
1841                 config.phy_type = abilities.phy_type;
1842                 config.phy_type_ext = abilities.phy_type_ext;
1843                 config.link_speed = abilities.link_speed;
1844                 config.eee_capability = abilities.eee_capability;
1845                 config.eeer = abilities.eeer_val;
1846                 config.low_power_ctrl = abilities.d3_lpan;
1847                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1848                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1849                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1850
1851                 if (status)
1852                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1853         }
1854         /* Update the link info */
1855         status = i40e_update_link_info(hw);
1856         if (status) {
1857                 /* Wait a little bit (on 40G cards it sometimes takes a really
1858                  * long time for link to come back from the atomic reset)
1859                  * and try once more
1860                  */
1861                 i40e_msec_delay(1000);
1862                 status = i40e_update_link_info(hw);
1863         }
1864         if (status)
1865                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1866
1867         return status;
1868 }
1869
1870 /**
1871  * i40e_aq_set_mac_config
1872  * @hw: pointer to the hw struct
1873  * @max_frame_size: Maximum Frame Size to be supported by the port
1874  * @crc_en: Tell HW to append a CRC to outgoing frames
1875  * @pacing: Pacing configurations
1876  * @cmd_details: pointer to command details structure or NULL
1877  *
1878  * Configure MAC settings for frame size, jumbo frame support and the
1879  * addition of a CRC by the hardware.
1880  **/
1881 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1882                                 u16 max_frame_size,
1883                                 bool crc_en, u16 pacing,
1884                                 struct i40e_asq_cmd_details *cmd_details)
1885 {
1886         struct i40e_aq_desc desc;
1887         struct i40e_aq_set_mac_config *cmd =
1888                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1889         enum i40e_status_code status;
1890
1891         if (max_frame_size == 0)
1892                 return I40E_ERR_PARAM;
1893
1894         i40e_fill_default_direct_cmd_desc(&desc,
1895                                           i40e_aqc_opc_set_mac_config);
1896
1897         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1898         cmd->params = ((u8)pacing & 0x0F) << 3;
1899         if (crc_en)
1900                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1901
1902 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1903         cmd->fc_refresh_threshold =
1904                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1905
1906         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1907
1908         return status;
1909 }
1910
1911 /**
1912  * i40e_aq_clear_pxe_mode
1913  * @hw: pointer to the hw struct
1914  * @cmd_details: pointer to command details structure or NULL
1915  *
1916  * Tell the firmware that the driver is taking over from PXE
1917  **/
1918 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1919                         struct i40e_asq_cmd_details *cmd_details)
1920 {
1921         enum i40e_status_code status;
1922         struct i40e_aq_desc desc;
1923         struct i40e_aqc_clear_pxe *cmd =
1924                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1925
1926         i40e_fill_default_direct_cmd_desc(&desc,
1927                                           i40e_aqc_opc_clear_pxe_mode);
1928
1929         cmd->rx_cnt = 0x2;
1930
1931         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1932
1933         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1934
1935         return status;
1936 }
1937
1938 /**
1939  * i40e_aq_set_link_restart_an
1940  * @hw: pointer to the hw struct
1941  * @enable_link: if true: enable link, if false: disable link
1942  * @cmd_details: pointer to command details structure or NULL
1943  *
1944  * Sets up the link and restarts the Auto-Negotiation over the link.
1945  **/
1946 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1947                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1948 {
1949         struct i40e_aq_desc desc;
1950         struct i40e_aqc_set_link_restart_an *cmd =
1951                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1952         enum i40e_status_code status;
1953
1954         i40e_fill_default_direct_cmd_desc(&desc,
1955                                           i40e_aqc_opc_set_link_restart_an);
1956
1957         cmd->command = I40E_AQ_PHY_RESTART_AN;
1958         if (enable_link)
1959                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1960         else
1961                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1962
1963         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1964
1965         return status;
1966 }
1967
1968 /**
1969  * i40e_aq_get_link_info
1970  * @hw: pointer to the hw struct
1971  * @enable_lse: enable/disable LinkStatusEvent reporting
1972  * @link: pointer to link status structure - optional
1973  * @cmd_details: pointer to command details structure or NULL
1974  *
1975  * Returns the link status of the adapter.
1976  **/
1977 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1978                                 bool enable_lse, struct i40e_link_status *link,
1979                                 struct i40e_asq_cmd_details *cmd_details)
1980 {
1981         struct i40e_aq_desc desc;
1982         struct i40e_aqc_get_link_status *resp =
1983                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1984         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1985         enum i40e_status_code status;
1986         bool tx_pause, rx_pause;
1987         u16 command_flags;
1988
1989         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1990
1991         if (enable_lse)
1992                 command_flags = I40E_AQ_LSE_ENABLE;
1993         else
1994                 command_flags = I40E_AQ_LSE_DISABLE;
1995         resp->command_flags = CPU_TO_LE16(command_flags);
1996
1997         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1998
1999         if (status != I40E_SUCCESS)
2000                 goto aq_get_link_info_exit;
2001
2002         /* save off old link status information */
2003         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2004                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2005
2006         /* update link status */
2007         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2008         hw->phy.media_type = i40e_get_media_type(hw);
2009         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2010         hw_link_info->link_info = resp->link_info;
2011         hw_link_info->an_info = resp->an_info;
2012         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2013                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
2014         hw_link_info->ext_info = resp->ext_info;
2015         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2016         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2017         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2018
2019         /* update fc info */
2020         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2021         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2022         if (tx_pause & rx_pause)
2023                 hw->fc.current_mode = I40E_FC_FULL;
2024         else if (tx_pause)
2025                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2026         else if (rx_pause)
2027                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2028         else
2029                 hw->fc.current_mode = I40E_FC_NONE;
2030
2031         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2032                 hw_link_info->crc_enable = true;
2033         else
2034                 hw_link_info->crc_enable = false;
2035
2036         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2037                 hw_link_info->lse_enable = true;
2038         else
2039                 hw_link_info->lse_enable = false;
2040
2041         if ((hw->mac.type == I40E_MAC_XL710) &&
2042             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2043              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2044                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2045
2046         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2047             hw->mac.type != I40E_MAC_X722) {
2048                 __le32 tmp;
2049
2050                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2051                             I40E_NONDMA_TO_NONDMA);
2052                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2053                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2054         }
2055
2056         /* save link status information */
2057         if (link)
2058                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2059                             I40E_NONDMA_TO_NONDMA);
2060
2061         /* flag cleared so helper functions don't call AQ again */
2062         hw->phy.get_link_info = false;
2063
2064 aq_get_link_info_exit:
2065         return status;
2066 }
2067
2068 /**
2069  * i40e_aq_set_phy_int_mask
2070  * @hw: pointer to the hw struct
2071  * @mask: interrupt mask to be set
2072  * @cmd_details: pointer to command details structure or NULL
2073  *
2074  * Set link interrupt mask.
2075  **/
2076 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2077                                 u16 mask,
2078                                 struct i40e_asq_cmd_details *cmd_details)
2079 {
2080         struct i40e_aq_desc desc;
2081         struct i40e_aqc_set_phy_int_mask *cmd =
2082                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2083         enum i40e_status_code status;
2084
2085         i40e_fill_default_direct_cmd_desc(&desc,
2086                                           i40e_aqc_opc_set_phy_int_mask);
2087
2088         cmd->event_mask = CPU_TO_LE16(mask);
2089
2090         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2091
2092         return status;
2093 }
2094
2095 /**
2096  * i40e_aq_get_local_advt_reg
2097  * @hw: pointer to the hw struct
2098  * @advt_reg: local AN advertisement register value
2099  * @cmd_details: pointer to command details structure or NULL
2100  *
2101  * Get the Local AN advertisement register value.
2102  **/
2103 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2104                                 u64 *advt_reg,
2105                                 struct i40e_asq_cmd_details *cmd_details)
2106 {
2107         struct i40e_aq_desc desc;
2108         struct i40e_aqc_an_advt_reg *resp =
2109                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2110         enum i40e_status_code status;
2111
2112         i40e_fill_default_direct_cmd_desc(&desc,
2113                                           i40e_aqc_opc_get_local_advt_reg);
2114
2115         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2116
2117         if (status != I40E_SUCCESS)
2118                 goto aq_get_local_advt_reg_exit;
2119
2120         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2121         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2122
2123 aq_get_local_advt_reg_exit:
2124         return status;
2125 }
2126
2127 /**
2128  * i40e_aq_set_local_advt_reg
2129  * @hw: pointer to the hw struct
2130  * @advt_reg: local AN advertisement register value
2131  * @cmd_details: pointer to command details structure or NULL
2132  *
2133  * Get the Local AN advertisement register value.
2134  **/
2135 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2136                                 u64 advt_reg,
2137                                 struct i40e_asq_cmd_details *cmd_details)
2138 {
2139         struct i40e_aq_desc desc;
2140         struct i40e_aqc_an_advt_reg *cmd =
2141                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2142         enum i40e_status_code status;
2143
2144         i40e_fill_default_direct_cmd_desc(&desc,
2145                                           i40e_aqc_opc_get_local_advt_reg);
2146
2147         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2148         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2149
2150         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2151
2152         return status;
2153 }
2154
2155 /**
2156  * i40e_aq_get_partner_advt
2157  * @hw: pointer to the hw struct
2158  * @advt_reg: AN partner advertisement register value
2159  * @cmd_details: pointer to command details structure or NULL
2160  *
2161  * Get the link partner AN advertisement register value.
2162  **/
2163 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2164                                 u64 *advt_reg,
2165                                 struct i40e_asq_cmd_details *cmd_details)
2166 {
2167         struct i40e_aq_desc desc;
2168         struct i40e_aqc_an_advt_reg *resp =
2169                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2170         enum i40e_status_code status;
2171
2172         i40e_fill_default_direct_cmd_desc(&desc,
2173                                           i40e_aqc_opc_get_partner_advt);
2174
2175         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2176
2177         if (status != I40E_SUCCESS)
2178                 goto aq_get_partner_advt_exit;
2179
2180         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2181         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2182
2183 aq_get_partner_advt_exit:
2184         return status;
2185 }
2186
2187 /**
2188  * i40e_aq_set_lb_modes
2189  * @hw: pointer to the hw struct
2190  * @lb_modes: loopback mode to be set
2191  * @cmd_details: pointer to command details structure or NULL
2192  *
2193  * Sets loopback modes.
2194  **/
2195 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2196                                 u16 lb_modes,
2197                                 struct i40e_asq_cmd_details *cmd_details)
2198 {
2199         struct i40e_aq_desc desc;
2200         struct i40e_aqc_set_lb_mode *cmd =
2201                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2202         enum i40e_status_code status;
2203
2204         i40e_fill_default_direct_cmd_desc(&desc,
2205                                           i40e_aqc_opc_set_lb_modes);
2206
2207         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2208
2209         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2210
2211         return status;
2212 }
2213
2214 /**
2215  * i40e_aq_set_phy_debug
2216  * @hw: pointer to the hw struct
2217  * @cmd_flags: debug command flags
2218  * @cmd_details: pointer to command details structure or NULL
2219  *
2220  * Reset the external PHY.
2221  **/
2222 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2223                                 struct i40e_asq_cmd_details *cmd_details)
2224 {
2225         struct i40e_aq_desc desc;
2226         struct i40e_aqc_set_phy_debug *cmd =
2227                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2228         enum i40e_status_code status;
2229
2230         i40e_fill_default_direct_cmd_desc(&desc,
2231                                           i40e_aqc_opc_set_phy_debug);
2232
2233         cmd->command_flags = cmd_flags;
2234
2235         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2236
2237         return status;
2238 }
2239
2240 /**
2241  * i40e_aq_add_vsi
2242  * @hw: pointer to the hw struct
2243  * @vsi_ctx: pointer to a vsi context struct
2244  * @cmd_details: pointer to command details structure or NULL
2245  *
2246  * Add a VSI context to the hardware.
2247 **/
2248 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2249                                 struct i40e_vsi_context *vsi_ctx,
2250                                 struct i40e_asq_cmd_details *cmd_details)
2251 {
2252         struct i40e_aq_desc desc;
2253         struct i40e_aqc_add_get_update_vsi *cmd =
2254                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2255         struct i40e_aqc_add_get_update_vsi_completion *resp =
2256                 (struct i40e_aqc_add_get_update_vsi_completion *)
2257                 &desc.params.raw;
2258         enum i40e_status_code status;
2259
2260         i40e_fill_default_direct_cmd_desc(&desc,
2261                                           i40e_aqc_opc_add_vsi);
2262
2263         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2264         cmd->connection_type = vsi_ctx->connection_type;
2265         cmd->vf_id = vsi_ctx->vf_num;
2266         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2267
2268         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2269
2270         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2271                                     sizeof(vsi_ctx->info), cmd_details);
2272
2273         if (status != I40E_SUCCESS)
2274                 goto aq_add_vsi_exit;
2275
2276         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2277         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2278         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2279         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2280
2281 aq_add_vsi_exit:
2282         return status;
2283 }
2284
2285 /**
2286  * i40e_aq_set_default_vsi
2287  * @hw: pointer to the hw struct
2288  * @seid: vsi number
2289  * @cmd_details: pointer to command details structure or NULL
2290  **/
2291 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2292                                 u16 seid,
2293                                 struct i40e_asq_cmd_details *cmd_details)
2294 {
2295         struct i40e_aq_desc desc;
2296         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2297                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2298                 &desc.params.raw;
2299         enum i40e_status_code status;
2300
2301         i40e_fill_default_direct_cmd_desc(&desc,
2302                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2303
2304         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2305         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2306         cmd->seid = CPU_TO_LE16(seid);
2307
2308         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2309
2310         return status;
2311 }
2312
2313 /**
2314  * i40e_aq_clear_default_vsi
2315  * @hw: pointer to the hw struct
2316  * @seid: vsi number
2317  * @cmd_details: pointer to command details structure or NULL
2318  **/
2319 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2320                                 u16 seid,
2321                                 struct i40e_asq_cmd_details *cmd_details)
2322 {
2323         struct i40e_aq_desc desc;
2324         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2325                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2326                 &desc.params.raw;
2327         enum i40e_status_code status;
2328
2329         i40e_fill_default_direct_cmd_desc(&desc,
2330                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2331
2332         cmd->promiscuous_flags = CPU_TO_LE16(0);
2333         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2334         cmd->seid = CPU_TO_LE16(seid);
2335
2336         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2337
2338         return status;
2339 }
2340
2341 /**
2342  * i40e_aq_set_vsi_unicast_promiscuous
2343  * @hw: pointer to the hw struct
2344  * @seid: vsi number
2345  * @set: set unicast promiscuous enable/disable
2346  * @cmd_details: pointer to command details structure or NULL
2347  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2348  **/
2349 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2350                                 u16 seid, bool set,
2351                                 struct i40e_asq_cmd_details *cmd_details,
2352                                 bool rx_only_promisc)
2353 {
2354         struct i40e_aq_desc desc;
2355         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2356                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2357         enum i40e_status_code status;
2358         u16 flags = 0;
2359
2360         i40e_fill_default_direct_cmd_desc(&desc,
2361                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2362
2363         if (set) {
2364                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2365                 if (rx_only_promisc &&
2366                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2367                      (hw->aq.api_maj_ver > 1)))
2368                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2369         }
2370
2371         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2372
2373         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2374         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2375              (hw->aq.api_maj_ver > 1))
2376                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2377
2378         cmd->seid = CPU_TO_LE16(seid);
2379         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2380
2381         return status;
2382 }
2383
2384 /**
2385  * i40e_aq_set_vsi_multicast_promiscuous
2386  * @hw: pointer to the hw struct
2387  * @seid: vsi number
2388  * @set: set multicast promiscuous enable/disable
2389  * @cmd_details: pointer to command details structure or NULL
2390  **/
2391 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2392                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2393 {
2394         struct i40e_aq_desc desc;
2395         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2396                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2397         enum i40e_status_code status;
2398         u16 flags = 0;
2399
2400         i40e_fill_default_direct_cmd_desc(&desc,
2401                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2402
2403         if (set)
2404                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2405
2406         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2407
2408         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2409
2410         cmd->seid = CPU_TO_LE16(seid);
2411         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2412
2413         return status;
2414 }
2415
2416 /**
2417 * i40e_aq_set_vsi_full_promiscuous
2418 * @hw: pointer to the hw struct
2419 * @seid: VSI number
2420 * @set: set promiscuous enable/disable
2421 * @cmd_details: pointer to command details structure or NULL
2422 **/
2423 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2424                                 u16 seid, bool set,
2425                                 struct i40e_asq_cmd_details *cmd_details)
2426 {
2427         struct i40e_aq_desc desc;
2428         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2429                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2430         enum i40e_status_code status;
2431         u16 flags = 0;
2432
2433         i40e_fill_default_direct_cmd_desc(&desc,
2434                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2435
2436         if (set)
2437                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2438                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2439                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2440
2441         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2442
2443         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2444                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2445                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2446
2447         cmd->seid = CPU_TO_LE16(seid);
2448         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2449
2450         return status;
2451 }
2452
2453 /**
2454  * i40e_aq_set_vsi_mc_promisc_on_vlan
2455  * @hw: pointer to the hw struct
2456  * @seid: vsi number
2457  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2458  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2459  * @cmd_details: pointer to command details structure or NULL
2460  **/
2461 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2462                                 u16 seid, bool enable, u16 vid,
2463                                 struct i40e_asq_cmd_details *cmd_details)
2464 {
2465         struct i40e_aq_desc desc;
2466         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2467                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2468         enum i40e_status_code status;
2469         u16 flags = 0;
2470
2471         i40e_fill_default_direct_cmd_desc(&desc,
2472                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2473
2474         if (enable)
2475                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2476
2477         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2478         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2479         cmd->seid = CPU_TO_LE16(seid);
2480         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2481
2482         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2483
2484         return status;
2485 }
2486
2487 /**
2488  * i40e_aq_set_vsi_uc_promisc_on_vlan
2489  * @hw: pointer to the hw struct
2490  * @seid: vsi number
2491  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2492  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2493  * @cmd_details: pointer to command details structure or NULL
2494  **/
2495 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2496                                 u16 seid, bool enable, u16 vid,
2497                                 struct i40e_asq_cmd_details *cmd_details)
2498 {
2499         struct i40e_aq_desc desc;
2500         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2501                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2502         enum i40e_status_code status;
2503         u16 flags = 0;
2504
2505         i40e_fill_default_direct_cmd_desc(&desc,
2506                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2507
2508         if (enable)
2509                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2510
2511         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2512         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2513         cmd->seid = CPU_TO_LE16(seid);
2514         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2515
2516         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2517
2518         return status;
2519 }
2520
2521 /**
2522  * i40e_aq_set_vsi_bc_promisc_on_vlan
2523  * @hw: pointer to the hw struct
2524  * @seid: vsi number
2525  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2526  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2527  * @cmd_details: pointer to command details structure or NULL
2528  **/
2529 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2530                                 u16 seid, bool enable, u16 vid,
2531                                 struct i40e_asq_cmd_details *cmd_details)
2532 {
2533         struct i40e_aq_desc desc;
2534         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2535                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2536         enum i40e_status_code status;
2537         u16 flags = 0;
2538
2539         i40e_fill_default_direct_cmd_desc(&desc,
2540                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2541
2542         if (enable)
2543                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2544
2545         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2546         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2547         cmd->seid = CPU_TO_LE16(seid);
2548         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2549
2550         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2551
2552         return status;
2553 }
2554
2555 /**
2556  * i40e_aq_set_vsi_broadcast
2557  * @hw: pointer to the hw struct
2558  * @seid: vsi number
2559  * @set_filter: true to set filter, false to clear filter
2560  * @cmd_details: pointer to command details structure or NULL
2561  *
2562  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2563  **/
2564 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2565                                 u16 seid, bool set_filter,
2566                                 struct i40e_asq_cmd_details *cmd_details)
2567 {
2568         struct i40e_aq_desc desc;
2569         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2570                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2571         enum i40e_status_code status;
2572
2573         i40e_fill_default_direct_cmd_desc(&desc,
2574                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2575
2576         if (set_filter)
2577                 cmd->promiscuous_flags
2578                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2579         else
2580                 cmd->promiscuous_flags
2581                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2582
2583         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2584         cmd->seid = CPU_TO_LE16(seid);
2585         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2586
2587         return status;
2588 }
2589
2590 /**
2591  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2592  * @hw: pointer to the hw struct
2593  * @seid: vsi number
2594  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2595  * @cmd_details: pointer to command details structure or NULL
2596  **/
2597 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2598                                 u16 seid, bool enable,
2599                                 struct i40e_asq_cmd_details *cmd_details)
2600 {
2601         struct i40e_aq_desc desc;
2602         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2603                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2604         enum i40e_status_code status;
2605         u16 flags = 0;
2606
2607         i40e_fill_default_direct_cmd_desc(&desc,
2608                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2609         if (enable)
2610                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2611
2612         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2613         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2614         cmd->seid = CPU_TO_LE16(seid);
2615
2616         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2617
2618         return status;
2619 }
2620
2621 /**
2622  * i40e_get_vsi_params - get VSI configuration info
2623  * @hw: pointer to the hw struct
2624  * @vsi_ctx: pointer to a vsi context struct
2625  * @cmd_details: pointer to command details structure or NULL
2626  **/
2627 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2628                                 struct i40e_vsi_context *vsi_ctx,
2629                                 struct i40e_asq_cmd_details *cmd_details)
2630 {
2631         struct i40e_aq_desc desc;
2632         struct i40e_aqc_add_get_update_vsi *cmd =
2633                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2634         struct i40e_aqc_add_get_update_vsi_completion *resp =
2635                 (struct i40e_aqc_add_get_update_vsi_completion *)
2636                 &desc.params.raw;
2637         enum i40e_status_code status;
2638
2639         UNREFERENCED_1PARAMETER(cmd_details);
2640         i40e_fill_default_direct_cmd_desc(&desc,
2641                                           i40e_aqc_opc_get_vsi_parameters);
2642
2643         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2644
2645         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2646
2647         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2648                                     sizeof(vsi_ctx->info), NULL);
2649
2650         if (status != I40E_SUCCESS)
2651                 goto aq_get_vsi_params_exit;
2652
2653         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2654         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2655         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2656         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2657
2658 aq_get_vsi_params_exit:
2659         return status;
2660 }
2661
2662 /**
2663  * i40e_aq_update_vsi_params
2664  * @hw: pointer to the hw struct
2665  * @vsi_ctx: pointer to a vsi context struct
2666  * @cmd_details: pointer to command details structure or NULL
2667  *
2668  * Update a VSI context.
2669  **/
2670 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2671                                 struct i40e_vsi_context *vsi_ctx,
2672                                 struct i40e_asq_cmd_details *cmd_details)
2673 {
2674         struct i40e_aq_desc desc;
2675         struct i40e_aqc_add_get_update_vsi *cmd =
2676                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2677         struct i40e_aqc_add_get_update_vsi_completion *resp =
2678                 (struct i40e_aqc_add_get_update_vsi_completion *)
2679                 &desc.params.raw;
2680         enum i40e_status_code status;
2681
2682         i40e_fill_default_direct_cmd_desc(&desc,
2683                                           i40e_aqc_opc_update_vsi_parameters);
2684         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2685
2686         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2687
2688         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2689                                     sizeof(vsi_ctx->info), cmd_details);
2690
2691         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2692         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2693
2694         return status;
2695 }
2696
2697 /**
2698  * i40e_aq_get_switch_config
2699  * @hw: pointer to the hardware structure
2700  * @buf: pointer to the result buffer
2701  * @buf_size: length of input buffer
2702  * @start_seid: seid to start for the report, 0 == beginning
2703  * @cmd_details: pointer to command details structure or NULL
2704  *
2705  * Fill the buf with switch configuration returned from AdminQ command
2706  **/
2707 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2708                                 struct i40e_aqc_get_switch_config_resp *buf,
2709                                 u16 buf_size, u16 *start_seid,
2710                                 struct i40e_asq_cmd_details *cmd_details)
2711 {
2712         struct i40e_aq_desc desc;
2713         struct i40e_aqc_switch_seid *scfg =
2714                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2715         enum i40e_status_code status;
2716
2717         i40e_fill_default_direct_cmd_desc(&desc,
2718                                           i40e_aqc_opc_get_switch_config);
2719         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2720         if (buf_size > I40E_AQ_LARGE_BUF)
2721                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2722         scfg->seid = CPU_TO_LE16(*start_seid);
2723
2724         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2725         *start_seid = LE16_TO_CPU(scfg->seid);
2726
2727         return status;
2728 }
2729
2730 /**
2731  * i40e_aq_set_switch_config
2732  * @hw: pointer to the hardware structure
2733  * @flags: bit flag values to set
2734  * @mode: cloud filter mode
2735  * @valid_flags: which bit flags to set
2736  * @cmd_details: pointer to command details structure or NULL
2737  *
2738  * Set switch configuration bits
2739  **/
2740 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2741                                 u16 flags, u16 valid_flags, u8 mode,
2742                                 struct i40e_asq_cmd_details *cmd_details)
2743 {
2744         struct i40e_aq_desc desc;
2745         struct i40e_aqc_set_switch_config *scfg =
2746                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2747         enum i40e_status_code status;
2748
2749         i40e_fill_default_direct_cmd_desc(&desc,
2750                                           i40e_aqc_opc_set_switch_config);
2751         scfg->flags = CPU_TO_LE16(flags);
2752         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2753         scfg->mode = mode;
2754         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2755                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2756                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2757                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2758         }
2759         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2760
2761         return status;
2762 }
2763
2764 /**
2765  * i40e_aq_get_firmware_version
2766  * @hw: pointer to the hw struct
2767  * @fw_major_version: firmware major version
2768  * @fw_minor_version: firmware minor version
2769  * @fw_build: firmware build number
2770  * @api_major_version: major queue version
2771  * @api_minor_version: minor queue version
2772  * @cmd_details: pointer to command details structure or NULL
2773  *
2774  * Get the firmware version from the admin queue commands
2775  **/
2776 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2777                                 u16 *fw_major_version, u16 *fw_minor_version,
2778                                 u32 *fw_build,
2779                                 u16 *api_major_version, u16 *api_minor_version,
2780                                 struct i40e_asq_cmd_details *cmd_details)
2781 {
2782         struct i40e_aq_desc desc;
2783         struct i40e_aqc_get_version *resp =
2784                 (struct i40e_aqc_get_version *)&desc.params.raw;
2785         enum i40e_status_code status;
2786
2787         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2788
2789         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2790
2791         if (status == I40E_SUCCESS) {
2792                 if (fw_major_version != NULL)
2793                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2794                 if (fw_minor_version != NULL)
2795                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2796                 if (fw_build != NULL)
2797                         *fw_build = LE32_TO_CPU(resp->fw_build);
2798                 if (api_major_version != NULL)
2799                         *api_major_version = LE16_TO_CPU(resp->api_major);
2800                 if (api_minor_version != NULL)
2801                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2802
2803                 /* A workaround to fix the API version in SW */
2804                 if (api_major_version && api_minor_version &&
2805                     fw_major_version && fw_minor_version &&
2806                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2807                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2808                      (*fw_major_version > 4)))
2809                         *api_minor_version = 2;
2810         }
2811
2812         return status;
2813 }
2814
2815 /**
2816  * i40e_aq_send_driver_version
2817  * @hw: pointer to the hw struct
2818  * @dv: driver's major, minor version
2819  * @cmd_details: pointer to command details structure or NULL
2820  *
2821  * Send the driver version to the firmware
2822  **/
2823 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2824                                 struct i40e_driver_version *dv,
2825                                 struct i40e_asq_cmd_details *cmd_details)
2826 {
2827         struct i40e_aq_desc desc;
2828         struct i40e_aqc_driver_version *cmd =
2829                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2830         enum i40e_status_code status;
2831         u16 len;
2832
2833         if (dv == NULL)
2834                 return I40E_ERR_PARAM;
2835
2836         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2837
2838         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2839         cmd->driver_major_ver = dv->major_version;
2840         cmd->driver_minor_ver = dv->minor_version;
2841         cmd->driver_build_ver = dv->build_version;
2842         cmd->driver_subbuild_ver = dv->subbuild_version;
2843
2844         len = 0;
2845         while (len < sizeof(dv->driver_string) &&
2846                (dv->driver_string[len] < 0x80) &&
2847                dv->driver_string[len])
2848                 len++;
2849         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2850                                        len, cmd_details);
2851
2852         return status;
2853 }
2854
2855 /**
2856  * i40e_get_link_status - get status of the HW network link
2857  * @hw: pointer to the hw struct
2858  * @link_up: pointer to bool (true/false = linkup/linkdown)
2859  *
2860  * Variable link_up true if link is up, false if link is down.
2861  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2862  *
2863  * Side effect: LinkStatusEvent reporting becomes enabled
2864  **/
2865 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2866 {
2867         enum i40e_status_code status = I40E_SUCCESS;
2868
2869         if (hw->phy.get_link_info) {
2870                 status = i40e_update_link_info(hw);
2871
2872                 if (status != I40E_SUCCESS)
2873                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2874                                    status);
2875         }
2876
2877         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2878
2879         return status;
2880 }
2881
2882 /**
2883  * i40e_updatelink_status - update status of the HW network link
2884  * @hw: pointer to the hw struct
2885  **/
2886 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2887 {
2888         struct i40e_aq_get_phy_abilities_resp abilities;
2889         enum i40e_status_code status = I40E_SUCCESS;
2890
2891         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2892         if (status)
2893                 return status;
2894
2895         /* extra checking needed to ensure link info to user is timely */
2896         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2897             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2898              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2899                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2900                                                       &abilities, NULL);
2901                 if (status)
2902                         return status;
2903
2904                 hw->phy.link_info.req_fec_info =
2905                         abilities.fec_cfg_curr_mod_ext_info &
2906                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2907
2908                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2909                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2910         }
2911         return status;
2912 }
2913
2914
2915 /**
2916  * i40e_get_link_speed
2917  * @hw: pointer to the hw struct
2918  *
2919  * Returns the link speed of the adapter.
2920  **/
2921 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2922 {
2923         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2924         enum i40e_status_code status = I40E_SUCCESS;
2925
2926         if (hw->phy.get_link_info) {
2927                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2928
2929                 if (status != I40E_SUCCESS)
2930                         goto i40e_link_speed_exit;
2931         }
2932
2933         speed = hw->phy.link_info.link_speed;
2934
2935 i40e_link_speed_exit:
2936         return speed;
2937 }
2938
2939 /**
2940  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2941  * @hw: pointer to the hw struct
2942  * @uplink_seid: the MAC or other gizmo SEID
2943  * @downlink_seid: the VSI SEID
2944  * @enabled_tc: bitmap of TCs to be enabled
2945  * @default_port: true for default port VSI, false for control port
2946  * @veb_seid: pointer to where to put the resulting VEB SEID
2947  * @enable_stats: true to turn on VEB stats
2948  * @cmd_details: pointer to command details structure or NULL
2949  *
2950  * This asks the FW to add a VEB between the uplink and downlink
2951  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2952  **/
2953 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2954                                 u16 downlink_seid, u8 enabled_tc,
2955                                 bool default_port, u16 *veb_seid,
2956                                 bool enable_stats,
2957                                 struct i40e_asq_cmd_details *cmd_details)
2958 {
2959         struct i40e_aq_desc desc;
2960         struct i40e_aqc_add_veb *cmd =
2961                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2962         struct i40e_aqc_add_veb_completion *resp =
2963                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2964         enum i40e_status_code status;
2965         u16 veb_flags = 0;
2966
2967         /* SEIDs need to either both be set or both be 0 for floating VEB */
2968         if (!!uplink_seid != !!downlink_seid)
2969                 return I40E_ERR_PARAM;
2970
2971         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2972
2973         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2974         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2975         cmd->enable_tcs = enabled_tc;
2976         if (!uplink_seid)
2977                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2978         if (default_port)
2979                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2980         else
2981                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2982
2983         /* reverse logic here: set the bitflag to disable the stats */
2984         if (!enable_stats)
2985                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2986
2987         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2988
2989         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2990
2991         if (!status && veb_seid)
2992                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2993
2994         return status;
2995 }
2996
2997 /**
2998  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2999  * @hw: pointer to the hw struct
3000  * @veb_seid: the SEID of the VEB to query
3001  * @switch_id: the uplink switch id
3002  * @floating: set to true if the VEB is floating
3003  * @statistic_index: index of the stats counter block for this VEB
3004  * @vebs_used: number of VEB's used by function
3005  * @vebs_free: total VEB's not reserved by any function
3006  * @cmd_details: pointer to command details structure or NULL
3007  *
3008  * This retrieves the parameters for a particular VEB, specified by
3009  * uplink_seid, and returns them to the caller.
3010  **/
3011 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3012                                 u16 veb_seid, u16 *switch_id,
3013                                 bool *floating, u16 *statistic_index,
3014                                 u16 *vebs_used, u16 *vebs_free,
3015                                 struct i40e_asq_cmd_details *cmd_details)
3016 {
3017         struct i40e_aq_desc desc;
3018         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3019                 (struct i40e_aqc_get_veb_parameters_completion *)
3020                 &desc.params.raw;
3021         enum i40e_status_code status;
3022
3023         if (veb_seid == 0)
3024                 return I40E_ERR_PARAM;
3025
3026         i40e_fill_default_direct_cmd_desc(&desc,
3027                                           i40e_aqc_opc_get_veb_parameters);
3028         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3029
3030         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3031         if (status)
3032                 goto get_veb_exit;
3033
3034         if (switch_id)
3035                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3036         if (statistic_index)
3037                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3038         if (vebs_used)
3039                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3040         if (vebs_free)
3041                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3042         if (floating) {
3043                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3044
3045                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3046                         *floating = true;
3047                 else
3048                         *floating = false;
3049         }
3050
3051 get_veb_exit:
3052         return status;
3053 }
3054
3055 /**
3056  * i40e_aq_add_macvlan
3057  * @hw: pointer to the hw struct
3058  * @seid: VSI for the mac address
3059  * @mv_list: list of macvlans to be added
3060  * @count: length of the list
3061  * @cmd_details: pointer to command details structure or NULL
3062  *
3063  * Add MAC/VLAN addresses to the HW filtering
3064  **/
3065 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3066                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3067                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3068 {
3069         struct i40e_aq_desc desc;
3070         struct i40e_aqc_macvlan *cmd =
3071                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3072         enum i40e_status_code status;
3073         u16 buf_size;
3074         int i;
3075
3076         if (count == 0 || !mv_list || !hw)
3077                 return I40E_ERR_PARAM;
3078
3079         buf_size = count * sizeof(*mv_list);
3080
3081         /* prep the rest of the request */
3082         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3083         cmd->num_addresses = CPU_TO_LE16(count);
3084         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3085         cmd->seid[1] = 0;
3086         cmd->seid[2] = 0;
3087
3088         for (i = 0; i < count; i++)
3089                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3090                         mv_list[i].flags |=
3091                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3092
3093         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3094         if (buf_size > I40E_AQ_LARGE_BUF)
3095                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3096
3097         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3098                                        cmd_details);
3099
3100         return status;
3101 }
3102
3103 /**
3104  * i40e_aq_remove_macvlan
3105  * @hw: pointer to the hw struct
3106  * @seid: VSI for the mac address
3107  * @mv_list: list of macvlans to be removed
3108  * @count: length of the list
3109  * @cmd_details: pointer to command details structure or NULL
3110  *
3111  * Remove MAC/VLAN addresses from the HW filtering
3112  **/
3113 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3114                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3115                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3116 {
3117         struct i40e_aq_desc desc;
3118         struct i40e_aqc_macvlan *cmd =
3119                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3120         enum i40e_status_code status;
3121         u16 buf_size;
3122
3123         if (count == 0 || !mv_list || !hw)
3124                 return I40E_ERR_PARAM;
3125
3126         buf_size = count * sizeof(*mv_list);
3127
3128         /* prep the rest of the request */
3129         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3130         cmd->num_addresses = CPU_TO_LE16(count);
3131         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3132         cmd->seid[1] = 0;
3133         cmd->seid[2] = 0;
3134
3135         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3136         if (buf_size > I40E_AQ_LARGE_BUF)
3137                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3138
3139         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3140                                        cmd_details);
3141
3142         return status;
3143 }
3144
3145 /**
3146  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3147  * @hw: pointer to the hw struct
3148  * @opcode: AQ opcode for add or delete mirror rule
3149  * @sw_seid: Switch SEID (to which rule refers)
3150  * @rule_type: Rule Type (ingress/egress/VLAN)
3151  * @id: Destination VSI SEID or Rule ID
3152  * @count: length of the list
3153  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3154  * @cmd_details: pointer to command details structure or NULL
3155  * @rule_id: Rule ID returned from FW
3156  * @rules_used: Number of rules used in internal switch
3157  * @rules_free: Number of rules free in internal switch
3158  *
3159  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3160  * VEBs/VEPA elements only
3161  **/
3162 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3163                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3164                         u16 count, __le16 *mr_list,
3165                         struct i40e_asq_cmd_details *cmd_details,
3166                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3167 {
3168         struct i40e_aq_desc desc;
3169         struct i40e_aqc_add_delete_mirror_rule *cmd =
3170                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3171         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3172         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3173         enum i40e_status_code status;
3174         u16 buf_size;
3175
3176         buf_size = count * sizeof(*mr_list);
3177
3178         /* prep the rest of the request */
3179         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3180         cmd->seid = CPU_TO_LE16(sw_seid);
3181         cmd->rule_type = CPU_TO_LE16(rule_type &
3182                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3183         cmd->num_entries = CPU_TO_LE16(count);
3184         /* Dest VSI for add, rule_id for delete */
3185         cmd->destination = CPU_TO_LE16(id);
3186         if (mr_list) {
3187                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3188                                                 I40E_AQ_FLAG_RD));
3189                 if (buf_size > I40E_AQ_LARGE_BUF)
3190                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3191         }
3192
3193         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3194                                        cmd_details);
3195         if (status == I40E_SUCCESS ||
3196             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3197                 if (rule_id)
3198                         *rule_id = LE16_TO_CPU(resp->rule_id);
3199                 if (rules_used)
3200                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3201                 if (rules_free)
3202                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3203         }
3204         return status;
3205 }
3206
3207 /**
3208  * i40e_aq_add_mirrorrule - add a mirror rule
3209  * @hw: pointer to the hw struct
3210  * @sw_seid: Switch SEID (to which rule refers)
3211  * @rule_type: Rule Type (ingress/egress/VLAN)
3212  * @dest_vsi: SEID of VSI to which packets will be mirrored
3213  * @count: length of the list
3214  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3215  * @cmd_details: pointer to command details structure or NULL
3216  * @rule_id: Rule ID returned from FW
3217  * @rules_used: Number of rules used in internal switch
3218  * @rules_free: Number of rules free in internal switch
3219  *
3220  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3221  **/
3222 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3223                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3224                         struct i40e_asq_cmd_details *cmd_details,
3225                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3226 {
3227         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3228             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3229                 if (count == 0 || !mr_list)
3230                         return I40E_ERR_PARAM;
3231         }
3232
3233         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3234                                   rule_type, dest_vsi, count, mr_list,
3235                                   cmd_details, rule_id, rules_used, rules_free);
3236 }
3237
3238 /**
3239  * i40e_aq_delete_mirrorrule - delete a mirror rule
3240  * @hw: pointer to the hw struct
3241  * @sw_seid: Switch SEID (to which rule refers)
3242  * @rule_type: Rule Type (ingress/egress/VLAN)
3243  * @count: length of the list
3244  * @rule_id: Rule ID that is returned in the receive desc as part of
3245  *              add_mirrorrule.
3246  * @mr_list: list of mirrored VLAN IDs to be removed
3247  * @cmd_details: pointer to command details structure or NULL
3248  * @rules_used: Number of rules used in internal switch
3249  * @rules_free: Number of rules free in internal switch
3250  *
3251  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3252  **/
3253 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3254                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3255                         struct i40e_asq_cmd_details *cmd_details,
3256                         u16 *rules_used, u16 *rules_free)
3257 {
3258         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3259         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3260                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3261                  * mirroring. For other rule_type, count and rule_type should
3262                  * not matter.
3263                  */
3264                 if (count == 0 || !mr_list)
3265                         return I40E_ERR_PARAM;
3266         }
3267
3268         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3269                                   rule_type, rule_id, count, mr_list,
3270                                   cmd_details, NULL, rules_used, rules_free);
3271 }
3272
3273 /**
3274  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3275  * @hw: pointer to the hw struct
3276  * @seid: VSI for the vlan filters
3277  * @v_list: list of vlan filters to be added
3278  * @count: length of the list
3279  * @cmd_details: pointer to command details structure or NULL
3280  **/
3281 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3282                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3283                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3284 {
3285         struct i40e_aq_desc desc;
3286         struct i40e_aqc_macvlan *cmd =
3287                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3288         enum i40e_status_code status;
3289         u16 buf_size;
3290
3291         if (count == 0 || !v_list || !hw)
3292                 return I40E_ERR_PARAM;
3293
3294         buf_size = count * sizeof(*v_list);
3295
3296         /* prep the rest of the request */
3297         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3298         cmd->num_addresses = CPU_TO_LE16(count);
3299         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3300         cmd->seid[1] = 0;
3301         cmd->seid[2] = 0;
3302
3303         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3304         if (buf_size > I40E_AQ_LARGE_BUF)
3305                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3306
3307         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3308                                        cmd_details);
3309
3310         return status;
3311 }
3312
3313 /**
3314  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3315  * @hw: pointer to the hw struct
3316  * @seid: VSI for the vlan filters
3317  * @v_list: list of macvlans to be removed
3318  * @count: length of the list
3319  * @cmd_details: pointer to command details structure or NULL
3320  **/
3321 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3322                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3323                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3324 {
3325         struct i40e_aq_desc desc;
3326         struct i40e_aqc_macvlan *cmd =
3327                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3328         enum i40e_status_code status;
3329         u16 buf_size;
3330
3331         if (count == 0 || !v_list || !hw)
3332                 return I40E_ERR_PARAM;
3333
3334         buf_size = count * sizeof(*v_list);
3335
3336         /* prep the rest of the request */
3337         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3338         cmd->num_addresses = CPU_TO_LE16(count);
3339         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3340         cmd->seid[1] = 0;
3341         cmd->seid[2] = 0;
3342
3343         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3344         if (buf_size > I40E_AQ_LARGE_BUF)
3345                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3346
3347         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3348                                        cmd_details);
3349
3350         return status;
3351 }
3352
3353 /**
3354  * i40e_aq_send_msg_to_vf
3355  * @hw: pointer to the hardware structure
3356  * @vfid: vf id to send msg
3357  * @v_opcode: opcodes for VF-PF communication
3358  * @v_retval: return error code
3359  * @msg: pointer to the msg buffer
3360  * @msglen: msg length
3361  * @cmd_details: pointer to command details
3362  *
3363  * send msg to vf
3364  **/
3365 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3366                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3367                                 struct i40e_asq_cmd_details *cmd_details)
3368 {
3369         struct i40e_aq_desc desc;
3370         struct i40e_aqc_pf_vf_message *cmd =
3371                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3372         enum i40e_status_code status;
3373
3374         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3375         cmd->id = CPU_TO_LE32(vfid);
3376         desc.cookie_high = CPU_TO_LE32(v_opcode);
3377         desc.cookie_low = CPU_TO_LE32(v_retval);
3378         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3379         if (msglen) {
3380                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3381                                                 I40E_AQ_FLAG_RD));
3382                 if (msglen > I40E_AQ_LARGE_BUF)
3383                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3384                 desc.datalen = CPU_TO_LE16(msglen);
3385         }
3386         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3387
3388         return status;
3389 }
3390
3391 /**
3392  * i40e_aq_debug_read_register
3393  * @hw: pointer to the hw struct
3394  * @reg_addr: register address
3395  * @reg_val: register value
3396  * @cmd_details: pointer to command details structure or NULL
3397  *
3398  * Read the register using the admin queue commands
3399  **/
3400 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3401                                 u32 reg_addr, u64 *reg_val,
3402                                 struct i40e_asq_cmd_details *cmd_details)
3403 {
3404         struct i40e_aq_desc desc;
3405         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3406                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3407         enum i40e_status_code status;
3408
3409         if (reg_val == NULL)
3410                 return I40E_ERR_PARAM;
3411
3412         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3413
3414         cmd_resp->address = CPU_TO_LE32(reg_addr);
3415
3416         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3417
3418         if (status == I40E_SUCCESS) {
3419                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3420                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3421         }
3422
3423         return status;
3424 }
3425
3426 /**
3427  * i40e_aq_debug_write_register
3428  * @hw: pointer to the hw struct
3429  * @reg_addr: register address
3430  * @reg_val: register value
3431  * @cmd_details: pointer to command details structure or NULL
3432  *
3433  * Write to a register using the admin queue commands
3434  **/
3435 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3436                                 u32 reg_addr, u64 reg_val,
3437                                 struct i40e_asq_cmd_details *cmd_details)
3438 {
3439         struct i40e_aq_desc desc;
3440         struct i40e_aqc_debug_reg_read_write *cmd =
3441                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3442         enum i40e_status_code status;
3443
3444         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3445
3446         cmd->address = CPU_TO_LE32(reg_addr);
3447         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3448         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3449
3450         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3451
3452         return status;
3453 }
3454
3455 /**
3456  * i40e_aq_request_resource
3457  * @hw: pointer to the hw struct
3458  * @resource: resource id
3459  * @access: access type
3460  * @sdp_number: resource number
3461  * @timeout: the maximum time in ms that the driver may hold the resource
3462  * @cmd_details: pointer to command details structure or NULL
3463  *
3464  * requests common resource using the admin queue commands
3465  **/
3466 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3467                                 enum i40e_aq_resources_ids resource,
3468                                 enum i40e_aq_resource_access_type access,
3469                                 u8 sdp_number, u64 *timeout,
3470                                 struct i40e_asq_cmd_details *cmd_details)
3471 {
3472         struct i40e_aq_desc desc;
3473         struct i40e_aqc_request_resource *cmd_resp =
3474                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3475         enum i40e_status_code status;
3476
3477         DEBUGFUNC("i40e_aq_request_resource");
3478
3479         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3480
3481         cmd_resp->resource_id = CPU_TO_LE16(resource);
3482         cmd_resp->access_type = CPU_TO_LE16(access);
3483         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3484
3485         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3486         /* The completion specifies the maximum time in ms that the driver
3487          * may hold the resource in the Timeout field.
3488          * If the resource is held by someone else, the command completes with
3489          * busy return value and the timeout field indicates the maximum time
3490          * the current owner of the resource has to free it.
3491          */
3492         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3493                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3494
3495         return status;
3496 }
3497
3498 /**
3499  * i40e_aq_release_resource
3500  * @hw: pointer to the hw struct
3501  * @resource: resource id
3502  * @sdp_number: resource number
3503  * @cmd_details: pointer to command details structure or NULL
3504  *
3505  * release common resource using the admin queue commands
3506  **/
3507 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3508                                 enum i40e_aq_resources_ids resource,
3509                                 u8 sdp_number,
3510                                 struct i40e_asq_cmd_details *cmd_details)
3511 {
3512         struct i40e_aq_desc desc;
3513         struct i40e_aqc_request_resource *cmd =
3514                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3515         enum i40e_status_code status;
3516
3517         DEBUGFUNC("i40e_aq_release_resource");
3518
3519         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3520
3521         cmd->resource_id = CPU_TO_LE16(resource);
3522         cmd->resource_number = CPU_TO_LE32(sdp_number);
3523
3524         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3525
3526         return status;
3527 }
3528
3529 /**
3530  * i40e_aq_read_nvm
3531  * @hw: pointer to the hw struct
3532  * @module_pointer: module pointer location in words from the NVM beginning
3533  * @offset: byte offset from the module beginning
3534  * @length: length of the section to be read (in bytes from the offset)
3535  * @data: command buffer (size [bytes] = length)
3536  * @last_command: tells if this is the last command in a series
3537  * @cmd_details: pointer to command details structure or NULL
3538  *
3539  * Read the NVM using the admin queue commands
3540  **/
3541 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3542                                 u32 offset, u16 length, void *data,
3543                                 bool last_command,
3544                                 struct i40e_asq_cmd_details *cmd_details)
3545 {
3546         struct i40e_aq_desc desc;
3547         struct i40e_aqc_nvm_update *cmd =
3548                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3549         enum i40e_status_code status;
3550
3551         DEBUGFUNC("i40e_aq_read_nvm");
3552
3553         /* In offset the highest byte must be zeroed. */
3554         if (offset & 0xFF000000) {
3555                 status = I40E_ERR_PARAM;
3556                 goto i40e_aq_read_nvm_exit;
3557         }
3558
3559         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3560
3561         /* If this is the last command in a series, set the proper flag. */
3562         if (last_command)
3563                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3564         cmd->module_pointer = module_pointer;
3565         cmd->offset = CPU_TO_LE32(offset);
3566         cmd->length = CPU_TO_LE16(length);
3567
3568         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3569         if (length > I40E_AQ_LARGE_BUF)
3570                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3571
3572         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3573
3574 i40e_aq_read_nvm_exit:
3575         return status;
3576 }
3577
3578 /**
3579  * i40e_aq_read_nvm_config - read an nvm config block
3580  * @hw: pointer to the hw struct
3581  * @cmd_flags: NVM access admin command bits
3582  * @field_id: field or feature id
3583  * @data: buffer for result
3584  * @buf_size: buffer size
3585  * @element_count: pointer to count of elements read by FW
3586  * @cmd_details: pointer to command details structure or NULL
3587  **/
3588 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3589                                 u8 cmd_flags, u32 field_id, void *data,
3590                                 u16 buf_size, u16 *element_count,
3591                                 struct i40e_asq_cmd_details *cmd_details)
3592 {
3593         struct i40e_aq_desc desc;
3594         struct i40e_aqc_nvm_config_read *cmd =
3595                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3596         enum i40e_status_code status;
3597
3598         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3599         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3600         if (buf_size > I40E_AQ_LARGE_BUF)
3601                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3602
3603         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3604         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3605         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3606                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3607         else
3608                 cmd->element_id_msw = 0;
3609
3610         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3611
3612         if (!status && element_count)
3613                 *element_count = LE16_TO_CPU(cmd->element_count);
3614
3615         return status;
3616 }
3617
3618 /**
3619  * i40e_aq_write_nvm_config - write an nvm config block
3620  * @hw: pointer to the hw struct
3621  * @cmd_flags: NVM access admin command bits
3622  * @data: buffer for result
3623  * @buf_size: buffer size
3624  * @element_count: count of elements to be written
3625  * @cmd_details: pointer to command details structure or NULL
3626  **/
3627 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3628                                 u8 cmd_flags, void *data, u16 buf_size,
3629                                 u16 element_count,
3630                                 struct i40e_asq_cmd_details *cmd_details)
3631 {
3632         struct i40e_aq_desc desc;
3633         struct i40e_aqc_nvm_config_write *cmd =
3634                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3635         enum i40e_status_code status;
3636
3637         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3638         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3639         if (buf_size > I40E_AQ_LARGE_BUF)
3640                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3641
3642         cmd->element_count = CPU_TO_LE16(element_count);
3643         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3644         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3645
3646         return status;
3647 }
3648
3649 /**
3650  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3651  * @hw: pointer to the hw struct
3652  * @buff: buffer for result
3653  * @buff_size: buffer size
3654  * @cmd_details: pointer to command details structure or NULL
3655  **/
3656 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3657                                 void *buff, u16 buff_size,
3658                                 struct i40e_asq_cmd_details *cmd_details)
3659 {
3660         struct i40e_aq_desc desc;
3661         enum i40e_status_code status;
3662
3663         UNREFERENCED_2PARAMETER(buff, buff_size);
3664
3665         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3666         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3667         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3668                 status = I40E_ERR_NOT_IMPLEMENTED;
3669
3670         return status;
3671 }
3672
3673 /**
3674  * i40e_aq_erase_nvm
3675  * @hw: pointer to the hw struct
3676  * @module_pointer: module pointer location in words from the NVM beginning
3677  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3678  * @length: length of the section to be erased (expressed in 4 KB)
3679  * @last_command: tells if this is the last command in a series
3680  * @cmd_details: pointer to command details structure or NULL
3681  *
3682  * Erase the NVM sector using the admin queue commands
3683  **/
3684 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3685                                 u32 offset, u16 length, bool last_command,
3686                                 struct i40e_asq_cmd_details *cmd_details)
3687 {
3688         struct i40e_aq_desc desc;
3689         struct i40e_aqc_nvm_update *cmd =
3690                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3691         enum i40e_status_code status;
3692
3693         DEBUGFUNC("i40e_aq_erase_nvm");
3694
3695         /* In offset the highest byte must be zeroed. */
3696         if (offset & 0xFF000000) {
3697                 status = I40E_ERR_PARAM;
3698                 goto i40e_aq_erase_nvm_exit;
3699         }
3700
3701         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3702
3703         /* If this is the last command in a series, set the proper flag. */
3704         if (last_command)
3705                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3706         cmd->module_pointer = module_pointer;
3707         cmd->offset = CPU_TO_LE32(offset);
3708         cmd->length = CPU_TO_LE16(length);
3709
3710         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3711
3712 i40e_aq_erase_nvm_exit:
3713         return status;
3714 }
3715
3716 /**
3717  * i40e_parse_discover_capabilities
3718  * @hw: pointer to the hw struct
3719  * @buff: pointer to a buffer containing device/function capability records
3720  * @cap_count: number of capability records in the list
3721  * @list_type_opc: type of capabilities list to parse
3722  *
3723  * Parse the device/function capabilities list.
3724  **/
3725 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3726                                      u32 cap_count,
3727                                      enum i40e_admin_queue_opc list_type_opc)
3728 {
3729         struct i40e_aqc_list_capabilities_element_resp *cap;
3730         u32 valid_functions, num_functions;
3731         u32 number, logical_id, phys_id;
3732         struct i40e_hw_capabilities *p;
3733         enum i40e_status_code status;
3734         u16 id, ocp_cfg_word0;
3735         u8 major_rev;
3736         u32 i = 0;
3737
3738         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3739
3740         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3741                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3742         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3743                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3744         else
3745                 return;
3746
3747         for (i = 0; i < cap_count; i++, cap++) {
3748                 id = LE16_TO_CPU(cap->id);
3749                 number = LE32_TO_CPU(cap->number);
3750                 logical_id = LE32_TO_CPU(cap->logical_id);
3751                 phys_id = LE32_TO_CPU(cap->phys_id);
3752                 major_rev = cap->major_rev;
3753
3754                 switch (id) {
3755                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3756                         p->switch_mode = number;
3757                         i40e_debug(hw, I40E_DEBUG_INIT,
3758                                    "HW Capability: Switch mode = %d\n",
3759                                    p->switch_mode);
3760                         break;
3761                 case I40E_AQ_CAP_ID_MNG_MODE:
3762                         p->management_mode = number;
3763                         if (major_rev > 1) {
3764                                 p->mng_protocols_over_mctp = logical_id;
3765                                 i40e_debug(hw, I40E_DEBUG_INIT,
3766                                            "HW Capability: Protocols over MCTP = %d\n",
3767                                            p->mng_protocols_over_mctp);
3768                         } else {
3769                                 p->mng_protocols_over_mctp = 0;
3770                         }
3771                         i40e_debug(hw, I40E_DEBUG_INIT,
3772                                    "HW Capability: Management Mode = %d\n",
3773                                    p->management_mode);
3774                         break;
3775                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3776                         p->npar_enable = number;
3777                         i40e_debug(hw, I40E_DEBUG_INIT,
3778                                    "HW Capability: NPAR enable = %d\n",
3779                                    p->npar_enable);
3780                         break;
3781                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3782                         p->os2bmc = number;
3783                         i40e_debug(hw, I40E_DEBUG_INIT,
3784                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3785                         break;
3786                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3787                         p->valid_functions = number;
3788                         i40e_debug(hw, I40E_DEBUG_INIT,
3789                                    "HW Capability: Valid Functions = %d\n",
3790                                    p->valid_functions);
3791                         break;
3792                 case I40E_AQ_CAP_ID_SRIOV:
3793                         if (number == 1)
3794                                 p->sr_iov_1_1 = true;
3795                         i40e_debug(hw, I40E_DEBUG_INIT,
3796                                    "HW Capability: SR-IOV = %d\n",
3797                                    p->sr_iov_1_1);
3798                         break;
3799                 case I40E_AQ_CAP_ID_VF:
3800                         p->num_vfs = number;
3801                         p->vf_base_id = logical_id;
3802                         i40e_debug(hw, I40E_DEBUG_INIT,
3803                                    "HW Capability: VF count = %d\n",
3804                                    p->num_vfs);
3805                         i40e_debug(hw, I40E_DEBUG_INIT,
3806                                    "HW Capability: VF base_id = %d\n",
3807                                    p->vf_base_id);
3808                         break;
3809                 case I40E_AQ_CAP_ID_VMDQ:
3810                         if (number == 1)
3811                                 p->vmdq = true;
3812                         i40e_debug(hw, I40E_DEBUG_INIT,
3813                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3814                         break;
3815                 case I40E_AQ_CAP_ID_8021QBG:
3816                         if (number == 1)
3817                                 p->evb_802_1_qbg = true;
3818                         i40e_debug(hw, I40E_DEBUG_INIT,
3819                                    "HW Capability: 802.1Qbg = %d\n", number);
3820                         break;
3821                 case I40E_AQ_CAP_ID_8021QBR:
3822                         if (number == 1)
3823                                 p->evb_802_1_qbh = true;
3824                         i40e_debug(hw, I40E_DEBUG_INIT,
3825                                    "HW Capability: 802.1Qbh = %d\n", number);
3826                         break;
3827                 case I40E_AQ_CAP_ID_VSI:
3828                         p->num_vsis = number;
3829                         i40e_debug(hw, I40E_DEBUG_INIT,
3830                                    "HW Capability: VSI count = %d\n",
3831                                    p->num_vsis);
3832                         break;
3833                 case I40E_AQ_CAP_ID_DCB:
3834                         if (number == 1) {
3835                                 p->dcb = true;
3836                                 p->enabled_tcmap = logical_id;
3837                                 p->maxtc = phys_id;
3838                         }
3839                         i40e_debug(hw, I40E_DEBUG_INIT,
3840                                    "HW Capability: DCB = %d\n", p->dcb);
3841                         i40e_debug(hw, I40E_DEBUG_INIT,
3842                                    "HW Capability: TC Mapping = %d\n",
3843                                    logical_id);
3844                         i40e_debug(hw, I40E_DEBUG_INIT,
3845                                    "HW Capability: TC Max = %d\n", p->maxtc);
3846                         break;
3847                 case I40E_AQ_CAP_ID_FCOE:
3848                         if (number == 1)
3849                                 p->fcoe = true;
3850                         i40e_debug(hw, I40E_DEBUG_INIT,
3851                                    "HW Capability: FCOE = %d\n", p->fcoe);
3852                         break;
3853                 case I40E_AQ_CAP_ID_ISCSI:
3854                         if (number == 1)
3855                                 p->iscsi = true;
3856                         i40e_debug(hw, I40E_DEBUG_INIT,
3857                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3858                         break;
3859                 case I40E_AQ_CAP_ID_RSS:
3860                         p->rss = true;
3861                         p->rss_table_size = number;
3862                         p->rss_table_entry_width = logical_id;
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: RSS = %d\n", p->rss);
3865                         i40e_debug(hw, I40E_DEBUG_INIT,
3866                                    "HW Capability: RSS table size = %d\n",
3867                                    p->rss_table_size);
3868                         i40e_debug(hw, I40E_DEBUG_INIT,
3869                                    "HW Capability: RSS table width = %d\n",
3870                                    p->rss_table_entry_width);
3871                         break;
3872                 case I40E_AQ_CAP_ID_RXQ:
3873                         p->num_rx_qp = number;
3874                         p->base_queue = phys_id;
3875                         i40e_debug(hw, I40E_DEBUG_INIT,
3876                                    "HW Capability: Rx QP = %d\n", number);
3877                         i40e_debug(hw, I40E_DEBUG_INIT,
3878                                    "HW Capability: base_queue = %d\n",
3879                                    p->base_queue);
3880                         break;
3881                 case I40E_AQ_CAP_ID_TXQ:
3882                         p->num_tx_qp = number;
3883                         p->base_queue = phys_id;
3884                         i40e_debug(hw, I40E_DEBUG_INIT,
3885                                    "HW Capability: Tx QP = %d\n", number);
3886                         i40e_debug(hw, I40E_DEBUG_INIT,
3887                                    "HW Capability: base_queue = %d\n",
3888                                    p->base_queue);
3889                         break;
3890                 case I40E_AQ_CAP_ID_MSIX:
3891                         p->num_msix_vectors = number;
3892                         i40e_debug(hw, I40E_DEBUG_INIT,
3893                                    "HW Capability: MSIX vector count = %d\n",
3894                                    p->num_msix_vectors);
3895                         break;
3896                 case I40E_AQ_CAP_ID_VF_MSIX:
3897                         p->num_msix_vectors_vf = number;
3898                         i40e_debug(hw, I40E_DEBUG_INIT,
3899                                    "HW Capability: MSIX VF vector count = %d\n",
3900                                    p->num_msix_vectors_vf);
3901                         break;
3902                 case I40E_AQ_CAP_ID_FLEX10:
3903                         if (major_rev == 1) {
3904                                 if (number == 1) {
3905                                         p->flex10_enable = true;
3906                                         p->flex10_capable = true;
3907                                 }
3908                         } else {
3909                                 /* Capability revision >= 2 */
3910                                 if (number & 1)
3911                                         p->flex10_enable = true;
3912                                 if (number & 2)
3913                                         p->flex10_capable = true;
3914                         }
3915                         p->flex10_mode = logical_id;
3916                         p->flex10_status = phys_id;
3917                         i40e_debug(hw, I40E_DEBUG_INIT,
3918                                    "HW Capability: Flex10 mode = %d\n",
3919                                    p->flex10_mode);
3920                         i40e_debug(hw, I40E_DEBUG_INIT,
3921                                    "HW Capability: Flex10 status = %d\n",
3922                                    p->flex10_status);
3923                         break;
3924                 case I40E_AQ_CAP_ID_CEM:
3925                         if (number == 1)
3926                                 p->mgmt_cem = true;
3927                         i40e_debug(hw, I40E_DEBUG_INIT,
3928                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3929                         break;
3930                 case I40E_AQ_CAP_ID_IWARP:
3931                         if (number == 1)
3932                                 p->iwarp = true;
3933                         i40e_debug(hw, I40E_DEBUG_INIT,
3934                                    "HW Capability: iWARP = %d\n", p->iwarp);
3935                         break;
3936                 case I40E_AQ_CAP_ID_LED:
3937                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3938                                 p->led[phys_id] = true;
3939                         i40e_debug(hw, I40E_DEBUG_INIT,
3940                                    "HW Capability: LED - PIN %d\n", phys_id);
3941                         break;
3942                 case I40E_AQ_CAP_ID_SDP:
3943                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3944                                 p->sdp[phys_id] = true;
3945                         i40e_debug(hw, I40E_DEBUG_INIT,
3946                                    "HW Capability: SDP - PIN %d\n", phys_id);
3947                         break;
3948                 case I40E_AQ_CAP_ID_MDIO:
3949                         if (number == 1) {
3950                                 p->mdio_port_num = phys_id;
3951                                 p->mdio_port_mode = logical_id;
3952                         }
3953                         i40e_debug(hw, I40E_DEBUG_INIT,
3954                                    "HW Capability: MDIO port number = %d\n",
3955                                    p->mdio_port_num);
3956                         i40e_debug(hw, I40E_DEBUG_INIT,
3957                                    "HW Capability: MDIO port mode = %d\n",
3958                                    p->mdio_port_mode);
3959                         break;
3960                 case I40E_AQ_CAP_ID_1588:
3961                         if (number == 1)
3962                                 p->ieee_1588 = true;
3963                         i40e_debug(hw, I40E_DEBUG_INIT,
3964                                    "HW Capability: IEEE 1588 = %d\n",
3965                                    p->ieee_1588);
3966                         break;
3967                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3968                         p->fd = true;
3969                         p->fd_filters_guaranteed = number;
3970                         p->fd_filters_best_effort = logical_id;
3971                         i40e_debug(hw, I40E_DEBUG_INIT,
3972                                    "HW Capability: Flow Director = 1\n");
3973                         i40e_debug(hw, I40E_DEBUG_INIT,
3974                                    "HW Capability: Guaranteed FD filters = %d\n",
3975                                    p->fd_filters_guaranteed);
3976                         break;
3977                 case I40E_AQ_CAP_ID_WSR_PROT:
3978                         p->wr_csr_prot = (u64)number;
3979                         p->wr_csr_prot |= (u64)logical_id << 32;
3980                         i40e_debug(hw, I40E_DEBUG_INIT,
3981                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3982                                    (p->wr_csr_prot & 0xffff));
3983                         break;
3984                 case I40E_AQ_CAP_ID_NVM_MGMT:
3985                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3986                                 p->sec_rev_disabled = true;
3987                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3988                                 p->update_disabled = true;
3989                         break;
3990                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3991                         hw->num_wol_proxy_filters = (u16)number;
3992                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3993                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3994                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3995                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3996                         else
3997                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3998                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3999                         i40e_debug(hw, I40E_DEBUG_INIT,
4000                                    "HW Capability: WOL proxy filters = %d\n",
4001                                    hw->num_wol_proxy_filters);
4002                         break;
4003                 default:
4004                         break;
4005                 }
4006         }
4007
4008         if (p->fcoe)
4009                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4010
4011         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4012         p->fcoe = false;
4013
4014         /* count the enabled ports (aka the "not disabled" ports) */
4015         hw->num_ports = 0;
4016         for (i = 0; i < 4; i++) {
4017                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4018                 u64 port_cfg = 0;
4019
4020                 /* use AQ read to get the physical register offset instead
4021                  * of the port relative offset
4022                  */
4023                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4024                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4025                         hw->num_ports++;
4026         }
4027
4028         /* OCP cards case: if a mezz is removed the ethernet port is at
4029          * disabled state in PRTGEN_CNF register. Additional NVM read is
4030          * needed in order to check if we are dealing with OCP card.
4031          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4032          * physical ports results in wrong partition id calculation and thus
4033          * not supporting WoL.
4034          */
4035         if (hw->mac.type == I40E_MAC_X722) {
4036                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4037                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4038                                                   2 * I40E_SR_OCP_CFG_WORD0,
4039                                                   sizeof(ocp_cfg_word0),
4040                                                   &ocp_cfg_word0, true, NULL);
4041                         if (status == I40E_SUCCESS &&
4042                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4043                                 hw->num_ports = 4;
4044                         i40e_release_nvm(hw);
4045                 }
4046         }
4047
4048         valid_functions = p->valid_functions;
4049         num_functions = 0;
4050         while (valid_functions) {
4051                 if (valid_functions & 1)
4052                         num_functions++;
4053                 valid_functions >>= 1;
4054         }
4055
4056         /* partition id is 1-based, and functions are evenly spread
4057          * across the ports as partitions
4058          */
4059         if (hw->num_ports != 0) {
4060                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4061                 hw->num_partitions = num_functions / hw->num_ports;
4062         }
4063
4064         /* additional HW specific goodies that might
4065          * someday be HW version specific
4066          */
4067         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4068 }
4069
4070 /**
4071  * i40e_aq_discover_capabilities
4072  * @hw: pointer to the hw struct
4073  * @buff: a virtual buffer to hold the capabilities
4074  * @buff_size: Size of the virtual buffer
4075  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4076  * @list_type_opc: capabilities type to discover - pass in the command opcode
4077  * @cmd_details: pointer to command details structure or NULL
4078  *
4079  * Get the device capabilities descriptions from the firmware
4080  **/
4081 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4082                                 void *buff, u16 buff_size, u16 *data_size,
4083                                 enum i40e_admin_queue_opc list_type_opc,
4084                                 struct i40e_asq_cmd_details *cmd_details)
4085 {
4086         struct i40e_aqc_list_capabilites *cmd;
4087         struct i40e_aq_desc desc;
4088         enum i40e_status_code status = I40E_SUCCESS;
4089
4090         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4091
4092         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4093                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4094                 status = I40E_ERR_PARAM;
4095                 goto exit;
4096         }
4097
4098         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4099
4100         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4101         if (buff_size > I40E_AQ_LARGE_BUF)
4102                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4103
4104         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4105         *data_size = LE16_TO_CPU(desc.datalen);
4106
4107         if (status)
4108                 goto exit;
4109
4110         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4111                                          list_type_opc);
4112
4113 exit:
4114         return status;
4115 }
4116
4117 /**
4118  * i40e_aq_update_nvm
4119  * @hw: pointer to the hw struct
4120  * @module_pointer: module pointer location in words from the NVM beginning
4121  * @offset: byte offset from the module beginning
4122  * @length: length of the section to be written (in bytes from the offset)
4123  * @data: command buffer (size [bytes] = length)
4124  * @last_command: tells if this is the last command in a series
4125  * @preservation_flags: Preservation mode flags
4126  * @cmd_details: pointer to command details structure or NULL
4127  *
4128  * Update the NVM using the admin queue commands
4129  **/
4130 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4131                                 u32 offset, u16 length, void *data,
4132                                 bool last_command, u8 preservation_flags,
4133                                 struct i40e_asq_cmd_details *cmd_details)
4134 {
4135         struct i40e_aq_desc desc;
4136         struct i40e_aqc_nvm_update *cmd =
4137                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4138         enum i40e_status_code status;
4139
4140         DEBUGFUNC("i40e_aq_update_nvm");
4141
4142         /* In offset the highest byte must be zeroed. */
4143         if (offset & 0xFF000000) {
4144                 status = I40E_ERR_PARAM;
4145                 goto i40e_aq_update_nvm_exit;
4146         }
4147
4148         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4149
4150         /* If this is the last command in a series, set the proper flag. */
4151         if (last_command)
4152                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4153         if (hw->mac.type == I40E_MAC_X722) {
4154                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4155                         cmd->command_flags |=
4156                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4157                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4158                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4159                         cmd->command_flags |=
4160                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4161                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4162         }
4163         cmd->module_pointer = module_pointer;
4164         cmd->offset = CPU_TO_LE32(offset);
4165         cmd->length = CPU_TO_LE16(length);
4166
4167         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4168         if (length > I40E_AQ_LARGE_BUF)
4169                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4170
4171         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4172
4173 i40e_aq_update_nvm_exit:
4174         return status;
4175 }
4176
4177 /**
4178  * i40e_aq_rearrange_nvm
4179  * @hw: pointer to the hw struct
4180  * @rearrange_nvm: defines direction of rearrangement
4181  * @cmd_details: pointer to command details structure or NULL
4182  *
4183  * Rearrange NVM structure, available only for transition FW
4184  **/
4185 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4186                                 u8 rearrange_nvm,
4187                                 struct i40e_asq_cmd_details *cmd_details)
4188 {
4189         struct i40e_aqc_nvm_update *cmd;
4190         enum i40e_status_code status;
4191         struct i40e_aq_desc desc;
4192
4193         DEBUGFUNC("i40e_aq_rearrange_nvm");
4194
4195         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4196
4197         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4198
4199         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4200                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4201
4202         if (!rearrange_nvm) {
4203                 status = I40E_ERR_PARAM;
4204                 goto i40e_aq_rearrange_nvm_exit;
4205         }
4206
4207         cmd->command_flags |= rearrange_nvm;
4208         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4209
4210 i40e_aq_rearrange_nvm_exit:
4211         return status;
4212 }
4213
4214 /**
4215  * i40e_aq_nvm_progress
4216  * @hw: pointer to the hw struct
4217  * @progress: pointer to progress returned from AQ
4218  * @cmd_details: pointer to command details structure or NULL
4219  *
4220  * Gets progress of flash rearrangement process
4221  **/
4222 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4223                                 struct i40e_asq_cmd_details *cmd_details)
4224 {
4225         enum i40e_status_code status;
4226         struct i40e_aq_desc desc;
4227
4228         DEBUGFUNC("i40e_aq_nvm_progress");
4229
4230         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4231         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4232         *progress = desc.params.raw[0];
4233         return status;
4234 }
4235
4236 /**
4237  * i40e_aq_get_lldp_mib
4238  * @hw: pointer to the hw struct
4239  * @bridge_type: type of bridge requested
4240  * @mib_type: Local, Remote or both Local and Remote MIBs
4241  * @buff: pointer to a user supplied buffer to store the MIB block
4242  * @buff_size: size of the buffer (in bytes)
4243  * @local_len : length of the returned Local LLDP MIB
4244  * @remote_len: length of the returned Remote LLDP MIB
4245  * @cmd_details: pointer to command details structure or NULL
4246  *
4247  * Requests the complete LLDP MIB (entire packet).
4248  **/
4249 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4250                                 u8 mib_type, void *buff, u16 buff_size,
4251                                 u16 *local_len, u16 *remote_len,
4252                                 struct i40e_asq_cmd_details *cmd_details)
4253 {
4254         struct i40e_aq_desc desc;
4255         struct i40e_aqc_lldp_get_mib *cmd =
4256                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4257         struct i40e_aqc_lldp_get_mib *resp =
4258                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4259         enum i40e_status_code status;
4260
4261         if (buff_size == 0 || !buff)
4262                 return I40E_ERR_PARAM;
4263
4264         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4265         /* Indirect Command */
4266         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4267
4268         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4269         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4270                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4271
4272         desc.datalen = CPU_TO_LE16(buff_size);
4273
4274         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4275         if (buff_size > I40E_AQ_LARGE_BUF)
4276                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4277
4278         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4279         if (!status) {
4280                 if (local_len != NULL)
4281                         *local_len = LE16_TO_CPU(resp->local_len);
4282                 if (remote_len != NULL)
4283                         *remote_len = LE16_TO_CPU(resp->remote_len);
4284         }
4285
4286         return status;
4287 }
4288
4289  /**
4290  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4291  * @hw: pointer to the hw struct
4292  * @mib_type: Local, Remote or both Local and Remote MIBs
4293  * @buff: pointer to a user supplied buffer to store the MIB block
4294  * @buff_size: size of the buffer (in bytes)
4295  * @cmd_details: pointer to command details structure or NULL
4296  *
4297  * Set the LLDP MIB.
4298  **/
4299 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4300                                 u8 mib_type, void *buff, u16 buff_size,
4301                                 struct i40e_asq_cmd_details *cmd_details)
4302 {
4303         struct i40e_aq_desc desc;
4304         struct i40e_aqc_lldp_set_local_mib *cmd =
4305                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4306         enum i40e_status_code status;
4307
4308         if (buff_size == 0 || !buff)
4309                 return I40E_ERR_PARAM;
4310
4311         i40e_fill_default_direct_cmd_desc(&desc,
4312                                 i40e_aqc_opc_lldp_set_local_mib);
4313         /* Indirect Command */
4314         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4315         if (buff_size > I40E_AQ_LARGE_BUF)
4316                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4317         desc.datalen = CPU_TO_LE16(buff_size);
4318
4319         cmd->type = mib_type;
4320         cmd->length = CPU_TO_LE16(buff_size);
4321         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4322         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4323
4324         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4325         return status;
4326 }
4327
4328 /**
4329  * i40e_aq_cfg_lldp_mib_change_event
4330  * @hw: pointer to the hw struct
4331  * @enable_update: Enable or Disable event posting
4332  * @cmd_details: pointer to command details structure or NULL
4333  *
4334  * Enable or Disable posting of an event on ARQ when LLDP MIB
4335  * associated with the interface changes
4336  **/
4337 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4338                                 bool enable_update,
4339                                 struct i40e_asq_cmd_details *cmd_details)
4340 {
4341         struct i40e_aq_desc desc;
4342         struct i40e_aqc_lldp_update_mib *cmd =
4343                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4344         enum i40e_status_code status;
4345
4346         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4347
4348         if (!enable_update)
4349                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4350
4351         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4352
4353         return status;
4354 }
4355
4356 /**
4357  * i40e_aq_restore_lldp
4358  * @hw: pointer to the hw struct
4359  * @setting: pointer to factory setting variable or NULL
4360  * @restore: True if factory settings should be restored
4361  * @cmd_details: pointer to command details structure or NULL
4362  *
4363  * Restore LLDP Agent factory settings if @restore set to True. In other case
4364  * only returns factory setting in AQ response.
4365  **/
4366 enum i40e_status_code
4367 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4368                      struct i40e_asq_cmd_details *cmd_details)
4369 {
4370         struct i40e_aq_desc desc;
4371         struct i40e_aqc_lldp_restore *cmd =
4372                 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4373         enum i40e_status_code status;
4374
4375         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4376                 i40e_debug(hw, I40E_DEBUG_ALL,
4377                            "Restore LLDP not supported by current FW version.\n");
4378                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4379         }
4380
4381         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4382
4383         if (restore)
4384                 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4385
4386         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4387
4388         if (setting)
4389                 *setting = cmd->command & 1;
4390
4391         return status;
4392 }
4393
4394 /**
4395  * i40e_aq_stop_lldp
4396  * @hw: pointer to the hw struct
4397  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4398  * @persist: True if stop of LLDP should be persistent across power cycles
4399  * @cmd_details: pointer to command details structure or NULL
4400  *
4401  * Stop or Shutdown the embedded LLDP Agent
4402  **/
4403 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4404                                 bool persist,
4405                                 struct i40e_asq_cmd_details *cmd_details)
4406 {
4407         struct i40e_aq_desc desc;
4408         struct i40e_aqc_lldp_stop *cmd =
4409                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4410         enum i40e_status_code status;
4411
4412         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4413
4414         if (shutdown_agent)
4415                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4416
4417         if (persist) {
4418                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4419                         cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4420                 else
4421                         i40e_debug(hw, I40E_DEBUG_ALL,
4422                                    "Persistent Stop LLDP not supported by current FW version.\n");
4423         }
4424
4425         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4426
4427         return status;
4428 }
4429
4430 /**
4431  * i40e_aq_start_lldp
4432  * @hw: pointer to the hw struct
4433  * @persist: True if start of LLDP should be persistent across power cycles
4434  * @cmd_details: pointer to command details structure or NULL
4435  *
4436  * Start the embedded LLDP Agent on all ports.
4437  **/
4438 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4439                                 bool persist,
4440                                 struct i40e_asq_cmd_details *cmd_details)
4441 {
4442         struct i40e_aq_desc desc;
4443         struct i40e_aqc_lldp_start *cmd =
4444                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4445         enum i40e_status_code status;
4446
4447         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4448
4449         cmd->command = I40E_AQ_LLDP_AGENT_START;
4450
4451         if (persist) {
4452                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4453                         cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4454                 else
4455                         i40e_debug(hw, I40E_DEBUG_ALL,
4456                                    "Persistent Start LLDP not supported by current FW version.\n");
4457         }
4458
4459         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4460
4461         return status;
4462 }
4463
4464 /**
4465  * i40e_aq_set_dcb_parameters
4466  * @hw: pointer to the hw struct
4467  * @cmd_details: pointer to command details structure or NULL
4468  * @dcb_enable: True if DCB configuration needs to be applied
4469  *
4470  **/
4471 enum i40e_status_code
4472 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4473                            struct i40e_asq_cmd_details *cmd_details)
4474 {
4475         struct i40e_aq_desc desc;
4476         struct i40e_aqc_set_dcb_parameters *cmd =
4477                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4478         enum i40e_status_code status;
4479
4480         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4481                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4482
4483         i40e_fill_default_direct_cmd_desc(&desc,
4484                                           i40e_aqc_opc_set_dcb_parameters);
4485
4486         if (dcb_enable) {
4487                 cmd->valid_flags = I40E_DCB_VALID;
4488                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4489         }
4490         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4491
4492         return status;
4493 }
4494
4495 /**
4496  * i40e_aq_get_cee_dcb_config
4497  * @hw: pointer to the hw struct
4498  * @buff: response buffer that stores CEE operational configuration
4499  * @buff_size: size of the buffer passed
4500  * @cmd_details: pointer to command details structure or NULL
4501  *
4502  * Get CEE DCBX mode operational configuration from firmware
4503  **/
4504 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4505                                 void *buff, u16 buff_size,
4506                                 struct i40e_asq_cmd_details *cmd_details)
4507 {
4508         struct i40e_aq_desc desc;
4509         enum i40e_status_code status;
4510
4511         if (buff_size == 0 || !buff)
4512                 return I40E_ERR_PARAM;
4513
4514         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4515
4516         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4517         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4518                                        cmd_details);
4519
4520         return status;
4521 }
4522
4523 /**
4524  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4525  * @hw: pointer to the hw struct
4526  * @start_agent: True if DCBx Agent needs to be Started
4527  *                              False if DCBx Agent needs to be Stopped
4528  * @cmd_details: pointer to command details structure or NULL
4529  *
4530  * Start/Stop the embedded dcbx Agent
4531  **/
4532 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4533                                 bool start_agent,
4534                                 struct i40e_asq_cmd_details *cmd_details)
4535 {
4536         struct i40e_aq_desc desc;
4537         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4538                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4539                                 &desc.params.raw;
4540         enum i40e_status_code status;
4541
4542         i40e_fill_default_direct_cmd_desc(&desc,
4543                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4544
4545         if (start_agent)
4546                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4547
4548         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4549
4550         return status;
4551 }
4552
4553 /**
4554  * i40e_aq_add_udp_tunnel
4555  * @hw: pointer to the hw struct
4556  * @udp_port: the UDP port to add in Host byte order
4557  * @protocol_index: protocol index type
4558  * @filter_index: pointer to filter index
4559  * @cmd_details: pointer to command details structure or NULL
4560  *
4561  * Note: Firmware expects the udp_port value to be in Little Endian format,
4562  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4563  * Little Endian order.
4564  **/
4565 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4566                                 u16 udp_port, u8 protocol_index,
4567                                 u8 *filter_index,
4568                                 struct i40e_asq_cmd_details *cmd_details)
4569 {
4570         struct i40e_aq_desc desc;
4571         struct i40e_aqc_add_udp_tunnel *cmd =
4572                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4573         struct i40e_aqc_del_udp_tunnel_completion *resp =
4574                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4575         enum i40e_status_code status;
4576
4577         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4578
4579         cmd->udp_port = CPU_TO_LE16(udp_port);
4580         cmd->protocol_type = protocol_index;
4581
4582         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4583
4584         if (!status && filter_index)
4585                 *filter_index = resp->index;
4586
4587         return status;
4588 }
4589
4590 /**
4591  * i40e_aq_del_udp_tunnel
4592  * @hw: pointer to the hw struct
4593  * @index: filter index
4594  * @cmd_details: pointer to command details structure or NULL
4595  **/
4596 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4597                                 struct i40e_asq_cmd_details *cmd_details)
4598 {
4599         struct i40e_aq_desc desc;
4600         struct i40e_aqc_remove_udp_tunnel *cmd =
4601                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4602         enum i40e_status_code status;
4603
4604         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4605
4606         cmd->index = index;
4607
4608         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4609
4610         return status;
4611 }
4612
4613 /**
4614  * i40e_aq_get_switch_resource_alloc (0x0204)
4615  * @hw: pointer to the hw struct
4616  * @num_entries: pointer to u8 to store the number of resource entries returned
4617  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4618  *        to store the resource information for all resource types.  Each
4619  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4620  * @count: size, in bytes, of the buffer provided
4621  * @cmd_details: pointer to command details structure or NULL
4622  *
4623  * Query the resources allocated to a function.
4624  **/
4625 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4626                         u8 *num_entries,
4627                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4628                         u16 count,
4629                         struct i40e_asq_cmd_details *cmd_details)
4630 {
4631         struct i40e_aq_desc desc;
4632         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4633                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4634         enum i40e_status_code status;
4635         u16 length = count * sizeof(*buf);
4636
4637         i40e_fill_default_direct_cmd_desc(&desc,
4638                                         i40e_aqc_opc_get_switch_resource_alloc);
4639
4640         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4641         if (length > I40E_AQ_LARGE_BUF)
4642                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4643
4644         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4645
4646         if (!status && num_entries)
4647                 *num_entries = cmd_resp->num_entries;
4648
4649         return status;
4650 }
4651
4652 /**
4653  * i40e_aq_delete_element - Delete switch element
4654  * @hw: pointer to the hw struct
4655  * @seid: the SEID to delete from the switch
4656  * @cmd_details: pointer to command details structure or NULL
4657  *
4658  * This deletes a switch element from the switch.
4659  **/
4660 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4661                                 struct i40e_asq_cmd_details *cmd_details)
4662 {
4663         struct i40e_aq_desc desc;
4664         struct i40e_aqc_switch_seid *cmd =
4665                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4666         enum i40e_status_code status;
4667
4668         if (seid == 0)
4669                 return I40E_ERR_PARAM;
4670
4671         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4672
4673         cmd->seid = CPU_TO_LE16(seid);
4674
4675         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4676
4677         return status;
4678 }
4679
4680 /**
4681  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4682  * @hw: pointer to the hw struct
4683  * @flags: component flags
4684  * @mac_seid: uplink seid (MAC SEID)
4685  * @vsi_seid: connected vsi seid
4686  * @ret_seid: seid of create pv component
4687  *
4688  * This instantiates an i40e port virtualizer with specified flags.
4689  * Depending on specified flags the port virtualizer can act as a
4690  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4691  */
4692 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4693                                        u16 mac_seid, u16 vsi_seid,
4694                                        u16 *ret_seid)
4695 {
4696         struct i40e_aq_desc desc;
4697         struct i40e_aqc_add_update_pv *cmd =
4698                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4699         struct i40e_aqc_add_update_pv_completion *resp =
4700                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4701         enum i40e_status_code status;
4702
4703         if (vsi_seid == 0)
4704                 return I40E_ERR_PARAM;
4705
4706         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4707         cmd->command_flags = CPU_TO_LE16(flags);
4708         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4709         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4710
4711         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4712         if (!status && ret_seid)
4713                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4714
4715         return status;
4716 }
4717
4718 /**
4719  * i40e_aq_add_tag - Add an S/E-tag
4720  * @hw: pointer to the hw struct
4721  * @direct_to_queue: should s-tag direct flow to a specific queue
4722  * @vsi_seid: VSI SEID to use this tag
4723  * @tag: value of the tag
4724  * @queue_num: queue number, only valid is direct_to_queue is true
4725  * @tags_used: return value, number of tags in use by this PF
4726  * @tags_free: return value, number of unallocated tags
4727  * @cmd_details: pointer to command details structure or NULL
4728  *
4729  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4730  * the number of tags allocated by the PF, and the number of unallocated
4731  * tags available.
4732  **/
4733 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4734                                 u16 vsi_seid, u16 tag, u16 queue_num,
4735                                 u16 *tags_used, u16 *tags_free,
4736                                 struct i40e_asq_cmd_details *cmd_details)
4737 {
4738         struct i40e_aq_desc desc;
4739         struct i40e_aqc_add_tag *cmd =
4740                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4741         struct i40e_aqc_add_remove_tag_completion *resp =
4742                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4743         enum i40e_status_code status;
4744
4745         if (vsi_seid == 0)
4746                 return I40E_ERR_PARAM;
4747
4748         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4749
4750         cmd->seid = CPU_TO_LE16(vsi_seid);
4751         cmd->tag = CPU_TO_LE16(tag);
4752         if (direct_to_queue) {
4753                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4754                 cmd->queue_number = CPU_TO_LE16(queue_num);
4755         }
4756
4757         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4758
4759         if (!status) {
4760                 if (tags_used != NULL)
4761                         *tags_used = LE16_TO_CPU(resp->tags_used);
4762                 if (tags_free != NULL)
4763                         *tags_free = LE16_TO_CPU(resp->tags_free);
4764         }
4765
4766         return status;
4767 }
4768
4769 /**
4770  * i40e_aq_remove_tag - Remove an S- or E-tag
4771  * @hw: pointer to the hw struct
4772  * @vsi_seid: VSI SEID this tag is associated with
4773  * @tag: value of the S-tag to delete
4774  * @tags_used: return value, number of tags in use by this PF
4775  * @tags_free: return value, number of unallocated tags
4776  * @cmd_details: pointer to command details structure or NULL
4777  *
4778  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4779  * the number of tags allocated by the PF, and the number of unallocated
4780  * tags available.
4781  **/
4782 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4783                                 u16 tag, u16 *tags_used, u16 *tags_free,
4784                                 struct i40e_asq_cmd_details *cmd_details)
4785 {
4786         struct i40e_aq_desc desc;
4787         struct i40e_aqc_remove_tag *cmd =
4788                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4789         struct i40e_aqc_add_remove_tag_completion *resp =
4790                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4791         enum i40e_status_code status;
4792
4793         if (vsi_seid == 0)
4794                 return I40E_ERR_PARAM;
4795
4796         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4797
4798         cmd->seid = CPU_TO_LE16(vsi_seid);
4799         cmd->tag = CPU_TO_LE16(tag);
4800
4801         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4802
4803         if (!status) {
4804                 if (tags_used != NULL)
4805                         *tags_used = LE16_TO_CPU(resp->tags_used);
4806                 if (tags_free != NULL)
4807                         *tags_free = LE16_TO_CPU(resp->tags_free);
4808         }
4809
4810         return status;
4811 }
4812
4813 /**
4814  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4815  * @hw: pointer to the hw struct
4816  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4817  * @etag: value of E-tag to add
4818  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4819  * @buf: address of indirect buffer
4820  * @tags_used: return value, number of E-tags in use by this port
4821  * @tags_free: return value, number of unallocated M-tags
4822  * @cmd_details: pointer to command details structure or NULL
4823  *
4824  * This associates a multicast E-tag to a port virtualizer.  It will return
4825  * the number of tags allocated by the PF, and the number of unallocated
4826  * tags available.
4827  *
4828  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4829  * num_tags_in_buf long.
4830  **/
4831 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4832                                 u16 etag, u8 num_tags_in_buf, void *buf,
4833                                 u16 *tags_used, u16 *tags_free,
4834                                 struct i40e_asq_cmd_details *cmd_details)
4835 {
4836         struct i40e_aq_desc desc;
4837         struct i40e_aqc_add_remove_mcast_etag *cmd =
4838                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4839         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4840            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4841         enum i40e_status_code status;
4842         u16 length = sizeof(u16) * num_tags_in_buf;
4843
4844         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4845                 return I40E_ERR_PARAM;
4846
4847         i40e_fill_default_direct_cmd_desc(&desc,
4848                                           i40e_aqc_opc_add_multicast_etag);
4849
4850         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4851         cmd->etag = CPU_TO_LE16(etag);
4852         cmd->num_unicast_etags = num_tags_in_buf;
4853
4854         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4855         if (length > I40E_AQ_LARGE_BUF)
4856                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4857
4858         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4859
4860         if (!status) {
4861                 if (tags_used != NULL)
4862                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4863                 if (tags_free != NULL)
4864                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4865         }
4866
4867         return status;
4868 }
4869
4870 /**
4871  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4872  * @hw: pointer to the hw struct
4873  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4874  * @etag: value of the E-tag to remove
4875  * @tags_used: return value, number of tags in use by this port
4876  * @tags_free: return value, number of unallocated tags
4877  * @cmd_details: pointer to command details structure or NULL
4878  *
4879  * This deletes an E-tag from the port virtualizer.  It will return
4880  * the number of tags allocated by the port, and the number of unallocated
4881  * tags available.
4882  **/
4883 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4884                                 u16 etag, u16 *tags_used, u16 *tags_free,
4885                                 struct i40e_asq_cmd_details *cmd_details)
4886 {
4887         struct i40e_aq_desc desc;
4888         struct i40e_aqc_add_remove_mcast_etag *cmd =
4889                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4890         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4891            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4892         enum i40e_status_code status;
4893
4894
4895         if (pv_seid == 0)
4896                 return I40E_ERR_PARAM;
4897
4898         i40e_fill_default_direct_cmd_desc(&desc,
4899                                           i40e_aqc_opc_remove_multicast_etag);
4900
4901         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4902         cmd->etag = CPU_TO_LE16(etag);
4903
4904         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4905
4906         if (!status) {
4907                 if (tags_used != NULL)
4908                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4909                 if (tags_free != NULL)
4910                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4911         }
4912
4913         return status;
4914 }
4915
4916 /**
4917  * i40e_aq_update_tag - Update an S/E-tag
4918  * @hw: pointer to the hw struct
4919  * @vsi_seid: VSI SEID using this S-tag
4920  * @old_tag: old tag value
4921  * @new_tag: new tag value
4922  * @tags_used: return value, number of tags in use by this PF
4923  * @tags_free: return value, number of unallocated tags
4924  * @cmd_details: pointer to command details structure or NULL
4925  *
4926  * This updates the value of the tag currently attached to this VSI
4927  * in the switch complex.  It will return the number of tags allocated
4928  * by the PF, and the number of unallocated tags available.
4929  **/
4930 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4931                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4932                                 u16 *tags_free,
4933                                 struct i40e_asq_cmd_details *cmd_details)
4934 {
4935         struct i40e_aq_desc desc;
4936         struct i40e_aqc_update_tag *cmd =
4937                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4938         struct i40e_aqc_update_tag_completion *resp =
4939                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4940         enum i40e_status_code status;
4941
4942         if (vsi_seid == 0)
4943                 return I40E_ERR_PARAM;
4944
4945         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4946
4947         cmd->seid = CPU_TO_LE16(vsi_seid);
4948         cmd->old_tag = CPU_TO_LE16(old_tag);
4949         cmd->new_tag = CPU_TO_LE16(new_tag);
4950
4951         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4952
4953         if (!status) {
4954                 if (tags_used != NULL)
4955                         *tags_used = LE16_TO_CPU(resp->tags_used);
4956                 if (tags_free != NULL)
4957                         *tags_free = LE16_TO_CPU(resp->tags_free);
4958         }
4959
4960         return status;
4961 }
4962
4963 /**
4964  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4965  * @hw: pointer to the hw struct
4966  * @tcmap: TC map for request/release any ignore PFC condition
4967  * @request: request or release ignore PFC condition
4968  * @tcmap_ret: return TCs for which PFC is currently ignored
4969  * @cmd_details: pointer to command details structure or NULL
4970  *
4971  * This sends out request/release to ignore PFC condition for a TC.
4972  * It will return the TCs for which PFC is currently ignored.
4973  **/
4974 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4975                                 bool request, u8 *tcmap_ret,
4976                                 struct i40e_asq_cmd_details *cmd_details)
4977 {
4978         struct i40e_aq_desc desc;
4979         struct i40e_aqc_pfc_ignore *cmd_resp =
4980                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4981         enum i40e_status_code status;
4982
4983         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4984
4985         if (request)
4986                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4987
4988         cmd_resp->tc_bitmap = tcmap;
4989
4990         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4991
4992         if (!status) {
4993                 if (tcmap_ret != NULL)
4994                         *tcmap_ret = cmd_resp->tc_bitmap;
4995         }
4996
4997         return status;
4998 }
4999
5000 /**
5001  * i40e_aq_dcb_updated - DCB Updated Command
5002  * @hw: pointer to the hw struct
5003  * @cmd_details: pointer to command details structure or NULL
5004  *
5005  * When LLDP is handled in PF this command is used by the PF
5006  * to notify EMP that a DCB setting is modified.
5007  * When LLDP is handled in EMP this command is used by the PF
5008  * to notify EMP whenever one of the following parameters get
5009  * modified:
5010  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5011  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5012  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5013  * EMP will return when the shared RPB settings have been
5014  * recomputed and modified. The retval field in the descriptor
5015  * will be set to 0 when RPB is modified.
5016  **/
5017 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5018                                 struct i40e_asq_cmd_details *cmd_details)
5019 {
5020         struct i40e_aq_desc desc;
5021         enum i40e_status_code status;
5022
5023         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5024
5025         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5026
5027         return status;
5028 }
5029
5030 /**
5031  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5032  * @hw: pointer to the hw struct
5033  * @seid: defines the SEID of the switch for which the stats are requested
5034  * @vlan_id: the VLAN ID for which the statistics are requested
5035  * @stat_index: index of the statistics counters block assigned to this VLAN
5036  * @cmd_details: pointer to command details structure or NULL
5037  *
5038  * XL710 supports 128 smonVlanStats counters.This command is used to
5039  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5040  * switch.
5041  **/
5042 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5043                                 u16 vlan_id, u16 *stat_index,
5044                                 struct i40e_asq_cmd_details *cmd_details)
5045 {
5046         struct i40e_aq_desc desc;
5047         struct i40e_aqc_add_remove_statistics *cmd_resp =
5048                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5049         enum i40e_status_code status;
5050
5051         if ((seid == 0) || (stat_index == NULL))
5052                 return I40E_ERR_PARAM;
5053
5054         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5055
5056         cmd_resp->seid = CPU_TO_LE16(seid);
5057         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5058
5059         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5060
5061         if (!status && stat_index)
5062                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5063
5064         return status;
5065 }
5066
5067 /**
5068  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5069  * @hw: pointer to the hw struct
5070  * @seid: defines the SEID of the switch for which the stats are requested
5071  * @vlan_id: the VLAN ID for which the statistics are requested
5072  * @stat_index: index of the statistics counters block assigned to this VLAN
5073  * @cmd_details: pointer to command details structure or NULL
5074  *
5075  * XL710 supports 128 smonVlanStats counters.This command is used to
5076  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5077  * switch.
5078  **/
5079 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5080                                 u16 vlan_id, u16 stat_index,
5081                                 struct i40e_asq_cmd_details *cmd_details)
5082 {
5083         struct i40e_aq_desc desc;
5084         struct i40e_aqc_add_remove_statistics *cmd =
5085                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5086         enum i40e_status_code status;
5087
5088         if (seid == 0)
5089                 return I40E_ERR_PARAM;
5090
5091         i40e_fill_default_direct_cmd_desc(&desc,
5092                                           i40e_aqc_opc_remove_statistics);
5093
5094         cmd->seid = CPU_TO_LE16(seid);
5095         cmd->vlan  = CPU_TO_LE16(vlan_id);
5096         cmd->stat_index = CPU_TO_LE16(stat_index);
5097
5098         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5099
5100         return status;
5101 }
5102
5103 /**
5104  * i40e_aq_set_port_parameters - set physical port parameters.
5105  * @hw: pointer to the hw struct
5106  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5107  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5108  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5109  * @double_vlan: if set double VLAN is enabled
5110  * @cmd_details: pointer to command details structure or NULL
5111  **/
5112 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5113                                 u16 bad_frame_vsi, bool save_bad_pac,
5114                                 bool pad_short_pac, bool double_vlan,
5115                                 struct i40e_asq_cmd_details *cmd_details)
5116 {
5117         struct i40e_aqc_set_port_parameters *cmd;
5118         enum i40e_status_code status;
5119         struct i40e_aq_desc desc;
5120         u16 command_flags = 0;
5121
5122         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5123
5124         i40e_fill_default_direct_cmd_desc(&desc,
5125                                           i40e_aqc_opc_set_port_parameters);
5126
5127         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5128         if (save_bad_pac)
5129                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5130         if (pad_short_pac)
5131                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5132         if (double_vlan)
5133                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5134         cmd->command_flags = CPU_TO_LE16(command_flags);
5135
5136         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5137
5138         return status;
5139 }
5140
5141 /**
5142  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5143  * @hw: pointer to the hw struct
5144  * @seid: seid for the physical port/switching component/vsi
5145  * @buff: Indirect buffer to hold data parameters and response
5146  * @buff_size: Indirect buffer size
5147  * @opcode: Tx scheduler AQ command opcode
5148  * @cmd_details: pointer to command details structure or NULL
5149  *
5150  * Generic command handler for Tx scheduler AQ commands
5151  **/
5152 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5153                                 void *buff, u16 buff_size,
5154                                  enum i40e_admin_queue_opc opcode,
5155                                 struct i40e_asq_cmd_details *cmd_details)
5156 {
5157         struct i40e_aq_desc desc;
5158         struct i40e_aqc_tx_sched_ind *cmd =
5159                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5160         enum i40e_status_code status;
5161         bool cmd_param_flag = false;
5162
5163         switch (opcode) {
5164         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5165         case i40e_aqc_opc_configure_vsi_tc_bw:
5166         case i40e_aqc_opc_enable_switching_comp_ets:
5167         case i40e_aqc_opc_modify_switching_comp_ets:
5168         case i40e_aqc_opc_disable_switching_comp_ets:
5169         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5170         case i40e_aqc_opc_configure_switching_comp_bw_config:
5171                 cmd_param_flag = true;
5172                 break;
5173         case i40e_aqc_opc_query_vsi_bw_config:
5174         case i40e_aqc_opc_query_vsi_ets_sla_config:
5175         case i40e_aqc_opc_query_switching_comp_ets_config:
5176         case i40e_aqc_opc_query_port_ets_config:
5177         case i40e_aqc_opc_query_switching_comp_bw_config:
5178                 cmd_param_flag = false;
5179                 break;
5180         default:
5181                 return I40E_ERR_PARAM;
5182         }
5183
5184         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5185
5186         /* Indirect command */
5187         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5188         if (cmd_param_flag)
5189                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5190         if (buff_size > I40E_AQ_LARGE_BUF)
5191                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5192
5193         desc.datalen = CPU_TO_LE16(buff_size);
5194
5195         cmd->vsi_seid = CPU_TO_LE16(seid);
5196
5197         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5198
5199         return status;
5200 }
5201
5202 /**
5203  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5204  * @hw: pointer to the hw struct
5205  * @seid: VSI seid
5206  * @credit: BW limit credits (0 = disabled)
5207  * @max_credit: Max BW limit credits
5208  * @cmd_details: pointer to command details structure or NULL
5209  **/
5210 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5211                                 u16 seid, u16 credit, u8 max_credit,
5212                                 struct i40e_asq_cmd_details *cmd_details)
5213 {
5214         struct i40e_aq_desc desc;
5215         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5216                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5217         enum i40e_status_code status;
5218
5219         i40e_fill_default_direct_cmd_desc(&desc,
5220                                           i40e_aqc_opc_configure_vsi_bw_limit);
5221
5222         cmd->vsi_seid = CPU_TO_LE16(seid);
5223         cmd->credit = CPU_TO_LE16(credit);
5224         cmd->max_credit = max_credit;
5225
5226         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5227
5228         return status;
5229 }
5230
5231 /**
5232  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5233  * @hw: pointer to the hw struct
5234  * @seid: switching component seid
5235  * @credit: BW limit credits (0 = disabled)
5236  * @max_bw: Max BW limit credits
5237  * @cmd_details: pointer to command details structure or NULL
5238  **/
5239 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5240                                 u16 seid, u16 credit, u8 max_bw,
5241                                 struct i40e_asq_cmd_details *cmd_details)
5242 {
5243         struct i40e_aq_desc desc;
5244         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5245           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5246         enum i40e_status_code status;
5247
5248         i40e_fill_default_direct_cmd_desc(&desc,
5249                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5250
5251         cmd->seid = CPU_TO_LE16(seid);
5252         cmd->credit = CPU_TO_LE16(credit);
5253         cmd->max_bw = max_bw;
5254
5255         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5256
5257         return status;
5258 }
5259
5260 /**
5261  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5262  * @hw: pointer to the hw struct
5263  * @seid: VSI seid
5264  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5265  * @cmd_details: pointer to command details structure or NULL
5266  **/
5267 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5268                         u16 seid,
5269                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5270                         struct i40e_asq_cmd_details *cmd_details)
5271 {
5272         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5273                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5274                                     cmd_details);
5275 }
5276
5277 /**
5278  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5279  * @hw: pointer to the hw struct
5280  * @seid: VSI seid
5281  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5282  * @cmd_details: pointer to command details structure or NULL
5283  **/
5284 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5285                         u16 seid,
5286                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5287                         struct i40e_asq_cmd_details *cmd_details)
5288 {
5289         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5290                                     i40e_aqc_opc_configure_vsi_tc_bw,
5291                                     cmd_details);
5292 }
5293
5294 /**
5295  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5296  * @hw: pointer to the hw struct
5297  * @seid: seid of the switching component connected to Physical Port
5298  * @ets_data: Buffer holding ETS parameters
5299  * @opcode: Tx scheduler AQ command opcode
5300  * @cmd_details: pointer to command details structure or NULL
5301  **/
5302 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5303                 u16 seid,
5304                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5305                 enum i40e_admin_queue_opc opcode,
5306                 struct i40e_asq_cmd_details *cmd_details)
5307 {
5308         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5309                                     sizeof(*ets_data), opcode, cmd_details);
5310 }
5311
5312 /**
5313  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5314  * @hw: pointer to the hw struct
5315  * @seid: seid of the switching component
5316  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5317  * @cmd_details: pointer to command details structure or NULL
5318  **/
5319 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5320         u16 seid,
5321         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5322         struct i40e_asq_cmd_details *cmd_details)
5323 {
5324         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5325                             i40e_aqc_opc_configure_switching_comp_bw_config,
5326                             cmd_details);
5327 }
5328
5329 /**
5330  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5331  * @hw: pointer to the hw struct
5332  * @seid: seid of the switching component
5333  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5334  * @cmd_details: pointer to command details structure or NULL
5335  **/
5336 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5337         struct i40e_hw *hw, u16 seid,
5338         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5339         struct i40e_asq_cmd_details *cmd_details)
5340 {
5341         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5342                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5343                             cmd_details);
5344 }
5345
5346 /**
5347  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5348  * @hw: pointer to the hw struct
5349  * @seid: seid of the VSI
5350  * @bw_data: Buffer to hold VSI BW configuration
5351  * @cmd_details: pointer to command details structure or NULL
5352  **/
5353 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5354                         u16 seid,
5355                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5356                         struct i40e_asq_cmd_details *cmd_details)
5357 {
5358         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5359                                     i40e_aqc_opc_query_vsi_bw_config,
5360                                     cmd_details);
5361 }
5362
5363 /**
5364  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5365  * @hw: pointer to the hw struct
5366  * @seid: seid of the VSI
5367  * @bw_data: Buffer to hold VSI BW configuration per TC
5368  * @cmd_details: pointer to command details structure or NULL
5369  **/
5370 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5371                         u16 seid,
5372                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5373                         struct i40e_asq_cmd_details *cmd_details)
5374 {
5375         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5376                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5377                                     cmd_details);
5378 }
5379
5380 /**
5381  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5382  * @hw: pointer to the hw struct
5383  * @seid: seid of the switching component
5384  * @bw_data: Buffer to hold switching component's per TC BW config
5385  * @cmd_details: pointer to command details structure or NULL
5386  **/
5387 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5388                 u16 seid,
5389                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5390                 struct i40e_asq_cmd_details *cmd_details)
5391 {
5392         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5393                                    i40e_aqc_opc_query_switching_comp_ets_config,
5394                                    cmd_details);
5395 }
5396
5397 /**
5398  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5399  * @hw: pointer to the hw struct
5400  * @seid: seid of the VSI or switching component connected to Physical Port
5401  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5402  * @cmd_details: pointer to command details structure or NULL
5403  **/
5404 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5405                         u16 seid,
5406                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5407                         struct i40e_asq_cmd_details *cmd_details)
5408 {
5409         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5410                                     i40e_aqc_opc_query_port_ets_config,
5411                                     cmd_details);
5412 }
5413
5414 /**
5415  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5416  * @hw: pointer to the hw struct
5417  * @seid: seid of the switching component
5418  * @bw_data: Buffer to hold switching component's BW configuration
5419  * @cmd_details: pointer to command details structure or NULL
5420  **/
5421 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5422                 u16 seid,
5423                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5424                 struct i40e_asq_cmd_details *cmd_details)
5425 {
5426         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5427                                     i40e_aqc_opc_query_switching_comp_bw_config,
5428                                     cmd_details);
5429 }
5430
5431 /**
5432  * i40e_validate_filter_settings
5433  * @hw: pointer to the hardware structure
5434  * @settings: Filter control settings
5435  *
5436  * Check and validate the filter control settings passed.
5437  * The function checks for the valid filter/context sizes being
5438  * passed for FCoE and PE.
5439  *
5440  * Returns I40E_SUCCESS if the values passed are valid and within
5441  * range else returns an error.
5442  **/
5443 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5444                                 struct i40e_filter_control_settings *settings)
5445 {
5446         u32 fcoe_cntx_size, fcoe_filt_size;
5447         u32 pe_cntx_size, pe_filt_size;
5448         u32 fcoe_fmax;
5449
5450         u32 val;
5451
5452         /* Validate FCoE settings passed */
5453         switch (settings->fcoe_filt_num) {
5454         case I40E_HASH_FILTER_SIZE_1K:
5455         case I40E_HASH_FILTER_SIZE_2K:
5456         case I40E_HASH_FILTER_SIZE_4K:
5457         case I40E_HASH_FILTER_SIZE_8K:
5458         case I40E_HASH_FILTER_SIZE_16K:
5459         case I40E_HASH_FILTER_SIZE_32K:
5460                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5461                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5462                 break;
5463         default:
5464                 return I40E_ERR_PARAM;
5465         }
5466
5467         switch (settings->fcoe_cntx_num) {
5468         case I40E_DMA_CNTX_SIZE_512:
5469         case I40E_DMA_CNTX_SIZE_1K:
5470         case I40E_DMA_CNTX_SIZE_2K:
5471         case I40E_DMA_CNTX_SIZE_4K:
5472                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5473                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5474                 break;
5475         default:
5476                 return I40E_ERR_PARAM;
5477         }
5478
5479         /* Validate PE settings passed */
5480         switch (settings->pe_filt_num) {
5481         case I40E_HASH_FILTER_SIZE_1K:
5482         case I40E_HASH_FILTER_SIZE_2K:
5483         case I40E_HASH_FILTER_SIZE_4K:
5484         case I40E_HASH_FILTER_SIZE_8K:
5485         case I40E_HASH_FILTER_SIZE_16K:
5486         case I40E_HASH_FILTER_SIZE_32K:
5487         case I40E_HASH_FILTER_SIZE_64K:
5488         case I40E_HASH_FILTER_SIZE_128K:
5489         case I40E_HASH_FILTER_SIZE_256K:
5490         case I40E_HASH_FILTER_SIZE_512K:
5491         case I40E_HASH_FILTER_SIZE_1M:
5492                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5493                 pe_filt_size <<= (u32)settings->pe_filt_num;
5494                 break;
5495         default:
5496                 return I40E_ERR_PARAM;
5497         }
5498
5499         switch (settings->pe_cntx_num) {
5500         case I40E_DMA_CNTX_SIZE_512:
5501         case I40E_DMA_CNTX_SIZE_1K:
5502         case I40E_DMA_CNTX_SIZE_2K:
5503         case I40E_DMA_CNTX_SIZE_4K:
5504         case I40E_DMA_CNTX_SIZE_8K:
5505         case I40E_DMA_CNTX_SIZE_16K:
5506         case I40E_DMA_CNTX_SIZE_32K:
5507         case I40E_DMA_CNTX_SIZE_64K:
5508         case I40E_DMA_CNTX_SIZE_128K:
5509         case I40E_DMA_CNTX_SIZE_256K:
5510                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5511                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5512                 break;
5513         default:
5514                 return I40E_ERR_PARAM;
5515         }
5516
5517         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5518         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5519         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5520                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5521         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5522                 return I40E_ERR_INVALID_SIZE;
5523
5524         return I40E_SUCCESS;
5525 }
5526
5527 /**
5528  * i40e_set_filter_control
5529  * @hw: pointer to the hardware structure
5530  * @settings: Filter control settings
5531  *
5532  * Set the Queue Filters for PE/FCoE and enable filters required
5533  * for a single PF. It is expected that these settings are programmed
5534  * at the driver initialization time.
5535  **/
5536 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5537                                 struct i40e_filter_control_settings *settings)
5538 {
5539         enum i40e_status_code ret = I40E_SUCCESS;
5540         u32 hash_lut_size = 0;
5541         u32 val;
5542
5543         if (!settings)
5544                 return I40E_ERR_PARAM;
5545
5546         /* Validate the input settings */
5547         ret = i40e_validate_filter_settings(hw, settings);
5548         if (ret)
5549                 return ret;
5550
5551         /* Read the PF Queue Filter control register */
5552         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5553
5554         /* Program required PE hash buckets for the PF */
5555         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5556         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5557                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5558         /* Program required PE contexts for the PF */
5559         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5560         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5561                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5562
5563         /* Program required FCoE hash buckets for the PF */
5564         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5565         val |= ((u32)settings->fcoe_filt_num <<
5566                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5567                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5568         /* Program required FCoE DDP contexts for the PF */
5569         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5570         val |= ((u32)settings->fcoe_cntx_num <<
5571                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5572                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5573
5574         /* Program Hash LUT size for the PF */
5575         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5576         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5577                 hash_lut_size = 1;
5578         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5579                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5580
5581         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5582         if (settings->enable_fdir)
5583                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5584         if (settings->enable_ethtype)
5585                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5586         if (settings->enable_macvlan)
5587                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5588
5589         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5590
5591         return I40E_SUCCESS;
5592 }
5593
5594 /**
5595  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5596  * @hw: pointer to the hw struct
5597  * @mac_addr: MAC address to use in the filter
5598  * @ethtype: Ethertype to use in the filter
5599  * @flags: Flags that needs to be applied to the filter
5600  * @vsi_seid: seid of the control VSI
5601  * @queue: VSI queue number to send the packet to
5602  * @is_add: Add control packet filter if True else remove
5603  * @stats: Structure to hold information on control filter counts
5604  * @cmd_details: pointer to command details structure or NULL
5605  *
5606  * This command will Add or Remove control packet filter for a control VSI.
5607  * In return it will update the total number of perfect filter count in
5608  * the stats member.
5609  **/
5610 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5611                                 u8 *mac_addr, u16 ethtype, u16 flags,
5612                                 u16 vsi_seid, u16 queue, bool is_add,
5613                                 struct i40e_control_filter_stats *stats,
5614                                 struct i40e_asq_cmd_details *cmd_details)
5615 {
5616         struct i40e_aq_desc desc;
5617         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5618                 (struct i40e_aqc_add_remove_control_packet_filter *)
5619                 &desc.params.raw;
5620         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5621                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5622                 &desc.params.raw;
5623         enum i40e_status_code status;
5624
5625         if (vsi_seid == 0)
5626                 return I40E_ERR_PARAM;
5627
5628         if (is_add) {
5629                 i40e_fill_default_direct_cmd_desc(&desc,
5630                                 i40e_aqc_opc_add_control_packet_filter);
5631                 cmd->queue = CPU_TO_LE16(queue);
5632         } else {
5633                 i40e_fill_default_direct_cmd_desc(&desc,
5634                                 i40e_aqc_opc_remove_control_packet_filter);
5635         }
5636
5637         if (mac_addr)
5638                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5639                             I40E_NONDMA_TO_NONDMA);
5640
5641         cmd->etype = CPU_TO_LE16(ethtype);
5642         cmd->flags = CPU_TO_LE16(flags);
5643         cmd->seid = CPU_TO_LE16(vsi_seid);
5644
5645         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5646
5647         if (!status && stats) {
5648                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5649                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5650                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5651                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5652         }
5653
5654         return status;
5655 }
5656
5657 /**
5658  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5659  * @hw: pointer to the hw struct
5660  * @seid: VSI seid to add ethertype filter from
5661  **/
5662 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5663                                                     u16 seid)
5664 {
5665 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5666         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5667                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5668                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5669         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5670         enum i40e_status_code status;
5671
5672         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5673                                                        seid, 0, true, NULL,
5674                                                        NULL);
5675         if (status)
5676                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5677 }
5678
5679 /**
5680  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5681  * @filters: list of cloud filters
5682  * @filter_count: length of list
5683  *
5684  * There's an issue in the device where the Geneve VNI layout needs
5685  * to be shifted 1 byte over from the VxLAN VNI
5686  **/
5687 STATIC void i40e_fix_up_geneve_vni(
5688         struct i40e_aqc_cloud_filters_element_data *filters,
5689         u8 filter_count)
5690 {
5691         struct i40e_aqc_cloud_filters_element_data *f = filters;
5692         int i;
5693
5694         for (i = 0; i < filter_count; i++) {
5695                 u16 tnl_type;
5696                 u32 ti;
5697
5698                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5699                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5700                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5701                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5702                         ti = LE32_TO_CPU(f[i].tenant_id);
5703                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5704                 }
5705         }
5706 }
5707
5708 /**
5709  * i40e_aq_add_cloud_filters
5710  * @hw: pointer to the hardware structure
5711  * @seid: VSI seid to add cloud filters from
5712  * @filters: Buffer which contains the filters to be added
5713  * @filter_count: number of filters contained in the buffer
5714  *
5715  * Set the cloud filters for a given VSI.  The contents of the
5716  * i40e_aqc_cloud_filters_element_data are filled
5717  * in by the caller of the function.
5718  *
5719  **/
5720 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5721         u16 seid,
5722         struct i40e_aqc_cloud_filters_element_data *filters,
5723         u8 filter_count)
5724 {
5725         struct i40e_aq_desc desc;
5726         struct i40e_aqc_add_remove_cloud_filters *cmd =
5727         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5728         enum i40e_status_code status;
5729         u16 buff_len;
5730
5731         i40e_fill_default_direct_cmd_desc(&desc,
5732                                           i40e_aqc_opc_add_cloud_filters);
5733
5734         buff_len = filter_count * sizeof(*filters);
5735         desc.datalen = CPU_TO_LE16(buff_len);
5736         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5737         cmd->num_filters = filter_count;
5738         cmd->seid = CPU_TO_LE16(seid);
5739
5740         i40e_fix_up_geneve_vni(filters, filter_count);
5741
5742         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5743
5744         return status;
5745 }
5746
5747 /**
5748  * i40e_aq_add_cloud_filters_bb
5749  * @hw: pointer to the hardware structure
5750  * @seid: VSI seid to add cloud filters from
5751  * @filters: Buffer which contains the filters in big buffer to be added
5752  * @filter_count: number of filters contained in the buffer
5753  *
5754  * Set the cloud filters for a given VSI.  The contents of the
5755  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5756  * the function.
5757  *
5758  **/
5759 enum i40e_status_code
5760 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5761                              struct i40e_aqc_cloud_filters_element_bb *filters,
5762                              u8 filter_count)
5763 {
5764         struct i40e_aq_desc desc;
5765         struct i40e_aqc_add_remove_cloud_filters *cmd =
5766         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5767         enum i40e_status_code status;
5768         u16 buff_len;
5769         int i;
5770
5771         i40e_fill_default_direct_cmd_desc(&desc,
5772                                           i40e_aqc_opc_add_cloud_filters);
5773
5774         buff_len = filter_count * sizeof(*filters);
5775         desc.datalen = CPU_TO_LE16(buff_len);
5776         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5777         cmd->num_filters = filter_count;
5778         cmd->seid = CPU_TO_LE16(seid);
5779         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5780
5781         for (i = 0; i < filter_count; i++) {
5782                 u16 tnl_type;
5783                 u32 ti;
5784
5785                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5786                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5787                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5788
5789                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5790                  * one more byte further than normally used for Tenant ID in
5791                  * other tunnel types.
5792                  */
5793                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5794                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5795                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5796                 }
5797         }
5798
5799         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5800
5801         return status;
5802 }
5803
5804 /**
5805  * i40e_aq_rem_cloud_filters
5806  * @hw: pointer to the hardware structure
5807  * @seid: VSI seid to remove cloud filters from
5808  * @filters: Buffer which contains the filters to be removed
5809  * @filter_count: number of filters contained in the buffer
5810  *
5811  * Remove the cloud filters for a given VSI.  The contents of the
5812  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5813  * of the function.
5814  *
5815  **/
5816 enum i40e_status_code
5817 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5818                           struct i40e_aqc_cloud_filters_element_data *filters,
5819                           u8 filter_count)
5820 {
5821         struct i40e_aq_desc desc;
5822         struct i40e_aqc_add_remove_cloud_filters *cmd =
5823         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5824         enum i40e_status_code status;
5825         u16 buff_len;
5826
5827         i40e_fill_default_direct_cmd_desc(&desc,
5828                                           i40e_aqc_opc_remove_cloud_filters);
5829
5830         buff_len = filter_count * sizeof(*filters);
5831         desc.datalen = CPU_TO_LE16(buff_len);
5832         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5833         cmd->num_filters = filter_count;
5834         cmd->seid = CPU_TO_LE16(seid);
5835
5836         i40e_fix_up_geneve_vni(filters, filter_count);
5837
5838         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5839
5840         return status;
5841 }
5842
5843 /**
5844  * i40e_aq_rem_cloud_filters_bb
5845  * @hw: pointer to the hardware structure
5846  * @seid: VSI seid to remove cloud filters from
5847  * @filters: Buffer which contains the filters in big buffer to be removed
5848  * @filter_count: number of filters contained in the buffer
5849  *
5850  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5851  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5852  * function.
5853  *
5854  **/
5855 enum i40e_status_code
5856 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5857                              struct i40e_aqc_cloud_filters_element_bb *filters,
5858                              u8 filter_count)
5859 {
5860         struct i40e_aq_desc desc;
5861         struct i40e_aqc_add_remove_cloud_filters *cmd =
5862         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5863         enum i40e_status_code status;
5864         u16 buff_len;
5865         int i;
5866
5867         i40e_fill_default_direct_cmd_desc(&desc,
5868                                           i40e_aqc_opc_remove_cloud_filters);
5869
5870         buff_len = filter_count * sizeof(*filters);
5871         desc.datalen = CPU_TO_LE16(buff_len);
5872         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5873         cmd->num_filters = filter_count;
5874         cmd->seid = CPU_TO_LE16(seid);
5875         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5876
5877         for (i = 0; i < filter_count; i++) {
5878                 u16 tnl_type;
5879                 u32 ti;
5880
5881                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5882                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5883                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5884
5885                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5886                  * one more byte further than normally used for Tenant ID in
5887                  * other tunnel types.
5888                  */
5889                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5890                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5891                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5892                 }
5893         }
5894
5895         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5896
5897         return status;
5898 }
5899
5900 /**
5901  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5902  * @hw: pointer to the hw struct
5903  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5904  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5905  *
5906  **/
5907 enum
5908 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5909         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5910         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5911 {
5912         struct i40e_aq_desc desc;
5913         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5914                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5915         enum i40e_status_code status = I40E_SUCCESS;
5916         int i = 0;
5917
5918         /* X722 doesn't support this command */
5919         if (hw->mac.type == I40E_MAC_X722)
5920                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5921
5922         /* need FW version greater than 6.00 */
5923         if (hw->aq.fw_maj_ver < 6)
5924                 return I40E_NOT_SUPPORTED;
5925
5926         i40e_fill_default_direct_cmd_desc(&desc,
5927                                           i40e_aqc_opc_replace_cloud_filters);
5928
5929         desc.datalen = CPU_TO_LE16(32);
5930         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5931         cmd->old_filter_type = filters->old_filter_type;
5932         cmd->new_filter_type = filters->new_filter_type;
5933         cmd->valid_flags = filters->valid_flags;
5934         cmd->tr_bit = filters->tr_bit;
5935         cmd->tr_bit2 = filters->tr_bit2;
5936
5937         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5938                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5939
5940         /* for get cloud filters command */
5941         for (i = 0; i < 32; i += 4) {
5942                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5943                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5944                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5945                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5946         }
5947
5948         return status;
5949 }
5950
5951
5952 /**
5953  * i40e_aq_alternate_write
5954  * @hw: pointer to the hardware structure
5955  * @reg_addr0: address of first dword to be read
5956  * @reg_val0: value to be written under 'reg_addr0'
5957  * @reg_addr1: address of second dword to be read
5958  * @reg_val1: value to be written under 'reg_addr1'
5959  *
5960  * Write one or two dwords to alternate structure. Fields are indicated
5961  * by 'reg_addr0' and 'reg_addr1' register numbers.
5962  *
5963  **/
5964 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5965                                 u32 reg_addr0, u32 reg_val0,
5966                                 u32 reg_addr1, u32 reg_val1)
5967 {
5968         struct i40e_aq_desc desc;
5969         struct i40e_aqc_alternate_write *cmd_resp =
5970                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5971         enum i40e_status_code status;
5972
5973         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5974         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5975         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5976         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5977         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5978
5979         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5980
5981         return status;
5982 }
5983
5984 /**
5985  * i40e_aq_alternate_write_indirect
5986  * @hw: pointer to the hardware structure
5987  * @addr: address of a first register to be modified
5988  * @dw_count: number of alternate structure fields to write
5989  * @buffer: pointer to the command buffer
5990  *
5991  * Write 'dw_count' dwords from 'buffer' to alternate structure
5992  * starting at 'addr'.
5993  *
5994  **/
5995 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5996                                 u32 addr, u32 dw_count, void *buffer)
5997 {
5998         struct i40e_aq_desc desc;
5999         struct i40e_aqc_alternate_ind_write *cmd_resp =
6000                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6001         enum i40e_status_code status;
6002
6003         if (buffer == NULL)
6004                 return I40E_ERR_PARAM;
6005
6006         /* Indirect command */
6007         i40e_fill_default_direct_cmd_desc(&desc,
6008                                          i40e_aqc_opc_alternate_write_indirect);
6009
6010         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6011         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6012         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6013                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6014
6015         cmd_resp->address = CPU_TO_LE32(addr);
6016         cmd_resp->length = CPU_TO_LE32(dw_count);
6017
6018         status = i40e_asq_send_command(hw, &desc, buffer,
6019                                        I40E_LO_DWORD(4*dw_count), NULL);
6020
6021         return status;
6022 }
6023
6024 /**
6025  * i40e_aq_alternate_read
6026  * @hw: pointer to the hardware structure
6027  * @reg_addr0: address of first dword to be read
6028  * @reg_val0: pointer for data read from 'reg_addr0'
6029  * @reg_addr1: address of second dword to be read
6030  * @reg_val1: pointer for data read from 'reg_addr1'
6031  *
6032  * Read one or two dwords from alternate structure. Fields are indicated
6033  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6034  * is not passed then only register at 'reg_addr0' is read.
6035  *
6036  **/
6037 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6038                                 u32 reg_addr0, u32 *reg_val0,
6039                                 u32 reg_addr1, u32 *reg_val1)
6040 {
6041         struct i40e_aq_desc desc;
6042         struct i40e_aqc_alternate_write *cmd_resp =
6043                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6044         enum i40e_status_code status;
6045
6046         if (reg_val0 == NULL)
6047                 return I40E_ERR_PARAM;
6048
6049         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6050         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6051         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6052
6053         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6054
6055         if (status == I40E_SUCCESS) {
6056                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6057
6058                 if (reg_val1 != NULL)
6059                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6060         }
6061
6062         return status;
6063 }
6064
6065 /**
6066  * i40e_aq_alternate_read_indirect
6067  * @hw: pointer to the hardware structure
6068  * @addr: address of the alternate structure field
6069  * @dw_count: number of alternate structure fields to read
6070  * @buffer: pointer to the command buffer
6071  *
6072  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6073  * place them in 'buffer'. The buffer should be allocated by caller.
6074  *
6075  **/
6076 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6077                                 u32 addr, u32 dw_count, void *buffer)
6078 {
6079         struct i40e_aq_desc desc;
6080         struct i40e_aqc_alternate_ind_write *cmd_resp =
6081                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6082         enum i40e_status_code status;
6083
6084         if (buffer == NULL)
6085                 return I40E_ERR_PARAM;
6086
6087         /* Indirect command */
6088         i40e_fill_default_direct_cmd_desc(&desc,
6089                 i40e_aqc_opc_alternate_read_indirect);
6090
6091         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6092         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6093         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6094                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6095
6096         cmd_resp->address = CPU_TO_LE32(addr);
6097         cmd_resp->length = CPU_TO_LE32(dw_count);
6098
6099         status = i40e_asq_send_command(hw, &desc, buffer,
6100                                        I40E_LO_DWORD(4*dw_count), NULL);
6101
6102         return status;
6103 }
6104
6105 /**
6106  *  i40e_aq_alternate_clear
6107  *  @hw: pointer to the HW structure.
6108  *
6109  *  Clear the alternate structures of the port from which the function
6110  *  is called.
6111  *
6112  **/
6113 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6114 {
6115         struct i40e_aq_desc desc;
6116         enum i40e_status_code status;
6117
6118         i40e_fill_default_direct_cmd_desc(&desc,
6119                                           i40e_aqc_opc_alternate_clear_port);
6120
6121         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6122
6123         return status;
6124 }
6125
6126 /**
6127  *  i40e_aq_alternate_write_done
6128  *  @hw: pointer to the HW structure.
6129  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6130  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6131  *
6132  *  Indicates to the FW that alternate structures have been changed.
6133  *
6134  **/
6135 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6136                 u8 bios_mode, bool *reset_needed)
6137 {
6138         struct i40e_aq_desc desc;
6139         struct i40e_aqc_alternate_write_done *cmd =
6140                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6141         enum i40e_status_code status;
6142
6143         if (reset_needed == NULL)
6144                 return I40E_ERR_PARAM;
6145
6146         i40e_fill_default_direct_cmd_desc(&desc,
6147                                           i40e_aqc_opc_alternate_write_done);
6148
6149         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6150
6151         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6152         if (!status && reset_needed)
6153                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6154                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6155
6156         return status;
6157 }
6158
6159 /**
6160  *  i40e_aq_set_oem_mode
6161  *  @hw: pointer to the HW structure.
6162  *  @oem_mode: the OEM mode to be used
6163  *
6164  *  Sets the device to a specific operating mode. Currently the only supported
6165  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6166  *
6167  **/
6168 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6169                 u8 oem_mode)
6170 {
6171         struct i40e_aq_desc desc;
6172         struct i40e_aqc_alternate_write_done *cmd =
6173                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6174         enum i40e_status_code status;
6175
6176         i40e_fill_default_direct_cmd_desc(&desc,
6177                                           i40e_aqc_opc_alternate_set_mode);
6178
6179         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6180
6181         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6182
6183         return status;
6184 }
6185
6186 /**
6187  * i40e_aq_resume_port_tx
6188  * @hw: pointer to the hardware structure
6189  * @cmd_details: pointer to command details structure or NULL
6190  *
6191  * Resume port's Tx traffic
6192  **/
6193 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6194                                 struct i40e_asq_cmd_details *cmd_details)
6195 {
6196         struct i40e_aq_desc desc;
6197         enum i40e_status_code status;
6198
6199         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6200
6201         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6202
6203         return status;
6204 }
6205
6206 /**
6207  * i40e_set_pci_config_data - store PCI bus info
6208  * @hw: pointer to hardware structure
6209  * @link_status: the link status word from PCI config space
6210  *
6211  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6212  **/
6213 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6214 {
6215         hw->bus.type = i40e_bus_type_pci_express;
6216
6217         switch (link_status & I40E_PCI_LINK_WIDTH) {
6218         case I40E_PCI_LINK_WIDTH_1:
6219                 hw->bus.width = i40e_bus_width_pcie_x1;
6220                 break;
6221         case I40E_PCI_LINK_WIDTH_2:
6222                 hw->bus.width = i40e_bus_width_pcie_x2;
6223                 break;
6224         case I40E_PCI_LINK_WIDTH_4:
6225                 hw->bus.width = i40e_bus_width_pcie_x4;
6226                 break;
6227         case I40E_PCI_LINK_WIDTH_8:
6228                 hw->bus.width = i40e_bus_width_pcie_x8;
6229                 break;
6230         default:
6231                 hw->bus.width = i40e_bus_width_unknown;
6232                 break;
6233         }
6234
6235         switch (link_status & I40E_PCI_LINK_SPEED) {
6236         case I40E_PCI_LINK_SPEED_2500:
6237                 hw->bus.speed = i40e_bus_speed_2500;
6238                 break;
6239         case I40E_PCI_LINK_SPEED_5000:
6240                 hw->bus.speed = i40e_bus_speed_5000;
6241                 break;
6242         case I40E_PCI_LINK_SPEED_8000:
6243                 hw->bus.speed = i40e_bus_speed_8000;
6244                 break;
6245         default:
6246                 hw->bus.speed = i40e_bus_speed_unknown;
6247                 break;
6248         }
6249 }
6250
6251 /**
6252  * i40e_aq_debug_dump
6253  * @hw: pointer to the hardware structure
6254  * @cluster_id: specific cluster to dump
6255  * @table_id: table id within cluster
6256  * @start_index: index of line in the block to read
6257  * @buff_size: dump buffer size
6258  * @buff: dump buffer
6259  * @ret_buff_size: actual buffer size returned
6260  * @ret_next_table: next block to read
6261  * @ret_next_index: next index to read
6262  * @cmd_details: pointer to command details structure or NULL
6263  *
6264  * Dump internal FW/HW data for debug purposes.
6265  *
6266  **/
6267 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6268                                 u8 table_id, u32 start_index, u16 buff_size,
6269                                 void *buff, u16 *ret_buff_size,
6270                                 u8 *ret_next_table, u32 *ret_next_index,
6271                                 struct i40e_asq_cmd_details *cmd_details)
6272 {
6273         struct i40e_aq_desc desc;
6274         struct i40e_aqc_debug_dump_internals *cmd =
6275                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6276         struct i40e_aqc_debug_dump_internals *resp =
6277                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6278         enum i40e_status_code status;
6279
6280         if (buff_size == 0 || !buff)
6281                 return I40E_ERR_PARAM;
6282
6283         i40e_fill_default_direct_cmd_desc(&desc,
6284                                           i40e_aqc_opc_debug_dump_internals);
6285         /* Indirect Command */
6286         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6287         if (buff_size > I40E_AQ_LARGE_BUF)
6288                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6289
6290         cmd->cluster_id = cluster_id;
6291         cmd->table_id = table_id;
6292         cmd->idx = CPU_TO_LE32(start_index);
6293
6294         desc.datalen = CPU_TO_LE16(buff_size);
6295
6296         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6297         if (!status) {
6298                 if (ret_buff_size != NULL)
6299                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6300                 if (ret_next_table != NULL)
6301                         *ret_next_table = resp->table_id;
6302                 if (ret_next_index != NULL)
6303                         *ret_next_index = LE32_TO_CPU(resp->idx);
6304         }
6305
6306         return status;
6307 }
6308
6309
6310 /**
6311  * i40e_enable_eee
6312  * @hw: pointer to the hardware structure
6313  * @enable: state of Energy Efficient Ethernet mode to be set
6314  *
6315  * Enables or disables Energy Efficient Ethernet (EEE) mode
6316  * accordingly to @enable parameter.
6317  **/
6318 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6319 {
6320         struct i40e_aq_get_phy_abilities_resp abilities;
6321         struct i40e_aq_set_phy_config config;
6322         enum i40e_status_code status;
6323         __le16 eee_capability;
6324
6325         /* Get initial PHY capabilities */
6326         status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6327                                               NULL);
6328         if (status)
6329                 goto err;
6330
6331         /* Check whether NIC configuration is compatible with Energy Efficient
6332          * Ethernet (EEE) mode.
6333          */
6334         if (abilities.eee_capability == 0) {
6335                 status = I40E_ERR_CONFIG;
6336                 goto err;
6337         }
6338
6339         /* Cache initial EEE capability */
6340         eee_capability = abilities.eee_capability;
6341
6342         /* Get current configuration */
6343         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6344                                               NULL);
6345         if (status)
6346                 goto err;
6347
6348         /* Cache current configuration */
6349         config.phy_type = abilities.phy_type;
6350         config.link_speed = abilities.link_speed;
6351         config.abilities = abilities.abilities |
6352                            I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6353         config.eeer = abilities.eeer_val;
6354         config.low_power_ctrl = abilities.d3_lpan;
6355         config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6356                             I40E_AQ_PHY_FEC_CONFIG_MASK;
6357
6358         /* Set desired EEE state */
6359         if (enable) {
6360                 config.eee_capability = eee_capability;
6361                 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6362         } else {
6363                 config.eee_capability = 0;
6364                 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6365         }
6366
6367         /* Save modified config */
6368         status = i40e_aq_set_phy_config(hw, &config, NULL);
6369 err:
6370         return status;
6371 }
6372
6373 /**
6374  * i40e_read_bw_from_alt_ram
6375  * @hw: pointer to the hardware structure
6376  * @max_bw: pointer for max_bw read
6377  * @min_bw: pointer for min_bw read
6378  * @min_valid: pointer for bool that is true if min_bw is a valid value
6379  * @max_valid: pointer for bool that is true if max_bw is a valid value
6380  *
6381  * Read bw from the alternate ram for the given pf
6382  **/
6383 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6384                                         u32 *max_bw, u32 *min_bw,
6385                                         bool *min_valid, bool *max_valid)
6386 {
6387         enum i40e_status_code status;
6388         u32 max_bw_addr, min_bw_addr;
6389
6390         /* Calculate the address of the min/max bw registers */
6391         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6392                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6393                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6394         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6395                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6396                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6397
6398         /* Read the bandwidths from alt ram */
6399         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6400                                         min_bw_addr, min_bw);
6401
6402         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6403                 *min_valid = true;
6404         else
6405                 *min_valid = false;
6406
6407         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6408                 *max_valid = true;
6409         else
6410                 *max_valid = false;
6411
6412         return status;
6413 }
6414
6415 /**
6416  * i40e_aq_configure_partition_bw
6417  * @hw: pointer to the hardware structure
6418  * @bw_data: Buffer holding valid pfs and bw limits
6419  * @cmd_details: pointer to command details
6420  *
6421  * Configure partitions guaranteed/max bw
6422  **/
6423 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6424                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6425                         struct i40e_asq_cmd_details *cmd_details)
6426 {
6427         enum i40e_status_code status;
6428         struct i40e_aq_desc desc;
6429         u16 bwd_size = sizeof(*bw_data);
6430
6431         i40e_fill_default_direct_cmd_desc(&desc,
6432                                 i40e_aqc_opc_configure_partition_bw);
6433
6434         /* Indirect command */
6435         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6436         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6437
6438         desc.datalen = CPU_TO_LE16(bwd_size);
6439
6440         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6441
6442         return status;
6443 }
6444
6445 /**
6446  * i40e_read_phy_register_clause22
6447  * @hw: pointer to the HW structure
6448  * @reg: register address in the page
6449  * @phy_addr: PHY address on MDIO interface
6450  * @value: PHY register value
6451  *
6452  * Reads specified PHY register value
6453  **/
6454 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6455                                         u16 reg, u8 phy_addr, u16 *value)
6456 {
6457         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6458         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6459         u32 command = 0;
6460         u16 retry = 1000;
6461
6462         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6463                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6464                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6465                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6466                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6467         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6468         do {
6469                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6470                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6471                         status = I40E_SUCCESS;
6472                         break;
6473                 }
6474                 i40e_usec_delay(10);
6475                 retry--;
6476         } while (retry);
6477
6478         if (status) {
6479                 i40e_debug(hw, I40E_DEBUG_PHY,
6480                            "PHY: Can't write command to external PHY.\n");
6481         } else {
6482                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6483                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6484                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6485         }
6486
6487         return status;
6488 }
6489
6490 /**
6491  * i40e_write_phy_register_clause22
6492  * @hw: pointer to the HW structure
6493  * @reg: register address in the page
6494  * @phy_addr: PHY address on MDIO interface
6495  * @value: PHY register value
6496  *
6497  * Writes specified PHY register value
6498  **/
6499 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6500                                         u16 reg, u8 phy_addr, u16 value)
6501 {
6502         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6503         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6504         u32 command  = 0;
6505         u16 retry = 1000;
6506
6507         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6508         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6509
6510         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6511                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6512                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6513                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6514                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6515
6516         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6517         do {
6518                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6519                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6520                         status = I40E_SUCCESS;
6521                         break;
6522                 }
6523                 i40e_usec_delay(10);
6524                 retry--;
6525         } while (retry);
6526
6527         return status;
6528 }
6529
6530 /**
6531  * i40e_read_phy_register_clause45
6532  * @hw: pointer to the HW structure
6533  * @page: registers page number
6534  * @reg: register address in the page
6535  * @phy_addr: PHY address on MDIO interface
6536  * @value: PHY register value
6537  *
6538  * Reads specified PHY register value
6539  **/
6540 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6541                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6542 {
6543         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6544         u32 command  = 0;
6545         u16 retry = 1000;
6546         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6547
6548         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6549                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6550                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6551                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6552                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6553                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6554                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6555         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6556         do {
6557                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6558                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6559                         status = I40E_SUCCESS;
6560                         break;
6561                 }
6562                 i40e_usec_delay(10);
6563                 retry--;
6564         } while (retry);
6565
6566         if (status) {
6567                 i40e_debug(hw, I40E_DEBUG_PHY,
6568                            "PHY: Can't write command to external PHY.\n");
6569                 goto phy_read_end;
6570         }
6571
6572         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6573                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6574                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6575                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6576                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6577                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6578         status = I40E_ERR_TIMEOUT;
6579         retry = 1000;
6580         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6581         do {
6582                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6583                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6584                         status = I40E_SUCCESS;
6585                         break;
6586                 }
6587                 i40e_usec_delay(10);
6588                 retry--;
6589         } while (retry);
6590
6591         if (!status) {
6592                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6593                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6594                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6595         } else {
6596                 i40e_debug(hw, I40E_DEBUG_PHY,
6597                            "PHY: Can't read register value from external PHY.\n");
6598         }
6599
6600 phy_read_end:
6601         return status;
6602 }
6603
6604 /**
6605  * i40e_write_phy_register_clause45
6606  * @hw: pointer to the HW structure
6607  * @page: registers page number
6608  * @reg: register address in the page
6609  * @phy_addr: PHY address on MDIO interface
6610  * @value: PHY register value
6611  *
6612  * Writes value to specified PHY register
6613  **/
6614 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6615                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6616 {
6617         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6618         u32 command  = 0;
6619         u16 retry = 1000;
6620         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6621
6622         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6623                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6624                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6625                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6626                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6627                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6628                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6629         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6630         do {
6631                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6632                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6633                         status = I40E_SUCCESS;
6634                         break;
6635                 }
6636                 i40e_usec_delay(10);
6637                 retry--;
6638         } while (retry);
6639         if (status) {
6640                 i40e_debug(hw, I40E_DEBUG_PHY,
6641                            "PHY: Can't write command to external PHY.\n");
6642                 goto phy_write_end;
6643         }
6644
6645         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6646         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6647
6648         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6649                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6650                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6651                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6652                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6653                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6654         status = I40E_ERR_TIMEOUT;
6655         retry = 1000;
6656         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6657         do {
6658                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6659                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6660                         status = I40E_SUCCESS;
6661                         break;
6662                 }
6663                 i40e_usec_delay(10);
6664                 retry--;
6665         } while (retry);
6666
6667 phy_write_end:
6668         return status;
6669 }
6670
6671 /**
6672  * i40e_write_phy_register
6673  * @hw: pointer to the HW structure
6674  * @page: registers page number
6675  * @reg: register address in the page
6676  * @phy_addr: PHY address on MDIO interface
6677  * @value: PHY register value
6678  *
6679  * Writes value to specified PHY register
6680  **/
6681 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6682                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6683 {
6684         enum i40e_status_code status;
6685
6686         switch (hw->device_id) {
6687         case I40E_DEV_ID_1G_BASE_T_X722:
6688                 status = i40e_write_phy_register_clause22(hw,
6689                         reg, phy_addr, value);
6690                 break;
6691         case I40E_DEV_ID_10G_BASE_T:
6692         case I40E_DEV_ID_10G_BASE_T4:
6693         case I40E_DEV_ID_10G_BASE_T_BC:
6694         case I40E_DEV_ID_10G_BASE_T_X722:
6695         case I40E_DEV_ID_25G_B:
6696         case I40E_DEV_ID_25G_SFP28:
6697                 status = i40e_write_phy_register_clause45(hw,
6698                         page, reg, phy_addr, value);
6699                 break;
6700         default:
6701                 status = I40E_ERR_UNKNOWN_PHY;
6702                 break;
6703         }
6704
6705         return status;
6706 }
6707
6708 /**
6709  * i40e_read_phy_register
6710  * @hw: pointer to the HW structure
6711  * @page: registers page number
6712  * @reg: register address in the page
6713  * @phy_addr: PHY address on MDIO interface
6714  * @value: PHY register value
6715  *
6716  * Reads specified PHY register value
6717  **/
6718 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6719                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6720 {
6721         enum i40e_status_code status;
6722
6723         switch (hw->device_id) {
6724         case I40E_DEV_ID_1G_BASE_T_X722:
6725                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6726                                                          value);
6727                 break;
6728         case I40E_DEV_ID_10G_BASE_T:
6729         case I40E_DEV_ID_10G_BASE_T4:
6730         case I40E_DEV_ID_10G_BASE_T_X722:
6731         case I40E_DEV_ID_25G_B:
6732         case I40E_DEV_ID_25G_SFP28:
6733                 status = i40e_read_phy_register_clause45(hw, page, reg,
6734                                                          phy_addr, value);
6735                 break;
6736         default:
6737                 status = I40E_ERR_UNKNOWN_PHY;
6738                 break;
6739         }
6740
6741         return status;
6742 }
6743
6744 /**
6745  * i40e_get_phy_address
6746  * @hw: pointer to the HW structure
6747  * @dev_num: PHY port num that address we want
6748  *
6749  * Gets PHY address for current port
6750  **/
6751 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6752 {
6753         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6754         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6755
6756         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6757 }
6758
6759 /**
6760  * i40e_blink_phy_led
6761  * @hw: pointer to the HW structure
6762  * @time: time how long led will blinks in secs
6763  * @interval: gap between LED on and off in msecs
6764  *
6765  * Blinks PHY link LED
6766  **/
6767 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6768                                               u32 time, u32 interval)
6769 {
6770         enum i40e_status_code status = I40E_SUCCESS;
6771         u32 i;
6772         u16 led_ctl = 0;
6773         u16 gpio_led_port;
6774         u16 led_reg;
6775         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6776         u8 phy_addr = 0;
6777         u8 port_num;
6778
6779         i = rd32(hw, I40E_PFGEN_PORTNUM);
6780         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6781         phy_addr = i40e_get_phy_address(hw, port_num);
6782
6783         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6784              led_addr++) {
6785                 status = i40e_read_phy_register_clause45(hw,
6786                                                          I40E_PHY_COM_REG_PAGE,
6787                                                          led_addr, phy_addr,
6788                                                          &led_reg);
6789                 if (status)
6790                         goto phy_blinking_end;
6791                 led_ctl = led_reg;
6792                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6793                         led_reg = 0;
6794                         status = i40e_write_phy_register_clause45(hw,
6795                                                          I40E_PHY_COM_REG_PAGE,
6796                                                          led_addr, phy_addr,
6797                                                          led_reg);
6798                         if (status)
6799                                 goto phy_blinking_end;
6800                         break;
6801                 }
6802         }
6803
6804         if (time > 0 && interval > 0) {
6805                 for (i = 0; i < time * 1000; i += interval) {
6806                         status = i40e_read_phy_register_clause45(hw,
6807                                                 I40E_PHY_COM_REG_PAGE,
6808                                                 led_addr, phy_addr, &led_reg);
6809                         if (status)
6810                                 goto restore_config;
6811                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6812                                 led_reg = 0;
6813                         else
6814                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6815                         status = i40e_write_phy_register_clause45(hw,
6816                                                 I40E_PHY_COM_REG_PAGE,
6817                                                 led_addr, phy_addr, led_reg);
6818                         if (status)
6819                                 goto restore_config;
6820                         i40e_msec_delay(interval);
6821                 }
6822         }
6823
6824 restore_config:
6825         status = i40e_write_phy_register_clause45(hw,
6826                                                   I40E_PHY_COM_REG_PAGE,
6827                                                   led_addr, phy_addr, led_ctl);
6828
6829 phy_blinking_end:
6830         return status;
6831 }
6832
6833 /**
6834  * i40e_led_get_reg - read LED register
6835  * @hw: pointer to the HW structure
6836  * @led_addr: LED register address
6837  * @reg_val: read register value
6838  **/
6839 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6840                                               u32 *reg_val)
6841 {
6842         enum i40e_status_code status;
6843         u8 phy_addr = 0;
6844
6845         *reg_val = 0;
6846         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6847                 status = i40e_aq_get_phy_register(hw,
6848                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6849                                                 I40E_PHY_COM_REG_PAGE, true,
6850                                                 I40E_PHY_LED_PROV_REG_1,
6851                                                 reg_val, NULL);
6852         } else {
6853                 phy_addr = i40e_get_phy_address(hw, hw->port);
6854                 status = i40e_read_phy_register_clause45(hw,
6855                                                          I40E_PHY_COM_REG_PAGE,
6856                                                          led_addr, phy_addr,
6857                                                          (u16 *)reg_val);
6858         }
6859         return status;
6860 }
6861
6862 /**
6863  * i40e_led_set_reg - write LED register
6864  * @hw: pointer to the HW structure
6865  * @led_addr: LED register address
6866  * @reg_val: register value to write
6867  **/
6868 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6869                                               u32 reg_val)
6870 {
6871         enum i40e_status_code status;
6872         u8 phy_addr = 0;
6873
6874         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6875                 status = i40e_aq_set_phy_register(hw,
6876                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6877                                                 I40E_PHY_COM_REG_PAGE, true,
6878                                                 I40E_PHY_LED_PROV_REG_1,
6879                                                 reg_val, NULL);
6880         } else {
6881                 phy_addr = i40e_get_phy_address(hw, hw->port);
6882                 status = i40e_write_phy_register_clause45(hw,
6883                                                           I40E_PHY_COM_REG_PAGE,
6884                                                           led_addr, phy_addr,
6885                                                           (u16)reg_val);
6886         }
6887
6888         return status;
6889 }
6890
6891 /**
6892  * i40e_led_get_phy - return current on/off mode
6893  * @hw: pointer to the hw struct
6894  * @led_addr: address of led register to use
6895  * @val: original value of register to use
6896  *
6897  **/
6898 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6899                                        u16 *val)
6900 {
6901         enum i40e_status_code status = I40E_SUCCESS;
6902         u16 gpio_led_port;
6903         u32 reg_val_aq;
6904         u16 temp_addr;
6905         u8 phy_addr = 0;
6906         u16 reg_val;
6907
6908         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6909                 status = i40e_aq_get_phy_register(hw,
6910                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6911                                                 I40E_PHY_COM_REG_PAGE, true,
6912                                                 I40E_PHY_LED_PROV_REG_1,
6913                                                 &reg_val_aq, NULL);
6914                 if (status == I40E_SUCCESS)
6915                         *val = (u16)reg_val_aq;
6916                 return status;
6917         }
6918         temp_addr = I40E_PHY_LED_PROV_REG_1;
6919         phy_addr = i40e_get_phy_address(hw, hw->port);
6920         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6921              temp_addr++) {
6922                 status = i40e_read_phy_register_clause45(hw,
6923                                                          I40E_PHY_COM_REG_PAGE,
6924                                                          temp_addr, phy_addr,
6925                                                          &reg_val);
6926                 if (status)
6927                         return status;
6928                 *val = reg_val;
6929                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6930                         *led_addr = temp_addr;
6931                         break;
6932                 }
6933         }
6934         return status;
6935 }
6936
6937 /**
6938  * i40e_led_set_phy
6939  * @hw: pointer to the HW structure
6940  * @on: true or false
6941  * @led_addr: address of led register to use
6942  * @mode: original val plus bit for set or ignore
6943  *
6944  * Set led's on or off when controlled by the PHY
6945  *
6946  **/
6947 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6948                                        u16 led_addr, u32 mode)
6949 {
6950         enum i40e_status_code status = I40E_SUCCESS;
6951         u32 led_ctl = 0;
6952         u32 led_reg = 0;
6953
6954         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6955         if (status)
6956                 return status;
6957         led_ctl = led_reg;
6958         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6959                 led_reg = 0;
6960                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6961                 if (status)
6962                         return status;
6963         }
6964         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6965         if (status)
6966                 goto restore_config;
6967         if (on)
6968                 led_reg = I40E_PHY_LED_MANUAL_ON;
6969         else
6970                 led_reg = 0;
6971         status = i40e_led_set_reg(hw, led_addr, led_reg);
6972         if (status)
6973                 goto restore_config;
6974         if (mode & I40E_PHY_LED_MODE_ORIG) {
6975                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6976                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6977         }
6978         return status;
6979
6980 restore_config:
6981         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6982         return status;
6983 }
6984 #endif /* PF_DRIVER */
6985 /**
6986  * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
6987  * @hw: pointer to the hw struct
6988  * @stat: pointer to structure with status of rx and tx lpi
6989  *
6990  * Read LPI state directly from external PHY register or from MAC
6991  * register, depending on device ID and current link speed.
6992  */
6993 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
6994                                               struct i40e_hw_port_stats *stat)
6995 {
6996         enum i40e_status_code ret = I40E_SUCCESS;
6997         u32 val;
6998
6999         stat->rx_lpi_status = 0;
7000         stat->tx_lpi_status = 0;
7001
7002         if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7003             (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7004              hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
7005                 ret = i40e_aq_get_phy_register(hw,
7006                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7007                                                I40E_BCM_PHY_PCS_STATUS1_PAGE,
7008                                                true,
7009                                                I40E_BCM_PHY_PCS_STATUS1_REG,
7010                                                &val, NULL);
7011
7012                 if (ret != I40E_SUCCESS)
7013                         return ret;
7014
7015                 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7016                 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7017
7018                 return ret;
7019         }
7020
7021         val = rd32(hw, I40E_PRTPM_EEE_STAT);
7022         stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7023                                I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7024         stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7025                                I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7026
7027         return ret;
7028 }
7029
7030 /**
7031  * i40e_get_lpi_counters - read LPI counters from EEE statistics
7032  * @hw: pointer to the hw struct
7033  * @tx_counter: pointer to memory for TX LPI counter
7034  * @rx_counter: pointer to memory for RX LPI counter
7035  * @is_clear:   returns true if counters are clear after read
7036  *
7037  * Read Low Power Idle (LPI) mode counters from Energy Efficient
7038  * Ethernet (EEE) statistics.
7039  **/
7040 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7041                                             u32 *tx_counter, u32 *rx_counter,
7042                                             bool *is_clear)
7043 {
7044         /* only X710-T*L requires special handling of counters
7045          * for other devices we just read the MAC registers
7046          */
7047         if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7048             hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7049                 enum i40e_status_code retval;
7050                 u32 cmd_status = 0;
7051
7052                 *is_clear = false;
7053                 retval = i40e_aq_run_phy_activity(hw,
7054                                 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7055                                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7056                                 &cmd_status, tx_counter, rx_counter, NULL);
7057
7058                 if (cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7059                         retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7060
7061                 return retval;
7062         }
7063
7064         *is_clear = true;
7065         *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7066         *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7067
7068         return I40E_SUCCESS;
7069 }
7070
7071 /**
7072  * i40e_lpi_stat_update - update LPI counters with values relative to offset
7073  * @hw: pointer to the hw struct
7074  * @offset_loaded: flag indicating need of writing current value to offset
7075  * @tx_offset: pointer to offset of TX LPI counter
7076  * @tx_stat: pointer to value of TX LPI counter
7077  * @rx_offset: pointer to offset of RX LPI counter
7078  * @rx_stat: pointer to value of RX LPI counter
7079  *
7080  * Update Low Power Idle (LPI) mode counters while having regard to passed
7081  * offsets.
7082  **/
7083 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7084                                            bool offset_loaded, u64 *tx_offset,
7085                                            u64 *tx_stat, u64 *rx_offset,
7086                                            u64 *rx_stat)
7087 {
7088         enum i40e_status_code retval;
7089         u32 tx_counter, rx_counter;
7090         bool is_clear;
7091
7092         retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7093         if (retval)
7094                 goto err;
7095
7096         if (is_clear) {
7097                 *tx_stat += tx_counter;
7098                 *rx_stat += rx_counter;
7099         } else {
7100                 if (!offset_loaded) {
7101                         *tx_offset = tx_counter;
7102                         *rx_offset = rx_counter;
7103                 }
7104
7105                 *tx_stat = (tx_counter >= *tx_offset) ?
7106                         (u32)(tx_counter - *tx_offset) :
7107                         (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7108                 *rx_stat = (rx_counter >= *rx_offset) ?
7109                         (u32)(rx_counter - *rx_offset) :
7110                         (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7111         }
7112 err:
7113         return retval;
7114 }
7115
7116 /**
7117  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7118  * @hw: pointer to the hw struct
7119  * @reg_addr: register address
7120  * @reg_val: ptr to register value
7121  * @cmd_details: pointer to command details structure or NULL
7122  *
7123  * Use the firmware to read the Rx control register,
7124  * especially useful if the Rx unit is under heavy pressure
7125  **/
7126 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7127                                 u32 reg_addr, u32 *reg_val,
7128                                 struct i40e_asq_cmd_details *cmd_details)
7129 {
7130         struct i40e_aq_desc desc;
7131         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7132                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7133         enum i40e_status_code status;
7134
7135         if (reg_val == NULL)
7136                 return I40E_ERR_PARAM;
7137
7138         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7139
7140         cmd_resp->address = CPU_TO_LE32(reg_addr);
7141
7142         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7143
7144         if (status == I40E_SUCCESS)
7145                 *reg_val = LE32_TO_CPU(cmd_resp->value);
7146
7147         return status;
7148 }
7149
7150 /**
7151  * i40e_read_rx_ctl - read from an Rx control register
7152  * @hw: pointer to the hw struct
7153  * @reg_addr: register address
7154  **/
7155 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7156 {
7157         enum i40e_status_code status = I40E_SUCCESS;
7158         bool use_register;
7159         int retry = 5;
7160         u32 val = 0;
7161
7162         use_register = (((hw->aq.api_maj_ver == 1) &&
7163                         (hw->aq.api_min_ver < 5)) ||
7164                         (hw->mac.type == I40E_MAC_X722));
7165         if (!use_register) {
7166 do_retry:
7167                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7168                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7169                         i40e_msec_delay(1);
7170                         retry--;
7171                         goto do_retry;
7172                 }
7173         }
7174
7175         /* if the AQ access failed, try the old-fashioned way */
7176         if (status || use_register)
7177                 val = rd32(hw, reg_addr);
7178
7179         return val;
7180 }
7181
7182 /**
7183  * i40e_aq_rx_ctl_write_register
7184  * @hw: pointer to the hw struct
7185  * @reg_addr: register address
7186  * @reg_val: register value
7187  * @cmd_details: pointer to command details structure or NULL
7188  *
7189  * Use the firmware to write to an Rx control register,
7190  * especially useful if the Rx unit is under heavy pressure
7191  **/
7192 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7193                                 u32 reg_addr, u32 reg_val,
7194                                 struct i40e_asq_cmd_details *cmd_details)
7195 {
7196         struct i40e_aq_desc desc;
7197         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7198                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7199         enum i40e_status_code status;
7200
7201         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7202
7203         cmd->address = CPU_TO_LE32(reg_addr);
7204         cmd->value = CPU_TO_LE32(reg_val);
7205
7206         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7207
7208         return status;
7209 }
7210
7211 /**
7212  * i40e_write_rx_ctl - write to an Rx control register
7213  * @hw: pointer to the hw struct
7214  * @reg_addr: register address
7215  * @reg_val: register value
7216  **/
7217 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7218 {
7219         enum i40e_status_code status = I40E_SUCCESS;
7220         bool use_register;
7221         int retry = 5;
7222
7223         use_register = (((hw->aq.api_maj_ver == 1) &&
7224                         (hw->aq.api_min_ver < 5)) ||
7225                         (hw->mac.type == I40E_MAC_X722));
7226         if (!use_register) {
7227 do_retry:
7228                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7229                                                        reg_val, NULL);
7230                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7231                         i40e_msec_delay(1);
7232                         retry--;
7233                         goto do_retry;
7234                 }
7235         }
7236
7237         /* if the AQ access failed, try the old-fashioned way */
7238         if (status || use_register)
7239                 wr32(hw, reg_addr, reg_val);
7240 }
7241
7242 /**
7243  * i40e_mdio_if_number_selection - MDIO I/F number selection
7244  * @hw: pointer to the hw struct
7245  * @set_mdio: use MDIO I/F number specified by mdio_num
7246  * @mdio_num: MDIO I/F number
7247  * @cmd: pointer to PHY Register command structure
7248  **/
7249 static void
7250 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7251                               struct i40e_aqc_phy_register_access *cmd)
7252 {
7253         if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7254                 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7255                         cmd->cmd_flags |=
7256                                 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7257                                 ((mdio_num <<
7258                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7259                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7260                 else
7261                         i40e_debug(hw, I40E_DEBUG_PHY,
7262                                    "MDIO I/F number selection not supported by current FW version.\n");
7263         }
7264 }
7265
7266 /**
7267  * i40e_aq_set_phy_register_ext
7268  * @hw: pointer to the hw struct
7269  * @phy_select: select which phy should be accessed
7270  * @dev_addr: PHY device address
7271  * @page_change: enable auto page change
7272  * @set_mdio: use MDIO I/F number specified by mdio_num
7273  * @mdio_num: MDIO I/F number
7274  * @reg_addr: PHY register address
7275  * @reg_val: new register value
7276  * @cmd_details: pointer to command details structure or NULL
7277  *
7278  * Write the external PHY register.
7279  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7280  * may use simple wrapper i40e_aq_set_phy_register.
7281  **/
7282 enum i40e_status_code
7283 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7284                              u8 phy_select, u8 dev_addr, bool page_change,
7285                              bool set_mdio, u8 mdio_num,
7286                              u32 reg_addr, u32 reg_val,
7287                              struct i40e_asq_cmd_details *cmd_details)
7288 {
7289         struct i40e_aq_desc desc;
7290         struct i40e_aqc_phy_register_access *cmd =
7291                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7292         enum i40e_status_code status;
7293
7294         i40e_fill_default_direct_cmd_desc(&desc,
7295                                           i40e_aqc_opc_set_phy_register);
7296
7297         cmd->phy_interface = phy_select;
7298         cmd->dev_addres = dev_addr;
7299         cmd->reg_address = CPU_TO_LE32(reg_addr);
7300         cmd->reg_value = CPU_TO_LE32(reg_val);
7301
7302         if (!page_change)
7303                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7304
7305         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7306
7307         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7308
7309         return status;
7310 }
7311
7312 /**
7313  * i40e_aq_get_phy_register_ext
7314  * @hw: pointer to the hw struct
7315  * @phy_select: select which phy should be accessed
7316  * @dev_addr: PHY device address
7317  * @page_change: enable auto page change
7318  * @set_mdio: use MDIO I/F number specified by mdio_num
7319  * @mdio_num: MDIO I/F number
7320  * @reg_addr: PHY register address
7321  * @reg_val: read register value
7322  * @cmd_details: pointer to command details structure or NULL
7323  *
7324  * Read the external PHY register.
7325  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7326  * may use simple wrapper i40e_aq_get_phy_register.
7327  **/
7328 enum i40e_status_code
7329 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7330                              u8 phy_select, u8 dev_addr, bool page_change,
7331                              bool set_mdio, u8 mdio_num,
7332                              u32 reg_addr, u32 *reg_val,
7333                              struct i40e_asq_cmd_details *cmd_details)
7334 {
7335         struct i40e_aq_desc desc;
7336         struct i40e_aqc_phy_register_access *cmd =
7337                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7338         enum i40e_status_code status;
7339
7340         i40e_fill_default_direct_cmd_desc(&desc,
7341                                           i40e_aqc_opc_get_phy_register);
7342
7343         cmd->phy_interface = phy_select;
7344         cmd->dev_addres = dev_addr;
7345         cmd->reg_address = CPU_TO_LE32(reg_addr);
7346
7347         if (!page_change)
7348                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7349
7350         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7351
7352         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7353         if (!status)
7354                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7355
7356         return status;
7357 }
7358
7359 /**
7360  * i40e_aq_run_phy_activity
7361  * @hw: pointer to the hw struct
7362  * @activity_id: ID of DNL activity to run
7363  * @dnl_opcode: opcode passed to DNL script
7364  * @cmd_status: pointer to memory to write return value of DNL script
7365  * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7366  * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7367  * @cmd_details: pointer to command details structure or NULL
7368  *
7369  * Run DNL admin command.
7370  **/
7371 enum i40e_status_code
7372 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7373                          u32 *cmd_status, u32 *data0, u32 *data1,
7374                          struct i40e_asq_cmd_details *cmd_details)
7375 {
7376         struct i40e_aqc_run_phy_activity *cmd;
7377         enum i40e_status_code retval;
7378         struct i40e_aq_desc desc;
7379
7380         cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7381
7382         if (!cmd_status || !data0 || !data1) {
7383                 retval = I40E_ERR_PARAM;
7384                 goto err;
7385         }
7386
7387         i40e_fill_default_direct_cmd_desc(&desc,
7388                                           i40e_aqc_opc_run_phy_activity);
7389
7390         cmd->activity_id = CPU_TO_LE16(activity_id);
7391         cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7392
7393         retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7394         if (retval)
7395                 goto err;
7396
7397         *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7398         *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7399         *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7400 err:
7401         return retval;
7402 }
7403
7404 #ifdef VF_DRIVER
7405
7406 /**
7407  * i40e_aq_send_msg_to_pf
7408  * @hw: pointer to the hardware structure
7409  * @v_opcode: opcodes for VF-PF communication
7410  * @v_retval: return error code
7411  * @msg: pointer to the msg buffer
7412  * @msglen: msg length
7413  * @cmd_details: pointer to command details
7414  *
7415  * Send message to PF driver using admin queue. By default, this message
7416  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7417  * completion before returning.
7418  **/
7419 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7420                                 enum virtchnl_ops v_opcode,
7421                                 enum i40e_status_code v_retval,
7422                                 u8 *msg, u16 msglen,
7423                                 struct i40e_asq_cmd_details *cmd_details)
7424 {
7425         struct i40e_aq_desc desc;
7426         struct i40e_asq_cmd_details details;
7427         enum i40e_status_code status;
7428
7429         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7430         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7431         desc.cookie_high = CPU_TO_LE32(v_opcode);
7432         desc.cookie_low = CPU_TO_LE32(v_retval);
7433         if (msglen) {
7434                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7435                                                 | I40E_AQ_FLAG_RD));
7436                 if (msglen > I40E_AQ_LARGE_BUF)
7437                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7438                 desc.datalen = CPU_TO_LE16(msglen);
7439         }
7440         if (!cmd_details) {
7441                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7442                 details.async = true;
7443                 cmd_details = &details;
7444         }
7445         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7446                                        msglen, cmd_details);
7447         return status;
7448 }
7449
7450 /**
7451  * i40e_vf_parse_hw_config
7452  * @hw: pointer to the hardware structure
7453  * @msg: pointer to the virtual channel VF resource structure
7454  *
7455  * Given a VF resource message from the PF, populate the hw struct
7456  * with appropriate information.
7457  **/
7458 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7459                              struct virtchnl_vf_resource *msg)
7460 {
7461         struct virtchnl_vsi_resource *vsi_res;
7462         int i;
7463
7464         vsi_res = &msg->vsi_res[0];
7465
7466         hw->dev_caps.num_vsis = msg->num_vsis;
7467         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7468         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7469         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7470         hw->dev_caps.dcb = msg->vf_cap_flags &
7471                            VIRTCHNL_VF_OFFLOAD_L2;
7472         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7473                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7474         for (i = 0; i < msg->num_vsis; i++) {
7475                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7476                         i40e_memcpy(hw->mac.perm_addr,
7477                                     vsi_res->default_mac_addr,
7478                                     ETH_ALEN,
7479                                     I40E_NONDMA_TO_NONDMA);
7480                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7481                                     ETH_ALEN,
7482                                     I40E_NONDMA_TO_NONDMA);
7483                 }
7484                 vsi_res++;
7485         }
7486 }
7487
7488 /**
7489  * i40e_vf_reset
7490  * @hw: pointer to the hardware structure
7491  *
7492  * Send a VF_RESET message to the PF. Does not wait for response from PF
7493  * as none will be forthcoming. Immediately after calling this function,
7494  * the admin queue should be shut down and (optionally) reinitialized.
7495  **/
7496 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7497 {
7498         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7499                                       I40E_SUCCESS, NULL, 0, NULL);
7500 }
7501 #endif /* VF_DRIVER */
7502
7503 /**
7504  * i40e_aq_set_arp_proxy_config
7505  * @hw: pointer to the HW structure
7506  * @proxy_config: pointer to proxy config command table struct
7507  * @cmd_details: pointer to command details
7508  *
7509  * Set ARP offload parameters from pre-populated
7510  * i40e_aqc_arp_proxy_data struct
7511  **/
7512 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7513                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7514                                 struct i40e_asq_cmd_details *cmd_details)
7515 {
7516         struct i40e_aq_desc desc;
7517         enum i40e_status_code status;
7518
7519         if (!proxy_config)
7520                 return I40E_ERR_PARAM;
7521
7522         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7523
7524         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7525         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7526         desc.params.external.addr_high =
7527                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7528         desc.params.external.addr_low =
7529                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7530         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7531
7532         status = i40e_asq_send_command(hw, &desc, proxy_config,
7533                                        sizeof(struct i40e_aqc_arp_proxy_data),
7534                                        cmd_details);
7535
7536         return status;
7537 }
7538
7539 /**
7540  * i40e_aq_opc_set_ns_proxy_table_entry
7541  * @hw: pointer to the HW structure
7542  * @ns_proxy_table_entry: pointer to NS table entry command struct
7543  * @cmd_details: pointer to command details
7544  *
7545  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7546  * from pre-populated i40e_aqc_ns_proxy_data struct
7547  **/
7548 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7549                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7550                         struct i40e_asq_cmd_details *cmd_details)
7551 {
7552         struct i40e_aq_desc desc;
7553         enum i40e_status_code status;
7554
7555         if (!ns_proxy_table_entry)
7556                 return I40E_ERR_PARAM;
7557
7558         i40e_fill_default_direct_cmd_desc(&desc,
7559                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7560
7561         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7562         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7563         desc.params.external.addr_high =
7564                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7565         desc.params.external.addr_low =
7566                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7567         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7568
7569         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7570                                        sizeof(struct i40e_aqc_ns_proxy_data),
7571                                        cmd_details);
7572
7573         return status;
7574 }
7575
7576 /**
7577  * i40e_aq_set_clear_wol_filter
7578  * @hw: pointer to the hw struct
7579  * @filter_index: index of filter to modify (0-7)
7580  * @filter: buffer containing filter to be set
7581  * @set_filter: true to set filter, false to clear filter
7582  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7583  *              if false, pass through packets may cause wake-up
7584  * @filter_valid: true if filter action is valid
7585  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7586  * @cmd_details: pointer to command details structure or NULL
7587  *
7588  * Set or clear WoL filter for port attached to the PF
7589  **/
7590 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7591                                 u8 filter_index,
7592                                 struct i40e_aqc_set_wol_filter_data *filter,
7593                                 bool set_filter, bool no_wol_tco,
7594                                 bool filter_valid, bool no_wol_tco_valid,
7595                                 struct i40e_asq_cmd_details *cmd_details)
7596 {
7597         struct i40e_aq_desc desc;
7598         struct i40e_aqc_set_wol_filter *cmd =
7599                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7600         enum i40e_status_code status;
7601         u16 cmd_flags = 0;
7602         u16 valid_flags = 0;
7603         u16 buff_len = 0;
7604
7605         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7606
7607         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7608                 return  I40E_ERR_PARAM;
7609         cmd->filter_index = CPU_TO_LE16(filter_index);
7610
7611         if (set_filter) {
7612                 if (!filter)
7613                         return  I40E_ERR_PARAM;
7614
7615                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7616                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7617         }
7618
7619         if (no_wol_tco)
7620                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7621         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7622
7623         if (filter_valid)
7624                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7625         if (no_wol_tco_valid)
7626                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7627         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7628
7629         buff_len = sizeof(*filter);
7630         desc.datalen = CPU_TO_LE16(buff_len);
7631
7632         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7633         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7634
7635         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7636         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7637
7638         status = i40e_asq_send_command(hw, &desc, filter,
7639                                        buff_len, cmd_details);
7640
7641         return status;
7642 }
7643
7644 /**
7645  * i40e_aq_get_wake_event_reason
7646  * @hw: pointer to the hw struct
7647  * @wake_reason: return value, index of matching filter
7648  * @cmd_details: pointer to command details structure or NULL
7649  *
7650  * Get information for the reason of a Wake Up event
7651  **/
7652 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7653                                 u16 *wake_reason,
7654                                 struct i40e_asq_cmd_details *cmd_details)
7655 {
7656         struct i40e_aq_desc desc;
7657         struct i40e_aqc_get_wake_reason_completion *resp =
7658                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7659         enum i40e_status_code status;
7660
7661         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7662
7663         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7664
7665         if (status == I40E_SUCCESS)
7666                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7667
7668         return status;
7669 }
7670
7671 /**
7672 * i40e_aq_clear_all_wol_filters
7673 * @hw: pointer to the hw struct
7674 * @cmd_details: pointer to command details structure or NULL
7675 *
7676 * Get information for the reason of a Wake Up event
7677 **/
7678 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7679         struct i40e_asq_cmd_details *cmd_details)
7680 {
7681         struct i40e_aq_desc desc;
7682         enum i40e_status_code status;
7683
7684         i40e_fill_default_direct_cmd_desc(&desc,
7685                                           i40e_aqc_opc_clear_all_wol_filters);
7686
7687         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7688
7689         return status;
7690 }
7691
7692 /**
7693  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7694  * @hw: pointer to the hw struct
7695  * @buff: command buffer (size in bytes = buff_size)
7696  * @buff_size: buffer size in bytes
7697  * @track_id: package tracking id
7698  * @error_offset: returns error offset
7699  * @error_info: returns error information
7700  * @cmd_details: pointer to command details structure or NULL
7701  **/
7702 enum
7703 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7704                                    u16 buff_size, u32 track_id,
7705                                    u32 *error_offset, u32 *error_info,
7706                                    struct i40e_asq_cmd_details *cmd_details)
7707 {
7708         struct i40e_aq_desc desc;
7709         struct i40e_aqc_write_personalization_profile *cmd =
7710                 (struct i40e_aqc_write_personalization_profile *)
7711                 &desc.params.raw;
7712         struct i40e_aqc_write_ddp_resp *resp;
7713         enum i40e_status_code status;
7714
7715         i40e_fill_default_direct_cmd_desc(&desc,
7716                                   i40e_aqc_opc_write_personalization_profile);
7717
7718         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7719         if (buff_size > I40E_AQ_LARGE_BUF)
7720                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7721
7722         desc.datalen = CPU_TO_LE16(buff_size);
7723
7724         cmd->profile_track_id = CPU_TO_LE32(track_id);
7725
7726         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7727         if (!status) {
7728                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7729                 if (error_offset)
7730                         *error_offset = LE32_TO_CPU(resp->error_offset);
7731                 if (error_info)
7732                         *error_info = LE32_TO_CPU(resp->error_info);
7733         }
7734
7735         return status;
7736 }
7737
7738 /**
7739  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7740  * @hw: pointer to the hw struct
7741  * @buff: command buffer (size in bytes = buff_size)
7742  * @buff_size: buffer size in bytes
7743  * @flags: AdminQ command flags
7744  * @cmd_details: pointer to command details structure or NULL
7745  **/
7746 enum
7747 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7748                                       u16 buff_size, u8 flags,
7749                                       struct i40e_asq_cmd_details *cmd_details)
7750 {
7751         struct i40e_aq_desc desc;
7752         struct i40e_aqc_get_applied_profiles *cmd =
7753                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7754         enum i40e_status_code status;
7755
7756         i40e_fill_default_direct_cmd_desc(&desc,
7757                           i40e_aqc_opc_get_personalization_profile_list);
7758
7759         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7760         if (buff_size > I40E_AQ_LARGE_BUF)
7761                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7762         desc.datalen = CPU_TO_LE16(buff_size);
7763
7764         cmd->flags = flags;
7765
7766         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7767
7768         return status;
7769 }
7770
7771 /**
7772  * i40e_find_segment_in_package
7773  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7774  * @pkg_hdr: pointer to the package header to be searched
7775  *
7776  * This function searches a package file for a particular segment type. On
7777  * success it returns a pointer to the segment header, otherwise it will
7778  * return NULL.
7779  **/
7780 struct i40e_generic_seg_header *
7781 i40e_find_segment_in_package(u32 segment_type,
7782                              struct i40e_package_header *pkg_hdr)
7783 {
7784         struct i40e_generic_seg_header *segment;
7785         u32 i;
7786
7787         /* Search all package segments for the requested segment type */
7788         for (i = 0; i < pkg_hdr->segment_count; i++) {
7789                 segment =
7790                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7791                          pkg_hdr->segment_offset[i]);
7792
7793                 if (segment->type == segment_type)
7794                         return segment;
7795         }
7796
7797         return NULL;
7798 }
7799
7800 /* Get section table in profile */
7801 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7802         do {                                                            \
7803                 struct i40e_profile_segment *p = (profile);             \
7804                 u32 count;                                              \
7805                 u32 *nvm;                                               \
7806                 count = p->device_table_count;                          \
7807                 nvm = (u32 *)&p->device_table[count];                   \
7808                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7809         } while (0)
7810
7811 /* Get section header in profile */
7812 #define I40E_SECTION_HEADER(profile, offset)                            \
7813         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7814
7815 /**
7816  * i40e_find_section_in_profile
7817  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7818  * @profile: pointer to the i40e segment header to be searched
7819  *
7820  * This function searches i40e segment for a particular section type. On
7821  * success it returns a pointer to the section header, otherwise it will
7822  * return NULL.
7823  **/
7824 struct i40e_profile_section_header *
7825 i40e_find_section_in_profile(u32 section_type,
7826                              struct i40e_profile_segment *profile)
7827 {
7828         struct i40e_profile_section_header *sec;
7829         struct i40e_section_table *sec_tbl;
7830         u32 sec_off;
7831         u32 i;
7832
7833         if (profile->header.type != SEGMENT_TYPE_I40E)
7834                 return NULL;
7835
7836         I40E_SECTION_TABLE(profile, sec_tbl);
7837
7838         for (i = 0; i < sec_tbl->section_count; i++) {
7839                 sec_off = sec_tbl->section_offset[i];
7840                 sec = I40E_SECTION_HEADER(profile, sec_off);
7841                 if (sec->section.type == section_type)
7842                         return sec;
7843         }
7844
7845         return NULL;
7846 }
7847
7848 /**
7849  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7850  * @hw: pointer to the hw struct
7851  * @aq: command buffer containing all data to execute AQ
7852  **/
7853 STATIC enum
7854 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7855                                           struct i40e_profile_aq_section *aq)
7856 {
7857         enum i40e_status_code status;
7858         struct i40e_aq_desc desc;
7859         u8 *msg = NULL;
7860         u16 msglen;
7861
7862         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7863         desc.flags |= CPU_TO_LE16(aq->flags);
7864         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7865                     I40E_NONDMA_TO_NONDMA);
7866
7867         msglen = aq->datalen;
7868         if (msglen) {
7869                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7870                                                 I40E_AQ_FLAG_RD));
7871                 if (msglen > I40E_AQ_LARGE_BUF)
7872                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7873                 desc.datalen = CPU_TO_LE16(msglen);
7874                 msg = &aq->data[0];
7875         }
7876
7877         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7878
7879         if (status != I40E_SUCCESS) {
7880                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7881                            "unable to exec DDP AQ opcode %u, error %d\n",
7882                            aq->opcode, status);
7883                 return status;
7884         }
7885
7886         /* copy returned desc to aq_buf */
7887         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7888                     I40E_NONDMA_TO_NONDMA);
7889
7890         return I40E_SUCCESS;
7891 }
7892
7893 /**
7894  * i40e_validate_profile
7895  * @hw: pointer to the hardware structure
7896  * @profile: pointer to the profile segment of the package to be validated
7897  * @track_id: package tracking id
7898  * @rollback: flag if the profile is for rollback.
7899  *
7900  * Validates supported devices and profile's sections.
7901  */
7902 STATIC enum i40e_status_code
7903 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7904                       u32 track_id, bool rollback)
7905 {
7906         struct i40e_profile_section_header *sec = NULL;
7907         enum i40e_status_code status = I40E_SUCCESS;
7908         struct i40e_section_table *sec_tbl;
7909         u32 vendor_dev_id;
7910         u32 dev_cnt;
7911         u32 sec_off;
7912         u32 i;
7913
7914         if (track_id == I40E_DDP_TRACKID_INVALID) {
7915                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7916                 return I40E_NOT_SUPPORTED;
7917         }
7918
7919         dev_cnt = profile->device_table_count;
7920         for (i = 0; i < dev_cnt; i++) {
7921                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7922                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7923                     hw->device_id == (vendor_dev_id & 0xFFFF))
7924                         break;
7925         }
7926         if (dev_cnt && (i == dev_cnt)) {
7927                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7928                            "Device doesn't support DDP\n");
7929                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7930         }
7931
7932         I40E_SECTION_TABLE(profile, sec_tbl);
7933
7934         /* Validate sections types */
7935         for (i = 0; i < sec_tbl->section_count; i++) {
7936                 sec_off = sec_tbl->section_offset[i];
7937                 sec = I40E_SECTION_HEADER(profile, sec_off);
7938                 if (rollback) {
7939                         if (sec->section.type == SECTION_TYPE_MMIO ||
7940                             sec->section.type == SECTION_TYPE_AQ ||
7941                             sec->section.type == SECTION_TYPE_RB_AQ) {
7942                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7943                                            "Not a roll-back package\n");
7944                                 return I40E_NOT_SUPPORTED;
7945                         }
7946                 } else {
7947                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7948                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7949                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7950                                            "Not an original package\n");
7951                                 return I40E_NOT_SUPPORTED;
7952                         }
7953                 }
7954         }
7955
7956         return status;
7957 }
7958
7959 /**
7960  * i40e_write_profile
7961  * @hw: pointer to the hardware structure
7962  * @profile: pointer to the profile segment of the package to be downloaded
7963  * @track_id: package tracking id
7964  *
7965  * Handles the download of a complete package.
7966  */
7967 enum i40e_status_code
7968 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7969                    u32 track_id)
7970 {
7971         enum i40e_status_code status = I40E_SUCCESS;
7972         struct i40e_section_table *sec_tbl;
7973         struct i40e_profile_section_header *sec = NULL;
7974         struct i40e_profile_aq_section *ddp_aq;
7975         u32 section_size = 0;
7976         u32 offset = 0, info = 0;
7977         u32 sec_off;
7978         u32 i;
7979
7980         status = i40e_validate_profile(hw, profile, track_id, false);
7981         if (status)
7982                 return status;
7983
7984         I40E_SECTION_TABLE(profile, sec_tbl);
7985
7986         for (i = 0; i < sec_tbl->section_count; i++) {
7987                 sec_off = sec_tbl->section_offset[i];
7988                 sec = I40E_SECTION_HEADER(profile, sec_off);
7989                 /* Process generic admin command */
7990                 if (sec->section.type == SECTION_TYPE_AQ) {
7991                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7992                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7993                         if (status) {
7994                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7995                                            "Failed to execute aq: section %d, opcode %u\n",
7996                                            i, ddp_aq->opcode);
7997                                 break;
7998                         }
7999                         sec->section.type = SECTION_TYPE_RB_AQ;
8000                 }
8001
8002                 /* Skip any non-mmio sections */
8003                 if (sec->section.type != SECTION_TYPE_MMIO)
8004                         continue;
8005
8006                 section_size = sec->section.size +
8007                         sizeof(struct i40e_profile_section_header);
8008
8009                 /* Write MMIO section */
8010                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8011                                            track_id, &offset, &info, NULL);
8012                 if (status) {
8013                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8014                                    "Failed to write profile: section %d, offset %d, info %d\n",
8015                                    i, offset, info);
8016                         break;
8017                 }
8018         }
8019         return status;
8020 }
8021
8022 /**
8023  * i40e_rollback_profile
8024  * @hw: pointer to the hardware structure
8025  * @profile: pointer to the profile segment of the package to be removed
8026  * @track_id: package tracking id
8027  *
8028  * Rolls back previously loaded package.
8029  */
8030 enum i40e_status_code
8031 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8032                       u32 track_id)
8033 {
8034         struct i40e_profile_section_header *sec = NULL;
8035         enum i40e_status_code status = I40E_SUCCESS;
8036         struct i40e_section_table *sec_tbl;
8037         u32 offset = 0, info = 0;
8038         u32 section_size = 0;
8039         u32 sec_off;
8040         int i;
8041
8042         status = i40e_validate_profile(hw, profile, track_id, true);
8043         if (status)
8044                 return status;
8045
8046         I40E_SECTION_TABLE(profile, sec_tbl);
8047
8048         /* For rollback write sections in reverse */
8049         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8050                 sec_off = sec_tbl->section_offset[i];
8051                 sec = I40E_SECTION_HEADER(profile, sec_off);
8052
8053                 /* Skip any non-rollback sections */
8054                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8055                         continue;
8056
8057                 section_size = sec->section.size +
8058                         sizeof(struct i40e_profile_section_header);
8059
8060                 /* Write roll-back MMIO section */
8061                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8062                                            track_id, &offset, &info, NULL);
8063                 if (status) {
8064                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8065                                    "Failed to write profile: section %d, offset %d, info %d\n",
8066                                    i, offset, info);
8067                         break;
8068                 }
8069         }
8070         return status;
8071 }
8072
8073 /**
8074  * i40e_add_pinfo_to_list
8075  * @hw: pointer to the hardware structure
8076  * @profile: pointer to the profile segment of the package
8077  * @profile_info_sec: buffer for information section
8078  * @track_id: package tracking id
8079  *
8080  * Register a profile to the list of loaded profiles.
8081  */
8082 enum i40e_status_code
8083 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8084                        struct i40e_profile_segment *profile,
8085                        u8 *profile_info_sec, u32 track_id)
8086 {
8087         enum i40e_status_code status = I40E_SUCCESS;
8088         struct i40e_profile_section_header *sec = NULL;
8089         struct i40e_profile_info *pinfo;
8090         u32 offset = 0, info = 0;
8091
8092         sec = (struct i40e_profile_section_header *)profile_info_sec;
8093         sec->tbl_size = 1;
8094         sec->data_end = sizeof(struct i40e_profile_section_header) +
8095                         sizeof(struct i40e_profile_info);
8096         sec->section.type = SECTION_TYPE_INFO;
8097         sec->section.offset = sizeof(struct i40e_profile_section_header);
8098         sec->section.size = sizeof(struct i40e_profile_info);
8099         pinfo = (struct i40e_profile_info *)(profile_info_sec +
8100                                              sec->section.offset);
8101         pinfo->track_id = track_id;
8102         pinfo->version = profile->version;
8103         pinfo->op = I40E_DDP_ADD_TRACKID;
8104         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8105                     I40E_NONDMA_TO_NONDMA);
8106
8107         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8108                                    track_id, &offset, &info, NULL);
8109         return status;
8110 }