1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 hw->mac.type = I40E_MAC_X722;
88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
89 case I40E_DEV_ID_X722_VF:
90 case I40E_DEV_ID_X722_VF_HV:
91 #ifdef X722_A0_SUPPORT
92 case I40E_DEV_ID_X722_A0_VF:
94 hw->mac.type = I40E_MAC_X722_VF;
96 #endif /* INTEGRATED_VF || VF_DRIVER */
97 #endif /* X722_SUPPORT */
98 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
100 case I40E_DEV_ID_VF_HV:
101 hw->mac.type = I40E_MAC_VF;
105 hw->mac.type = I40E_MAC_GENERIC;
109 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
112 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
113 hw->mac.type, status);
117 #ifndef I40E_NDIS_SUPPORT
119 * i40e_aq_str - convert AQ err code to a string
120 * @hw: pointer to the HW structure
121 * @aq_err: the AQ error code to convert
123 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
128 case I40E_AQ_RC_EPERM:
129 return "I40E_AQ_RC_EPERM";
130 case I40E_AQ_RC_ENOENT:
131 return "I40E_AQ_RC_ENOENT";
132 case I40E_AQ_RC_ESRCH:
133 return "I40E_AQ_RC_ESRCH";
134 case I40E_AQ_RC_EINTR:
135 return "I40E_AQ_RC_EINTR";
137 return "I40E_AQ_RC_EIO";
138 case I40E_AQ_RC_ENXIO:
139 return "I40E_AQ_RC_ENXIO";
140 case I40E_AQ_RC_E2BIG:
141 return "I40E_AQ_RC_E2BIG";
142 case I40E_AQ_RC_EAGAIN:
143 return "I40E_AQ_RC_EAGAIN";
144 case I40E_AQ_RC_ENOMEM:
145 return "I40E_AQ_RC_ENOMEM";
146 case I40E_AQ_RC_EACCES:
147 return "I40E_AQ_RC_EACCES";
148 case I40E_AQ_RC_EFAULT:
149 return "I40E_AQ_RC_EFAULT";
150 case I40E_AQ_RC_EBUSY:
151 return "I40E_AQ_RC_EBUSY";
152 case I40E_AQ_RC_EEXIST:
153 return "I40E_AQ_RC_EEXIST";
154 case I40E_AQ_RC_EINVAL:
155 return "I40E_AQ_RC_EINVAL";
156 case I40E_AQ_RC_ENOTTY:
157 return "I40E_AQ_RC_ENOTTY";
158 case I40E_AQ_RC_ENOSPC:
159 return "I40E_AQ_RC_ENOSPC";
160 case I40E_AQ_RC_ENOSYS:
161 return "I40E_AQ_RC_ENOSYS";
162 case I40E_AQ_RC_ERANGE:
163 return "I40E_AQ_RC_ERANGE";
164 case I40E_AQ_RC_EFLUSHED:
165 return "I40E_AQ_RC_EFLUSHED";
166 case I40E_AQ_RC_BAD_ADDR:
167 return "I40E_AQ_RC_BAD_ADDR";
168 case I40E_AQ_RC_EMODE:
169 return "I40E_AQ_RC_EMODE";
170 case I40E_AQ_RC_EFBIG:
171 return "I40E_AQ_RC_EFBIG";
174 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
179 * i40e_stat_str - convert status err code to a string
180 * @hw: pointer to the HW structure
181 * @stat_err: the status error code to convert
183 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
189 return "I40E_ERR_NVM";
190 case I40E_ERR_NVM_CHECKSUM:
191 return "I40E_ERR_NVM_CHECKSUM";
193 return "I40E_ERR_PHY";
194 case I40E_ERR_CONFIG:
195 return "I40E_ERR_CONFIG";
197 return "I40E_ERR_PARAM";
198 case I40E_ERR_MAC_TYPE:
199 return "I40E_ERR_MAC_TYPE";
200 case I40E_ERR_UNKNOWN_PHY:
201 return "I40E_ERR_UNKNOWN_PHY";
202 case I40E_ERR_LINK_SETUP:
203 return "I40E_ERR_LINK_SETUP";
204 case I40E_ERR_ADAPTER_STOPPED:
205 return "I40E_ERR_ADAPTER_STOPPED";
206 case I40E_ERR_INVALID_MAC_ADDR:
207 return "I40E_ERR_INVALID_MAC_ADDR";
208 case I40E_ERR_DEVICE_NOT_SUPPORTED:
209 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
210 case I40E_ERR_MASTER_REQUESTS_PENDING:
211 return "I40E_ERR_MASTER_REQUESTS_PENDING";
212 case I40E_ERR_INVALID_LINK_SETTINGS:
213 return "I40E_ERR_INVALID_LINK_SETTINGS";
214 case I40E_ERR_AUTONEG_NOT_COMPLETE:
215 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
216 case I40E_ERR_RESET_FAILED:
217 return "I40E_ERR_RESET_FAILED";
218 case I40E_ERR_SWFW_SYNC:
219 return "I40E_ERR_SWFW_SYNC";
220 case I40E_ERR_NO_AVAILABLE_VSI:
221 return "I40E_ERR_NO_AVAILABLE_VSI";
222 case I40E_ERR_NO_MEMORY:
223 return "I40E_ERR_NO_MEMORY";
224 case I40E_ERR_BAD_PTR:
225 return "I40E_ERR_BAD_PTR";
226 case I40E_ERR_RING_FULL:
227 return "I40E_ERR_RING_FULL";
228 case I40E_ERR_INVALID_PD_ID:
229 return "I40E_ERR_INVALID_PD_ID";
230 case I40E_ERR_INVALID_QP_ID:
231 return "I40E_ERR_INVALID_QP_ID";
232 case I40E_ERR_INVALID_CQ_ID:
233 return "I40E_ERR_INVALID_CQ_ID";
234 case I40E_ERR_INVALID_CEQ_ID:
235 return "I40E_ERR_INVALID_CEQ_ID";
236 case I40E_ERR_INVALID_AEQ_ID:
237 return "I40E_ERR_INVALID_AEQ_ID";
238 case I40E_ERR_INVALID_SIZE:
239 return "I40E_ERR_INVALID_SIZE";
240 case I40E_ERR_INVALID_ARP_INDEX:
241 return "I40E_ERR_INVALID_ARP_INDEX";
242 case I40E_ERR_INVALID_FPM_FUNC_ID:
243 return "I40E_ERR_INVALID_FPM_FUNC_ID";
244 case I40E_ERR_QP_INVALID_MSG_SIZE:
245 return "I40E_ERR_QP_INVALID_MSG_SIZE";
246 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
247 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
248 case I40E_ERR_INVALID_FRAG_COUNT:
249 return "I40E_ERR_INVALID_FRAG_COUNT";
250 case I40E_ERR_QUEUE_EMPTY:
251 return "I40E_ERR_QUEUE_EMPTY";
252 case I40E_ERR_INVALID_ALIGNMENT:
253 return "I40E_ERR_INVALID_ALIGNMENT";
254 case I40E_ERR_FLUSHED_QUEUE:
255 return "I40E_ERR_FLUSHED_QUEUE";
256 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
257 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
258 case I40E_ERR_INVALID_IMM_DATA_SIZE:
259 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
260 case I40E_ERR_TIMEOUT:
261 return "I40E_ERR_TIMEOUT";
262 case I40E_ERR_OPCODE_MISMATCH:
263 return "I40E_ERR_OPCODE_MISMATCH";
264 case I40E_ERR_CQP_COMPL_ERROR:
265 return "I40E_ERR_CQP_COMPL_ERROR";
266 case I40E_ERR_INVALID_VF_ID:
267 return "I40E_ERR_INVALID_VF_ID";
268 case I40E_ERR_INVALID_HMCFN_ID:
269 return "I40E_ERR_INVALID_HMCFN_ID";
270 case I40E_ERR_BACKING_PAGE_ERROR:
271 return "I40E_ERR_BACKING_PAGE_ERROR";
272 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
273 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
274 case I40E_ERR_INVALID_PBLE_INDEX:
275 return "I40E_ERR_INVALID_PBLE_INDEX";
276 case I40E_ERR_INVALID_SD_INDEX:
277 return "I40E_ERR_INVALID_SD_INDEX";
278 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
279 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
280 case I40E_ERR_INVALID_SD_TYPE:
281 return "I40E_ERR_INVALID_SD_TYPE";
282 case I40E_ERR_MEMCPY_FAILED:
283 return "I40E_ERR_MEMCPY_FAILED";
284 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
285 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
286 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
287 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
288 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
289 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
290 case I40E_ERR_SRQ_ENABLED:
291 return "I40E_ERR_SRQ_ENABLED";
292 case I40E_ERR_ADMIN_QUEUE_ERROR:
293 return "I40E_ERR_ADMIN_QUEUE_ERROR";
294 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
295 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
296 case I40E_ERR_BUF_TOO_SHORT:
297 return "I40E_ERR_BUF_TOO_SHORT";
298 case I40E_ERR_ADMIN_QUEUE_FULL:
299 return "I40E_ERR_ADMIN_QUEUE_FULL";
300 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
301 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
302 case I40E_ERR_BAD_IWARP_CQE:
303 return "I40E_ERR_BAD_IWARP_CQE";
304 case I40E_ERR_NVM_BLANK_MODE:
305 return "I40E_ERR_NVM_BLANK_MODE";
306 case I40E_ERR_NOT_IMPLEMENTED:
307 return "I40E_ERR_NOT_IMPLEMENTED";
308 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
309 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
310 case I40E_ERR_DIAG_TEST_FAILED:
311 return "I40E_ERR_DIAG_TEST_FAILED";
312 case I40E_ERR_NOT_READY:
313 return "I40E_ERR_NOT_READY";
314 case I40E_NOT_SUPPORTED:
315 return "I40E_NOT_SUPPORTED";
316 case I40E_ERR_FIRMWARE_API_VERSION:
317 return "I40E_ERR_FIRMWARE_API_VERSION";
320 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
324 #endif /* I40E_NDIS_SUPPORT */
327 * @hw: debug mask related to admin queue
329 * @desc: pointer to admin queue descriptor
330 * @buffer: pointer to command buffer
331 * @buf_len: max length of buffer
333 * Dumps debug log about adminq command with descriptor contents.
335 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
336 void *buffer, u16 buf_len)
338 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
339 u16 len = LE16_TO_CPU(aq_desc->datalen);
340 u8 *buf = (u8 *)buffer;
343 if ((!(mask & hw->debug_mask)) || (desc == NULL))
347 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
348 LE16_TO_CPU(aq_desc->opcode),
349 LE16_TO_CPU(aq_desc->flags),
350 LE16_TO_CPU(aq_desc->datalen),
351 LE16_TO_CPU(aq_desc->retval));
352 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
353 LE32_TO_CPU(aq_desc->cookie_high),
354 LE32_TO_CPU(aq_desc->cookie_low));
355 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
356 LE32_TO_CPU(aq_desc->params.internal.param0),
357 LE32_TO_CPU(aq_desc->params.internal.param1));
358 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
359 LE32_TO_CPU(aq_desc->params.external.addr_high),
360 LE32_TO_CPU(aq_desc->params.external.addr_low));
362 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
363 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
366 /* write the full 16-byte chunks */
367 for (i = 0; i < (len - 16); i += 16)
369 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
370 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
371 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
372 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
373 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
374 /* the most we could have left is 16 bytes, pad with zeros */
380 memset(d_buf, 0, sizeof(d_buf));
381 for (j = 0; i < len; j++, i++)
384 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
385 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
386 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
387 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
388 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
394 * i40e_check_asq_alive
395 * @hw: pointer to the hw struct
397 * Returns true if Queue is enabled else false.
399 bool i40e_check_asq_alive(struct i40e_hw *hw)
405 return !!(rd32(hw, hw->aq.asq.len) &
406 I40E_PF_ATQLEN_ATQENABLE_MASK);
408 return !!(rd32(hw, hw->aq.asq.len) &
409 I40E_PF_ATQLEN_ATQENABLE_MASK);
410 #endif /* INTEGRATED_VF */
411 #endif /* PF_DRIVER */
415 return !!(rd32(hw, hw->aq.asq.len) &
416 I40E_VF_ATQLEN1_ATQENABLE_MASK);
418 return !!(rd32(hw, hw->aq.asq.len) &
419 I40E_VF_ATQLEN1_ATQENABLE_MASK);
420 #endif /* INTEGRATED_VF */
421 #endif /* VF_DRIVER */
426 * i40e_aq_queue_shutdown
427 * @hw: pointer to the hw struct
428 * @unloading: is the driver unloading itself
430 * Tell the Firmware that we're shutting down the AdminQ and whether
431 * or not the driver is unloading as well.
433 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
436 struct i40e_aq_desc desc;
437 struct i40e_aqc_queue_shutdown *cmd =
438 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
439 enum i40e_status_code status;
441 i40e_fill_default_direct_cmd_desc(&desc,
442 i40e_aqc_opc_queue_shutdown);
445 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
446 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
453 * i40e_aq_get_set_rss_lut
454 * @hw: pointer to the hardware structure
455 * @vsi_id: vsi fw index
456 * @pf_lut: for PF table set true, for VSI table set false
457 * @lut: pointer to the lut buffer provided by the caller
458 * @lut_size: size of the lut buffer
459 * @set: set true to set the table, false to get the table
461 * Internal function to get or set RSS look up table
463 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
464 u16 vsi_id, bool pf_lut,
465 u8 *lut, u16 lut_size,
468 enum i40e_status_code status;
469 struct i40e_aq_desc desc;
470 struct i40e_aqc_get_set_rss_lut *cmd_resp =
471 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
474 i40e_fill_default_direct_cmd_desc(&desc,
475 i40e_aqc_opc_set_rss_lut);
477 i40e_fill_default_direct_cmd_desc(&desc,
478 i40e_aqc_opc_get_rss_lut);
480 /* Indirect command */
481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
482 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
485 CPU_TO_LE16((u16)((vsi_id <<
486 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
487 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
488 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
491 cmd_resp->flags |= CPU_TO_LE16((u16)
492 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
493 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
494 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
496 cmd_resp->flags |= CPU_TO_LE16((u16)
497 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
498 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
499 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
501 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
507 * i40e_aq_get_rss_lut
508 * @hw: pointer to the hardware structure
509 * @vsi_id: vsi fw index
510 * @pf_lut: for PF table set true, for VSI table set false
511 * @lut: pointer to the lut buffer provided by the caller
512 * @lut_size: size of the lut buffer
514 * get the RSS lookup table, PF or VSI type
516 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
517 bool pf_lut, u8 *lut, u16 lut_size)
519 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
524 * i40e_aq_set_rss_lut
525 * @hw: pointer to the hardware structure
526 * @vsi_id: vsi fw index
527 * @pf_lut: for PF table set true, for VSI table set false
528 * @lut: pointer to the lut buffer provided by the caller
529 * @lut_size: size of the lut buffer
531 * set the RSS lookup table, PF or VSI type
533 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
534 bool pf_lut, u8 *lut, u16 lut_size)
536 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
540 * i40e_aq_get_set_rss_key
541 * @hw: pointer to the hw struct
542 * @vsi_id: vsi fw index
543 * @key: pointer to key info struct
544 * @set: set true to set the key, false to get the key
546 * get the RSS key per VSI
548 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
550 struct i40e_aqc_get_set_rss_key_data *key,
553 enum i40e_status_code status;
554 struct i40e_aq_desc desc;
555 struct i40e_aqc_get_set_rss_key *cmd_resp =
556 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
557 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
560 i40e_fill_default_direct_cmd_desc(&desc,
561 i40e_aqc_opc_set_rss_key);
563 i40e_fill_default_direct_cmd_desc(&desc,
564 i40e_aqc_opc_get_rss_key);
566 /* Indirect command */
567 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
568 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
571 CPU_TO_LE16((u16)((vsi_id <<
572 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
573 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
574 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
576 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
582 * i40e_aq_get_rss_key
583 * @hw: pointer to the hw struct
584 * @vsi_id: vsi fw index
585 * @key: pointer to key info struct
588 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
590 struct i40e_aqc_get_set_rss_key_data *key)
592 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
596 * i40e_aq_set_rss_key
597 * @hw: pointer to the hw struct
598 * @vsi_id: vsi fw index
599 * @key: pointer to key info struct
601 * set the RSS key per VSI
603 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
605 struct i40e_aqc_get_set_rss_key_data *key)
607 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
609 #endif /* X722_SUPPORT */
611 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
612 * hardware to a bit-field that can be used by SW to more easily determine the
615 * Macros are used to shorten the table lines and make this table human
618 * We store the PTYPE in the top byte of the bit field - this is just so that
619 * we can check that the table doesn't have a row missing, as the index into
620 * the table should be the PTYPE.
624 * IF NOT i40e_ptype_lookup[ptype].known
627 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
628 * Use the rest of the fields to look at the tunnels, inner protocols, etc
630 * Use the enum i40e_rx_l2_ptype to decode the packet type
634 /* macro to make the table lines short */
635 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
638 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
639 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
640 I40E_RX_PTYPE_##OUTER_FRAG, \
641 I40E_RX_PTYPE_TUNNEL_##T, \
642 I40E_RX_PTYPE_TUNNEL_END_##TE, \
643 I40E_RX_PTYPE_##TEF, \
644 I40E_RX_PTYPE_INNER_PROT_##I, \
645 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
647 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
648 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
650 /* shorter macros makes the table fit but are terse */
651 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
652 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
653 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
655 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
656 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
657 /* L2 Packet types */
658 I40E_PTT_UNUSED_ENTRY(0),
659 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
660 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
661 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT_UNUSED_ENTRY(4),
663 I40E_PTT_UNUSED_ENTRY(5),
664 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
666 I40E_PTT_UNUSED_ENTRY(8),
667 I40E_PTT_UNUSED_ENTRY(9),
668 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
669 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
670 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
681 /* Non Tunneled IPv4 */
682 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
683 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
684 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
685 I40E_PTT_UNUSED_ENTRY(25),
686 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
687 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
688 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
691 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
692 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
693 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
694 I40E_PTT_UNUSED_ENTRY(32),
695 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
696 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
697 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
700 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
701 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
702 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
703 I40E_PTT_UNUSED_ENTRY(39),
704 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
705 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
706 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
708 /* IPv4 --> GRE/NAT */
709 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
711 /* IPv4 --> GRE/NAT --> IPv4 */
712 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
713 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
714 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
715 I40E_PTT_UNUSED_ENTRY(47),
716 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
717 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
718 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
720 /* IPv4 --> GRE/NAT --> IPv6 */
721 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
722 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
723 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
724 I40E_PTT_UNUSED_ENTRY(54),
725 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
726 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
727 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
729 /* IPv4 --> GRE/NAT --> MAC */
730 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
732 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
733 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
734 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
735 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
736 I40E_PTT_UNUSED_ENTRY(62),
737 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
738 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
739 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
741 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
742 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
743 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
744 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
745 I40E_PTT_UNUSED_ENTRY(69),
746 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
747 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
748 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
750 /* IPv4 --> GRE/NAT --> MAC/VLAN */
751 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
753 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
754 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
755 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
756 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
757 I40E_PTT_UNUSED_ENTRY(77),
758 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
759 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
760 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
762 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
763 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
764 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
765 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
766 I40E_PTT_UNUSED_ENTRY(84),
767 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
768 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
769 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
771 /* Non Tunneled IPv6 */
772 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
773 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
774 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
775 I40E_PTT_UNUSED_ENTRY(91),
776 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
777 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
778 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
781 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
782 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
783 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
784 I40E_PTT_UNUSED_ENTRY(98),
785 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
786 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
787 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
790 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
791 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
792 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
793 I40E_PTT_UNUSED_ENTRY(105),
794 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
795 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
796 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
798 /* IPv6 --> GRE/NAT */
799 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
801 /* IPv6 --> GRE/NAT -> IPv4 */
802 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
803 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
804 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
805 I40E_PTT_UNUSED_ENTRY(113),
806 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
807 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
808 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
810 /* IPv6 --> GRE/NAT -> IPv6 */
811 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
812 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
813 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
814 I40E_PTT_UNUSED_ENTRY(120),
815 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
816 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
817 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
819 /* IPv6 --> GRE/NAT -> MAC */
820 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
822 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
823 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
824 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
825 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
826 I40E_PTT_UNUSED_ENTRY(128),
827 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
828 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
829 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
831 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
832 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
833 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
834 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
835 I40E_PTT_UNUSED_ENTRY(135),
836 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
837 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
838 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
840 /* IPv6 --> GRE/NAT -> MAC/VLAN */
841 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
843 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
844 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
845 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
846 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
847 I40E_PTT_UNUSED_ENTRY(143),
848 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
849 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
850 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
852 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
853 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
854 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
855 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
856 I40E_PTT_UNUSED_ENTRY(150),
857 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
858 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
859 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
862 I40E_PTT_UNUSED_ENTRY(154),
863 I40E_PTT_UNUSED_ENTRY(155),
864 I40E_PTT_UNUSED_ENTRY(156),
865 I40E_PTT_UNUSED_ENTRY(157),
866 I40E_PTT_UNUSED_ENTRY(158),
867 I40E_PTT_UNUSED_ENTRY(159),
869 I40E_PTT_UNUSED_ENTRY(160),
870 I40E_PTT_UNUSED_ENTRY(161),
871 I40E_PTT_UNUSED_ENTRY(162),
872 I40E_PTT_UNUSED_ENTRY(163),
873 I40E_PTT_UNUSED_ENTRY(164),
874 I40E_PTT_UNUSED_ENTRY(165),
875 I40E_PTT_UNUSED_ENTRY(166),
876 I40E_PTT_UNUSED_ENTRY(167),
877 I40E_PTT_UNUSED_ENTRY(168),
878 I40E_PTT_UNUSED_ENTRY(169),
880 I40E_PTT_UNUSED_ENTRY(170),
881 I40E_PTT_UNUSED_ENTRY(171),
882 I40E_PTT_UNUSED_ENTRY(172),
883 I40E_PTT_UNUSED_ENTRY(173),
884 I40E_PTT_UNUSED_ENTRY(174),
885 I40E_PTT_UNUSED_ENTRY(175),
886 I40E_PTT_UNUSED_ENTRY(176),
887 I40E_PTT_UNUSED_ENTRY(177),
888 I40E_PTT_UNUSED_ENTRY(178),
889 I40E_PTT_UNUSED_ENTRY(179),
891 I40E_PTT_UNUSED_ENTRY(180),
892 I40E_PTT_UNUSED_ENTRY(181),
893 I40E_PTT_UNUSED_ENTRY(182),
894 I40E_PTT_UNUSED_ENTRY(183),
895 I40E_PTT_UNUSED_ENTRY(184),
896 I40E_PTT_UNUSED_ENTRY(185),
897 I40E_PTT_UNUSED_ENTRY(186),
898 I40E_PTT_UNUSED_ENTRY(187),
899 I40E_PTT_UNUSED_ENTRY(188),
900 I40E_PTT_UNUSED_ENTRY(189),
902 I40E_PTT_UNUSED_ENTRY(190),
903 I40E_PTT_UNUSED_ENTRY(191),
904 I40E_PTT_UNUSED_ENTRY(192),
905 I40E_PTT_UNUSED_ENTRY(193),
906 I40E_PTT_UNUSED_ENTRY(194),
907 I40E_PTT_UNUSED_ENTRY(195),
908 I40E_PTT_UNUSED_ENTRY(196),
909 I40E_PTT_UNUSED_ENTRY(197),
910 I40E_PTT_UNUSED_ENTRY(198),
911 I40E_PTT_UNUSED_ENTRY(199),
913 I40E_PTT_UNUSED_ENTRY(200),
914 I40E_PTT_UNUSED_ENTRY(201),
915 I40E_PTT_UNUSED_ENTRY(202),
916 I40E_PTT_UNUSED_ENTRY(203),
917 I40E_PTT_UNUSED_ENTRY(204),
918 I40E_PTT_UNUSED_ENTRY(205),
919 I40E_PTT_UNUSED_ENTRY(206),
920 I40E_PTT_UNUSED_ENTRY(207),
921 I40E_PTT_UNUSED_ENTRY(208),
922 I40E_PTT_UNUSED_ENTRY(209),
924 I40E_PTT_UNUSED_ENTRY(210),
925 I40E_PTT_UNUSED_ENTRY(211),
926 I40E_PTT_UNUSED_ENTRY(212),
927 I40E_PTT_UNUSED_ENTRY(213),
928 I40E_PTT_UNUSED_ENTRY(214),
929 I40E_PTT_UNUSED_ENTRY(215),
930 I40E_PTT_UNUSED_ENTRY(216),
931 I40E_PTT_UNUSED_ENTRY(217),
932 I40E_PTT_UNUSED_ENTRY(218),
933 I40E_PTT_UNUSED_ENTRY(219),
935 I40E_PTT_UNUSED_ENTRY(220),
936 I40E_PTT_UNUSED_ENTRY(221),
937 I40E_PTT_UNUSED_ENTRY(222),
938 I40E_PTT_UNUSED_ENTRY(223),
939 I40E_PTT_UNUSED_ENTRY(224),
940 I40E_PTT_UNUSED_ENTRY(225),
941 I40E_PTT_UNUSED_ENTRY(226),
942 I40E_PTT_UNUSED_ENTRY(227),
943 I40E_PTT_UNUSED_ENTRY(228),
944 I40E_PTT_UNUSED_ENTRY(229),
946 I40E_PTT_UNUSED_ENTRY(230),
947 I40E_PTT_UNUSED_ENTRY(231),
948 I40E_PTT_UNUSED_ENTRY(232),
949 I40E_PTT_UNUSED_ENTRY(233),
950 I40E_PTT_UNUSED_ENTRY(234),
951 I40E_PTT_UNUSED_ENTRY(235),
952 I40E_PTT_UNUSED_ENTRY(236),
953 I40E_PTT_UNUSED_ENTRY(237),
954 I40E_PTT_UNUSED_ENTRY(238),
955 I40E_PTT_UNUSED_ENTRY(239),
957 I40E_PTT_UNUSED_ENTRY(240),
958 I40E_PTT_UNUSED_ENTRY(241),
959 I40E_PTT_UNUSED_ENTRY(242),
960 I40E_PTT_UNUSED_ENTRY(243),
961 I40E_PTT_UNUSED_ENTRY(244),
962 I40E_PTT_UNUSED_ENTRY(245),
963 I40E_PTT_UNUSED_ENTRY(246),
964 I40E_PTT_UNUSED_ENTRY(247),
965 I40E_PTT_UNUSED_ENTRY(248),
966 I40E_PTT_UNUSED_ENTRY(249),
968 I40E_PTT_UNUSED_ENTRY(250),
969 I40E_PTT_UNUSED_ENTRY(251),
970 I40E_PTT_UNUSED_ENTRY(252),
971 I40E_PTT_UNUSED_ENTRY(253),
972 I40E_PTT_UNUSED_ENTRY(254),
973 I40E_PTT_UNUSED_ENTRY(255)
978 * i40e_validate_mac_addr - Validate unicast MAC address
979 * @mac_addr: pointer to MAC address
981 * Tests a MAC address to ensure it is a valid Individual Address
983 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
985 enum i40e_status_code status = I40E_SUCCESS;
987 DEBUGFUNC("i40e_validate_mac_addr");
989 /* Broadcast addresses ARE multicast addresses
990 * Make sure it is not a multicast address
991 * Reject the zero address
993 if (I40E_IS_MULTICAST(mac_addr) ||
994 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
995 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
996 status = I40E_ERR_INVALID_MAC_ADDR;
1003 * i40e_init_shared_code - Initialize the shared code
1004 * @hw: pointer to hardware structure
1006 * This assigns the MAC type and PHY code and inits the NVM.
1007 * Does not touch the hardware. This function must be called prior to any
1008 * other function in the shared code. The i40e_hw structure should be
1009 * memset to 0 prior to calling this function. The following fields in
1010 * hw structure should be filled in prior to calling this function:
1011 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1012 * subsystem_vendor_id, and revision_id
1014 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1016 enum i40e_status_code status = I40E_SUCCESS;
1017 u32 port, ari, func_rid;
1019 DEBUGFUNC("i40e_init_shared_code");
1021 i40e_set_mac_type(hw);
1023 switch (hw->mac.type) {
1024 case I40E_MAC_XL710:
1030 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1033 hw->phy.get_link_info = true;
1035 /* Determine port number and PF number*/
1036 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1037 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1038 hw->port = (u8)port;
1039 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1040 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1041 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1043 hw->pf_id = (u8)(func_rid & 0xff);
1045 hw->pf_id = (u8)(func_rid & 0x7);
1048 if (hw->mac.type == I40E_MAC_X722)
1049 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1052 status = i40e_init_nvm(hw);
1057 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1058 * @hw: pointer to the hw struct
1059 * @flags: a return indicator of what addresses were added to the addr store
1060 * @addrs: the requestor's mac addr store
1061 * @cmd_details: pointer to command details structure or NULL
1063 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1065 struct i40e_aqc_mac_address_read_data *addrs,
1066 struct i40e_asq_cmd_details *cmd_details)
1068 struct i40e_aq_desc desc;
1069 struct i40e_aqc_mac_address_read *cmd_data =
1070 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1071 enum i40e_status_code status;
1073 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1074 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1076 status = i40e_asq_send_command(hw, &desc, addrs,
1077 sizeof(*addrs), cmd_details);
1078 *flags = LE16_TO_CPU(cmd_data->command_flags);
1084 * i40e_aq_mac_address_write - Change the MAC addresses
1085 * @hw: pointer to the hw struct
1086 * @flags: indicates which MAC to be written
1087 * @mac_addr: address to write
1088 * @cmd_details: pointer to command details structure or NULL
1090 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1091 u16 flags, u8 *mac_addr,
1092 struct i40e_asq_cmd_details *cmd_details)
1094 struct i40e_aq_desc desc;
1095 struct i40e_aqc_mac_address_write *cmd_data =
1096 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1097 enum i40e_status_code status;
1099 i40e_fill_default_direct_cmd_desc(&desc,
1100 i40e_aqc_opc_mac_address_write);
1101 cmd_data->command_flags = CPU_TO_LE16(flags);
1102 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1103 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1104 ((u32)mac_addr[3] << 16) |
1105 ((u32)mac_addr[4] << 8) |
1108 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1114 * i40e_get_mac_addr - get MAC address
1115 * @hw: pointer to the HW structure
1116 * @mac_addr: pointer to MAC address
1118 * Reads the adapter's MAC address from register
1120 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1122 struct i40e_aqc_mac_address_read_data addrs;
1123 enum i40e_status_code status;
1126 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1128 if (flags & I40E_AQC_LAN_ADDR_VALID)
1129 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1135 * i40e_get_port_mac_addr - get Port MAC address
1136 * @hw: pointer to the HW structure
1137 * @mac_addr: pointer to Port MAC address
1139 * Reads the adapter's Port MAC address
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1143 struct i40e_aqc_mac_address_read_data addrs;
1144 enum i40e_status_code status;
1147 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1151 if (flags & I40E_AQC_PORT_ADDR_VALID)
1152 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1154 status = I40E_ERR_INVALID_MAC_ADDR;
1160 * i40e_pre_tx_queue_cfg - pre tx queue configure
1161 * @hw: pointer to the HW structure
1162 * @queue: target pf queue index
1163 * @enable: state change request
1165 * Handles hw requirement to indicate intention to enable
1166 * or disable target queue.
1168 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1170 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1174 if (abs_queue_idx >= 128) {
1175 reg_block = abs_queue_idx / 128;
1176 abs_queue_idx %= 128;
1179 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1180 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1181 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1184 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1186 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1188 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1192 * i40e_get_san_mac_addr - get SAN MAC address
1193 * @hw: pointer to the HW structure
1194 * @mac_addr: pointer to SAN MAC address
1196 * Reads the adapter's SAN MAC address from NVM
1198 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1201 struct i40e_aqc_mac_address_read_data addrs;
1202 enum i40e_status_code status;
1205 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1209 if (flags & I40E_AQC_SAN_ADDR_VALID)
1210 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
1212 status = I40E_ERR_INVALID_MAC_ADDR;
1218 * i40e_read_pba_string - Reads part number string from EEPROM
1219 * @hw: pointer to hardware structure
1220 * @pba_num: stores the part number string from the EEPROM
1221 * @pba_num_size: part number string buffer length
1223 * Reads the part number string from the EEPROM.
1225 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1228 enum i40e_status_code status = I40E_SUCCESS;
1234 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1235 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1236 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1240 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1241 if (status != I40E_SUCCESS) {
1242 DEBUGOUT("Failed to read PBA Block pointer.\n");
1246 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1247 if (status != I40E_SUCCESS) {
1248 DEBUGOUT("Failed to read PBA Block size.\n");
1252 /* Subtract one to get PBA word count (PBA Size word is included in
1256 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1257 DEBUGOUT("Buffer to small for PBA data.\n");
1258 return I40E_ERR_PARAM;
1261 for (i = 0; i < pba_size; i++) {
1262 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1263 if (status != I40E_SUCCESS) {
1264 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1268 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1269 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1271 pba_num[(pba_size * 2)] = '\0';
1277 * i40e_get_media_type - Gets media type
1278 * @hw: pointer to the hardware structure
1280 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1282 enum i40e_media_type media;
1284 switch (hw->phy.link_info.phy_type) {
1285 case I40E_PHY_TYPE_10GBASE_SR:
1286 case I40E_PHY_TYPE_10GBASE_LR:
1287 case I40E_PHY_TYPE_1000BASE_SX:
1288 case I40E_PHY_TYPE_1000BASE_LX:
1289 case I40E_PHY_TYPE_40GBASE_SR4:
1290 case I40E_PHY_TYPE_40GBASE_LR4:
1291 case I40E_PHY_TYPE_25GBASE_LR:
1292 case I40E_PHY_TYPE_25GBASE_SR:
1293 media = I40E_MEDIA_TYPE_FIBER;
1295 case I40E_PHY_TYPE_100BASE_TX:
1296 case I40E_PHY_TYPE_1000BASE_T:
1297 case I40E_PHY_TYPE_10GBASE_T:
1298 media = I40E_MEDIA_TYPE_BASET;
1300 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1301 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1302 case I40E_PHY_TYPE_10GBASE_CR1:
1303 case I40E_PHY_TYPE_40GBASE_CR4:
1304 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1305 case I40E_PHY_TYPE_40GBASE_AOC:
1306 case I40E_PHY_TYPE_10GBASE_AOC:
1307 case I40E_PHY_TYPE_25GBASE_CR:
1308 media = I40E_MEDIA_TYPE_DA;
1310 case I40E_PHY_TYPE_1000BASE_KX:
1311 case I40E_PHY_TYPE_10GBASE_KX4:
1312 case I40E_PHY_TYPE_10GBASE_KR:
1313 case I40E_PHY_TYPE_40GBASE_KR4:
1314 case I40E_PHY_TYPE_20GBASE_KR2:
1315 case I40E_PHY_TYPE_25GBASE_KR:
1316 media = I40E_MEDIA_TYPE_BACKPLANE;
1318 case I40E_PHY_TYPE_SGMII:
1319 case I40E_PHY_TYPE_XAUI:
1320 case I40E_PHY_TYPE_XFI:
1321 case I40E_PHY_TYPE_XLAUI:
1322 case I40E_PHY_TYPE_XLPPI:
1324 media = I40E_MEDIA_TYPE_UNKNOWN;
1331 #define I40E_PF_RESET_WAIT_COUNT 200
1333 * i40e_pf_reset - Reset the PF
1334 * @hw: pointer to the hardware structure
1336 * Assuming someone else has triggered a global reset,
1337 * assure the global reset is complete and then reset the PF
1339 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1346 /* Poll for Global Reset steady state in case of recent GRST.
1347 * The grst delay value is in 100ms units, and we'll wait a
1348 * couple counts longer to be sure we don't just miss the end.
1350 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1351 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1352 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1354 grst_del = grst_del * 20;
1356 for (cnt = 0; cnt < grst_del; cnt++) {
1357 reg = rd32(hw, I40E_GLGEN_RSTAT);
1358 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1360 i40e_msec_delay(100);
1362 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1363 DEBUGOUT("Global reset polling failed to complete.\n");
1364 return I40E_ERR_RESET_FAILED;
1367 /* Now Wait for the FW to be ready */
1368 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1369 reg = rd32(hw, I40E_GLNVM_ULD);
1370 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1372 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1374 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1377 i40e_msec_delay(10);
1379 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1380 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1381 DEBUGOUT("wait for FW Reset complete timedout\n");
1382 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1383 return I40E_ERR_RESET_FAILED;
1386 /* If there was a Global Reset in progress when we got here,
1387 * we don't need to do the PF Reset
1390 reg = rd32(hw, I40E_PFGEN_CTRL);
1391 wr32(hw, I40E_PFGEN_CTRL,
1392 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1393 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1394 reg = rd32(hw, I40E_PFGEN_CTRL);
1395 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1399 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1400 DEBUGOUT("PF reset polling failed to complete.\n");
1401 return I40E_ERR_RESET_FAILED;
1405 i40e_clear_pxe_mode(hw);
1408 return I40E_SUCCESS;
1412 * i40e_clear_hw - clear out any left over hw state
1413 * @hw: pointer to the hw struct
1415 * Clear queues and interrupts, typically called at init time,
1416 * but after the capabilities have been found so we know how many
1417 * queues and msix vectors have been allocated.
1419 void i40e_clear_hw(struct i40e_hw *hw)
1421 u32 num_queues, base_queue;
1429 /* get number of interrupts, queues, and vfs */
1430 val = rd32(hw, I40E_GLPCI_CNF2);
1431 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1432 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1433 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1434 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1436 val = rd32(hw, I40E_PFLAN_QALLOC);
1437 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1438 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1439 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1440 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1441 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1442 num_queues = (j - base_queue) + 1;
1446 val = rd32(hw, I40E_PF_VT_PFALLOC);
1447 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1448 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1449 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1450 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1451 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1452 num_vfs = (j - i) + 1;
1456 /* stop all the interrupts */
1457 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1458 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1459 for (i = 0; i < num_pf_int - 2; i++)
1460 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1462 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1463 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1464 wr32(hw, I40E_PFINT_LNKLST0, val);
1465 for (i = 0; i < num_pf_int - 2; i++)
1466 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1467 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1468 for (i = 0; i < num_vfs; i++)
1469 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1470 for (i = 0; i < num_vf_int - 2; i++)
1471 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1473 /* warn the HW of the coming Tx disables */
1474 for (i = 0; i < num_queues; i++) {
1475 u32 abs_queue_idx = base_queue + i;
1478 if (abs_queue_idx >= 128) {
1479 reg_block = abs_queue_idx / 128;
1480 abs_queue_idx %= 128;
1483 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1484 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1485 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1486 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1488 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1490 i40e_usec_delay(400);
1492 /* stop all the queues */
1493 for (i = 0; i < num_queues; i++) {
1494 wr32(hw, I40E_QINT_TQCTL(i), 0);
1495 wr32(hw, I40E_QTX_ENA(i), 0);
1496 wr32(hw, I40E_QINT_RQCTL(i), 0);
1497 wr32(hw, I40E_QRX_ENA(i), 0);
1500 /* short wait for all queue disables to settle */
1501 i40e_usec_delay(50);
1505 * i40e_clear_pxe_mode - clear pxe operations mode
1506 * @hw: pointer to the hw struct
1508 * Make sure all PXE mode settings are cleared, including things
1509 * like descriptor fetch/write-back mode.
1511 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1513 if (i40e_check_asq_alive(hw))
1514 i40e_aq_clear_pxe_mode(hw, NULL);
1518 * i40e_led_is_mine - helper to find matching led
1519 * @hw: pointer to the hw struct
1520 * @idx: index into GPIO registers
1522 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1524 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1529 if (!hw->func_caps.led[idx])
1532 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1533 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1534 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1536 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1537 * if it is not our port then ignore
1539 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1546 #define I40E_COMBINED_ACTIVITY 0xA
1547 #define I40E_FILTER_ACTIVITY 0xE
1548 #define I40E_LINK_ACTIVITY 0xC
1549 #define I40E_MAC_ACTIVITY 0xD
1550 #define I40E_LED0 22
1553 * i40e_led_get - return current on/off mode
1554 * @hw: pointer to the hw struct
1556 * The value returned is the 'mode' field as defined in the
1557 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1558 * values are variations of possible behaviors relating to
1559 * blink, link, and wire.
1561 u32 i40e_led_get(struct i40e_hw *hw)
1563 u32 current_mode = 0;
1567 /* as per the documentation GPIO 22-29 are the LED
1568 * GPIO pins named LED0..LED7
1570 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1571 u32 gpio_val = i40e_led_is_mine(hw, i);
1576 /* ignore gpio LED src mode entries related to the activity
1579 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1580 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1581 switch (current_mode) {
1582 case I40E_COMBINED_ACTIVITY:
1583 case I40E_FILTER_ACTIVITY:
1584 case I40E_MAC_ACTIVITY:
1590 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1599 * i40e_led_set - set new on/off mode
1600 * @hw: pointer to the hw struct
1601 * @mode: 0=off, 0xf=on (else see manual for mode details)
1602 * @blink: true if the LED should blink when on, false if steady
1604 * if this function is used to turn on the blink it should
1605 * be used to disable the blink when restoring the original state.
1607 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1609 u32 current_mode = 0;
1612 if (mode & 0xfffffff0)
1613 DEBUGOUT1("invalid mode passed in %X\n", mode);
1615 /* as per the documentation GPIO 22-29 are the LED
1616 * GPIO pins named LED0..LED7
1618 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1619 u32 gpio_val = i40e_led_is_mine(hw, i);
1624 /* ignore gpio LED src mode entries related to the activity
1627 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1628 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1629 switch (current_mode) {
1630 case I40E_COMBINED_ACTIVITY:
1631 case I40E_FILTER_ACTIVITY:
1632 case I40E_MAC_ACTIVITY:
1638 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1639 /* this & is a bit of paranoia, but serves as a range check */
1640 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1641 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1643 if (mode == I40E_LINK_ACTIVITY)
1647 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1649 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1651 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1656 /* Admin command wrappers */
1659 * i40e_aq_get_phy_capabilities
1660 * @hw: pointer to the hw struct
1661 * @abilities: structure for PHY capabilities to be filled
1662 * @qualified_modules: report Qualified Modules
1663 * @report_init: report init capabilities (active are default)
1664 * @cmd_details: pointer to command details structure or NULL
1666 * Returns the various PHY abilities supported on the Port.
1668 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1669 bool qualified_modules, bool report_init,
1670 struct i40e_aq_get_phy_abilities_resp *abilities,
1671 struct i40e_asq_cmd_details *cmd_details)
1673 struct i40e_aq_desc desc;
1674 enum i40e_status_code status;
1675 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1678 return I40E_ERR_PARAM;
1680 i40e_fill_default_direct_cmd_desc(&desc,
1681 i40e_aqc_opc_get_phy_abilities);
1683 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1684 if (abilities_size > I40E_AQ_LARGE_BUF)
1685 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1687 if (qualified_modules)
1688 desc.params.external.param0 |=
1689 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1692 desc.params.external.param0 |=
1693 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1695 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1698 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1699 status = I40E_ERR_UNKNOWN_PHY;
1702 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1703 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1710 * i40e_aq_set_phy_config
1711 * @hw: pointer to the hw struct
1712 * @config: structure with PHY configuration to be set
1713 * @cmd_details: pointer to command details structure or NULL
1715 * Set the various PHY configuration parameters
1716 * supported on the Port.One or more of the Set PHY config parameters may be
1717 * ignored in an MFP mode as the PF may not have the privilege to set some
1718 * of the PHY Config parameters. This status will be indicated by the
1721 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1722 struct i40e_aq_set_phy_config *config,
1723 struct i40e_asq_cmd_details *cmd_details)
1725 struct i40e_aq_desc desc;
1726 struct i40e_aq_set_phy_config *cmd =
1727 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1728 enum i40e_status_code status;
1731 return I40E_ERR_PARAM;
1733 i40e_fill_default_direct_cmd_desc(&desc,
1734 i40e_aqc_opc_set_phy_config);
1738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1745 * @hw: pointer to the hw struct
1747 * Set the requested flow control mode using set_phy_config.
1749 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1750 bool atomic_restart)
1752 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1753 struct i40e_aq_get_phy_abilities_resp abilities;
1754 struct i40e_aq_set_phy_config config;
1755 enum i40e_status_code status;
1756 u8 pause_mask = 0x0;
1762 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1763 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1765 case I40E_FC_RX_PAUSE:
1766 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1768 case I40E_FC_TX_PAUSE:
1769 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1775 /* Get the current phy config */
1776 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1779 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1783 memset(&config, 0, sizeof(config));
1784 /* clear the old pause settings */
1785 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1786 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1787 /* set the new abilities */
1788 config.abilities |= pause_mask;
1789 /* If the abilities have changed, then set the new config */
1790 if (config.abilities != abilities.abilities) {
1791 /* Auto restart link so settings take effect */
1793 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794 /* Copy over all the old settings */
1795 config.phy_type = abilities.phy_type;
1796 config.phy_type_ext = abilities.phy_type_ext;
1797 config.link_speed = abilities.link_speed;
1798 config.eee_capability = abilities.eee_capability;
1799 config.eeer = abilities.eeer_val;
1800 config.low_power_ctrl = abilities.d3_lpan;
1801 status = i40e_aq_set_phy_config(hw, &config, NULL);
1804 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1806 /* Update the link info */
1807 status = i40e_update_link_info(hw);
1809 /* Wait a little bit (on 40G cards it sometimes takes a really
1810 * long time for link to come back from the atomic reset)
1813 i40e_msec_delay(1000);
1814 status = i40e_update_link_info(hw);
1817 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1823 * i40e_aq_set_mac_config
1824 * @hw: pointer to the hw struct
1825 * @max_frame_size: Maximum Frame Size to be supported by the port
1826 * @crc_en: Tell HW to append a CRC to outgoing frames
1827 * @pacing: Pacing configurations
1828 * @cmd_details: pointer to command details structure or NULL
1830 * Configure MAC settings for frame size, jumbo frame support and the
1831 * addition of a CRC by the hardware.
1833 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1835 bool crc_en, u16 pacing,
1836 struct i40e_asq_cmd_details *cmd_details)
1838 struct i40e_aq_desc desc;
1839 struct i40e_aq_set_mac_config *cmd =
1840 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1841 enum i40e_status_code status;
1843 if (max_frame_size == 0)
1844 return I40E_ERR_PARAM;
1846 i40e_fill_default_direct_cmd_desc(&desc,
1847 i40e_aqc_opc_set_mac_config);
1849 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1850 cmd->params = ((u8)pacing & 0x0F) << 3;
1852 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1854 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1860 * i40e_aq_clear_pxe_mode
1861 * @hw: pointer to the hw struct
1862 * @cmd_details: pointer to command details structure or NULL
1864 * Tell the firmware that the driver is taking over from PXE
1866 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1867 struct i40e_asq_cmd_details *cmd_details)
1869 enum i40e_status_code status;
1870 struct i40e_aq_desc desc;
1871 struct i40e_aqc_clear_pxe *cmd =
1872 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1874 i40e_fill_default_direct_cmd_desc(&desc,
1875 i40e_aqc_opc_clear_pxe_mode);
1879 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1881 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1887 * i40e_aq_set_link_restart_an
1888 * @hw: pointer to the hw struct
1889 * @enable_link: if true: enable link, if false: disable link
1890 * @cmd_details: pointer to command details structure or NULL
1892 * Sets up the link and restarts the Auto-Negotiation over the link.
1894 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1895 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1897 struct i40e_aq_desc desc;
1898 struct i40e_aqc_set_link_restart_an *cmd =
1899 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1900 enum i40e_status_code status;
1902 i40e_fill_default_direct_cmd_desc(&desc,
1903 i40e_aqc_opc_set_link_restart_an);
1905 cmd->command = I40E_AQ_PHY_RESTART_AN;
1907 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1909 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1911 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1917 * i40e_aq_get_link_info
1918 * @hw: pointer to the hw struct
1919 * @enable_lse: enable/disable LinkStatusEvent reporting
1920 * @link: pointer to link status structure - optional
1921 * @cmd_details: pointer to command details structure or NULL
1923 * Returns the link status of the adapter.
1925 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1926 bool enable_lse, struct i40e_link_status *link,
1927 struct i40e_asq_cmd_details *cmd_details)
1929 struct i40e_aq_desc desc;
1930 struct i40e_aqc_get_link_status *resp =
1931 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1932 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1933 enum i40e_status_code status;
1934 bool tx_pause, rx_pause;
1937 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1940 command_flags = I40E_AQ_LSE_ENABLE;
1942 command_flags = I40E_AQ_LSE_DISABLE;
1943 resp->command_flags = CPU_TO_LE16(command_flags);
1945 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1947 if (status != I40E_SUCCESS)
1948 goto aq_get_link_info_exit;
1950 /* save off old link status information */
1951 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1952 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1954 /* update link status */
1955 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1956 hw->phy.media_type = i40e_get_media_type(hw);
1957 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1958 hw_link_info->link_info = resp->link_info;
1959 hw_link_info->an_info = resp->an_info;
1960 hw_link_info->ext_info = resp->ext_info;
1961 hw_link_info->loopback = resp->loopback;
1962 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1963 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1965 /* update fc info */
1966 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1967 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1968 if (tx_pause & rx_pause)
1969 hw->fc.current_mode = I40E_FC_FULL;
1971 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1973 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1975 hw->fc.current_mode = I40E_FC_NONE;
1977 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1978 hw_link_info->crc_enable = true;
1980 hw_link_info->crc_enable = false;
1982 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1983 hw_link_info->lse_enable = true;
1985 hw_link_info->lse_enable = false;
1987 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1988 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1989 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1991 /* save link status information */
1993 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1994 I40E_NONDMA_TO_NONDMA);
1996 /* flag cleared so helper functions don't call AQ again */
1997 hw->phy.get_link_info = false;
1999 aq_get_link_info_exit:
2004 * i40e_aq_set_phy_int_mask
2005 * @hw: pointer to the hw struct
2006 * @mask: interrupt mask to be set
2007 * @cmd_details: pointer to command details structure or NULL
2009 * Set link interrupt mask.
2011 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2013 struct i40e_asq_cmd_details *cmd_details)
2015 struct i40e_aq_desc desc;
2016 struct i40e_aqc_set_phy_int_mask *cmd =
2017 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2018 enum i40e_status_code status;
2020 i40e_fill_default_direct_cmd_desc(&desc,
2021 i40e_aqc_opc_set_phy_int_mask);
2023 cmd->event_mask = CPU_TO_LE16(mask);
2025 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2031 * i40e_aq_get_local_advt_reg
2032 * @hw: pointer to the hw struct
2033 * @advt_reg: local AN advertisement register value
2034 * @cmd_details: pointer to command details structure or NULL
2036 * Get the Local AN advertisement register value.
2038 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2040 struct i40e_asq_cmd_details *cmd_details)
2042 struct i40e_aq_desc desc;
2043 struct i40e_aqc_an_advt_reg *resp =
2044 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2045 enum i40e_status_code status;
2047 i40e_fill_default_direct_cmd_desc(&desc,
2048 i40e_aqc_opc_get_local_advt_reg);
2050 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2052 if (status != I40E_SUCCESS)
2053 goto aq_get_local_advt_reg_exit;
2055 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2056 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2058 aq_get_local_advt_reg_exit:
2063 * i40e_aq_set_local_advt_reg
2064 * @hw: pointer to the hw struct
2065 * @advt_reg: local AN advertisement register value
2066 * @cmd_details: pointer to command details structure or NULL
2068 * Get the Local AN advertisement register value.
2070 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2072 struct i40e_asq_cmd_details *cmd_details)
2074 struct i40e_aq_desc desc;
2075 struct i40e_aqc_an_advt_reg *cmd =
2076 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2077 enum i40e_status_code status;
2079 i40e_fill_default_direct_cmd_desc(&desc,
2080 i40e_aqc_opc_get_local_advt_reg);
2082 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2083 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2085 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2091 * i40e_aq_get_partner_advt
2092 * @hw: pointer to the hw struct
2093 * @advt_reg: AN partner advertisement register value
2094 * @cmd_details: pointer to command details structure or NULL
2096 * Get the link partner AN advertisement register value.
2098 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2100 struct i40e_asq_cmd_details *cmd_details)
2102 struct i40e_aq_desc desc;
2103 struct i40e_aqc_an_advt_reg *resp =
2104 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2105 enum i40e_status_code status;
2107 i40e_fill_default_direct_cmd_desc(&desc,
2108 i40e_aqc_opc_get_partner_advt);
2110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2112 if (status != I40E_SUCCESS)
2113 goto aq_get_partner_advt_exit;
2115 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2116 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2118 aq_get_partner_advt_exit:
2123 * i40e_aq_set_lb_modes
2124 * @hw: pointer to the hw struct
2125 * @lb_modes: loopback mode to be set
2126 * @cmd_details: pointer to command details structure or NULL
2128 * Sets loopback modes.
2130 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2132 struct i40e_asq_cmd_details *cmd_details)
2134 struct i40e_aq_desc desc;
2135 struct i40e_aqc_set_lb_mode *cmd =
2136 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2137 enum i40e_status_code status;
2139 i40e_fill_default_direct_cmd_desc(&desc,
2140 i40e_aqc_opc_set_lb_modes);
2142 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2150 * i40e_aq_set_phy_debug
2151 * @hw: pointer to the hw struct
2152 * @cmd_flags: debug command flags
2153 * @cmd_details: pointer to command details structure or NULL
2155 * Reset the external PHY.
2157 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2158 struct i40e_asq_cmd_details *cmd_details)
2160 struct i40e_aq_desc desc;
2161 struct i40e_aqc_set_phy_debug *cmd =
2162 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2163 enum i40e_status_code status;
2165 i40e_fill_default_direct_cmd_desc(&desc,
2166 i40e_aqc_opc_set_phy_debug);
2168 cmd->command_flags = cmd_flags;
2170 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2177 * @hw: pointer to the hw struct
2178 * @vsi_ctx: pointer to a vsi context struct
2179 * @cmd_details: pointer to command details structure or NULL
2181 * Add a VSI context to the hardware.
2183 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2184 struct i40e_vsi_context *vsi_ctx,
2185 struct i40e_asq_cmd_details *cmd_details)
2187 struct i40e_aq_desc desc;
2188 struct i40e_aqc_add_get_update_vsi *cmd =
2189 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2190 struct i40e_aqc_add_get_update_vsi_completion *resp =
2191 (struct i40e_aqc_add_get_update_vsi_completion *)
2193 enum i40e_status_code status;
2195 i40e_fill_default_direct_cmd_desc(&desc,
2196 i40e_aqc_opc_add_vsi);
2198 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2199 cmd->connection_type = vsi_ctx->connection_type;
2200 cmd->vf_id = vsi_ctx->vf_num;
2201 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2203 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2205 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2206 sizeof(vsi_ctx->info), cmd_details);
2208 if (status != I40E_SUCCESS)
2209 goto aq_add_vsi_exit;
2211 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2212 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2213 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2214 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2221 * i40e_aq_set_default_vsi
2222 * @hw: pointer to the hw struct
2224 * @cmd_details: pointer to command details structure or NULL
2226 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2228 struct i40e_asq_cmd_details *cmd_details)
2230 struct i40e_aq_desc desc;
2231 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2232 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2234 enum i40e_status_code status;
2236 i40e_fill_default_direct_cmd_desc(&desc,
2237 i40e_aqc_opc_set_vsi_promiscuous_modes);
2239 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2240 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2241 cmd->seid = CPU_TO_LE16(seid);
2243 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2249 * i40e_aq_clear_default_vsi
2250 * @hw: pointer to the hw struct
2252 * @cmd_details: pointer to command details structure or NULL
2254 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2256 struct i40e_asq_cmd_details *cmd_details)
2258 struct i40e_aq_desc desc;
2259 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2260 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2262 enum i40e_status_code status;
2264 i40e_fill_default_direct_cmd_desc(&desc,
2265 i40e_aqc_opc_set_vsi_promiscuous_modes);
2267 cmd->promiscuous_flags = CPU_TO_LE16(0);
2268 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2269 cmd->seid = CPU_TO_LE16(seid);
2271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2277 * i40e_aq_set_vsi_unicast_promiscuous
2278 * @hw: pointer to the hw struct
2280 * @set: set unicast promiscuous enable/disable
2281 * @cmd_details: pointer to command details structure or NULL
2282 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2284 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2286 struct i40e_asq_cmd_details *cmd_details,
2287 bool rx_only_promisc)
2289 struct i40e_aq_desc desc;
2290 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2291 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2292 enum i40e_status_code status;
2295 i40e_fill_default_direct_cmd_desc(&desc,
2296 i40e_aqc_opc_set_vsi_promiscuous_modes);
2299 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2300 if (rx_only_promisc &&
2301 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2302 (hw->aq.api_maj_ver > 1)))
2303 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2306 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2308 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2309 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2310 (hw->aq.api_maj_ver > 1))
2311 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2313 cmd->seid = CPU_TO_LE16(seid);
2314 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2320 * i40e_aq_set_vsi_multicast_promiscuous
2321 * @hw: pointer to the hw struct
2323 * @set: set multicast promiscuous enable/disable
2324 * @cmd_details: pointer to command details structure or NULL
2326 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2327 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2329 struct i40e_aq_desc desc;
2330 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2331 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2332 enum i40e_status_code status;
2335 i40e_fill_default_direct_cmd_desc(&desc,
2336 i40e_aqc_opc_set_vsi_promiscuous_modes);
2339 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2341 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2343 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2345 cmd->seid = CPU_TO_LE16(seid);
2346 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2352 * i40e_aq_set_vsi_mc_promisc_on_vlan
2353 * @hw: pointer to the hw struct
2355 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2356 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2357 * @cmd_details: pointer to command details structure or NULL
2359 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2360 u16 seid, bool enable, u16 vid,
2361 struct i40e_asq_cmd_details *cmd_details)
2363 struct i40e_aq_desc desc;
2364 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2365 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2366 enum i40e_status_code status;
2369 i40e_fill_default_direct_cmd_desc(&desc,
2370 i40e_aqc_opc_set_vsi_promiscuous_modes);
2373 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2375 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2376 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2377 cmd->seid = CPU_TO_LE16(seid);
2378 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2380 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2386 * i40e_aq_set_vsi_uc_promisc_on_vlan
2387 * @hw: pointer to the hw struct
2389 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2390 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2391 * @cmd_details: pointer to command details structure or NULL
2393 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2394 u16 seid, bool enable, u16 vid,
2395 struct i40e_asq_cmd_details *cmd_details)
2397 struct i40e_aq_desc desc;
2398 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2399 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2400 enum i40e_status_code status;
2403 i40e_fill_default_direct_cmd_desc(&desc,
2404 i40e_aqc_opc_set_vsi_promiscuous_modes);
2407 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2409 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2410 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2411 cmd->seid = CPU_TO_LE16(seid);
2412 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2414 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2420 * i40e_aq_set_vsi_broadcast
2421 * @hw: pointer to the hw struct
2423 * @set_filter: true to set filter, false to clear filter
2424 * @cmd_details: pointer to command details structure or NULL
2426 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2428 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2429 u16 seid, bool set_filter,
2430 struct i40e_asq_cmd_details *cmd_details)
2432 struct i40e_aq_desc desc;
2433 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2434 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2435 enum i40e_status_code status;
2437 i40e_fill_default_direct_cmd_desc(&desc,
2438 i40e_aqc_opc_set_vsi_promiscuous_modes);
2441 cmd->promiscuous_flags
2442 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2444 cmd->promiscuous_flags
2445 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2447 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2448 cmd->seid = CPU_TO_LE16(seid);
2449 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2455 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2456 * @hw: pointer to the hw struct
2458 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2459 * @cmd_details: pointer to command details structure or NULL
2461 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2462 u16 seid, bool enable,
2463 struct i40e_asq_cmd_details *cmd_details)
2465 struct i40e_aq_desc desc;
2466 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2467 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2468 enum i40e_status_code status;
2471 i40e_fill_default_direct_cmd_desc(&desc,
2472 i40e_aqc_opc_set_vsi_promiscuous_modes);
2474 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2476 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2477 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2478 cmd->seid = CPU_TO_LE16(seid);
2480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2486 * i40e_get_vsi_params - get VSI configuration info
2487 * @hw: pointer to the hw struct
2488 * @vsi_ctx: pointer to a vsi context struct
2489 * @cmd_details: pointer to command details structure or NULL
2491 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2492 struct i40e_vsi_context *vsi_ctx,
2493 struct i40e_asq_cmd_details *cmd_details)
2495 struct i40e_aq_desc desc;
2496 struct i40e_aqc_add_get_update_vsi *cmd =
2497 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2498 struct i40e_aqc_add_get_update_vsi_completion *resp =
2499 (struct i40e_aqc_add_get_update_vsi_completion *)
2501 enum i40e_status_code status;
2503 UNREFERENCED_1PARAMETER(cmd_details);
2504 i40e_fill_default_direct_cmd_desc(&desc,
2505 i40e_aqc_opc_get_vsi_parameters);
2507 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2509 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2511 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2512 sizeof(vsi_ctx->info), NULL);
2514 if (status != I40E_SUCCESS)
2515 goto aq_get_vsi_params_exit;
2517 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2518 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2519 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2520 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2522 aq_get_vsi_params_exit:
2527 * i40e_aq_update_vsi_params
2528 * @hw: pointer to the hw struct
2529 * @vsi_ctx: pointer to a vsi context struct
2530 * @cmd_details: pointer to command details structure or NULL
2532 * Update a VSI context.
2534 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2535 struct i40e_vsi_context *vsi_ctx,
2536 struct i40e_asq_cmd_details *cmd_details)
2538 struct i40e_aq_desc desc;
2539 struct i40e_aqc_add_get_update_vsi *cmd =
2540 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2541 struct i40e_aqc_add_get_update_vsi_completion *resp =
2542 (struct i40e_aqc_add_get_update_vsi_completion *)
2544 enum i40e_status_code status;
2546 i40e_fill_default_direct_cmd_desc(&desc,
2547 i40e_aqc_opc_update_vsi_parameters);
2548 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2550 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2552 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2553 sizeof(vsi_ctx->info), cmd_details);
2555 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2556 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2562 * i40e_aq_get_switch_config
2563 * @hw: pointer to the hardware structure
2564 * @buf: pointer to the result buffer
2565 * @buf_size: length of input buffer
2566 * @start_seid: seid to start for the report, 0 == beginning
2567 * @cmd_details: pointer to command details structure or NULL
2569 * Fill the buf with switch configuration returned from AdminQ command
2571 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2572 struct i40e_aqc_get_switch_config_resp *buf,
2573 u16 buf_size, u16 *start_seid,
2574 struct i40e_asq_cmd_details *cmd_details)
2576 struct i40e_aq_desc desc;
2577 struct i40e_aqc_switch_seid *scfg =
2578 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2579 enum i40e_status_code status;
2581 i40e_fill_default_direct_cmd_desc(&desc,
2582 i40e_aqc_opc_get_switch_config);
2583 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2584 if (buf_size > I40E_AQ_LARGE_BUF)
2585 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2586 scfg->seid = CPU_TO_LE16(*start_seid);
2588 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2589 *start_seid = LE16_TO_CPU(scfg->seid);
2595 * i40e_aq_set_switch_config
2596 * @hw: pointer to the hardware structure
2597 * @flags: bit flag values to set
2598 * @valid_flags: which bit flags to set
2599 * @cmd_details: pointer to command details structure or NULL
2601 * Set switch configuration bits
2603 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2604 u16 flags, u16 valid_flags,
2605 struct i40e_asq_cmd_details *cmd_details)
2607 struct i40e_aq_desc desc;
2608 struct i40e_aqc_set_switch_config *scfg =
2609 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2610 enum i40e_status_code status;
2612 i40e_fill_default_direct_cmd_desc(&desc,
2613 i40e_aqc_opc_set_switch_config);
2614 scfg->flags = CPU_TO_LE16(flags);
2615 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2617 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2623 * i40e_aq_get_firmware_version
2624 * @hw: pointer to the hw struct
2625 * @fw_major_version: firmware major version
2626 * @fw_minor_version: firmware minor version
2627 * @fw_build: firmware build number
2628 * @api_major_version: major queue version
2629 * @api_minor_version: minor queue version
2630 * @cmd_details: pointer to command details structure or NULL
2632 * Get the firmware version from the admin queue commands
2634 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2635 u16 *fw_major_version, u16 *fw_minor_version,
2637 u16 *api_major_version, u16 *api_minor_version,
2638 struct i40e_asq_cmd_details *cmd_details)
2640 struct i40e_aq_desc desc;
2641 struct i40e_aqc_get_version *resp =
2642 (struct i40e_aqc_get_version *)&desc.params.raw;
2643 enum i40e_status_code status;
2645 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2647 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2649 if (status == I40E_SUCCESS) {
2650 if (fw_major_version != NULL)
2651 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2652 if (fw_minor_version != NULL)
2653 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2654 if (fw_build != NULL)
2655 *fw_build = LE32_TO_CPU(resp->fw_build);
2656 if (api_major_version != NULL)
2657 *api_major_version = LE16_TO_CPU(resp->api_major);
2658 if (api_minor_version != NULL)
2659 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2661 /* A workaround to fix the API version in SW */
2662 if (api_major_version && api_minor_version &&
2663 fw_major_version && fw_minor_version &&
2664 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2665 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2666 (*fw_major_version > 4)))
2667 *api_minor_version = 2;
2674 * i40e_aq_send_driver_version
2675 * @hw: pointer to the hw struct
2676 * @dv: driver's major, minor version
2677 * @cmd_details: pointer to command details structure or NULL
2679 * Send the driver version to the firmware
2681 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2682 struct i40e_driver_version *dv,
2683 struct i40e_asq_cmd_details *cmd_details)
2685 struct i40e_aq_desc desc;
2686 struct i40e_aqc_driver_version *cmd =
2687 (struct i40e_aqc_driver_version *)&desc.params.raw;
2688 enum i40e_status_code status;
2692 return I40E_ERR_PARAM;
2694 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2696 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2697 cmd->driver_major_ver = dv->major_version;
2698 cmd->driver_minor_ver = dv->minor_version;
2699 cmd->driver_build_ver = dv->build_version;
2700 cmd->driver_subbuild_ver = dv->subbuild_version;
2703 while (len < sizeof(dv->driver_string) &&
2704 (dv->driver_string[len] < 0x80) &&
2705 dv->driver_string[len])
2707 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2714 * i40e_get_link_status - get status of the HW network link
2715 * @hw: pointer to the hw struct
2716 * @link_up: pointer to bool (true/false = linkup/linkdown)
2718 * Variable link_up true if link is up, false if link is down.
2719 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2721 * Side effect: LinkStatusEvent reporting becomes enabled
2723 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2725 enum i40e_status_code status = I40E_SUCCESS;
2727 if (hw->phy.get_link_info) {
2728 status = i40e_update_link_info(hw);
2730 if (status != I40E_SUCCESS)
2731 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2735 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2741 * i40e_updatelink_status - update status of the HW network link
2742 * @hw: pointer to the hw struct
2744 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2746 struct i40e_aq_get_phy_abilities_resp abilities;
2747 enum i40e_status_code status = I40E_SUCCESS;
2749 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2753 /* extra checking needed to ensure link info to user is timely */
2754 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2755 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2756 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2757 status = i40e_aq_get_phy_capabilities(hw, false, false,
2762 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2763 sizeof(hw->phy.link_info.module_type));
2770 * i40e_get_link_speed
2771 * @hw: pointer to the hw struct
2773 * Returns the link speed of the adapter.
2775 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2777 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2778 enum i40e_status_code status = I40E_SUCCESS;
2780 if (hw->phy.get_link_info) {
2781 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2783 if (status != I40E_SUCCESS)
2784 goto i40e_link_speed_exit;
2787 speed = hw->phy.link_info.link_speed;
2789 i40e_link_speed_exit:
2794 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2795 * @hw: pointer to the hw struct
2796 * @uplink_seid: the MAC or other gizmo SEID
2797 * @downlink_seid: the VSI SEID
2798 * @enabled_tc: bitmap of TCs to be enabled
2799 * @default_port: true for default port VSI, false for control port
2800 * @veb_seid: pointer to where to put the resulting VEB SEID
2801 * @enable_stats: true to turn on VEB stats
2802 * @cmd_details: pointer to command details structure or NULL
2804 * This asks the FW to add a VEB between the uplink and downlink
2805 * elements. If the uplink SEID is 0, this will be a floating VEB.
2807 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2808 u16 downlink_seid, u8 enabled_tc,
2809 bool default_port, u16 *veb_seid,
2811 struct i40e_asq_cmd_details *cmd_details)
2813 struct i40e_aq_desc desc;
2814 struct i40e_aqc_add_veb *cmd =
2815 (struct i40e_aqc_add_veb *)&desc.params.raw;
2816 struct i40e_aqc_add_veb_completion *resp =
2817 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2818 enum i40e_status_code status;
2821 /* SEIDs need to either both be set or both be 0 for floating VEB */
2822 if (!!uplink_seid != !!downlink_seid)
2823 return I40E_ERR_PARAM;
2825 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2827 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2828 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2829 cmd->enable_tcs = enabled_tc;
2831 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2833 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2835 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2837 /* reverse logic here: set the bitflag to disable the stats */
2839 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2841 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2843 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2845 if (!status && veb_seid)
2846 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2852 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2853 * @hw: pointer to the hw struct
2854 * @veb_seid: the SEID of the VEB to query
2855 * @switch_id: the uplink switch id
2856 * @floating: set to true if the VEB is floating
2857 * @statistic_index: index of the stats counter block for this VEB
2858 * @vebs_used: number of VEB's used by function
2859 * @vebs_free: total VEB's not reserved by any function
2860 * @cmd_details: pointer to command details structure or NULL
2862 * This retrieves the parameters for a particular VEB, specified by
2863 * uplink_seid, and returns them to the caller.
2865 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2866 u16 veb_seid, u16 *switch_id,
2867 bool *floating, u16 *statistic_index,
2868 u16 *vebs_used, u16 *vebs_free,
2869 struct i40e_asq_cmd_details *cmd_details)
2871 struct i40e_aq_desc desc;
2872 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2873 (struct i40e_aqc_get_veb_parameters_completion *)
2875 enum i40e_status_code status;
2878 return I40E_ERR_PARAM;
2880 i40e_fill_default_direct_cmd_desc(&desc,
2881 i40e_aqc_opc_get_veb_parameters);
2882 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2884 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2889 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2890 if (statistic_index)
2891 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2893 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2895 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2897 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2899 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2910 * i40e_aq_add_macvlan
2911 * @hw: pointer to the hw struct
2912 * @seid: VSI for the mac address
2913 * @mv_list: list of macvlans to be added
2914 * @count: length of the list
2915 * @cmd_details: pointer to command details structure or NULL
2917 * Add MAC/VLAN addresses to the HW filtering
2919 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2920 struct i40e_aqc_add_macvlan_element_data *mv_list,
2921 u16 count, struct i40e_asq_cmd_details *cmd_details)
2923 struct i40e_aq_desc desc;
2924 struct i40e_aqc_macvlan *cmd =
2925 (struct i40e_aqc_macvlan *)&desc.params.raw;
2926 enum i40e_status_code status;
2930 if (count == 0 || !mv_list || !hw)
2931 return I40E_ERR_PARAM;
2933 buf_size = count * sizeof(*mv_list);
2935 /* prep the rest of the request */
2936 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2937 cmd->num_addresses = CPU_TO_LE16(count);
2938 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2942 for (i = 0; i < count; i++)
2943 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2945 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2947 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2948 if (buf_size > I40E_AQ_LARGE_BUF)
2949 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2951 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2958 * i40e_aq_remove_macvlan
2959 * @hw: pointer to the hw struct
2960 * @seid: VSI for the mac address
2961 * @mv_list: list of macvlans to be removed
2962 * @count: length of the list
2963 * @cmd_details: pointer to command details structure or NULL
2965 * Remove MAC/VLAN addresses from the HW filtering
2967 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2968 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2969 u16 count, struct i40e_asq_cmd_details *cmd_details)
2971 struct i40e_aq_desc desc;
2972 struct i40e_aqc_macvlan *cmd =
2973 (struct i40e_aqc_macvlan *)&desc.params.raw;
2974 enum i40e_status_code status;
2977 if (count == 0 || !mv_list || !hw)
2978 return I40E_ERR_PARAM;
2980 buf_size = count * sizeof(*mv_list);
2982 /* prep the rest of the request */
2983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2984 cmd->num_addresses = CPU_TO_LE16(count);
2985 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2989 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2990 if (buf_size > I40E_AQ_LARGE_BUF)
2991 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2993 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3000 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3001 * @hw: pointer to the hw struct
3002 * @opcode: AQ opcode for add or delete mirror rule
3003 * @sw_seid: Switch SEID (to which rule refers)
3004 * @rule_type: Rule Type (ingress/egress/VLAN)
3005 * @id: Destination VSI SEID or Rule ID
3006 * @count: length of the list
3007 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3008 * @cmd_details: pointer to command details structure or NULL
3009 * @rule_id: Rule ID returned from FW
3010 * @rule_used: Number of rules used in internal switch
3011 * @rule_free: Number of rules free in internal switch
3013 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3014 * VEBs/VEPA elements only
3016 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3017 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3018 u16 count, __le16 *mr_list,
3019 struct i40e_asq_cmd_details *cmd_details,
3020 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3022 struct i40e_aq_desc desc;
3023 struct i40e_aqc_add_delete_mirror_rule *cmd =
3024 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3025 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3026 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3027 enum i40e_status_code status;
3030 buf_size = count * sizeof(*mr_list);
3032 /* prep the rest of the request */
3033 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3034 cmd->seid = CPU_TO_LE16(sw_seid);
3035 cmd->rule_type = CPU_TO_LE16(rule_type &
3036 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3037 cmd->num_entries = CPU_TO_LE16(count);
3038 /* Dest VSI for add, rule_id for delete */
3039 cmd->destination = CPU_TO_LE16(id);
3041 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3043 if (buf_size > I40E_AQ_LARGE_BUF)
3044 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3047 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3049 if (status == I40E_SUCCESS ||
3050 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3052 *rule_id = LE16_TO_CPU(resp->rule_id);
3054 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3056 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3062 * i40e_aq_add_mirrorrule - add a mirror rule
3063 * @hw: pointer to the hw struct
3064 * @sw_seid: Switch SEID (to which rule refers)
3065 * @rule_type: Rule Type (ingress/egress/VLAN)
3066 * @dest_vsi: SEID of VSI to which packets will be mirrored
3067 * @count: length of the list
3068 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3069 * @cmd_details: pointer to command details structure or NULL
3070 * @rule_id: Rule ID returned from FW
3071 * @rule_used: Number of rules used in internal switch
3072 * @rule_free: Number of rules free in internal switch
3074 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3076 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3077 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3078 struct i40e_asq_cmd_details *cmd_details,
3079 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3081 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3082 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3083 if (count == 0 || !mr_list)
3084 return I40E_ERR_PARAM;
3087 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3088 rule_type, dest_vsi, count, mr_list,
3089 cmd_details, rule_id, rules_used, rules_free);
3093 * i40e_aq_delete_mirrorrule - delete a mirror rule
3094 * @hw: pointer to the hw struct
3095 * @sw_seid: Switch SEID (to which rule refers)
3096 * @rule_type: Rule Type (ingress/egress/VLAN)
3097 * @count: length of the list
3098 * @rule_id: Rule ID that is returned in the receive desc as part of
3100 * @mr_list: list of mirrored VLAN IDs to be removed
3101 * @cmd_details: pointer to command details structure or NULL
3102 * @rule_used: Number of rules used in internal switch
3103 * @rule_free: Number of rules free in internal switch
3105 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3107 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3108 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3109 struct i40e_asq_cmd_details *cmd_details,
3110 u16 *rules_used, u16 *rules_free)
3112 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3113 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3114 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3115 * mirroring. For other rule_type, count and rule_type should
3118 if (count == 0 || !mr_list)
3119 return I40E_ERR_PARAM;
3122 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3123 rule_type, rule_id, count, mr_list,
3124 cmd_details, NULL, rules_used, rules_free);
3128 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3129 * @hw: pointer to the hw struct
3130 * @seid: VSI for the vlan filters
3131 * @v_list: list of vlan filters to be added
3132 * @count: length of the list
3133 * @cmd_details: pointer to command details structure or NULL
3135 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3136 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3137 u8 count, struct i40e_asq_cmd_details *cmd_details)
3139 struct i40e_aq_desc desc;
3140 struct i40e_aqc_macvlan *cmd =
3141 (struct i40e_aqc_macvlan *)&desc.params.raw;
3142 enum i40e_status_code status;
3145 if (count == 0 || !v_list || !hw)
3146 return I40E_ERR_PARAM;
3148 buf_size = count * sizeof(*v_list);
3150 /* prep the rest of the request */
3151 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3152 cmd->num_addresses = CPU_TO_LE16(count);
3153 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3157 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3158 if (buf_size > I40E_AQ_LARGE_BUF)
3159 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3161 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3168 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3169 * @hw: pointer to the hw struct
3170 * @seid: VSI for the vlan filters
3171 * @v_list: list of macvlans to be removed
3172 * @count: length of the list
3173 * @cmd_details: pointer to command details structure or NULL
3175 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3176 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3177 u8 count, struct i40e_asq_cmd_details *cmd_details)
3179 struct i40e_aq_desc desc;
3180 struct i40e_aqc_macvlan *cmd =
3181 (struct i40e_aqc_macvlan *)&desc.params.raw;
3182 enum i40e_status_code status;
3185 if (count == 0 || !v_list || !hw)
3186 return I40E_ERR_PARAM;
3188 buf_size = count * sizeof(*v_list);
3190 /* prep the rest of the request */
3191 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3192 cmd->num_addresses = CPU_TO_LE16(count);
3193 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3197 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3198 if (buf_size > I40E_AQ_LARGE_BUF)
3199 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3201 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3208 * i40e_aq_send_msg_to_vf
3209 * @hw: pointer to the hardware structure
3210 * @vfid: vf id to send msg
3211 * @v_opcode: opcodes for VF-PF communication
3212 * @v_retval: return error code
3213 * @msg: pointer to the msg buffer
3214 * @msglen: msg length
3215 * @cmd_details: pointer to command details
3219 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3220 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3221 struct i40e_asq_cmd_details *cmd_details)
3223 struct i40e_aq_desc desc;
3224 struct i40e_aqc_pf_vf_message *cmd =
3225 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3226 enum i40e_status_code status;
3228 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3229 cmd->id = CPU_TO_LE32(vfid);
3230 desc.cookie_high = CPU_TO_LE32(v_opcode);
3231 desc.cookie_low = CPU_TO_LE32(v_retval);
3232 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3234 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3236 if (msglen > I40E_AQ_LARGE_BUF)
3237 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3238 desc.datalen = CPU_TO_LE16(msglen);
3240 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3246 * i40e_aq_debug_read_register
3247 * @hw: pointer to the hw struct
3248 * @reg_addr: register address
3249 * @reg_val: register value
3250 * @cmd_details: pointer to command details structure or NULL
3252 * Read the register using the admin queue commands
3254 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3255 u32 reg_addr, u64 *reg_val,
3256 struct i40e_asq_cmd_details *cmd_details)
3258 struct i40e_aq_desc desc;
3259 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3260 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3261 enum i40e_status_code status;
3263 if (reg_val == NULL)
3264 return I40E_ERR_PARAM;
3266 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3268 cmd_resp->address = CPU_TO_LE32(reg_addr);
3270 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3272 if (status == I40E_SUCCESS) {
3273 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3274 (u64)LE32_TO_CPU(cmd_resp->value_low);
3281 * i40e_aq_debug_write_register
3282 * @hw: pointer to the hw struct
3283 * @reg_addr: register address
3284 * @reg_val: register value
3285 * @cmd_details: pointer to command details structure or NULL
3287 * Write to a register using the admin queue commands
3289 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3290 u32 reg_addr, u64 reg_val,
3291 struct i40e_asq_cmd_details *cmd_details)
3293 struct i40e_aq_desc desc;
3294 struct i40e_aqc_debug_reg_read_write *cmd =
3295 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3296 enum i40e_status_code status;
3298 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3300 cmd->address = CPU_TO_LE32(reg_addr);
3301 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3302 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3304 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3310 * i40e_aq_request_resource
3311 * @hw: pointer to the hw struct
3312 * @resource: resource id
3313 * @access: access type
3314 * @sdp_number: resource number
3315 * @timeout: the maximum time in ms that the driver may hold the resource
3316 * @cmd_details: pointer to command details structure or NULL
3318 * requests common resource using the admin queue commands
3320 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3321 enum i40e_aq_resources_ids resource,
3322 enum i40e_aq_resource_access_type access,
3323 u8 sdp_number, u64 *timeout,
3324 struct i40e_asq_cmd_details *cmd_details)
3326 struct i40e_aq_desc desc;
3327 struct i40e_aqc_request_resource *cmd_resp =
3328 (struct i40e_aqc_request_resource *)&desc.params.raw;
3329 enum i40e_status_code status;
3331 DEBUGFUNC("i40e_aq_request_resource");
3333 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3335 cmd_resp->resource_id = CPU_TO_LE16(resource);
3336 cmd_resp->access_type = CPU_TO_LE16(access);
3337 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3339 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3340 /* The completion specifies the maximum time in ms that the driver
3341 * may hold the resource in the Timeout field.
3342 * If the resource is held by someone else, the command completes with
3343 * busy return value and the timeout field indicates the maximum time
3344 * the current owner of the resource has to free it.
3346 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3347 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3353 * i40e_aq_release_resource
3354 * @hw: pointer to the hw struct
3355 * @resource: resource id
3356 * @sdp_number: resource number
3357 * @cmd_details: pointer to command details structure or NULL
3359 * release common resource using the admin queue commands
3361 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3362 enum i40e_aq_resources_ids resource,
3364 struct i40e_asq_cmd_details *cmd_details)
3366 struct i40e_aq_desc desc;
3367 struct i40e_aqc_request_resource *cmd =
3368 (struct i40e_aqc_request_resource *)&desc.params.raw;
3369 enum i40e_status_code status;
3371 DEBUGFUNC("i40e_aq_release_resource");
3373 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3375 cmd->resource_id = CPU_TO_LE16(resource);
3376 cmd->resource_number = CPU_TO_LE32(sdp_number);
3378 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3385 * @hw: pointer to the hw struct
3386 * @module_pointer: module pointer location in words from the NVM beginning
3387 * @offset: byte offset from the module beginning
3388 * @length: length of the section to be read (in bytes from the offset)
3389 * @data: command buffer (size [bytes] = length)
3390 * @last_command: tells if this is the last command in a series
3391 * @cmd_details: pointer to command details structure or NULL
3393 * Read the NVM using the admin queue commands
3395 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3396 u32 offset, u16 length, void *data,
3398 struct i40e_asq_cmd_details *cmd_details)
3400 struct i40e_aq_desc desc;
3401 struct i40e_aqc_nvm_update *cmd =
3402 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3403 enum i40e_status_code status;
3405 DEBUGFUNC("i40e_aq_read_nvm");
3407 /* In offset the highest byte must be zeroed. */
3408 if (offset & 0xFF000000) {
3409 status = I40E_ERR_PARAM;
3410 goto i40e_aq_read_nvm_exit;
3413 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3415 /* If this is the last command in a series, set the proper flag. */
3417 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3418 cmd->module_pointer = module_pointer;
3419 cmd->offset = CPU_TO_LE32(offset);
3420 cmd->length = CPU_TO_LE16(length);
3422 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3423 if (length > I40E_AQ_LARGE_BUF)
3424 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3426 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3428 i40e_aq_read_nvm_exit:
3433 * i40e_aq_read_nvm_config - read an nvm config block
3434 * @hw: pointer to the hw struct
3435 * @cmd_flags: NVM access admin command bits
3436 * @field_id: field or feature id
3437 * @data: buffer for result
3438 * @buf_size: buffer size
3439 * @element_count: pointer to count of elements read by FW
3440 * @cmd_details: pointer to command details structure or NULL
3442 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3443 u8 cmd_flags, u32 field_id, void *data,
3444 u16 buf_size, u16 *element_count,
3445 struct i40e_asq_cmd_details *cmd_details)
3447 struct i40e_aq_desc desc;
3448 struct i40e_aqc_nvm_config_read *cmd =
3449 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3450 enum i40e_status_code status;
3452 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3453 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3454 if (buf_size > I40E_AQ_LARGE_BUF)
3455 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3457 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3458 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3459 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3460 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3462 cmd->element_id_msw = 0;
3464 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3466 if (!status && element_count)
3467 *element_count = LE16_TO_CPU(cmd->element_count);
3473 * i40e_aq_write_nvm_config - write an nvm config block
3474 * @hw: pointer to the hw struct
3475 * @cmd_flags: NVM access admin command bits
3476 * @data: buffer for result
3477 * @buf_size: buffer size
3478 * @element_count: count of elements to be written
3479 * @cmd_details: pointer to command details structure or NULL
3481 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3482 u8 cmd_flags, void *data, u16 buf_size,
3484 struct i40e_asq_cmd_details *cmd_details)
3486 struct i40e_aq_desc desc;
3487 struct i40e_aqc_nvm_config_write *cmd =
3488 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3489 enum i40e_status_code status;
3491 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3492 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3493 if (buf_size > I40E_AQ_LARGE_BUF)
3494 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3496 cmd->element_count = CPU_TO_LE16(element_count);
3497 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3498 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3504 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3505 * @hw: pointer to the hw struct
3506 * @cmd_details: pointer to command details structure or NULL
3508 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3509 void *buff, u16 buff_size,
3510 struct i40e_asq_cmd_details *cmd_details)
3512 struct i40e_aq_desc desc;
3513 enum i40e_status_code status;
3515 UNREFERENCED_2PARAMETER(buff, buff_size);
3517 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3518 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3519 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3520 status = I40E_ERR_NOT_IMPLEMENTED;
3527 * @hw: pointer to the hw struct
3528 * @module_pointer: module pointer location in words from the NVM beginning
3529 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3530 * @length: length of the section to be erased (expressed in 4 KB)
3531 * @last_command: tells if this is the last command in a series
3532 * @cmd_details: pointer to command details structure or NULL
3534 * Erase the NVM sector using the admin queue commands
3536 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3537 u32 offset, u16 length, bool last_command,
3538 struct i40e_asq_cmd_details *cmd_details)
3540 struct i40e_aq_desc desc;
3541 struct i40e_aqc_nvm_update *cmd =
3542 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3543 enum i40e_status_code status;
3545 DEBUGFUNC("i40e_aq_erase_nvm");
3547 /* In offset the highest byte must be zeroed. */
3548 if (offset & 0xFF000000) {
3549 status = I40E_ERR_PARAM;
3550 goto i40e_aq_erase_nvm_exit;
3553 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3555 /* If this is the last command in a series, set the proper flag. */
3557 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3558 cmd->module_pointer = module_pointer;
3559 cmd->offset = CPU_TO_LE32(offset);
3560 cmd->length = CPU_TO_LE16(length);
3562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3564 i40e_aq_erase_nvm_exit:
3569 * i40e_parse_discover_capabilities
3570 * @hw: pointer to the hw struct
3571 * @buff: pointer to a buffer containing device/function capability records
3572 * @cap_count: number of capability records in the list
3573 * @list_type_opc: type of capabilities list to parse
3575 * Parse the device/function capabilities list.
3577 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3579 enum i40e_admin_queue_opc list_type_opc)
3581 struct i40e_aqc_list_capabilities_element_resp *cap;
3582 u32 valid_functions, num_functions;
3583 u32 number, logical_id, phys_id;
3584 struct i40e_hw_capabilities *p;
3589 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3591 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3592 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3593 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3594 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3598 for (i = 0; i < cap_count; i++, cap++) {
3599 id = LE16_TO_CPU(cap->id);
3600 number = LE32_TO_CPU(cap->number);
3601 logical_id = LE32_TO_CPU(cap->logical_id);
3602 phys_id = LE32_TO_CPU(cap->phys_id);
3603 major_rev = cap->major_rev;
3606 case I40E_AQ_CAP_ID_SWITCH_MODE:
3607 p->switch_mode = number;
3608 i40e_debug(hw, I40E_DEBUG_INIT,
3609 "HW Capability: Switch mode = %d\n",
3612 case I40E_AQ_CAP_ID_MNG_MODE:
3613 p->management_mode = number;
3614 if (major_rev > 1) {
3615 p->mng_protocols_over_mctp = logical_id;
3616 i40e_debug(hw, I40E_DEBUG_INIT,
3617 "HW Capability: Protocols over MCTP = %d\n",
3618 p->mng_protocols_over_mctp);
3620 p->mng_protocols_over_mctp = 0;
3622 i40e_debug(hw, I40E_DEBUG_INIT,
3623 "HW Capability: Management Mode = %d\n",
3624 p->management_mode);
3626 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3627 p->npar_enable = number;
3628 i40e_debug(hw, I40E_DEBUG_INIT,
3629 "HW Capability: NPAR enable = %d\n",
3632 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3634 i40e_debug(hw, I40E_DEBUG_INIT,
3635 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3637 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3638 p->valid_functions = number;
3639 i40e_debug(hw, I40E_DEBUG_INIT,
3640 "HW Capability: Valid Functions = %d\n",
3641 p->valid_functions);
3643 case I40E_AQ_CAP_ID_SRIOV:
3645 p->sr_iov_1_1 = true;
3646 i40e_debug(hw, I40E_DEBUG_INIT,
3647 "HW Capability: SR-IOV = %d\n",
3650 case I40E_AQ_CAP_ID_VF:
3651 p->num_vfs = number;
3652 p->vf_base_id = logical_id;
3653 i40e_debug(hw, I40E_DEBUG_INIT,
3654 "HW Capability: VF count = %d\n",
3656 i40e_debug(hw, I40E_DEBUG_INIT,
3657 "HW Capability: VF base_id = %d\n",
3660 case I40E_AQ_CAP_ID_VMDQ:
3663 i40e_debug(hw, I40E_DEBUG_INIT,
3664 "HW Capability: VMDQ = %d\n", p->vmdq);
3666 case I40E_AQ_CAP_ID_8021QBG:
3668 p->evb_802_1_qbg = true;
3669 i40e_debug(hw, I40E_DEBUG_INIT,
3670 "HW Capability: 802.1Qbg = %d\n", number);
3672 case I40E_AQ_CAP_ID_8021QBR:
3674 p->evb_802_1_qbh = true;
3675 i40e_debug(hw, I40E_DEBUG_INIT,
3676 "HW Capability: 802.1Qbh = %d\n", number);
3678 case I40E_AQ_CAP_ID_VSI:
3679 p->num_vsis = number;
3680 i40e_debug(hw, I40E_DEBUG_INIT,
3681 "HW Capability: VSI count = %d\n",
3684 case I40E_AQ_CAP_ID_DCB:
3687 p->enabled_tcmap = logical_id;
3690 i40e_debug(hw, I40E_DEBUG_INIT,
3691 "HW Capability: DCB = %d\n", p->dcb);
3692 i40e_debug(hw, I40E_DEBUG_INIT,
3693 "HW Capability: TC Mapping = %d\n",
3695 i40e_debug(hw, I40E_DEBUG_INIT,
3696 "HW Capability: TC Max = %d\n", p->maxtc);
3698 case I40E_AQ_CAP_ID_FCOE:
3701 i40e_debug(hw, I40E_DEBUG_INIT,
3702 "HW Capability: FCOE = %d\n", p->fcoe);
3704 case I40E_AQ_CAP_ID_ISCSI:
3707 i40e_debug(hw, I40E_DEBUG_INIT,
3708 "HW Capability: iSCSI = %d\n", p->iscsi);
3710 case I40E_AQ_CAP_ID_RSS:
3712 p->rss_table_size = number;
3713 p->rss_table_entry_width = logical_id;
3714 i40e_debug(hw, I40E_DEBUG_INIT,
3715 "HW Capability: RSS = %d\n", p->rss);
3716 i40e_debug(hw, I40E_DEBUG_INIT,
3717 "HW Capability: RSS table size = %d\n",
3719 i40e_debug(hw, I40E_DEBUG_INIT,
3720 "HW Capability: RSS table width = %d\n",
3721 p->rss_table_entry_width);
3723 case I40E_AQ_CAP_ID_RXQ:
3724 p->num_rx_qp = number;
3725 p->base_queue = phys_id;
3726 i40e_debug(hw, I40E_DEBUG_INIT,
3727 "HW Capability: Rx QP = %d\n", number);
3728 i40e_debug(hw, I40E_DEBUG_INIT,
3729 "HW Capability: base_queue = %d\n",
3732 case I40E_AQ_CAP_ID_TXQ:
3733 p->num_tx_qp = number;
3734 p->base_queue = phys_id;
3735 i40e_debug(hw, I40E_DEBUG_INIT,
3736 "HW Capability: Tx QP = %d\n", number);
3737 i40e_debug(hw, I40E_DEBUG_INIT,
3738 "HW Capability: base_queue = %d\n",
3741 case I40E_AQ_CAP_ID_MSIX:
3742 p->num_msix_vectors = number;
3743 i40e_debug(hw, I40E_DEBUG_INIT,
3744 "HW Capability: MSIX vector count = %d\n",
3745 p->num_msix_vectors);
3747 case I40E_AQ_CAP_ID_VF_MSIX:
3748 p->num_msix_vectors_vf = number;
3749 i40e_debug(hw, I40E_DEBUG_INIT,
3750 "HW Capability: MSIX VF vector count = %d\n",
3751 p->num_msix_vectors_vf);
3753 case I40E_AQ_CAP_ID_FLEX10:
3754 if (major_rev == 1) {
3756 p->flex10_enable = true;
3757 p->flex10_capable = true;
3760 /* Capability revision >= 2 */
3762 p->flex10_enable = true;
3764 p->flex10_capable = true;
3766 p->flex10_mode = logical_id;
3767 p->flex10_status = phys_id;
3768 i40e_debug(hw, I40E_DEBUG_INIT,
3769 "HW Capability: Flex10 mode = %d\n",
3771 i40e_debug(hw, I40E_DEBUG_INIT,
3772 "HW Capability: Flex10 status = %d\n",
3775 case I40E_AQ_CAP_ID_CEM:
3778 i40e_debug(hw, I40E_DEBUG_INIT,
3779 "HW Capability: CEM = %d\n", p->mgmt_cem);
3781 case I40E_AQ_CAP_ID_IWARP:
3784 i40e_debug(hw, I40E_DEBUG_INIT,
3785 "HW Capability: iWARP = %d\n", p->iwarp);
3787 case I40E_AQ_CAP_ID_LED:
3788 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3789 p->led[phys_id] = true;
3790 i40e_debug(hw, I40E_DEBUG_INIT,
3791 "HW Capability: LED - PIN %d\n", phys_id);
3793 case I40E_AQ_CAP_ID_SDP:
3794 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3795 p->sdp[phys_id] = true;
3796 i40e_debug(hw, I40E_DEBUG_INIT,
3797 "HW Capability: SDP - PIN %d\n", phys_id);
3799 case I40E_AQ_CAP_ID_MDIO:
3801 p->mdio_port_num = phys_id;
3802 p->mdio_port_mode = logical_id;
3804 i40e_debug(hw, I40E_DEBUG_INIT,
3805 "HW Capability: MDIO port number = %d\n",
3807 i40e_debug(hw, I40E_DEBUG_INIT,
3808 "HW Capability: MDIO port mode = %d\n",
3811 case I40E_AQ_CAP_ID_1588:
3813 p->ieee_1588 = true;
3814 i40e_debug(hw, I40E_DEBUG_INIT,
3815 "HW Capability: IEEE 1588 = %d\n",
3818 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3820 p->fd_filters_guaranteed = number;
3821 p->fd_filters_best_effort = logical_id;
3822 i40e_debug(hw, I40E_DEBUG_INIT,
3823 "HW Capability: Flow Director = 1\n");
3824 i40e_debug(hw, I40E_DEBUG_INIT,
3825 "HW Capability: Guaranteed FD filters = %d\n",
3826 p->fd_filters_guaranteed);
3828 case I40E_AQ_CAP_ID_WSR_PROT:
3829 p->wr_csr_prot = (u64)number;
3830 p->wr_csr_prot |= (u64)logical_id << 32;
3831 i40e_debug(hw, I40E_DEBUG_INIT,
3832 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3833 (p->wr_csr_prot & 0xffff));
3835 case I40E_AQ_CAP_ID_NVM_MGMT:
3836 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3837 p->sec_rev_disabled = true;
3838 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3839 p->update_disabled = true;
3842 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3843 hw->num_wol_proxy_filters = (u16)number;
3844 hw->wol_proxy_vsi_seid = (u16)logical_id;
3845 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3846 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3847 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3849 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3850 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3851 i40e_debug(hw, I40E_DEBUG_INIT,
3852 "HW Capability: WOL proxy filters = %d\n",
3853 hw->num_wol_proxy_filters);
3862 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3864 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3867 /* count the enabled ports (aka the "not disabled" ports) */
3869 for (i = 0; i < 4; i++) {
3870 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3873 /* use AQ read to get the physical register offset instead
3874 * of the port relative offset
3876 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3877 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3881 valid_functions = p->valid_functions;
3883 while (valid_functions) {
3884 if (valid_functions & 1)
3886 valid_functions >>= 1;
3889 /* partition id is 1-based, and functions are evenly spread
3890 * across the ports as partitions
3892 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3893 hw->num_partitions = num_functions / hw->num_ports;
3895 /* additional HW specific goodies that might
3896 * someday be HW version specific
3898 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3902 * i40e_aq_discover_capabilities
3903 * @hw: pointer to the hw struct
3904 * @buff: a virtual buffer to hold the capabilities
3905 * @buff_size: Size of the virtual buffer
3906 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3907 * @list_type_opc: capabilities type to discover - pass in the command opcode
3908 * @cmd_details: pointer to command details structure or NULL
3910 * Get the device capabilities descriptions from the firmware
3912 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3913 void *buff, u16 buff_size, u16 *data_size,
3914 enum i40e_admin_queue_opc list_type_opc,
3915 struct i40e_asq_cmd_details *cmd_details)
3917 struct i40e_aqc_list_capabilites *cmd;
3918 struct i40e_aq_desc desc;
3919 enum i40e_status_code status = I40E_SUCCESS;
3921 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3923 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3924 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3925 status = I40E_ERR_PARAM;
3929 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3931 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3932 if (buff_size > I40E_AQ_LARGE_BUF)
3933 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3935 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3936 *data_size = LE16_TO_CPU(desc.datalen);
3941 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3949 * i40e_aq_update_nvm
3950 * @hw: pointer to the hw struct
3951 * @module_pointer: module pointer location in words from the NVM beginning
3952 * @offset: byte offset from the module beginning
3953 * @length: length of the section to be written (in bytes from the offset)
3954 * @data: command buffer (size [bytes] = length)
3955 * @last_command: tells if this is the last command in a series
3956 * @cmd_details: pointer to command details structure or NULL
3958 * Update the NVM using the admin queue commands
3960 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3961 u32 offset, u16 length, void *data,
3963 struct i40e_asq_cmd_details *cmd_details)
3965 struct i40e_aq_desc desc;
3966 struct i40e_aqc_nvm_update *cmd =
3967 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3968 enum i40e_status_code status;
3970 DEBUGFUNC("i40e_aq_update_nvm");
3972 /* In offset the highest byte must be zeroed. */
3973 if (offset & 0xFF000000) {
3974 status = I40E_ERR_PARAM;
3975 goto i40e_aq_update_nvm_exit;
3978 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3980 /* If this is the last command in a series, set the proper flag. */
3982 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3983 cmd->module_pointer = module_pointer;
3984 cmd->offset = CPU_TO_LE32(offset);
3985 cmd->length = CPU_TO_LE16(length);
3987 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3988 if (length > I40E_AQ_LARGE_BUF)
3989 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3991 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3993 i40e_aq_update_nvm_exit:
3998 * i40e_aq_get_lldp_mib
3999 * @hw: pointer to the hw struct
4000 * @bridge_type: type of bridge requested
4001 * @mib_type: Local, Remote or both Local and Remote MIBs
4002 * @buff: pointer to a user supplied buffer to store the MIB block
4003 * @buff_size: size of the buffer (in bytes)
4004 * @local_len : length of the returned Local LLDP MIB
4005 * @remote_len: length of the returned Remote LLDP MIB
4006 * @cmd_details: pointer to command details structure or NULL
4008 * Requests the complete LLDP MIB (entire packet).
4010 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4011 u8 mib_type, void *buff, u16 buff_size,
4012 u16 *local_len, u16 *remote_len,
4013 struct i40e_asq_cmd_details *cmd_details)
4015 struct i40e_aq_desc desc;
4016 struct i40e_aqc_lldp_get_mib *cmd =
4017 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4018 struct i40e_aqc_lldp_get_mib *resp =
4019 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4020 enum i40e_status_code status;
4022 if (buff_size == 0 || !buff)
4023 return I40E_ERR_PARAM;
4025 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4026 /* Indirect Command */
4027 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4029 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4030 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4031 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4033 desc.datalen = CPU_TO_LE16(buff_size);
4035 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4036 if (buff_size > I40E_AQ_LARGE_BUF)
4037 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4039 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4041 if (local_len != NULL)
4042 *local_len = LE16_TO_CPU(resp->local_len);
4043 if (remote_len != NULL)
4044 *remote_len = LE16_TO_CPU(resp->remote_len);
4051 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4052 * @hw: pointer to the hw struct
4053 * @mib_type: Local, Remote or both Local and Remote MIBs
4054 * @buff: pointer to a user supplied buffer to store the MIB block
4055 * @buff_size: size of the buffer (in bytes)
4056 * @cmd_details: pointer to command details structure or NULL
4060 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4061 u8 mib_type, void *buff, u16 buff_size,
4062 struct i40e_asq_cmd_details *cmd_details)
4064 struct i40e_aq_desc desc;
4065 struct i40e_aqc_lldp_set_local_mib *cmd =
4066 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4067 enum i40e_status_code status;
4069 if (buff_size == 0 || !buff)
4070 return I40E_ERR_PARAM;
4072 i40e_fill_default_direct_cmd_desc(&desc,
4073 i40e_aqc_opc_lldp_set_local_mib);
4074 /* Indirect Command */
4075 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4076 if (buff_size > I40E_AQ_LARGE_BUF)
4077 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4078 desc.datalen = CPU_TO_LE16(buff_size);
4080 cmd->type = mib_type;
4081 cmd->length = CPU_TO_LE16(buff_size);
4082 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4083 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4085 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4090 * i40e_aq_cfg_lldp_mib_change_event
4091 * @hw: pointer to the hw struct
4092 * @enable_update: Enable or Disable event posting
4093 * @cmd_details: pointer to command details structure or NULL
4095 * Enable or Disable posting of an event on ARQ when LLDP MIB
4096 * associated with the interface changes
4098 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4100 struct i40e_asq_cmd_details *cmd_details)
4102 struct i40e_aq_desc desc;
4103 struct i40e_aqc_lldp_update_mib *cmd =
4104 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4105 enum i40e_status_code status;
4107 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4110 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4112 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4118 * i40e_aq_add_lldp_tlv
4119 * @hw: pointer to the hw struct
4120 * @bridge_type: type of bridge
4121 * @buff: buffer with TLV to add
4122 * @buff_size: length of the buffer
4123 * @tlv_len: length of the TLV to be added
4124 * @mib_len: length of the LLDP MIB returned in response
4125 * @cmd_details: pointer to command details structure or NULL
4127 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4128 * it is responsibility of the caller to make sure that the TLV is not
4129 * already present in the LLDPDU.
4130 * In return firmware will write the complete LLDP MIB with the newly
4131 * added TLV in the response buffer.
4133 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4134 void *buff, u16 buff_size, u16 tlv_len,
4136 struct i40e_asq_cmd_details *cmd_details)
4138 struct i40e_aq_desc desc;
4139 struct i40e_aqc_lldp_add_tlv *cmd =
4140 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4141 enum i40e_status_code status;
4143 if (buff_size == 0 || !buff || tlv_len == 0)
4144 return I40E_ERR_PARAM;
4146 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4148 /* Indirect Command */
4149 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4150 if (buff_size > I40E_AQ_LARGE_BUF)
4151 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4152 desc.datalen = CPU_TO_LE16(buff_size);
4154 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4155 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4156 cmd->len = CPU_TO_LE16(tlv_len);
4158 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4160 if (mib_len != NULL)
4161 *mib_len = LE16_TO_CPU(desc.datalen);
4168 * i40e_aq_update_lldp_tlv
4169 * @hw: pointer to the hw struct
4170 * @bridge_type: type of bridge
4171 * @buff: buffer with TLV to update
4172 * @buff_size: size of the buffer holding original and updated TLVs
4173 * @old_len: Length of the Original TLV
4174 * @new_len: Length of the Updated TLV
4175 * @offset: offset of the updated TLV in the buff
4176 * @mib_len: length of the returned LLDP MIB
4177 * @cmd_details: pointer to command details structure or NULL
4179 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4180 * Firmware will place the complete LLDP MIB in response buffer with the
4183 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4184 u8 bridge_type, void *buff, u16 buff_size,
4185 u16 old_len, u16 new_len, u16 offset,
4187 struct i40e_asq_cmd_details *cmd_details)
4189 struct i40e_aq_desc desc;
4190 struct i40e_aqc_lldp_update_tlv *cmd =
4191 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4192 enum i40e_status_code status;
4194 if (buff_size == 0 || !buff || offset == 0 ||
4195 old_len == 0 || new_len == 0)
4196 return I40E_ERR_PARAM;
4198 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4200 /* Indirect Command */
4201 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4202 if (buff_size > I40E_AQ_LARGE_BUF)
4203 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4204 desc.datalen = CPU_TO_LE16(buff_size);
4206 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4207 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4208 cmd->old_len = CPU_TO_LE16(old_len);
4209 cmd->new_offset = CPU_TO_LE16(offset);
4210 cmd->new_len = CPU_TO_LE16(new_len);
4212 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4214 if (mib_len != NULL)
4215 *mib_len = LE16_TO_CPU(desc.datalen);
4222 * i40e_aq_delete_lldp_tlv
4223 * @hw: pointer to the hw struct
4224 * @bridge_type: type of bridge
4225 * @buff: pointer to a user supplied buffer that has the TLV
4226 * @buff_size: length of the buffer
4227 * @tlv_len: length of the TLV to be deleted
4228 * @mib_len: length of the returned LLDP MIB
4229 * @cmd_details: pointer to command details structure or NULL
4231 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4232 * The firmware places the entire LLDP MIB in the response buffer.
4234 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4235 u8 bridge_type, void *buff, u16 buff_size,
4236 u16 tlv_len, u16 *mib_len,
4237 struct i40e_asq_cmd_details *cmd_details)
4239 struct i40e_aq_desc desc;
4240 struct i40e_aqc_lldp_add_tlv *cmd =
4241 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4242 enum i40e_status_code status;
4244 if (buff_size == 0 || !buff)
4245 return I40E_ERR_PARAM;
4247 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4249 /* Indirect Command */
4250 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4251 if (buff_size > I40E_AQ_LARGE_BUF)
4252 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4253 desc.datalen = CPU_TO_LE16(buff_size);
4254 cmd->len = CPU_TO_LE16(tlv_len);
4255 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4256 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4258 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4260 if (mib_len != NULL)
4261 *mib_len = LE16_TO_CPU(desc.datalen);
4269 * @hw: pointer to the hw struct
4270 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4271 * @cmd_details: pointer to command details structure or NULL
4273 * Stop or Shutdown the embedded LLDP Agent
4275 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4276 struct i40e_asq_cmd_details *cmd_details)
4278 struct i40e_aq_desc desc;
4279 struct i40e_aqc_lldp_stop *cmd =
4280 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4281 enum i40e_status_code status;
4283 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4286 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4288 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4294 * i40e_aq_start_lldp
4295 * @hw: pointer to the hw struct
4296 * @cmd_details: pointer to command details structure or NULL
4298 * Start the embedded LLDP Agent on all ports.
4300 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4301 struct i40e_asq_cmd_details *cmd_details)
4303 struct i40e_aq_desc desc;
4304 struct i40e_aqc_lldp_start *cmd =
4305 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4306 enum i40e_status_code status;
4308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4310 cmd->command = I40E_AQ_LLDP_AGENT_START;
4312 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4318 * i40e_aq_get_cee_dcb_config
4319 * @hw: pointer to the hw struct
4320 * @buff: response buffer that stores CEE operational configuration
4321 * @buff_size: size of the buffer passed
4322 * @cmd_details: pointer to command details structure or NULL
4324 * Get CEE DCBX mode operational configuration from firmware
4326 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4327 void *buff, u16 buff_size,
4328 struct i40e_asq_cmd_details *cmd_details)
4330 struct i40e_aq_desc desc;
4331 enum i40e_status_code status;
4333 if (buff_size == 0 || !buff)
4334 return I40E_ERR_PARAM;
4336 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4338 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4339 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4346 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4347 * @hw: pointer to the hw struct
4348 * @start_agent: True if DCBx Agent needs to be Started
4349 * False if DCBx Agent needs to be Stopped
4350 * @cmd_details: pointer to command details structure or NULL
4352 * Start/Stop the embedded dcbx Agent
4354 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4356 struct i40e_asq_cmd_details *cmd_details)
4358 struct i40e_aq_desc desc;
4359 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4360 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4362 enum i40e_status_code status;
4364 i40e_fill_default_direct_cmd_desc(&desc,
4365 i40e_aqc_opc_lldp_stop_start_spec_agent);
4368 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4370 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4376 * i40e_aq_add_udp_tunnel
4377 * @hw: pointer to the hw struct
4378 * @udp_port: the UDP port to add
4379 * @header_len: length of the tunneling header length in DWords
4380 * @protocol_index: protocol index type
4381 * @filter_index: pointer to filter index
4382 * @cmd_details: pointer to command details structure or NULL
4384 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4385 u16 udp_port, u8 protocol_index,
4387 struct i40e_asq_cmd_details *cmd_details)
4389 struct i40e_aq_desc desc;
4390 struct i40e_aqc_add_udp_tunnel *cmd =
4391 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4392 struct i40e_aqc_del_udp_tunnel_completion *resp =
4393 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4394 enum i40e_status_code status;
4396 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4398 cmd->udp_port = CPU_TO_LE16(udp_port);
4399 cmd->protocol_type = protocol_index;
4401 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4403 if (!status && filter_index)
4404 *filter_index = resp->index;
4410 * i40e_aq_del_udp_tunnel
4411 * @hw: pointer to the hw struct
4412 * @index: filter index
4413 * @cmd_details: pointer to command details structure or NULL
4415 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4416 struct i40e_asq_cmd_details *cmd_details)
4418 struct i40e_aq_desc desc;
4419 struct i40e_aqc_remove_udp_tunnel *cmd =
4420 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4421 enum i40e_status_code status;
4423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4427 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4433 * i40e_aq_get_switch_resource_alloc (0x0204)
4434 * @hw: pointer to the hw struct
4435 * @num_entries: pointer to u8 to store the number of resource entries returned
4436 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4437 * to store the resource information for all resource types. Each
4438 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4439 * @count: size, in bytes, of the buffer provided
4440 * @cmd_details: pointer to command details structure or NULL
4442 * Query the resources allocated to a function.
4444 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4446 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4448 struct i40e_asq_cmd_details *cmd_details)
4450 struct i40e_aq_desc desc;
4451 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4452 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4453 enum i40e_status_code status;
4454 u16 length = count * sizeof(*buf);
4456 i40e_fill_default_direct_cmd_desc(&desc,
4457 i40e_aqc_opc_get_switch_resource_alloc);
4459 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4460 if (length > I40E_AQ_LARGE_BUF)
4461 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4463 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4465 if (!status && num_entries)
4466 *num_entries = cmd_resp->num_entries;
4472 * i40e_aq_delete_element - Delete switch element
4473 * @hw: pointer to the hw struct
4474 * @seid: the SEID to delete from the switch
4475 * @cmd_details: pointer to command details structure or NULL
4477 * This deletes a switch element from the switch.
4479 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4480 struct i40e_asq_cmd_details *cmd_details)
4482 struct i40e_aq_desc desc;
4483 struct i40e_aqc_switch_seid *cmd =
4484 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4485 enum i40e_status_code status;
4488 return I40E_ERR_PARAM;
4490 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4492 cmd->seid = CPU_TO_LE16(seid);
4494 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4500 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4501 * @hw: pointer to the hw struct
4502 * @flags: component flags
4503 * @mac_seid: uplink seid (MAC SEID)
4504 * @vsi_seid: connected vsi seid
4505 * @ret_seid: seid of create pv component
4507 * This instantiates an i40e port virtualizer with specified flags.
4508 * Depending on specified flags the port virtualizer can act as a
4509 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4511 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4512 u16 mac_seid, u16 vsi_seid,
4515 struct i40e_aq_desc desc;
4516 struct i40e_aqc_add_update_pv *cmd =
4517 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4518 struct i40e_aqc_add_update_pv_completion *resp =
4519 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4520 enum i40e_status_code status;
4523 return I40E_ERR_PARAM;
4525 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4526 cmd->command_flags = CPU_TO_LE16(flags);
4527 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4528 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4530 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4531 if (!status && ret_seid)
4532 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4538 * i40e_aq_add_tag - Add an S/E-tag
4539 * @hw: pointer to the hw struct
4540 * @direct_to_queue: should s-tag direct flow to a specific queue
4541 * @vsi_seid: VSI SEID to use this tag
4542 * @tag: value of the tag
4543 * @queue_num: queue number, only valid is direct_to_queue is true
4544 * @tags_used: return value, number of tags in use by this PF
4545 * @tags_free: return value, number of unallocated tags
4546 * @cmd_details: pointer to command details structure or NULL
4548 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4549 * the number of tags allocated by the PF, and the number of unallocated
4552 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4553 u16 vsi_seid, u16 tag, u16 queue_num,
4554 u16 *tags_used, u16 *tags_free,
4555 struct i40e_asq_cmd_details *cmd_details)
4557 struct i40e_aq_desc desc;
4558 struct i40e_aqc_add_tag *cmd =
4559 (struct i40e_aqc_add_tag *)&desc.params.raw;
4560 struct i40e_aqc_add_remove_tag_completion *resp =
4561 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4562 enum i40e_status_code status;
4565 return I40E_ERR_PARAM;
4567 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4569 cmd->seid = CPU_TO_LE16(vsi_seid);
4570 cmd->tag = CPU_TO_LE16(tag);
4571 if (direct_to_queue) {
4572 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4573 cmd->queue_number = CPU_TO_LE16(queue_num);
4576 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4579 if (tags_used != NULL)
4580 *tags_used = LE16_TO_CPU(resp->tags_used);
4581 if (tags_free != NULL)
4582 *tags_free = LE16_TO_CPU(resp->tags_free);
4589 * i40e_aq_remove_tag - Remove an S- or E-tag
4590 * @hw: pointer to the hw struct
4591 * @vsi_seid: VSI SEID this tag is associated with
4592 * @tag: value of the S-tag to delete
4593 * @tags_used: return value, number of tags in use by this PF
4594 * @tags_free: return value, number of unallocated tags
4595 * @cmd_details: pointer to command details structure or NULL
4597 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4598 * the number of tags allocated by the PF, and the number of unallocated
4601 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4602 u16 tag, u16 *tags_used, u16 *tags_free,
4603 struct i40e_asq_cmd_details *cmd_details)
4605 struct i40e_aq_desc desc;
4606 struct i40e_aqc_remove_tag *cmd =
4607 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4608 struct i40e_aqc_add_remove_tag_completion *resp =
4609 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4610 enum i40e_status_code status;
4613 return I40E_ERR_PARAM;
4615 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4617 cmd->seid = CPU_TO_LE16(vsi_seid);
4618 cmd->tag = CPU_TO_LE16(tag);
4620 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4623 if (tags_used != NULL)
4624 *tags_used = LE16_TO_CPU(resp->tags_used);
4625 if (tags_free != NULL)
4626 *tags_free = LE16_TO_CPU(resp->tags_free);
4633 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4634 * @hw: pointer to the hw struct
4635 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4636 * @etag: value of E-tag to add
4637 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4638 * @buf: address of indirect buffer
4639 * @tags_used: return value, number of E-tags in use by this port
4640 * @tags_free: return value, number of unallocated M-tags
4641 * @cmd_details: pointer to command details structure or NULL
4643 * This associates a multicast E-tag to a port virtualizer. It will return
4644 * the number of tags allocated by the PF, and the number of unallocated
4647 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4648 * num_tags_in_buf long.
4650 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4651 u16 etag, u8 num_tags_in_buf, void *buf,
4652 u16 *tags_used, u16 *tags_free,
4653 struct i40e_asq_cmd_details *cmd_details)
4655 struct i40e_aq_desc desc;
4656 struct i40e_aqc_add_remove_mcast_etag *cmd =
4657 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4658 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4659 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4660 enum i40e_status_code status;
4661 u16 length = sizeof(u16) * num_tags_in_buf;
4663 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4664 return I40E_ERR_PARAM;
4666 i40e_fill_default_direct_cmd_desc(&desc,
4667 i40e_aqc_opc_add_multicast_etag);
4669 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4670 cmd->etag = CPU_TO_LE16(etag);
4671 cmd->num_unicast_etags = num_tags_in_buf;
4673 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4674 if (length > I40E_AQ_LARGE_BUF)
4675 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4677 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4680 if (tags_used != NULL)
4681 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4682 if (tags_free != NULL)
4683 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4690 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4691 * @hw: pointer to the hw struct
4692 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4693 * @etag: value of the E-tag to remove
4694 * @tags_used: return value, number of tags in use by this port
4695 * @tags_free: return value, number of unallocated tags
4696 * @cmd_details: pointer to command details structure or NULL
4698 * This deletes an E-tag from the port virtualizer. It will return
4699 * the number of tags allocated by the port, and the number of unallocated
4702 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4703 u16 etag, u16 *tags_used, u16 *tags_free,
4704 struct i40e_asq_cmd_details *cmd_details)
4706 struct i40e_aq_desc desc;
4707 struct i40e_aqc_add_remove_mcast_etag *cmd =
4708 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4709 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4710 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4711 enum i40e_status_code status;
4715 return I40E_ERR_PARAM;
4717 i40e_fill_default_direct_cmd_desc(&desc,
4718 i40e_aqc_opc_remove_multicast_etag);
4720 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4721 cmd->etag = CPU_TO_LE16(etag);
4723 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4726 if (tags_used != NULL)
4727 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4728 if (tags_free != NULL)
4729 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4736 * i40e_aq_update_tag - Update an S/E-tag
4737 * @hw: pointer to the hw struct
4738 * @vsi_seid: VSI SEID using this S-tag
4739 * @old_tag: old tag value
4740 * @new_tag: new tag value
4741 * @tags_used: return value, number of tags in use by this PF
4742 * @tags_free: return value, number of unallocated tags
4743 * @cmd_details: pointer to command details structure or NULL
4745 * This updates the value of the tag currently attached to this VSI
4746 * in the switch complex. It will return the number of tags allocated
4747 * by the PF, and the number of unallocated tags available.
4749 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4750 u16 old_tag, u16 new_tag, u16 *tags_used,
4752 struct i40e_asq_cmd_details *cmd_details)
4754 struct i40e_aq_desc desc;
4755 struct i40e_aqc_update_tag *cmd =
4756 (struct i40e_aqc_update_tag *)&desc.params.raw;
4757 struct i40e_aqc_update_tag_completion *resp =
4758 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4759 enum i40e_status_code status;
4762 return I40E_ERR_PARAM;
4764 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4766 cmd->seid = CPU_TO_LE16(vsi_seid);
4767 cmd->old_tag = CPU_TO_LE16(old_tag);
4768 cmd->new_tag = CPU_TO_LE16(new_tag);
4770 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4773 if (tags_used != NULL)
4774 *tags_used = LE16_TO_CPU(resp->tags_used);
4775 if (tags_free != NULL)
4776 *tags_free = LE16_TO_CPU(resp->tags_free);
4783 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4784 * @hw: pointer to the hw struct
4785 * @tcmap: TC map for request/release any ignore PFC condition
4786 * @request: request or release ignore PFC condition
4787 * @tcmap_ret: return TCs for which PFC is currently ignored
4788 * @cmd_details: pointer to command details structure or NULL
4790 * This sends out request/release to ignore PFC condition for a TC.
4791 * It will return the TCs for which PFC is currently ignored.
4793 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4794 bool request, u8 *tcmap_ret,
4795 struct i40e_asq_cmd_details *cmd_details)
4797 struct i40e_aq_desc desc;
4798 struct i40e_aqc_pfc_ignore *cmd_resp =
4799 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4800 enum i40e_status_code status;
4802 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4805 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4807 cmd_resp->tc_bitmap = tcmap;
4809 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4812 if (tcmap_ret != NULL)
4813 *tcmap_ret = cmd_resp->tc_bitmap;
4820 * i40e_aq_dcb_updated - DCB Updated Command
4821 * @hw: pointer to the hw struct
4822 * @cmd_details: pointer to command details structure or NULL
4824 * When LLDP is handled in PF this command is used by the PF
4825 * to notify EMP that a DCB setting is modified.
4826 * When LLDP is handled in EMP this command is used by the PF
4827 * to notify EMP whenever one of the following parameters get
4829 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4830 * - PCIRTT in PRTDCB_GENC.PCIRTT
4831 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4832 * EMP will return when the shared RPB settings have been
4833 * recomputed and modified. The retval field in the descriptor
4834 * will be set to 0 when RPB is modified.
4836 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4837 struct i40e_asq_cmd_details *cmd_details)
4839 struct i40e_aq_desc desc;
4840 enum i40e_status_code status;
4842 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4844 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4850 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4851 * @hw: pointer to the hw struct
4852 * @seid: defines the SEID of the switch for which the stats are requested
4853 * @vlan_id: the VLAN ID for which the statistics are requested
4854 * @stat_index: index of the statistics counters block assigned to this VLAN
4855 * @cmd_details: pointer to command details structure or NULL
4857 * XL710 supports 128 smonVlanStats counters.This command is used to
4858 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4861 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4862 u16 vlan_id, u16 *stat_index,
4863 struct i40e_asq_cmd_details *cmd_details)
4865 struct i40e_aq_desc desc;
4866 struct i40e_aqc_add_remove_statistics *cmd_resp =
4867 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4868 enum i40e_status_code status;
4870 if ((seid == 0) || (stat_index == NULL))
4871 return I40E_ERR_PARAM;
4873 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4875 cmd_resp->seid = CPU_TO_LE16(seid);
4876 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4878 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4880 if (!status && stat_index)
4881 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4887 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4888 * @hw: pointer to the hw struct
4889 * @seid: defines the SEID of the switch for which the stats are requested
4890 * @vlan_id: the VLAN ID for which the statistics are requested
4891 * @stat_index: index of the statistics counters block assigned to this VLAN
4892 * @cmd_details: pointer to command details structure or NULL
4894 * XL710 supports 128 smonVlanStats counters.This command is used to
4895 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4898 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4899 u16 vlan_id, u16 stat_index,
4900 struct i40e_asq_cmd_details *cmd_details)
4902 struct i40e_aq_desc desc;
4903 struct i40e_aqc_add_remove_statistics *cmd =
4904 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4905 enum i40e_status_code status;
4908 return I40E_ERR_PARAM;
4910 i40e_fill_default_direct_cmd_desc(&desc,
4911 i40e_aqc_opc_remove_statistics);
4913 cmd->seid = CPU_TO_LE16(seid);
4914 cmd->vlan = CPU_TO_LE16(vlan_id);
4915 cmd->stat_index = CPU_TO_LE16(stat_index);
4917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4923 * i40e_aq_set_port_parameters - set physical port parameters.
4924 * @hw: pointer to the hw struct
4925 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4926 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4927 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4928 * @double_vlan: if set double VLAN is enabled
4929 * @cmd_details: pointer to command details structure or NULL
4931 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4932 u16 bad_frame_vsi, bool save_bad_pac,
4933 bool pad_short_pac, bool double_vlan,
4934 struct i40e_asq_cmd_details *cmd_details)
4936 struct i40e_aqc_set_port_parameters *cmd;
4937 enum i40e_status_code status;
4938 struct i40e_aq_desc desc;
4939 u16 command_flags = 0;
4941 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4943 i40e_fill_default_direct_cmd_desc(&desc,
4944 i40e_aqc_opc_set_port_parameters);
4946 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4948 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4950 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4952 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4953 cmd->command_flags = CPU_TO_LE16(command_flags);
4955 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4961 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4962 * @hw: pointer to the hw struct
4963 * @seid: seid for the physical port/switching component/vsi
4964 * @buff: Indirect buffer to hold data parameters and response
4965 * @buff_size: Indirect buffer size
4966 * @opcode: Tx scheduler AQ command opcode
4967 * @cmd_details: pointer to command details structure or NULL
4969 * Generic command handler for Tx scheduler AQ commands
4971 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4972 void *buff, u16 buff_size,
4973 enum i40e_admin_queue_opc opcode,
4974 struct i40e_asq_cmd_details *cmd_details)
4976 struct i40e_aq_desc desc;
4977 struct i40e_aqc_tx_sched_ind *cmd =
4978 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4979 enum i40e_status_code status;
4980 bool cmd_param_flag = false;
4983 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4984 case i40e_aqc_opc_configure_vsi_tc_bw:
4985 case i40e_aqc_opc_enable_switching_comp_ets:
4986 case i40e_aqc_opc_modify_switching_comp_ets:
4987 case i40e_aqc_opc_disable_switching_comp_ets:
4988 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4989 case i40e_aqc_opc_configure_switching_comp_bw_config:
4990 cmd_param_flag = true;
4992 case i40e_aqc_opc_query_vsi_bw_config:
4993 case i40e_aqc_opc_query_vsi_ets_sla_config:
4994 case i40e_aqc_opc_query_switching_comp_ets_config:
4995 case i40e_aqc_opc_query_port_ets_config:
4996 case i40e_aqc_opc_query_switching_comp_bw_config:
4997 cmd_param_flag = false;
5000 return I40E_ERR_PARAM;
5003 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5005 /* Indirect command */
5006 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5008 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5009 if (buff_size > I40E_AQ_LARGE_BUF)
5010 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5012 desc.datalen = CPU_TO_LE16(buff_size);
5014 cmd->vsi_seid = CPU_TO_LE16(seid);
5016 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5022 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5023 * @hw: pointer to the hw struct
5025 * @credit: BW limit credits (0 = disabled)
5026 * @max_credit: Max BW limit credits
5027 * @cmd_details: pointer to command details structure or NULL
5029 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5030 u16 seid, u16 credit, u8 max_credit,
5031 struct i40e_asq_cmd_details *cmd_details)
5033 struct i40e_aq_desc desc;
5034 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5035 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5036 enum i40e_status_code status;
5038 i40e_fill_default_direct_cmd_desc(&desc,
5039 i40e_aqc_opc_configure_vsi_bw_limit);
5041 cmd->vsi_seid = CPU_TO_LE16(seid);
5042 cmd->credit = CPU_TO_LE16(credit);
5043 cmd->max_credit = max_credit;
5045 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5051 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5052 * @hw: pointer to the hw struct
5053 * @seid: switching component seid
5054 * @credit: BW limit credits (0 = disabled)
5055 * @max_bw: Max BW limit credits
5056 * @cmd_details: pointer to command details structure or NULL
5058 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5059 u16 seid, u16 credit, u8 max_bw,
5060 struct i40e_asq_cmd_details *cmd_details)
5062 struct i40e_aq_desc desc;
5063 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5064 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5065 enum i40e_status_code status;
5067 i40e_fill_default_direct_cmd_desc(&desc,
5068 i40e_aqc_opc_configure_switching_comp_bw_limit);
5070 cmd->seid = CPU_TO_LE16(seid);
5071 cmd->credit = CPU_TO_LE16(credit);
5072 cmd->max_bw = max_bw;
5074 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5080 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5081 * @hw: pointer to the hw struct
5083 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5084 * @cmd_details: pointer to command details structure or NULL
5086 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5088 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5089 struct i40e_asq_cmd_details *cmd_details)
5091 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5092 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5097 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5098 * @hw: pointer to the hw struct
5100 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5101 * @cmd_details: pointer to command details structure or NULL
5103 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5105 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5106 struct i40e_asq_cmd_details *cmd_details)
5108 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5109 i40e_aqc_opc_configure_vsi_tc_bw,
5114 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5115 * @hw: pointer to the hw struct
5116 * @seid: seid of the switching component connected to Physical Port
5117 * @ets_data: Buffer holding ETS parameters
5118 * @cmd_details: pointer to command details structure or NULL
5120 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5122 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5123 enum i40e_admin_queue_opc opcode,
5124 struct i40e_asq_cmd_details *cmd_details)
5126 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5127 sizeof(*ets_data), opcode, cmd_details);
5131 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5132 * @hw: pointer to the hw struct
5133 * @seid: seid of the switching component
5134 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5135 * @cmd_details: pointer to command details structure or NULL
5137 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5139 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5140 struct i40e_asq_cmd_details *cmd_details)
5142 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5143 i40e_aqc_opc_configure_switching_comp_bw_config,
5148 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5149 * @hw: pointer to the hw struct
5150 * @seid: seid of the switching component
5151 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5152 * @cmd_details: pointer to command details structure or NULL
5154 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5155 struct i40e_hw *hw, u16 seid,
5156 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5157 struct i40e_asq_cmd_details *cmd_details)
5159 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5160 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5165 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5166 * @hw: pointer to the hw struct
5167 * @seid: seid of the VSI
5168 * @bw_data: Buffer to hold VSI BW configuration
5169 * @cmd_details: pointer to command details structure or NULL
5171 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5173 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5174 struct i40e_asq_cmd_details *cmd_details)
5176 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5177 i40e_aqc_opc_query_vsi_bw_config,
5182 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5183 * @hw: pointer to the hw struct
5184 * @seid: seid of the VSI
5185 * @bw_data: Buffer to hold VSI BW configuration per TC
5186 * @cmd_details: pointer to command details structure or NULL
5188 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5190 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5191 struct i40e_asq_cmd_details *cmd_details)
5193 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5194 i40e_aqc_opc_query_vsi_ets_sla_config,
5199 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5200 * @hw: pointer to the hw struct
5201 * @seid: seid of the switching component
5202 * @bw_data: Buffer to hold switching component's per TC BW config
5203 * @cmd_details: pointer to command details structure or NULL
5205 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5207 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5208 struct i40e_asq_cmd_details *cmd_details)
5210 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5211 i40e_aqc_opc_query_switching_comp_ets_config,
5216 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5217 * @hw: pointer to the hw struct
5218 * @seid: seid of the VSI or switching component connected to Physical Port
5219 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5220 * @cmd_details: pointer to command details structure or NULL
5222 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5224 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5225 struct i40e_asq_cmd_details *cmd_details)
5227 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5228 i40e_aqc_opc_query_port_ets_config,
5233 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5234 * @hw: pointer to the hw struct
5235 * @seid: seid of the switching component
5236 * @bw_data: Buffer to hold switching component's BW configuration
5237 * @cmd_details: pointer to command details structure or NULL
5239 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5241 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5242 struct i40e_asq_cmd_details *cmd_details)
5244 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5245 i40e_aqc_opc_query_switching_comp_bw_config,
5250 * i40e_validate_filter_settings
5251 * @hw: pointer to the hardware structure
5252 * @settings: Filter control settings
5254 * Check and validate the filter control settings passed.
5255 * The function checks for the valid filter/context sizes being
5256 * passed for FCoE and PE.
5258 * Returns I40E_SUCCESS if the values passed are valid and within
5259 * range else returns an error.
5261 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5262 struct i40e_filter_control_settings *settings)
5264 u32 fcoe_cntx_size, fcoe_filt_size;
5265 u32 pe_cntx_size, pe_filt_size;
5270 /* Validate FCoE settings passed */
5271 switch (settings->fcoe_filt_num) {
5272 case I40E_HASH_FILTER_SIZE_1K:
5273 case I40E_HASH_FILTER_SIZE_2K:
5274 case I40E_HASH_FILTER_SIZE_4K:
5275 case I40E_HASH_FILTER_SIZE_8K:
5276 case I40E_HASH_FILTER_SIZE_16K:
5277 case I40E_HASH_FILTER_SIZE_32K:
5278 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5279 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5282 return I40E_ERR_PARAM;
5285 switch (settings->fcoe_cntx_num) {
5286 case I40E_DMA_CNTX_SIZE_512:
5287 case I40E_DMA_CNTX_SIZE_1K:
5288 case I40E_DMA_CNTX_SIZE_2K:
5289 case I40E_DMA_CNTX_SIZE_4K:
5290 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5291 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5294 return I40E_ERR_PARAM;
5297 /* Validate PE settings passed */
5298 switch (settings->pe_filt_num) {
5299 case I40E_HASH_FILTER_SIZE_1K:
5300 case I40E_HASH_FILTER_SIZE_2K:
5301 case I40E_HASH_FILTER_SIZE_4K:
5302 case I40E_HASH_FILTER_SIZE_8K:
5303 case I40E_HASH_FILTER_SIZE_16K:
5304 case I40E_HASH_FILTER_SIZE_32K:
5305 case I40E_HASH_FILTER_SIZE_64K:
5306 case I40E_HASH_FILTER_SIZE_128K:
5307 case I40E_HASH_FILTER_SIZE_256K:
5308 case I40E_HASH_FILTER_SIZE_512K:
5309 case I40E_HASH_FILTER_SIZE_1M:
5310 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5311 pe_filt_size <<= (u32)settings->pe_filt_num;
5314 return I40E_ERR_PARAM;
5317 switch (settings->pe_cntx_num) {
5318 case I40E_DMA_CNTX_SIZE_512:
5319 case I40E_DMA_CNTX_SIZE_1K:
5320 case I40E_DMA_CNTX_SIZE_2K:
5321 case I40E_DMA_CNTX_SIZE_4K:
5322 case I40E_DMA_CNTX_SIZE_8K:
5323 case I40E_DMA_CNTX_SIZE_16K:
5324 case I40E_DMA_CNTX_SIZE_32K:
5325 case I40E_DMA_CNTX_SIZE_64K:
5326 case I40E_DMA_CNTX_SIZE_128K:
5327 case I40E_DMA_CNTX_SIZE_256K:
5328 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5329 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5332 return I40E_ERR_PARAM;
5335 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5336 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5337 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5338 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5339 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5340 return I40E_ERR_INVALID_SIZE;
5342 return I40E_SUCCESS;
5346 * i40e_set_filter_control
5347 * @hw: pointer to the hardware structure
5348 * @settings: Filter control settings
5350 * Set the Queue Filters for PE/FCoE and enable filters required
5351 * for a single PF. It is expected that these settings are programmed
5352 * at the driver initialization time.
5354 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5355 struct i40e_filter_control_settings *settings)
5357 enum i40e_status_code ret = I40E_SUCCESS;
5358 u32 hash_lut_size = 0;
5362 return I40E_ERR_PARAM;
5364 /* Validate the input settings */
5365 ret = i40e_validate_filter_settings(hw, settings);
5369 /* Read the PF Queue Filter control register */
5370 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5372 /* Program required PE hash buckets for the PF */
5373 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5374 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5375 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5376 /* Program required PE contexts for the PF */
5377 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5378 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5379 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5381 /* Program required FCoE hash buckets for the PF */
5382 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5383 val |= ((u32)settings->fcoe_filt_num <<
5384 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5385 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5386 /* Program required FCoE DDP contexts for the PF */
5387 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5388 val |= ((u32)settings->fcoe_cntx_num <<
5389 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5390 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5392 /* Program Hash LUT size for the PF */
5393 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5394 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5396 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5397 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5399 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5400 if (settings->enable_fdir)
5401 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5402 if (settings->enable_ethtype)
5403 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5404 if (settings->enable_macvlan)
5405 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5407 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5409 return I40E_SUCCESS;
5413 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5414 * @hw: pointer to the hw struct
5415 * @mac_addr: MAC address to use in the filter
5416 * @ethtype: Ethertype to use in the filter
5417 * @flags: Flags that needs to be applied to the filter
5418 * @vsi_seid: seid of the control VSI
5419 * @queue: VSI queue number to send the packet to
5420 * @is_add: Add control packet filter if True else remove
5421 * @stats: Structure to hold information on control filter counts
5422 * @cmd_details: pointer to command details structure or NULL
5424 * This command will Add or Remove control packet filter for a control VSI.
5425 * In return it will update the total number of perfect filter count in
5428 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5429 u8 *mac_addr, u16 ethtype, u16 flags,
5430 u16 vsi_seid, u16 queue, bool is_add,
5431 struct i40e_control_filter_stats *stats,
5432 struct i40e_asq_cmd_details *cmd_details)
5434 struct i40e_aq_desc desc;
5435 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5436 (struct i40e_aqc_add_remove_control_packet_filter *)
5438 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5439 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5441 enum i40e_status_code status;
5444 return I40E_ERR_PARAM;
5447 i40e_fill_default_direct_cmd_desc(&desc,
5448 i40e_aqc_opc_add_control_packet_filter);
5449 cmd->queue = CPU_TO_LE16(queue);
5451 i40e_fill_default_direct_cmd_desc(&desc,
5452 i40e_aqc_opc_remove_control_packet_filter);
5456 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5457 I40E_NONDMA_TO_NONDMA);
5459 cmd->etype = CPU_TO_LE16(ethtype);
5460 cmd->flags = CPU_TO_LE16(flags);
5461 cmd->seid = CPU_TO_LE16(vsi_seid);
5463 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5465 if (!status && stats) {
5466 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5467 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5468 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5469 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5476 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5477 * @hw: pointer to the hw struct
5478 * @seid: VSI seid to add ethertype filter from
5480 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5481 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5484 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5485 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5486 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5487 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5488 enum i40e_status_code status;
5490 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5491 seid, 0, true, NULL,
5494 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5498 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5499 * @filters: list of cloud filters
5500 * @filter_count: length of list
5502 * There's an issue in the device where the Geneve VNI layout needs
5503 * to be shifted 1 byte over from the VxLAN VNI
5505 STATIC void i40e_fix_up_geneve_vni(
5506 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5509 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5512 for (i = 0; i < filter_count; i++) {
5516 tnl_type = (LE16_TO_CPU(f[i].flags) &
5517 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5518 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5519 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5520 ti = LE32_TO_CPU(f[i].tenant_id);
5521 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5527 * i40e_aq_add_cloud_filters
5528 * @hw: pointer to the hardware structure
5529 * @seid: VSI seid to add cloud filters from
5530 * @filters: Buffer which contains the filters to be added
5531 * @filter_count: number of filters contained in the buffer
5533 * Set the cloud filters for a given VSI. The contents of the
5534 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5535 * in by the caller of the function.
5538 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5540 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5543 struct i40e_aq_desc desc;
5544 struct i40e_aqc_add_remove_cloud_filters *cmd =
5545 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5546 enum i40e_status_code status;
5549 i40e_fill_default_direct_cmd_desc(&desc,
5550 i40e_aqc_opc_add_cloud_filters);
5552 buff_len = filter_count * sizeof(*filters);
5553 desc.datalen = CPU_TO_LE16(buff_len);
5554 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5555 cmd->num_filters = filter_count;
5556 cmd->seid = CPU_TO_LE16(seid);
5558 i40e_fix_up_geneve_vni(filters, filter_count);
5560 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5566 * i40e_aq_remove_cloud_filters
5567 * @hw: pointer to the hardware structure
5568 * @seid: VSI seid to remove cloud filters from
5569 * @filters: Buffer which contains the filters to be removed
5570 * @filter_count: number of filters contained in the buffer
5572 * Remove the cloud filters for a given VSI. The contents of the
5573 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5574 * in by the caller of the function.
5577 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5579 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5582 struct i40e_aq_desc desc;
5583 struct i40e_aqc_add_remove_cloud_filters *cmd =
5584 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5585 enum i40e_status_code status;
5588 i40e_fill_default_direct_cmd_desc(&desc,
5589 i40e_aqc_opc_remove_cloud_filters);
5591 buff_len = filter_count * sizeof(*filters);
5592 desc.datalen = CPU_TO_LE16(buff_len);
5593 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5594 cmd->num_filters = filter_count;
5595 cmd->seid = CPU_TO_LE16(seid);
5597 i40e_fix_up_geneve_vni(filters, filter_count);
5599 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5605 * i40e_aq_alternate_write
5606 * @hw: pointer to the hardware structure
5607 * @reg_addr0: address of first dword to be read
5608 * @reg_val0: value to be written under 'reg_addr0'
5609 * @reg_addr1: address of second dword to be read
5610 * @reg_val1: value to be written under 'reg_addr1'
5612 * Write one or two dwords to alternate structure. Fields are indicated
5613 * by 'reg_addr0' and 'reg_addr1' register numbers.
5616 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5617 u32 reg_addr0, u32 reg_val0,
5618 u32 reg_addr1, u32 reg_val1)
5620 struct i40e_aq_desc desc;
5621 struct i40e_aqc_alternate_write *cmd_resp =
5622 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5623 enum i40e_status_code status;
5625 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5626 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5627 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5628 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5629 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5631 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5637 * i40e_aq_alternate_write_indirect
5638 * @hw: pointer to the hardware structure
5639 * @addr: address of a first register to be modified
5640 * @dw_count: number of alternate structure fields to write
5641 * @buffer: pointer to the command buffer
5643 * Write 'dw_count' dwords from 'buffer' to alternate structure
5644 * starting at 'addr'.
5647 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5648 u32 addr, u32 dw_count, void *buffer)
5650 struct i40e_aq_desc desc;
5651 struct i40e_aqc_alternate_ind_write *cmd_resp =
5652 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5653 enum i40e_status_code status;
5656 return I40E_ERR_PARAM;
5658 /* Indirect command */
5659 i40e_fill_default_direct_cmd_desc(&desc,
5660 i40e_aqc_opc_alternate_write_indirect);
5662 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5663 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5664 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5665 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5667 cmd_resp->address = CPU_TO_LE32(addr);
5668 cmd_resp->length = CPU_TO_LE32(dw_count);
5670 status = i40e_asq_send_command(hw, &desc, buffer,
5671 I40E_LO_DWORD(4*dw_count), NULL);
5677 * i40e_aq_alternate_read
5678 * @hw: pointer to the hardware structure
5679 * @reg_addr0: address of first dword to be read
5680 * @reg_val0: pointer for data read from 'reg_addr0'
5681 * @reg_addr1: address of second dword to be read
5682 * @reg_val1: pointer for data read from 'reg_addr1'
5684 * Read one or two dwords from alternate structure. Fields are indicated
5685 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5686 * is not passed then only register at 'reg_addr0' is read.
5689 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5690 u32 reg_addr0, u32 *reg_val0,
5691 u32 reg_addr1, u32 *reg_val1)
5693 struct i40e_aq_desc desc;
5694 struct i40e_aqc_alternate_write *cmd_resp =
5695 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5696 enum i40e_status_code status;
5698 if (reg_val0 == NULL)
5699 return I40E_ERR_PARAM;
5701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5702 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5703 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5705 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5707 if (status == I40E_SUCCESS) {
5708 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5710 if (reg_val1 != NULL)
5711 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5718 * i40e_aq_alternate_read_indirect
5719 * @hw: pointer to the hardware structure
5720 * @addr: address of the alternate structure field
5721 * @dw_count: number of alternate structure fields to read
5722 * @buffer: pointer to the command buffer
5724 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5725 * place them in 'buffer'. The buffer should be allocated by caller.
5728 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5729 u32 addr, u32 dw_count, void *buffer)
5731 struct i40e_aq_desc desc;
5732 struct i40e_aqc_alternate_ind_write *cmd_resp =
5733 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5734 enum i40e_status_code status;
5737 return I40E_ERR_PARAM;
5739 /* Indirect command */
5740 i40e_fill_default_direct_cmd_desc(&desc,
5741 i40e_aqc_opc_alternate_read_indirect);
5743 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5744 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5745 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5746 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5748 cmd_resp->address = CPU_TO_LE32(addr);
5749 cmd_resp->length = CPU_TO_LE32(dw_count);
5751 status = i40e_asq_send_command(hw, &desc, buffer,
5752 I40E_LO_DWORD(4*dw_count), NULL);
5758 * i40e_aq_alternate_clear
5759 * @hw: pointer to the HW structure.
5761 * Clear the alternate structures of the port from which the function
5765 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5767 struct i40e_aq_desc desc;
5768 enum i40e_status_code status;
5770 i40e_fill_default_direct_cmd_desc(&desc,
5771 i40e_aqc_opc_alternate_clear_port);
5773 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5779 * i40e_aq_alternate_write_done
5780 * @hw: pointer to the HW structure.
5781 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5782 * @reset_needed: indicates the SW should trigger GLOBAL reset
5784 * Indicates to the FW that alternate structures have been changed.
5787 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5788 u8 bios_mode, bool *reset_needed)
5790 struct i40e_aq_desc desc;
5791 struct i40e_aqc_alternate_write_done *cmd =
5792 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5793 enum i40e_status_code status;
5795 if (reset_needed == NULL)
5796 return I40E_ERR_PARAM;
5798 i40e_fill_default_direct_cmd_desc(&desc,
5799 i40e_aqc_opc_alternate_write_done);
5801 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5803 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5804 if (!status && reset_needed)
5805 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5806 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5812 * i40e_aq_set_oem_mode
5813 * @hw: pointer to the HW structure.
5814 * @oem_mode: the OEM mode to be used
5816 * Sets the device to a specific operating mode. Currently the only supported
5817 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5820 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5823 struct i40e_aq_desc desc;
5824 struct i40e_aqc_alternate_write_done *cmd =
5825 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5826 enum i40e_status_code status;
5828 i40e_fill_default_direct_cmd_desc(&desc,
5829 i40e_aqc_opc_alternate_set_mode);
5831 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5833 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5839 * i40e_aq_resume_port_tx
5840 * @hw: pointer to the hardware structure
5841 * @cmd_details: pointer to command details structure or NULL
5843 * Resume port's Tx traffic
5845 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5846 struct i40e_asq_cmd_details *cmd_details)
5848 struct i40e_aq_desc desc;
5849 enum i40e_status_code status;
5851 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5853 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5859 * i40e_set_pci_config_data - store PCI bus info
5860 * @hw: pointer to hardware structure
5861 * @link_status: the link status word from PCI config space
5863 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5865 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5867 hw->bus.type = i40e_bus_type_pci_express;
5869 switch (link_status & I40E_PCI_LINK_WIDTH) {
5870 case I40E_PCI_LINK_WIDTH_1:
5871 hw->bus.width = i40e_bus_width_pcie_x1;
5873 case I40E_PCI_LINK_WIDTH_2:
5874 hw->bus.width = i40e_bus_width_pcie_x2;
5876 case I40E_PCI_LINK_WIDTH_4:
5877 hw->bus.width = i40e_bus_width_pcie_x4;
5879 case I40E_PCI_LINK_WIDTH_8:
5880 hw->bus.width = i40e_bus_width_pcie_x8;
5883 hw->bus.width = i40e_bus_width_unknown;
5887 switch (link_status & I40E_PCI_LINK_SPEED) {
5888 case I40E_PCI_LINK_SPEED_2500:
5889 hw->bus.speed = i40e_bus_speed_2500;
5891 case I40E_PCI_LINK_SPEED_5000:
5892 hw->bus.speed = i40e_bus_speed_5000;
5894 case I40E_PCI_LINK_SPEED_8000:
5895 hw->bus.speed = i40e_bus_speed_8000;
5898 hw->bus.speed = i40e_bus_speed_unknown;
5904 * i40e_aq_debug_dump
5905 * @hw: pointer to the hardware structure
5906 * @cluster_id: specific cluster to dump
5907 * @table_id: table id within cluster
5908 * @start_index: index of line in the block to read
5909 * @buff_size: dump buffer size
5910 * @buff: dump buffer
5911 * @ret_buff_size: actual buffer size returned
5912 * @ret_next_table: next block to read
5913 * @ret_next_index: next index to read
5915 * Dump internal FW/HW data for debug purposes.
5918 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5919 u8 table_id, u32 start_index, u16 buff_size,
5920 void *buff, u16 *ret_buff_size,
5921 u8 *ret_next_table, u32 *ret_next_index,
5922 struct i40e_asq_cmd_details *cmd_details)
5924 struct i40e_aq_desc desc;
5925 struct i40e_aqc_debug_dump_internals *cmd =
5926 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5927 struct i40e_aqc_debug_dump_internals *resp =
5928 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5929 enum i40e_status_code status;
5931 if (buff_size == 0 || !buff)
5932 return I40E_ERR_PARAM;
5934 i40e_fill_default_direct_cmd_desc(&desc,
5935 i40e_aqc_opc_debug_dump_internals);
5936 /* Indirect Command */
5937 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5938 if (buff_size > I40E_AQ_LARGE_BUF)
5939 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5941 cmd->cluster_id = cluster_id;
5942 cmd->table_id = table_id;
5943 cmd->idx = CPU_TO_LE32(start_index);
5945 desc.datalen = CPU_TO_LE16(buff_size);
5947 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5949 if (ret_buff_size != NULL)
5950 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5951 if (ret_next_table != NULL)
5952 *ret_next_table = resp->table_id;
5953 if (ret_next_index != NULL)
5954 *ret_next_index = LE32_TO_CPU(resp->idx);
5961 * i40e_read_bw_from_alt_ram
5962 * @hw: pointer to the hardware structure
5963 * @max_bw: pointer for max_bw read
5964 * @min_bw: pointer for min_bw read
5965 * @min_valid: pointer for bool that is true if min_bw is a valid value
5966 * @max_valid: pointer for bool that is true if max_bw is a valid value
5968 * Read bw from the alternate ram for the given pf
5970 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5971 u32 *max_bw, u32 *min_bw,
5972 bool *min_valid, bool *max_valid)
5974 enum i40e_status_code status;
5975 u32 max_bw_addr, min_bw_addr;
5977 /* Calculate the address of the min/max bw registers */
5978 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5979 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5980 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5981 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5982 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5983 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5985 /* Read the bandwidths from alt ram */
5986 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5987 min_bw_addr, min_bw);
5989 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5994 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6003 * i40e_aq_configure_partition_bw
6004 * @hw: pointer to the hardware structure
6005 * @bw_data: Buffer holding valid pfs and bw limits
6006 * @cmd_details: pointer to command details
6008 * Configure partitions guaranteed/max bw
6010 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6011 struct i40e_aqc_configure_partition_bw_data *bw_data,
6012 struct i40e_asq_cmd_details *cmd_details)
6014 enum i40e_status_code status;
6015 struct i40e_aq_desc desc;
6016 u16 bwd_size = sizeof(*bw_data);
6018 i40e_fill_default_direct_cmd_desc(&desc,
6019 i40e_aqc_opc_configure_partition_bw);
6021 /* Indirect command */
6022 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6023 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6025 desc.datalen = CPU_TO_LE16(bwd_size);
6027 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6033 * i40e_read_phy_register_clause22
6034 * @hw: pointer to the HW structure
6035 * @reg: register address in the page
6036 * @phy_adr: PHY address on MDIO interface
6037 * @value: PHY register value
6039 * Reads specified PHY register value
6041 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6042 u16 reg, u8 phy_addr, u16 *value)
6044 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6045 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6049 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6050 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6051 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6052 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6053 (I40E_GLGEN_MSCA_MDICMD_MASK);
6054 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6056 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6057 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6058 status = I40E_SUCCESS;
6061 i40e_usec_delay(10);
6066 i40e_debug(hw, I40E_DEBUG_PHY,
6067 "PHY: Can't write command to external PHY.\n");
6069 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6070 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6071 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6078 * i40e_write_phy_register_clause22
6079 * @hw: pointer to the HW structure
6080 * @reg: register address in the page
6081 * @phy_adr: PHY address on MDIO interface
6082 * @value: PHY register value
6084 * Writes specified PHY register value
6086 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6087 u16 reg, u8 phy_addr, u16 value)
6089 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6090 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6094 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6095 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6097 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6098 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6099 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6100 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6101 (I40E_GLGEN_MSCA_MDICMD_MASK);
6103 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6105 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6106 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6107 status = I40E_SUCCESS;
6110 i40e_usec_delay(10);
6118 * i40e_read_phy_register_clause45
6119 * @hw: pointer to the HW structure
6120 * @page: registers page number
6121 * @reg: register address in the page
6122 * @phy_adr: PHY address on MDIO interface
6123 * @value: PHY register value
6125 * Reads specified PHY register value
6127 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6128 u8 page, u16 reg, u8 phy_addr, u16 *value)
6130 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6133 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6135 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6136 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6137 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6138 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6139 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6140 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6141 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6142 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6144 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6145 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6146 status = I40E_SUCCESS;
6149 i40e_usec_delay(10);
6154 i40e_debug(hw, I40E_DEBUG_PHY,
6155 "PHY: Can't write command to external PHY.\n");
6159 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6160 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6161 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6162 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6163 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6164 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6165 status = I40E_ERR_TIMEOUT;
6167 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6169 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6170 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6171 status = I40E_SUCCESS;
6174 i40e_usec_delay(10);
6179 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6180 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6181 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6183 i40e_debug(hw, I40E_DEBUG_PHY,
6184 "PHY: Can't read register value from external PHY.\n");
6192 * i40e_write_phy_register_clause45
6193 * @hw: pointer to the HW structure
6194 * @page: registers page number
6195 * @reg: register address in the page
6196 * @phy_adr: PHY address on MDIO interface
6197 * @value: PHY register value
6199 * Writes value to specified PHY register
6201 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6202 u8 page, u16 reg, u8 phy_addr, u16 value)
6204 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6207 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6209 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6210 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6211 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6212 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6213 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6214 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6215 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6216 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6218 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6219 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6220 status = I40E_SUCCESS;
6223 i40e_usec_delay(10);
6227 i40e_debug(hw, I40E_DEBUG_PHY,
6228 "PHY: Can't write command to external PHY.\n");
6232 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6233 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6235 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6236 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6237 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6238 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6239 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6240 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6241 status = I40E_ERR_TIMEOUT;
6243 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6245 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6246 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6247 status = I40E_SUCCESS;
6250 i40e_usec_delay(10);
6259 * i40e_write_phy_register
6260 * @hw: pointer to the HW structure
6261 * @page: registers page number
6262 * @reg: register address in the page
6263 * @phy_adr: PHY address on MDIO interface
6264 * @value: PHY register value
6266 * Writes value to specified PHY register
6268 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6269 u8 page, u16 reg, u8 phy_addr, u16 value)
6271 enum i40e_status_code status;
6273 switch (hw->device_id) {
6274 case I40E_DEV_ID_1G_BASE_T_X722:
6275 status = i40e_write_phy_register_clause22(hw,
6276 reg, phy_addr, value);
6278 case I40E_DEV_ID_10G_BASE_T:
6279 case I40E_DEV_ID_10G_BASE_T4:
6280 case I40E_DEV_ID_10G_BASE_T_X722:
6281 case I40E_DEV_ID_25G_B:
6282 case I40E_DEV_ID_25G_SFP28:
6283 status = i40e_write_phy_register_clause45(hw,
6284 page, reg, phy_addr, value);
6287 status = I40E_ERR_UNKNOWN_PHY;
6295 * i40e_read_phy_register
6296 * @hw: pointer to the HW structure
6297 * @page: registers page number
6298 * @reg: register address in the page
6299 * @phy_adr: PHY address on MDIO interface
6300 * @value: PHY register value
6302 * Reads specified PHY register value
6304 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6305 u8 page, u16 reg, u8 phy_addr, u16 *value)
6307 enum i40e_status_code status;
6309 switch (hw->device_id) {
6310 case I40E_DEV_ID_1G_BASE_T_X722:
6311 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6314 case I40E_DEV_ID_10G_BASE_T:
6315 case I40E_DEV_ID_10G_BASE_T4:
6316 case I40E_DEV_ID_10G_BASE_T_X722:
6317 case I40E_DEV_ID_25G_B:
6318 case I40E_DEV_ID_25G_SFP28:
6319 status = i40e_read_phy_register_clause45(hw, page, reg,
6323 status = I40E_ERR_UNKNOWN_PHY;
6331 * i40e_get_phy_address
6332 * @hw: pointer to the HW structure
6333 * @dev_num: PHY port num that address we want
6334 * @phy_addr: Returned PHY address
6336 * Gets PHY address for current port
6338 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6340 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6341 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6343 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6347 * i40e_blink_phy_led
6348 * @hw: pointer to the HW structure
6349 * @time: time how long led will blinks in secs
6350 * @interval: gap between LED on and off in msecs
6352 * Blinks PHY link LED
6354 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6355 u32 time, u32 interval)
6357 enum i40e_status_code status = I40E_SUCCESS;
6362 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6366 i = rd32(hw, I40E_PFGEN_PORTNUM);
6367 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6368 phy_addr = i40e_get_phy_address(hw, port_num);
6370 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6372 status = i40e_read_phy_register_clause45(hw,
6373 I40E_PHY_COM_REG_PAGE,
6377 goto phy_blinking_end;
6379 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6381 status = i40e_write_phy_register_clause45(hw,
6382 I40E_PHY_COM_REG_PAGE,
6386 goto phy_blinking_end;
6391 if (time > 0 && interval > 0) {
6392 for (i = 0; i < time * 1000; i += interval) {
6393 status = i40e_read_phy_register_clause45(hw,
6394 I40E_PHY_COM_REG_PAGE,
6395 led_addr, phy_addr, &led_reg);
6397 goto restore_config;
6398 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6401 led_reg = I40E_PHY_LED_MANUAL_ON;
6402 status = i40e_write_phy_register_clause45(hw,
6403 I40E_PHY_COM_REG_PAGE,
6404 led_addr, phy_addr, led_reg);
6406 goto restore_config;
6407 i40e_msec_delay(interval);
6412 status = i40e_write_phy_register_clause45(hw,
6413 I40E_PHY_COM_REG_PAGE,
6414 led_addr, phy_addr, led_ctl);
6421 * i40e_led_get_phy - return current on/off mode
6422 * @hw: pointer to the hw struct
6423 * @led_addr: address of led register to use
6424 * @val: original value of register to use
6427 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6430 enum i40e_status_code status = I40E_SUCCESS;
6438 temp_addr = I40E_PHY_LED_PROV_REG_1;
6439 i = rd32(hw, I40E_PFGEN_PORTNUM);
6440 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6441 phy_addr = i40e_get_phy_address(hw, port_num);
6443 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6445 status = i40e_read_phy_register_clause45(hw,
6446 I40E_PHY_COM_REG_PAGE,
6447 temp_addr, phy_addr,
6452 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6453 *led_addr = temp_addr;
6462 * @hw: pointer to the HW structure
6463 * @on: true or false
6464 * @mode: original val plus bit for set or ignore
6465 * Set led's on or off when controlled by the PHY
6468 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6469 u16 led_addr, u32 mode)
6471 enum i40e_status_code status = I40E_SUCCESS;
6478 i = rd32(hw, I40E_PFGEN_PORTNUM);
6479 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6480 phy_addr = i40e_get_phy_address(hw, port_num);
6481 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6482 led_addr, phy_addr, &led_reg);
6486 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6488 status = i40e_write_phy_register_clause45(hw,
6489 I40E_PHY_COM_REG_PAGE,
6495 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6496 led_addr, phy_addr, &led_reg);
6498 goto restore_config;
6500 led_reg = I40E_PHY_LED_MANUAL_ON;
6503 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6504 led_addr, phy_addr, led_reg);
6506 goto restore_config;
6507 if (mode & I40E_PHY_LED_MODE_ORIG) {
6508 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6509 status = i40e_write_phy_register_clause45(hw,
6510 I40E_PHY_COM_REG_PAGE,
6511 led_addr, phy_addr, led_ctl);
6515 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6516 led_addr, phy_addr, led_ctl);
6519 #endif /* PF_DRIVER */
6522 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6523 * @hw: pointer to the hw struct
6524 * @reg_addr: register address
6525 * @reg_val: ptr to register value
6526 * @cmd_details: pointer to command details structure or NULL
6528 * Use the firmware to read the Rx control register,
6529 * especially useful if the Rx unit is under heavy pressure
6531 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6532 u32 reg_addr, u32 *reg_val,
6533 struct i40e_asq_cmd_details *cmd_details)
6535 struct i40e_aq_desc desc;
6536 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6537 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6538 enum i40e_status_code status;
6540 if (reg_val == NULL)
6541 return I40E_ERR_PARAM;
6543 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6545 cmd_resp->address = CPU_TO_LE32(reg_addr);
6547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6549 if (status == I40E_SUCCESS)
6550 *reg_val = LE32_TO_CPU(cmd_resp->value);
6556 * i40e_read_rx_ctl - read from an Rx control register
6557 * @hw: pointer to the hw struct
6558 * @reg_addr: register address
6560 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6562 enum i40e_status_code status = I40E_SUCCESS;
6567 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6568 if (!use_register) {
6570 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6571 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6578 /* if the AQ access failed, try the old-fashioned way */
6579 if (status || use_register)
6580 val = rd32(hw, reg_addr);
6586 * i40e_aq_rx_ctl_write_register
6587 * @hw: pointer to the hw struct
6588 * @reg_addr: register address
6589 * @reg_val: register value
6590 * @cmd_details: pointer to command details structure or NULL
6592 * Use the firmware to write to an Rx control register,
6593 * especially useful if the Rx unit is under heavy pressure
6595 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6596 u32 reg_addr, u32 reg_val,
6597 struct i40e_asq_cmd_details *cmd_details)
6599 struct i40e_aq_desc desc;
6600 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6601 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6602 enum i40e_status_code status;
6604 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6606 cmd->address = CPU_TO_LE32(reg_addr);
6607 cmd->value = CPU_TO_LE32(reg_val);
6609 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6615 * i40e_write_rx_ctl - write to an Rx control register
6616 * @hw: pointer to the hw struct
6617 * @reg_addr: register address
6618 * @reg_val: register value
6620 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6622 enum i40e_status_code status = I40E_SUCCESS;
6626 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6627 if (!use_register) {
6629 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6631 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6638 /* if the AQ access failed, try the old-fashioned way */
6639 if (status || use_register)
6640 wr32(hw, reg_addr, reg_val);
6645 * i40e_aq_send_msg_to_pf
6646 * @hw: pointer to the hardware structure
6647 * @v_opcode: opcodes for VF-PF communication
6648 * @v_retval: return error code
6649 * @msg: pointer to the msg buffer
6650 * @msglen: msg length
6651 * @cmd_details: pointer to command details
6653 * Send message to PF driver using admin queue. By default, this message
6654 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6655 * completion before returning.
6657 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6658 enum i40e_virtchnl_ops v_opcode,
6659 enum i40e_status_code v_retval,
6660 u8 *msg, u16 msglen,
6661 struct i40e_asq_cmd_details *cmd_details)
6663 struct i40e_aq_desc desc;
6664 struct i40e_asq_cmd_details details;
6665 enum i40e_status_code status;
6667 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6668 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6669 desc.cookie_high = CPU_TO_LE32(v_opcode);
6670 desc.cookie_low = CPU_TO_LE32(v_retval);
6672 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6673 | I40E_AQ_FLAG_RD));
6674 if (msglen > I40E_AQ_LARGE_BUF)
6675 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6676 desc.datalen = CPU_TO_LE16(msglen);
6679 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6680 details.async = true;
6681 cmd_details = &details;
6683 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6684 msglen, cmd_details);
6689 * i40e_vf_parse_hw_config
6690 * @hw: pointer to the hardware structure
6691 * @msg: pointer to the virtual channel VF resource structure
6693 * Given a VF resource message from the PF, populate the hw struct
6694 * with appropriate information.
6696 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6697 struct i40e_virtchnl_vf_resource *msg)
6699 struct i40e_virtchnl_vsi_resource *vsi_res;
6702 vsi_res = &msg->vsi_res[0];
6704 hw->dev_caps.num_vsis = msg->num_vsis;
6705 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6706 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6707 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6708 hw->dev_caps.dcb = msg->vf_offload_flags &
6709 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6710 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6711 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6712 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6713 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6714 for (i = 0; i < msg->num_vsis; i++) {
6715 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6716 i40e_memcpy(hw->mac.perm_addr,
6717 vsi_res->default_mac_addr,
6718 I40E_ETH_LENGTH_OF_ADDRESS,
6719 I40E_NONDMA_TO_NONDMA);
6720 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6721 I40E_ETH_LENGTH_OF_ADDRESS,
6722 I40E_NONDMA_TO_NONDMA);
6730 * @hw: pointer to the hardware structure
6732 * Send a VF_RESET message to the PF. Does not wait for response from PF
6733 * as none will be forthcoming. Immediately after calling this function,
6734 * the admin queue should be shut down and (optionally) reinitialized.
6736 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6738 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6739 I40E_SUCCESS, NULL, 0, NULL);
6741 #endif /* VF_DRIVER */
6745 * i40e_aq_set_arp_proxy_config
6746 * @hw: pointer to the HW structure
6747 * @proxy_config - pointer to proxy config command table struct
6748 * @cmd_details: pointer to command details
6750 * Set ARP offload parameters from pre-populated
6751 * i40e_aqc_arp_proxy_data struct
6753 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6754 struct i40e_aqc_arp_proxy_data *proxy_config,
6755 struct i40e_asq_cmd_details *cmd_details)
6757 struct i40e_aq_desc desc;
6758 enum i40e_status_code status;
6761 return I40E_ERR_PARAM;
6763 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6765 desc.params.external.addr_high =
6766 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6767 desc.params.external.addr_low =
6768 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6770 status = i40e_asq_send_command(hw, &desc, proxy_config,
6771 sizeof(struct i40e_aqc_arp_proxy_data),
6778 * i40e_aq_opc_set_ns_proxy_table_entry
6779 * @hw: pointer to the HW structure
6780 * @ns_proxy_table_entry: pointer to NS table entry command struct
6781 * @cmd_details: pointer to command details
6783 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6784 * from pre-populated i40e_aqc_ns_proxy_data struct
6786 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6787 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6788 struct i40e_asq_cmd_details *cmd_details)
6790 struct i40e_aq_desc desc;
6791 enum i40e_status_code status;
6793 if (!ns_proxy_table_entry)
6794 return I40E_ERR_PARAM;
6796 i40e_fill_default_direct_cmd_desc(&desc,
6797 i40e_aqc_opc_set_ns_proxy_table_entry);
6799 desc.params.external.addr_high =
6800 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6801 desc.params.external.addr_low =
6802 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6804 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6805 sizeof(struct i40e_aqc_ns_proxy_data),
6812 * i40e_aq_set_clear_wol_filter
6813 * @hw: pointer to the hw struct
6814 * @filter_index: index of filter to modify (0-7)
6815 * @filter: buffer containing filter to be set
6816 * @set_filter: true to set filter, false to clear filter
6817 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6818 * if false, pass through packets may cause wake-up
6819 * @filter_valid: true if filter action is valid
6820 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6821 * @cmd_details: pointer to command details structure or NULL
6823 * Set or clear WoL filter for port attached to the PF
6825 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6827 struct i40e_aqc_set_wol_filter_data *filter,
6828 bool set_filter, bool no_wol_tco,
6829 bool filter_valid, bool no_wol_tco_valid,
6830 struct i40e_asq_cmd_details *cmd_details)
6832 struct i40e_aq_desc desc;
6833 struct i40e_aqc_set_wol_filter *cmd =
6834 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6835 enum i40e_status_code status;
6837 u16 valid_flags = 0;
6840 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6842 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6843 return I40E_ERR_PARAM;
6844 cmd->filter_index = CPU_TO_LE16(filter_index);
6848 return I40E_ERR_PARAM;
6849 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6850 buff_len = sizeof(*filter);
6853 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6854 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6857 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6858 if (no_wol_tco_valid)
6859 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6860 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6862 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6863 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6865 status = i40e_asq_send_command(hw, &desc, filter,
6866 buff_len, cmd_details);
6872 * i40e_aq_get_wake_event_reason
6873 * @hw: pointer to the hw struct
6874 * @wake_reason: return value, index of matching filter
6875 * @cmd_details: pointer to command details structure or NULL
6877 * Get information for the reason of a Wake Up event
6879 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6881 struct i40e_asq_cmd_details *cmd_details)
6883 struct i40e_aq_desc desc;
6884 struct i40e_aqc_get_wake_reason_completion *resp =
6885 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6886 enum i40e_status_code status;
6888 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6890 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6892 if (status == I40E_SUCCESS)
6893 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6898 #endif /* X722_SUPPORT */