drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  19 #else
  20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  21 #endif
  22 {
  23         enum i40e_status_code status = I40E_SUCCESS;
  24
  25         DEBUGFUNC("i40e_set_mac_type\n");
  26
  27         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  28                 switch (hw->device_id) {
  29                 case I40E_DEV_ID_SFP_XL710:
  30                 case I40E_DEV_ID_QEMU:
  31                 case I40E_DEV_ID_KX_B:
  32                 case I40E_DEV_ID_KX_C:
  33                 case I40E_DEV_ID_QSFP_A:
  34                 case I40E_DEV_ID_QSFP_B:
  35                 case I40E_DEV_ID_QSFP_C:
  36                 case I40E_DEV_ID_10G_BASE_T:
  37                 case I40E_DEV_ID_10G_BASE_T4:
  38                 case I40E_DEV_ID_20G_KR2:
  39                 case I40E_DEV_ID_20G_KR2_A:
  40                 case I40E_DEV_ID_25G_B:
  41                 case I40E_DEV_ID_25G_SFP28:
  42                         hw->mac.type = I40E_MAC_XL710;
  43                         break;
  44 #ifdef X722_A0_SUPPORT
  45                 case I40E_DEV_ID_X722_A0:
  46 #endif
  47                 case I40E_DEV_ID_KX_X722:
  48                 case I40E_DEV_ID_QSFP_X722:
  49                 case I40E_DEV_ID_SFP_X722:
  50                 case I40E_DEV_ID_1G_BASE_T_X722:
  51                 case I40E_DEV_ID_10G_BASE_T_X722:
  52                 case I40E_DEV_ID_SFP_I_X722:
  53                         hw->mac.type = I40E_MAC_X722;
  54                         break;
  55 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  56                 case I40E_DEV_ID_X722_VF:
  57 #ifdef X722_A0_SUPPORT
  58                 case I40E_DEV_ID_X722_A0_VF:
  59 #endif
  60                         hw->mac.type = I40E_MAC_X722_VF;
  61                         break;
  62 #endif /* INTEGRATED_VF || VF_DRIVER */
  63 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  64                 case I40E_DEV_ID_VF:
  65                 case I40E_DEV_ID_VF_HV:
  66                 case I40E_DEV_ID_ADAPTIVE_VF:
  67                         hw->mac.type = I40E_MAC_VF;
  68                         break;
  69 #endif
  70                 default:
  71                         hw->mac.type = I40E_MAC_GENERIC;
  72                         break;
  73                 }
  74         } else {
  75                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  76         }
  77
  78         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  79                   hw->mac.type, status);
  80         return status;
  81 }
  82
  83 /**
  84  * i40e_aq_str - convert AQ err code to a string
  85  * @hw: pointer to the HW structure
  86  * @aq_err: the AQ error code to convert
  87  **/
  88 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  89 {
  90         switch (aq_err) {
  91         case I40E_AQ_RC_OK:
  92                 return "OK";
  93         case I40E_AQ_RC_EPERM:
  94                 return "I40E_AQ_RC_EPERM";
  95         case I40E_AQ_RC_ENOENT:
  96                 return "I40E_AQ_RC_ENOENT";
  97         case I40E_AQ_RC_ESRCH:
  98                 return "I40E_AQ_RC_ESRCH";
  99         case I40E_AQ_RC_EINTR:
 100                 return "I40E_AQ_RC_EINTR";
 101         case I40E_AQ_RC_EIO:
 102                 return "I40E_AQ_RC_EIO";
 103         case I40E_AQ_RC_ENXIO:
 104                 return "I40E_AQ_RC_ENXIO";
 105         case I40E_AQ_RC_E2BIG:
 106                 return "I40E_AQ_RC_E2BIG";
 107         case I40E_AQ_RC_EAGAIN:
 108                 return "I40E_AQ_RC_EAGAIN";
 109         case I40E_AQ_RC_ENOMEM:
 110                 return "I40E_AQ_RC_ENOMEM";
 111         case I40E_AQ_RC_EACCES:
 112                 return "I40E_AQ_RC_EACCES";
 113         case I40E_AQ_RC_EFAULT:
 114                 return "I40E_AQ_RC_EFAULT";
 115         case I40E_AQ_RC_EBUSY:
 116                 return "I40E_AQ_RC_EBUSY";
 117         case I40E_AQ_RC_EEXIST:
 118                 return "I40E_AQ_RC_EEXIST";
 119         case I40E_AQ_RC_EINVAL:
 120                 return "I40E_AQ_RC_EINVAL";
 121         case I40E_AQ_RC_ENOTTY:
 122                 return "I40E_AQ_RC_ENOTTY";
 123         case I40E_AQ_RC_ENOSPC:
 124                 return "I40E_AQ_RC_ENOSPC";
 125         case I40E_AQ_RC_ENOSYS:
 126                 return "I40E_AQ_RC_ENOSYS";
 127         case I40E_AQ_RC_ERANGE:
 128                 return "I40E_AQ_RC_ERANGE";
 129         case I40E_AQ_RC_EFLUSHED:
 130                 return "I40E_AQ_RC_EFLUSHED";
 131         case I40E_AQ_RC_BAD_ADDR:
 132                 return "I40E_AQ_RC_BAD_ADDR";
 133         case I40E_AQ_RC_EMODE:
 134                 return "I40E_AQ_RC_EMODE";
 135         case I40E_AQ_RC_EFBIG:
 136                 return "I40E_AQ_RC_EFBIG";
 137         }
 138
 139         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 140         return hw->err_str;
 141 }
 142
 143 /**
 144  * i40e_stat_str - convert status err code to a string
 145  * @hw: pointer to the HW structure
 146  * @stat_err: the status error code to convert
 147  **/
 148 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 149 {
 150         switch (stat_err) {
 151         case I40E_SUCCESS:
 152                 return "OK";
 153         case I40E_ERR_NVM:
 154                 return "I40E_ERR_NVM";
 155         case I40E_ERR_NVM_CHECKSUM:
 156                 return "I40E_ERR_NVM_CHECKSUM";
 157         case I40E_ERR_PHY:
 158                 return "I40E_ERR_PHY";
 159         case I40E_ERR_CONFIG:
 160                 return "I40E_ERR_CONFIG";
 161         case I40E_ERR_PARAM:
 162                 return "I40E_ERR_PARAM";
 163         case I40E_ERR_MAC_TYPE:
 164                 return "I40E_ERR_MAC_TYPE";
 165         case I40E_ERR_UNKNOWN_PHY:
 166                 return "I40E_ERR_UNKNOWN_PHY";
 167         case I40E_ERR_LINK_SETUP:
 168                 return "I40E_ERR_LINK_SETUP";
 169         case I40E_ERR_ADAPTER_STOPPED:
 170                 return "I40E_ERR_ADAPTER_STOPPED";
 171         case I40E_ERR_INVALID_MAC_ADDR:
 172                 return "I40E_ERR_INVALID_MAC_ADDR";
 173         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 174                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 175         case I40E_ERR_MASTER_REQUESTS_PENDING:
 176                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 177         case I40E_ERR_INVALID_LINK_SETTINGS:
 178                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 179         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 180                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 181         case I40E_ERR_RESET_FAILED:
 182                 return "I40E_ERR_RESET_FAILED";
 183         case I40E_ERR_SWFW_SYNC:
 184                 return "I40E_ERR_SWFW_SYNC";
 185         case I40E_ERR_NO_AVAILABLE_VSI:
 186                 return "I40E_ERR_NO_AVAILABLE_VSI";
 187         case I40E_ERR_NO_MEMORY:
 188                 return "I40E_ERR_NO_MEMORY";
 189         case I40E_ERR_BAD_PTR:
 190                 return "I40E_ERR_BAD_PTR";
 191         case I40E_ERR_RING_FULL:
 192                 return "I40E_ERR_RING_FULL";
 193         case I40E_ERR_INVALID_PD_ID:
 194                 return "I40E_ERR_INVALID_PD_ID";
 195         case I40E_ERR_INVALID_QP_ID:
 196                 return "I40E_ERR_INVALID_QP_ID";
 197         case I40E_ERR_INVALID_CQ_ID:
 198                 return "I40E_ERR_INVALID_CQ_ID";
 199         case I40E_ERR_INVALID_CEQ_ID:
 200                 return "I40E_ERR_INVALID_CEQ_ID";
 201         case I40E_ERR_INVALID_AEQ_ID:
 202                 return "I40E_ERR_INVALID_AEQ_ID";
 203         case I40E_ERR_INVALID_SIZE:
 204                 return "I40E_ERR_INVALID_SIZE";
 205         case I40E_ERR_INVALID_ARP_INDEX:
 206                 return "I40E_ERR_INVALID_ARP_INDEX";
 207         case I40E_ERR_INVALID_FPM_FUNC_ID:
 208                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 209         case I40E_ERR_QP_INVALID_MSG_SIZE:
 210                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 211         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 212                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 213         case I40E_ERR_INVALID_FRAG_COUNT:
 214                 return "I40E_ERR_INVALID_FRAG_COUNT";
 215         case I40E_ERR_QUEUE_EMPTY:
 216                 return "I40E_ERR_QUEUE_EMPTY";
 217         case I40E_ERR_INVALID_ALIGNMENT:
 218                 return "I40E_ERR_INVALID_ALIGNMENT";
 219         case I40E_ERR_FLUSHED_QUEUE:
 220                 return "I40E_ERR_FLUSHED_QUEUE";
 221         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 222                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 223         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 224                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 225         case I40E_ERR_TIMEOUT:
 226                 return "I40E_ERR_TIMEOUT";
 227         case I40E_ERR_OPCODE_MISMATCH:
 228                 return "I40E_ERR_OPCODE_MISMATCH";
 229         case I40E_ERR_CQP_COMPL_ERROR:
 230                 return "I40E_ERR_CQP_COMPL_ERROR";
 231         case I40E_ERR_INVALID_VF_ID:
 232                 return "I40E_ERR_INVALID_VF_ID";
 233         case I40E_ERR_INVALID_HMCFN_ID:
 234                 return "I40E_ERR_INVALID_HMCFN_ID";
 235         case I40E_ERR_BACKING_PAGE_ERROR:
 236                 return "I40E_ERR_BACKING_PAGE_ERROR";
 237         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 238                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 239         case I40E_ERR_INVALID_PBLE_INDEX:
 240                 return "I40E_ERR_INVALID_PBLE_INDEX";
 241         case I40E_ERR_INVALID_SD_INDEX:
 242                 return "I40E_ERR_INVALID_SD_INDEX";
 243         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 244                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 245         case I40E_ERR_INVALID_SD_TYPE:
 246                 return "I40E_ERR_INVALID_SD_TYPE";
 247         case I40E_ERR_MEMCPY_FAILED:
 248                 return "I40E_ERR_MEMCPY_FAILED";
 249         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 250                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 251         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 252                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 253         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 254                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 255         case I40E_ERR_SRQ_ENABLED:
 256                 return "I40E_ERR_SRQ_ENABLED";
 257         case I40E_ERR_ADMIN_QUEUE_ERROR:
 258                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 259         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 260                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 261         case I40E_ERR_BUF_TOO_SHORT:
 262                 return "I40E_ERR_BUF_TOO_SHORT";
 263         case I40E_ERR_ADMIN_QUEUE_FULL:
 264                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 265         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 266                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 267         case I40E_ERR_BAD_IWARP_CQE:
 268                 return "I40E_ERR_BAD_IWARP_CQE";
 269         case I40E_ERR_NVM_BLANK_MODE:
 270                 return "I40E_ERR_NVM_BLANK_MODE";
 271         case I40E_ERR_NOT_IMPLEMENTED:
 272                 return "I40E_ERR_NOT_IMPLEMENTED";
 273         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 274                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 275         case I40E_ERR_DIAG_TEST_FAILED:
 276                 return "I40E_ERR_DIAG_TEST_FAILED";
 277         case I40E_ERR_NOT_READY:
 278                 return "I40E_ERR_NOT_READY";
 279         case I40E_NOT_SUPPORTED:
 280                 return "I40E_NOT_SUPPORTED";
 281         case I40E_ERR_FIRMWARE_API_VERSION:
 282                 return "I40E_ERR_FIRMWARE_API_VERSION";
 283         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 284                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 285         }
 286
 287         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 288         return hw->err_str;
 289 }
 290
 291 /**
 292  * i40e_debug_aq
 293  * @hw: debug mask related to admin queue
 294  * @mask: debug mask
 295  * @desc: pointer to admin queue descriptor
 296  * @buffer: pointer to command buffer
 297  * @buf_len: max length of buffer
 298  *
 299  * Dumps debug log about adminq command with descriptor contents.
 300  **/
 301 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 302                    void *buffer, u16 buf_len)
 303 {
 304         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 305         u8 *buf = (u8 *)buffer;
 306         u16 len;
 307         u16 i = 0;
 308
 309         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 310                 return;
 311
 312         len = LE16_TO_CPU(aq_desc->datalen);
 313
 314         i40e_debug(hw, mask,
 315                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 316                    LE16_TO_CPU(aq_desc->opcode),
 317                    LE16_TO_CPU(aq_desc->flags),
 318                    LE16_TO_CPU(aq_desc->datalen),
 319                    LE16_TO_CPU(aq_desc->retval));
 320         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 321                    LE32_TO_CPU(aq_desc->cookie_high),
 322                    LE32_TO_CPU(aq_desc->cookie_low));
 323         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 324                    LE32_TO_CPU(aq_desc->params.internal.param0),
 325                    LE32_TO_CPU(aq_desc->params.internal.param1));
 326         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 327                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 328                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 329
 330         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 331                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 332                 if (buf_len < len)
 333                         len = buf_len;
 334                 /* write the full 16-byte chunks */
 335                 for (i = 0; i < (len - 16); i += 16)
 336                         i40e_debug(hw, mask,
 337                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 338                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 339                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 340                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 341                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 342                 /* the most we could have left is 16 bytes, pad with zeros */
 343                 if (i < len) {
 344                         char d_buf[16];
 345                         int j, i_sav;
 346
 347                         i_sav = i;
 348                         memset(d_buf, 0, sizeof(d_buf));
 349                         for (j = 0; i < len; j++, i++)
 350                                 d_buf[j] = buf[i];
 351                         i40e_debug(hw, mask,
 352                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 353                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 354                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 355                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 356                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 357                 }
 358         }
 359 }
 360
 361 /**
 362  * i40e_check_asq_alive
 363  * @hw: pointer to the hw struct
 364  *
 365  * Returns true if Queue is enabled else false.
 366  **/
 367 bool i40e_check_asq_alive(struct i40e_hw *hw)
 368 {
 369         if (hw->aq.asq.len)
 370 #ifdef PF_DRIVER
 371 #ifdef INTEGRATED_VF
 372                 if (!i40e_is_vf(hw))
 373                         return !!(rd32(hw, hw->aq.asq.len) &
 374                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 375 #else
 376                 return !!(rd32(hw, hw->aq.asq.len) &
 377                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 378 #endif /* INTEGRATED_VF */
 379 #endif /* PF_DRIVER */
 380 #ifdef VF_DRIVER
 381 #ifdef INTEGRATED_VF
 382                 if (i40e_is_vf(hw))
 383                         return !!(rd32(hw, hw->aq.asq.len) &
 384                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 385 #else
 386                 return !!(rd32(hw, hw->aq.asq.len) &
 387                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 388 #endif /* INTEGRATED_VF */
 389 #endif /* VF_DRIVER */
 390         return false;
 391 }
 392
 393 /**
 394  * i40e_aq_queue_shutdown
 395  * @hw: pointer to the hw struct
 396  * @unloading: is the driver unloading itself
 397  *
 398  * Tell the Firmware that we're shutting down the AdminQ and whether
 399  * or not the driver is unloading as well.
 400  **/
 401 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 402                                              bool unloading)
 403 {
 404         struct i40e_aq_desc desc;
 405         struct i40e_aqc_queue_shutdown *cmd =
 406                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 407         enum i40e_status_code status;
 408
 409         i40e_fill_default_direct_cmd_desc(&desc,
 410                                           i40e_aqc_opc_queue_shutdown);
 411
 412         if (unloading)
 413                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 414         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 415
 416         return status;
 417 }
 418
 419 /**
 420  * i40e_aq_get_set_rss_lut
 421  * @hw: pointer to the hardware structure
 422  * @vsi_id: vsi fw index
 423  * @pf_lut: for PF table set true, for VSI table set false
 424  * @lut: pointer to the lut buffer provided by the caller
 425  * @lut_size: size of the lut buffer
 426  * @set: set true to set the table, false to get the table
 427  *
 428  * Internal function to get or set RSS look up table
 429  **/
 430 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 431                                                      u16 vsi_id, bool pf_lut,
 432                                                      u8 *lut, u16 lut_size,
 433                                                      bool set)
 434 {
 435         enum i40e_status_code status;
 436         struct i40e_aq_desc desc;
 437         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 438                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 439
 440         if (set)
 441                 i40e_fill_default_direct_cmd_desc(&desc,
 442                                                   i40e_aqc_opc_set_rss_lut);
 443         else
 444                 i40e_fill_default_direct_cmd_desc(&desc,
 445                                                   i40e_aqc_opc_get_rss_lut);
 446
 447         /* Indirect command */
 448         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 449         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 450
 451         cmd_resp->vsi_id =
 452                         CPU_TO_LE16((u16)((vsi_id <<
 453                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 454                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 455         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 456
 457         if (pf_lut)
 458                 cmd_resp->flags |= CPU_TO_LE16((u16)
 459                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 460                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 461                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 462         else
 463                 cmd_resp->flags |= CPU_TO_LE16((u16)
 464                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 465                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 466                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 467
 468         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 469
 470         return status;
 471 }
 472
 473 /**
 474  * i40e_aq_get_rss_lut
 475  * @hw: pointer to the hardware structure
 476  * @vsi_id: vsi fw index
 477  * @pf_lut: for PF table set true, for VSI table set false
 478  * @lut: pointer to the lut buffer provided by the caller
 479  * @lut_size: size of the lut buffer
 480  *
 481  * get the RSS lookup table, PF or VSI type
 482  **/
 483 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 484                                           bool pf_lut, u8 *lut, u16 lut_size)
 485 {
 486         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 487                                        false);
 488 }
 489
 490 /**
 491  * i40e_aq_set_rss_lut
 492  * @hw: pointer to the hardware structure
 493  * @vsi_id: vsi fw index
 494  * @pf_lut: for PF table set true, for VSI table set false
 495  * @lut: pointer to the lut buffer provided by the caller
 496  * @lut_size: size of the lut buffer
 497  *
 498  * set the RSS lookup table, PF or VSI type
 499  **/
 500 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 501                                           bool pf_lut, u8 *lut, u16 lut_size)
 502 {
 503         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 504 }
 505
 506 /**
 507  * i40e_aq_get_set_rss_key
 508  * @hw: pointer to the hw struct
 509  * @vsi_id: vsi fw index
 510  * @key: pointer to key info struct
 511  * @set: set true to set the key, false to get the key
 512  *
 513  * get the RSS key per VSI
 514  **/
 515 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 516                                       u16 vsi_id,
 517                                       struct i40e_aqc_get_set_rss_key_data *key,
 518                                       bool set)
 519 {
 520         enum i40e_status_code status;
 521         struct i40e_aq_desc desc;
 522         struct i40e_aqc_get_set_rss_key *cmd_resp =
 523                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 524         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 525
 526         if (set)
 527                 i40e_fill_default_direct_cmd_desc(&desc,
 528                                                   i40e_aqc_opc_set_rss_key);
 529         else
 530                 i40e_fill_default_direct_cmd_desc(&desc,
 531                                                   i40e_aqc_opc_get_rss_key);
 532
 533         /* Indirect command */
 534         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 535         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 536
 537         cmd_resp->vsi_id =
 538                         CPU_TO_LE16((u16)((vsi_id <<
 539                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 540                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 541         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 542
 543         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 544
 545         return status;
 546 }
 547
 548 /**
 549  * i40e_aq_get_rss_key
 550  * @hw: pointer to the hw struct
 551  * @vsi_id: vsi fw index
 552  * @key: pointer to key info struct
 553  *
 554  **/
 555 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 556                                       u16 vsi_id,
 557                                       struct i40e_aqc_get_set_rss_key_data *key)
 558 {
 559         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 560 }
 561
 562 /**
 563  * i40e_aq_set_rss_key
 564  * @hw: pointer to the hw struct
 565  * @vsi_id: vsi fw index
 566  * @key: pointer to key info struct
 567  *
 568  * set the RSS key per VSI
 569  **/
 570 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 571                                       u16 vsi_id,
 572                                       struct i40e_aqc_get_set_rss_key_data *key)
 573 {
 574         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 575 }
 576
 577 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 578  * hardware to a bit-field that can be used by SW to more easily determine the
 579  * packet type.
 580  *
 581  * Macros are used to shorten the table lines and make this table human
 582  * readable.
 583  *
 584  * We store the PTYPE in the top byte of the bit field - this is just so that
 585  * we can check that the table doesn't have a row missing, as the index into
 586  * the table should be the PTYPE.
 587  *
 588  * Typical work flow:
 589  *
 590  * IF NOT i40e_ptype_lookup[ptype].known
 591  * THEN
 592  *      Packet is unknown
 593  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 594  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 595  * ELSE
 596  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 597  * ENDIF
 598  */
 599
 600 /* macro to make the table lines short */
 601 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 602         {       PTYPE, \
 603                 1, \
 604                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 605                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 606                 I40E_RX_PTYPE_##OUTER_FRAG, \
 607                 I40E_RX_PTYPE_TUNNEL_##T, \
 608                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 609                 I40E_RX_PTYPE_##TEF, \
 610                 I40E_RX_PTYPE_INNER_PROT_##I, \
 611                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 612
 613 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 614                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 615
 616 /* shorter macros makes the table fit but are terse */
 617 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 618 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 619 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 620
 621 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 622 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 623         /* L2 Packet types */
 624         I40E_PTT_UNUSED_ENTRY(0),
 625         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 626         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 627         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 628         I40E_PTT_UNUSED_ENTRY(4),
 629         I40E_PTT_UNUSED_ENTRY(5),
 630         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 631         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 632         I40E_PTT_UNUSED_ENTRY(8),
 633         I40E_PTT_UNUSED_ENTRY(9),
 634         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 635         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 636         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 637         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 638         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 639         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 640         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 641         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 642         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646
 647         /* Non Tunneled IPv4 */
 648         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 651         I40E_PTT_UNUSED_ENTRY(25),
 652         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 653         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 654         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 655
 656         /* IPv4 --> IPv4 */
 657         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 658         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 659         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 660         I40E_PTT_UNUSED_ENTRY(32),
 661         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 662         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 663         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 664
 665         /* IPv4 --> IPv6 */
 666         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 667         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 668         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 669         I40E_PTT_UNUSED_ENTRY(39),
 670         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 671         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 672         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 673
 674         /* IPv4 --> GRE/NAT */
 675         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 676
 677         /* IPv4 --> GRE/NAT --> IPv4 */
 678         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 679         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 680         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(47),
 682         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 683         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 684         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> GRE/NAT --> IPv6 */
 687         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 688         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 689         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(54),
 691         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 692         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 693         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> GRE/NAT --> MAC */
 696         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 697
 698         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 699         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 700         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 701         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 702         I40E_PTT_UNUSED_ENTRY(62),
 703         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 704         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 705         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 706
 707         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 708         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 709         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 710         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(69),
 712         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 713         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 714         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 717         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 718
 719         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 720         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 721         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 722         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 723         I40E_PTT_UNUSED_ENTRY(77),
 724         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 725         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 726         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 727
 728         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 729         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 730         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 731         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(84),
 733         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 734         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 735         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 736
 737         /* Non Tunneled IPv6 */
 738         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 739         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 740         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(91),
 742         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 743         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 744         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 745
 746         /* IPv6 --> IPv4 */
 747         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 748         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 749         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 750         I40E_PTT_UNUSED_ENTRY(98),
 751         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 752         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 753         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 754
 755         /* IPv6 --> IPv6 */
 756         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 757         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 758         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 759         I40E_PTT_UNUSED_ENTRY(105),
 760         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 761         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 762         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 763
 764         /* IPv6 --> GRE/NAT */
 765         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 766
 767         /* IPv6 --> GRE/NAT -> IPv4 */
 768         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 769         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 770         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 771         I40E_PTT_UNUSED_ENTRY(113),
 772         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 773         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 774         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> GRE/NAT -> IPv6 */
 777         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 778         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 779         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(120),
 781         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 782         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 783         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> GRE/NAT -> MAC */
 786         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 787
 788         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 789         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 790         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 791         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 792         I40E_PTT_UNUSED_ENTRY(128),
 793         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 794         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 795         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 796
 797         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 798         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 799         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 800         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(135),
 802         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 803         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 804         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 807         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 808
 809         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 810         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 811         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 812         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 813         I40E_PTT_UNUSED_ENTRY(143),
 814         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 815         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 816         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 817
 818         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 819         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 820         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 821         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(150),
 823         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 824         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 825         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 826
 827         /* unused entries */
 828         I40E_PTT_UNUSED_ENTRY(154),
 829         I40E_PTT_UNUSED_ENTRY(155),
 830         I40E_PTT_UNUSED_ENTRY(156),
 831         I40E_PTT_UNUSED_ENTRY(157),
 832         I40E_PTT_UNUSED_ENTRY(158),
 833         I40E_PTT_UNUSED_ENTRY(159),
 834
 835         I40E_PTT_UNUSED_ENTRY(160),
 836         I40E_PTT_UNUSED_ENTRY(161),
 837         I40E_PTT_UNUSED_ENTRY(162),
 838         I40E_PTT_UNUSED_ENTRY(163),
 839         I40E_PTT_UNUSED_ENTRY(164),
 840         I40E_PTT_UNUSED_ENTRY(165),
 841         I40E_PTT_UNUSED_ENTRY(166),
 842         I40E_PTT_UNUSED_ENTRY(167),
 843         I40E_PTT_UNUSED_ENTRY(168),
 844         I40E_PTT_UNUSED_ENTRY(169),
 845
 846         I40E_PTT_UNUSED_ENTRY(170),
 847         I40E_PTT_UNUSED_ENTRY(171),
 848         I40E_PTT_UNUSED_ENTRY(172),
 849         I40E_PTT_UNUSED_ENTRY(173),
 850         I40E_PTT_UNUSED_ENTRY(174),
 851         I40E_PTT_UNUSED_ENTRY(175),
 852         I40E_PTT_UNUSED_ENTRY(176),
 853         I40E_PTT_UNUSED_ENTRY(177),
 854         I40E_PTT_UNUSED_ENTRY(178),
 855         I40E_PTT_UNUSED_ENTRY(179),
 856
 857         I40E_PTT_UNUSED_ENTRY(180),
 858         I40E_PTT_UNUSED_ENTRY(181),
 859         I40E_PTT_UNUSED_ENTRY(182),
 860         I40E_PTT_UNUSED_ENTRY(183),
 861         I40E_PTT_UNUSED_ENTRY(184),
 862         I40E_PTT_UNUSED_ENTRY(185),
 863         I40E_PTT_UNUSED_ENTRY(186),
 864         I40E_PTT_UNUSED_ENTRY(187),
 865         I40E_PTT_UNUSED_ENTRY(188),
 866         I40E_PTT_UNUSED_ENTRY(189),
 867
 868         I40E_PTT_UNUSED_ENTRY(190),
 869         I40E_PTT_UNUSED_ENTRY(191),
 870         I40E_PTT_UNUSED_ENTRY(192),
 871         I40E_PTT_UNUSED_ENTRY(193),
 872         I40E_PTT_UNUSED_ENTRY(194),
 873         I40E_PTT_UNUSED_ENTRY(195),
 874         I40E_PTT_UNUSED_ENTRY(196),
 875         I40E_PTT_UNUSED_ENTRY(197),
 876         I40E_PTT_UNUSED_ENTRY(198),
 877         I40E_PTT_UNUSED_ENTRY(199),
 878
 879         I40E_PTT_UNUSED_ENTRY(200),
 880         I40E_PTT_UNUSED_ENTRY(201),
 881         I40E_PTT_UNUSED_ENTRY(202),
 882         I40E_PTT_UNUSED_ENTRY(203),
 883         I40E_PTT_UNUSED_ENTRY(204),
 884         I40E_PTT_UNUSED_ENTRY(205),
 885         I40E_PTT_UNUSED_ENTRY(206),
 886         I40E_PTT_UNUSED_ENTRY(207),
 887         I40E_PTT_UNUSED_ENTRY(208),
 888         I40E_PTT_UNUSED_ENTRY(209),
 889
 890         I40E_PTT_UNUSED_ENTRY(210),
 891         I40E_PTT_UNUSED_ENTRY(211),
 892         I40E_PTT_UNUSED_ENTRY(212),
 893         I40E_PTT_UNUSED_ENTRY(213),
 894         I40E_PTT_UNUSED_ENTRY(214),
 895         I40E_PTT_UNUSED_ENTRY(215),
 896         I40E_PTT_UNUSED_ENTRY(216),
 897         I40E_PTT_UNUSED_ENTRY(217),
 898         I40E_PTT_UNUSED_ENTRY(218),
 899         I40E_PTT_UNUSED_ENTRY(219),
 900
 901         I40E_PTT_UNUSED_ENTRY(220),
 902         I40E_PTT_UNUSED_ENTRY(221),
 903         I40E_PTT_UNUSED_ENTRY(222),
 904         I40E_PTT_UNUSED_ENTRY(223),
 905         I40E_PTT_UNUSED_ENTRY(224),
 906         I40E_PTT_UNUSED_ENTRY(225),
 907         I40E_PTT_UNUSED_ENTRY(226),
 908         I40E_PTT_UNUSED_ENTRY(227),
 909         I40E_PTT_UNUSED_ENTRY(228),
 910         I40E_PTT_UNUSED_ENTRY(229),
 911
 912         I40E_PTT_UNUSED_ENTRY(230),
 913         I40E_PTT_UNUSED_ENTRY(231),
 914         I40E_PTT_UNUSED_ENTRY(232),
 915         I40E_PTT_UNUSED_ENTRY(233),
 916         I40E_PTT_UNUSED_ENTRY(234),
 917         I40E_PTT_UNUSED_ENTRY(235),
 918         I40E_PTT_UNUSED_ENTRY(236),
 919         I40E_PTT_UNUSED_ENTRY(237),
 920         I40E_PTT_UNUSED_ENTRY(238),
 921         I40E_PTT_UNUSED_ENTRY(239),
 922
 923         I40E_PTT_UNUSED_ENTRY(240),
 924         I40E_PTT_UNUSED_ENTRY(241),
 925         I40E_PTT_UNUSED_ENTRY(242),
 926         I40E_PTT_UNUSED_ENTRY(243),
 927         I40E_PTT_UNUSED_ENTRY(244),
 928         I40E_PTT_UNUSED_ENTRY(245),
 929         I40E_PTT_UNUSED_ENTRY(246),
 930         I40E_PTT_UNUSED_ENTRY(247),
 931         I40E_PTT_UNUSED_ENTRY(248),
 932         I40E_PTT_UNUSED_ENTRY(249),
 933
 934         I40E_PTT_UNUSED_ENTRY(250),
 935         I40E_PTT_UNUSED_ENTRY(251),
 936         I40E_PTT_UNUSED_ENTRY(252),
 937         I40E_PTT_UNUSED_ENTRY(253),
 938         I40E_PTT_UNUSED_ENTRY(254),
 939         I40E_PTT_UNUSED_ENTRY(255)
 940 };
 941
 942
 943 /**
 944  * i40e_validate_mac_addr - Validate unicast MAC address
 945  * @mac_addr: pointer to MAC address
 946  *
 947  * Tests a MAC address to ensure it is a valid Individual Address
 948  **/
 949 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 950 {
 951         enum i40e_status_code status = I40E_SUCCESS;
 952
 953         DEBUGFUNC("i40e_validate_mac_addr");
 954
 955         /* Broadcast addresses ARE multicast addresses
 956          * Make sure it is not a multicast address
 957          * Reject the zero address
 958          */
 959         if (I40E_IS_MULTICAST(mac_addr) ||
 960             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 961               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 962                 status = I40E_ERR_INVALID_MAC_ADDR;
 963
 964         return status;
 965 }
 966 #ifdef PF_DRIVER
 967
 968 /**
 969  * i40e_init_shared_code - Initialize the shared code
 970  * @hw: pointer to hardware structure
 971  *
 972  * This assigns the MAC type and PHY code and inits the NVM.
 973  * Does not touch the hardware. This function must be called prior to any
 974  * other function in the shared code. The i40e_hw structure should be
 975  * memset to 0 prior to calling this function.  The following fields in
 976  * hw structure should be filled in prior to calling this function:
 977  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 978  * subsystem_vendor_id, and revision_id
 979  **/
 980 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 981 {
 982         enum i40e_status_code status = I40E_SUCCESS;
 983         u32 port, ari, func_rid;
 984
 985         DEBUGFUNC("i40e_init_shared_code");
 986
 987         i40e_set_mac_type(hw);
 988
 989         switch (hw->mac.type) {
 990         case I40E_MAC_XL710:
 991         case I40E_MAC_X722:
 992                 break;
 993         default:
 994                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 995         }
 996
 997         hw->phy.get_link_info = true;
 998
 999         /* Determine port number and PF number*/
1000         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1001                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1002         hw->port = (u8)port;
1003         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1004                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1005         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1006         if (ari)
1007                 hw->pf_id = (u8)(func_rid & 0xff);
1008         else
1009                 hw->pf_id = (u8)(func_rid & 0x7);
1010
1011         if (hw->mac.type == I40E_MAC_X722)
1012                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1013                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1014
1015         status = i40e_init_nvm(hw);
1016         return status;
1017 }
1018
1019 /**
1020  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1021  * @hw: pointer to the hw struct
1022  * @flags: a return indicator of what addresses were added to the addr store
1023  * @addrs: the requestor's mac addr store
1024  * @cmd_details: pointer to command details structure or NULL
1025  **/
1026 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1027                                    u16 *flags,
1028                                    struct i40e_aqc_mac_address_read_data *addrs,
1029                                    struct i40e_asq_cmd_details *cmd_details)
1030 {
1031         struct i40e_aq_desc desc;
1032         struct i40e_aqc_mac_address_read *cmd_data =
1033                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1034         enum i40e_status_code status;
1035
1036         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1037         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1038
1039         status = i40e_asq_send_command(hw, &desc, addrs,
1040                                        sizeof(*addrs), cmd_details);
1041         *flags = LE16_TO_CPU(cmd_data->command_flags);
1042
1043         return status;
1044 }
1045
1046 /**
1047  * i40e_aq_mac_address_write - Change the MAC addresses
1048  * @hw: pointer to the hw struct
1049  * @flags: indicates which MAC to be written
1050  * @mac_addr: address to write
1051  * @cmd_details: pointer to command details structure or NULL
1052  **/
1053 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1054                                     u16 flags, u8 *mac_addr,
1055                                     struct i40e_asq_cmd_details *cmd_details)
1056 {
1057         struct i40e_aq_desc desc;
1058         struct i40e_aqc_mac_address_write *cmd_data =
1059                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1060         enum i40e_status_code status;
1061
1062         i40e_fill_default_direct_cmd_desc(&desc,
1063                                           i40e_aqc_opc_mac_address_write);
1064         cmd_data->command_flags = CPU_TO_LE16(flags);
1065         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1066         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1067                                         ((u32)mac_addr[3] << 16) |
1068                                         ((u32)mac_addr[4] << 8) |
1069                                         mac_addr[5]);
1070
1071         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1072
1073         return status;
1074 }
1075
1076 /**
1077  * i40e_get_mac_addr - get MAC address
1078  * @hw: pointer to the HW structure
1079  * @mac_addr: pointer to MAC address
1080  *
1081  * Reads the adapter's MAC address from register
1082  **/
1083 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1084 {
1085         struct i40e_aqc_mac_address_read_data addrs;
1086         enum i40e_status_code status;
1087         u16 flags = 0;
1088
1089         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1090
1091         if (flags & I40E_AQC_LAN_ADDR_VALID)
1092                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1093                         I40E_NONDMA_TO_NONDMA);
1094
1095         return status;
1096 }
1097
1098 /**
1099  * i40e_get_port_mac_addr - get Port MAC address
1100  * @hw: pointer to the HW structure
1101  * @mac_addr: pointer to Port MAC address
1102  *
1103  * Reads the adapter's Port MAC address
1104  **/
1105 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1106 {
1107         struct i40e_aqc_mac_address_read_data addrs;
1108         enum i40e_status_code status;
1109         u16 flags = 0;
1110
1111         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1112         if (status)
1113                 return status;
1114
1115         if (flags & I40E_AQC_PORT_ADDR_VALID)
1116                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1117                         I40E_NONDMA_TO_NONDMA);
1118         else
1119                 status = I40E_ERR_INVALID_MAC_ADDR;
1120
1121         return status;
1122 }
1123
1124 /**
1125  * i40e_pre_tx_queue_cfg - pre tx queue configure
1126  * @hw: pointer to the HW structure
1127  * @queue: target pf queue index
1128  * @enable: state change request
1129  *
1130  * Handles hw requirement to indicate intention to enable
1131  * or disable target queue.
1132  **/
1133 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1134 {
1135         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1136         u32 reg_block = 0;
1137         u32 reg_val;
1138
1139         if (abs_queue_idx >= 128) {
1140                 reg_block = abs_queue_idx / 128;
1141                 abs_queue_idx %= 128;
1142         }
1143
1144         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1145         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1146         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1147
1148         if (enable)
1149                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1150         else
1151                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1152
1153         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1154 }
1155
1156 /**
1157  * i40e_get_san_mac_addr - get SAN MAC address
1158  * @hw: pointer to the HW structure
1159  * @mac_addr: pointer to SAN MAC address
1160  *
1161  * Reads the adapter's SAN MAC address from NVM
1162  **/
1163 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1164                                             u8 *mac_addr)
1165 {
1166         struct i40e_aqc_mac_address_read_data addrs;
1167         enum i40e_status_code status;
1168         u16 flags = 0;
1169
1170         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1171         if (status)
1172                 return status;
1173
1174         if (flags & I40E_AQC_SAN_ADDR_VALID)
1175                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1176                         I40E_NONDMA_TO_NONDMA);
1177         else
1178                 status = I40E_ERR_INVALID_MAC_ADDR;
1179
1180         return status;
1181 }
1182
1183 /**
1184  *  i40e_read_pba_string - Reads part number string from EEPROM
1185  *  @hw: pointer to hardware structure
1186  *  @pba_num: stores the part number string from the EEPROM
1187  *  @pba_num_size: part number string buffer length
1188  *
1189  *  Reads the part number string from the EEPROM.
1190  **/
1191 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1192                                             u32 pba_num_size)
1193 {
1194         enum i40e_status_code status = I40E_SUCCESS;
1195         u16 pba_word = 0;
1196         u16 pba_size = 0;
1197         u16 pba_ptr = 0;
1198         u16 i = 0;
1199
1200         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1201         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1202                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1203                 return status;
1204         }
1205
1206         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1207         if (status != I40E_SUCCESS) {
1208                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1209                 return status;
1210         }
1211
1212         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1213         if (status != I40E_SUCCESS) {
1214                 DEBUGOUT("Failed to read PBA Block size.\n");
1215                 return status;
1216         }
1217
1218         /* Subtract one to get PBA word count (PBA Size word is included in
1219          * total size)
1220          */
1221         pba_size--;
1222         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1223                 DEBUGOUT("Buffer to small for PBA data.\n");
1224                 return I40E_ERR_PARAM;
1225         }
1226
1227         for (i = 0; i < pba_size; i++) {
1228                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1229                 if (status != I40E_SUCCESS) {
1230                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1231                         return status;
1232                 }
1233
1234                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1235                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1236         }
1237         pba_num[(pba_size * 2)] = '\0';
1238
1239         return status;
1240 }
1241
1242 /**
1243  * i40e_get_media_type - Gets media type
1244  * @hw: pointer to the hardware structure
1245  **/
1246 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1247 {
1248         enum i40e_media_type media;
1249
1250         switch (hw->phy.link_info.phy_type) {
1251         case I40E_PHY_TYPE_10GBASE_SR:
1252         case I40E_PHY_TYPE_10GBASE_LR:
1253         case I40E_PHY_TYPE_1000BASE_SX:
1254         case I40E_PHY_TYPE_1000BASE_LX:
1255         case I40E_PHY_TYPE_40GBASE_SR4:
1256         case I40E_PHY_TYPE_40GBASE_LR4:
1257         case I40E_PHY_TYPE_25GBASE_LR:
1258         case I40E_PHY_TYPE_25GBASE_SR:
1259                 media = I40E_MEDIA_TYPE_FIBER;
1260                 break;
1261         case I40E_PHY_TYPE_100BASE_TX:
1262         case I40E_PHY_TYPE_1000BASE_T:
1263         case I40E_PHY_TYPE_10GBASE_T:
1264                 media = I40E_MEDIA_TYPE_BASET;
1265                 break;
1266         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1267         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1268         case I40E_PHY_TYPE_10GBASE_CR1:
1269         case I40E_PHY_TYPE_40GBASE_CR4:
1270         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1271         case I40E_PHY_TYPE_40GBASE_AOC:
1272         case I40E_PHY_TYPE_10GBASE_AOC:
1273         case I40E_PHY_TYPE_25GBASE_CR:
1274         case I40E_PHY_TYPE_25GBASE_AOC:
1275         case I40E_PHY_TYPE_25GBASE_ACC:
1276                 media = I40E_MEDIA_TYPE_DA;
1277                 break;
1278         case I40E_PHY_TYPE_1000BASE_KX:
1279         case I40E_PHY_TYPE_10GBASE_KX4:
1280         case I40E_PHY_TYPE_10GBASE_KR:
1281         case I40E_PHY_TYPE_40GBASE_KR4:
1282         case I40E_PHY_TYPE_20GBASE_KR2:
1283         case I40E_PHY_TYPE_25GBASE_KR:
1284                 media = I40E_MEDIA_TYPE_BACKPLANE;
1285                 break;
1286         case I40E_PHY_TYPE_SGMII:
1287         case I40E_PHY_TYPE_XAUI:
1288         case I40E_PHY_TYPE_XFI:
1289         case I40E_PHY_TYPE_XLAUI:
1290         case I40E_PHY_TYPE_XLPPI:
1291         default:
1292                 media = I40E_MEDIA_TYPE_UNKNOWN;
1293                 break;
1294         }
1295
1296         return media;
1297 }
1298
1299 /**
1300  * i40e_poll_globr - Poll for Global Reset completion
1301  * @hw: pointer to the hardware structure
1302  * @retry_limit: how many times to retry before failure
1303  **/
1304 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1305                                              u32 retry_limit)
1306 {
1307         u32 cnt, reg = 0;
1308
1309         for (cnt = 0; cnt < retry_limit; cnt++) {
1310                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1311                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1312                         return I40E_SUCCESS;
1313                 i40e_msec_delay(100);
1314         }
1315
1316         DEBUGOUT("Global reset failed.\n");
1317         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1318
1319         return I40E_ERR_RESET_FAILED;
1320 }
1321
1322 #define I40E_PF_RESET_WAIT_COUNT        200
1323 /**
1324  * i40e_pf_reset - Reset the PF
1325  * @hw: pointer to the hardware structure
1326  *
1327  * Assuming someone else has triggered a global reset,
1328  * assure the global reset is complete and then reset the PF
1329  **/
1330 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1331 {
1332         u32 cnt = 0;
1333         u32 cnt1 = 0;
1334         u32 reg = 0;
1335         u32 grst_del;
1336
1337         /* Poll for Global Reset steady state in case of recent GRST.
1338          * The grst delay value is in 100ms units, and we'll wait a
1339          * couple counts longer to be sure we don't just miss the end.
1340          */
1341         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1342                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1343                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1344
1345         grst_del = min(grst_del * 20, 160U);
1346
1347         for (cnt = 0; cnt < grst_del; cnt++) {
1348                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1349                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1350                         break;
1351                 i40e_msec_delay(100);
1352         }
1353         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1354                 DEBUGOUT("Global reset polling failed to complete.\n");
1355                 return I40E_ERR_RESET_FAILED;
1356         }
1357
1358         /* Now Wait for the FW to be ready */
1359         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1360                 reg = rd32(hw, I40E_GLNVM_ULD);
1361                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1362                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1363                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1364                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1365                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1366                         break;
1367                 }
1368                 i40e_msec_delay(10);
1369         }
1370         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1372                 DEBUGOUT("wait for FW Reset complete timedout\n");
1373                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1374                 return I40E_ERR_RESET_FAILED;
1375         }
1376
1377         /* If there was a Global Reset in progress when we got here,
1378          * we don't need to do the PF Reset
1379          */
1380         if (!cnt) {
1381                 u32 reg2 = 0;
1382
1383                 reg = rd32(hw, I40E_PFGEN_CTRL);
1384                 wr32(hw, I40E_PFGEN_CTRL,
1385                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1386                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1387                         reg = rd32(hw, I40E_PFGEN_CTRL);
1388                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1389                                 break;
1390                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1391                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1392                                 break;
1393                         i40e_msec_delay(1);
1394                 }
1395                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1396                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1397                                 return I40E_ERR_RESET_FAILED;
1398                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1399                         DEBUGOUT("PF reset polling failed to complete.\n");
1400                         return I40E_ERR_RESET_FAILED;
1401                 }
1402         }
1403
1404         i40e_clear_pxe_mode(hw);
1405
1406
1407         return I40E_SUCCESS;
1408 }
1409
1410 /**
1411  * i40e_clear_hw - clear out any left over hw state
1412  * @hw: pointer to the hw struct
1413  *
1414  * Clear queues and interrupts, typically called at init time,
1415  * but after the capabilities have been found so we know how many
1416  * queues and msix vectors have been allocated.
1417  **/
1418 void i40e_clear_hw(struct i40e_hw *hw)
1419 {
1420         u32 num_queues, base_queue;
1421         u32 num_pf_int;
1422         u32 num_vf_int;
1423         u32 num_vfs;
1424         u32 i, j;
1425         u32 val;
1426         u32 eol = 0x7ff;
1427
1428         /* get number of interrupts, queues, and vfs */
1429         val = rd32(hw, I40E_GLPCI_CNF2);
1430         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1431                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1432         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1433                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1434
1435         val = rd32(hw, I40E_PFLAN_QALLOC);
1436         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1437                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1438         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1439                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1440         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1441                 num_queues = (j - base_queue) + 1;
1442         else
1443                 num_queues = 0;
1444
1445         val = rd32(hw, I40E_PF_VT_PFALLOC);
1446         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1447                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1448         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1449                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1450         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1451                 num_vfs = (j - i) + 1;
1452         else
1453                 num_vfs = 0;
1454
1455         /* stop all the interrupts */
1456         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1457         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1458         for (i = 0; i < num_pf_int - 2; i++)
1459                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1460
1461         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1462         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1463         wr32(hw, I40E_PFINT_LNKLST0, val);
1464         for (i = 0; i < num_pf_int - 2; i++)
1465                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1466         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1467         for (i = 0; i < num_vfs; i++)
1468                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1469         for (i = 0; i < num_vf_int - 2; i++)
1470                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1471
1472         /* warn the HW of the coming Tx disables */
1473         for (i = 0; i < num_queues; i++) {
1474                 u32 abs_queue_idx = base_queue + i;
1475                 u32 reg_block = 0;
1476
1477                 if (abs_queue_idx >= 128) {
1478                         reg_block = abs_queue_idx / 128;
1479                         abs_queue_idx %= 128;
1480                 }
1481
1482                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1483                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1484                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1485                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1486
1487                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1488         }
1489         i40e_usec_delay(400);
1490
1491         /* stop all the queues */
1492         for (i = 0; i < num_queues; i++) {
1493                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1494                 wr32(hw, I40E_QTX_ENA(i), 0);
1495                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1496                 wr32(hw, I40E_QRX_ENA(i), 0);
1497         }
1498
1499         /* short wait for all queue disables to settle */
1500         i40e_usec_delay(50);
1501 }
1502
1503 /**
1504  * i40e_clear_pxe_mode - clear pxe operations mode
1505  * @hw: pointer to the hw struct
1506  *
1507  * Make sure all PXE mode settings are cleared, including things
1508  * like descriptor fetch/write-back mode.
1509  **/
1510 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1511 {
1512         if (i40e_check_asq_alive(hw))
1513                 i40e_aq_clear_pxe_mode(hw, NULL);
1514 }
1515
1516 /**
1517  * i40e_led_is_mine - helper to find matching led
1518  * @hw: pointer to the hw struct
1519  * @idx: index into GPIO registers
1520  *
1521  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1522  */
1523 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1524 {
1525         u32 gpio_val = 0;
1526         u32 port;
1527
1528         if (!hw->func_caps.led[idx])
1529                 return 0;
1530
1531         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1532         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1533                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1534
1535         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1536          * if it is not our port then ignore
1537          */
1538         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1539             (port != hw->port))
1540                 return 0;
1541
1542         return gpio_val;
1543 }
1544
1545 #define I40E_COMBINED_ACTIVITY 0xA
1546 #define I40E_FILTER_ACTIVITY 0xE
1547 #define I40E_LINK_ACTIVITY 0xC
1548 #define I40E_MAC_ACTIVITY 0xD
1549 #define I40E_LED0 22
1550
1551 /**
1552  * i40e_led_get - return current on/off mode
1553  * @hw: pointer to the hw struct
1554  *
1555  * The value returned is the 'mode' field as defined in the
1556  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1557  * values are variations of possible behaviors relating to
1558  * blink, link, and wire.
1559  **/
1560 u32 i40e_led_get(struct i40e_hw *hw)
1561 {
1562         u32 current_mode = 0;
1563         u32 mode = 0;
1564         int i;
1565
1566         /* as per the documentation GPIO 22-29 are the LED
1567          * GPIO pins named LED0..LED7
1568          */
1569         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1570                 u32 gpio_val = i40e_led_is_mine(hw, i);
1571
1572                 if (!gpio_val)
1573                         continue;
1574
1575                 /* ignore gpio LED src mode entries related to the activity
1576                  *  LEDs
1577                  */
1578                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1579                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1580                 switch (current_mode) {
1581                 case I40E_COMBINED_ACTIVITY:
1582                 case I40E_FILTER_ACTIVITY:
1583                 case I40E_MAC_ACTIVITY:
1584                 case I40E_LINK_ACTIVITY:
1585                         continue;
1586                 default:
1587                         break;
1588                 }
1589
1590                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1592                 break;
1593         }
1594
1595         return mode;
1596 }
1597
1598 /**
1599  * i40e_led_set - set new on/off mode
1600  * @hw: pointer to the hw struct
1601  * @mode: 0=off, 0xf=on (else see manual for mode details)
1602  * @blink: true if the LED should blink when on, false if steady
1603  *
1604  * if this function is used to turn on the blink it should
1605  * be used to disable the blink when restoring the original state.
1606  **/
1607 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1608 {
1609         u32 current_mode = 0;
1610         int i;
1611
1612         if (mode & 0xfffffff0)
1613                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1614
1615         /* as per the documentation GPIO 22-29 are the LED
1616          * GPIO pins named LED0..LED7
1617          */
1618         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1619                 u32 gpio_val = i40e_led_is_mine(hw, i);
1620
1621                 if (!gpio_val)
1622                         continue;
1623
1624                 /* ignore gpio LED src mode entries related to the activity
1625                  * LEDs
1626                  */
1627                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1628                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1629                 switch (current_mode) {
1630                 case I40E_COMBINED_ACTIVITY:
1631                 case I40E_FILTER_ACTIVITY:
1632                 case I40E_MAC_ACTIVITY:
1633                 case I40E_LINK_ACTIVITY:
1634                         continue;
1635                 default:
1636                         break;
1637                 }
1638
1639                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1640                 /* this & is a bit of paranoia, but serves as a range check */
1641                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1642                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1643
1644                 if (blink)
1645                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1646                 else
1647                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1648
1649                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1650                 break;
1651         }
1652 }
1653
1654 /* Admin command wrappers */
1655
1656 /**
1657  * i40e_aq_get_phy_capabilities
1658  * @hw: pointer to the hw struct
1659  * @abilities: structure for PHY capabilities to be filled
1660  * @qualified_modules: report Qualified Modules
1661  * @report_init: report init capabilities (active are default)
1662  * @cmd_details: pointer to command details structure or NULL
1663  *
1664  * Returns the various PHY abilities supported on the Port.
1665  **/
1666 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1667                         bool qualified_modules, bool report_init,
1668                         struct i40e_aq_get_phy_abilities_resp *abilities,
1669                         struct i40e_asq_cmd_details *cmd_details)
1670 {
1671         struct i40e_aq_desc desc;
1672         enum i40e_status_code status;
1673         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1674         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1675
1676         if (!abilities)
1677                 return I40E_ERR_PARAM;
1678
1679         do {
1680                 i40e_fill_default_direct_cmd_desc(&desc,
1681                                                i40e_aqc_opc_get_phy_abilities);
1682
1683                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1684                 if (abilities_size > I40E_AQ_LARGE_BUF)
1685                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1686
1687                 if (qualified_modules)
1688                         desc.params.external.param0 |=
1689                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1690
1691                 if (report_init)
1692                         desc.params.external.param0 |=
1693                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1694
1695                 status = i40e_asq_send_command(hw, &desc, abilities,
1696                                                abilities_size, cmd_details);
1697
1698                 if (status != I40E_SUCCESS)
1699                         break;
1700
1701                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1702                         status = I40E_ERR_UNKNOWN_PHY;
1703                         break;
1704                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1705                         i40e_msec_delay(1);
1706                         total_delay++;
1707                         status = I40E_ERR_TIMEOUT;
1708                 }
1709         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1710                  (total_delay < max_delay));
1711
1712         if (status != I40E_SUCCESS)
1713                 return status;
1714
1715         if (report_init) {
1716                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1717                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1718                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1719                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1720                 } else {
1721                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1722                         hw->phy.phy_types |=
1723                                         ((u64)abilities->phy_type_ext << 32);
1724                 }
1725         }
1726
1727         return status;
1728 }
1729
1730 /**
1731  * i40e_aq_set_phy_config
1732  * @hw: pointer to the hw struct
1733  * @config: structure with PHY configuration to be set
1734  * @cmd_details: pointer to command details structure or NULL
1735  *
1736  * Set the various PHY configuration parameters
1737  * supported on the Port.One or more of the Set PHY config parameters may be
1738  * ignored in an MFP mode as the PF may not have the privilege to set some
1739  * of the PHY Config parameters. This status will be indicated by the
1740  * command response.
1741  **/
1742 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1743                                 struct i40e_aq_set_phy_config *config,
1744                                 struct i40e_asq_cmd_details *cmd_details)
1745 {
1746         struct i40e_aq_desc desc;
1747         struct i40e_aq_set_phy_config *cmd =
1748                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1749         enum i40e_status_code status;
1750
1751         if (!config)
1752                 return I40E_ERR_PARAM;
1753
1754         i40e_fill_default_direct_cmd_desc(&desc,
1755                                           i40e_aqc_opc_set_phy_config);
1756
1757         *cmd = *config;
1758
1759         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1760
1761         return status;
1762 }
1763
1764 /**
1765  * i40e_set_fc
1766  * @hw: pointer to the hw struct
1767  * @aq_failures: buffer to return AdminQ failure information
1768  * @atomic_restart: whether to enable atomic link restart
1769  *
1770  * Set the requested flow control mode using set_phy_config.
1771  **/
1772 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1773                                   bool atomic_restart)
1774 {
1775         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1776         struct i40e_aq_get_phy_abilities_resp abilities;
1777         struct i40e_aq_set_phy_config config;
1778         enum i40e_status_code status;
1779         u8 pause_mask = 0x0;
1780
1781         *aq_failures = 0x0;
1782
1783         switch (fc_mode) {
1784         case I40E_FC_FULL:
1785                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1786                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1787                 break;
1788         case I40E_FC_RX_PAUSE:
1789                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1790                 break;
1791         case I40E_FC_TX_PAUSE:
1792                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1793                 break;
1794         default:
1795                 break;
1796         }
1797
1798         /* Get the current phy config */
1799         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1800                                               NULL);
1801         if (status) {
1802                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1803                 return status;
1804         }
1805
1806         memset(&config, 0, sizeof(config));
1807         /* clear the old pause settings */
1808         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1809                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1810         /* set the new abilities */
1811         config.abilities |= pause_mask;
1812         /* If the abilities have changed, then set the new config */
1813         if (config.abilities != abilities.abilities) {
1814                 /* Auto restart link so settings take effect */
1815                 if (atomic_restart)
1816                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1817                 /* Copy over all the old settings */
1818                 config.phy_type = abilities.phy_type;
1819                 config.phy_type_ext = abilities.phy_type_ext;
1820                 config.link_speed = abilities.link_speed;
1821                 config.eee_capability = abilities.eee_capability;
1822                 config.eeer = abilities.eeer_val;
1823                 config.low_power_ctrl = abilities.d3_lpan;
1824                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1825                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1826                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1827
1828                 if (status)
1829                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1830         }
1831         /* Update the link info */
1832         status = i40e_update_link_info(hw);
1833         if (status) {
1834                 /* Wait a little bit (on 40G cards it sometimes takes a really
1835                  * long time for link to come back from the atomic reset)
1836                  * and try once more
1837                  */
1838                 i40e_msec_delay(1000);
1839                 status = i40e_update_link_info(hw);
1840         }
1841         if (status)
1842                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1843
1844         return status;
1845 }
1846
1847 /**
1848  * i40e_aq_set_mac_config
1849  * @hw: pointer to the hw struct
1850  * @max_frame_size: Maximum Frame Size to be supported by the port
1851  * @crc_en: Tell HW to append a CRC to outgoing frames
1852  * @pacing: Pacing configurations
1853  * @cmd_details: pointer to command details structure or NULL
1854  *
1855  * Configure MAC settings for frame size, jumbo frame support and the
1856  * addition of a CRC by the hardware.
1857  **/
1858 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1859                                 u16 max_frame_size,
1860                                 bool crc_en, u16 pacing,
1861                                 struct i40e_asq_cmd_details *cmd_details)
1862 {
1863         struct i40e_aq_desc desc;
1864         struct i40e_aq_set_mac_config *cmd =
1865                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1866         enum i40e_status_code status;
1867
1868         if (max_frame_size == 0)
1869                 return I40E_ERR_PARAM;
1870
1871         i40e_fill_default_direct_cmd_desc(&desc,
1872                                           i40e_aqc_opc_set_mac_config);
1873
1874         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1875         cmd->params = ((u8)pacing & 0x0F) << 3;
1876         if (crc_en)
1877                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1878
1879 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1880         cmd->fc_refresh_threshold =
1881                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1882
1883         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1884
1885         return status;
1886 }
1887
1888 /**
1889  * i40e_aq_clear_pxe_mode
1890  * @hw: pointer to the hw struct
1891  * @cmd_details: pointer to command details structure or NULL
1892  *
1893  * Tell the firmware that the driver is taking over from PXE
1894  **/
1895 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1896                         struct i40e_asq_cmd_details *cmd_details)
1897 {
1898         enum i40e_status_code status;
1899         struct i40e_aq_desc desc;
1900         struct i40e_aqc_clear_pxe *cmd =
1901                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1902
1903         i40e_fill_default_direct_cmd_desc(&desc,
1904                                           i40e_aqc_opc_clear_pxe_mode);
1905
1906         cmd->rx_cnt = 0x2;
1907
1908         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1909
1910         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1911
1912         return status;
1913 }
1914
1915 /**
1916  * i40e_aq_set_link_restart_an
1917  * @hw: pointer to the hw struct
1918  * @enable_link: if true: enable link, if false: disable link
1919  * @cmd_details: pointer to command details structure or NULL
1920  *
1921  * Sets up the link and restarts the Auto-Negotiation over the link.
1922  **/
1923 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1924                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1925 {
1926         struct i40e_aq_desc desc;
1927         struct i40e_aqc_set_link_restart_an *cmd =
1928                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1929         enum i40e_status_code status;
1930
1931         i40e_fill_default_direct_cmd_desc(&desc,
1932                                           i40e_aqc_opc_set_link_restart_an);
1933
1934         cmd->command = I40E_AQ_PHY_RESTART_AN;
1935         if (enable_link)
1936                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1937         else
1938                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1939
1940         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1941
1942         return status;
1943 }
1944
1945 /**
1946  * i40e_aq_get_link_info
1947  * @hw: pointer to the hw struct
1948  * @enable_lse: enable/disable LinkStatusEvent reporting
1949  * @link: pointer to link status structure - optional
1950  * @cmd_details: pointer to command details structure or NULL
1951  *
1952  * Returns the link status of the adapter.
1953  **/
1954 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1955                                 bool enable_lse, struct i40e_link_status *link,
1956                                 struct i40e_asq_cmd_details *cmd_details)
1957 {
1958         struct i40e_aq_desc desc;
1959         struct i40e_aqc_get_link_status *resp =
1960                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1961         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1962         enum i40e_status_code status;
1963         bool tx_pause, rx_pause;
1964         u16 command_flags;
1965
1966         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1967
1968         if (enable_lse)
1969                 command_flags = I40E_AQ_LSE_ENABLE;
1970         else
1971                 command_flags = I40E_AQ_LSE_DISABLE;
1972         resp->command_flags = CPU_TO_LE16(command_flags);
1973
1974         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1975
1976         if (status != I40E_SUCCESS)
1977                 goto aq_get_link_info_exit;
1978
1979         /* save off old link status information */
1980         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1981                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1982
1983         /* update link status */
1984         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1985         hw->phy.media_type = i40e_get_media_type(hw);
1986         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1987         hw_link_info->link_info = resp->link_info;
1988         hw_link_info->an_info = resp->an_info;
1989         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1990                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1991         hw_link_info->ext_info = resp->ext_info;
1992         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1993         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1994         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1995
1996         /* update fc info */
1997         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1998         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1999         if (tx_pause & rx_pause)
2000                 hw->fc.current_mode = I40E_FC_FULL;
2001         else if (tx_pause)
2002                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2003         else if (rx_pause)
2004                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2005         else
2006                 hw->fc.current_mode = I40E_FC_NONE;
2007
2008         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2009                 hw_link_info->crc_enable = true;
2010         else
2011                 hw_link_info->crc_enable = false;
2012
2013         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2014                 hw_link_info->lse_enable = true;
2015         else
2016                 hw_link_info->lse_enable = false;
2017
2018         if ((hw->mac.type == I40E_MAC_XL710) &&
2019             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2020              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2021                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2022
2023         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2024             hw->aq.api_min_ver >= 7) {
2025                 __le32 tmp;
2026
2027                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2028                             I40E_NONDMA_TO_NONDMA);
2029                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2030                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2031         }
2032
2033         /* save link status information */
2034         if (link)
2035                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2036                             I40E_NONDMA_TO_NONDMA);
2037
2038         /* flag cleared so helper functions don't call AQ again */
2039         hw->phy.get_link_info = false;
2040
2041 aq_get_link_info_exit:
2042         return status;
2043 }
2044
2045 /**
2046  * i40e_aq_set_phy_int_mask
2047  * @hw: pointer to the hw struct
2048  * @mask: interrupt mask to be set
2049  * @cmd_details: pointer to command details structure or NULL
2050  *
2051  * Set link interrupt mask.
2052  **/
2053 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2054                                 u16 mask,
2055                                 struct i40e_asq_cmd_details *cmd_details)
2056 {
2057         struct i40e_aq_desc desc;
2058         struct i40e_aqc_set_phy_int_mask *cmd =
2059                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2060         enum i40e_status_code status;
2061
2062         i40e_fill_default_direct_cmd_desc(&desc,
2063                                           i40e_aqc_opc_set_phy_int_mask);
2064
2065         cmd->event_mask = CPU_TO_LE16(mask);
2066
2067         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2068
2069         return status;
2070 }
2071
2072 /**
2073  * i40e_aq_get_local_advt_reg
2074  * @hw: pointer to the hw struct
2075  * @advt_reg: local AN advertisement register value
2076  * @cmd_details: pointer to command details structure or NULL
2077  *
2078  * Get the Local AN advertisement register value.
2079  **/
2080 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2081                                 u64 *advt_reg,
2082                                 struct i40e_asq_cmd_details *cmd_details)
2083 {
2084         struct i40e_aq_desc desc;
2085         struct i40e_aqc_an_advt_reg *resp =
2086                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2087         enum i40e_status_code status;
2088
2089         i40e_fill_default_direct_cmd_desc(&desc,
2090                                           i40e_aqc_opc_get_local_advt_reg);
2091
2092         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2093
2094         if (status != I40E_SUCCESS)
2095                 goto aq_get_local_advt_reg_exit;
2096
2097         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2098         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2099
2100 aq_get_local_advt_reg_exit:
2101         return status;
2102 }
2103
2104 /**
2105  * i40e_aq_set_local_advt_reg
2106  * @hw: pointer to the hw struct
2107  * @advt_reg: local AN advertisement register value
2108  * @cmd_details: pointer to command details structure or NULL
2109  *
2110  * Get the Local AN advertisement register value.
2111  **/
2112 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2113                                 u64 advt_reg,
2114                                 struct i40e_asq_cmd_details *cmd_details)
2115 {
2116         struct i40e_aq_desc desc;
2117         struct i40e_aqc_an_advt_reg *cmd =
2118                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2119         enum i40e_status_code status;
2120
2121         i40e_fill_default_direct_cmd_desc(&desc,
2122                                           i40e_aqc_opc_get_local_advt_reg);
2123
2124         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2125         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2126
2127         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2128
2129         return status;
2130 }
2131
2132 /**
2133  * i40e_aq_get_partner_advt
2134  * @hw: pointer to the hw struct
2135  * @advt_reg: AN partner advertisement register value
2136  * @cmd_details: pointer to command details structure or NULL
2137  *
2138  * Get the link partner AN advertisement register value.
2139  **/
2140 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2141                                 u64 *advt_reg,
2142                                 struct i40e_asq_cmd_details *cmd_details)
2143 {
2144         struct i40e_aq_desc desc;
2145         struct i40e_aqc_an_advt_reg *resp =
2146                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2147         enum i40e_status_code status;
2148
2149         i40e_fill_default_direct_cmd_desc(&desc,
2150                                           i40e_aqc_opc_get_partner_advt);
2151
2152         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2153
2154         if (status != I40E_SUCCESS)
2155                 goto aq_get_partner_advt_exit;
2156
2157         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2158         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2159
2160 aq_get_partner_advt_exit:
2161         return status;
2162 }
2163
2164 /**
2165  * i40e_aq_set_lb_modes
2166  * @hw: pointer to the hw struct
2167  * @lb_modes: loopback mode to be set
2168  * @cmd_details: pointer to command details structure or NULL
2169  *
2170  * Sets loopback modes.
2171  **/
2172 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2173                                 u16 lb_modes,
2174                                 struct i40e_asq_cmd_details *cmd_details)
2175 {
2176         struct i40e_aq_desc desc;
2177         struct i40e_aqc_set_lb_mode *cmd =
2178                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2179         enum i40e_status_code status;
2180
2181         i40e_fill_default_direct_cmd_desc(&desc,
2182                                           i40e_aqc_opc_set_lb_modes);
2183
2184         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2185
2186         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2187
2188         return status;
2189 }
2190
2191 /**
2192  * i40e_aq_set_phy_debug
2193  * @hw: pointer to the hw struct
2194  * @cmd_flags: debug command flags
2195  * @cmd_details: pointer to command details structure or NULL
2196  *
2197  * Reset the external PHY.
2198  **/
2199 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2200                                 struct i40e_asq_cmd_details *cmd_details)
2201 {
2202         struct i40e_aq_desc desc;
2203         struct i40e_aqc_set_phy_debug *cmd =
2204                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2205         enum i40e_status_code status;
2206
2207         i40e_fill_default_direct_cmd_desc(&desc,
2208                                           i40e_aqc_opc_set_phy_debug);
2209
2210         cmd->command_flags = cmd_flags;
2211
2212         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2213
2214         return status;
2215 }
2216
2217 /**
2218  * i40e_aq_add_vsi
2219  * @hw: pointer to the hw struct
2220  * @vsi_ctx: pointer to a vsi context struct
2221  * @cmd_details: pointer to command details structure or NULL
2222  *
2223  * Add a VSI context to the hardware.
2224 **/
2225 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2226                                 struct i40e_vsi_context *vsi_ctx,
2227                                 struct i40e_asq_cmd_details *cmd_details)
2228 {
2229         struct i40e_aq_desc desc;
2230         struct i40e_aqc_add_get_update_vsi *cmd =
2231                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2232         struct i40e_aqc_add_get_update_vsi_completion *resp =
2233                 (struct i40e_aqc_add_get_update_vsi_completion *)
2234                 &desc.params.raw;
2235         enum i40e_status_code status;
2236
2237         i40e_fill_default_direct_cmd_desc(&desc,
2238                                           i40e_aqc_opc_add_vsi);
2239
2240         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2241         cmd->connection_type = vsi_ctx->connection_type;
2242         cmd->vf_id = vsi_ctx->vf_num;
2243         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2244
2245         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2246
2247         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2248                                     sizeof(vsi_ctx->info), cmd_details);
2249
2250         if (status != I40E_SUCCESS)
2251                 goto aq_add_vsi_exit;
2252
2253         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2254         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2255         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2256         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2257
2258 aq_add_vsi_exit:
2259         return status;
2260 }
2261
2262 /**
2263  * i40e_aq_set_default_vsi
2264  * @hw: pointer to the hw struct
2265  * @seid: vsi number
2266  * @cmd_details: pointer to command details structure or NULL
2267  **/
2268 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2269                                 u16 seid,
2270                                 struct i40e_asq_cmd_details *cmd_details)
2271 {
2272         struct i40e_aq_desc desc;
2273         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2274                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2275                 &desc.params.raw;
2276         enum i40e_status_code status;
2277
2278         i40e_fill_default_direct_cmd_desc(&desc,
2279                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2280
2281         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2282         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2283         cmd->seid = CPU_TO_LE16(seid);
2284
2285         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2286
2287         return status;
2288 }
2289
2290 /**
2291  * i40e_aq_clear_default_vsi
2292  * @hw: pointer to the hw struct
2293  * @seid: vsi number
2294  * @cmd_details: pointer to command details structure or NULL
2295  **/
2296 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2297                                 u16 seid,
2298                                 struct i40e_asq_cmd_details *cmd_details)
2299 {
2300         struct i40e_aq_desc desc;
2301         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2302                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2303                 &desc.params.raw;
2304         enum i40e_status_code status;
2305
2306         i40e_fill_default_direct_cmd_desc(&desc,
2307                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2308
2309         cmd->promiscuous_flags = CPU_TO_LE16(0);
2310         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2311         cmd->seid = CPU_TO_LE16(seid);
2312
2313         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2314
2315         return status;
2316 }
2317
2318 /**
2319  * i40e_aq_set_vsi_unicast_promiscuous
2320  * @hw: pointer to the hw struct
2321  * @seid: vsi number
2322  * @set: set unicast promiscuous enable/disable
2323  * @cmd_details: pointer to command details structure or NULL
2324  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2325  **/
2326 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2327                                 u16 seid, bool set,
2328                                 struct i40e_asq_cmd_details *cmd_details,
2329                                 bool rx_only_promisc)
2330 {
2331         struct i40e_aq_desc desc;
2332         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2333                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2334         enum i40e_status_code status;
2335         u16 flags = 0;
2336
2337         i40e_fill_default_direct_cmd_desc(&desc,
2338                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2339
2340         if (set) {
2341                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2342                 if (rx_only_promisc &&
2343                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2344                      (hw->aq.api_maj_ver > 1)))
2345                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2346         }
2347
2348         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2349
2350         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2351         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2352              (hw->aq.api_maj_ver > 1))
2353                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2354
2355         cmd->seid = CPU_TO_LE16(seid);
2356         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2357
2358         return status;
2359 }
2360
2361 /**
2362  * i40e_aq_set_vsi_multicast_promiscuous
2363  * @hw: pointer to the hw struct
2364  * @seid: vsi number
2365  * @set: set multicast promiscuous enable/disable
2366  * @cmd_details: pointer to command details structure or NULL
2367  **/
2368 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2369                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2370 {
2371         struct i40e_aq_desc desc;
2372         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2373                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2374         enum i40e_status_code status;
2375         u16 flags = 0;
2376
2377         i40e_fill_default_direct_cmd_desc(&desc,
2378                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2379
2380         if (set)
2381                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2382
2383         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2384
2385         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2386
2387         cmd->seid = CPU_TO_LE16(seid);
2388         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2389
2390         return status;
2391 }
2392
2393 /**
2394 * i40e_aq_set_vsi_full_promiscuous
2395 * @hw: pointer to the hw struct
2396 * @seid: VSI number
2397 * @set: set promiscuous enable/disable
2398 * @cmd_details: pointer to command details structure or NULL
2399 **/
2400 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2401                                 u16 seid, bool set,
2402                                 struct i40e_asq_cmd_details *cmd_details)
2403 {
2404         struct i40e_aq_desc desc;
2405         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2406                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2407         enum i40e_status_code status;
2408         u16 flags = 0;
2409
2410         i40e_fill_default_direct_cmd_desc(&desc,
2411                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2412
2413         if (set)
2414                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2415                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2416                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2417
2418         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2419
2420         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2421                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2422                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2423
2424         cmd->seid = CPU_TO_LE16(seid);
2425         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2426
2427         return status;
2428 }
2429
2430 /**
2431  * i40e_aq_set_vsi_mc_promisc_on_vlan
2432  * @hw: pointer to the hw struct
2433  * @seid: vsi number
2434  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2435  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2436  * @cmd_details: pointer to command details structure or NULL
2437  **/
2438 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2439                                 u16 seid, bool enable, u16 vid,
2440                                 struct i40e_asq_cmd_details *cmd_details)
2441 {
2442         struct i40e_aq_desc desc;
2443         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2444                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2445         enum i40e_status_code status;
2446         u16 flags = 0;
2447
2448         i40e_fill_default_direct_cmd_desc(&desc,
2449                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2450
2451         if (enable)
2452                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2453
2454         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2455         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2456         cmd->seid = CPU_TO_LE16(seid);
2457         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2458
2459         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2460
2461         return status;
2462 }
2463
2464 /**
2465  * i40e_aq_set_vsi_uc_promisc_on_vlan
2466  * @hw: pointer to the hw struct
2467  * @seid: vsi number
2468  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2469  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2470  * @cmd_details: pointer to command details structure or NULL
2471  **/
2472 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2473                                 u16 seid, bool enable, u16 vid,
2474                                 struct i40e_asq_cmd_details *cmd_details)
2475 {
2476         struct i40e_aq_desc desc;
2477         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2478                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2479         enum i40e_status_code status;
2480         u16 flags = 0;
2481
2482         i40e_fill_default_direct_cmd_desc(&desc,
2483                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2484
2485         if (enable)
2486                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2487
2488         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2489         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2490         cmd->seid = CPU_TO_LE16(seid);
2491         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2492
2493         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2494
2495         return status;
2496 }
2497
2498 /**
2499  * i40e_aq_set_vsi_bc_promisc_on_vlan
2500  * @hw: pointer to the hw struct
2501  * @seid: vsi number
2502  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2503  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2504  * @cmd_details: pointer to command details structure or NULL
2505  **/
2506 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2507                                 u16 seid, bool enable, u16 vid,
2508                                 struct i40e_asq_cmd_details *cmd_details)
2509 {
2510         struct i40e_aq_desc desc;
2511         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2512                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2513         enum i40e_status_code status;
2514         u16 flags = 0;
2515
2516         i40e_fill_default_direct_cmd_desc(&desc,
2517                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2518
2519         if (enable)
2520                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2521
2522         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2523         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2524         cmd->seid = CPU_TO_LE16(seid);
2525         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2526
2527         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2528
2529         return status;
2530 }
2531
2532 /**
2533  * i40e_aq_set_vsi_broadcast
2534  * @hw: pointer to the hw struct
2535  * @seid: vsi number
2536  * @set_filter: true to set filter, false to clear filter
2537  * @cmd_details: pointer to command details structure or NULL
2538  *
2539  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2540  **/
2541 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2542                                 u16 seid, bool set_filter,
2543                                 struct i40e_asq_cmd_details *cmd_details)
2544 {
2545         struct i40e_aq_desc desc;
2546         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2547                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2548         enum i40e_status_code status;
2549
2550         i40e_fill_default_direct_cmd_desc(&desc,
2551                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2552
2553         if (set_filter)
2554                 cmd->promiscuous_flags
2555                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2556         else
2557                 cmd->promiscuous_flags
2558                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2559
2560         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2561         cmd->seid = CPU_TO_LE16(seid);
2562         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2563
2564         return status;
2565 }
2566
2567 /**
2568  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2569  * @hw: pointer to the hw struct
2570  * @seid: vsi number
2571  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2572  * @cmd_details: pointer to command details structure or NULL
2573  **/
2574 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2575                                 u16 seid, bool enable,
2576                                 struct i40e_asq_cmd_details *cmd_details)
2577 {
2578         struct i40e_aq_desc desc;
2579         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2580                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2581         enum i40e_status_code status;
2582         u16 flags = 0;
2583
2584         i40e_fill_default_direct_cmd_desc(&desc,
2585                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2586         if (enable)
2587                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2588
2589         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2590         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2591         cmd->seid = CPU_TO_LE16(seid);
2592
2593         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2594
2595         return status;
2596 }
2597
2598 /**
2599  * i40e_get_vsi_params - get VSI configuration info
2600  * @hw: pointer to the hw struct
2601  * @vsi_ctx: pointer to a vsi context struct
2602  * @cmd_details: pointer to command details structure or NULL
2603  **/
2604 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2605                                 struct i40e_vsi_context *vsi_ctx,
2606                                 struct i40e_asq_cmd_details *cmd_details)
2607 {
2608         struct i40e_aq_desc desc;
2609         struct i40e_aqc_add_get_update_vsi *cmd =
2610                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2611         struct i40e_aqc_add_get_update_vsi_completion *resp =
2612                 (struct i40e_aqc_add_get_update_vsi_completion *)
2613                 &desc.params.raw;
2614         enum i40e_status_code status;
2615
2616         UNREFERENCED_1PARAMETER(cmd_details);
2617         i40e_fill_default_direct_cmd_desc(&desc,
2618                                           i40e_aqc_opc_get_vsi_parameters);
2619
2620         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2621
2622         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2623
2624         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2625                                     sizeof(vsi_ctx->info), NULL);
2626
2627         if (status != I40E_SUCCESS)
2628                 goto aq_get_vsi_params_exit;
2629
2630         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2631         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2632         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2633         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2634
2635 aq_get_vsi_params_exit:
2636         return status;
2637 }
2638
2639 /**
2640  * i40e_aq_update_vsi_params
2641  * @hw: pointer to the hw struct
2642  * @vsi_ctx: pointer to a vsi context struct
2643  * @cmd_details: pointer to command details structure or NULL
2644  *
2645  * Update a VSI context.
2646  **/
2647 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2648                                 struct i40e_vsi_context *vsi_ctx,
2649                                 struct i40e_asq_cmd_details *cmd_details)
2650 {
2651         struct i40e_aq_desc desc;
2652         struct i40e_aqc_add_get_update_vsi *cmd =
2653                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2654         struct i40e_aqc_add_get_update_vsi_completion *resp =
2655                 (struct i40e_aqc_add_get_update_vsi_completion *)
2656                 &desc.params.raw;
2657         enum i40e_status_code status;
2658
2659         i40e_fill_default_direct_cmd_desc(&desc,
2660                                           i40e_aqc_opc_update_vsi_parameters);
2661         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2662
2663         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2664
2665         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2666                                     sizeof(vsi_ctx->info), cmd_details);
2667
2668         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2669         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2670
2671         return status;
2672 }
2673
2674 /**
2675  * i40e_aq_get_switch_config
2676  * @hw: pointer to the hardware structure
2677  * @buf: pointer to the result buffer
2678  * @buf_size: length of input buffer
2679  * @start_seid: seid to start for the report, 0 == beginning
2680  * @cmd_details: pointer to command details structure or NULL
2681  *
2682  * Fill the buf with switch configuration returned from AdminQ command
2683  **/
2684 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2685                                 struct i40e_aqc_get_switch_config_resp *buf,
2686                                 u16 buf_size, u16 *start_seid,
2687                                 struct i40e_asq_cmd_details *cmd_details)
2688 {
2689         struct i40e_aq_desc desc;
2690         struct i40e_aqc_switch_seid *scfg =
2691                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2692         enum i40e_status_code status;
2693
2694         i40e_fill_default_direct_cmd_desc(&desc,
2695                                           i40e_aqc_opc_get_switch_config);
2696         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2697         if (buf_size > I40E_AQ_LARGE_BUF)
2698                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2699         scfg->seid = CPU_TO_LE16(*start_seid);
2700
2701         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2702         *start_seid = LE16_TO_CPU(scfg->seid);
2703
2704         return status;
2705 }
2706
2707 /**
2708  * i40e_aq_set_switch_config
2709  * @hw: pointer to the hardware structure
2710  * @flags: bit flag values to set
2711  * @mode: cloud filter mode
2712  * @valid_flags: which bit flags to set
2713  * @cmd_details: pointer to command details structure or NULL
2714  *
2715  * Set switch configuration bits
2716  **/
2717 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2718                                 u16 flags, u16 valid_flags, u8 mode,
2719                                 struct i40e_asq_cmd_details *cmd_details)
2720 {
2721         struct i40e_aq_desc desc;
2722         struct i40e_aqc_set_switch_config *scfg =
2723                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2724         enum i40e_status_code status;
2725
2726         i40e_fill_default_direct_cmd_desc(&desc,
2727                                           i40e_aqc_opc_set_switch_config);
2728         scfg->flags = CPU_TO_LE16(flags);
2729         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2730         scfg->mode = mode;
2731         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2732                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2733                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2734                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2735         }
2736         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2737
2738         return status;
2739 }
2740
2741 /**
2742  * i40e_aq_get_firmware_version
2743  * @hw: pointer to the hw struct
2744  * @fw_major_version: firmware major version
2745  * @fw_minor_version: firmware minor version
2746  * @fw_build: firmware build number
2747  * @api_major_version: major queue version
2748  * @api_minor_version: minor queue version
2749  * @cmd_details: pointer to command details structure or NULL
2750  *
2751  * Get the firmware version from the admin queue commands
2752  **/
2753 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2754                                 u16 *fw_major_version, u16 *fw_minor_version,
2755                                 u32 *fw_build,
2756                                 u16 *api_major_version, u16 *api_minor_version,
2757                                 struct i40e_asq_cmd_details *cmd_details)
2758 {
2759         struct i40e_aq_desc desc;
2760         struct i40e_aqc_get_version *resp =
2761                 (struct i40e_aqc_get_version *)&desc.params.raw;
2762         enum i40e_status_code status;
2763
2764         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2765
2766         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2767
2768         if (status == I40E_SUCCESS) {
2769                 if (fw_major_version != NULL)
2770                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2771                 if (fw_minor_version != NULL)
2772                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2773                 if (fw_build != NULL)
2774                         *fw_build = LE32_TO_CPU(resp->fw_build);
2775                 if (api_major_version != NULL)
2776                         *api_major_version = LE16_TO_CPU(resp->api_major);
2777                 if (api_minor_version != NULL)
2778                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2779
2780                 /* A workaround to fix the API version in SW */
2781                 if (api_major_version && api_minor_version &&
2782                     fw_major_version && fw_minor_version &&
2783                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2784                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2785                      (*fw_major_version > 4)))
2786                         *api_minor_version = 2;
2787         }
2788
2789         return status;
2790 }
2791
2792 /**
2793  * i40e_aq_send_driver_version
2794  * @hw: pointer to the hw struct
2795  * @dv: driver's major, minor version
2796  * @cmd_details: pointer to command details structure or NULL
2797  *
2798  * Send the driver version to the firmware
2799  **/
2800 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2801                                 struct i40e_driver_version *dv,
2802                                 struct i40e_asq_cmd_details *cmd_details)
2803 {
2804         struct i40e_aq_desc desc;
2805         struct i40e_aqc_driver_version *cmd =
2806                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2807         enum i40e_status_code status;
2808         u16 len;
2809
2810         if (dv == NULL)
2811                 return I40E_ERR_PARAM;
2812
2813         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2814
2815         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2816         cmd->driver_major_ver = dv->major_version;
2817         cmd->driver_minor_ver = dv->minor_version;
2818         cmd->driver_build_ver = dv->build_version;
2819         cmd->driver_subbuild_ver = dv->subbuild_version;
2820
2821         len = 0;
2822         while (len < sizeof(dv->driver_string) &&
2823                (dv->driver_string[len] < 0x80) &&
2824                dv->driver_string[len])
2825                 len++;
2826         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2827                                        len, cmd_details);
2828
2829         return status;
2830 }
2831
2832 /**
2833  * i40e_get_link_status - get status of the HW network link
2834  * @hw: pointer to the hw struct
2835  * @link_up: pointer to bool (true/false = linkup/linkdown)
2836  *
2837  * Variable link_up true if link is up, false if link is down.
2838  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2839  *
2840  * Side effect: LinkStatusEvent reporting becomes enabled
2841  **/
2842 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2843 {
2844         enum i40e_status_code status = I40E_SUCCESS;
2845
2846         if (hw->phy.get_link_info) {
2847                 status = i40e_update_link_info(hw);
2848
2849                 if (status != I40E_SUCCESS)
2850                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2851                                    status);
2852         }
2853
2854         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2855
2856         return status;
2857 }
2858
2859 /**
2860  * i40e_updatelink_status - update status of the HW network link
2861  * @hw: pointer to the hw struct
2862  **/
2863 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2864 {
2865         struct i40e_aq_get_phy_abilities_resp abilities;
2866         enum i40e_status_code status = I40E_SUCCESS;
2867
2868         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2869         if (status)
2870                 return status;
2871
2872         /* extra checking needed to ensure link info to user is timely */
2873         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2874             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2875              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2876                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2877                                                       &abilities, NULL);
2878                 if (status)
2879                         return status;
2880
2881                 hw->phy.link_info.req_fec_info =
2882                         abilities.fec_cfg_curr_mod_ext_info &
2883                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2884
2885                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2886                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2887         }
2888         return status;
2889 }
2890
2891
2892 /**
2893  * i40e_get_link_speed
2894  * @hw: pointer to the hw struct
2895  *
2896  * Returns the link speed of the adapter.
2897  **/
2898 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2899 {
2900         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2901         enum i40e_status_code status = I40E_SUCCESS;
2902
2903         if (hw->phy.get_link_info) {
2904                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2905
2906                 if (status != I40E_SUCCESS)
2907                         goto i40e_link_speed_exit;
2908         }
2909
2910         speed = hw->phy.link_info.link_speed;
2911
2912 i40e_link_speed_exit:
2913         return speed;
2914 }
2915
2916 /**
2917  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2918  * @hw: pointer to the hw struct
2919  * @uplink_seid: the MAC or other gizmo SEID
2920  * @downlink_seid: the VSI SEID
2921  * @enabled_tc: bitmap of TCs to be enabled
2922  * @default_port: true for default port VSI, false for control port
2923  * @veb_seid: pointer to where to put the resulting VEB SEID
2924  * @enable_stats: true to turn on VEB stats
2925  * @cmd_details: pointer to command details structure or NULL
2926  *
2927  * This asks the FW to add a VEB between the uplink and downlink
2928  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2929  **/
2930 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2931                                 u16 downlink_seid, u8 enabled_tc,
2932                                 bool default_port, u16 *veb_seid,
2933                                 bool enable_stats,
2934                                 struct i40e_asq_cmd_details *cmd_details)
2935 {
2936         struct i40e_aq_desc desc;
2937         struct i40e_aqc_add_veb *cmd =
2938                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2939         struct i40e_aqc_add_veb_completion *resp =
2940                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2941         enum i40e_status_code status;
2942         u16 veb_flags = 0;
2943
2944         /* SEIDs need to either both be set or both be 0 for floating VEB */
2945         if (!!uplink_seid != !!downlink_seid)
2946                 return I40E_ERR_PARAM;
2947
2948         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2949
2950         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2951         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2952         cmd->enable_tcs = enabled_tc;
2953         if (!uplink_seid)
2954                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2955         if (default_port)
2956                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2957         else
2958                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2959
2960         /* reverse logic here: set the bitflag to disable the stats */
2961         if (!enable_stats)
2962                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2963
2964         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2965
2966         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2967
2968         if (!status && veb_seid)
2969                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2970
2971         return status;
2972 }
2973
2974 /**
2975  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2976  * @hw: pointer to the hw struct
2977  * @veb_seid: the SEID of the VEB to query
2978  * @switch_id: the uplink switch id
2979  * @floating: set to true if the VEB is floating
2980  * @statistic_index: index of the stats counter block for this VEB
2981  * @vebs_used: number of VEB's used by function
2982  * @vebs_free: total VEB's not reserved by any function
2983  * @cmd_details: pointer to command details structure or NULL
2984  *
2985  * This retrieves the parameters for a particular VEB, specified by
2986  * uplink_seid, and returns them to the caller.
2987  **/
2988 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2989                                 u16 veb_seid, u16 *switch_id,
2990                                 bool *floating, u16 *statistic_index,
2991                                 u16 *vebs_used, u16 *vebs_free,
2992                                 struct i40e_asq_cmd_details *cmd_details)
2993 {
2994         struct i40e_aq_desc desc;
2995         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2996                 (struct i40e_aqc_get_veb_parameters_completion *)
2997                 &desc.params.raw;
2998         enum i40e_status_code status;
2999
3000         if (veb_seid == 0)
3001                 return I40E_ERR_PARAM;
3002
3003         i40e_fill_default_direct_cmd_desc(&desc,
3004                                           i40e_aqc_opc_get_veb_parameters);
3005         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3006
3007         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3008         if (status)
3009                 goto get_veb_exit;
3010
3011         if (switch_id)
3012                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3013         if (statistic_index)
3014                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3015         if (vebs_used)
3016                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3017         if (vebs_free)
3018                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3019         if (floating) {
3020                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3021
3022                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3023                         *floating = true;
3024                 else
3025                         *floating = false;
3026         }
3027
3028 get_veb_exit:
3029         return status;
3030 }
3031
3032 /**
3033  * i40e_aq_add_macvlan
3034  * @hw: pointer to the hw struct
3035  * @seid: VSI for the mac address
3036  * @mv_list: list of macvlans to be added
3037  * @count: length of the list
3038  * @cmd_details: pointer to command details structure or NULL
3039  *
3040  * Add MAC/VLAN addresses to the HW filtering
3041  **/
3042 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3043                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3044                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3045 {
3046         struct i40e_aq_desc desc;
3047         struct i40e_aqc_macvlan *cmd =
3048                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3049         enum i40e_status_code status;
3050         u16 buf_size;
3051         int i;
3052
3053         if (count == 0 || !mv_list || !hw)
3054                 return I40E_ERR_PARAM;
3055
3056         buf_size = count * sizeof(*mv_list);
3057
3058         /* prep the rest of the request */
3059         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3060         cmd->num_addresses = CPU_TO_LE16(count);
3061         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3062         cmd->seid[1] = 0;
3063         cmd->seid[2] = 0;
3064
3065         for (i = 0; i < count; i++)
3066                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3067                         mv_list[i].flags |=
3068                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3069
3070         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3071         if (buf_size > I40E_AQ_LARGE_BUF)
3072                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3073
3074         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3075                                        cmd_details);
3076
3077         return status;
3078 }
3079
3080 /**
3081  * i40e_aq_remove_macvlan
3082  * @hw: pointer to the hw struct
3083  * @seid: VSI for the mac address
3084  * @mv_list: list of macvlans to be removed
3085  * @count: length of the list
3086  * @cmd_details: pointer to command details structure or NULL
3087  *
3088  * Remove MAC/VLAN addresses from the HW filtering
3089  **/
3090 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3091                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3092                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3093 {
3094         struct i40e_aq_desc desc;
3095         struct i40e_aqc_macvlan *cmd =
3096                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3097         enum i40e_status_code status;
3098         u16 buf_size;
3099
3100         if (count == 0 || !mv_list || !hw)
3101                 return I40E_ERR_PARAM;
3102
3103         buf_size = count * sizeof(*mv_list);
3104
3105         /* prep the rest of the request */
3106         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3107         cmd->num_addresses = CPU_TO_LE16(count);
3108         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3109         cmd->seid[1] = 0;
3110         cmd->seid[2] = 0;
3111
3112         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3113         if (buf_size > I40E_AQ_LARGE_BUF)
3114                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3115
3116         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3117                                        cmd_details);
3118
3119         return status;
3120 }
3121
3122 /**
3123  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3124  * @hw: pointer to the hw struct
3125  * @opcode: AQ opcode for add or delete mirror rule
3126  * @sw_seid: Switch SEID (to which rule refers)
3127  * @rule_type: Rule Type (ingress/egress/VLAN)
3128  * @id: Destination VSI SEID or Rule ID
3129  * @count: length of the list
3130  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3131  * @cmd_details: pointer to command details structure or NULL
3132  * @rule_id: Rule ID returned from FW
3133  * @rules_used: Number of rules used in internal switch
3134  * @rules_free: Number of rules free in internal switch
3135  *
3136  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3137  * VEBs/VEPA elements only
3138  **/
3139 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3140                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3141                         u16 count, __le16 *mr_list,
3142                         struct i40e_asq_cmd_details *cmd_details,
3143                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3144 {
3145         struct i40e_aq_desc desc;
3146         struct i40e_aqc_add_delete_mirror_rule *cmd =
3147                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3148         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3149         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3150         enum i40e_status_code status;
3151         u16 buf_size;
3152
3153         buf_size = count * sizeof(*mr_list);
3154
3155         /* prep the rest of the request */
3156         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3157         cmd->seid = CPU_TO_LE16(sw_seid);
3158         cmd->rule_type = CPU_TO_LE16(rule_type &
3159                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3160         cmd->num_entries = CPU_TO_LE16(count);
3161         /* Dest VSI for add, rule_id for delete */
3162         cmd->destination = CPU_TO_LE16(id);
3163         if (mr_list) {
3164                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3165                                                 I40E_AQ_FLAG_RD));
3166                 if (buf_size > I40E_AQ_LARGE_BUF)
3167                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3168         }
3169
3170         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3171                                        cmd_details);
3172         if (status == I40E_SUCCESS ||
3173             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3174                 if (rule_id)
3175                         *rule_id = LE16_TO_CPU(resp->rule_id);
3176                 if (rules_used)
3177                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3178                 if (rules_free)
3179                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3180         }
3181         return status;
3182 }
3183
3184 /**
3185  * i40e_aq_add_mirrorrule - add a mirror rule
3186  * @hw: pointer to the hw struct
3187  * @sw_seid: Switch SEID (to which rule refers)
3188  * @rule_type: Rule Type (ingress/egress/VLAN)
3189  * @dest_vsi: SEID of VSI to which packets will be mirrored
3190  * @count: length of the list
3191  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3192  * @cmd_details: pointer to command details structure or NULL
3193  * @rule_id: Rule ID returned from FW
3194  * @rules_used: Number of rules used in internal switch
3195  * @rules_free: Number of rules free in internal switch
3196  *
3197  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3198  **/
3199 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3200                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3201                         struct i40e_asq_cmd_details *cmd_details,
3202                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3203 {
3204         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3205             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3206                 if (count == 0 || !mr_list)
3207                         return I40E_ERR_PARAM;
3208         }
3209
3210         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3211                                   rule_type, dest_vsi, count, mr_list,
3212                                   cmd_details, rule_id, rules_used, rules_free);
3213 }
3214
3215 /**
3216  * i40e_aq_delete_mirrorrule - delete a mirror rule
3217  * @hw: pointer to the hw struct
3218  * @sw_seid: Switch SEID (to which rule refers)
3219  * @rule_type: Rule Type (ingress/egress/VLAN)
3220  * @count: length of the list
3221  * @rule_id: Rule ID that is returned in the receive desc as part of
3222  *              add_mirrorrule.
3223  * @mr_list: list of mirrored VLAN IDs to be removed
3224  * @cmd_details: pointer to command details structure or NULL
3225  * @rules_used: Number of rules used in internal switch
3226  * @rules_free: Number of rules free in internal switch
3227  *
3228  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3229  **/
3230 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3231                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3232                         struct i40e_asq_cmd_details *cmd_details,
3233                         u16 *rules_used, u16 *rules_free)
3234 {
3235         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3236         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3237                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3238                  * mirroring. For other rule_type, count and rule_type should
3239                  * not matter.
3240                  */
3241                 if (count == 0 || !mr_list)
3242                         return I40E_ERR_PARAM;
3243         }
3244
3245         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3246                                   rule_type, rule_id, count, mr_list,
3247                                   cmd_details, NULL, rules_used, rules_free);
3248 }
3249
3250 /**
3251  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3252  * @hw: pointer to the hw struct
3253  * @seid: VSI for the vlan filters
3254  * @v_list: list of vlan filters to be added
3255  * @count: length of the list
3256  * @cmd_details: pointer to command details structure or NULL
3257  **/
3258 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3259                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3260                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3261 {
3262         struct i40e_aq_desc desc;
3263         struct i40e_aqc_macvlan *cmd =
3264                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3265         enum i40e_status_code status;
3266         u16 buf_size;
3267
3268         if (count == 0 || !v_list || !hw)
3269                 return I40E_ERR_PARAM;
3270
3271         buf_size = count * sizeof(*v_list);
3272
3273         /* prep the rest of the request */
3274         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3275         cmd->num_addresses = CPU_TO_LE16(count);
3276         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3277         cmd->seid[1] = 0;
3278         cmd->seid[2] = 0;
3279
3280         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3281         if (buf_size > I40E_AQ_LARGE_BUF)
3282                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3283
3284         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3285                                        cmd_details);
3286
3287         return status;
3288 }
3289
3290 /**
3291  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3292  * @hw: pointer to the hw struct
3293  * @seid: VSI for the vlan filters
3294  * @v_list: list of macvlans to be removed
3295  * @count: length of the list
3296  * @cmd_details: pointer to command details structure or NULL
3297  **/
3298 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3299                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3300                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3301 {
3302         struct i40e_aq_desc desc;
3303         struct i40e_aqc_macvlan *cmd =
3304                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3305         enum i40e_status_code status;
3306         u16 buf_size;
3307
3308         if (count == 0 || !v_list || !hw)
3309                 return I40E_ERR_PARAM;
3310
3311         buf_size = count * sizeof(*v_list);
3312
3313         /* prep the rest of the request */
3314         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3315         cmd->num_addresses = CPU_TO_LE16(count);
3316         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3317         cmd->seid[1] = 0;
3318         cmd->seid[2] = 0;
3319
3320         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3321         if (buf_size > I40E_AQ_LARGE_BUF)
3322                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3323
3324         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3325                                        cmd_details);
3326
3327         return status;
3328 }
3329
3330 /**
3331  * i40e_aq_send_msg_to_vf
3332  * @hw: pointer to the hardware structure
3333  * @vfid: vf id to send msg
3334  * @v_opcode: opcodes for VF-PF communication
3335  * @v_retval: return error code
3336  * @msg: pointer to the msg buffer
3337  * @msglen: msg length
3338  * @cmd_details: pointer to command details
3339  *
3340  * send msg to vf
3341  **/
3342 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3343                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3344                                 struct i40e_asq_cmd_details *cmd_details)
3345 {
3346         struct i40e_aq_desc desc;
3347         struct i40e_aqc_pf_vf_message *cmd =
3348                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3349         enum i40e_status_code status;
3350
3351         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3352         cmd->id = CPU_TO_LE32(vfid);
3353         desc.cookie_high = CPU_TO_LE32(v_opcode);
3354         desc.cookie_low = CPU_TO_LE32(v_retval);
3355         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3356         if (msglen) {
3357                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3358                                                 I40E_AQ_FLAG_RD));
3359                 if (msglen > I40E_AQ_LARGE_BUF)
3360                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3361                 desc.datalen = CPU_TO_LE16(msglen);
3362         }
3363         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3364
3365         return status;
3366 }
3367
3368 /**
3369  * i40e_aq_debug_read_register
3370  * @hw: pointer to the hw struct
3371  * @reg_addr: register address
3372  * @reg_val: register value
3373  * @cmd_details: pointer to command details structure or NULL
3374  *
3375  * Read the register using the admin queue commands
3376  **/
3377 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3378                                 u32 reg_addr, u64 *reg_val,
3379                                 struct i40e_asq_cmd_details *cmd_details)
3380 {
3381         struct i40e_aq_desc desc;
3382         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3383                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3384         enum i40e_status_code status;
3385
3386         if (reg_val == NULL)
3387                 return I40E_ERR_PARAM;
3388
3389         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3390
3391         cmd_resp->address = CPU_TO_LE32(reg_addr);
3392
3393         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3394
3395         if (status == I40E_SUCCESS) {
3396                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3397                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3398         }
3399
3400         return status;
3401 }
3402
3403 /**
3404  * i40e_aq_debug_write_register
3405  * @hw: pointer to the hw struct
3406  * @reg_addr: register address
3407  * @reg_val: register value
3408  * @cmd_details: pointer to command details structure or NULL
3409  *
3410  * Write to a register using the admin queue commands
3411  **/
3412 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3413                                 u32 reg_addr, u64 reg_val,
3414                                 struct i40e_asq_cmd_details *cmd_details)
3415 {
3416         struct i40e_aq_desc desc;
3417         struct i40e_aqc_debug_reg_read_write *cmd =
3418                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3419         enum i40e_status_code status;
3420
3421         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3422
3423         cmd->address = CPU_TO_LE32(reg_addr);
3424         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3425         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3426
3427         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3428
3429         return status;
3430 }
3431
3432 /**
3433  * i40e_aq_request_resource
3434  * @hw: pointer to the hw struct
3435  * @resource: resource id
3436  * @access: access type
3437  * @sdp_number: resource number
3438  * @timeout: the maximum time in ms that the driver may hold the resource
3439  * @cmd_details: pointer to command details structure or NULL
3440  *
3441  * requests common resource using the admin queue commands
3442  **/
3443 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3444                                 enum i40e_aq_resources_ids resource,
3445                                 enum i40e_aq_resource_access_type access,
3446                                 u8 sdp_number, u64 *timeout,
3447                                 struct i40e_asq_cmd_details *cmd_details)
3448 {
3449         struct i40e_aq_desc desc;
3450         struct i40e_aqc_request_resource *cmd_resp =
3451                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3452         enum i40e_status_code status;
3453
3454         DEBUGFUNC("i40e_aq_request_resource");
3455
3456         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3457
3458         cmd_resp->resource_id = CPU_TO_LE16(resource);
3459         cmd_resp->access_type = CPU_TO_LE16(access);
3460         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3461
3462         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3463         /* The completion specifies the maximum time in ms that the driver
3464          * may hold the resource in the Timeout field.
3465          * If the resource is held by someone else, the command completes with
3466          * busy return value and the timeout field indicates the maximum time
3467          * the current owner of the resource has to free it.
3468          */
3469         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3470                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3471
3472         return status;
3473 }
3474
3475 /**
3476  * i40e_aq_release_resource
3477  * @hw: pointer to the hw struct
3478  * @resource: resource id
3479  * @sdp_number: resource number
3480  * @cmd_details: pointer to command details structure or NULL
3481  *
3482  * release common resource using the admin queue commands
3483  **/
3484 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3485                                 enum i40e_aq_resources_ids resource,
3486                                 u8 sdp_number,
3487                                 struct i40e_asq_cmd_details *cmd_details)
3488 {
3489         struct i40e_aq_desc desc;
3490         struct i40e_aqc_request_resource *cmd =
3491                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3492         enum i40e_status_code status;
3493
3494         DEBUGFUNC("i40e_aq_release_resource");
3495
3496         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3497
3498         cmd->resource_id = CPU_TO_LE16(resource);
3499         cmd->resource_number = CPU_TO_LE32(sdp_number);
3500
3501         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3502
3503         return status;
3504 }
3505
3506 /**
3507  * i40e_aq_read_nvm
3508  * @hw: pointer to the hw struct
3509  * @module_pointer: module pointer location in words from the NVM beginning
3510  * @offset: byte offset from the module beginning
3511  * @length: length of the section to be read (in bytes from the offset)
3512  * @data: command buffer (size [bytes] = length)
3513  * @last_command: tells if this is the last command in a series
3514  * @cmd_details: pointer to command details structure or NULL
3515  *
3516  * Read the NVM using the admin queue commands
3517  **/
3518 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3519                                 u32 offset, u16 length, void *data,
3520                                 bool last_command,
3521                                 struct i40e_asq_cmd_details *cmd_details)
3522 {
3523         struct i40e_aq_desc desc;
3524         struct i40e_aqc_nvm_update *cmd =
3525                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3526         enum i40e_status_code status;
3527
3528         DEBUGFUNC("i40e_aq_read_nvm");
3529
3530         /* In offset the highest byte must be zeroed. */
3531         if (offset & 0xFF000000) {
3532                 status = I40E_ERR_PARAM;
3533                 goto i40e_aq_read_nvm_exit;
3534         }
3535
3536         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3537
3538         /* If this is the last command in a series, set the proper flag. */
3539         if (last_command)
3540                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3541         cmd->module_pointer = module_pointer;
3542         cmd->offset = CPU_TO_LE32(offset);
3543         cmd->length = CPU_TO_LE16(length);
3544
3545         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3546         if (length > I40E_AQ_LARGE_BUF)
3547                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3548
3549         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3550
3551 i40e_aq_read_nvm_exit:
3552         return status;
3553 }
3554
3555 /**
3556  * i40e_aq_read_nvm_config - read an nvm config block
3557  * @hw: pointer to the hw struct
3558  * @cmd_flags: NVM access admin command bits
3559  * @field_id: field or feature id
3560  * @data: buffer for result
3561  * @buf_size: buffer size
3562  * @element_count: pointer to count of elements read by FW
3563  * @cmd_details: pointer to command details structure or NULL
3564  **/
3565 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3566                                 u8 cmd_flags, u32 field_id, void *data,
3567                                 u16 buf_size, u16 *element_count,
3568                                 struct i40e_asq_cmd_details *cmd_details)
3569 {
3570         struct i40e_aq_desc desc;
3571         struct i40e_aqc_nvm_config_read *cmd =
3572                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3573         enum i40e_status_code status;
3574
3575         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3576         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3577         if (buf_size > I40E_AQ_LARGE_BUF)
3578                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3579
3580         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3581         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3582         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3583                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3584         else
3585                 cmd->element_id_msw = 0;
3586
3587         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3588
3589         if (!status && element_count)
3590                 *element_count = LE16_TO_CPU(cmd->element_count);
3591
3592         return status;
3593 }
3594
3595 /**
3596  * i40e_aq_write_nvm_config - write an nvm config block
3597  * @hw: pointer to the hw struct
3598  * @cmd_flags: NVM access admin command bits
3599  * @data: buffer for result
3600  * @buf_size: buffer size
3601  * @element_count: count of elements to be written
3602  * @cmd_details: pointer to command details structure or NULL
3603  **/
3604 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3605                                 u8 cmd_flags, void *data, u16 buf_size,
3606                                 u16 element_count,
3607                                 struct i40e_asq_cmd_details *cmd_details)
3608 {
3609         struct i40e_aq_desc desc;
3610         struct i40e_aqc_nvm_config_write *cmd =
3611                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3612         enum i40e_status_code status;
3613
3614         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3615         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3616         if (buf_size > I40E_AQ_LARGE_BUF)
3617                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3618
3619         cmd->element_count = CPU_TO_LE16(element_count);
3620         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3621         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3622
3623         return status;
3624 }
3625
3626 /**
3627  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3628  * @hw: pointer to the hw struct
3629  * @buff: buffer for result
3630  * @buff_size: buffer size
3631  * @cmd_details: pointer to command details structure or NULL
3632  **/
3633 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3634                                 void *buff, u16 buff_size,
3635                                 struct i40e_asq_cmd_details *cmd_details)
3636 {
3637         struct i40e_aq_desc desc;
3638         enum i40e_status_code status;
3639
3640         UNREFERENCED_2PARAMETER(buff, buff_size);
3641
3642         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3643         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3644         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3645                 status = I40E_ERR_NOT_IMPLEMENTED;
3646
3647         return status;
3648 }
3649
3650 /**
3651  * i40e_aq_erase_nvm
3652  * @hw: pointer to the hw struct
3653  * @module_pointer: module pointer location in words from the NVM beginning
3654  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3655  * @length: length of the section to be erased (expressed in 4 KB)
3656  * @last_command: tells if this is the last command in a series
3657  * @cmd_details: pointer to command details structure or NULL
3658  *
3659  * Erase the NVM sector using the admin queue commands
3660  **/
3661 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3662                                 u32 offset, u16 length, bool last_command,
3663                                 struct i40e_asq_cmd_details *cmd_details)
3664 {
3665         struct i40e_aq_desc desc;
3666         struct i40e_aqc_nvm_update *cmd =
3667                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3668         enum i40e_status_code status;
3669
3670         DEBUGFUNC("i40e_aq_erase_nvm");
3671
3672         /* In offset the highest byte must be zeroed. */
3673         if (offset & 0xFF000000) {
3674                 status = I40E_ERR_PARAM;
3675                 goto i40e_aq_erase_nvm_exit;
3676         }
3677
3678         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3679
3680         /* If this is the last command in a series, set the proper flag. */
3681         if (last_command)
3682                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3683         cmd->module_pointer = module_pointer;
3684         cmd->offset = CPU_TO_LE32(offset);
3685         cmd->length = CPU_TO_LE16(length);
3686
3687         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3688
3689 i40e_aq_erase_nvm_exit:
3690         return status;
3691 }
3692
3693 /**
3694  * i40e_parse_discover_capabilities
3695  * @hw: pointer to the hw struct
3696  * @buff: pointer to a buffer containing device/function capability records
3697  * @cap_count: number of capability records in the list
3698  * @list_type_opc: type of capabilities list to parse
3699  *
3700  * Parse the device/function capabilities list.
3701  **/
3702 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3703                                      u32 cap_count,
3704                                      enum i40e_admin_queue_opc list_type_opc)
3705 {
3706         struct i40e_aqc_list_capabilities_element_resp *cap;
3707         u32 valid_functions, num_functions;
3708         u32 number, logical_id, phys_id;
3709         struct i40e_hw_capabilities *p;
3710         enum i40e_status_code status;
3711         u16 id, ocp_cfg_word0;
3712         u8 major_rev;
3713         u32 i = 0;
3714
3715         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3716
3717         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3718                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3719         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3720                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3721         else
3722                 return;
3723
3724         for (i = 0; i < cap_count; i++, cap++) {
3725                 id = LE16_TO_CPU(cap->id);
3726                 number = LE32_TO_CPU(cap->number);
3727                 logical_id = LE32_TO_CPU(cap->logical_id);
3728                 phys_id = LE32_TO_CPU(cap->phys_id);
3729                 major_rev = cap->major_rev;
3730
3731                 switch (id) {
3732                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3733                         p->switch_mode = number;
3734                         i40e_debug(hw, I40E_DEBUG_INIT,
3735                                    "HW Capability: Switch mode = %d\n",
3736                                    p->switch_mode);
3737                         break;
3738                 case I40E_AQ_CAP_ID_MNG_MODE:
3739                         p->management_mode = number;
3740                         if (major_rev > 1) {
3741                                 p->mng_protocols_over_mctp = logical_id;
3742                                 i40e_debug(hw, I40E_DEBUG_INIT,
3743                                            "HW Capability: Protocols over MCTP = %d\n",
3744                                            p->mng_protocols_over_mctp);
3745                         } else {
3746                                 p->mng_protocols_over_mctp = 0;
3747                         }
3748                         i40e_debug(hw, I40E_DEBUG_INIT,
3749                                    "HW Capability: Management Mode = %d\n",
3750                                    p->management_mode);
3751                         break;
3752                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3753                         p->npar_enable = number;
3754                         i40e_debug(hw, I40E_DEBUG_INIT,
3755                                    "HW Capability: NPAR enable = %d\n",
3756                                    p->npar_enable);
3757                         break;
3758                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3759                         p->os2bmc = number;
3760                         i40e_debug(hw, I40E_DEBUG_INIT,
3761                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3762                         break;
3763                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3764                         p->valid_functions = number;
3765                         i40e_debug(hw, I40E_DEBUG_INIT,
3766                                    "HW Capability: Valid Functions = %d\n",
3767                                    p->valid_functions);
3768                         break;
3769                 case I40E_AQ_CAP_ID_SRIOV:
3770                         if (number == 1)
3771                                 p->sr_iov_1_1 = true;
3772                         i40e_debug(hw, I40E_DEBUG_INIT,
3773                                    "HW Capability: SR-IOV = %d\n",
3774                                    p->sr_iov_1_1);
3775                         break;
3776                 case I40E_AQ_CAP_ID_VF:
3777                         p->num_vfs = number;
3778                         p->vf_base_id = logical_id;
3779                         i40e_debug(hw, I40E_DEBUG_INIT,
3780                                    "HW Capability: VF count = %d\n",
3781                                    p->num_vfs);
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: VF base_id = %d\n",
3784                                    p->vf_base_id);
3785                         break;
3786                 case I40E_AQ_CAP_ID_VMDQ:
3787                         if (number == 1)
3788                                 p->vmdq = true;
3789                         i40e_debug(hw, I40E_DEBUG_INIT,
3790                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3791                         break;
3792                 case I40E_AQ_CAP_ID_8021QBG:
3793                         if (number == 1)
3794                                 p->evb_802_1_qbg = true;
3795                         i40e_debug(hw, I40E_DEBUG_INIT,
3796                                    "HW Capability: 802.1Qbg = %d\n", number);
3797                         break;
3798                 case I40E_AQ_CAP_ID_8021QBR:
3799                         if (number == 1)
3800                                 p->evb_802_1_qbh = true;
3801                         i40e_debug(hw, I40E_DEBUG_INIT,
3802                                    "HW Capability: 802.1Qbh = %d\n", number);
3803                         break;
3804                 case I40E_AQ_CAP_ID_VSI:
3805                         p->num_vsis = number;
3806                         i40e_debug(hw, I40E_DEBUG_INIT,
3807                                    "HW Capability: VSI count = %d\n",
3808                                    p->num_vsis);
3809                         break;
3810                 case I40E_AQ_CAP_ID_DCB:
3811                         if (number == 1) {
3812                                 p->dcb = true;
3813                                 p->enabled_tcmap = logical_id;
3814                                 p->maxtc = phys_id;
3815                         }
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: DCB = %d\n", p->dcb);
3818                         i40e_debug(hw, I40E_DEBUG_INIT,
3819                                    "HW Capability: TC Mapping = %d\n",
3820                                    logical_id);
3821                         i40e_debug(hw, I40E_DEBUG_INIT,
3822                                    "HW Capability: TC Max = %d\n", p->maxtc);
3823                         break;
3824                 case I40E_AQ_CAP_ID_FCOE:
3825                         if (number == 1)
3826                                 p->fcoe = true;
3827                         i40e_debug(hw, I40E_DEBUG_INIT,
3828                                    "HW Capability: FCOE = %d\n", p->fcoe);
3829                         break;
3830                 case I40E_AQ_CAP_ID_ISCSI:
3831                         if (number == 1)
3832                                 p->iscsi = true;
3833                         i40e_debug(hw, I40E_DEBUG_INIT,
3834                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3835                         break;
3836                 case I40E_AQ_CAP_ID_RSS:
3837                         p->rss = true;
3838                         p->rss_table_size = number;
3839                         p->rss_table_entry_width = logical_id;
3840                         i40e_debug(hw, I40E_DEBUG_INIT,
3841                                    "HW Capability: RSS = %d\n", p->rss);
3842                         i40e_debug(hw, I40E_DEBUG_INIT,
3843                                    "HW Capability: RSS table size = %d\n",
3844                                    p->rss_table_size);
3845                         i40e_debug(hw, I40E_DEBUG_INIT,
3846                                    "HW Capability: RSS table width = %d\n",
3847                                    p->rss_table_entry_width);
3848                         break;
3849                 case I40E_AQ_CAP_ID_RXQ:
3850                         p->num_rx_qp = number;
3851                         p->base_queue = phys_id;
3852                         i40e_debug(hw, I40E_DEBUG_INIT,
3853                                    "HW Capability: Rx QP = %d\n", number);
3854                         i40e_debug(hw, I40E_DEBUG_INIT,
3855                                    "HW Capability: base_queue = %d\n",
3856                                    p->base_queue);
3857                         break;
3858                 case I40E_AQ_CAP_ID_TXQ:
3859                         p->num_tx_qp = number;
3860                         p->base_queue = phys_id;
3861                         i40e_debug(hw, I40E_DEBUG_INIT,
3862                                    "HW Capability: Tx QP = %d\n", number);
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: base_queue = %d\n",
3865                                    p->base_queue);
3866                         break;
3867                 case I40E_AQ_CAP_ID_MSIX:
3868                         p->num_msix_vectors = number;
3869                         i40e_debug(hw, I40E_DEBUG_INIT,
3870                                    "HW Capability: MSIX vector count = %d\n",
3871                                    p->num_msix_vectors);
3872                         break;
3873                 case I40E_AQ_CAP_ID_VF_MSIX:
3874                         p->num_msix_vectors_vf = number;
3875                         i40e_debug(hw, I40E_DEBUG_INIT,
3876                                    "HW Capability: MSIX VF vector count = %d\n",
3877                                    p->num_msix_vectors_vf);
3878                         break;
3879                 case I40E_AQ_CAP_ID_FLEX10:
3880                         if (major_rev == 1) {
3881                                 if (number == 1) {
3882                                         p->flex10_enable = true;
3883                                         p->flex10_capable = true;
3884                                 }
3885                         } else {
3886                                 /* Capability revision >= 2 */
3887                                 if (number & 1)
3888                                         p->flex10_enable = true;
3889                                 if (number & 2)
3890                                         p->flex10_capable = true;
3891                         }
3892                         p->flex10_mode = logical_id;
3893                         p->flex10_status = phys_id;
3894                         i40e_debug(hw, I40E_DEBUG_INIT,
3895                                    "HW Capability: Flex10 mode = %d\n",
3896                                    p->flex10_mode);
3897                         i40e_debug(hw, I40E_DEBUG_INIT,
3898                                    "HW Capability: Flex10 status = %d\n",
3899                                    p->flex10_status);
3900                         break;
3901                 case I40E_AQ_CAP_ID_CEM:
3902                         if (number == 1)
3903                                 p->mgmt_cem = true;
3904                         i40e_debug(hw, I40E_DEBUG_INIT,
3905                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3906                         break;
3907                 case I40E_AQ_CAP_ID_IWARP:
3908                         if (number == 1)
3909                                 p->iwarp = true;
3910                         i40e_debug(hw, I40E_DEBUG_INIT,
3911                                    "HW Capability: iWARP = %d\n", p->iwarp);
3912                         break;
3913                 case I40E_AQ_CAP_ID_LED:
3914                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3915                                 p->led[phys_id] = true;
3916                         i40e_debug(hw, I40E_DEBUG_INIT,
3917                                    "HW Capability: LED - PIN %d\n", phys_id);
3918                         break;
3919                 case I40E_AQ_CAP_ID_SDP:
3920                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3921                                 p->sdp[phys_id] = true;
3922                         i40e_debug(hw, I40E_DEBUG_INIT,
3923                                    "HW Capability: SDP - PIN %d\n", phys_id);
3924                         break;
3925                 case I40E_AQ_CAP_ID_MDIO:
3926                         if (number == 1) {
3927                                 p->mdio_port_num = phys_id;
3928                                 p->mdio_port_mode = logical_id;
3929                         }
3930                         i40e_debug(hw, I40E_DEBUG_INIT,
3931                                    "HW Capability: MDIO port number = %d\n",
3932                                    p->mdio_port_num);
3933                         i40e_debug(hw, I40E_DEBUG_INIT,
3934                                    "HW Capability: MDIO port mode = %d\n",
3935                                    p->mdio_port_mode);
3936                         break;
3937                 case I40E_AQ_CAP_ID_1588:
3938                         if (number == 1)
3939                                 p->ieee_1588 = true;
3940                         i40e_debug(hw, I40E_DEBUG_INIT,
3941                                    "HW Capability: IEEE 1588 = %d\n",
3942                                    p->ieee_1588);
3943                         break;
3944                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3945                         p->fd = true;
3946                         p->fd_filters_guaranteed = number;
3947                         p->fd_filters_best_effort = logical_id;
3948                         i40e_debug(hw, I40E_DEBUG_INIT,
3949                                    "HW Capability: Flow Director = 1\n");
3950                         i40e_debug(hw, I40E_DEBUG_INIT,
3951                                    "HW Capability: Guaranteed FD filters = %d\n",
3952                                    p->fd_filters_guaranteed);
3953                         break;
3954                 case I40E_AQ_CAP_ID_WSR_PROT:
3955                         p->wr_csr_prot = (u64)number;
3956                         p->wr_csr_prot |= (u64)logical_id << 32;
3957                         i40e_debug(hw, I40E_DEBUG_INIT,
3958                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3959                                    (p->wr_csr_prot & 0xffff));
3960                         break;
3961                 case I40E_AQ_CAP_ID_NVM_MGMT:
3962                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3963                                 p->sec_rev_disabled = true;
3964                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3965                                 p->update_disabled = true;
3966                         break;
3967                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3968                         hw->num_wol_proxy_filters = (u16)number;
3969                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3970                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3971                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3972                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3973                         else
3974                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3975                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3976                         i40e_debug(hw, I40E_DEBUG_INIT,
3977                                    "HW Capability: WOL proxy filters = %d\n",
3978                                    hw->num_wol_proxy_filters);
3979                         break;
3980                 default:
3981                         break;
3982                 }
3983         }
3984
3985         if (p->fcoe)
3986                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3987
3988         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3989         p->fcoe = false;
3990
3991         /* count the enabled ports (aka the "not disabled" ports) */
3992         hw->num_ports = 0;
3993         for (i = 0; i < 4; i++) {
3994                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3995                 u64 port_cfg = 0;
3996
3997                 /* use AQ read to get the physical register offset instead
3998                  * of the port relative offset
3999                  */
4000                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4001                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4002                         hw->num_ports++;
4003         }
4004
4005         /* OCP cards case: if a mezz is removed the ethernet port is at
4006          * disabled state in PRTGEN_CNF register. Additional NVM read is
4007          * needed in order to check if we are dealing with OCP card.
4008          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4009          * physical ports results in wrong partition id calculation and thus
4010          * not supporting WoL.
4011          */
4012         if (hw->mac.type == I40E_MAC_X722) {
4013                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4014                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4015                                                   2 * I40E_SR_OCP_CFG_WORD0,
4016                                                   sizeof(ocp_cfg_word0),
4017                                                   &ocp_cfg_word0, true, NULL);
4018                         if (status == I40E_SUCCESS &&
4019                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4020                                 hw->num_ports = 4;
4021                         i40e_release_nvm(hw);
4022                 }
4023         }
4024
4025         valid_functions = p->valid_functions;
4026         num_functions = 0;
4027         while (valid_functions) {
4028                 if (valid_functions & 1)
4029                         num_functions++;
4030                 valid_functions >>= 1;
4031         }
4032
4033         /* partition id is 1-based, and functions are evenly spread
4034          * across the ports as partitions
4035          */
4036         if (hw->num_ports != 0) {
4037                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4038                 hw->num_partitions = num_functions / hw->num_ports;
4039         }
4040
4041         /* additional HW specific goodies that might
4042          * someday be HW version specific
4043          */
4044         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4045 }
4046
4047 /**
4048  * i40e_aq_discover_capabilities
4049  * @hw: pointer to the hw struct
4050  * @buff: a virtual buffer to hold the capabilities
4051  * @buff_size: Size of the virtual buffer
4052  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4053  * @list_type_opc: capabilities type to discover - pass in the command opcode
4054  * @cmd_details: pointer to command details structure or NULL
4055  *
4056  * Get the device capabilities descriptions from the firmware
4057  **/
4058 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4059                                 void *buff, u16 buff_size, u16 *data_size,
4060                                 enum i40e_admin_queue_opc list_type_opc,
4061                                 struct i40e_asq_cmd_details *cmd_details)
4062 {
4063         struct i40e_aqc_list_capabilites *cmd;
4064         struct i40e_aq_desc desc;
4065         enum i40e_status_code status = I40E_SUCCESS;
4066
4067         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4068
4069         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4070                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4071                 status = I40E_ERR_PARAM;
4072                 goto exit;
4073         }
4074
4075         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4076
4077         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4078         if (buff_size > I40E_AQ_LARGE_BUF)
4079                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4080
4081         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4082         *data_size = LE16_TO_CPU(desc.datalen);
4083
4084         if (status)
4085                 goto exit;
4086
4087         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4088                                          list_type_opc);
4089
4090 exit:
4091         return status;
4092 }
4093
4094 /**
4095  * i40e_aq_update_nvm
4096  * @hw: pointer to the hw struct
4097  * @module_pointer: module pointer location in words from the NVM beginning
4098  * @offset: byte offset from the module beginning
4099  * @length: length of the section to be written (in bytes from the offset)
4100  * @data: command buffer (size [bytes] = length)
4101  * @last_command: tells if this is the last command in a series
4102  * @preservation_flags: Preservation mode flags
4103  * @cmd_details: pointer to command details structure or NULL
4104  *
4105  * Update the NVM using the admin queue commands
4106  **/
4107 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4108                                 u32 offset, u16 length, void *data,
4109                                 bool last_command, u8 preservation_flags,
4110                                 struct i40e_asq_cmd_details *cmd_details)
4111 {
4112         struct i40e_aq_desc desc;
4113         struct i40e_aqc_nvm_update *cmd =
4114                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4115         enum i40e_status_code status;
4116
4117         DEBUGFUNC("i40e_aq_update_nvm");
4118
4119         /* In offset the highest byte must be zeroed. */
4120         if (offset & 0xFF000000) {
4121                 status = I40E_ERR_PARAM;
4122                 goto i40e_aq_update_nvm_exit;
4123         }
4124
4125         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4126
4127         /* If this is the last command in a series, set the proper flag. */
4128         if (last_command)
4129                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4130         if (hw->mac.type == I40E_MAC_X722) {
4131                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4132                         cmd->command_flags |=
4133                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4134                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4135                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4136                         cmd->command_flags |=
4137                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4138                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4139         }
4140         cmd->module_pointer = module_pointer;
4141         cmd->offset = CPU_TO_LE32(offset);
4142         cmd->length = CPU_TO_LE16(length);
4143
4144         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4145         if (length > I40E_AQ_LARGE_BUF)
4146                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4147
4148         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4149
4150 i40e_aq_update_nvm_exit:
4151         return status;
4152 }
4153
4154 /**
4155  * i40e_aq_rearrange_nvm
4156  * @hw: pointer to the hw struct
4157  * @rearrange_nvm: defines direction of rearrangement
4158  * @cmd_details: pointer to command details structure or NULL
4159  *
4160  * Rearrange NVM structure, available only for transition FW
4161  **/
4162 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4163                                 u8 rearrange_nvm,
4164                                 struct i40e_asq_cmd_details *cmd_details)
4165 {
4166         struct i40e_aqc_nvm_update *cmd;
4167         enum i40e_status_code status;
4168         struct i40e_aq_desc desc;
4169
4170         DEBUGFUNC("i40e_aq_rearrange_nvm");
4171
4172         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4173
4174         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4175
4176         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4177                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4178
4179         if (!rearrange_nvm) {
4180                 status = I40E_ERR_PARAM;
4181                 goto i40e_aq_rearrange_nvm_exit;
4182         }
4183
4184         cmd->command_flags |= rearrange_nvm;
4185         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4186
4187 i40e_aq_rearrange_nvm_exit:
4188         return status;
4189 }
4190
4191 /**
4192  * i40e_aq_nvm_progress
4193  * @hw: pointer to the hw struct
4194  * @progress: pointer to progress returned from AQ
4195  * @cmd_details: pointer to command details structure or NULL
4196  *
4197  * Gets progress of flash rearrangement process
4198  **/
4199 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4200                                 struct i40e_asq_cmd_details *cmd_details)
4201 {
4202         enum i40e_status_code status;
4203         struct i40e_aq_desc desc;
4204
4205         DEBUGFUNC("i40e_aq_nvm_progress");
4206
4207         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4208         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4209         *progress = desc.params.raw[0];
4210         return status;
4211 }
4212
4213 /**
4214  * i40e_aq_get_lldp_mib
4215  * @hw: pointer to the hw struct
4216  * @bridge_type: type of bridge requested
4217  * @mib_type: Local, Remote or both Local and Remote MIBs
4218  * @buff: pointer to a user supplied buffer to store the MIB block
4219  * @buff_size: size of the buffer (in bytes)
4220  * @local_len : length of the returned Local LLDP MIB
4221  * @remote_len: length of the returned Remote LLDP MIB
4222  * @cmd_details: pointer to command details structure or NULL
4223  *
4224  * Requests the complete LLDP MIB (entire packet).
4225  **/
4226 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4227                                 u8 mib_type, void *buff, u16 buff_size,
4228                                 u16 *local_len, u16 *remote_len,
4229                                 struct i40e_asq_cmd_details *cmd_details)
4230 {
4231         struct i40e_aq_desc desc;
4232         struct i40e_aqc_lldp_get_mib *cmd =
4233                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4234         struct i40e_aqc_lldp_get_mib *resp =
4235                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4236         enum i40e_status_code status;
4237
4238         if (buff_size == 0 || !buff)
4239                 return I40E_ERR_PARAM;
4240
4241         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4242         /* Indirect Command */
4243         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4244
4245         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4246         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4247                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4248
4249         desc.datalen = CPU_TO_LE16(buff_size);
4250
4251         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4252         if (buff_size > I40E_AQ_LARGE_BUF)
4253                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4254
4255         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4256         if (!status) {
4257                 if (local_len != NULL)
4258                         *local_len = LE16_TO_CPU(resp->local_len);
4259                 if (remote_len != NULL)
4260                         *remote_len = LE16_TO_CPU(resp->remote_len);
4261         }
4262
4263         return status;
4264 }
4265
4266  /**
4267  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4268  * @hw: pointer to the hw struct
4269  * @mib_type: Local, Remote or both Local and Remote MIBs
4270  * @buff: pointer to a user supplied buffer to store the MIB block
4271  * @buff_size: size of the buffer (in bytes)
4272  * @cmd_details: pointer to command details structure or NULL
4273  *
4274  * Set the LLDP MIB.
4275  **/
4276 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4277                                 u8 mib_type, void *buff, u16 buff_size,
4278                                 struct i40e_asq_cmd_details *cmd_details)
4279 {
4280         struct i40e_aq_desc desc;
4281         struct i40e_aqc_lldp_set_local_mib *cmd =
4282                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4283         enum i40e_status_code status;
4284
4285         if (buff_size == 0 || !buff)
4286                 return I40E_ERR_PARAM;
4287
4288         i40e_fill_default_direct_cmd_desc(&desc,
4289                                 i40e_aqc_opc_lldp_set_local_mib);
4290         /* Indirect Command */
4291         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4292         if (buff_size > I40E_AQ_LARGE_BUF)
4293                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4294         desc.datalen = CPU_TO_LE16(buff_size);
4295
4296         cmd->type = mib_type;
4297         cmd->length = CPU_TO_LE16(buff_size);
4298         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4299         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4300
4301         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4302         return status;
4303 }
4304
4305 /**
4306  * i40e_aq_cfg_lldp_mib_change_event
4307  * @hw: pointer to the hw struct
4308  * @enable_update: Enable or Disable event posting
4309  * @cmd_details: pointer to command details structure or NULL
4310  *
4311  * Enable or Disable posting of an event on ARQ when LLDP MIB
4312  * associated with the interface changes
4313  **/
4314 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4315                                 bool enable_update,
4316                                 struct i40e_asq_cmd_details *cmd_details)
4317 {
4318         struct i40e_aq_desc desc;
4319         struct i40e_aqc_lldp_update_mib *cmd =
4320                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4321         enum i40e_status_code status;
4322
4323         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4324
4325         if (!enable_update)
4326                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4327
4328         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4329
4330         return status;
4331 }
4332
4333 /**
4334  * i40e_aq_add_lldp_tlv
4335  * @hw: pointer to the hw struct
4336  * @bridge_type: type of bridge
4337  * @buff: buffer with TLV to add
4338  * @buff_size: length of the buffer
4339  * @tlv_len: length of the TLV to be added
4340  * @mib_len: length of the LLDP MIB returned in response
4341  * @cmd_details: pointer to command details structure or NULL
4342  *
4343  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4344  * it is responsibility of the caller to make sure that the TLV is not
4345  * already present in the LLDPDU.
4346  * In return firmware will write the complete LLDP MIB with the newly
4347  * added TLV in the response buffer.
4348  **/
4349 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4350                                 void *buff, u16 buff_size, u16 tlv_len,
4351                                 u16 *mib_len,
4352                                 struct i40e_asq_cmd_details *cmd_details)
4353 {
4354         struct i40e_aq_desc desc;
4355         struct i40e_aqc_lldp_add_tlv *cmd =
4356                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4357         enum i40e_status_code status;
4358
4359         if (buff_size == 0 || !buff || tlv_len == 0)
4360                 return I40E_ERR_PARAM;
4361
4362         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4363
4364         /* Indirect Command */
4365         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4366         if (buff_size > I40E_AQ_LARGE_BUF)
4367                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4368         desc.datalen = CPU_TO_LE16(buff_size);
4369
4370         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4371                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4372         cmd->len = CPU_TO_LE16(tlv_len);
4373
4374         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4375         if (!status) {
4376                 if (mib_len != NULL)
4377                         *mib_len = LE16_TO_CPU(desc.datalen);
4378         }
4379
4380         return status;
4381 }
4382
4383 /**
4384  * i40e_aq_update_lldp_tlv
4385  * @hw: pointer to the hw struct
4386  * @bridge_type: type of bridge
4387  * @buff: buffer with TLV to update
4388  * @buff_size: size of the buffer holding original and updated TLVs
4389  * @old_len: Length of the Original TLV
4390  * @new_len: Length of the Updated TLV
4391  * @offset: offset of the updated TLV in the buff
4392  * @mib_len: length of the returned LLDP MIB
4393  * @cmd_details: pointer to command details structure or NULL
4394  *
4395  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4396  * Firmware will place the complete LLDP MIB in response buffer with the
4397  * updated TLV.
4398  **/
4399 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4400                                 u8 bridge_type, void *buff, u16 buff_size,
4401                                 u16 old_len, u16 new_len, u16 offset,
4402                                 u16 *mib_len,
4403                                 struct i40e_asq_cmd_details *cmd_details)
4404 {
4405         struct i40e_aq_desc desc;
4406         struct i40e_aqc_lldp_update_tlv *cmd =
4407                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4408         enum i40e_status_code status;
4409
4410         if (buff_size == 0 || !buff || offset == 0 ||
4411             old_len == 0 || new_len == 0)
4412                 return I40E_ERR_PARAM;
4413
4414         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4415
4416         /* Indirect Command */
4417         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4418         if (buff_size > I40E_AQ_LARGE_BUF)
4419                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4420         desc.datalen = CPU_TO_LE16(buff_size);
4421
4422         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4423                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4424         cmd->old_len = CPU_TO_LE16(old_len);
4425         cmd->new_offset = CPU_TO_LE16(offset);
4426         cmd->new_len = CPU_TO_LE16(new_len);
4427
4428         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4429         if (!status) {
4430                 if (mib_len != NULL)
4431                         *mib_len = LE16_TO_CPU(desc.datalen);
4432         }
4433
4434         return status;
4435 }
4436
4437 /**
4438  * i40e_aq_delete_lldp_tlv
4439  * @hw: pointer to the hw struct
4440  * @bridge_type: type of bridge
4441  * @buff: pointer to a user supplied buffer that has the TLV
4442  * @buff_size: length of the buffer
4443  * @tlv_len: length of the TLV to be deleted
4444  * @mib_len: length of the returned LLDP MIB
4445  * @cmd_details: pointer to command details structure or NULL
4446  *
4447  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4448  * The firmware places the entire LLDP MIB in the response buffer.
4449  **/
4450 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4451                                 u8 bridge_type, void *buff, u16 buff_size,
4452                                 u16 tlv_len, u16 *mib_len,
4453                                 struct i40e_asq_cmd_details *cmd_details)
4454 {
4455         struct i40e_aq_desc desc;
4456         struct i40e_aqc_lldp_add_tlv *cmd =
4457                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4458         enum i40e_status_code status;
4459
4460         if (buff_size == 0 || !buff)
4461                 return I40E_ERR_PARAM;
4462
4463         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4464
4465         /* Indirect Command */
4466         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4467         if (buff_size > I40E_AQ_LARGE_BUF)
4468                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4469         desc.datalen = CPU_TO_LE16(buff_size);
4470         cmd->len = CPU_TO_LE16(tlv_len);
4471         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4472                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4473
4474         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4475         if (!status) {
4476                 if (mib_len != NULL)
4477                         *mib_len = LE16_TO_CPU(desc.datalen);
4478         }
4479
4480         return status;
4481 }
4482
4483 /**
4484  * i40e_aq_stop_lldp
4485  * @hw: pointer to the hw struct
4486  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4487  * @cmd_details: pointer to command details structure or NULL
4488  *
4489  * Stop or Shutdown the embedded LLDP Agent
4490  **/
4491 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4492                                 struct i40e_asq_cmd_details *cmd_details)
4493 {
4494         struct i40e_aq_desc desc;
4495         struct i40e_aqc_lldp_stop *cmd =
4496                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4497         enum i40e_status_code status;
4498
4499         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4500
4501         if (shutdown_agent)
4502                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4503
4504         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4505
4506         return status;
4507 }
4508
4509 /**
4510  * i40e_aq_start_lldp
4511  * @hw: pointer to the hw struct
4512  * @cmd_details: pointer to command details structure or NULL
4513  *
4514  * Start the embedded LLDP Agent on all ports.
4515  **/
4516 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4517                                 struct i40e_asq_cmd_details *cmd_details)
4518 {
4519         struct i40e_aq_desc desc;
4520         struct i40e_aqc_lldp_start *cmd =
4521                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4522         enum i40e_status_code status;
4523
4524         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4525
4526         cmd->command = I40E_AQ_LLDP_AGENT_START;
4527         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4528
4529         return status;
4530 }
4531
4532 /**
4533  * i40e_aq_set_dcb_parameters
4534  * @hw: pointer to the hw struct
4535  * @cmd_details: pointer to command details structure or NULL
4536  * @dcb_enable: True if DCB configuration needs to be applied
4537  *
4538  **/
4539 enum i40e_status_code
4540 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4541                            struct i40e_asq_cmd_details *cmd_details)
4542 {
4543         struct i40e_aq_desc desc;
4544         struct i40e_aqc_set_dcb_parameters *cmd =
4545                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4546         enum i40e_status_code status;
4547
4548         i40e_fill_default_direct_cmd_desc(&desc,
4549                                           i40e_aqc_opc_set_dcb_parameters);
4550
4551         if (dcb_enable) {
4552                 cmd->valid_flags = I40E_DCB_VALID;
4553                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4554         }
4555         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4556
4557         return status;
4558 }
4559
4560 /**
4561  * i40e_aq_get_cee_dcb_config
4562  * @hw: pointer to the hw struct
4563  * @buff: response buffer that stores CEE operational configuration
4564  * @buff_size: size of the buffer passed
4565  * @cmd_details: pointer to command details structure or NULL
4566  *
4567  * Get CEE DCBX mode operational configuration from firmware
4568  **/
4569 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4570                                 void *buff, u16 buff_size,
4571                                 struct i40e_asq_cmd_details *cmd_details)
4572 {
4573         struct i40e_aq_desc desc;
4574         enum i40e_status_code status;
4575
4576         if (buff_size == 0 || !buff)
4577                 return I40E_ERR_PARAM;
4578
4579         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4580
4581         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4582         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4583                                        cmd_details);
4584
4585         return status;
4586 }
4587
4588 /**
4589  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4590  * @hw: pointer to the hw struct
4591  * @start_agent: True if DCBx Agent needs to be Started
4592  *                              False if DCBx Agent needs to be Stopped
4593  * @cmd_details: pointer to command details structure or NULL
4594  *
4595  * Start/Stop the embedded dcbx Agent
4596  **/
4597 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4598                                 bool start_agent,
4599                                 struct i40e_asq_cmd_details *cmd_details)
4600 {
4601         struct i40e_aq_desc desc;
4602         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4603                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4604                                 &desc.params.raw;
4605         enum i40e_status_code status;
4606
4607         i40e_fill_default_direct_cmd_desc(&desc,
4608                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4609
4610         if (start_agent)
4611                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4612
4613         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4614
4615         return status;
4616 }
4617
4618 /**
4619  * i40e_aq_add_udp_tunnel
4620  * @hw: pointer to the hw struct
4621  * @udp_port: the UDP port to add in Host byte order
4622  * @protocol_index: protocol index type
4623  * @filter_index: pointer to filter index
4624  * @cmd_details: pointer to command details structure or NULL
4625  *
4626  * Note: Firmware expects the udp_port value to be in Little Endian format,
4627  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4628  * Little Endian order.
4629  **/
4630 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4631                                 u16 udp_port, u8 protocol_index,
4632                                 u8 *filter_index,
4633                                 struct i40e_asq_cmd_details *cmd_details)
4634 {
4635         struct i40e_aq_desc desc;
4636         struct i40e_aqc_add_udp_tunnel *cmd =
4637                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4638         struct i40e_aqc_del_udp_tunnel_completion *resp =
4639                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4640         enum i40e_status_code status;
4641
4642         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4643
4644         cmd->udp_port = CPU_TO_LE16(udp_port);
4645         cmd->protocol_type = protocol_index;
4646
4647         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4648
4649         if (!status && filter_index)
4650                 *filter_index = resp->index;
4651
4652         return status;
4653 }
4654
4655 /**
4656  * i40e_aq_del_udp_tunnel
4657  * @hw: pointer to the hw struct
4658  * @index: filter index
4659  * @cmd_details: pointer to command details structure or NULL
4660  **/
4661 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4662                                 struct i40e_asq_cmd_details *cmd_details)
4663 {
4664         struct i40e_aq_desc desc;
4665         struct i40e_aqc_remove_udp_tunnel *cmd =
4666                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4667         enum i40e_status_code status;
4668
4669         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4670
4671         cmd->index = index;
4672
4673         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4674
4675         return status;
4676 }
4677
4678 /**
4679  * i40e_aq_get_switch_resource_alloc (0x0204)
4680  * @hw: pointer to the hw struct
4681  * @num_entries: pointer to u8 to store the number of resource entries returned
4682  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4683  *        to store the resource information for all resource types.  Each
4684  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4685  * @count: size, in bytes, of the buffer provided
4686  * @cmd_details: pointer to command details structure or NULL
4687  *
4688  * Query the resources allocated to a function.
4689  **/
4690 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4691                         u8 *num_entries,
4692                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4693                         u16 count,
4694                         struct i40e_asq_cmd_details *cmd_details)
4695 {
4696         struct i40e_aq_desc desc;
4697         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4698                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4699         enum i40e_status_code status;
4700         u16 length = count * sizeof(*buf);
4701
4702         i40e_fill_default_direct_cmd_desc(&desc,
4703                                         i40e_aqc_opc_get_switch_resource_alloc);
4704
4705         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4706         if (length > I40E_AQ_LARGE_BUF)
4707                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4708
4709         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4710
4711         if (!status && num_entries)
4712                 *num_entries = cmd_resp->num_entries;
4713
4714         return status;
4715 }
4716
4717 /**
4718  * i40e_aq_delete_element - Delete switch element
4719  * @hw: pointer to the hw struct
4720  * @seid: the SEID to delete from the switch
4721  * @cmd_details: pointer to command details structure or NULL
4722  *
4723  * This deletes a switch element from the switch.
4724  **/
4725 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4726                                 struct i40e_asq_cmd_details *cmd_details)
4727 {
4728         struct i40e_aq_desc desc;
4729         struct i40e_aqc_switch_seid *cmd =
4730                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4731         enum i40e_status_code status;
4732
4733         if (seid == 0)
4734                 return I40E_ERR_PARAM;
4735
4736         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4737
4738         cmd->seid = CPU_TO_LE16(seid);
4739
4740         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4741
4742         return status;
4743 }
4744
4745 /**
4746  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4747  * @hw: pointer to the hw struct
4748  * @flags: component flags
4749  * @mac_seid: uplink seid (MAC SEID)
4750  * @vsi_seid: connected vsi seid
4751  * @ret_seid: seid of create pv component
4752  *
4753  * This instantiates an i40e port virtualizer with specified flags.
4754  * Depending on specified flags the port virtualizer can act as a
4755  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4756  */
4757 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4758                                        u16 mac_seid, u16 vsi_seid,
4759                                        u16 *ret_seid)
4760 {
4761         struct i40e_aq_desc desc;
4762         struct i40e_aqc_add_update_pv *cmd =
4763                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4764         struct i40e_aqc_add_update_pv_completion *resp =
4765                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4766         enum i40e_status_code status;
4767
4768         if (vsi_seid == 0)
4769                 return I40E_ERR_PARAM;
4770
4771         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4772         cmd->command_flags = CPU_TO_LE16(flags);
4773         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4774         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4775
4776         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4777         if (!status && ret_seid)
4778                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4779
4780         return status;
4781 }
4782
4783 /**
4784  * i40e_aq_add_tag - Add an S/E-tag
4785  * @hw: pointer to the hw struct
4786  * @direct_to_queue: should s-tag direct flow to a specific queue
4787  * @vsi_seid: VSI SEID to use this tag
4788  * @tag: value of the tag
4789  * @queue_num: queue number, only valid is direct_to_queue is true
4790  * @tags_used: return value, number of tags in use by this PF
4791  * @tags_free: return value, number of unallocated tags
4792  * @cmd_details: pointer to command details structure or NULL
4793  *
4794  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4795  * the number of tags allocated by the PF, and the number of unallocated
4796  * tags available.
4797  **/
4798 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4799                                 u16 vsi_seid, u16 tag, u16 queue_num,
4800                                 u16 *tags_used, u16 *tags_free,
4801                                 struct i40e_asq_cmd_details *cmd_details)
4802 {
4803         struct i40e_aq_desc desc;
4804         struct i40e_aqc_add_tag *cmd =
4805                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4806         struct i40e_aqc_add_remove_tag_completion *resp =
4807                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4808         enum i40e_status_code status;
4809
4810         if (vsi_seid == 0)
4811                 return I40E_ERR_PARAM;
4812
4813         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4814
4815         cmd->seid = CPU_TO_LE16(vsi_seid);
4816         cmd->tag = CPU_TO_LE16(tag);
4817         if (direct_to_queue) {
4818                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4819                 cmd->queue_number = CPU_TO_LE16(queue_num);
4820         }
4821
4822         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4823
4824         if (!status) {
4825                 if (tags_used != NULL)
4826                         *tags_used = LE16_TO_CPU(resp->tags_used);
4827                 if (tags_free != NULL)
4828                         *tags_free = LE16_TO_CPU(resp->tags_free);
4829         }
4830
4831         return status;
4832 }
4833
4834 /**
4835  * i40e_aq_remove_tag - Remove an S- or E-tag
4836  * @hw: pointer to the hw struct
4837  * @vsi_seid: VSI SEID this tag is associated with
4838  * @tag: value of the S-tag to delete
4839  * @tags_used: return value, number of tags in use by this PF
4840  * @tags_free: return value, number of unallocated tags
4841  * @cmd_details: pointer to command details structure or NULL
4842  *
4843  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4844  * the number of tags allocated by the PF, and the number of unallocated
4845  * tags available.
4846  **/
4847 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4848                                 u16 tag, u16 *tags_used, u16 *tags_free,
4849                                 struct i40e_asq_cmd_details *cmd_details)
4850 {
4851         struct i40e_aq_desc desc;
4852         struct i40e_aqc_remove_tag *cmd =
4853                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4854         struct i40e_aqc_add_remove_tag_completion *resp =
4855                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4856         enum i40e_status_code status;
4857
4858         if (vsi_seid == 0)
4859                 return I40E_ERR_PARAM;
4860
4861         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4862
4863         cmd->seid = CPU_TO_LE16(vsi_seid);
4864         cmd->tag = CPU_TO_LE16(tag);
4865
4866         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4867
4868         if (!status) {
4869                 if (tags_used != NULL)
4870                         *tags_used = LE16_TO_CPU(resp->tags_used);
4871                 if (tags_free != NULL)
4872                         *tags_free = LE16_TO_CPU(resp->tags_free);
4873         }
4874
4875         return status;
4876 }
4877
4878 /**
4879  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4880  * @hw: pointer to the hw struct
4881  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4882  * @etag: value of E-tag to add
4883  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4884  * @buf: address of indirect buffer
4885  * @tags_used: return value, number of E-tags in use by this port
4886  * @tags_free: return value, number of unallocated M-tags
4887  * @cmd_details: pointer to command details structure or NULL
4888  *
4889  * This associates a multicast E-tag to a port virtualizer.  It will return
4890  * the number of tags allocated by the PF, and the number of unallocated
4891  * tags available.
4892  *
4893  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4894  * num_tags_in_buf long.
4895  **/
4896 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4897                                 u16 etag, u8 num_tags_in_buf, void *buf,
4898                                 u16 *tags_used, u16 *tags_free,
4899                                 struct i40e_asq_cmd_details *cmd_details)
4900 {
4901         struct i40e_aq_desc desc;
4902         struct i40e_aqc_add_remove_mcast_etag *cmd =
4903                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4904         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4905            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4906         enum i40e_status_code status;
4907         u16 length = sizeof(u16) * num_tags_in_buf;
4908
4909         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4910                 return I40E_ERR_PARAM;
4911
4912         i40e_fill_default_direct_cmd_desc(&desc,
4913                                           i40e_aqc_opc_add_multicast_etag);
4914
4915         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4916         cmd->etag = CPU_TO_LE16(etag);
4917         cmd->num_unicast_etags = num_tags_in_buf;
4918
4919         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4920         if (length > I40E_AQ_LARGE_BUF)
4921                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4922
4923         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4924
4925         if (!status) {
4926                 if (tags_used != NULL)
4927                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4928                 if (tags_free != NULL)
4929                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4930         }
4931
4932         return status;
4933 }
4934
4935 /**
4936  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4937  * @hw: pointer to the hw struct
4938  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4939  * @etag: value of the E-tag to remove
4940  * @tags_used: return value, number of tags in use by this port
4941  * @tags_free: return value, number of unallocated tags
4942  * @cmd_details: pointer to command details structure or NULL
4943  *
4944  * This deletes an E-tag from the port virtualizer.  It will return
4945  * the number of tags allocated by the port, and the number of unallocated
4946  * tags available.
4947  **/
4948 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4949                                 u16 etag, u16 *tags_used, u16 *tags_free,
4950                                 struct i40e_asq_cmd_details *cmd_details)
4951 {
4952         struct i40e_aq_desc desc;
4953         struct i40e_aqc_add_remove_mcast_etag *cmd =
4954                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4955         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4956            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4957         enum i40e_status_code status;
4958
4959
4960         if (pv_seid == 0)
4961                 return I40E_ERR_PARAM;
4962
4963         i40e_fill_default_direct_cmd_desc(&desc,
4964                                           i40e_aqc_opc_remove_multicast_etag);
4965
4966         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4967         cmd->etag = CPU_TO_LE16(etag);
4968
4969         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4970
4971         if (!status) {
4972                 if (tags_used != NULL)
4973                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4974                 if (tags_free != NULL)
4975                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4976         }
4977
4978         return status;
4979 }
4980
4981 /**
4982  * i40e_aq_update_tag - Update an S/E-tag
4983  * @hw: pointer to the hw struct
4984  * @vsi_seid: VSI SEID using this S-tag
4985  * @old_tag: old tag value
4986  * @new_tag: new tag value
4987  * @tags_used: return value, number of tags in use by this PF
4988  * @tags_free: return value, number of unallocated tags
4989  * @cmd_details: pointer to command details structure or NULL
4990  *
4991  * This updates the value of the tag currently attached to this VSI
4992  * in the switch complex.  It will return the number of tags allocated
4993  * by the PF, and the number of unallocated tags available.
4994  **/
4995 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4996                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4997                                 u16 *tags_free,
4998                                 struct i40e_asq_cmd_details *cmd_details)
4999 {
5000         struct i40e_aq_desc desc;
5001         struct i40e_aqc_update_tag *cmd =
5002                 (struct i40e_aqc_update_tag *)&desc.params.raw;
5003         struct i40e_aqc_update_tag_completion *resp =
5004                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
5005         enum i40e_status_code status;
5006
5007         if (vsi_seid == 0)
5008                 return I40E_ERR_PARAM;
5009
5010         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
5011
5012         cmd->seid = CPU_TO_LE16(vsi_seid);
5013         cmd->old_tag = CPU_TO_LE16(old_tag);
5014         cmd->new_tag = CPU_TO_LE16(new_tag);
5015
5016         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5017
5018         if (!status) {
5019                 if (tags_used != NULL)
5020                         *tags_used = LE16_TO_CPU(resp->tags_used);
5021                 if (tags_free != NULL)
5022                         *tags_free = LE16_TO_CPU(resp->tags_free);
5023         }
5024
5025         return status;
5026 }
5027
5028 /**
5029  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5030  * @hw: pointer to the hw struct
5031  * @tcmap: TC map for request/release any ignore PFC condition
5032  * @request: request or release ignore PFC condition
5033  * @tcmap_ret: return TCs for which PFC is currently ignored
5034  * @cmd_details: pointer to command details structure or NULL
5035  *
5036  * This sends out request/release to ignore PFC condition for a TC.
5037  * It will return the TCs for which PFC is currently ignored.
5038  **/
5039 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5040                                 bool request, u8 *tcmap_ret,
5041                                 struct i40e_asq_cmd_details *cmd_details)
5042 {
5043         struct i40e_aq_desc desc;
5044         struct i40e_aqc_pfc_ignore *cmd_resp =
5045                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5046         enum i40e_status_code status;
5047
5048         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5049
5050         if (request)
5051                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5052
5053         cmd_resp->tc_bitmap = tcmap;
5054
5055         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5056
5057         if (!status) {
5058                 if (tcmap_ret != NULL)
5059                         *tcmap_ret = cmd_resp->tc_bitmap;
5060         }
5061
5062         return status;
5063 }
5064
5065 /**
5066  * i40e_aq_dcb_updated - DCB Updated Command
5067  * @hw: pointer to the hw struct
5068  * @cmd_details: pointer to command details structure or NULL
5069  *
5070  * When LLDP is handled in PF this command is used by the PF
5071  * to notify EMP that a DCB setting is modified.
5072  * When LLDP is handled in EMP this command is used by the PF
5073  * to notify EMP whenever one of the following parameters get
5074  * modified:
5075  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5076  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5077  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5078  * EMP will return when the shared RPB settings have been
5079  * recomputed and modified. The retval field in the descriptor
5080  * will be set to 0 when RPB is modified.
5081  **/
5082 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5083                                 struct i40e_asq_cmd_details *cmd_details)
5084 {
5085         struct i40e_aq_desc desc;
5086         enum i40e_status_code status;
5087
5088         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5089
5090         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5091
5092         return status;
5093 }
5094
5095 /**
5096  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5097  * @hw: pointer to the hw struct
5098  * @seid: defines the SEID of the switch for which the stats are requested
5099  * @vlan_id: the VLAN ID for which the statistics are requested
5100  * @stat_index: index of the statistics counters block assigned to this VLAN
5101  * @cmd_details: pointer to command details structure or NULL
5102  *
5103  * XL710 supports 128 smonVlanStats counters.This command is used to
5104  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5105  * switch.
5106  **/
5107 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5108                                 u16 vlan_id, u16 *stat_index,
5109                                 struct i40e_asq_cmd_details *cmd_details)
5110 {
5111         struct i40e_aq_desc desc;
5112         struct i40e_aqc_add_remove_statistics *cmd_resp =
5113                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5114         enum i40e_status_code status;
5115
5116         if ((seid == 0) || (stat_index == NULL))
5117                 return I40E_ERR_PARAM;
5118
5119         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5120
5121         cmd_resp->seid = CPU_TO_LE16(seid);
5122         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5123
5124         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5125
5126         if (!status && stat_index)
5127                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5128
5129         return status;
5130 }
5131
5132 /**
5133  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5134  * @hw: pointer to the hw struct
5135  * @seid: defines the SEID of the switch for which the stats are requested
5136  * @vlan_id: the VLAN ID for which the statistics are requested
5137  * @stat_index: index of the statistics counters block assigned to this VLAN
5138  * @cmd_details: pointer to command details structure or NULL
5139  *
5140  * XL710 supports 128 smonVlanStats counters.This command is used to
5141  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5142  * switch.
5143  **/
5144 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5145                                 u16 vlan_id, u16 stat_index,
5146                                 struct i40e_asq_cmd_details *cmd_details)
5147 {
5148         struct i40e_aq_desc desc;
5149         struct i40e_aqc_add_remove_statistics *cmd =
5150                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5151         enum i40e_status_code status;
5152
5153         if (seid == 0)
5154                 return I40E_ERR_PARAM;
5155
5156         i40e_fill_default_direct_cmd_desc(&desc,
5157                                           i40e_aqc_opc_remove_statistics);
5158
5159         cmd->seid = CPU_TO_LE16(seid);
5160         cmd->vlan  = CPU_TO_LE16(vlan_id);
5161         cmd->stat_index = CPU_TO_LE16(stat_index);
5162
5163         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5164
5165         return status;
5166 }
5167
5168 /**
5169  * i40e_aq_set_port_parameters - set physical port parameters.
5170  * @hw: pointer to the hw struct
5171  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5172  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5173  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5174  * @double_vlan: if set double VLAN is enabled
5175  * @cmd_details: pointer to command details structure or NULL
5176  **/
5177 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5178                                 u16 bad_frame_vsi, bool save_bad_pac,
5179                                 bool pad_short_pac, bool double_vlan,
5180                                 struct i40e_asq_cmd_details *cmd_details)
5181 {
5182         struct i40e_aqc_set_port_parameters *cmd;
5183         enum i40e_status_code status;
5184         struct i40e_aq_desc desc;
5185         u16 command_flags = 0;
5186
5187         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5188
5189         i40e_fill_default_direct_cmd_desc(&desc,
5190                                           i40e_aqc_opc_set_port_parameters);
5191
5192         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5193         if (save_bad_pac)
5194                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5195         if (pad_short_pac)
5196                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5197         if (double_vlan)
5198                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5199         cmd->command_flags = CPU_TO_LE16(command_flags);
5200
5201         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5202
5203         return status;
5204 }
5205
5206 /**
5207  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5208  * @hw: pointer to the hw struct
5209  * @seid: seid for the physical port/switching component/vsi
5210  * @buff: Indirect buffer to hold data parameters and response
5211  * @buff_size: Indirect buffer size
5212  * @opcode: Tx scheduler AQ command opcode
5213  * @cmd_details: pointer to command details structure or NULL
5214  *
5215  * Generic command handler for Tx scheduler AQ commands
5216  **/
5217 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5218                                 void *buff, u16 buff_size,
5219                                  enum i40e_admin_queue_opc opcode,
5220                                 struct i40e_asq_cmd_details *cmd_details)
5221 {
5222         struct i40e_aq_desc desc;
5223         struct i40e_aqc_tx_sched_ind *cmd =
5224                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5225         enum i40e_status_code status;
5226         bool cmd_param_flag = false;
5227
5228         switch (opcode) {
5229         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5230         case i40e_aqc_opc_configure_vsi_tc_bw:
5231         case i40e_aqc_opc_enable_switching_comp_ets:
5232         case i40e_aqc_opc_modify_switching_comp_ets:
5233         case i40e_aqc_opc_disable_switching_comp_ets:
5234         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5235         case i40e_aqc_opc_configure_switching_comp_bw_config:
5236                 cmd_param_flag = true;
5237                 break;
5238         case i40e_aqc_opc_query_vsi_bw_config:
5239         case i40e_aqc_opc_query_vsi_ets_sla_config:
5240         case i40e_aqc_opc_query_switching_comp_ets_config:
5241         case i40e_aqc_opc_query_port_ets_config:
5242         case i40e_aqc_opc_query_switching_comp_bw_config:
5243                 cmd_param_flag = false;
5244                 break;
5245         default:
5246                 return I40E_ERR_PARAM;
5247         }
5248
5249         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5250
5251         /* Indirect command */
5252         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5253         if (cmd_param_flag)
5254                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5255         if (buff_size > I40E_AQ_LARGE_BUF)
5256                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5257
5258         desc.datalen = CPU_TO_LE16(buff_size);
5259
5260         cmd->vsi_seid = CPU_TO_LE16(seid);
5261
5262         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5263
5264         return status;
5265 }
5266
5267 /**
5268  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5269  * @hw: pointer to the hw struct
5270  * @seid: VSI seid
5271  * @credit: BW limit credits (0 = disabled)
5272  * @max_credit: Max BW limit credits
5273  * @cmd_details: pointer to command details structure or NULL
5274  **/
5275 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5276                                 u16 seid, u16 credit, u8 max_credit,
5277                                 struct i40e_asq_cmd_details *cmd_details)
5278 {
5279         struct i40e_aq_desc desc;
5280         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5281                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5282         enum i40e_status_code status;
5283
5284         i40e_fill_default_direct_cmd_desc(&desc,
5285                                           i40e_aqc_opc_configure_vsi_bw_limit);
5286
5287         cmd->vsi_seid = CPU_TO_LE16(seid);
5288         cmd->credit = CPU_TO_LE16(credit);
5289         cmd->max_credit = max_credit;
5290
5291         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5292
5293         return status;
5294 }
5295
5296 /**
5297  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5298  * @hw: pointer to the hw struct
5299  * @seid: switching component seid
5300  * @credit: BW limit credits (0 = disabled)
5301  * @max_bw: Max BW limit credits
5302  * @cmd_details: pointer to command details structure or NULL
5303  **/
5304 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5305                                 u16 seid, u16 credit, u8 max_bw,
5306                                 struct i40e_asq_cmd_details *cmd_details)
5307 {
5308         struct i40e_aq_desc desc;
5309         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5310           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5311         enum i40e_status_code status;
5312
5313         i40e_fill_default_direct_cmd_desc(&desc,
5314                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5315
5316         cmd->seid = CPU_TO_LE16(seid);
5317         cmd->credit = CPU_TO_LE16(credit);
5318         cmd->max_bw = max_bw;
5319
5320         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5321
5322         return status;
5323 }
5324
5325 /**
5326  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5327  * @hw: pointer to the hw struct
5328  * @seid: VSI seid
5329  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5330  * @cmd_details: pointer to command details structure or NULL
5331  **/
5332 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5333                         u16 seid,
5334                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5335                         struct i40e_asq_cmd_details *cmd_details)
5336 {
5337         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5338                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5339                                     cmd_details);
5340 }
5341
5342 /**
5343  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5344  * @hw: pointer to the hw struct
5345  * @seid: VSI seid
5346  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5347  * @cmd_details: pointer to command details structure or NULL
5348  **/
5349 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5350                         u16 seid,
5351                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5352                         struct i40e_asq_cmd_details *cmd_details)
5353 {
5354         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5355                                     i40e_aqc_opc_configure_vsi_tc_bw,
5356                                     cmd_details);
5357 }
5358
5359 /**
5360  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5361  * @hw: pointer to the hw struct
5362  * @seid: seid of the switching component connected to Physical Port
5363  * @ets_data: Buffer holding ETS parameters
5364  * @opcode: Tx scheduler AQ command opcode
5365  * @cmd_details: pointer to command details structure or NULL
5366  **/
5367 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5368                 u16 seid,
5369                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5370                 enum i40e_admin_queue_opc opcode,
5371                 struct i40e_asq_cmd_details *cmd_details)
5372 {
5373         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5374                                     sizeof(*ets_data), opcode, cmd_details);
5375 }
5376
5377 /**
5378  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5379  * @hw: pointer to the hw struct
5380  * @seid: seid of the switching component
5381  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5382  * @cmd_details: pointer to command details structure or NULL
5383  **/
5384 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5385         u16 seid,
5386         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5387         struct i40e_asq_cmd_details *cmd_details)
5388 {
5389         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5390                             i40e_aqc_opc_configure_switching_comp_bw_config,
5391                             cmd_details);
5392 }
5393
5394 /**
5395  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5396  * @hw: pointer to the hw struct
5397  * @seid: seid of the switching component
5398  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5399  * @cmd_details: pointer to command details structure or NULL
5400  **/
5401 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5402         struct i40e_hw *hw, u16 seid,
5403         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5404         struct i40e_asq_cmd_details *cmd_details)
5405 {
5406         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5407                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5408                             cmd_details);
5409 }
5410
5411 /**
5412  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5413  * @hw: pointer to the hw struct
5414  * @seid: seid of the VSI
5415  * @bw_data: Buffer to hold VSI BW configuration
5416  * @cmd_details: pointer to command details structure or NULL
5417  **/
5418 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5419                         u16 seid,
5420                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5421                         struct i40e_asq_cmd_details *cmd_details)
5422 {
5423         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5424                                     i40e_aqc_opc_query_vsi_bw_config,
5425                                     cmd_details);
5426 }
5427
5428 /**
5429  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5430  * @hw: pointer to the hw struct
5431  * @seid: seid of the VSI
5432  * @bw_data: Buffer to hold VSI BW configuration per TC
5433  * @cmd_details: pointer to command details structure or NULL
5434  **/
5435 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5436                         u16 seid,
5437                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5438                         struct i40e_asq_cmd_details *cmd_details)
5439 {
5440         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5441                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5442                                     cmd_details);
5443 }
5444
5445 /**
5446  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5447  * @hw: pointer to the hw struct
5448  * @seid: seid of the switching component
5449  * @bw_data: Buffer to hold switching component's per TC BW config
5450  * @cmd_details: pointer to command details structure or NULL
5451  **/
5452 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5453                 u16 seid,
5454                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5455                 struct i40e_asq_cmd_details *cmd_details)
5456 {
5457         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5458                                    i40e_aqc_opc_query_switching_comp_ets_config,
5459                                    cmd_details);
5460 }
5461
5462 /**
5463  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5464  * @hw: pointer to the hw struct
5465  * @seid: seid of the VSI or switching component connected to Physical Port
5466  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5467  * @cmd_details: pointer to command details structure or NULL
5468  **/
5469 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5470                         u16 seid,
5471                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5472                         struct i40e_asq_cmd_details *cmd_details)
5473 {
5474         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5475                                     i40e_aqc_opc_query_port_ets_config,
5476                                     cmd_details);
5477 }
5478
5479 /**
5480  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5481  * @hw: pointer to the hw struct
5482  * @seid: seid of the switching component
5483  * @bw_data: Buffer to hold switching component's BW configuration
5484  * @cmd_details: pointer to command details structure or NULL
5485  **/
5486 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5487                 u16 seid,
5488                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5489                 struct i40e_asq_cmd_details *cmd_details)
5490 {
5491         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5492                                     i40e_aqc_opc_query_switching_comp_bw_config,
5493                                     cmd_details);
5494 }
5495
5496 /**
5497  * i40e_validate_filter_settings
5498  * @hw: pointer to the hardware structure
5499  * @settings: Filter control settings
5500  *
5501  * Check and validate the filter control settings passed.
5502  * The function checks for the valid filter/context sizes being
5503  * passed for FCoE and PE.
5504  *
5505  * Returns I40E_SUCCESS if the values passed are valid and within
5506  * range else returns an error.
5507  **/
5508 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5509                                 struct i40e_filter_control_settings *settings)
5510 {
5511         u32 fcoe_cntx_size, fcoe_filt_size;
5512         u32 pe_cntx_size, pe_filt_size;
5513         u32 fcoe_fmax;
5514
5515         u32 val;
5516
5517         /* Validate FCoE settings passed */
5518         switch (settings->fcoe_filt_num) {
5519         case I40E_HASH_FILTER_SIZE_1K:
5520         case I40E_HASH_FILTER_SIZE_2K:
5521         case I40E_HASH_FILTER_SIZE_4K:
5522         case I40E_HASH_FILTER_SIZE_8K:
5523         case I40E_HASH_FILTER_SIZE_16K:
5524         case I40E_HASH_FILTER_SIZE_32K:
5525                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5526                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5527                 break;
5528         default:
5529                 return I40E_ERR_PARAM;
5530         }
5531
5532         switch (settings->fcoe_cntx_num) {
5533         case I40E_DMA_CNTX_SIZE_512:
5534         case I40E_DMA_CNTX_SIZE_1K:
5535         case I40E_DMA_CNTX_SIZE_2K:
5536         case I40E_DMA_CNTX_SIZE_4K:
5537                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5538                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5539                 break;
5540         default:
5541                 return I40E_ERR_PARAM;
5542         }
5543
5544         /* Validate PE settings passed */
5545         switch (settings->pe_filt_num) {
5546         case I40E_HASH_FILTER_SIZE_1K:
5547         case I40E_HASH_FILTER_SIZE_2K:
5548         case I40E_HASH_FILTER_SIZE_4K:
5549         case I40E_HASH_FILTER_SIZE_8K:
5550         case I40E_HASH_FILTER_SIZE_16K:
5551         case I40E_HASH_FILTER_SIZE_32K:
5552         case I40E_HASH_FILTER_SIZE_64K:
5553         case I40E_HASH_FILTER_SIZE_128K:
5554         case I40E_HASH_FILTER_SIZE_256K:
5555         case I40E_HASH_FILTER_SIZE_512K:
5556         case I40E_HASH_FILTER_SIZE_1M:
5557                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5558                 pe_filt_size <<= (u32)settings->pe_filt_num;
5559                 break;
5560         default:
5561                 return I40E_ERR_PARAM;
5562         }
5563
5564         switch (settings->pe_cntx_num) {
5565         case I40E_DMA_CNTX_SIZE_512:
5566         case I40E_DMA_CNTX_SIZE_1K:
5567         case I40E_DMA_CNTX_SIZE_2K:
5568         case I40E_DMA_CNTX_SIZE_4K:
5569         case I40E_DMA_CNTX_SIZE_8K:
5570         case I40E_DMA_CNTX_SIZE_16K:
5571         case I40E_DMA_CNTX_SIZE_32K:
5572         case I40E_DMA_CNTX_SIZE_64K:
5573         case I40E_DMA_CNTX_SIZE_128K:
5574         case I40E_DMA_CNTX_SIZE_256K:
5575                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5576                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5577                 break;
5578         default:
5579                 return I40E_ERR_PARAM;
5580         }
5581
5582         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5583         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5584         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5585                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5586         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5587                 return I40E_ERR_INVALID_SIZE;
5588
5589         return I40E_SUCCESS;
5590 }
5591
5592 /**
5593  * i40e_set_filter_control
5594  * @hw: pointer to the hardware structure
5595  * @settings: Filter control settings
5596  *
5597  * Set the Queue Filters for PE/FCoE and enable filters required
5598  * for a single PF. It is expected that these settings are programmed
5599  * at the driver initialization time.
5600  **/
5601 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5602                                 struct i40e_filter_control_settings *settings)
5603 {
5604         enum i40e_status_code ret = I40E_SUCCESS;
5605         u32 hash_lut_size = 0;
5606         u32 val;
5607
5608         if (!settings)
5609                 return I40E_ERR_PARAM;
5610
5611         /* Validate the input settings */
5612         ret = i40e_validate_filter_settings(hw, settings);
5613         if (ret)
5614                 return ret;
5615
5616         /* Read the PF Queue Filter control register */
5617         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5618
5619         /* Program required PE hash buckets for the PF */
5620         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5621         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5622                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5623         /* Program required PE contexts for the PF */
5624         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5625         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5626                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5627
5628         /* Program required FCoE hash buckets for the PF */
5629         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5630         val |= ((u32)settings->fcoe_filt_num <<
5631                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5632                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5633         /* Program required FCoE DDP contexts for the PF */
5634         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5635         val |= ((u32)settings->fcoe_cntx_num <<
5636                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5637                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5638
5639         /* Program Hash LUT size for the PF */
5640         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5641         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5642                 hash_lut_size = 1;
5643         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5644                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5645
5646         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5647         if (settings->enable_fdir)
5648                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5649         if (settings->enable_ethtype)
5650                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5651         if (settings->enable_macvlan)
5652                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5653
5654         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5655
5656         return I40E_SUCCESS;
5657 }
5658
5659 /**
5660  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5661  * @hw: pointer to the hw struct
5662  * @mac_addr: MAC address to use in the filter
5663  * @ethtype: Ethertype to use in the filter
5664  * @flags: Flags that needs to be applied to the filter
5665  * @vsi_seid: seid of the control VSI
5666  * @queue: VSI queue number to send the packet to
5667  * @is_add: Add control packet filter if True else remove
5668  * @stats: Structure to hold information on control filter counts
5669  * @cmd_details: pointer to command details structure or NULL
5670  *
5671  * This command will Add or Remove control packet filter for a control VSI.
5672  * In return it will update the total number of perfect filter count in
5673  * the stats member.
5674  **/
5675 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5676                                 u8 *mac_addr, u16 ethtype, u16 flags,
5677                                 u16 vsi_seid, u16 queue, bool is_add,
5678                                 struct i40e_control_filter_stats *stats,
5679                                 struct i40e_asq_cmd_details *cmd_details)
5680 {
5681         struct i40e_aq_desc desc;
5682         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5683                 (struct i40e_aqc_add_remove_control_packet_filter *)
5684                 &desc.params.raw;
5685         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5686                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5687                 &desc.params.raw;
5688         enum i40e_status_code status;
5689
5690         if (vsi_seid == 0)
5691                 return I40E_ERR_PARAM;
5692
5693         if (is_add) {
5694                 i40e_fill_default_direct_cmd_desc(&desc,
5695                                 i40e_aqc_opc_add_control_packet_filter);
5696                 cmd->queue = CPU_TO_LE16(queue);
5697         } else {
5698                 i40e_fill_default_direct_cmd_desc(&desc,
5699                                 i40e_aqc_opc_remove_control_packet_filter);
5700         }
5701
5702         if (mac_addr)
5703                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5704                             I40E_NONDMA_TO_NONDMA);
5705
5706         cmd->etype = CPU_TO_LE16(ethtype);
5707         cmd->flags = CPU_TO_LE16(flags);
5708         cmd->seid = CPU_TO_LE16(vsi_seid);
5709
5710         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5711
5712         if (!status && stats) {
5713                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5714                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5715                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5716                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5717         }
5718
5719         return status;
5720 }
5721
5722 /**
5723  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5724  * @hw: pointer to the hw struct
5725  * @seid: VSI seid to add ethertype filter from
5726  **/
5727 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5728                                                     u16 seid)
5729 {
5730 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5731         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5732                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5733                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5734         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5735         enum i40e_status_code status;
5736
5737         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5738                                                        seid, 0, true, NULL,
5739                                                        NULL);
5740         if (status)
5741                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5742 }
5743
5744 /**
5745  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5746  * @filters: list of cloud filters
5747  * @filter_count: length of list
5748  *
5749  * There's an issue in the device where the Geneve VNI layout needs
5750  * to be shifted 1 byte over from the VxLAN VNI
5751  **/
5752 STATIC void i40e_fix_up_geneve_vni(
5753         struct i40e_aqc_cloud_filters_element_data *filters,
5754         u8 filter_count)
5755 {
5756         struct i40e_aqc_cloud_filters_element_data *f = filters;
5757         int i;
5758
5759         for (i = 0; i < filter_count; i++) {
5760                 u16 tnl_type;
5761                 u32 ti;
5762
5763                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5764                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5765                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5766                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5767                         ti = LE32_TO_CPU(f[i].tenant_id);
5768                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5769                 }
5770         }
5771 }
5772
5773 /**
5774  * i40e_aq_add_cloud_filters
5775  * @hw: pointer to the hardware structure
5776  * @seid: VSI seid to add cloud filters from
5777  * @filters: Buffer which contains the filters to be added
5778  * @filter_count: number of filters contained in the buffer
5779  *
5780  * Set the cloud filters for a given VSI.  The contents of the
5781  * i40e_aqc_cloud_filters_element_data are filled
5782  * in by the caller of the function.
5783  *
5784  **/
5785 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5786         u16 seid,
5787         struct i40e_aqc_cloud_filters_element_data *filters,
5788         u8 filter_count)
5789 {
5790         struct i40e_aq_desc desc;
5791         struct i40e_aqc_add_remove_cloud_filters *cmd =
5792         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5793         enum i40e_status_code status;
5794         u16 buff_len;
5795
5796         i40e_fill_default_direct_cmd_desc(&desc,
5797                                           i40e_aqc_opc_add_cloud_filters);
5798
5799         buff_len = filter_count * sizeof(*filters);
5800         desc.datalen = CPU_TO_LE16(buff_len);
5801         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5802         cmd->num_filters = filter_count;
5803         cmd->seid = CPU_TO_LE16(seid);
5804
5805         i40e_fix_up_geneve_vni(filters, filter_count);
5806
5807         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5808
5809         return status;
5810 }
5811
5812 /**
5813  * i40e_aq_add_cloud_filters_bb
5814  * @hw: pointer to the hardware structure
5815  * @seid: VSI seid to add cloud filters from
5816  * @filters: Buffer which contains the filters in big buffer to be added
5817  * @filter_count: number of filters contained in the buffer
5818  *
5819  * Set the cloud filters for a given VSI.  The contents of the
5820  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5821  * the function.
5822  *
5823  **/
5824 enum i40e_status_code
5825 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5826                              struct i40e_aqc_cloud_filters_element_bb *filters,
5827                              u8 filter_count)
5828 {
5829         struct i40e_aq_desc desc;
5830         struct i40e_aqc_add_remove_cloud_filters *cmd =
5831         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5832         enum i40e_status_code status;
5833         u16 buff_len;
5834         int i;
5835
5836         i40e_fill_default_direct_cmd_desc(&desc,
5837                                           i40e_aqc_opc_add_cloud_filters);
5838
5839         buff_len = filter_count * sizeof(*filters);
5840         desc.datalen = CPU_TO_LE16(buff_len);
5841         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5842         cmd->num_filters = filter_count;
5843         cmd->seid = CPU_TO_LE16(seid);
5844         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5845
5846         for (i = 0; i < filter_count; i++) {
5847                 u16 tnl_type;
5848                 u32 ti;
5849
5850                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5851                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5852                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5853
5854                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5855                  * one more byte further than normally used for Tenant ID in
5856                  * other tunnel types.
5857                  */
5858                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5859                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5860                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5861                 }
5862         }
5863
5864         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5865
5866         return status;
5867 }
5868
5869 /**
5870  * i40e_aq_rem_cloud_filters
5871  * @hw: pointer to the hardware structure
5872  * @seid: VSI seid to remove cloud filters from
5873  * @filters: Buffer which contains the filters to be removed
5874  * @filter_count: number of filters contained in the buffer
5875  *
5876  * Remove the cloud filters for a given VSI.  The contents of the
5877  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5878  * of the function.
5879  *
5880  **/
5881 enum i40e_status_code
5882 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5883                           struct i40e_aqc_cloud_filters_element_data *filters,
5884                           u8 filter_count)
5885 {
5886         struct i40e_aq_desc desc;
5887         struct i40e_aqc_add_remove_cloud_filters *cmd =
5888         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5889         enum i40e_status_code status;
5890         u16 buff_len;
5891
5892         i40e_fill_default_direct_cmd_desc(&desc,
5893                                           i40e_aqc_opc_remove_cloud_filters);
5894
5895         buff_len = filter_count * sizeof(*filters);
5896         desc.datalen = CPU_TO_LE16(buff_len);
5897         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5898         cmd->num_filters = filter_count;
5899         cmd->seid = CPU_TO_LE16(seid);
5900
5901         i40e_fix_up_geneve_vni(filters, filter_count);
5902
5903         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5904
5905         return status;
5906 }
5907
5908 /**
5909  * i40e_aq_rem_cloud_filters_bb
5910  * @hw: pointer to the hardware structure
5911  * @seid: VSI seid to remove cloud filters from
5912  * @filters: Buffer which contains the filters in big buffer to be removed
5913  * @filter_count: number of filters contained in the buffer
5914  *
5915  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5916  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5917  * function.
5918  *
5919  **/
5920 enum i40e_status_code
5921 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5922                              struct i40e_aqc_cloud_filters_element_bb *filters,
5923                              u8 filter_count)
5924 {
5925         struct i40e_aq_desc desc;
5926         struct i40e_aqc_add_remove_cloud_filters *cmd =
5927         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5928         enum i40e_status_code status;
5929         u16 buff_len;
5930         int i;
5931
5932         i40e_fill_default_direct_cmd_desc(&desc,
5933                                           i40e_aqc_opc_remove_cloud_filters);
5934
5935         buff_len = filter_count * sizeof(*filters);
5936         desc.datalen = CPU_TO_LE16(buff_len);
5937         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5938         cmd->num_filters = filter_count;
5939         cmd->seid = CPU_TO_LE16(seid);
5940         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5941
5942         for (i = 0; i < filter_count; i++) {
5943                 u16 tnl_type;
5944                 u32 ti;
5945
5946                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5947                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5948                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5949
5950                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5951                  * one more byte further than normally used for Tenant ID in
5952                  * other tunnel types.
5953                  */
5954                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5955                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5956                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5957                 }
5958         }
5959
5960         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5961
5962         return status;
5963 }
5964
5965 /**
5966  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5967  * @hw: pointer to the hw struct
5968  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5969  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5970  *
5971  **/
5972 enum
5973 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5974         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5975         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5976 {
5977         struct i40e_aq_desc desc;
5978         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5979                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5980         enum i40e_status_code status = I40E_SUCCESS;
5981         int i = 0;
5982
5983         i40e_fill_default_direct_cmd_desc(&desc,
5984                                           i40e_aqc_opc_replace_cloud_filters);
5985
5986         desc.datalen = CPU_TO_LE16(32);
5987         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5988         cmd->old_filter_type = filters->old_filter_type;
5989         cmd->new_filter_type = filters->new_filter_type;
5990         cmd->valid_flags = filters->valid_flags;
5991         cmd->tr_bit = filters->tr_bit;
5992
5993         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5994                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5995
5996         /* for get cloud filters command */
5997         for (i = 0; i < 32; i += 4) {
5998                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5999                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
6000                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
6001                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
6002         }
6003
6004         return status;
6005 }
6006
6007
6008 /**
6009  * i40e_aq_alternate_write
6010  * @hw: pointer to the hardware structure
6011  * @reg_addr0: address of first dword to be read
6012  * @reg_val0: value to be written under 'reg_addr0'
6013  * @reg_addr1: address of second dword to be read
6014  * @reg_val1: value to be written under 'reg_addr1'
6015  *
6016  * Write one or two dwords to alternate structure. Fields are indicated
6017  * by 'reg_addr0' and 'reg_addr1' register numbers.
6018  *
6019  **/
6020 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6021                                 u32 reg_addr0, u32 reg_val0,
6022                                 u32 reg_addr1, u32 reg_val1)
6023 {
6024         struct i40e_aq_desc desc;
6025         struct i40e_aqc_alternate_write *cmd_resp =
6026                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6027         enum i40e_status_code status;
6028
6029         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6030         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6031         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6032         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6033         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6034
6035         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6036
6037         return status;
6038 }
6039
6040 /**
6041  * i40e_aq_alternate_write_indirect
6042  * @hw: pointer to the hardware structure
6043  * @addr: address of a first register to be modified
6044  * @dw_count: number of alternate structure fields to write
6045  * @buffer: pointer to the command buffer
6046  *
6047  * Write 'dw_count' dwords from 'buffer' to alternate structure
6048  * starting at 'addr'.
6049  *
6050  **/
6051 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6052                                 u32 addr, u32 dw_count, void *buffer)
6053 {
6054         struct i40e_aq_desc desc;
6055         struct i40e_aqc_alternate_ind_write *cmd_resp =
6056                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6057         enum i40e_status_code status;
6058
6059         if (buffer == NULL)
6060                 return I40E_ERR_PARAM;
6061
6062         /* Indirect command */
6063         i40e_fill_default_direct_cmd_desc(&desc,
6064                                          i40e_aqc_opc_alternate_write_indirect);
6065
6066         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6067         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6068         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6069                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6070
6071         cmd_resp->address = CPU_TO_LE32(addr);
6072         cmd_resp->length = CPU_TO_LE32(dw_count);
6073
6074         status = i40e_asq_send_command(hw, &desc, buffer,
6075                                        I40E_LO_DWORD(4*dw_count), NULL);
6076
6077         return status;
6078 }
6079
6080 /**
6081  * i40e_aq_alternate_read
6082  * @hw: pointer to the hardware structure
6083  * @reg_addr0: address of first dword to be read
6084  * @reg_val0: pointer for data read from 'reg_addr0'
6085  * @reg_addr1: address of second dword to be read
6086  * @reg_val1: pointer for data read from 'reg_addr1'
6087  *
6088  * Read one or two dwords from alternate structure. Fields are indicated
6089  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6090  * is not passed then only register at 'reg_addr0' is read.
6091  *
6092  **/
6093 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6094                                 u32 reg_addr0, u32 *reg_val0,
6095                                 u32 reg_addr1, u32 *reg_val1)
6096 {
6097         struct i40e_aq_desc desc;
6098         struct i40e_aqc_alternate_write *cmd_resp =
6099                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6100         enum i40e_status_code status;
6101
6102         if (reg_val0 == NULL)
6103                 return I40E_ERR_PARAM;
6104
6105         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6106         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6107         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6108
6109         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6110
6111         if (status == I40E_SUCCESS) {
6112                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6113
6114                 if (reg_val1 != NULL)
6115                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6116         }
6117
6118         return status;
6119 }
6120
6121 /**
6122  * i40e_aq_alternate_read_indirect
6123  * @hw: pointer to the hardware structure
6124  * @addr: address of the alternate structure field
6125  * @dw_count: number of alternate structure fields to read
6126  * @buffer: pointer to the command buffer
6127  *
6128  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6129  * place them in 'buffer'. The buffer should be allocated by caller.
6130  *
6131  **/
6132 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6133                                 u32 addr, u32 dw_count, void *buffer)
6134 {
6135         struct i40e_aq_desc desc;
6136         struct i40e_aqc_alternate_ind_write *cmd_resp =
6137                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6138         enum i40e_status_code status;
6139
6140         if (buffer == NULL)
6141                 return I40E_ERR_PARAM;
6142
6143         /* Indirect command */
6144         i40e_fill_default_direct_cmd_desc(&desc,
6145                 i40e_aqc_opc_alternate_read_indirect);
6146
6147         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6148         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6149         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6150                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6151
6152         cmd_resp->address = CPU_TO_LE32(addr);
6153         cmd_resp->length = CPU_TO_LE32(dw_count);
6154
6155         status = i40e_asq_send_command(hw, &desc, buffer,
6156                                        I40E_LO_DWORD(4*dw_count), NULL);
6157
6158         return status;
6159 }
6160
6161 /**
6162  *  i40e_aq_alternate_clear
6163  *  @hw: pointer to the HW structure.
6164  *
6165  *  Clear the alternate structures of the port from which the function
6166  *  is called.
6167  *
6168  **/
6169 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6170 {
6171         struct i40e_aq_desc desc;
6172         enum i40e_status_code status;
6173
6174         i40e_fill_default_direct_cmd_desc(&desc,
6175                                           i40e_aqc_opc_alternate_clear_port);
6176
6177         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6178
6179         return status;
6180 }
6181
6182 /**
6183  *  i40e_aq_alternate_write_done
6184  *  @hw: pointer to the HW structure.
6185  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6186  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6187  *
6188  *  Indicates to the FW that alternate structures have been changed.
6189  *
6190  **/
6191 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6192                 u8 bios_mode, bool *reset_needed)
6193 {
6194         struct i40e_aq_desc desc;
6195         struct i40e_aqc_alternate_write_done *cmd =
6196                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6197         enum i40e_status_code status;
6198
6199         if (reset_needed == NULL)
6200                 return I40E_ERR_PARAM;
6201
6202         i40e_fill_default_direct_cmd_desc(&desc,
6203                                           i40e_aqc_opc_alternate_write_done);
6204
6205         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6206
6207         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6208         if (!status && reset_needed)
6209                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6210                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6211
6212         return status;
6213 }
6214
6215 /**
6216  *  i40e_aq_set_oem_mode
6217  *  @hw: pointer to the HW structure.
6218  *  @oem_mode: the OEM mode to be used
6219  *
6220  *  Sets the device to a specific operating mode. Currently the only supported
6221  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6222  *
6223  **/
6224 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6225                 u8 oem_mode)
6226 {
6227         struct i40e_aq_desc desc;
6228         struct i40e_aqc_alternate_write_done *cmd =
6229                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6230         enum i40e_status_code status;
6231
6232         i40e_fill_default_direct_cmd_desc(&desc,
6233                                           i40e_aqc_opc_alternate_set_mode);
6234
6235         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6236
6237         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6238
6239         return status;
6240 }
6241
6242 /**
6243  * i40e_aq_resume_port_tx
6244  * @hw: pointer to the hardware structure
6245  * @cmd_details: pointer to command details structure or NULL
6246  *
6247  * Resume port's Tx traffic
6248  **/
6249 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6250                                 struct i40e_asq_cmd_details *cmd_details)
6251 {
6252         struct i40e_aq_desc desc;
6253         enum i40e_status_code status;
6254
6255         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6256
6257         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6258
6259         return status;
6260 }
6261
6262 /**
6263  * i40e_set_pci_config_data - store PCI bus info
6264  * @hw: pointer to hardware structure
6265  * @link_status: the link status word from PCI config space
6266  *
6267  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6268  **/
6269 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6270 {
6271         hw->bus.type = i40e_bus_type_pci_express;
6272
6273         switch (link_status & I40E_PCI_LINK_WIDTH) {
6274         case I40E_PCI_LINK_WIDTH_1:
6275                 hw->bus.width = i40e_bus_width_pcie_x1;
6276                 break;
6277         case I40E_PCI_LINK_WIDTH_2:
6278                 hw->bus.width = i40e_bus_width_pcie_x2;
6279                 break;
6280         case I40E_PCI_LINK_WIDTH_4:
6281                 hw->bus.width = i40e_bus_width_pcie_x4;
6282                 break;
6283         case I40E_PCI_LINK_WIDTH_8:
6284                 hw->bus.width = i40e_bus_width_pcie_x8;
6285                 break;
6286         default:
6287                 hw->bus.width = i40e_bus_width_unknown;
6288                 break;
6289         }
6290
6291         switch (link_status & I40E_PCI_LINK_SPEED) {
6292         case I40E_PCI_LINK_SPEED_2500:
6293                 hw->bus.speed = i40e_bus_speed_2500;
6294                 break;
6295         case I40E_PCI_LINK_SPEED_5000:
6296                 hw->bus.speed = i40e_bus_speed_5000;
6297                 break;
6298         case I40E_PCI_LINK_SPEED_8000:
6299                 hw->bus.speed = i40e_bus_speed_8000;
6300                 break;
6301         default:
6302                 hw->bus.speed = i40e_bus_speed_unknown;
6303                 break;
6304         }
6305 }
6306
6307 /**
6308  * i40e_aq_debug_dump
6309  * @hw: pointer to the hardware structure
6310  * @cluster_id: specific cluster to dump
6311  * @table_id: table id within cluster
6312  * @start_index: index of line in the block to read
6313  * @buff_size: dump buffer size
6314  * @buff: dump buffer
6315  * @ret_buff_size: actual buffer size returned
6316  * @ret_next_table: next block to read
6317  * @ret_next_index: next index to read
6318  * @cmd_details: pointer to command details structure or NULL
6319  *
6320  * Dump internal FW/HW data for debug purposes.
6321  *
6322  **/
6323 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6324                                 u8 table_id, u32 start_index, u16 buff_size,
6325                                 void *buff, u16 *ret_buff_size,
6326                                 u8 *ret_next_table, u32 *ret_next_index,
6327                                 struct i40e_asq_cmd_details *cmd_details)
6328 {
6329         struct i40e_aq_desc desc;
6330         struct i40e_aqc_debug_dump_internals *cmd =
6331                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6332         struct i40e_aqc_debug_dump_internals *resp =
6333                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6334         enum i40e_status_code status;
6335
6336         if (buff_size == 0 || !buff)
6337                 return I40E_ERR_PARAM;
6338
6339         i40e_fill_default_direct_cmd_desc(&desc,
6340                                           i40e_aqc_opc_debug_dump_internals);
6341         /* Indirect Command */
6342         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6343         if (buff_size > I40E_AQ_LARGE_BUF)
6344                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6345
6346         cmd->cluster_id = cluster_id;
6347         cmd->table_id = table_id;
6348         cmd->idx = CPU_TO_LE32(start_index);
6349
6350         desc.datalen = CPU_TO_LE16(buff_size);
6351
6352         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6353         if (!status) {
6354                 if (ret_buff_size != NULL)
6355                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6356                 if (ret_next_table != NULL)
6357                         *ret_next_table = resp->table_id;
6358                 if (ret_next_index != NULL)
6359                         *ret_next_index = LE32_TO_CPU(resp->idx);
6360         }
6361
6362         return status;
6363 }
6364
6365 /**
6366  * i40e_read_bw_from_alt_ram
6367  * @hw: pointer to the hardware structure
6368  * @max_bw: pointer for max_bw read
6369  * @min_bw: pointer for min_bw read
6370  * @min_valid: pointer for bool that is true if min_bw is a valid value
6371  * @max_valid: pointer for bool that is true if max_bw is a valid value
6372  *
6373  * Read bw from the alternate ram for the given pf
6374  **/
6375 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6376                                         u32 *max_bw, u32 *min_bw,
6377                                         bool *min_valid, bool *max_valid)
6378 {
6379         enum i40e_status_code status;
6380         u32 max_bw_addr, min_bw_addr;
6381
6382         /* Calculate the address of the min/max bw registers */
6383         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6384                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6385                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6386         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6387                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6388                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6389
6390         /* Read the bandwidths from alt ram */
6391         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6392                                         min_bw_addr, min_bw);
6393
6394         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6395                 *min_valid = true;
6396         else
6397                 *min_valid = false;
6398
6399         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6400                 *max_valid = true;
6401         else
6402                 *max_valid = false;
6403
6404         return status;
6405 }
6406
6407 /**
6408  * i40e_aq_configure_partition_bw
6409  * @hw: pointer to the hardware structure
6410  * @bw_data: Buffer holding valid pfs and bw limits
6411  * @cmd_details: pointer to command details
6412  *
6413  * Configure partitions guaranteed/max bw
6414  **/
6415 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6416                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6417                         struct i40e_asq_cmd_details *cmd_details)
6418 {
6419         enum i40e_status_code status;
6420         struct i40e_aq_desc desc;
6421         u16 bwd_size = sizeof(*bw_data);
6422
6423         i40e_fill_default_direct_cmd_desc(&desc,
6424                                 i40e_aqc_opc_configure_partition_bw);
6425
6426         /* Indirect command */
6427         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6428         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6429
6430         desc.datalen = CPU_TO_LE16(bwd_size);
6431
6432         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6433
6434         return status;
6435 }
6436
6437 /**
6438  * i40e_read_phy_register_clause22
6439  * @hw: pointer to the HW structure
6440  * @reg: register address in the page
6441  * @phy_addr: PHY address on MDIO interface
6442  * @value: PHY register value
6443  *
6444  * Reads specified PHY register value
6445  **/
6446 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6447                                         u16 reg, u8 phy_addr, u16 *value)
6448 {
6449         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6450         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6451         u32 command = 0;
6452         u16 retry = 1000;
6453
6454         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6455                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6456                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6457                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6458                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6459         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6460         do {
6461                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6462                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6463                         status = I40E_SUCCESS;
6464                         break;
6465                 }
6466                 i40e_usec_delay(10);
6467                 retry--;
6468         } while (retry);
6469
6470         if (status) {
6471                 i40e_debug(hw, I40E_DEBUG_PHY,
6472                            "PHY: Can't write command to external PHY.\n");
6473         } else {
6474                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6475                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6476                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6477         }
6478
6479         return status;
6480 }
6481
6482 /**
6483  * i40e_write_phy_register_clause22
6484  * @hw: pointer to the HW structure
6485  * @reg: register address in the page
6486  * @phy_addr: PHY address on MDIO interface
6487  * @value: PHY register value
6488  *
6489  * Writes specified PHY register value
6490  **/
6491 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6492                                         u16 reg, u8 phy_addr, u16 value)
6493 {
6494         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6495         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6496         u32 command  = 0;
6497         u16 retry = 1000;
6498
6499         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6500         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6501
6502         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6503                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6504                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6505                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6506                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6507
6508         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6509         do {
6510                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6511                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6512                         status = I40E_SUCCESS;
6513                         break;
6514                 }
6515                 i40e_usec_delay(10);
6516                 retry--;
6517         } while (retry);
6518
6519         return status;
6520 }
6521
6522 /**
6523  * i40e_read_phy_register_clause45
6524  * @hw: pointer to the HW structure
6525  * @page: registers page number
6526  * @reg: register address in the page
6527  * @phy_addr: PHY address on MDIO interface
6528  * @value: PHY register value
6529  *
6530  * Reads specified PHY register value
6531  **/
6532 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6533                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6534 {
6535         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6536         u32 command  = 0;
6537         u16 retry = 1000;
6538         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6539
6540         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6541                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6542                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6543                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6544                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6545                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6546                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6547         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6548         do {
6549                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6550                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6551                         status = I40E_SUCCESS;
6552                         break;
6553                 }
6554                 i40e_usec_delay(10);
6555                 retry--;
6556         } while (retry);
6557
6558         if (status) {
6559                 i40e_debug(hw, I40E_DEBUG_PHY,
6560                            "PHY: Can't write command to external PHY.\n");
6561                 goto phy_read_end;
6562         }
6563
6564         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6565                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6566                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6567                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6568                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6569                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6570         status = I40E_ERR_TIMEOUT;
6571         retry = 1000;
6572         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6573         do {
6574                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6575                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6576                         status = I40E_SUCCESS;
6577                         break;
6578                 }
6579                 i40e_usec_delay(10);
6580                 retry--;
6581         } while (retry);
6582
6583         if (!status) {
6584                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6585                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6586                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6587         } else {
6588                 i40e_debug(hw, I40E_DEBUG_PHY,
6589                            "PHY: Can't read register value from external PHY.\n");
6590         }
6591
6592 phy_read_end:
6593         return status;
6594 }
6595
6596 /**
6597  * i40e_write_phy_register_clause45
6598  * @hw: pointer to the HW structure
6599  * @page: registers page number
6600  * @reg: register address in the page
6601  * @phy_addr: PHY address on MDIO interface
6602  * @value: PHY register value
6603  *
6604  * Writes value to specified PHY register
6605  **/
6606 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6607                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6608 {
6609         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6610         u32 command  = 0;
6611         u16 retry = 1000;
6612         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6613
6614         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6615                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6616                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6617                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6618                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6619                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6620                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6621         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6622         do {
6623                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6624                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6625                         status = I40E_SUCCESS;
6626                         break;
6627                 }
6628                 i40e_usec_delay(10);
6629                 retry--;
6630         } while (retry);
6631         if (status) {
6632                 i40e_debug(hw, I40E_DEBUG_PHY,
6633                            "PHY: Can't write command to external PHY.\n");
6634                 goto phy_write_end;
6635         }
6636
6637         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6638         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6639
6640         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6641                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6642                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6643                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6644                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6645                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6646         status = I40E_ERR_TIMEOUT;
6647         retry = 1000;
6648         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6649         do {
6650                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6651                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6652                         status = I40E_SUCCESS;
6653                         break;
6654                 }
6655                 i40e_usec_delay(10);
6656                 retry--;
6657         } while (retry);
6658
6659 phy_write_end:
6660         return status;
6661 }
6662
6663 /**
6664  * i40e_write_phy_register
6665  * @hw: pointer to the HW structure
6666  * @page: registers page number
6667  * @reg: register address in the page
6668  * @phy_addr: PHY address on MDIO interface
6669  * @value: PHY register value
6670  *
6671  * Writes value to specified PHY register
6672  **/
6673 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6674                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6675 {
6676         enum i40e_status_code status;
6677
6678         switch (hw->device_id) {
6679         case I40E_DEV_ID_1G_BASE_T_X722:
6680                 status = i40e_write_phy_register_clause22(hw,
6681                         reg, phy_addr, value);
6682                 break;
6683         case I40E_DEV_ID_10G_BASE_T:
6684         case I40E_DEV_ID_10G_BASE_T4:
6685         case I40E_DEV_ID_10G_BASE_T_X722:
6686         case I40E_DEV_ID_25G_B:
6687         case I40E_DEV_ID_25G_SFP28:
6688                 status = i40e_write_phy_register_clause45(hw,
6689                         page, reg, phy_addr, value);
6690                 break;
6691         default:
6692                 status = I40E_ERR_UNKNOWN_PHY;
6693                 break;
6694         }
6695
6696         return status;
6697 }
6698
6699 /**
6700  * i40e_read_phy_register
6701  * @hw: pointer to the HW structure
6702  * @page: registers page number
6703  * @reg: register address in the page
6704  * @phy_addr: PHY address on MDIO interface
6705  * @value: PHY register value
6706  *
6707  * Reads specified PHY register value
6708  **/
6709 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6710                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6711 {
6712         enum i40e_status_code status;
6713
6714         switch (hw->device_id) {
6715         case I40E_DEV_ID_1G_BASE_T_X722:
6716                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6717                                                          value);
6718                 break;
6719         case I40E_DEV_ID_10G_BASE_T:
6720         case I40E_DEV_ID_10G_BASE_T4:
6721         case I40E_DEV_ID_10G_BASE_T_X722:
6722         case I40E_DEV_ID_25G_B:
6723         case I40E_DEV_ID_25G_SFP28:
6724                 status = i40e_read_phy_register_clause45(hw, page, reg,
6725                                                          phy_addr, value);
6726                 break;
6727         default:
6728                 status = I40E_ERR_UNKNOWN_PHY;
6729                 break;
6730         }
6731
6732         return status;
6733 }
6734
6735 /**
6736  * i40e_get_phy_address
6737  * @hw: pointer to the HW structure
6738  * @dev_num: PHY port num that address we want
6739  *
6740  * Gets PHY address for current port
6741  **/
6742 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6743 {
6744         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6745         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6746
6747         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6748 }
6749
6750 /**
6751  * i40e_blink_phy_led
6752  * @hw: pointer to the HW structure
6753  * @time: time how long led will blinks in secs
6754  * @interval: gap between LED on and off in msecs
6755  *
6756  * Blinks PHY link LED
6757  **/
6758 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6759                                               u32 time, u32 interval)
6760 {
6761         enum i40e_status_code status = I40E_SUCCESS;
6762         u32 i;
6763         u16 led_ctl = 0;
6764         u16 gpio_led_port;
6765         u16 led_reg;
6766         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6767         u8 phy_addr = 0;
6768         u8 port_num;
6769
6770         i = rd32(hw, I40E_PFGEN_PORTNUM);
6771         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6772         phy_addr = i40e_get_phy_address(hw, port_num);
6773
6774         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6775              led_addr++) {
6776                 status = i40e_read_phy_register_clause45(hw,
6777                                                          I40E_PHY_COM_REG_PAGE,
6778                                                          led_addr, phy_addr,
6779                                                          &led_reg);
6780                 if (status)
6781                         goto phy_blinking_end;
6782                 led_ctl = led_reg;
6783                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6784                         led_reg = 0;
6785                         status = i40e_write_phy_register_clause45(hw,
6786                                                          I40E_PHY_COM_REG_PAGE,
6787                                                          led_addr, phy_addr,
6788                                                          led_reg);
6789                         if (status)
6790                                 goto phy_blinking_end;
6791                         break;
6792                 }
6793         }
6794
6795         if (time > 0 && interval > 0) {
6796                 for (i = 0; i < time * 1000; i += interval) {
6797                         status = i40e_read_phy_register_clause45(hw,
6798                                                 I40E_PHY_COM_REG_PAGE,
6799                                                 led_addr, phy_addr, &led_reg);
6800                         if (status)
6801                                 goto restore_config;
6802                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6803                                 led_reg = 0;
6804                         else
6805                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6806                         status = i40e_write_phy_register_clause45(hw,
6807                                                 I40E_PHY_COM_REG_PAGE,
6808                                                 led_addr, phy_addr, led_reg);
6809                         if (status)
6810                                 goto restore_config;
6811                         i40e_msec_delay(interval);
6812                 }
6813         }
6814
6815 restore_config:
6816         status = i40e_write_phy_register_clause45(hw,
6817                                                   I40E_PHY_COM_REG_PAGE,
6818                                                   led_addr, phy_addr, led_ctl);
6819
6820 phy_blinking_end:
6821         return status;
6822 }
6823
6824 /**
6825  * i40e_led_get_reg - read LED register
6826  * @hw: pointer to the HW structure
6827  * @led_addr: LED register address
6828  * @reg_val: read register value
6829  **/
6830 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6831                                               u32 *reg_val)
6832 {
6833         enum i40e_status_code status;
6834         u8 phy_addr = 0;
6835
6836         *reg_val = 0;
6837         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6838                 status = i40e_aq_get_phy_register(hw,
6839                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6840                                                 I40E_PHY_COM_REG_PAGE, true,
6841                                                 I40E_PHY_LED_PROV_REG_1,
6842                                                 reg_val, NULL);
6843         } else {
6844                 phy_addr = i40e_get_phy_address(hw, hw->port);
6845                 status = i40e_read_phy_register_clause45(hw,
6846                                                          I40E_PHY_COM_REG_PAGE,
6847                                                          led_addr, phy_addr,
6848                                                          (u16 *)reg_val);
6849         }
6850         return status;
6851 }
6852
6853 /**
6854  * i40e_led_set_reg - write LED register
6855  * @hw: pointer to the HW structure
6856  * @led_addr: LED register address
6857  * @reg_val: register value to write
6858  **/
6859 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6860                                               u32 reg_val)
6861 {
6862         enum i40e_status_code status;
6863         u8 phy_addr = 0;
6864
6865         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6866                 status = i40e_aq_set_phy_register(hw,
6867                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6868                                                 I40E_PHY_COM_REG_PAGE, true,
6869                                                 I40E_PHY_LED_PROV_REG_1,
6870                                                 reg_val, NULL);
6871         } else {
6872                 phy_addr = i40e_get_phy_address(hw, hw->port);
6873                 status = i40e_write_phy_register_clause45(hw,
6874                                                           I40E_PHY_COM_REG_PAGE,
6875                                                           led_addr, phy_addr,
6876                                                           (u16)reg_val);
6877         }
6878
6879         return status;
6880 }
6881
6882 /**
6883  * i40e_led_get_phy - return current on/off mode
6884  * @hw: pointer to the hw struct
6885  * @led_addr: address of led register to use
6886  * @val: original value of register to use
6887  *
6888  **/
6889 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6890                                        u16 *val)
6891 {
6892         enum i40e_status_code status = I40E_SUCCESS;
6893         u16 gpio_led_port;
6894         u32 reg_val_aq;
6895         u16 temp_addr;
6896         u8 phy_addr = 0;
6897         u16 reg_val;
6898
6899         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6900                 status = i40e_aq_get_phy_register(hw,
6901                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6902                                                 I40E_PHY_COM_REG_PAGE, true,
6903                                                 I40E_PHY_LED_PROV_REG_1,
6904                                                 &reg_val_aq, NULL);
6905                 if (status == I40E_SUCCESS)
6906                         *val = (u16)reg_val_aq;
6907                 return status;
6908         }
6909         temp_addr = I40E_PHY_LED_PROV_REG_1;
6910         phy_addr = i40e_get_phy_address(hw, hw->port);
6911         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6912              temp_addr++) {
6913                 status = i40e_read_phy_register_clause45(hw,
6914                                                          I40E_PHY_COM_REG_PAGE,
6915                                                          temp_addr, phy_addr,
6916                                                          &reg_val);
6917                 if (status)
6918                         return status;
6919                 *val = reg_val;
6920                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6921                         *led_addr = temp_addr;
6922                         break;
6923                 }
6924         }
6925         return status;
6926 }
6927
6928 /**
6929  * i40e_led_set_phy
6930  * @hw: pointer to the HW structure
6931  * @on: true or false
6932  * @led_addr: address of led register to use
6933  * @mode: original val plus bit for set or ignore
6934  *
6935  * Set led's on or off when controlled by the PHY
6936  *
6937  **/
6938 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6939                                        u16 led_addr, u32 mode)
6940 {
6941         enum i40e_status_code status = I40E_SUCCESS;
6942         u32 led_ctl = 0;
6943         u32 led_reg = 0;
6944
6945         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6946         if (status)
6947                 return status;
6948         led_ctl = led_reg;
6949         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6950                 led_reg = 0;
6951                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6952                 if (status)
6953                         return status;
6954         }
6955         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6956         if (status)
6957                 goto restore_config;
6958         if (on)
6959                 led_reg = I40E_PHY_LED_MANUAL_ON;
6960         else
6961                 led_reg = 0;
6962         status = i40e_led_set_reg(hw, led_addr, led_reg);
6963         if (status)
6964                 goto restore_config;
6965         if (mode & I40E_PHY_LED_MODE_ORIG) {
6966                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6967                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6968         }
6969         return status;
6970
6971 restore_config:
6972         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6973         return status;
6974 }
6975 #endif /* PF_DRIVER */
6976
6977 /**
6978  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6979  * @hw: pointer to the hw struct
6980  * @reg_addr: register address
6981  * @reg_val: ptr to register value
6982  * @cmd_details: pointer to command details structure or NULL
6983  *
6984  * Use the firmware to read the Rx control register,
6985  * especially useful if the Rx unit is under heavy pressure
6986  **/
6987 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6988                                 u32 reg_addr, u32 *reg_val,
6989                                 struct i40e_asq_cmd_details *cmd_details)
6990 {
6991         struct i40e_aq_desc desc;
6992         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6993                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6994         enum i40e_status_code status;
6995
6996         if (reg_val == NULL)
6997                 return I40E_ERR_PARAM;
6998
6999         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7000
7001         cmd_resp->address = CPU_TO_LE32(reg_addr);
7002
7003         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7004
7005         if (status == I40E_SUCCESS)
7006                 *reg_val = LE32_TO_CPU(cmd_resp->value);
7007
7008         return status;
7009 }
7010
7011 /**
7012  * i40e_read_rx_ctl - read from an Rx control register
7013  * @hw: pointer to the hw struct
7014  * @reg_addr: register address
7015  **/
7016 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7017 {
7018         enum i40e_status_code status = I40E_SUCCESS;
7019         bool use_register;
7020         int retry = 5;
7021         u32 val = 0;
7022
7023         use_register = (((hw->aq.api_maj_ver == 1) &&
7024                         (hw->aq.api_min_ver < 5)) ||
7025                         (hw->mac.type == I40E_MAC_X722));
7026         if (!use_register) {
7027 do_retry:
7028                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7029                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7030                         i40e_msec_delay(1);
7031                         retry--;
7032                         goto do_retry;
7033                 }
7034         }
7035
7036         /* if the AQ access failed, try the old-fashioned way */
7037         if (status || use_register)
7038                 val = rd32(hw, reg_addr);
7039
7040         return val;
7041 }
7042
7043 /**
7044  * i40e_aq_rx_ctl_write_register
7045  * @hw: pointer to the hw struct
7046  * @reg_addr: register address
7047  * @reg_val: register value
7048  * @cmd_details: pointer to command details structure or NULL
7049  *
7050  * Use the firmware to write to an Rx control register,
7051  * especially useful if the Rx unit is under heavy pressure
7052  **/
7053 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7054                                 u32 reg_addr, u32 reg_val,
7055                                 struct i40e_asq_cmd_details *cmd_details)
7056 {
7057         struct i40e_aq_desc desc;
7058         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7059                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7060         enum i40e_status_code status;
7061
7062         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7063
7064         cmd->address = CPU_TO_LE32(reg_addr);
7065         cmd->value = CPU_TO_LE32(reg_val);
7066
7067         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7068
7069         return status;
7070 }
7071
7072 /**
7073  * i40e_write_rx_ctl - write to an Rx control register
7074  * @hw: pointer to the hw struct
7075  * @reg_addr: register address
7076  * @reg_val: register value
7077  **/
7078 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7079 {
7080         enum i40e_status_code status = I40E_SUCCESS;
7081         bool use_register;
7082         int retry = 5;
7083
7084         use_register = (((hw->aq.api_maj_ver == 1) &&
7085                         (hw->aq.api_min_ver < 5)) ||
7086                         (hw->mac.type == I40E_MAC_X722));
7087         if (!use_register) {
7088 do_retry:
7089                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7090                                                        reg_val, NULL);
7091                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7092                         i40e_msec_delay(1);
7093                         retry--;
7094                         goto do_retry;
7095                 }
7096         }
7097
7098         /* if the AQ access failed, try the old-fashioned way */
7099         if (status || use_register)
7100                 wr32(hw, reg_addr, reg_val);
7101 }
7102
7103 /**
7104  * i40e_aq_set_phy_register
7105  * @hw: pointer to the hw struct
7106  * @phy_select: select which phy should be accessed
7107  * @dev_addr: PHY device address
7108  * @page_change: enable auto page change
7109  * @reg_addr: PHY register address
7110  * @reg_val: new register value
7111  * @cmd_details: pointer to command details structure or NULL
7112  *
7113  * Write the external PHY register.
7114  **/
7115 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7116                                 u8 phy_select, u8 dev_addr, bool page_change,
7117                                 u32 reg_addr, u32 reg_val,
7118                                 struct i40e_asq_cmd_details *cmd_details)
7119 {
7120         struct i40e_aq_desc desc;
7121         struct i40e_aqc_phy_register_access *cmd =
7122                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7123         enum i40e_status_code status;
7124
7125         i40e_fill_default_direct_cmd_desc(&desc,
7126                                           i40e_aqc_opc_set_phy_register);
7127
7128         cmd->phy_interface = phy_select;
7129         cmd->dev_addres = dev_addr;
7130         cmd->reg_address = CPU_TO_LE32(reg_addr);
7131         cmd->reg_value = CPU_TO_LE32(reg_val);
7132
7133         if (!page_change)
7134                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7135
7136         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7137
7138         return status;
7139 }
7140
7141 /**
7142  * i40e_aq_get_phy_register
7143  * @hw: pointer to the hw struct
7144  * @phy_select: select which phy should be accessed
7145  * @dev_addr: PHY device address
7146  * @page_change: enable auto page change
7147  * @reg_addr: PHY register address
7148  * @reg_val: read register value
7149  * @cmd_details: pointer to command details structure or NULL
7150  *
7151  * Read the external PHY register.
7152  **/
7153 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7154                                 u8 phy_select, u8 dev_addr, bool page_change,
7155                                 u32 reg_addr, u32 *reg_val,
7156                                 struct i40e_asq_cmd_details *cmd_details)
7157 {
7158         struct i40e_aq_desc desc;
7159         struct i40e_aqc_phy_register_access *cmd =
7160                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7161         enum i40e_status_code status;
7162
7163         i40e_fill_default_direct_cmd_desc(&desc,
7164                                           i40e_aqc_opc_get_phy_register);
7165
7166         cmd->phy_interface = phy_select;
7167         cmd->dev_addres = dev_addr;
7168         cmd->reg_address = CPU_TO_LE32(reg_addr);
7169
7170         if (!page_change)
7171                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7172
7173         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7174         if (!status)
7175                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7176
7177         return status;
7178 }
7179
7180 #ifdef VF_DRIVER
7181
7182 /**
7183  * i40e_aq_send_msg_to_pf
7184  * @hw: pointer to the hardware structure
7185  * @v_opcode: opcodes for VF-PF communication
7186  * @v_retval: return error code
7187  * @msg: pointer to the msg buffer
7188  * @msglen: msg length
7189  * @cmd_details: pointer to command details
7190  *
7191  * Send message to PF driver using admin queue. By default, this message
7192  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7193  * completion before returning.
7194  **/
7195 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7196                                 enum virtchnl_ops v_opcode,
7197                                 enum i40e_status_code v_retval,
7198                                 u8 *msg, u16 msglen,
7199                                 struct i40e_asq_cmd_details *cmd_details)
7200 {
7201         struct i40e_aq_desc desc;
7202         struct i40e_asq_cmd_details details;
7203         enum i40e_status_code status;
7204
7205         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7206         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7207         desc.cookie_high = CPU_TO_LE32(v_opcode);
7208         desc.cookie_low = CPU_TO_LE32(v_retval);
7209         if (msglen) {
7210                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7211                                                 | I40E_AQ_FLAG_RD));
7212                 if (msglen > I40E_AQ_LARGE_BUF)
7213                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7214                 desc.datalen = CPU_TO_LE16(msglen);
7215         }
7216         if (!cmd_details) {
7217                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7218                 details.async = true;
7219                 cmd_details = &details;
7220         }
7221         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7222                                        msglen, cmd_details);
7223         return status;
7224 }
7225
7226 /**
7227  * i40e_vf_parse_hw_config
7228  * @hw: pointer to the hardware structure
7229  * @msg: pointer to the virtual channel VF resource structure
7230  *
7231  * Given a VF resource message from the PF, populate the hw struct
7232  * with appropriate information.
7233  **/
7234 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7235                              struct virtchnl_vf_resource *msg)
7236 {
7237         struct virtchnl_vsi_resource *vsi_res;
7238         int i;
7239
7240         vsi_res = &msg->vsi_res[0];
7241
7242         hw->dev_caps.num_vsis = msg->num_vsis;
7243         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7244         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7245         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7246         hw->dev_caps.dcb = msg->vf_cap_flags &
7247                            VIRTCHNL_VF_OFFLOAD_L2;
7248         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7249                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7250         for (i = 0; i < msg->num_vsis; i++) {
7251                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7252                         i40e_memcpy(hw->mac.perm_addr,
7253                                     vsi_res->default_mac_addr,
7254                                     ETH_ALEN,
7255                                     I40E_NONDMA_TO_NONDMA);
7256                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7257                                     ETH_ALEN,
7258                                     I40E_NONDMA_TO_NONDMA);
7259                 }
7260                 vsi_res++;
7261         }
7262 }
7263
7264 /**
7265  * i40e_vf_reset
7266  * @hw: pointer to the hardware structure
7267  *
7268  * Send a VF_RESET message to the PF. Does not wait for response from PF
7269  * as none will be forthcoming. Immediately after calling this function,
7270  * the admin queue should be shut down and (optionally) reinitialized.
7271  **/
7272 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7273 {
7274         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7275                                       I40E_SUCCESS, NULL, 0, NULL);
7276 }
7277 #endif /* VF_DRIVER */
7278
7279 /**
7280  * i40e_aq_set_arp_proxy_config
7281  * @hw: pointer to the HW structure
7282  * @proxy_config: pointer to proxy config command table struct
7283  * @cmd_details: pointer to command details
7284  *
7285  * Set ARP offload parameters from pre-populated
7286  * i40e_aqc_arp_proxy_data struct
7287  **/
7288 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7289                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7290                                 struct i40e_asq_cmd_details *cmd_details)
7291 {
7292         struct i40e_aq_desc desc;
7293         enum i40e_status_code status;
7294
7295         if (!proxy_config)
7296                 return I40E_ERR_PARAM;
7297
7298         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7299
7300         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7301         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7302         desc.params.external.addr_high =
7303                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7304         desc.params.external.addr_low =
7305                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7306         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7307
7308         status = i40e_asq_send_command(hw, &desc, proxy_config,
7309                                        sizeof(struct i40e_aqc_arp_proxy_data),
7310                                        cmd_details);
7311
7312         return status;
7313 }
7314
7315 /**
7316  * i40e_aq_opc_set_ns_proxy_table_entry
7317  * @hw: pointer to the HW structure
7318  * @ns_proxy_table_entry: pointer to NS table entry command struct
7319  * @cmd_details: pointer to command details
7320  *
7321  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7322  * from pre-populated i40e_aqc_ns_proxy_data struct
7323  **/
7324 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7325                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7326                         struct i40e_asq_cmd_details *cmd_details)
7327 {
7328         struct i40e_aq_desc desc;
7329         enum i40e_status_code status;
7330
7331         if (!ns_proxy_table_entry)
7332                 return I40E_ERR_PARAM;
7333
7334         i40e_fill_default_direct_cmd_desc(&desc,
7335                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7336
7337         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7338         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7339         desc.params.external.addr_high =
7340                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7341         desc.params.external.addr_low =
7342                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7343         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7344
7345         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7346                                        sizeof(struct i40e_aqc_ns_proxy_data),
7347                                        cmd_details);
7348
7349         return status;
7350 }
7351
7352 /**
7353  * i40e_aq_set_clear_wol_filter
7354  * @hw: pointer to the hw struct
7355  * @filter_index: index of filter to modify (0-7)
7356  * @filter: buffer containing filter to be set
7357  * @set_filter: true to set filter, false to clear filter
7358  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7359  *              if false, pass through packets may cause wake-up
7360  * @filter_valid: true if filter action is valid
7361  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7362  * @cmd_details: pointer to command details structure or NULL
7363  *
7364  * Set or clear WoL filter for port attached to the PF
7365  **/
7366 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7367                                 u8 filter_index,
7368                                 struct i40e_aqc_set_wol_filter_data *filter,
7369                                 bool set_filter, bool no_wol_tco,
7370                                 bool filter_valid, bool no_wol_tco_valid,
7371                                 struct i40e_asq_cmd_details *cmd_details)
7372 {
7373         struct i40e_aq_desc desc;
7374         struct i40e_aqc_set_wol_filter *cmd =
7375                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7376         enum i40e_status_code status;
7377         u16 cmd_flags = 0;
7378         u16 valid_flags = 0;
7379         u16 buff_len = 0;
7380
7381         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7382
7383         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7384                 return  I40E_ERR_PARAM;
7385         cmd->filter_index = CPU_TO_LE16(filter_index);
7386
7387         if (set_filter) {
7388                 if (!filter)
7389                         return  I40E_ERR_PARAM;
7390
7391                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7392                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7393         }
7394
7395         if (no_wol_tco)
7396                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7397         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7398
7399         if (filter_valid)
7400                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7401         if (no_wol_tco_valid)
7402                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7403         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7404
7405         buff_len = sizeof(*filter);
7406         desc.datalen = CPU_TO_LE16(buff_len);
7407
7408         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7409         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7410
7411         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7412         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7413
7414         status = i40e_asq_send_command(hw, &desc, filter,
7415                                        buff_len, cmd_details);
7416
7417         return status;
7418 }
7419
7420 /**
7421  * i40e_aq_get_wake_event_reason
7422  * @hw: pointer to the hw struct
7423  * @wake_reason: return value, index of matching filter
7424  * @cmd_details: pointer to command details structure or NULL
7425  *
7426  * Get information for the reason of a Wake Up event
7427  **/
7428 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7429                                 u16 *wake_reason,
7430                                 struct i40e_asq_cmd_details *cmd_details)
7431 {
7432         struct i40e_aq_desc desc;
7433         struct i40e_aqc_get_wake_reason_completion *resp =
7434                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7435         enum i40e_status_code status;
7436
7437         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7438
7439         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7440
7441         if (status == I40E_SUCCESS)
7442                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7443
7444         return status;
7445 }
7446
7447 /**
7448 * i40e_aq_clear_all_wol_filters
7449 * @hw: pointer to the hw struct
7450 * @cmd_details: pointer to command details structure or NULL
7451 *
7452 * Get information for the reason of a Wake Up event
7453 **/
7454 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7455         struct i40e_asq_cmd_details *cmd_details)
7456 {
7457         struct i40e_aq_desc desc;
7458         enum i40e_status_code status;
7459
7460         i40e_fill_default_direct_cmd_desc(&desc,
7461                                           i40e_aqc_opc_clear_all_wol_filters);
7462
7463         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7464
7465         return status;
7466 }
7467
7468 /**
7469  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7470  * @hw: pointer to the hw struct
7471  * @buff: command buffer (size in bytes = buff_size)
7472  * @buff_size: buffer size in bytes
7473  * @track_id: package tracking id
7474  * @error_offset: returns error offset
7475  * @error_info: returns error information
7476  * @cmd_details: pointer to command details structure or NULL
7477  **/
7478 enum
7479 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7480                                    u16 buff_size, u32 track_id,
7481                                    u32 *error_offset, u32 *error_info,
7482                                    struct i40e_asq_cmd_details *cmd_details)
7483 {
7484         struct i40e_aq_desc desc;
7485         struct i40e_aqc_write_personalization_profile *cmd =
7486                 (struct i40e_aqc_write_personalization_profile *)
7487                 &desc.params.raw;
7488         struct i40e_aqc_write_ddp_resp *resp;
7489         enum i40e_status_code status;
7490
7491         i40e_fill_default_direct_cmd_desc(&desc,
7492                                   i40e_aqc_opc_write_personalization_profile);
7493
7494         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7495         if (buff_size > I40E_AQ_LARGE_BUF)
7496                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7497
7498         desc.datalen = CPU_TO_LE16(buff_size);
7499
7500         cmd->profile_track_id = CPU_TO_LE32(track_id);
7501
7502         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7503         if (!status) {
7504                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7505                 if (error_offset)
7506                         *error_offset = LE32_TO_CPU(resp->error_offset);
7507                 if (error_info)
7508                         *error_info = LE32_TO_CPU(resp->error_info);
7509         }
7510
7511         return status;
7512 }
7513
7514 /**
7515  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7516  * @hw: pointer to the hw struct
7517  * @buff: command buffer (size in bytes = buff_size)
7518  * @buff_size: buffer size in bytes
7519  * @flags: AdminQ command flags
7520  * @cmd_details: pointer to command details structure or NULL
7521  **/
7522 enum
7523 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7524                                       u16 buff_size, u8 flags,
7525                                       struct i40e_asq_cmd_details *cmd_details)
7526 {
7527         struct i40e_aq_desc desc;
7528         struct i40e_aqc_get_applied_profiles *cmd =
7529                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7530         enum i40e_status_code status;
7531
7532         i40e_fill_default_direct_cmd_desc(&desc,
7533                           i40e_aqc_opc_get_personalization_profile_list);
7534
7535         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7536         if (buff_size > I40E_AQ_LARGE_BUF)
7537                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7538         desc.datalen = CPU_TO_LE16(buff_size);
7539
7540         cmd->flags = flags;
7541
7542         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7543
7544         return status;
7545 }
7546
7547 /**
7548  * i40e_find_segment_in_package
7549  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7550  * @pkg_hdr: pointer to the package header to be searched
7551  *
7552  * This function searches a package file for a particular segment type. On
7553  * success it returns a pointer to the segment header, otherwise it will
7554  * return NULL.
7555  **/
7556 struct i40e_generic_seg_header *
7557 i40e_find_segment_in_package(u32 segment_type,
7558                              struct i40e_package_header *pkg_hdr)
7559 {
7560         struct i40e_generic_seg_header *segment;
7561         u32 i;
7562
7563         /* Search all package segments for the requested segment type */
7564         for (i = 0; i < pkg_hdr->segment_count; i++) {
7565                 segment =
7566                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7567                          pkg_hdr->segment_offset[i]);
7568
7569                 if (segment->type == segment_type)
7570                         return segment;
7571         }
7572
7573         return NULL;
7574 }
7575
7576 /* Get section table in profile */
7577 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7578         do {                                                            \
7579                 struct i40e_profile_segment *p = (profile);             \
7580                 u32 count;                                              \
7581                 u32 *nvm;                                               \
7582                 count = p->device_table_count;                          \
7583                 nvm = (u32 *)&p->device_table[count];                   \
7584                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7585         } while (0)
7586
7587 /* Get section header in profile */
7588 #define I40E_SECTION_HEADER(profile, offset)                            \
7589         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7590
7591 /**
7592  * i40e_find_section_in_profile
7593  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7594  * @profile: pointer to the i40e segment header to be searched
7595  *
7596  * This function searches i40e segment for a particular section type. On
7597  * success it returns a pointer to the section header, otherwise it will
7598  * return NULL.
7599  **/
7600 struct i40e_profile_section_header *
7601 i40e_find_section_in_profile(u32 section_type,
7602                              struct i40e_profile_segment *profile)
7603 {
7604         struct i40e_profile_section_header *sec;
7605         struct i40e_section_table *sec_tbl;
7606         u32 sec_off;
7607         u32 i;
7608
7609         if (profile->header.type != SEGMENT_TYPE_I40E)
7610                 return NULL;
7611
7612         I40E_SECTION_TABLE(profile, sec_tbl);
7613
7614         for (i = 0; i < sec_tbl->section_count; i++) {
7615                 sec_off = sec_tbl->section_offset[i];
7616                 sec = I40E_SECTION_HEADER(profile, sec_off);
7617                 if (sec->section.type == section_type)
7618                         return sec;
7619         }
7620
7621         return NULL;
7622 }
7623
7624 /**
7625  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7626  * @hw: pointer to the hw struct
7627  * @aq: command buffer containing all data to execute AQ
7628  **/
7629 STATIC enum
7630 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7631                                           struct i40e_profile_aq_section *aq)
7632 {
7633         enum i40e_status_code status;
7634         struct i40e_aq_desc desc;
7635         u8 *msg = NULL;
7636         u16 msglen;
7637
7638         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7639         desc.flags |= CPU_TO_LE16(aq->flags);
7640         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7641                     I40E_NONDMA_TO_NONDMA);
7642
7643         msglen = aq->datalen;
7644         if (msglen) {
7645                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7646                                                 I40E_AQ_FLAG_RD));
7647                 if (msglen > I40E_AQ_LARGE_BUF)
7648                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7649                 desc.datalen = CPU_TO_LE16(msglen);
7650                 msg = &aq->data[0];
7651         }
7652
7653         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7654
7655         if (status != I40E_SUCCESS) {
7656                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7657                            "unable to exec DDP AQ opcode %u, error %d\n",
7658                            aq->opcode, status);
7659                 return status;
7660         }
7661
7662         /* copy returned desc to aq_buf */
7663         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7664                     I40E_NONDMA_TO_NONDMA);
7665
7666         return I40E_SUCCESS;
7667 }
7668
7669 /**
7670  * i40e_validate_profile
7671  * @hw: pointer to the hardware structure
7672  * @profile: pointer to the profile segment of the package to be validated
7673  * @track_id: package tracking id
7674  * @rollback: flag if the profile is for rollback.
7675  *
7676  * Validates supported devices and profile's sections.
7677  */
7678 STATIC enum i40e_status_code
7679 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7680                       u32 track_id, bool rollback)
7681 {
7682         struct i40e_profile_section_header *sec = NULL;
7683         enum i40e_status_code status = I40E_SUCCESS;
7684         struct i40e_section_table *sec_tbl;
7685         u32 vendor_dev_id;
7686         u32 dev_cnt;
7687         u32 sec_off;
7688         u32 i;
7689
7690         if (track_id == I40E_DDP_TRACKID_INVALID) {
7691                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7692                 return I40E_NOT_SUPPORTED;
7693         }
7694
7695         dev_cnt = profile->device_table_count;
7696         for (i = 0; i < dev_cnt; i++) {
7697                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7698                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7699                     hw->device_id == (vendor_dev_id & 0xFFFF))
7700                         break;
7701         }
7702         if (dev_cnt && (i == dev_cnt)) {
7703                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7704                            "Device doesn't support DDP\n");
7705                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7706         }
7707
7708         I40E_SECTION_TABLE(profile, sec_tbl);
7709
7710         /* Validate sections types */
7711         for (i = 0; i < sec_tbl->section_count; i++) {
7712                 sec_off = sec_tbl->section_offset[i];
7713                 sec = I40E_SECTION_HEADER(profile, sec_off);
7714                 if (rollback) {
7715                         if (sec->section.type == SECTION_TYPE_MMIO ||
7716                             sec->section.type == SECTION_TYPE_AQ ||
7717                             sec->section.type == SECTION_TYPE_RB_AQ) {
7718                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7719                                            "Not a roll-back package\n");
7720                                 return I40E_NOT_SUPPORTED;
7721                         }
7722                 } else {
7723                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7724                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7725                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7726                                            "Not an original package\n");
7727                                 return I40E_NOT_SUPPORTED;
7728                         }
7729                 }
7730         }
7731
7732         return status;
7733 }
7734
7735 /**
7736  * i40e_write_profile
7737  * @hw: pointer to the hardware structure
7738  * @profile: pointer to the profile segment of the package to be downloaded
7739  * @track_id: package tracking id
7740  *
7741  * Handles the download of a complete package.
7742  */
7743 enum i40e_status_code
7744 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7745                    u32 track_id)
7746 {
7747         enum i40e_status_code status = I40E_SUCCESS;
7748         struct i40e_section_table *sec_tbl;
7749         struct i40e_profile_section_header *sec = NULL;
7750         struct i40e_profile_aq_section *ddp_aq;
7751         u32 section_size = 0;
7752         u32 offset = 0, info = 0;
7753         u32 sec_off;
7754         u32 i;
7755
7756         status = i40e_validate_profile(hw, profile, track_id, false);
7757         if (status)
7758                 return status;
7759
7760         I40E_SECTION_TABLE(profile, sec_tbl);
7761
7762         for (i = 0; i < sec_tbl->section_count; i++) {
7763                 sec_off = sec_tbl->section_offset[i];
7764                 sec = I40E_SECTION_HEADER(profile, sec_off);
7765                 /* Process generic admin command */
7766                 if (sec->section.type == SECTION_TYPE_AQ) {
7767                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7768                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7769                         if (status) {
7770                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7771                                            "Failed to execute aq: section %d, opcode %u\n",
7772                                            i, ddp_aq->opcode);
7773                                 break;
7774                         }
7775                         sec->section.type = SECTION_TYPE_RB_AQ;
7776                 }
7777
7778                 /* Skip any non-mmio sections */
7779                 if (sec->section.type != SECTION_TYPE_MMIO)
7780                         continue;
7781
7782                 section_size = sec->section.size +
7783                         sizeof(struct i40e_profile_section_header);
7784
7785                 /* Write MMIO section */
7786                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7787                                            track_id, &offset, &info, NULL);
7788                 if (status) {
7789                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7790                                    "Failed to write profile: section %d, offset %d, info %d\n",
7791                                    i, offset, info);
7792                         break;
7793                 }
7794         }
7795         return status;
7796 }
7797
7798 /**
7799  * i40e_rollback_profile
7800  * @hw: pointer to the hardware structure
7801  * @profile: pointer to the profile segment of the package to be removed
7802  * @track_id: package tracking id
7803  *
7804  * Rolls back previously loaded package.
7805  */
7806 enum i40e_status_code
7807 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7808                       u32 track_id)
7809 {
7810         struct i40e_profile_section_header *sec = NULL;
7811         enum i40e_status_code status = I40E_SUCCESS;
7812         struct i40e_section_table *sec_tbl;
7813         u32 offset = 0, info = 0;
7814         u32 section_size = 0;
7815         u32 sec_off;
7816         int i;
7817
7818         status = i40e_validate_profile(hw, profile, track_id, true);
7819         if (status)
7820                 return status;
7821
7822         I40E_SECTION_TABLE(profile, sec_tbl);
7823
7824         /* For rollback write sections in reverse */
7825         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7826                 sec_off = sec_tbl->section_offset[i];
7827                 sec = I40E_SECTION_HEADER(profile, sec_off);
7828
7829                 /* Skip any non-rollback sections */
7830                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7831                         continue;
7832
7833                 section_size = sec->section.size +
7834                         sizeof(struct i40e_profile_section_header);
7835
7836                 /* Write roll-back MMIO section */
7837                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7838                                            track_id, &offset, &info, NULL);
7839                 if (status) {
7840                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7841                                    "Failed to write profile: section %d, offset %d, info %d\n",
7842                                    i, offset, info);
7843                         break;
7844                 }
7845         }
7846         return status;
7847 }
7848
7849 /**
7850  * i40e_add_pinfo_to_list
7851  * @hw: pointer to the hardware structure
7852  * @profile: pointer to the profile segment of the package
7853  * @profile_info_sec: buffer for information section
7854  * @track_id: package tracking id
7855  *
7856  * Register a profile to the list of loaded profiles.
7857  */
7858 enum i40e_status_code
7859 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7860                        struct i40e_profile_segment *profile,
7861                        u8 *profile_info_sec, u32 track_id)
7862 {
7863         enum i40e_status_code status = I40E_SUCCESS;
7864         struct i40e_profile_section_header *sec = NULL;
7865         struct i40e_profile_info *pinfo;
7866         u32 offset = 0, info = 0;
7867
7868         sec = (struct i40e_profile_section_header *)profile_info_sec;
7869         sec->tbl_size = 1;
7870         sec->data_end = sizeof(struct i40e_profile_section_header) +
7871                         sizeof(struct i40e_profile_info);
7872         sec->section.type = SECTION_TYPE_INFO;
7873         sec->section.offset = sizeof(struct i40e_profile_section_header);
7874         sec->section.size = sizeof(struct i40e_profile_info);
7875         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7876                                              sec->section.offset);
7877         pinfo->track_id = track_id;
7878         pinfo->version = profile->version;
7879         pinfo->op = I40E_DDP_ADD_TRACKID;
7880         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7881                     I40E_NONDMA_TO_NONDMA);
7882
7883         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7884                                    track_id, &offset, &info, NULL);
7885         return status;
7886 }