1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
6 #include "i40e_adminq.h"
7 #include "i40e_prototype.h"
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
17 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
19 enum i40e_status_code status = I40E_SUCCESS;
21 DEBUGFUNC("i40e_set_mac_type\n");
23 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
24 switch (hw->device_id) {
25 case I40E_DEV_ID_SFP_XL710:
26 case I40E_DEV_ID_QEMU:
27 case I40E_DEV_ID_KX_B:
28 case I40E_DEV_ID_KX_C:
29 case I40E_DEV_ID_QSFP_A:
30 case I40E_DEV_ID_QSFP_B:
31 case I40E_DEV_ID_QSFP_C:
32 case I40E_DEV_ID_10G_BASE_T:
33 case I40E_DEV_ID_10G_BASE_T4:
34 case I40E_DEV_ID_10G_BASE_T_BC:
35 case I40E_DEV_ID_10G_B:
36 case I40E_DEV_ID_10G_SFP:
37 case I40E_DEV_ID_5G_BASE_T_BC:
38 case I40E_DEV_ID_20G_KR2:
39 case I40E_DEV_ID_20G_KR2_A:
40 case I40E_DEV_ID_25G_B:
41 case I40E_DEV_ID_25G_SFP28:
42 case I40E_DEV_ID_X710_N3000:
43 case I40E_DEV_ID_XXV710_N3000:
44 hw->mac.type = I40E_MAC_XL710;
46 #ifdef X722_A0_SUPPORT
47 case I40E_DEV_ID_X722_A0:
49 case I40E_DEV_ID_KX_X722:
50 case I40E_DEV_ID_QSFP_X722:
51 case I40E_DEV_ID_SFP_X722:
52 case I40E_DEV_ID_1G_BASE_T_X722:
53 case I40E_DEV_ID_10G_BASE_T_X722:
54 case I40E_DEV_ID_SFP_I_X722:
55 hw->mac.type = I40E_MAC_X722;
57 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
58 case I40E_DEV_ID_X722_VF:
59 #ifdef X722_A0_SUPPORT
60 case I40E_DEV_ID_X722_A0_VF:
62 hw->mac.type = I40E_MAC_X722_VF;
64 #endif /* INTEGRATED_VF || VF_DRIVER */
65 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
67 case I40E_DEV_ID_VF_HV:
68 case I40E_DEV_ID_ADAPTIVE_VF:
69 hw->mac.type = I40E_MAC_VF;
73 hw->mac.type = I40E_MAC_GENERIC;
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
80 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
86 * i40e_aq_str - convert AQ err code to a string
87 * @hw: pointer to the HW structure
88 * @aq_err: the AQ error code to convert
90 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
95 case I40E_AQ_RC_EPERM:
96 return "I40E_AQ_RC_EPERM";
97 case I40E_AQ_RC_ENOENT:
98 return "I40E_AQ_RC_ENOENT";
99 case I40E_AQ_RC_ESRCH:
100 return "I40E_AQ_RC_ESRCH";
101 case I40E_AQ_RC_EINTR:
102 return "I40E_AQ_RC_EINTR";
104 return "I40E_AQ_RC_EIO";
105 case I40E_AQ_RC_ENXIO:
106 return "I40E_AQ_RC_ENXIO";
107 case I40E_AQ_RC_E2BIG:
108 return "I40E_AQ_RC_E2BIG";
109 case I40E_AQ_RC_EAGAIN:
110 return "I40E_AQ_RC_EAGAIN";
111 case I40E_AQ_RC_ENOMEM:
112 return "I40E_AQ_RC_ENOMEM";
113 case I40E_AQ_RC_EACCES:
114 return "I40E_AQ_RC_EACCES";
115 case I40E_AQ_RC_EFAULT:
116 return "I40E_AQ_RC_EFAULT";
117 case I40E_AQ_RC_EBUSY:
118 return "I40E_AQ_RC_EBUSY";
119 case I40E_AQ_RC_EEXIST:
120 return "I40E_AQ_RC_EEXIST";
121 case I40E_AQ_RC_EINVAL:
122 return "I40E_AQ_RC_EINVAL";
123 case I40E_AQ_RC_ENOTTY:
124 return "I40E_AQ_RC_ENOTTY";
125 case I40E_AQ_RC_ENOSPC:
126 return "I40E_AQ_RC_ENOSPC";
127 case I40E_AQ_RC_ENOSYS:
128 return "I40E_AQ_RC_ENOSYS";
129 case I40E_AQ_RC_ERANGE:
130 return "I40E_AQ_RC_ERANGE";
131 case I40E_AQ_RC_EFLUSHED:
132 return "I40E_AQ_RC_EFLUSHED";
133 case I40E_AQ_RC_BAD_ADDR:
134 return "I40E_AQ_RC_BAD_ADDR";
135 case I40E_AQ_RC_EMODE:
136 return "I40E_AQ_RC_EMODE";
137 case I40E_AQ_RC_EFBIG:
138 return "I40E_AQ_RC_EFBIG";
141 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
146 * i40e_stat_str - convert status err code to a string
147 * @hw: pointer to the HW structure
148 * @stat_err: the status error code to convert
150 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
156 return "I40E_ERR_NVM";
157 case I40E_ERR_NVM_CHECKSUM:
158 return "I40E_ERR_NVM_CHECKSUM";
160 return "I40E_ERR_PHY";
161 case I40E_ERR_CONFIG:
162 return "I40E_ERR_CONFIG";
164 return "I40E_ERR_PARAM";
165 case I40E_ERR_MAC_TYPE:
166 return "I40E_ERR_MAC_TYPE";
167 case I40E_ERR_UNKNOWN_PHY:
168 return "I40E_ERR_UNKNOWN_PHY";
169 case I40E_ERR_LINK_SETUP:
170 return "I40E_ERR_LINK_SETUP";
171 case I40E_ERR_ADAPTER_STOPPED:
172 return "I40E_ERR_ADAPTER_STOPPED";
173 case I40E_ERR_INVALID_MAC_ADDR:
174 return "I40E_ERR_INVALID_MAC_ADDR";
175 case I40E_ERR_DEVICE_NOT_SUPPORTED:
176 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
177 case I40E_ERR_MASTER_REQUESTS_PENDING:
178 return "I40E_ERR_MASTER_REQUESTS_PENDING";
179 case I40E_ERR_INVALID_LINK_SETTINGS:
180 return "I40E_ERR_INVALID_LINK_SETTINGS";
181 case I40E_ERR_AUTONEG_NOT_COMPLETE:
182 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
183 case I40E_ERR_RESET_FAILED:
184 return "I40E_ERR_RESET_FAILED";
185 case I40E_ERR_SWFW_SYNC:
186 return "I40E_ERR_SWFW_SYNC";
187 case I40E_ERR_NO_AVAILABLE_VSI:
188 return "I40E_ERR_NO_AVAILABLE_VSI";
189 case I40E_ERR_NO_MEMORY:
190 return "I40E_ERR_NO_MEMORY";
191 case I40E_ERR_BAD_PTR:
192 return "I40E_ERR_BAD_PTR";
193 case I40E_ERR_RING_FULL:
194 return "I40E_ERR_RING_FULL";
195 case I40E_ERR_INVALID_PD_ID:
196 return "I40E_ERR_INVALID_PD_ID";
197 case I40E_ERR_INVALID_QP_ID:
198 return "I40E_ERR_INVALID_QP_ID";
199 case I40E_ERR_INVALID_CQ_ID:
200 return "I40E_ERR_INVALID_CQ_ID";
201 case I40E_ERR_INVALID_CEQ_ID:
202 return "I40E_ERR_INVALID_CEQ_ID";
203 case I40E_ERR_INVALID_AEQ_ID:
204 return "I40E_ERR_INVALID_AEQ_ID";
205 case I40E_ERR_INVALID_SIZE:
206 return "I40E_ERR_INVALID_SIZE";
207 case I40E_ERR_INVALID_ARP_INDEX:
208 return "I40E_ERR_INVALID_ARP_INDEX";
209 case I40E_ERR_INVALID_FPM_FUNC_ID:
210 return "I40E_ERR_INVALID_FPM_FUNC_ID";
211 case I40E_ERR_QP_INVALID_MSG_SIZE:
212 return "I40E_ERR_QP_INVALID_MSG_SIZE";
213 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
214 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
215 case I40E_ERR_INVALID_FRAG_COUNT:
216 return "I40E_ERR_INVALID_FRAG_COUNT";
217 case I40E_ERR_QUEUE_EMPTY:
218 return "I40E_ERR_QUEUE_EMPTY";
219 case I40E_ERR_INVALID_ALIGNMENT:
220 return "I40E_ERR_INVALID_ALIGNMENT";
221 case I40E_ERR_FLUSHED_QUEUE:
222 return "I40E_ERR_FLUSHED_QUEUE";
223 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
224 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
225 case I40E_ERR_INVALID_IMM_DATA_SIZE:
226 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
227 case I40E_ERR_TIMEOUT:
228 return "I40E_ERR_TIMEOUT";
229 case I40E_ERR_OPCODE_MISMATCH:
230 return "I40E_ERR_OPCODE_MISMATCH";
231 case I40E_ERR_CQP_COMPL_ERROR:
232 return "I40E_ERR_CQP_COMPL_ERROR";
233 case I40E_ERR_INVALID_VF_ID:
234 return "I40E_ERR_INVALID_VF_ID";
235 case I40E_ERR_INVALID_HMCFN_ID:
236 return "I40E_ERR_INVALID_HMCFN_ID";
237 case I40E_ERR_BACKING_PAGE_ERROR:
238 return "I40E_ERR_BACKING_PAGE_ERROR";
239 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
240 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
241 case I40E_ERR_INVALID_PBLE_INDEX:
242 return "I40E_ERR_INVALID_PBLE_INDEX";
243 case I40E_ERR_INVALID_SD_INDEX:
244 return "I40E_ERR_INVALID_SD_INDEX";
245 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
246 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
247 case I40E_ERR_INVALID_SD_TYPE:
248 return "I40E_ERR_INVALID_SD_TYPE";
249 case I40E_ERR_MEMCPY_FAILED:
250 return "I40E_ERR_MEMCPY_FAILED";
251 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
252 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
253 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
254 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
255 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
256 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
257 case I40E_ERR_SRQ_ENABLED:
258 return "I40E_ERR_SRQ_ENABLED";
259 case I40E_ERR_ADMIN_QUEUE_ERROR:
260 return "I40E_ERR_ADMIN_QUEUE_ERROR";
261 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
262 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
263 case I40E_ERR_BUF_TOO_SHORT:
264 return "I40E_ERR_BUF_TOO_SHORT";
265 case I40E_ERR_ADMIN_QUEUE_FULL:
266 return "I40E_ERR_ADMIN_QUEUE_FULL";
267 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
268 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
269 case I40E_ERR_BAD_IWARP_CQE:
270 return "I40E_ERR_BAD_IWARP_CQE";
271 case I40E_ERR_NVM_BLANK_MODE:
272 return "I40E_ERR_NVM_BLANK_MODE";
273 case I40E_ERR_NOT_IMPLEMENTED:
274 return "I40E_ERR_NOT_IMPLEMENTED";
275 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
276 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
277 case I40E_ERR_DIAG_TEST_FAILED:
278 return "I40E_ERR_DIAG_TEST_FAILED";
279 case I40E_ERR_NOT_READY:
280 return "I40E_ERR_NOT_READY";
281 case I40E_NOT_SUPPORTED:
282 return "I40E_NOT_SUPPORTED";
283 case I40E_ERR_FIRMWARE_API_VERSION:
284 return "I40E_ERR_FIRMWARE_API_VERSION";
285 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
286 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
289 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
295 * @hw: debug mask related to admin queue
297 * @desc: pointer to admin queue descriptor
298 * @buffer: pointer to command buffer
299 * @buf_len: max length of buffer
301 * Dumps debug log about adminq command with descriptor contents.
303 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
304 void *buffer, u16 buf_len)
306 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
307 u32 effective_mask = hw->debug_mask & mask;
308 u8 *buf = (u8 *)buffer;
312 if (!effective_mask || !desc)
315 len = LE16_TO_CPU(aq_desc->datalen);
317 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
318 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
319 LE16_TO_CPU(aq_desc->opcode),
320 LE16_TO_CPU(aq_desc->flags),
321 LE16_TO_CPU(aq_desc->datalen),
322 LE16_TO_CPU(aq_desc->retval));
323 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
324 "\tcookie (h,l) 0x%08X 0x%08X\n",
325 LE32_TO_CPU(aq_desc->cookie_high),
326 LE32_TO_CPU(aq_desc->cookie_low));
327 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
328 "\tparam (0,1) 0x%08X 0x%08X\n",
329 LE32_TO_CPU(aq_desc->params.internal.param0),
330 LE32_TO_CPU(aq_desc->params.internal.param1));
331 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
332 "\taddr (h,l) 0x%08X 0x%08X\n",
333 LE32_TO_CPU(aq_desc->params.external.addr_high),
334 LE32_TO_CPU(aq_desc->params.external.addr_low));
336 if (buffer && (buf_len != 0) && (len != 0) &&
337 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
338 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
341 /* write the full 16-byte chunks */
342 for (i = 0; i < (len - 16); i += 16)
344 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
345 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
346 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
347 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
348 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
349 /* the most we could have left is 16 bytes, pad with zeros */
355 memset(d_buf, 0, sizeof(d_buf));
356 for (j = 0; i < len; j++, i++)
359 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
360 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
361 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
362 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
363 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
369 * i40e_check_asq_alive
370 * @hw: pointer to the hw struct
372 * Returns true if Queue is enabled else false.
374 bool i40e_check_asq_alive(struct i40e_hw *hw)
380 return !!(rd32(hw, hw->aq.asq.len) &
381 I40E_PF_ATQLEN_ATQENABLE_MASK);
383 return !!(rd32(hw, hw->aq.asq.len) &
384 I40E_PF_ATQLEN_ATQENABLE_MASK);
385 #endif /* INTEGRATED_VF */
386 #endif /* PF_DRIVER */
390 return !!(rd32(hw, hw->aq.asq.len) &
391 I40E_VF_ATQLEN1_ATQENABLE_MASK);
393 return !!(rd32(hw, hw->aq.asq.len) &
394 I40E_VF_ATQLEN1_ATQENABLE_MASK);
395 #endif /* INTEGRATED_VF */
396 #endif /* VF_DRIVER */
401 * i40e_aq_queue_shutdown
402 * @hw: pointer to the hw struct
403 * @unloading: is the driver unloading itself
405 * Tell the Firmware that we're shutting down the AdminQ and whether
406 * or not the driver is unloading as well.
408 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
411 struct i40e_aq_desc desc;
412 struct i40e_aqc_queue_shutdown *cmd =
413 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
414 enum i40e_status_code status;
416 i40e_fill_default_direct_cmd_desc(&desc,
417 i40e_aqc_opc_queue_shutdown);
420 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
421 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
427 * i40e_aq_get_set_rss_lut
428 * @hw: pointer to the hardware structure
429 * @vsi_id: vsi fw index
430 * @pf_lut: for PF table set true, for VSI table set false
431 * @lut: pointer to the lut buffer provided by the caller
432 * @lut_size: size of the lut buffer
433 * @set: set true to set the table, false to get the table
435 * Internal function to get or set RSS look up table
437 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
438 u16 vsi_id, bool pf_lut,
439 u8 *lut, u16 lut_size,
442 enum i40e_status_code status;
443 struct i40e_aq_desc desc;
444 struct i40e_aqc_get_set_rss_lut *cmd_resp =
445 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
448 i40e_fill_default_direct_cmd_desc(&desc,
449 i40e_aqc_opc_set_rss_lut);
451 i40e_fill_default_direct_cmd_desc(&desc,
452 i40e_aqc_opc_get_rss_lut);
454 /* Indirect command */
455 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
456 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
459 CPU_TO_LE16((u16)((vsi_id <<
460 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
461 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
462 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
465 cmd_resp->flags |= CPU_TO_LE16((u16)
466 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
467 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
468 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
470 cmd_resp->flags |= CPU_TO_LE16((u16)
471 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
472 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
473 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
475 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
481 * i40e_aq_get_rss_lut
482 * @hw: pointer to the hardware structure
483 * @vsi_id: vsi fw index
484 * @pf_lut: for PF table set true, for VSI table set false
485 * @lut: pointer to the lut buffer provided by the caller
486 * @lut_size: size of the lut buffer
488 * get the RSS lookup table, PF or VSI type
490 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
491 bool pf_lut, u8 *lut, u16 lut_size)
493 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
498 * i40e_aq_set_rss_lut
499 * @hw: pointer to the hardware structure
500 * @vsi_id: vsi fw index
501 * @pf_lut: for PF table set true, for VSI table set false
502 * @lut: pointer to the lut buffer provided by the caller
503 * @lut_size: size of the lut buffer
505 * set the RSS lookup table, PF or VSI type
507 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
508 bool pf_lut, u8 *lut, u16 lut_size)
510 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
514 * i40e_aq_get_set_rss_key
515 * @hw: pointer to the hw struct
516 * @vsi_id: vsi fw index
517 * @key: pointer to key info struct
518 * @set: set true to set the key, false to get the key
520 * get the RSS key per VSI
522 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
524 struct i40e_aqc_get_set_rss_key_data *key,
527 enum i40e_status_code status;
528 struct i40e_aq_desc desc;
529 struct i40e_aqc_get_set_rss_key *cmd_resp =
530 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
531 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
534 i40e_fill_default_direct_cmd_desc(&desc,
535 i40e_aqc_opc_set_rss_key);
537 i40e_fill_default_direct_cmd_desc(&desc,
538 i40e_aqc_opc_get_rss_key);
540 /* Indirect command */
541 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
542 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
545 CPU_TO_LE16((u16)((vsi_id <<
546 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
547 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
548 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
550 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
556 * i40e_aq_get_rss_key
557 * @hw: pointer to the hw struct
558 * @vsi_id: vsi fw index
559 * @key: pointer to key info struct
562 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
564 struct i40e_aqc_get_set_rss_key_data *key)
566 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
570 * i40e_aq_set_rss_key
571 * @hw: pointer to the hw struct
572 * @vsi_id: vsi fw index
573 * @key: pointer to key info struct
575 * set the RSS key per VSI
577 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
579 struct i40e_aqc_get_set_rss_key_data *key)
581 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
584 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
585 * hardware to a bit-field that can be used by SW to more easily determine the
588 * Macros are used to shorten the table lines and make this table human
591 * We store the PTYPE in the top byte of the bit field - this is just so that
592 * we can check that the table doesn't have a row missing, as the index into
593 * the table should be the PTYPE.
597 * IF NOT i40e_ptype_lookup[ptype].known
600 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
601 * Use the rest of the fields to look at the tunnels, inner protocols, etc
603 * Use the enum i40e_rx_l2_ptype to decode the packet type
607 /* macro to make the table lines short */
608 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
611 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
612 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
613 I40E_RX_PTYPE_##OUTER_FRAG, \
614 I40E_RX_PTYPE_TUNNEL_##T, \
615 I40E_RX_PTYPE_TUNNEL_END_##TE, \
616 I40E_RX_PTYPE_##TEF, \
617 I40E_RX_PTYPE_INNER_PROT_##I, \
618 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
620 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
621 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
623 /* shorter macros makes the table fit but are terse */
624 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
625 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
626 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
628 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
629 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
630 /* L2 Packet types */
631 I40E_PTT_UNUSED_ENTRY(0),
632 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
633 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
634 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
635 I40E_PTT_UNUSED_ENTRY(4),
636 I40E_PTT_UNUSED_ENTRY(5),
637 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
638 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
639 I40E_PTT_UNUSED_ENTRY(8),
640 I40E_PTT_UNUSED_ENTRY(9),
641 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
642 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
643 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
644 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
645 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
646 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
648 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
649 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
650 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
651 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
652 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
654 /* Non Tunneled IPv4 */
655 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
656 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
657 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
658 I40E_PTT_UNUSED_ENTRY(25),
659 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
660 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
661 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
664 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
665 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
666 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
667 I40E_PTT_UNUSED_ENTRY(32),
668 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
669 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
670 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
673 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
674 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
675 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
676 I40E_PTT_UNUSED_ENTRY(39),
677 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
678 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
679 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
681 /* IPv4 --> GRE/NAT */
682 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
684 /* IPv4 --> GRE/NAT --> IPv4 */
685 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
686 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
687 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
688 I40E_PTT_UNUSED_ENTRY(47),
689 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
690 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
691 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
693 /* IPv4 --> GRE/NAT --> IPv6 */
694 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
695 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
696 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
697 I40E_PTT_UNUSED_ENTRY(54),
698 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
699 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
700 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
702 /* IPv4 --> GRE/NAT --> MAC */
703 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
705 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
706 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
707 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
708 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
709 I40E_PTT_UNUSED_ENTRY(62),
710 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
711 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
712 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
714 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
715 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
716 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
717 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
718 I40E_PTT_UNUSED_ENTRY(69),
719 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
720 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
721 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
723 /* IPv4 --> GRE/NAT --> MAC/VLAN */
724 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
726 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
727 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
728 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
729 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
730 I40E_PTT_UNUSED_ENTRY(77),
731 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
732 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
733 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
735 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
736 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
737 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
738 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
739 I40E_PTT_UNUSED_ENTRY(84),
740 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
741 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
742 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
744 /* Non Tunneled IPv6 */
745 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
746 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
747 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
748 I40E_PTT_UNUSED_ENTRY(91),
749 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
750 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
751 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
754 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
755 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
756 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
757 I40E_PTT_UNUSED_ENTRY(98),
758 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
759 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
760 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
763 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
764 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
765 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
766 I40E_PTT_UNUSED_ENTRY(105),
767 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
768 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
769 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
771 /* IPv6 --> GRE/NAT */
772 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
774 /* IPv6 --> GRE/NAT -> IPv4 */
775 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
776 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
777 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
778 I40E_PTT_UNUSED_ENTRY(113),
779 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
780 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
781 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
783 /* IPv6 --> GRE/NAT -> IPv6 */
784 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
785 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
786 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
787 I40E_PTT_UNUSED_ENTRY(120),
788 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
789 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
790 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
792 /* IPv6 --> GRE/NAT -> MAC */
793 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
795 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
796 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
797 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
798 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
799 I40E_PTT_UNUSED_ENTRY(128),
800 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
801 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
802 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
804 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
805 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
806 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
807 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
808 I40E_PTT_UNUSED_ENTRY(135),
809 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
810 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
811 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
813 /* IPv6 --> GRE/NAT -> MAC/VLAN */
814 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
816 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
817 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
818 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
819 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
820 I40E_PTT_UNUSED_ENTRY(143),
821 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
822 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
823 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
825 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
826 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
827 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
828 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
829 I40E_PTT_UNUSED_ENTRY(150),
830 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
831 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
832 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
835 I40E_PTT_UNUSED_ENTRY(154),
836 I40E_PTT_UNUSED_ENTRY(155),
837 I40E_PTT_UNUSED_ENTRY(156),
838 I40E_PTT_UNUSED_ENTRY(157),
839 I40E_PTT_UNUSED_ENTRY(158),
840 I40E_PTT_UNUSED_ENTRY(159),
842 I40E_PTT_UNUSED_ENTRY(160),
843 I40E_PTT_UNUSED_ENTRY(161),
844 I40E_PTT_UNUSED_ENTRY(162),
845 I40E_PTT_UNUSED_ENTRY(163),
846 I40E_PTT_UNUSED_ENTRY(164),
847 I40E_PTT_UNUSED_ENTRY(165),
848 I40E_PTT_UNUSED_ENTRY(166),
849 I40E_PTT_UNUSED_ENTRY(167),
850 I40E_PTT_UNUSED_ENTRY(168),
851 I40E_PTT_UNUSED_ENTRY(169),
853 I40E_PTT_UNUSED_ENTRY(170),
854 I40E_PTT_UNUSED_ENTRY(171),
855 I40E_PTT_UNUSED_ENTRY(172),
856 I40E_PTT_UNUSED_ENTRY(173),
857 I40E_PTT_UNUSED_ENTRY(174),
858 I40E_PTT_UNUSED_ENTRY(175),
859 I40E_PTT_UNUSED_ENTRY(176),
860 I40E_PTT_UNUSED_ENTRY(177),
861 I40E_PTT_UNUSED_ENTRY(178),
862 I40E_PTT_UNUSED_ENTRY(179),
864 I40E_PTT_UNUSED_ENTRY(180),
865 I40E_PTT_UNUSED_ENTRY(181),
866 I40E_PTT_UNUSED_ENTRY(182),
867 I40E_PTT_UNUSED_ENTRY(183),
868 I40E_PTT_UNUSED_ENTRY(184),
869 I40E_PTT_UNUSED_ENTRY(185),
870 I40E_PTT_UNUSED_ENTRY(186),
871 I40E_PTT_UNUSED_ENTRY(187),
872 I40E_PTT_UNUSED_ENTRY(188),
873 I40E_PTT_UNUSED_ENTRY(189),
875 I40E_PTT_UNUSED_ENTRY(190),
876 I40E_PTT_UNUSED_ENTRY(191),
877 I40E_PTT_UNUSED_ENTRY(192),
878 I40E_PTT_UNUSED_ENTRY(193),
879 I40E_PTT_UNUSED_ENTRY(194),
880 I40E_PTT_UNUSED_ENTRY(195),
881 I40E_PTT_UNUSED_ENTRY(196),
882 I40E_PTT_UNUSED_ENTRY(197),
883 I40E_PTT_UNUSED_ENTRY(198),
884 I40E_PTT_UNUSED_ENTRY(199),
886 I40E_PTT_UNUSED_ENTRY(200),
887 I40E_PTT_UNUSED_ENTRY(201),
888 I40E_PTT_UNUSED_ENTRY(202),
889 I40E_PTT_UNUSED_ENTRY(203),
890 I40E_PTT_UNUSED_ENTRY(204),
891 I40E_PTT_UNUSED_ENTRY(205),
892 I40E_PTT_UNUSED_ENTRY(206),
893 I40E_PTT_UNUSED_ENTRY(207),
894 I40E_PTT_UNUSED_ENTRY(208),
895 I40E_PTT_UNUSED_ENTRY(209),
897 I40E_PTT_UNUSED_ENTRY(210),
898 I40E_PTT_UNUSED_ENTRY(211),
899 I40E_PTT_UNUSED_ENTRY(212),
900 I40E_PTT_UNUSED_ENTRY(213),
901 I40E_PTT_UNUSED_ENTRY(214),
902 I40E_PTT_UNUSED_ENTRY(215),
903 I40E_PTT_UNUSED_ENTRY(216),
904 I40E_PTT_UNUSED_ENTRY(217),
905 I40E_PTT_UNUSED_ENTRY(218),
906 I40E_PTT_UNUSED_ENTRY(219),
908 I40E_PTT_UNUSED_ENTRY(220),
909 I40E_PTT_UNUSED_ENTRY(221),
910 I40E_PTT_UNUSED_ENTRY(222),
911 I40E_PTT_UNUSED_ENTRY(223),
912 I40E_PTT_UNUSED_ENTRY(224),
913 I40E_PTT_UNUSED_ENTRY(225),
914 I40E_PTT_UNUSED_ENTRY(226),
915 I40E_PTT_UNUSED_ENTRY(227),
916 I40E_PTT_UNUSED_ENTRY(228),
917 I40E_PTT_UNUSED_ENTRY(229),
919 I40E_PTT_UNUSED_ENTRY(230),
920 I40E_PTT_UNUSED_ENTRY(231),
921 I40E_PTT_UNUSED_ENTRY(232),
922 I40E_PTT_UNUSED_ENTRY(233),
923 I40E_PTT_UNUSED_ENTRY(234),
924 I40E_PTT_UNUSED_ENTRY(235),
925 I40E_PTT_UNUSED_ENTRY(236),
926 I40E_PTT_UNUSED_ENTRY(237),
927 I40E_PTT_UNUSED_ENTRY(238),
928 I40E_PTT_UNUSED_ENTRY(239),
930 I40E_PTT_UNUSED_ENTRY(240),
931 I40E_PTT_UNUSED_ENTRY(241),
932 I40E_PTT_UNUSED_ENTRY(242),
933 I40E_PTT_UNUSED_ENTRY(243),
934 I40E_PTT_UNUSED_ENTRY(244),
935 I40E_PTT_UNUSED_ENTRY(245),
936 I40E_PTT_UNUSED_ENTRY(246),
937 I40E_PTT_UNUSED_ENTRY(247),
938 I40E_PTT_UNUSED_ENTRY(248),
939 I40E_PTT_UNUSED_ENTRY(249),
941 I40E_PTT_UNUSED_ENTRY(250),
942 I40E_PTT_UNUSED_ENTRY(251),
943 I40E_PTT_UNUSED_ENTRY(252),
944 I40E_PTT_UNUSED_ENTRY(253),
945 I40E_PTT_UNUSED_ENTRY(254),
946 I40E_PTT_UNUSED_ENTRY(255)
951 * i40e_validate_mac_addr - Validate unicast MAC address
952 * @mac_addr: pointer to MAC address
954 * Tests a MAC address to ensure it is a valid Individual Address
956 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
958 enum i40e_status_code status = I40E_SUCCESS;
960 DEBUGFUNC("i40e_validate_mac_addr");
962 /* Broadcast addresses ARE multicast addresses
963 * Make sure it is not a multicast address
964 * Reject the zero address
966 if (I40E_IS_MULTICAST(mac_addr) ||
967 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
968 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
969 status = I40E_ERR_INVALID_MAC_ADDR;
976 * i40e_init_shared_code - Initialize the shared code
977 * @hw: pointer to hardware structure
979 * This assigns the MAC type and PHY code and inits the NVM.
980 * Does not touch the hardware. This function must be called prior to any
981 * other function in the shared code. The i40e_hw structure should be
982 * memset to 0 prior to calling this function. The following fields in
983 * hw structure should be filled in prior to calling this function:
984 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
985 * subsystem_vendor_id, and revision_id
987 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
989 enum i40e_status_code status = I40E_SUCCESS;
990 u32 port, ari, func_rid;
992 DEBUGFUNC("i40e_init_shared_code");
994 i40e_set_mac_type(hw);
996 switch (hw->mac.type) {
1001 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1004 hw->phy.get_link_info = true;
1006 /* Determine port number and PF number*/
1007 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1008 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1009 hw->port = (u8)port;
1010 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1011 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1012 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1014 hw->pf_id = (u8)(func_rid & 0xff);
1016 hw->pf_id = (u8)(func_rid & 0x7);
1018 if (hw->mac.type == I40E_MAC_X722)
1019 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1020 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1021 /* NVMUpdate features structure initialization */
1022 hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1023 hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1024 hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1025 i40e_memset(hw->nvmupd_features.features, 0x0,
1026 I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1027 sizeof(*hw->nvmupd_features.features),
1030 /* No features supported at the moment */
1031 hw->nvmupd_features.features[0] = 0;
1033 status = i40e_init_nvm(hw);
1038 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1039 * @hw: pointer to the hw struct
1040 * @flags: a return indicator of what addresses were added to the addr store
1041 * @addrs: the requestor's mac addr store
1042 * @cmd_details: pointer to command details structure or NULL
1044 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1046 struct i40e_aqc_mac_address_read_data *addrs,
1047 struct i40e_asq_cmd_details *cmd_details)
1049 struct i40e_aq_desc desc;
1050 struct i40e_aqc_mac_address_read *cmd_data =
1051 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1052 enum i40e_status_code status;
1054 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1055 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1057 status = i40e_asq_send_command(hw, &desc, addrs,
1058 sizeof(*addrs), cmd_details);
1059 *flags = LE16_TO_CPU(cmd_data->command_flags);
1065 * i40e_aq_mac_address_write - Change the MAC addresses
1066 * @hw: pointer to the hw struct
1067 * @flags: indicates which MAC to be written
1068 * @mac_addr: address to write
1069 * @cmd_details: pointer to command details structure or NULL
1071 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1072 u16 flags, u8 *mac_addr,
1073 struct i40e_asq_cmd_details *cmd_details)
1075 struct i40e_aq_desc desc;
1076 struct i40e_aqc_mac_address_write *cmd_data =
1077 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1078 enum i40e_status_code status;
1080 i40e_fill_default_direct_cmd_desc(&desc,
1081 i40e_aqc_opc_mac_address_write);
1082 cmd_data->command_flags = CPU_TO_LE16(flags);
1083 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1084 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1085 ((u32)mac_addr[3] << 16) |
1086 ((u32)mac_addr[4] << 8) |
1089 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1095 * i40e_get_mac_addr - get MAC address
1096 * @hw: pointer to the HW structure
1097 * @mac_addr: pointer to MAC address
1099 * Reads the adapter's MAC address from register
1101 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1103 struct i40e_aqc_mac_address_read_data addrs;
1104 enum i40e_status_code status;
1107 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1109 if (flags & I40E_AQC_LAN_ADDR_VALID)
1110 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1111 I40E_NONDMA_TO_NONDMA);
1117 * i40e_get_port_mac_addr - get Port MAC address
1118 * @hw: pointer to the HW structure
1119 * @mac_addr: pointer to Port MAC address
1121 * Reads the adapter's Port MAC address
1123 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1125 struct i40e_aqc_mac_address_read_data addrs;
1126 enum i40e_status_code status;
1129 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1133 if (flags & I40E_AQC_PORT_ADDR_VALID)
1134 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1135 I40E_NONDMA_TO_NONDMA);
1137 status = I40E_ERR_INVALID_MAC_ADDR;
1143 * i40e_pre_tx_queue_cfg - pre tx queue configure
1144 * @hw: pointer to the HW structure
1145 * @queue: target pf queue index
1146 * @enable: state change request
1148 * Handles hw requirement to indicate intention to enable
1149 * or disable target queue.
1151 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1153 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1157 if (abs_queue_idx >= 128) {
1158 reg_block = abs_queue_idx / 128;
1159 abs_queue_idx %= 128;
1162 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1163 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1164 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1167 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1169 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1171 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1175 * i40e_get_san_mac_addr - get SAN MAC address
1176 * @hw: pointer to the HW structure
1177 * @mac_addr: pointer to SAN MAC address
1179 * Reads the adapter's SAN MAC address from NVM
1181 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1184 struct i40e_aqc_mac_address_read_data addrs;
1185 enum i40e_status_code status;
1188 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1192 if (flags & I40E_AQC_SAN_ADDR_VALID)
1193 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1194 I40E_NONDMA_TO_NONDMA);
1196 status = I40E_ERR_INVALID_MAC_ADDR;
1202 * i40e_read_pba_string - Reads part number string from EEPROM
1203 * @hw: pointer to hardware structure
1204 * @pba_num: stores the part number string from the EEPROM
1205 * @pba_num_size: part number string buffer length
1207 * Reads the part number string from the EEPROM.
1209 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1212 enum i40e_status_code status = I40E_SUCCESS;
1218 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1219 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1220 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1224 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1225 if (status != I40E_SUCCESS) {
1226 DEBUGOUT("Failed to read PBA Block pointer.\n");
1230 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1231 if (status != I40E_SUCCESS) {
1232 DEBUGOUT("Failed to read PBA Block size.\n");
1236 /* Subtract one to get PBA word count (PBA Size word is included in
1240 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1241 DEBUGOUT("Buffer to small for PBA data.\n");
1242 return I40E_ERR_PARAM;
1245 for (i = 0; i < pba_size; i++) {
1246 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1247 if (status != I40E_SUCCESS) {
1248 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1252 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1253 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1255 pba_num[(pba_size * 2)] = '\0';
1261 * i40e_get_media_type - Gets media type
1262 * @hw: pointer to the hardware structure
1264 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1266 enum i40e_media_type media;
1268 switch (hw->phy.link_info.phy_type) {
1269 case I40E_PHY_TYPE_10GBASE_SR:
1270 case I40E_PHY_TYPE_10GBASE_LR:
1271 case I40E_PHY_TYPE_1000BASE_SX:
1272 case I40E_PHY_TYPE_1000BASE_LX:
1273 case I40E_PHY_TYPE_40GBASE_SR4:
1274 case I40E_PHY_TYPE_40GBASE_LR4:
1275 case I40E_PHY_TYPE_25GBASE_LR:
1276 case I40E_PHY_TYPE_25GBASE_SR:
1277 media = I40E_MEDIA_TYPE_FIBER;
1279 case I40E_PHY_TYPE_100BASE_TX:
1280 case I40E_PHY_TYPE_1000BASE_T:
1281 case I40E_PHY_TYPE_2_5GBASE_T:
1282 case I40E_PHY_TYPE_5GBASE_T:
1283 case I40E_PHY_TYPE_10GBASE_T:
1284 media = I40E_MEDIA_TYPE_BASET;
1286 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1287 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1288 case I40E_PHY_TYPE_10GBASE_CR1:
1289 case I40E_PHY_TYPE_40GBASE_CR4:
1290 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1291 case I40E_PHY_TYPE_40GBASE_AOC:
1292 case I40E_PHY_TYPE_10GBASE_AOC:
1293 case I40E_PHY_TYPE_25GBASE_CR:
1294 case I40E_PHY_TYPE_25GBASE_AOC:
1295 case I40E_PHY_TYPE_25GBASE_ACC:
1296 media = I40E_MEDIA_TYPE_DA;
1298 case I40E_PHY_TYPE_1000BASE_KX:
1299 case I40E_PHY_TYPE_10GBASE_KX4:
1300 case I40E_PHY_TYPE_10GBASE_KR:
1301 case I40E_PHY_TYPE_40GBASE_KR4:
1302 case I40E_PHY_TYPE_20GBASE_KR2:
1303 case I40E_PHY_TYPE_25GBASE_KR:
1304 media = I40E_MEDIA_TYPE_BACKPLANE;
1306 case I40E_PHY_TYPE_SGMII:
1307 case I40E_PHY_TYPE_XAUI:
1308 case I40E_PHY_TYPE_XFI:
1309 case I40E_PHY_TYPE_XLAUI:
1310 case I40E_PHY_TYPE_XLPPI:
1312 media = I40E_MEDIA_TYPE_UNKNOWN;
1320 * i40e_poll_globr - Poll for Global Reset completion
1321 * @hw: pointer to the hardware structure
1322 * @retry_limit: how many times to retry before failure
1324 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1329 for (cnt = 0; cnt < retry_limit; cnt++) {
1330 reg = rd32(hw, I40E_GLGEN_RSTAT);
1331 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1332 return I40E_SUCCESS;
1333 i40e_msec_delay(100);
1336 DEBUGOUT("Global reset failed.\n");
1337 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1339 return I40E_ERR_RESET_FAILED;
1342 #define I40E_PF_RESET_WAIT_COUNT 200
1344 * i40e_pf_reset - Reset the PF
1345 * @hw: pointer to the hardware structure
1347 * Assuming someone else has triggered a global reset,
1348 * assure the global reset is complete and then reset the PF
1350 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1357 /* Poll for Global Reset steady state in case of recent GRST.
1358 * The grst delay value is in 100ms units, and we'll wait a
1359 * couple counts longer to be sure we don't just miss the end.
1361 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1362 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1363 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1365 grst_del = min(grst_del * 20, 160U);
1367 for (cnt = 0; cnt < grst_del; cnt++) {
1368 reg = rd32(hw, I40E_GLGEN_RSTAT);
1369 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1371 i40e_msec_delay(100);
1373 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1374 DEBUGOUT("Global reset polling failed to complete.\n");
1375 return I40E_ERR_RESET_FAILED;
1378 /* Now Wait for the FW to be ready */
1379 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1380 reg = rd32(hw, I40E_GLNVM_ULD);
1381 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1383 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1384 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1385 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1388 i40e_msec_delay(10);
1390 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1391 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1392 DEBUGOUT("wait for FW Reset complete timedout\n");
1393 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1394 return I40E_ERR_RESET_FAILED;
1397 /* If there was a Global Reset in progress when we got here,
1398 * we don't need to do the PF Reset
1403 reg = rd32(hw, I40E_PFGEN_CTRL);
1404 wr32(hw, I40E_PFGEN_CTRL,
1405 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1406 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1407 reg = rd32(hw, I40E_PFGEN_CTRL);
1408 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1410 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1411 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1415 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1416 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1417 return I40E_ERR_RESET_FAILED;
1418 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1419 DEBUGOUT("PF reset polling failed to complete.\n");
1420 return I40E_ERR_RESET_FAILED;
1424 i40e_clear_pxe_mode(hw);
1427 return I40E_SUCCESS;
1431 * i40e_clear_hw - clear out any left over hw state
1432 * @hw: pointer to the hw struct
1434 * Clear queues and interrupts, typically called at init time,
1435 * but after the capabilities have been found so we know how many
1436 * queues and msix vectors have been allocated.
1438 void i40e_clear_hw(struct i40e_hw *hw)
1440 u32 num_queues, base_queue;
1448 /* get number of interrupts, queues, and vfs */
1449 val = rd32(hw, I40E_GLPCI_CNF2);
1450 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1451 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1452 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1453 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1455 val = rd32(hw, I40E_PFLAN_QALLOC);
1456 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1457 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1458 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1459 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1460 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1461 num_queues = (j - base_queue) + 1;
1465 val = rd32(hw, I40E_PF_VT_PFALLOC);
1466 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1467 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1468 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1469 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1470 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1471 num_vfs = (j - i) + 1;
1475 /* stop all the interrupts */
1476 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1477 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1478 for (i = 0; i < num_pf_int - 2; i++)
1479 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1481 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1482 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1483 wr32(hw, I40E_PFINT_LNKLST0, val);
1484 for (i = 0; i < num_pf_int - 2; i++)
1485 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1486 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1487 for (i = 0; i < num_vfs; i++)
1488 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1489 for (i = 0; i < num_vf_int - 2; i++)
1490 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1492 /* warn the HW of the coming Tx disables */
1493 for (i = 0; i < num_queues; i++) {
1494 u32 abs_queue_idx = base_queue + i;
1497 if (abs_queue_idx >= 128) {
1498 reg_block = abs_queue_idx / 128;
1499 abs_queue_idx %= 128;
1502 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1503 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1504 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1505 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1507 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1509 i40e_usec_delay(400);
1511 /* stop all the queues */
1512 for (i = 0; i < num_queues; i++) {
1513 wr32(hw, I40E_QINT_TQCTL(i), 0);
1514 wr32(hw, I40E_QTX_ENA(i), 0);
1515 wr32(hw, I40E_QINT_RQCTL(i), 0);
1516 wr32(hw, I40E_QRX_ENA(i), 0);
1519 /* short wait for all queue disables to settle */
1520 i40e_usec_delay(50);
1524 * i40e_clear_pxe_mode - clear pxe operations mode
1525 * @hw: pointer to the hw struct
1527 * Make sure all PXE mode settings are cleared, including things
1528 * like descriptor fetch/write-back mode.
1530 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1532 if (i40e_check_asq_alive(hw))
1533 i40e_aq_clear_pxe_mode(hw, NULL);
1537 * i40e_led_is_mine - helper to find matching led
1538 * @hw: pointer to the hw struct
1539 * @idx: index into GPIO registers
1541 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1543 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1548 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1549 !hw->func_caps.led[idx])
1551 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1552 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1553 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1555 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1556 * if it is not our port then ignore
1558 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1565 #define I40E_COMBINED_ACTIVITY 0xA
1566 #define I40E_FILTER_ACTIVITY 0xE
1567 #define I40E_LINK_ACTIVITY 0xC
1568 #define I40E_MAC_ACTIVITY 0xD
1569 #define I40E_FW_LED BIT(4)
1570 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1571 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1573 #define I40E_LED0 22
1575 #define I40E_PIN_FUNC_SDP 0x0
1576 #define I40E_PIN_FUNC_LED 0x1
1579 * i40e_led_get - return current on/off mode
1580 * @hw: pointer to the hw struct
1582 * The value returned is the 'mode' field as defined in the
1583 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1584 * values are variations of possible behaviors relating to
1585 * blink, link, and wire.
1587 u32 i40e_led_get(struct i40e_hw *hw)
1589 u32 current_mode = 0;
1593 /* as per the documentation GPIO 22-29 are the LED
1594 * GPIO pins named LED0..LED7
1596 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1597 u32 gpio_val = i40e_led_is_mine(hw, i);
1602 /* ignore gpio LED src mode entries related to the activity
1605 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1606 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1607 switch (current_mode) {
1608 case I40E_COMBINED_ACTIVITY:
1609 case I40E_FILTER_ACTIVITY:
1610 case I40E_MAC_ACTIVITY:
1611 case I40E_LINK_ACTIVITY:
1617 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1618 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1626 * i40e_led_set - set new on/off mode
1627 * @hw: pointer to the hw struct
1628 * @mode: 0=off, 0xf=on (else see manual for mode details)
1629 * @blink: true if the LED should blink when on, false if steady
1631 * if this function is used to turn on the blink it should
1632 * be used to disable the blink when restoring the original state.
1634 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1636 u32 current_mode = 0;
1639 if (mode & ~I40E_LED_MODE_VALID) {
1640 DEBUGOUT1("invalid mode passed in %X\n", mode);
1644 /* as per the documentation GPIO 22-29 are the LED
1645 * GPIO pins named LED0..LED7
1647 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1648 u32 gpio_val = i40e_led_is_mine(hw, i);
1653 /* ignore gpio LED src mode entries related to the activity
1656 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1657 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1658 switch (current_mode) {
1659 case I40E_COMBINED_ACTIVITY:
1660 case I40E_FILTER_ACTIVITY:
1661 case I40E_MAC_ACTIVITY:
1662 case I40E_LINK_ACTIVITY:
1668 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1671 if (mode & I40E_FW_LED)
1672 pin_func = I40E_PIN_FUNC_SDP;
1674 pin_func = I40E_PIN_FUNC_LED;
1676 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1677 gpio_val |= ((pin_func <<
1678 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1679 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1681 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1682 /* this & is a bit of paranoia, but serves as a range check */
1683 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1684 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1687 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1689 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1691 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1696 /* Admin command wrappers */
1699 * i40e_aq_get_phy_capabilities
1700 * @hw: pointer to the hw struct
1701 * @abilities: structure for PHY capabilities to be filled
1702 * @qualified_modules: report Qualified Modules
1703 * @report_init: report init capabilities (active are default)
1704 * @cmd_details: pointer to command details structure or NULL
1706 * Returns the various PHY abilities supported on the Port.
1708 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1709 bool qualified_modules, bool report_init,
1710 struct i40e_aq_get_phy_abilities_resp *abilities,
1711 struct i40e_asq_cmd_details *cmd_details)
1713 struct i40e_aq_desc desc;
1714 enum i40e_status_code status;
1715 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1716 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1719 return I40E_ERR_PARAM;
1722 i40e_fill_default_direct_cmd_desc(&desc,
1723 i40e_aqc_opc_get_phy_abilities);
1725 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1726 if (abilities_size > I40E_AQ_LARGE_BUF)
1727 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1729 if (qualified_modules)
1730 desc.params.external.param0 |=
1731 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1734 desc.params.external.param0 |=
1735 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1737 status = i40e_asq_send_command(hw, &desc, abilities,
1738 abilities_size, cmd_details);
1740 switch (hw->aq.asq_last_status) {
1741 case I40E_AQ_RC_EIO:
1742 status = I40E_ERR_UNKNOWN_PHY;
1744 case I40E_AQ_RC_EAGAIN:
1747 status = I40E_ERR_TIMEOUT;
1749 /* also covers I40E_AQ_RC_OK */
1754 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1755 (total_delay < max_delay));
1757 if (status != I40E_SUCCESS)
1761 if (hw->mac.type == I40E_MAC_XL710 &&
1762 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1763 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1764 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1766 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1767 hw->phy.phy_types |=
1768 ((u64)abilities->phy_type_ext << 32);
1776 * i40e_aq_set_phy_config
1777 * @hw: pointer to the hw struct
1778 * @config: structure with PHY configuration to be set
1779 * @cmd_details: pointer to command details structure or NULL
1781 * Set the various PHY configuration parameters
1782 * supported on the Port.One or more of the Set PHY config parameters may be
1783 * ignored in an MFP mode as the PF may not have the privilege to set some
1784 * of the PHY Config parameters. This status will be indicated by the
1787 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1788 struct i40e_aq_set_phy_config *config,
1789 struct i40e_asq_cmd_details *cmd_details)
1791 struct i40e_aq_desc desc;
1792 struct i40e_aq_set_phy_config *cmd =
1793 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1794 enum i40e_status_code status;
1797 return I40E_ERR_PARAM;
1799 i40e_fill_default_direct_cmd_desc(&desc,
1800 i40e_aqc_opc_set_phy_config);
1804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1811 * @hw: pointer to the hw struct
1812 * @aq_failures: buffer to return AdminQ failure information
1813 * @atomic_restart: whether to enable atomic link restart
1815 * Set the requested flow control mode using set_phy_config.
1817 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1818 bool atomic_restart)
1820 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1821 struct i40e_aq_get_phy_abilities_resp abilities;
1822 struct i40e_aq_set_phy_config config;
1823 enum i40e_status_code status;
1824 u8 pause_mask = 0x0;
1830 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1831 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1833 case I40E_FC_RX_PAUSE:
1834 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1836 case I40E_FC_TX_PAUSE:
1837 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1843 /* Get the current phy config */
1844 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1847 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1851 memset(&config, 0, sizeof(config));
1852 /* clear the old pause settings */
1853 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1854 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1855 /* set the new abilities */
1856 config.abilities |= pause_mask;
1857 /* If the abilities have changed, then set the new config */
1858 if (config.abilities != abilities.abilities) {
1859 /* Auto restart link so settings take effect */
1861 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1862 /* Copy over all the old settings */
1863 config.phy_type = abilities.phy_type;
1864 config.phy_type_ext = abilities.phy_type_ext;
1865 config.link_speed = abilities.link_speed;
1866 config.eee_capability = abilities.eee_capability;
1867 config.eeer = abilities.eeer_val;
1868 config.low_power_ctrl = abilities.d3_lpan;
1869 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1870 I40E_AQ_PHY_FEC_CONFIG_MASK;
1871 status = i40e_aq_set_phy_config(hw, &config, NULL);
1874 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1876 /* Update the link info */
1877 status = i40e_update_link_info(hw);
1879 /* Wait a little bit (on 40G cards it sometimes takes a really
1880 * long time for link to come back from the atomic reset)
1883 i40e_msec_delay(1000);
1884 status = i40e_update_link_info(hw);
1887 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1893 * i40e_aq_set_mac_config
1894 * @hw: pointer to the hw struct
1895 * @max_frame_size: Maximum Frame Size to be supported by the port
1896 * @crc_en: Tell HW to append a CRC to outgoing frames
1897 * @pacing: Pacing configurations
1898 * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1899 * @cmd_details: pointer to command details structure or NULL
1901 * Configure MAC settings for frame size, jumbo frame support and the
1902 * addition of a CRC by the hardware.
1904 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1906 bool crc_en, u16 pacing,
1907 bool auto_drop_blocking_packets,
1908 struct i40e_asq_cmd_details *cmd_details)
1910 struct i40e_aq_desc desc;
1911 struct i40e_aq_set_mac_config *cmd =
1912 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1913 enum i40e_status_code status;
1915 if (max_frame_size == 0)
1916 return I40E_ERR_PARAM;
1918 i40e_fill_default_direct_cmd_desc(&desc,
1919 i40e_aqc_opc_set_mac_config);
1921 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1922 cmd->params = ((u8)pacing & 0x0F) << 3;
1924 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1926 if (auto_drop_blocking_packets) {
1927 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1929 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1931 i40e_debug(hw, I40E_DEBUG_ALL,
1932 "This FW api version does not support drop mode.\n");
1935 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
1936 cmd->fc_refresh_threshold =
1937 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1939 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1945 * i40e_aq_clear_pxe_mode
1946 * @hw: pointer to the hw struct
1947 * @cmd_details: pointer to command details structure or NULL
1949 * Tell the firmware that the driver is taking over from PXE
1951 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1952 struct i40e_asq_cmd_details *cmd_details)
1954 enum i40e_status_code status;
1955 struct i40e_aq_desc desc;
1956 struct i40e_aqc_clear_pxe *cmd =
1957 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1959 i40e_fill_default_direct_cmd_desc(&desc,
1960 i40e_aqc_opc_clear_pxe_mode);
1964 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1966 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1972 * i40e_aq_set_link_restart_an
1973 * @hw: pointer to the hw struct
1974 * @enable_link: if true: enable link, if false: disable link
1975 * @cmd_details: pointer to command details structure or NULL
1977 * Sets up the link and restarts the Auto-Negotiation over the link.
1979 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1980 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1982 struct i40e_aq_desc desc;
1983 struct i40e_aqc_set_link_restart_an *cmd =
1984 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1985 enum i40e_status_code status;
1987 i40e_fill_default_direct_cmd_desc(&desc,
1988 i40e_aqc_opc_set_link_restart_an);
1990 cmd->command = I40E_AQ_PHY_RESTART_AN;
1992 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1994 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1996 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2002 * i40e_aq_get_link_info
2003 * @hw: pointer to the hw struct
2004 * @enable_lse: enable/disable LinkStatusEvent reporting
2005 * @link: pointer to link status structure - optional
2006 * @cmd_details: pointer to command details structure or NULL
2008 * Returns the link status of the adapter.
2010 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
2011 bool enable_lse, struct i40e_link_status *link,
2012 struct i40e_asq_cmd_details *cmd_details)
2014 struct i40e_aq_desc desc;
2015 struct i40e_aqc_get_link_status *resp =
2016 (struct i40e_aqc_get_link_status *)&desc.params.raw;
2017 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
2018 enum i40e_status_code status;
2019 bool tx_pause, rx_pause;
2022 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2025 command_flags = I40E_AQ_LSE_ENABLE;
2027 command_flags = I40E_AQ_LSE_DISABLE;
2028 resp->command_flags = CPU_TO_LE16(command_flags);
2030 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2032 if (status != I40E_SUCCESS)
2033 goto aq_get_link_info_exit;
2035 /* save off old link status information */
2036 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2037 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2039 /* update link status */
2040 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2041 hw->phy.media_type = i40e_get_media_type(hw);
2042 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2043 hw_link_info->link_info = resp->link_info;
2044 hw_link_info->an_info = resp->an_info;
2045 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2046 I40E_AQ_CONFIG_FEC_RS_ENA);
2047 hw_link_info->ext_info = resp->ext_info;
2048 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2049 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2050 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2052 /* update fc info */
2053 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2054 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2055 if (tx_pause & rx_pause)
2056 hw->fc.current_mode = I40E_FC_FULL;
2058 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2060 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2062 hw->fc.current_mode = I40E_FC_NONE;
2064 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2065 hw_link_info->crc_enable = true;
2067 hw_link_info->crc_enable = false;
2069 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2070 hw_link_info->lse_enable = true;
2072 hw_link_info->lse_enable = false;
2074 if ((hw->mac.type == I40E_MAC_XL710) &&
2075 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2076 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2077 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2079 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2080 hw->mac.type != I40E_MAC_X722) {
2083 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2084 I40E_NONDMA_TO_NONDMA);
2085 hw->phy.phy_types = LE32_TO_CPU(tmp);
2086 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2089 /* save link status information */
2091 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2092 I40E_NONDMA_TO_NONDMA);
2094 /* flag cleared so helper functions don't call AQ again */
2095 hw->phy.get_link_info = false;
2097 aq_get_link_info_exit:
2102 * i40e_aq_set_phy_int_mask
2103 * @hw: pointer to the hw struct
2104 * @mask: interrupt mask to be set
2105 * @cmd_details: pointer to command details structure or NULL
2107 * Set link interrupt mask.
2109 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2111 struct i40e_asq_cmd_details *cmd_details)
2113 struct i40e_aq_desc desc;
2114 struct i40e_aqc_set_phy_int_mask *cmd =
2115 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2116 enum i40e_status_code status;
2118 i40e_fill_default_direct_cmd_desc(&desc,
2119 i40e_aqc_opc_set_phy_int_mask);
2121 cmd->event_mask = CPU_TO_LE16(mask);
2123 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2129 * i40e_aq_get_local_advt_reg
2130 * @hw: pointer to the hw struct
2131 * @advt_reg: local AN advertisement register value
2132 * @cmd_details: pointer to command details structure or NULL
2134 * Get the Local AN advertisement register value.
2136 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2138 struct i40e_asq_cmd_details *cmd_details)
2140 struct i40e_aq_desc desc;
2141 struct i40e_aqc_an_advt_reg *resp =
2142 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2143 enum i40e_status_code status;
2145 i40e_fill_default_direct_cmd_desc(&desc,
2146 i40e_aqc_opc_get_local_advt_reg);
2148 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2150 if (status != I40E_SUCCESS)
2151 goto aq_get_local_advt_reg_exit;
2153 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2154 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2156 aq_get_local_advt_reg_exit:
2161 * i40e_aq_set_local_advt_reg
2162 * @hw: pointer to the hw struct
2163 * @advt_reg: local AN advertisement register value
2164 * @cmd_details: pointer to command details structure or NULL
2166 * Get the Local AN advertisement register value.
2168 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2170 struct i40e_asq_cmd_details *cmd_details)
2172 struct i40e_aq_desc desc;
2173 struct i40e_aqc_an_advt_reg *cmd =
2174 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2175 enum i40e_status_code status;
2177 i40e_fill_default_direct_cmd_desc(&desc,
2178 i40e_aqc_opc_get_local_advt_reg);
2180 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2181 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2183 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2189 * i40e_aq_get_partner_advt
2190 * @hw: pointer to the hw struct
2191 * @advt_reg: AN partner advertisement register value
2192 * @cmd_details: pointer to command details structure or NULL
2194 * Get the link partner AN advertisement register value.
2196 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2198 struct i40e_asq_cmd_details *cmd_details)
2200 struct i40e_aq_desc desc;
2201 struct i40e_aqc_an_advt_reg *resp =
2202 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2203 enum i40e_status_code status;
2205 i40e_fill_default_direct_cmd_desc(&desc,
2206 i40e_aqc_opc_get_partner_advt);
2208 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2210 if (status != I40E_SUCCESS)
2211 goto aq_get_partner_advt_exit;
2213 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2214 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2216 aq_get_partner_advt_exit:
2221 * i40e_aq_set_lb_modes
2222 * @hw: pointer to the hw struct
2223 * @lb_modes: loopback mode to be set
2224 * @cmd_details: pointer to command details structure or NULL
2226 * Sets loopback modes.
2228 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2230 struct i40e_asq_cmd_details *cmd_details)
2232 struct i40e_aq_desc desc;
2233 struct i40e_aqc_set_lb_mode *cmd =
2234 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2235 enum i40e_status_code status;
2237 i40e_fill_default_direct_cmd_desc(&desc,
2238 i40e_aqc_opc_set_lb_modes);
2240 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2242 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2248 * i40e_aq_set_phy_debug
2249 * @hw: pointer to the hw struct
2250 * @cmd_flags: debug command flags
2251 * @cmd_details: pointer to command details structure or NULL
2253 * Reset the external PHY.
2255 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2256 struct i40e_asq_cmd_details *cmd_details)
2258 struct i40e_aq_desc desc;
2259 struct i40e_aqc_set_phy_debug *cmd =
2260 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2261 enum i40e_status_code status;
2263 i40e_fill_default_direct_cmd_desc(&desc,
2264 i40e_aqc_opc_set_phy_debug);
2266 cmd->command_flags = cmd_flags;
2268 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2275 * @hw: pointer to the hw struct
2276 * @vsi_ctx: pointer to a vsi context struct
2277 * @cmd_details: pointer to command details structure or NULL
2279 * Add a VSI context to the hardware.
2281 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2282 struct i40e_vsi_context *vsi_ctx,
2283 struct i40e_asq_cmd_details *cmd_details)
2285 struct i40e_aq_desc desc;
2286 struct i40e_aqc_add_get_update_vsi *cmd =
2287 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2288 struct i40e_aqc_add_get_update_vsi_completion *resp =
2289 (struct i40e_aqc_add_get_update_vsi_completion *)
2291 enum i40e_status_code status;
2293 i40e_fill_default_direct_cmd_desc(&desc,
2294 i40e_aqc_opc_add_vsi);
2296 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2297 cmd->connection_type = vsi_ctx->connection_type;
2298 cmd->vf_id = vsi_ctx->vf_num;
2299 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2301 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2303 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2304 sizeof(vsi_ctx->info), cmd_details);
2306 if (status != I40E_SUCCESS)
2307 goto aq_add_vsi_exit;
2309 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2310 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2311 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2312 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2319 * i40e_aq_set_default_vsi
2320 * @hw: pointer to the hw struct
2322 * @cmd_details: pointer to command details structure or NULL
2324 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2326 struct i40e_asq_cmd_details *cmd_details)
2328 struct i40e_aq_desc desc;
2329 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2330 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2332 enum i40e_status_code status;
2334 i40e_fill_default_direct_cmd_desc(&desc,
2335 i40e_aqc_opc_set_vsi_promiscuous_modes);
2337 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2338 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2339 cmd->seid = CPU_TO_LE16(seid);
2341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2347 * i40e_aq_clear_default_vsi
2348 * @hw: pointer to the hw struct
2350 * @cmd_details: pointer to command details structure or NULL
2352 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2354 struct i40e_asq_cmd_details *cmd_details)
2356 struct i40e_aq_desc desc;
2357 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2358 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2360 enum i40e_status_code status;
2362 i40e_fill_default_direct_cmd_desc(&desc,
2363 i40e_aqc_opc_set_vsi_promiscuous_modes);
2365 cmd->promiscuous_flags = CPU_TO_LE16(0);
2366 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2367 cmd->seid = CPU_TO_LE16(seid);
2369 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2375 * i40e_aq_set_vsi_unicast_promiscuous
2376 * @hw: pointer to the hw struct
2378 * @set: set unicast promiscuous enable/disable
2379 * @cmd_details: pointer to command details structure or NULL
2380 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2382 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2384 struct i40e_asq_cmd_details *cmd_details,
2385 bool rx_only_promisc)
2387 struct i40e_aq_desc desc;
2388 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2389 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2390 enum i40e_status_code status;
2393 i40e_fill_default_direct_cmd_desc(&desc,
2394 i40e_aqc_opc_set_vsi_promiscuous_modes);
2397 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2398 if (rx_only_promisc &&
2399 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2400 (hw->aq.api_maj_ver > 1)))
2401 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2404 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2406 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2407 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2408 (hw->aq.api_maj_ver > 1))
2409 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2411 cmd->seid = CPU_TO_LE16(seid);
2412 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2418 * i40e_aq_set_vsi_multicast_promiscuous
2419 * @hw: pointer to the hw struct
2421 * @set: set multicast promiscuous enable/disable
2422 * @cmd_details: pointer to command details structure or NULL
2424 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2425 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2427 struct i40e_aq_desc desc;
2428 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2429 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2430 enum i40e_status_code status;
2433 i40e_fill_default_direct_cmd_desc(&desc,
2434 i40e_aqc_opc_set_vsi_promiscuous_modes);
2437 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2439 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2441 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2443 cmd->seid = CPU_TO_LE16(seid);
2444 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2450 * i40e_aq_set_vsi_full_promiscuous
2451 * @hw: pointer to the hw struct
2453 * @set: set promiscuous enable/disable
2454 * @cmd_details: pointer to command details structure or NULL
2456 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2458 struct i40e_asq_cmd_details *cmd_details)
2460 struct i40e_aq_desc desc;
2461 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2462 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2463 enum i40e_status_code status;
2466 i40e_fill_default_direct_cmd_desc(&desc,
2467 i40e_aqc_opc_set_vsi_promiscuous_modes);
2470 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2471 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2472 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2474 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2476 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2477 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2478 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2480 cmd->seid = CPU_TO_LE16(seid);
2481 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2487 * i40e_aq_set_vsi_mc_promisc_on_vlan
2488 * @hw: pointer to the hw struct
2490 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2491 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2492 * @cmd_details: pointer to command details structure or NULL
2494 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2495 u16 seid, bool enable, u16 vid,
2496 struct i40e_asq_cmd_details *cmd_details)
2498 struct i40e_aq_desc desc;
2499 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2500 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2501 enum i40e_status_code status;
2504 i40e_fill_default_direct_cmd_desc(&desc,
2505 i40e_aqc_opc_set_vsi_promiscuous_modes);
2508 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2510 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2511 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2512 cmd->seid = CPU_TO_LE16(seid);
2513 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2515 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2521 * i40e_aq_set_vsi_uc_promisc_on_vlan
2522 * @hw: pointer to the hw struct
2524 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2525 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2526 * @cmd_details: pointer to command details structure or NULL
2528 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2529 u16 seid, bool enable, u16 vid,
2530 struct i40e_asq_cmd_details *cmd_details)
2532 struct i40e_aq_desc desc;
2533 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2534 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2535 enum i40e_status_code status;
2538 i40e_fill_default_direct_cmd_desc(&desc,
2539 i40e_aqc_opc_set_vsi_promiscuous_modes);
2542 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2544 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2545 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2546 cmd->seid = CPU_TO_LE16(seid);
2547 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2549 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2555 * i40e_aq_set_vsi_bc_promisc_on_vlan
2556 * @hw: pointer to the hw struct
2558 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2559 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2560 * @cmd_details: pointer to command details structure or NULL
2562 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2563 u16 seid, bool enable, u16 vid,
2564 struct i40e_asq_cmd_details *cmd_details)
2566 struct i40e_aq_desc desc;
2567 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2568 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2569 enum i40e_status_code status;
2572 i40e_fill_default_direct_cmd_desc(&desc,
2573 i40e_aqc_opc_set_vsi_promiscuous_modes);
2576 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2578 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2579 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2580 cmd->seid = CPU_TO_LE16(seid);
2581 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2583 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2589 * i40e_aq_set_vsi_broadcast
2590 * @hw: pointer to the hw struct
2592 * @set_filter: true to set filter, false to clear filter
2593 * @cmd_details: pointer to command details structure or NULL
2595 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2597 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2598 u16 seid, bool set_filter,
2599 struct i40e_asq_cmd_details *cmd_details)
2601 struct i40e_aq_desc desc;
2602 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2603 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2604 enum i40e_status_code status;
2606 i40e_fill_default_direct_cmd_desc(&desc,
2607 i40e_aqc_opc_set_vsi_promiscuous_modes);
2610 cmd->promiscuous_flags
2611 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2613 cmd->promiscuous_flags
2614 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2616 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2617 cmd->seid = CPU_TO_LE16(seid);
2618 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2624 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2625 * @hw: pointer to the hw struct
2627 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2628 * @cmd_details: pointer to command details structure or NULL
2630 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2631 u16 seid, bool enable,
2632 struct i40e_asq_cmd_details *cmd_details)
2634 struct i40e_aq_desc desc;
2635 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2636 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2637 enum i40e_status_code status;
2640 i40e_fill_default_direct_cmd_desc(&desc,
2641 i40e_aqc_opc_set_vsi_promiscuous_modes);
2643 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2645 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2646 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2647 cmd->seid = CPU_TO_LE16(seid);
2649 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2655 * i40e_get_vsi_params - get VSI configuration info
2656 * @hw: pointer to the hw struct
2657 * @vsi_ctx: pointer to a vsi context struct
2658 * @cmd_details: pointer to command details structure or NULL
2660 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2661 struct i40e_vsi_context *vsi_ctx,
2662 struct i40e_asq_cmd_details *cmd_details)
2664 struct i40e_aq_desc desc;
2665 struct i40e_aqc_add_get_update_vsi *cmd =
2666 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2667 struct i40e_aqc_add_get_update_vsi_completion *resp =
2668 (struct i40e_aqc_add_get_update_vsi_completion *)
2670 enum i40e_status_code status;
2672 UNREFERENCED_1PARAMETER(cmd_details);
2673 i40e_fill_default_direct_cmd_desc(&desc,
2674 i40e_aqc_opc_get_vsi_parameters);
2676 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2678 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2680 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2681 sizeof(vsi_ctx->info), NULL);
2683 if (status != I40E_SUCCESS)
2684 goto aq_get_vsi_params_exit;
2686 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2687 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2688 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2689 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2691 aq_get_vsi_params_exit:
2696 * i40e_aq_update_vsi_params
2697 * @hw: pointer to the hw struct
2698 * @vsi_ctx: pointer to a vsi context struct
2699 * @cmd_details: pointer to command details structure or NULL
2701 * Update a VSI context.
2703 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2704 struct i40e_vsi_context *vsi_ctx,
2705 struct i40e_asq_cmd_details *cmd_details)
2707 struct i40e_aq_desc desc;
2708 struct i40e_aqc_add_get_update_vsi *cmd =
2709 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2710 struct i40e_aqc_add_get_update_vsi_completion *resp =
2711 (struct i40e_aqc_add_get_update_vsi_completion *)
2713 enum i40e_status_code status;
2715 i40e_fill_default_direct_cmd_desc(&desc,
2716 i40e_aqc_opc_update_vsi_parameters);
2717 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2719 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2721 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2722 sizeof(vsi_ctx->info), cmd_details);
2724 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2725 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2731 * i40e_aq_get_switch_config
2732 * @hw: pointer to the hardware structure
2733 * @buf: pointer to the result buffer
2734 * @buf_size: length of input buffer
2735 * @start_seid: seid to start for the report, 0 == beginning
2736 * @cmd_details: pointer to command details structure or NULL
2738 * Fill the buf with switch configuration returned from AdminQ command
2740 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2741 struct i40e_aqc_get_switch_config_resp *buf,
2742 u16 buf_size, u16 *start_seid,
2743 struct i40e_asq_cmd_details *cmd_details)
2745 struct i40e_aq_desc desc;
2746 struct i40e_aqc_switch_seid *scfg =
2747 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2748 enum i40e_status_code status;
2750 i40e_fill_default_direct_cmd_desc(&desc,
2751 i40e_aqc_opc_get_switch_config);
2752 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2753 if (buf_size > I40E_AQ_LARGE_BUF)
2754 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2755 scfg->seid = CPU_TO_LE16(*start_seid);
2757 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2758 *start_seid = LE16_TO_CPU(scfg->seid);
2764 * i40e_aq_set_switch_config
2765 * @hw: pointer to the hardware structure
2766 * @flags: bit flag values to set
2767 * @mode: cloud filter mode
2768 * @valid_flags: which bit flags to set
2769 * @cmd_details: pointer to command details structure or NULL
2771 * Set switch configuration bits
2773 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2774 u16 flags, u16 valid_flags, u8 mode,
2775 struct i40e_asq_cmd_details *cmd_details)
2777 struct i40e_aq_desc desc;
2778 struct i40e_aqc_set_switch_config *scfg =
2779 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2780 enum i40e_status_code status;
2782 i40e_fill_default_direct_cmd_desc(&desc,
2783 i40e_aqc_opc_set_switch_config);
2784 scfg->flags = CPU_TO_LE16(flags);
2785 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2787 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2788 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2789 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2790 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2792 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2798 * i40e_aq_get_firmware_version
2799 * @hw: pointer to the hw struct
2800 * @fw_major_version: firmware major version
2801 * @fw_minor_version: firmware minor version
2802 * @fw_build: firmware build number
2803 * @api_major_version: major queue version
2804 * @api_minor_version: minor queue version
2805 * @cmd_details: pointer to command details structure or NULL
2807 * Get the firmware version from the admin queue commands
2809 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2810 u16 *fw_major_version, u16 *fw_minor_version,
2812 u16 *api_major_version, u16 *api_minor_version,
2813 struct i40e_asq_cmd_details *cmd_details)
2815 struct i40e_aq_desc desc;
2816 struct i40e_aqc_get_version *resp =
2817 (struct i40e_aqc_get_version *)&desc.params.raw;
2818 enum i40e_status_code status;
2820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2822 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2824 if (status == I40E_SUCCESS) {
2825 if (fw_major_version != NULL)
2826 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2827 if (fw_minor_version != NULL)
2828 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2829 if (fw_build != NULL)
2830 *fw_build = LE32_TO_CPU(resp->fw_build);
2831 if (api_major_version != NULL)
2832 *api_major_version = LE16_TO_CPU(resp->api_major);
2833 if (api_minor_version != NULL)
2834 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2836 /* A workaround to fix the API version in SW */
2837 if (api_major_version && api_minor_version &&
2838 fw_major_version && fw_minor_version &&
2839 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2840 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2841 (*fw_major_version > 4)))
2842 *api_minor_version = 2;
2849 * i40e_aq_send_driver_version
2850 * @hw: pointer to the hw struct
2851 * @dv: driver's major, minor version
2852 * @cmd_details: pointer to command details structure or NULL
2854 * Send the driver version to the firmware
2856 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2857 struct i40e_driver_version *dv,
2858 struct i40e_asq_cmd_details *cmd_details)
2860 struct i40e_aq_desc desc;
2861 struct i40e_aqc_driver_version *cmd =
2862 (struct i40e_aqc_driver_version *)&desc.params.raw;
2863 enum i40e_status_code status;
2867 return I40E_ERR_PARAM;
2869 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2871 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2872 cmd->driver_major_ver = dv->major_version;
2873 cmd->driver_minor_ver = dv->minor_version;
2874 cmd->driver_build_ver = dv->build_version;
2875 cmd->driver_subbuild_ver = dv->subbuild_version;
2878 while (len < sizeof(dv->driver_string) &&
2879 (dv->driver_string[len] < 0x80) &&
2880 dv->driver_string[len])
2882 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2889 * i40e_get_link_status - get status of the HW network link
2890 * @hw: pointer to the hw struct
2891 * @link_up: pointer to bool (true/false = linkup/linkdown)
2893 * Variable link_up true if link is up, false if link is down.
2894 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2896 * Side effect: LinkStatusEvent reporting becomes enabled
2898 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2900 enum i40e_status_code status = I40E_SUCCESS;
2902 if (hw->phy.get_link_info) {
2903 status = i40e_update_link_info(hw);
2905 if (status != I40E_SUCCESS)
2906 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2910 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2916 * i40e_updatelink_status - update status of the HW network link
2917 * @hw: pointer to the hw struct
2919 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2921 struct i40e_aq_get_phy_abilities_resp abilities;
2922 enum i40e_status_code status = I40E_SUCCESS;
2924 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2928 /* extra checking needed to ensure link info to user is timely */
2929 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2930 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2931 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2932 status = i40e_aq_get_phy_capabilities(hw, false, false,
2937 if (abilities.fec_cfg_curr_mod_ext_info &
2938 I40E_AQ_ENABLE_FEC_AUTO)
2939 hw->phy.link_info.req_fec_info =
2940 (I40E_AQ_REQUEST_FEC_KR |
2941 I40E_AQ_REQUEST_FEC_RS);
2943 hw->phy.link_info.req_fec_info =
2944 abilities.fec_cfg_curr_mod_ext_info &
2945 (I40E_AQ_REQUEST_FEC_KR |
2946 I40E_AQ_REQUEST_FEC_RS);
2948 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2949 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2956 * i40e_get_link_speed
2957 * @hw: pointer to the hw struct
2959 * Returns the link speed of the adapter.
2961 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2963 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2964 enum i40e_status_code status = I40E_SUCCESS;
2966 if (hw->phy.get_link_info) {
2967 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2969 if (status != I40E_SUCCESS)
2970 goto i40e_link_speed_exit;
2973 speed = hw->phy.link_info.link_speed;
2975 i40e_link_speed_exit:
2980 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2981 * @hw: pointer to the hw struct
2982 * @uplink_seid: the MAC or other gizmo SEID
2983 * @downlink_seid: the VSI SEID
2984 * @enabled_tc: bitmap of TCs to be enabled
2985 * @default_port: true for default port VSI, false for control port
2986 * @veb_seid: pointer to where to put the resulting VEB SEID
2987 * @enable_stats: true to turn on VEB stats
2988 * @cmd_details: pointer to command details structure or NULL
2990 * This asks the FW to add a VEB between the uplink and downlink
2991 * elements. If the uplink SEID is 0, this will be a floating VEB.
2993 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2994 u16 downlink_seid, u8 enabled_tc,
2995 bool default_port, u16 *veb_seid,
2997 struct i40e_asq_cmd_details *cmd_details)
2999 struct i40e_aq_desc desc;
3000 struct i40e_aqc_add_veb *cmd =
3001 (struct i40e_aqc_add_veb *)&desc.params.raw;
3002 struct i40e_aqc_add_veb_completion *resp =
3003 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
3004 enum i40e_status_code status;
3007 /* SEIDs need to either both be set or both be 0 for floating VEB */
3008 if (!!uplink_seid != !!downlink_seid)
3009 return I40E_ERR_PARAM;
3011 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
3013 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
3014 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
3015 cmd->enable_tcs = enabled_tc;
3017 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
3019 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
3021 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
3023 /* reverse logic here: set the bitflag to disable the stats */
3025 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
3027 cmd->veb_flags = CPU_TO_LE16(veb_flags);
3029 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3031 if (!status && veb_seid)
3032 *veb_seid = LE16_TO_CPU(resp->veb_seid);
3038 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
3039 * @hw: pointer to the hw struct
3040 * @veb_seid: the SEID of the VEB to query
3041 * @switch_id: the uplink switch id
3042 * @floating: set to true if the VEB is floating
3043 * @statistic_index: index of the stats counter block for this VEB
3044 * @vebs_used: number of VEB's used by function
3045 * @vebs_free: total VEB's not reserved by any function
3046 * @cmd_details: pointer to command details structure or NULL
3048 * This retrieves the parameters for a particular VEB, specified by
3049 * uplink_seid, and returns them to the caller.
3051 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3052 u16 veb_seid, u16 *switch_id,
3053 bool *floating, u16 *statistic_index,
3054 u16 *vebs_used, u16 *vebs_free,
3055 struct i40e_asq_cmd_details *cmd_details)
3057 struct i40e_aq_desc desc;
3058 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3059 (struct i40e_aqc_get_veb_parameters_completion *)
3061 enum i40e_status_code status;
3064 return I40E_ERR_PARAM;
3066 i40e_fill_default_direct_cmd_desc(&desc,
3067 i40e_aqc_opc_get_veb_parameters);
3068 cmd_resp->seid = CPU_TO_LE16(veb_seid);
3070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3075 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3076 if (statistic_index)
3077 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3079 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3081 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3083 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3085 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3096 * i40e_aq_add_macvlan
3097 * @hw: pointer to the hw struct
3098 * @seid: VSI for the mac address
3099 * @mv_list: list of macvlans to be added
3100 * @count: length of the list
3101 * @cmd_details: pointer to command details structure or NULL
3103 * Add MAC/VLAN addresses to the HW filtering
3105 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3106 struct i40e_aqc_add_macvlan_element_data *mv_list,
3107 u16 count, struct i40e_asq_cmd_details *cmd_details)
3109 struct i40e_aq_desc desc;
3110 struct i40e_aqc_macvlan *cmd =
3111 (struct i40e_aqc_macvlan *)&desc.params.raw;
3112 enum i40e_status_code status;
3116 if (count == 0 || !mv_list || !hw)
3117 return I40E_ERR_PARAM;
3119 buf_size = count * sizeof(*mv_list);
3121 /* prep the rest of the request */
3122 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3123 cmd->num_addresses = CPU_TO_LE16(count);
3124 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3128 for (i = 0; i < count; i++)
3129 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3131 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3133 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3134 if (buf_size > I40E_AQ_LARGE_BUF)
3135 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3137 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3144 * i40e_aq_remove_macvlan
3145 * @hw: pointer to the hw struct
3146 * @seid: VSI for the mac address
3147 * @mv_list: list of macvlans to be removed
3148 * @count: length of the list
3149 * @cmd_details: pointer to command details structure or NULL
3151 * Remove MAC/VLAN addresses from the HW filtering
3153 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3154 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3155 u16 count, struct i40e_asq_cmd_details *cmd_details)
3157 struct i40e_aq_desc desc;
3158 struct i40e_aqc_macvlan *cmd =
3159 (struct i40e_aqc_macvlan *)&desc.params.raw;
3160 enum i40e_status_code status;
3163 if (count == 0 || !mv_list || !hw)
3164 return I40E_ERR_PARAM;
3166 buf_size = count * sizeof(*mv_list);
3168 /* prep the rest of the request */
3169 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3170 cmd->num_addresses = CPU_TO_LE16(count);
3171 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3175 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3176 if (buf_size > I40E_AQ_LARGE_BUF)
3177 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3179 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3186 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3187 * @hw: pointer to the hw struct
3188 * @opcode: AQ opcode for add or delete mirror rule
3189 * @sw_seid: Switch SEID (to which rule refers)
3190 * @rule_type: Rule Type (ingress/egress/VLAN)
3191 * @id: Destination VSI SEID or Rule ID
3192 * @count: length of the list
3193 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3194 * @cmd_details: pointer to command details structure or NULL
3195 * @rule_id: Rule ID returned from FW
3196 * @rules_used: Number of rules used in internal switch
3197 * @rules_free: Number of rules free in internal switch
3199 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3200 * VEBs/VEPA elements only
3202 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3203 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3204 u16 count, __le16 *mr_list,
3205 struct i40e_asq_cmd_details *cmd_details,
3206 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3208 struct i40e_aq_desc desc;
3209 struct i40e_aqc_add_delete_mirror_rule *cmd =
3210 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3211 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3212 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3213 enum i40e_status_code status;
3216 buf_size = count * sizeof(*mr_list);
3218 /* prep the rest of the request */
3219 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3220 cmd->seid = CPU_TO_LE16(sw_seid);
3221 cmd->rule_type = CPU_TO_LE16(rule_type &
3222 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3223 cmd->num_entries = CPU_TO_LE16(count);
3224 /* Dest VSI for add, rule_id for delete */
3225 cmd->destination = CPU_TO_LE16(id);
3227 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3229 if (buf_size > I40E_AQ_LARGE_BUF)
3230 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3233 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3235 if (status == I40E_SUCCESS ||
3236 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3238 *rule_id = LE16_TO_CPU(resp->rule_id);
3240 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3242 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3248 * i40e_aq_add_mirrorrule - add a mirror rule
3249 * @hw: pointer to the hw struct
3250 * @sw_seid: Switch SEID (to which rule refers)
3251 * @rule_type: Rule Type (ingress/egress/VLAN)
3252 * @dest_vsi: SEID of VSI to which packets will be mirrored
3253 * @count: length of the list
3254 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3255 * @cmd_details: pointer to command details structure or NULL
3256 * @rule_id: Rule ID returned from FW
3257 * @rules_used: Number of rules used in internal switch
3258 * @rules_free: Number of rules free in internal switch
3260 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3262 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3263 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3264 struct i40e_asq_cmd_details *cmd_details,
3265 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3267 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3268 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3269 if (count == 0 || !mr_list)
3270 return I40E_ERR_PARAM;
3273 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3274 rule_type, dest_vsi, count, mr_list,
3275 cmd_details, rule_id, rules_used, rules_free);
3279 * i40e_aq_delete_mirrorrule - delete a mirror rule
3280 * @hw: pointer to the hw struct
3281 * @sw_seid: Switch SEID (to which rule refers)
3282 * @rule_type: Rule Type (ingress/egress/VLAN)
3283 * @count: length of the list
3284 * @rule_id: Rule ID that is returned in the receive desc as part of
3286 * @mr_list: list of mirrored VLAN IDs to be removed
3287 * @cmd_details: pointer to command details structure or NULL
3288 * @rules_used: Number of rules used in internal switch
3289 * @rules_free: Number of rules free in internal switch
3291 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3293 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3294 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3295 struct i40e_asq_cmd_details *cmd_details,
3296 u16 *rules_used, u16 *rules_free)
3298 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3299 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3300 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3301 * mirroring. For other rule_type, count and rule_type should
3304 if (count == 0 || !mr_list)
3305 return I40E_ERR_PARAM;
3308 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3309 rule_type, rule_id, count, mr_list,
3310 cmd_details, NULL, rules_used, rules_free);
3314 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3315 * @hw: pointer to the hw struct
3316 * @seid: VSI for the vlan filters
3317 * @v_list: list of vlan filters to be added
3318 * @count: length of the list
3319 * @cmd_details: pointer to command details structure or NULL
3321 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3322 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3323 u8 count, struct i40e_asq_cmd_details *cmd_details)
3325 struct i40e_aq_desc desc;
3326 struct i40e_aqc_macvlan *cmd =
3327 (struct i40e_aqc_macvlan *)&desc.params.raw;
3328 enum i40e_status_code status;
3331 if (count == 0 || !v_list || !hw)
3332 return I40E_ERR_PARAM;
3334 buf_size = count * sizeof(*v_list);
3336 /* prep the rest of the request */
3337 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3338 cmd->num_addresses = CPU_TO_LE16(count);
3339 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3343 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3344 if (buf_size > I40E_AQ_LARGE_BUF)
3345 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3347 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3354 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3355 * @hw: pointer to the hw struct
3356 * @seid: VSI for the vlan filters
3357 * @v_list: list of macvlans to be removed
3358 * @count: length of the list
3359 * @cmd_details: pointer to command details structure or NULL
3361 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3362 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3363 u8 count, struct i40e_asq_cmd_details *cmd_details)
3365 struct i40e_aq_desc desc;
3366 struct i40e_aqc_macvlan *cmd =
3367 (struct i40e_aqc_macvlan *)&desc.params.raw;
3368 enum i40e_status_code status;
3371 if (count == 0 || !v_list || !hw)
3372 return I40E_ERR_PARAM;
3374 buf_size = count * sizeof(*v_list);
3376 /* prep the rest of the request */
3377 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3378 cmd->num_addresses = CPU_TO_LE16(count);
3379 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3383 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3384 if (buf_size > I40E_AQ_LARGE_BUF)
3385 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3387 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3394 * i40e_aq_send_msg_to_vf
3395 * @hw: pointer to the hardware structure
3396 * @vfid: vf id to send msg
3397 * @v_opcode: opcodes for VF-PF communication
3398 * @v_retval: return error code
3399 * @msg: pointer to the msg buffer
3400 * @msglen: msg length
3401 * @cmd_details: pointer to command details
3405 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3406 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3407 struct i40e_asq_cmd_details *cmd_details)
3409 struct i40e_aq_desc desc;
3410 struct i40e_aqc_pf_vf_message *cmd =
3411 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3412 enum i40e_status_code status;
3414 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3415 cmd->id = CPU_TO_LE32(vfid);
3416 desc.cookie_high = CPU_TO_LE32(v_opcode);
3417 desc.cookie_low = CPU_TO_LE32(v_retval);
3418 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3420 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3422 if (msglen > I40E_AQ_LARGE_BUF)
3423 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3424 desc.datalen = CPU_TO_LE16(msglen);
3426 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3432 * i40e_aq_debug_read_register
3433 * @hw: pointer to the hw struct
3434 * @reg_addr: register address
3435 * @reg_val: register value
3436 * @cmd_details: pointer to command details structure or NULL
3438 * Read the register using the admin queue commands
3440 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3441 u32 reg_addr, u64 *reg_val,
3442 struct i40e_asq_cmd_details *cmd_details)
3444 struct i40e_aq_desc desc;
3445 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3446 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3447 enum i40e_status_code status;
3449 if (reg_val == NULL)
3450 return I40E_ERR_PARAM;
3452 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3454 cmd_resp->address = CPU_TO_LE32(reg_addr);
3456 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3458 if (status == I40E_SUCCESS) {
3459 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3460 (u64)LE32_TO_CPU(cmd_resp->value_low);
3467 * i40e_aq_debug_write_register
3468 * @hw: pointer to the hw struct
3469 * @reg_addr: register address
3470 * @reg_val: register value
3471 * @cmd_details: pointer to command details structure or NULL
3473 * Write to a register using the admin queue commands
3475 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3476 u32 reg_addr, u64 reg_val,
3477 struct i40e_asq_cmd_details *cmd_details)
3479 struct i40e_aq_desc desc;
3480 struct i40e_aqc_debug_reg_read_write *cmd =
3481 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3482 enum i40e_status_code status;
3484 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3486 cmd->address = CPU_TO_LE32(reg_addr);
3487 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3488 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3490 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3496 * i40e_aq_request_resource
3497 * @hw: pointer to the hw struct
3498 * @resource: resource id
3499 * @access: access type
3500 * @sdp_number: resource number
3501 * @timeout: the maximum time in ms that the driver may hold the resource
3502 * @cmd_details: pointer to command details structure or NULL
3504 * requests common resource using the admin queue commands
3506 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3507 enum i40e_aq_resources_ids resource,
3508 enum i40e_aq_resource_access_type access,
3509 u8 sdp_number, u64 *timeout,
3510 struct i40e_asq_cmd_details *cmd_details)
3512 struct i40e_aq_desc desc;
3513 struct i40e_aqc_request_resource *cmd_resp =
3514 (struct i40e_aqc_request_resource *)&desc.params.raw;
3515 enum i40e_status_code status;
3517 DEBUGFUNC("i40e_aq_request_resource");
3519 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3521 cmd_resp->resource_id = CPU_TO_LE16(resource);
3522 cmd_resp->access_type = CPU_TO_LE16(access);
3523 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3525 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3526 /* The completion specifies the maximum time in ms that the driver
3527 * may hold the resource in the Timeout field.
3528 * If the resource is held by someone else, the command completes with
3529 * busy return value and the timeout field indicates the maximum time
3530 * the current owner of the resource has to free it.
3532 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3533 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3539 * i40e_aq_release_resource
3540 * @hw: pointer to the hw struct
3541 * @resource: resource id
3542 * @sdp_number: resource number
3543 * @cmd_details: pointer to command details structure or NULL
3545 * release common resource using the admin queue commands
3547 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3548 enum i40e_aq_resources_ids resource,
3550 struct i40e_asq_cmd_details *cmd_details)
3552 struct i40e_aq_desc desc;
3553 struct i40e_aqc_request_resource *cmd =
3554 (struct i40e_aqc_request_resource *)&desc.params.raw;
3555 enum i40e_status_code status;
3557 DEBUGFUNC("i40e_aq_release_resource");
3559 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3561 cmd->resource_id = CPU_TO_LE16(resource);
3562 cmd->resource_number = CPU_TO_LE32(sdp_number);
3564 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3571 * @hw: pointer to the hw struct
3572 * @module_pointer: module pointer location in words from the NVM beginning
3573 * @offset: byte offset from the module beginning
3574 * @length: length of the section to be read (in bytes from the offset)
3575 * @data: command buffer (size [bytes] = length)
3576 * @last_command: tells if this is the last command in a series
3577 * @cmd_details: pointer to command details structure or NULL
3579 * Read the NVM using the admin queue commands
3581 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3582 u32 offset, u16 length, void *data,
3584 struct i40e_asq_cmd_details *cmd_details)
3586 struct i40e_aq_desc desc;
3587 struct i40e_aqc_nvm_update *cmd =
3588 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3589 enum i40e_status_code status;
3591 DEBUGFUNC("i40e_aq_read_nvm");
3593 /* In offset the highest byte must be zeroed. */
3594 if (offset & 0xFF000000) {
3595 status = I40E_ERR_PARAM;
3596 goto i40e_aq_read_nvm_exit;
3599 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3601 /* If this is the last command in a series, set the proper flag. */
3603 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3604 cmd->module_pointer = module_pointer;
3605 cmd->offset = CPU_TO_LE32(offset);
3606 cmd->length = CPU_TO_LE16(length);
3608 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3609 if (length > I40E_AQ_LARGE_BUF)
3610 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3612 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3614 i40e_aq_read_nvm_exit:
3619 * i40e_aq_read_nvm_config - read an nvm config block
3620 * @hw: pointer to the hw struct
3621 * @cmd_flags: NVM access admin command bits
3622 * @field_id: field or feature id
3623 * @data: buffer for result
3624 * @buf_size: buffer size
3625 * @element_count: pointer to count of elements read by FW
3626 * @cmd_details: pointer to command details structure or NULL
3628 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3629 u8 cmd_flags, u32 field_id, void *data,
3630 u16 buf_size, u16 *element_count,
3631 struct i40e_asq_cmd_details *cmd_details)
3633 struct i40e_aq_desc desc;
3634 struct i40e_aqc_nvm_config_read *cmd =
3635 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3636 enum i40e_status_code status;
3638 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3639 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3640 if (buf_size > I40E_AQ_LARGE_BUF)
3641 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3643 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3644 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3645 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3646 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3648 cmd->element_id_msw = 0;
3650 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3652 if (!status && element_count)
3653 *element_count = LE16_TO_CPU(cmd->element_count);
3659 * i40e_aq_write_nvm_config - write an nvm config block
3660 * @hw: pointer to the hw struct
3661 * @cmd_flags: NVM access admin command bits
3662 * @data: buffer for result
3663 * @buf_size: buffer size
3664 * @element_count: count of elements to be written
3665 * @cmd_details: pointer to command details structure or NULL
3667 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3668 u8 cmd_flags, void *data, u16 buf_size,
3670 struct i40e_asq_cmd_details *cmd_details)
3672 struct i40e_aq_desc desc;
3673 struct i40e_aqc_nvm_config_write *cmd =
3674 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3675 enum i40e_status_code status;
3677 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3678 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3679 if (buf_size > I40E_AQ_LARGE_BUF)
3680 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3682 cmd->element_count = CPU_TO_LE16(element_count);
3683 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3684 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3690 * i40e_aq_nvm_update_in_process
3691 * @hw: pointer to the hw struct
3692 * @update_flow_state: True indicates that update flow starts, false that ends
3693 * @cmd_details: pointer to command details structure or NULL
3695 * Indicate NVM update in process.
3697 enum i40e_status_code
3698 i40e_aq_nvm_update_in_process(struct i40e_hw *hw,
3699 bool update_flow_state,
3700 struct i40e_asq_cmd_details *cmd_details)
3702 struct i40e_aq_desc desc;
3703 struct i40e_aqc_nvm_update_in_process *cmd =
3704 (struct i40e_aqc_nvm_update_in_process *)&desc.params.raw;
3705 enum i40e_status_code status;
3707 i40e_fill_default_direct_cmd_desc(&desc,
3708 i40e_aqc_opc_nvm_update_in_process);
3710 cmd->command = I40E_AQ_UPDATE_FLOW_END;
3712 if (update_flow_state)
3713 cmd->command |= I40E_AQ_UPDATE_FLOW_START;
3715 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3721 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3722 * @hw: pointer to the hw struct
3723 * @buff: buffer for result
3724 * @buff_size: buffer size
3725 * @cmd_details: pointer to command details structure or NULL
3727 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3728 void *buff, u16 buff_size,
3729 struct i40e_asq_cmd_details *cmd_details)
3731 struct i40e_aq_desc desc;
3732 enum i40e_status_code status;
3734 UNREFERENCED_2PARAMETER(buff, buff_size);
3736 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3737 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3738 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3739 status = I40E_ERR_NOT_IMPLEMENTED;
3746 * @hw: pointer to the hw struct
3747 * @module_pointer: module pointer location in words from the NVM beginning
3748 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3749 * @length: length of the section to be erased (expressed in 4 KB)
3750 * @last_command: tells if this is the last command in a series
3751 * @cmd_details: pointer to command details structure or NULL
3753 * Erase the NVM sector using the admin queue commands
3755 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3756 u32 offset, u16 length, bool last_command,
3757 struct i40e_asq_cmd_details *cmd_details)
3759 struct i40e_aq_desc desc;
3760 struct i40e_aqc_nvm_update *cmd =
3761 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3762 enum i40e_status_code status;
3764 DEBUGFUNC("i40e_aq_erase_nvm");
3766 /* In offset the highest byte must be zeroed. */
3767 if (offset & 0xFF000000) {
3768 status = I40E_ERR_PARAM;
3769 goto i40e_aq_erase_nvm_exit;
3772 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3774 /* If this is the last command in a series, set the proper flag. */
3776 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3777 cmd->module_pointer = module_pointer;
3778 cmd->offset = CPU_TO_LE32(offset);
3779 cmd->length = CPU_TO_LE16(length);
3781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3783 i40e_aq_erase_nvm_exit:
3788 * i40e_parse_discover_capabilities
3789 * @hw: pointer to the hw struct
3790 * @buff: pointer to a buffer containing device/function capability records
3791 * @cap_count: number of capability records in the list
3792 * @list_type_opc: type of capabilities list to parse
3794 * Parse the device/function capabilities list.
3796 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3798 enum i40e_admin_queue_opc list_type_opc)
3800 struct i40e_aqc_list_capabilities_element_resp *cap;
3801 u32 valid_functions, num_functions;
3802 u32 number, logical_id, phys_id;
3803 struct i40e_hw_capabilities *p;
3804 enum i40e_status_code status;
3805 u16 id, ocp_cfg_word0;
3809 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3811 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3812 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3813 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3814 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3818 for (i = 0; i < cap_count; i++, cap++) {
3819 id = LE16_TO_CPU(cap->id);
3820 number = LE32_TO_CPU(cap->number);
3821 logical_id = LE32_TO_CPU(cap->logical_id);
3822 phys_id = LE32_TO_CPU(cap->phys_id);
3823 major_rev = cap->major_rev;
3826 case I40E_AQ_CAP_ID_SWITCH_MODE:
3827 p->switch_mode = number;
3828 i40e_debug(hw, I40E_DEBUG_INIT,
3829 "HW Capability: Switch mode = %d\n",
3832 case I40E_AQ_CAP_ID_MNG_MODE:
3833 p->management_mode = number;
3834 if (major_rev > 1) {
3835 p->mng_protocols_over_mctp = logical_id;
3836 i40e_debug(hw, I40E_DEBUG_INIT,
3837 "HW Capability: Protocols over MCTP = %d\n",
3838 p->mng_protocols_over_mctp);
3840 p->mng_protocols_over_mctp = 0;
3842 i40e_debug(hw, I40E_DEBUG_INIT,
3843 "HW Capability: Management Mode = %d\n",
3844 p->management_mode);
3846 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3847 p->npar_enable = number;
3848 i40e_debug(hw, I40E_DEBUG_INIT,
3849 "HW Capability: NPAR enable = %d\n",
3852 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3854 i40e_debug(hw, I40E_DEBUG_INIT,
3855 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3857 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3858 p->valid_functions = number;
3859 i40e_debug(hw, I40E_DEBUG_INIT,
3860 "HW Capability: Valid Functions = %d\n",
3861 p->valid_functions);
3863 case I40E_AQ_CAP_ID_SRIOV:
3865 p->sr_iov_1_1 = true;
3866 i40e_debug(hw, I40E_DEBUG_INIT,
3867 "HW Capability: SR-IOV = %d\n",
3870 case I40E_AQ_CAP_ID_VF:
3871 p->num_vfs = number;
3872 p->vf_base_id = logical_id;
3873 i40e_debug(hw, I40E_DEBUG_INIT,
3874 "HW Capability: VF count = %d\n",
3876 i40e_debug(hw, I40E_DEBUG_INIT,
3877 "HW Capability: VF base_id = %d\n",
3880 case I40E_AQ_CAP_ID_VMDQ:
3883 i40e_debug(hw, I40E_DEBUG_INIT,
3884 "HW Capability: VMDQ = %d\n", p->vmdq);
3886 case I40E_AQ_CAP_ID_8021QBG:
3888 p->evb_802_1_qbg = true;
3889 i40e_debug(hw, I40E_DEBUG_INIT,
3890 "HW Capability: 802.1Qbg = %d\n", number);
3892 case I40E_AQ_CAP_ID_8021QBR:
3894 p->evb_802_1_qbh = true;
3895 i40e_debug(hw, I40E_DEBUG_INIT,
3896 "HW Capability: 802.1Qbh = %d\n", number);
3898 case I40E_AQ_CAP_ID_VSI:
3899 p->num_vsis = number;
3900 i40e_debug(hw, I40E_DEBUG_INIT,
3901 "HW Capability: VSI count = %d\n",
3904 case I40E_AQ_CAP_ID_DCB:
3907 p->enabled_tcmap = logical_id;
3910 i40e_debug(hw, I40E_DEBUG_INIT,
3911 "HW Capability: DCB = %d\n", p->dcb);
3912 i40e_debug(hw, I40E_DEBUG_INIT,
3913 "HW Capability: TC Mapping = %d\n",
3915 i40e_debug(hw, I40E_DEBUG_INIT,
3916 "HW Capability: TC Max = %d\n", p->maxtc);
3918 case I40E_AQ_CAP_ID_FCOE:
3921 i40e_debug(hw, I40E_DEBUG_INIT,
3922 "HW Capability: FCOE = %d\n", p->fcoe);
3924 case I40E_AQ_CAP_ID_ISCSI:
3927 i40e_debug(hw, I40E_DEBUG_INIT,
3928 "HW Capability: iSCSI = %d\n", p->iscsi);
3930 case I40E_AQ_CAP_ID_RSS:
3932 p->rss_table_size = number;
3933 p->rss_table_entry_width = logical_id;
3934 i40e_debug(hw, I40E_DEBUG_INIT,
3935 "HW Capability: RSS = %d\n", p->rss);
3936 i40e_debug(hw, I40E_DEBUG_INIT,
3937 "HW Capability: RSS table size = %d\n",
3939 i40e_debug(hw, I40E_DEBUG_INIT,
3940 "HW Capability: RSS table width = %d\n",
3941 p->rss_table_entry_width);
3943 case I40E_AQ_CAP_ID_RXQ:
3944 p->num_rx_qp = number;
3945 p->base_queue = phys_id;
3946 i40e_debug(hw, I40E_DEBUG_INIT,
3947 "HW Capability: Rx QP = %d\n", number);
3948 i40e_debug(hw, I40E_DEBUG_INIT,
3949 "HW Capability: base_queue = %d\n",
3952 case I40E_AQ_CAP_ID_TXQ:
3953 p->num_tx_qp = number;
3954 p->base_queue = phys_id;
3955 i40e_debug(hw, I40E_DEBUG_INIT,
3956 "HW Capability: Tx QP = %d\n", number);
3957 i40e_debug(hw, I40E_DEBUG_INIT,
3958 "HW Capability: base_queue = %d\n",
3961 case I40E_AQ_CAP_ID_MSIX:
3962 p->num_msix_vectors = number;
3963 i40e_debug(hw, I40E_DEBUG_INIT,
3964 "HW Capability: MSIX vector count = %d\n",
3965 p->num_msix_vectors);
3967 case I40E_AQ_CAP_ID_VF_MSIX:
3968 p->num_msix_vectors_vf = number;
3969 i40e_debug(hw, I40E_DEBUG_INIT,
3970 "HW Capability: MSIX VF vector count = %d\n",
3971 p->num_msix_vectors_vf);
3973 case I40E_AQ_CAP_ID_FLEX10:
3974 if (major_rev == 1) {
3976 p->flex10_enable = true;
3977 p->flex10_capable = true;
3980 /* Capability revision >= 2 */
3982 p->flex10_enable = true;
3984 p->flex10_capable = true;
3986 p->flex10_mode = logical_id;
3987 p->flex10_status = phys_id;
3988 i40e_debug(hw, I40E_DEBUG_INIT,
3989 "HW Capability: Flex10 mode = %d\n",
3991 i40e_debug(hw, I40E_DEBUG_INIT,
3992 "HW Capability: Flex10 status = %d\n",
3995 case I40E_AQ_CAP_ID_CEM:
3998 i40e_debug(hw, I40E_DEBUG_INIT,
3999 "HW Capability: CEM = %d\n", p->mgmt_cem);
4001 case I40E_AQ_CAP_ID_IWARP:
4004 i40e_debug(hw, I40E_DEBUG_INIT,
4005 "HW Capability: iWARP = %d\n", p->iwarp);
4007 case I40E_AQ_CAP_ID_LED:
4008 if (phys_id < I40E_HW_CAP_MAX_GPIO)
4009 p->led[phys_id] = true;
4010 i40e_debug(hw, I40E_DEBUG_INIT,
4011 "HW Capability: LED - PIN %d\n", phys_id);
4013 case I40E_AQ_CAP_ID_SDP:
4014 if (phys_id < I40E_HW_CAP_MAX_GPIO)
4015 p->sdp[phys_id] = true;
4016 i40e_debug(hw, I40E_DEBUG_INIT,
4017 "HW Capability: SDP - PIN %d\n", phys_id);
4019 case I40E_AQ_CAP_ID_MDIO:
4021 p->mdio_port_num = phys_id;
4022 p->mdio_port_mode = logical_id;
4024 i40e_debug(hw, I40E_DEBUG_INIT,
4025 "HW Capability: MDIO port number = %d\n",
4027 i40e_debug(hw, I40E_DEBUG_INIT,
4028 "HW Capability: MDIO port mode = %d\n",
4031 case I40E_AQ_CAP_ID_1588:
4033 p->ieee_1588 = true;
4034 i40e_debug(hw, I40E_DEBUG_INIT,
4035 "HW Capability: IEEE 1588 = %d\n",
4038 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
4040 p->fd_filters_guaranteed = number;
4041 p->fd_filters_best_effort = logical_id;
4042 i40e_debug(hw, I40E_DEBUG_INIT,
4043 "HW Capability: Flow Director = 1\n");
4044 i40e_debug(hw, I40E_DEBUG_INIT,
4045 "HW Capability: Guaranteed FD filters = %d\n",
4046 p->fd_filters_guaranteed);
4048 case I40E_AQ_CAP_ID_WSR_PROT:
4049 p->wr_csr_prot = (u64)number;
4050 p->wr_csr_prot |= (u64)logical_id << 32;
4051 i40e_debug(hw, I40E_DEBUG_INIT,
4052 "HW Capability: wr_csr_prot = 0x%llX\n\n",
4053 (p->wr_csr_prot & 0xffff));
4055 case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS:
4056 p->dis_unused_ports = (bool)number;
4057 i40e_debug(hw, I40E_DEBUG_INIT,
4058 "HW Capability: dis_unused_ports = %d\n\n",
4059 p->dis_unused_ports);
4061 case I40E_AQ_CAP_ID_NVM_MGMT:
4062 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
4063 p->sec_rev_disabled = true;
4064 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
4065 p->update_disabled = true;
4067 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
4068 hw->num_wol_proxy_filters = (u16)number;
4069 hw->wol_proxy_vsi_seid = (u16)logical_id;
4070 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
4071 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
4072 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
4074 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
4075 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
4076 i40e_debug(hw, I40E_DEBUG_INIT,
4077 "HW Capability: WOL proxy filters = %d\n",
4078 hw->num_wol_proxy_filters);
4086 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4088 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4091 /* count the enabled ports (aka the "not disabled" ports) */
4093 for (i = 0; i < 4; i++) {
4094 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4097 /* use AQ read to get the physical register offset instead
4098 * of the port relative offset
4100 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4101 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4105 /* OCP cards case: if a mezz is removed the ethernet port is at
4106 * disabled state in PRTGEN_CNF register. Additional NVM read is
4107 * needed in order to check if we are dealing with OCP card.
4108 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4109 * physical ports results in wrong partition id calculation and thus
4110 * not supporting WoL.
4112 if (hw->mac.type == I40E_MAC_X722) {
4113 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4114 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4115 2 * I40E_SR_OCP_CFG_WORD0,
4116 sizeof(ocp_cfg_word0),
4117 &ocp_cfg_word0, true, NULL);
4118 if (status == I40E_SUCCESS &&
4119 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4121 i40e_release_nvm(hw);
4125 valid_functions = p->valid_functions;
4127 while (valid_functions) {
4128 if (valid_functions & 1)
4130 valid_functions >>= 1;
4133 /* partition id is 1-based, and functions are evenly spread
4134 * across the ports as partitions
4136 if (hw->num_ports != 0) {
4137 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4138 hw->num_partitions = num_functions / hw->num_ports;
4141 /* additional HW specific goodies that might
4142 * someday be HW version specific
4144 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4148 * i40e_aq_discover_capabilities
4149 * @hw: pointer to the hw struct
4150 * @buff: a virtual buffer to hold the capabilities
4151 * @buff_size: Size of the virtual buffer
4152 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4153 * @list_type_opc: capabilities type to discover - pass in the command opcode
4154 * @cmd_details: pointer to command details structure or NULL
4156 * Get the device capabilities descriptions from the firmware
4158 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4159 void *buff, u16 buff_size, u16 *data_size,
4160 enum i40e_admin_queue_opc list_type_opc,
4161 struct i40e_asq_cmd_details *cmd_details)
4163 struct i40e_aqc_list_capabilites *cmd;
4164 struct i40e_aq_desc desc;
4165 enum i40e_status_code status = I40E_SUCCESS;
4167 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4169 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4170 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4171 status = I40E_ERR_PARAM;
4175 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4177 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4178 if (buff_size > I40E_AQ_LARGE_BUF)
4179 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4181 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4182 *data_size = LE16_TO_CPU(desc.datalen);
4187 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4195 * i40e_aq_update_nvm
4196 * @hw: pointer to the hw struct
4197 * @module_pointer: module pointer location in words from the NVM beginning
4198 * @offset: byte offset from the module beginning
4199 * @length: length of the section to be written (in bytes from the offset)
4200 * @data: command buffer (size [bytes] = length)
4201 * @last_command: tells if this is the last command in a series
4202 * @preservation_flags: Preservation mode flags
4203 * @cmd_details: pointer to command details structure or NULL
4205 * Update the NVM using the admin queue commands
4207 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4208 u32 offset, u16 length, void *data,
4209 bool last_command, u8 preservation_flags,
4210 struct i40e_asq_cmd_details *cmd_details)
4212 struct i40e_aq_desc desc;
4213 struct i40e_aqc_nvm_update *cmd =
4214 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4215 enum i40e_status_code status;
4217 DEBUGFUNC("i40e_aq_update_nvm");
4219 /* In offset the highest byte must be zeroed. */
4220 if (offset & 0xFF000000) {
4221 status = I40E_ERR_PARAM;
4222 goto i40e_aq_update_nvm_exit;
4225 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4227 /* If this is the last command in a series, set the proper flag. */
4229 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4230 if (hw->mac.type == I40E_MAC_X722) {
4231 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4232 cmd->command_flags |=
4233 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4234 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4235 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4236 cmd->command_flags |=
4237 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4238 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4240 cmd->module_pointer = module_pointer;
4241 cmd->offset = CPU_TO_LE32(offset);
4242 cmd->length = CPU_TO_LE16(length);
4244 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4245 if (length > I40E_AQ_LARGE_BUF)
4246 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4248 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4250 i40e_aq_update_nvm_exit:
4255 * i40e_aq_rearrange_nvm
4256 * @hw: pointer to the hw struct
4257 * @rearrange_nvm: defines direction of rearrangement
4258 * @cmd_details: pointer to command details structure or NULL
4260 * Rearrange NVM structure, available only for transition FW
4262 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4264 struct i40e_asq_cmd_details *cmd_details)
4266 struct i40e_aqc_nvm_update *cmd;
4267 enum i40e_status_code status;
4268 struct i40e_aq_desc desc;
4270 DEBUGFUNC("i40e_aq_rearrange_nvm");
4272 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4274 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4276 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4277 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4279 if (!rearrange_nvm) {
4280 status = I40E_ERR_PARAM;
4281 goto i40e_aq_rearrange_nvm_exit;
4284 cmd->command_flags |= rearrange_nvm;
4285 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4287 i40e_aq_rearrange_nvm_exit:
4292 * i40e_aq_get_lldp_mib
4293 * @hw: pointer to the hw struct
4294 * @bridge_type: type of bridge requested
4295 * @mib_type: Local, Remote or both Local and Remote MIBs
4296 * @buff: pointer to a user supplied buffer to store the MIB block
4297 * @buff_size: size of the buffer (in bytes)
4298 * @local_len : length of the returned Local LLDP MIB
4299 * @remote_len: length of the returned Remote LLDP MIB
4300 * @cmd_details: pointer to command details structure or NULL
4302 * Requests the complete LLDP MIB (entire packet).
4304 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4305 u8 mib_type, void *buff, u16 buff_size,
4306 u16 *local_len, u16 *remote_len,
4307 struct i40e_asq_cmd_details *cmd_details)
4309 struct i40e_aq_desc desc;
4310 struct i40e_aqc_lldp_get_mib *cmd =
4311 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4312 struct i40e_aqc_lldp_get_mib *resp =
4313 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4314 enum i40e_status_code status;
4316 if (buff_size == 0 || !buff)
4317 return I40E_ERR_PARAM;
4319 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4320 /* Indirect Command */
4321 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4323 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4324 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4325 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4327 desc.datalen = CPU_TO_LE16(buff_size);
4329 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4330 if (buff_size > I40E_AQ_LARGE_BUF)
4331 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4333 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4335 if (local_len != NULL)
4336 *local_len = LE16_TO_CPU(resp->local_len);
4337 if (remote_len != NULL)
4338 *remote_len = LE16_TO_CPU(resp->remote_len);
4345 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4346 * @hw: pointer to the hw struct
4347 * @mib_type: Local, Remote or both Local and Remote MIBs
4348 * @buff: pointer to a user supplied buffer to store the MIB block
4349 * @buff_size: size of the buffer (in bytes)
4350 * @cmd_details: pointer to command details structure or NULL
4354 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4355 u8 mib_type, void *buff, u16 buff_size,
4356 struct i40e_asq_cmd_details *cmd_details)
4358 struct i40e_aq_desc desc;
4359 struct i40e_aqc_lldp_set_local_mib *cmd =
4360 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4361 enum i40e_status_code status;
4363 if (buff_size == 0 || !buff)
4364 return I40E_ERR_PARAM;
4366 i40e_fill_default_direct_cmd_desc(&desc,
4367 i40e_aqc_opc_lldp_set_local_mib);
4368 /* Indirect Command */
4369 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4370 if (buff_size > I40E_AQ_LARGE_BUF)
4371 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4372 desc.datalen = CPU_TO_LE16(buff_size);
4374 cmd->type = mib_type;
4375 cmd->length = CPU_TO_LE16(buff_size);
4376 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4377 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4379 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4384 * i40e_aq_cfg_lldp_mib_change_event
4385 * @hw: pointer to the hw struct
4386 * @enable_update: Enable or Disable event posting
4387 * @cmd_details: pointer to command details structure or NULL
4389 * Enable or Disable posting of an event on ARQ when LLDP MIB
4390 * associated with the interface changes
4392 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4394 struct i40e_asq_cmd_details *cmd_details)
4396 struct i40e_aq_desc desc;
4397 struct i40e_aqc_lldp_update_mib *cmd =
4398 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4399 enum i40e_status_code status;
4401 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4404 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4406 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4412 * i40e_aq_restore_lldp
4413 * @hw: pointer to the hw struct
4414 * @setting: pointer to factory setting variable or NULL
4415 * @restore: True if factory settings should be restored
4416 * @cmd_details: pointer to command details structure or NULL
4418 * Restore LLDP Agent factory settings if @restore set to True. In other case
4419 * only returns factory setting in AQ response.
4421 enum i40e_status_code
4422 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4423 struct i40e_asq_cmd_details *cmd_details)
4425 struct i40e_aq_desc desc;
4426 struct i40e_aqc_lldp_restore *cmd =
4427 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4428 enum i40e_status_code status;
4430 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4431 i40e_debug(hw, I40E_DEBUG_ALL,
4432 "Restore LLDP not supported by current FW version.\n");
4433 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4436 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4439 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4441 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4444 *setting = cmd->command & 1;
4451 * @hw: pointer to the hw struct
4452 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4453 * @persist: True if stop of LLDP should be persistent across power cycles
4454 * @cmd_details: pointer to command details structure or NULL
4456 * Stop or Shutdown the embedded LLDP Agent
4458 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4460 struct i40e_asq_cmd_details *cmd_details)
4462 struct i40e_aq_desc desc;
4463 struct i40e_aqc_lldp_stop *cmd =
4464 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4465 enum i40e_status_code status;
4467 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4470 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4473 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4474 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4476 i40e_debug(hw, I40E_DEBUG_ALL,
4477 "Persistent Stop LLDP not supported by current FW version.\n");
4480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4486 * i40e_aq_start_lldp
4487 * @hw: pointer to the hw struct
4488 * @persist: True if start of LLDP should be persistent across power cycles
4489 * @cmd_details: pointer to command details structure or NULL
4491 * Start the embedded LLDP Agent on all ports.
4493 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4495 struct i40e_asq_cmd_details *cmd_details)
4497 struct i40e_aq_desc desc;
4498 struct i40e_aqc_lldp_start *cmd =
4499 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4500 enum i40e_status_code status;
4502 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4504 cmd->command = I40E_AQ_LLDP_AGENT_START;
4507 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4508 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4510 i40e_debug(hw, I40E_DEBUG_ALL,
4511 "Persistent Start LLDP not supported by current FW version.\n");
4514 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4520 * i40e_aq_set_dcb_parameters
4521 * @hw: pointer to the hw struct
4522 * @cmd_details: pointer to command details structure or NULL
4523 * @dcb_enable: True if DCB configuration needs to be applied
4526 enum i40e_status_code
4527 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4528 struct i40e_asq_cmd_details *cmd_details)
4530 struct i40e_aq_desc desc;
4531 struct i40e_aqc_set_dcb_parameters *cmd =
4532 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4533 enum i40e_status_code status;
4535 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4536 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4538 i40e_fill_default_direct_cmd_desc(&desc,
4539 i40e_aqc_opc_set_dcb_parameters);
4542 cmd->valid_flags = I40E_DCB_VALID;
4543 cmd->command = I40E_AQ_DCB_SET_AGENT;
4545 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4551 * i40e_aq_get_cee_dcb_config
4552 * @hw: pointer to the hw struct
4553 * @buff: response buffer that stores CEE operational configuration
4554 * @buff_size: size of the buffer passed
4555 * @cmd_details: pointer to command details structure or NULL
4557 * Get CEE DCBX mode operational configuration from firmware
4559 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4560 void *buff, u16 buff_size,
4561 struct i40e_asq_cmd_details *cmd_details)
4563 struct i40e_aq_desc desc;
4564 enum i40e_status_code status;
4566 if (buff_size == 0 || !buff)
4567 return I40E_ERR_PARAM;
4569 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4571 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4572 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4579 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4580 * @hw: pointer to the hw struct
4581 * @start_agent: True if DCBx Agent needs to be Started
4582 * False if DCBx Agent needs to be Stopped
4583 * @cmd_details: pointer to command details structure or NULL
4585 * Start/Stop the embedded dcbx Agent
4587 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4589 struct i40e_asq_cmd_details *cmd_details)
4591 struct i40e_aq_desc desc;
4592 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4593 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4595 enum i40e_status_code status;
4597 i40e_fill_default_direct_cmd_desc(&desc,
4598 i40e_aqc_opc_lldp_stop_start_spec_agent);
4601 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4603 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4609 * i40e_aq_add_udp_tunnel
4610 * @hw: pointer to the hw struct
4611 * @udp_port: the UDP port to add in Host byte order
4612 * @protocol_index: protocol index type
4613 * @filter_index: pointer to filter index
4614 * @cmd_details: pointer to command details structure or NULL
4616 * Note: Firmware expects the udp_port value to be in Little Endian format,
4617 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4618 * Little Endian order.
4620 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4621 u16 udp_port, u8 protocol_index,
4623 struct i40e_asq_cmd_details *cmd_details)
4625 struct i40e_aq_desc desc;
4626 struct i40e_aqc_add_udp_tunnel *cmd =
4627 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4628 struct i40e_aqc_del_udp_tunnel_completion *resp =
4629 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4630 enum i40e_status_code status;
4632 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4634 cmd->udp_port = CPU_TO_LE16(udp_port);
4635 cmd->protocol_type = protocol_index;
4637 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4639 if (!status && filter_index)
4640 *filter_index = resp->index;
4646 * i40e_aq_del_udp_tunnel
4647 * @hw: pointer to the hw struct
4648 * @index: filter index
4649 * @cmd_details: pointer to command details structure or NULL
4651 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4652 struct i40e_asq_cmd_details *cmd_details)
4654 struct i40e_aq_desc desc;
4655 struct i40e_aqc_remove_udp_tunnel *cmd =
4656 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4657 enum i40e_status_code status;
4659 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4663 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4669 * i40e_aq_get_switch_resource_alloc (0x0204)
4670 * @hw: pointer to the hw struct
4671 * @num_entries: pointer to u8 to store the number of resource entries returned
4672 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4673 * to store the resource information for all resource types. Each
4674 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4675 * @count: size, in bytes, of the buffer provided
4676 * @cmd_details: pointer to command details structure or NULL
4678 * Query the resources allocated to a function.
4680 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4682 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4684 struct i40e_asq_cmd_details *cmd_details)
4686 struct i40e_aq_desc desc;
4687 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4688 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4689 enum i40e_status_code status;
4690 u16 length = count * sizeof(*buf);
4692 i40e_fill_default_direct_cmd_desc(&desc,
4693 i40e_aqc_opc_get_switch_resource_alloc);
4695 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4696 if (length > I40E_AQ_LARGE_BUF)
4697 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4699 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4701 if (!status && num_entries)
4702 *num_entries = cmd_resp->num_entries;
4708 * i40e_aq_delete_element - Delete switch element
4709 * @hw: pointer to the hw struct
4710 * @seid: the SEID to delete from the switch
4711 * @cmd_details: pointer to command details structure or NULL
4713 * This deletes a switch element from the switch.
4715 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4716 struct i40e_asq_cmd_details *cmd_details)
4718 struct i40e_aq_desc desc;
4719 struct i40e_aqc_switch_seid *cmd =
4720 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4721 enum i40e_status_code status;
4724 return I40E_ERR_PARAM;
4726 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4728 cmd->seid = CPU_TO_LE16(seid);
4730 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4736 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4737 * @hw: pointer to the hw struct
4738 * @flags: component flags
4739 * @mac_seid: uplink seid (MAC SEID)
4740 * @vsi_seid: connected vsi seid
4741 * @ret_seid: seid of create pv component
4743 * This instantiates an i40e port virtualizer with specified flags.
4744 * Depending on specified flags the port virtualizer can act as a
4745 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4747 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4748 u16 mac_seid, u16 vsi_seid,
4751 struct i40e_aq_desc desc;
4752 struct i40e_aqc_add_update_pv *cmd =
4753 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4754 struct i40e_aqc_add_update_pv_completion *resp =
4755 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4756 enum i40e_status_code status;
4759 return I40E_ERR_PARAM;
4761 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4762 cmd->command_flags = CPU_TO_LE16(flags);
4763 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4764 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4766 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4767 if (!status && ret_seid)
4768 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4774 * i40e_aq_add_tag - Add an S/E-tag
4775 * @hw: pointer to the hw struct
4776 * @direct_to_queue: should s-tag direct flow to a specific queue
4777 * @vsi_seid: VSI SEID to use this tag
4778 * @tag: value of the tag
4779 * @queue_num: queue number, only valid is direct_to_queue is true
4780 * @tags_used: return value, number of tags in use by this PF
4781 * @tags_free: return value, number of unallocated tags
4782 * @cmd_details: pointer to command details structure or NULL
4784 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4785 * the number of tags allocated by the PF, and the number of unallocated
4788 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4789 u16 vsi_seid, u16 tag, u16 queue_num,
4790 u16 *tags_used, u16 *tags_free,
4791 struct i40e_asq_cmd_details *cmd_details)
4793 struct i40e_aq_desc desc;
4794 struct i40e_aqc_add_tag *cmd =
4795 (struct i40e_aqc_add_tag *)&desc.params.raw;
4796 struct i40e_aqc_add_remove_tag_completion *resp =
4797 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4798 enum i40e_status_code status;
4801 return I40E_ERR_PARAM;
4803 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4805 cmd->seid = CPU_TO_LE16(vsi_seid);
4806 cmd->tag = CPU_TO_LE16(tag);
4807 if (direct_to_queue) {
4808 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4809 cmd->queue_number = CPU_TO_LE16(queue_num);
4812 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4815 if (tags_used != NULL)
4816 *tags_used = LE16_TO_CPU(resp->tags_used);
4817 if (tags_free != NULL)
4818 *tags_free = LE16_TO_CPU(resp->tags_free);
4825 * i40e_aq_remove_tag - Remove an S- or E-tag
4826 * @hw: pointer to the hw struct
4827 * @vsi_seid: VSI SEID this tag is associated with
4828 * @tag: value of the S-tag to delete
4829 * @tags_used: return value, number of tags in use by this PF
4830 * @tags_free: return value, number of unallocated tags
4831 * @cmd_details: pointer to command details structure or NULL
4833 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4834 * the number of tags allocated by the PF, and the number of unallocated
4837 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4838 u16 tag, u16 *tags_used, u16 *tags_free,
4839 struct i40e_asq_cmd_details *cmd_details)
4841 struct i40e_aq_desc desc;
4842 struct i40e_aqc_remove_tag *cmd =
4843 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4844 struct i40e_aqc_add_remove_tag_completion *resp =
4845 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4846 enum i40e_status_code status;
4849 return I40E_ERR_PARAM;
4851 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4853 cmd->seid = CPU_TO_LE16(vsi_seid);
4854 cmd->tag = CPU_TO_LE16(tag);
4856 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4859 if (tags_used != NULL)
4860 *tags_used = LE16_TO_CPU(resp->tags_used);
4861 if (tags_free != NULL)
4862 *tags_free = LE16_TO_CPU(resp->tags_free);
4869 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4870 * @hw: pointer to the hw struct
4871 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4872 * @etag: value of E-tag to add
4873 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4874 * @buf: address of indirect buffer
4875 * @tags_used: return value, number of E-tags in use by this port
4876 * @tags_free: return value, number of unallocated M-tags
4877 * @cmd_details: pointer to command details structure or NULL
4879 * This associates a multicast E-tag to a port virtualizer. It will return
4880 * the number of tags allocated by the PF, and the number of unallocated
4883 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4884 * num_tags_in_buf long.
4886 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4887 u16 etag, u8 num_tags_in_buf, void *buf,
4888 u16 *tags_used, u16 *tags_free,
4889 struct i40e_asq_cmd_details *cmd_details)
4891 struct i40e_aq_desc desc;
4892 struct i40e_aqc_add_remove_mcast_etag *cmd =
4893 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4894 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4895 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4896 enum i40e_status_code status;
4897 u16 length = sizeof(u16) * num_tags_in_buf;
4899 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4900 return I40E_ERR_PARAM;
4902 i40e_fill_default_direct_cmd_desc(&desc,
4903 i40e_aqc_opc_add_multicast_etag);
4905 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4906 cmd->etag = CPU_TO_LE16(etag);
4907 cmd->num_unicast_etags = num_tags_in_buf;
4909 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4911 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4914 if (tags_used != NULL)
4915 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4916 if (tags_free != NULL)
4917 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4924 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4925 * @hw: pointer to the hw struct
4926 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4927 * @etag: value of the E-tag to remove
4928 * @tags_used: return value, number of tags in use by this port
4929 * @tags_free: return value, number of unallocated tags
4930 * @cmd_details: pointer to command details structure or NULL
4932 * This deletes an E-tag from the port virtualizer. It will return
4933 * the number of tags allocated by the port, and the number of unallocated
4936 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4937 u16 etag, u16 *tags_used, u16 *tags_free,
4938 struct i40e_asq_cmd_details *cmd_details)
4940 struct i40e_aq_desc desc;
4941 struct i40e_aqc_add_remove_mcast_etag *cmd =
4942 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4943 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4944 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4945 enum i40e_status_code status;
4949 return I40E_ERR_PARAM;
4951 i40e_fill_default_direct_cmd_desc(&desc,
4952 i40e_aqc_opc_remove_multicast_etag);
4954 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4955 cmd->etag = CPU_TO_LE16(etag);
4957 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4960 if (tags_used != NULL)
4961 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4962 if (tags_free != NULL)
4963 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4970 * i40e_aq_update_tag - Update an S/E-tag
4971 * @hw: pointer to the hw struct
4972 * @vsi_seid: VSI SEID using this S-tag
4973 * @old_tag: old tag value
4974 * @new_tag: new tag value
4975 * @tags_used: return value, number of tags in use by this PF
4976 * @tags_free: return value, number of unallocated tags
4977 * @cmd_details: pointer to command details structure or NULL
4979 * This updates the value of the tag currently attached to this VSI
4980 * in the switch complex. It will return the number of tags allocated
4981 * by the PF, and the number of unallocated tags available.
4983 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4984 u16 old_tag, u16 new_tag, u16 *tags_used,
4986 struct i40e_asq_cmd_details *cmd_details)
4988 struct i40e_aq_desc desc;
4989 struct i40e_aqc_update_tag *cmd =
4990 (struct i40e_aqc_update_tag *)&desc.params.raw;
4991 struct i40e_aqc_update_tag_completion *resp =
4992 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4993 enum i40e_status_code status;
4996 return I40E_ERR_PARAM;
4998 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
5000 cmd->seid = CPU_TO_LE16(vsi_seid);
5001 cmd->old_tag = CPU_TO_LE16(old_tag);
5002 cmd->new_tag = CPU_TO_LE16(new_tag);
5004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5007 if (tags_used != NULL)
5008 *tags_used = LE16_TO_CPU(resp->tags_used);
5009 if (tags_free != NULL)
5010 *tags_free = LE16_TO_CPU(resp->tags_free);
5017 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5018 * @hw: pointer to the hw struct
5019 * @tcmap: TC map for request/release any ignore PFC condition
5020 * @request: request or release ignore PFC condition
5021 * @tcmap_ret: return TCs for which PFC is currently ignored
5022 * @cmd_details: pointer to command details structure or NULL
5024 * This sends out request/release to ignore PFC condition for a TC.
5025 * It will return the TCs for which PFC is currently ignored.
5027 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5028 bool request, u8 *tcmap_ret,
5029 struct i40e_asq_cmd_details *cmd_details)
5031 struct i40e_aq_desc desc;
5032 struct i40e_aqc_pfc_ignore *cmd_resp =
5033 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5034 enum i40e_status_code status;
5036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5039 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5041 cmd_resp->tc_bitmap = tcmap;
5043 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5046 if (tcmap_ret != NULL)
5047 *tcmap_ret = cmd_resp->tc_bitmap;
5054 * i40e_aq_dcb_updated - DCB Updated Command
5055 * @hw: pointer to the hw struct
5056 * @cmd_details: pointer to command details structure or NULL
5058 * When LLDP is handled in PF this command is used by the PF
5059 * to notify EMP that a DCB setting is modified.
5060 * When LLDP is handled in EMP this command is used by the PF
5061 * to notify EMP whenever one of the following parameters get
5063 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5064 * - PCIRTT in PRTDCB_GENC.PCIRTT
5065 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5066 * EMP will return when the shared RPB settings have been
5067 * recomputed and modified. The retval field in the descriptor
5068 * will be set to 0 when RPB is modified.
5070 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5071 struct i40e_asq_cmd_details *cmd_details)
5073 struct i40e_aq_desc desc;
5074 enum i40e_status_code status;
5076 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5078 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5084 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5085 * @hw: pointer to the hw struct
5086 * @seid: defines the SEID of the switch for which the stats are requested
5087 * @vlan_id: the VLAN ID for which the statistics are requested
5088 * @stat_index: index of the statistics counters block assigned to this VLAN
5089 * @cmd_details: pointer to command details structure or NULL
5091 * XL710 supports 128 smonVlanStats counters.This command is used to
5092 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5095 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5096 u16 vlan_id, u16 *stat_index,
5097 struct i40e_asq_cmd_details *cmd_details)
5099 struct i40e_aq_desc desc;
5100 struct i40e_aqc_add_remove_statistics *cmd_resp =
5101 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5102 enum i40e_status_code status;
5104 if ((seid == 0) || (stat_index == NULL))
5105 return I40E_ERR_PARAM;
5107 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5109 cmd_resp->seid = CPU_TO_LE16(seid);
5110 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5112 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5114 if (!status && stat_index)
5115 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5121 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5122 * @hw: pointer to the hw struct
5123 * @seid: defines the SEID of the switch for which the stats are requested
5124 * @vlan_id: the VLAN ID for which the statistics are requested
5125 * @stat_index: index of the statistics counters block assigned to this VLAN
5126 * @cmd_details: pointer to command details structure or NULL
5128 * XL710 supports 128 smonVlanStats counters.This command is used to
5129 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5132 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5133 u16 vlan_id, u16 stat_index,
5134 struct i40e_asq_cmd_details *cmd_details)
5136 struct i40e_aq_desc desc;
5137 struct i40e_aqc_add_remove_statistics *cmd =
5138 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5139 enum i40e_status_code status;
5142 return I40E_ERR_PARAM;
5144 i40e_fill_default_direct_cmd_desc(&desc,
5145 i40e_aqc_opc_remove_statistics);
5147 cmd->seid = CPU_TO_LE16(seid);
5148 cmd->vlan = CPU_TO_LE16(vlan_id);
5149 cmd->stat_index = CPU_TO_LE16(stat_index);
5151 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5157 * i40e_aq_set_port_parameters - set physical port parameters.
5158 * @hw: pointer to the hw struct
5159 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5160 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5161 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5162 * @double_vlan: if set double VLAN is enabled
5163 * @cmd_details: pointer to command details structure or NULL
5165 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5166 u16 bad_frame_vsi, bool save_bad_pac,
5167 bool pad_short_pac, bool double_vlan,
5168 struct i40e_asq_cmd_details *cmd_details)
5170 struct i40e_aqc_set_port_parameters *cmd;
5171 enum i40e_status_code status;
5172 struct i40e_aq_desc desc;
5173 u16 command_flags = 0;
5175 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5177 i40e_fill_default_direct_cmd_desc(&desc,
5178 i40e_aqc_opc_set_port_parameters);
5180 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5182 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5184 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5186 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5187 cmd->command_flags = CPU_TO_LE16(command_flags);
5189 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5195 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5196 * @hw: pointer to the hw struct
5197 * @seid: seid for the physical port/switching component/vsi
5198 * @buff: Indirect buffer to hold data parameters and response
5199 * @buff_size: Indirect buffer size
5200 * @opcode: Tx scheduler AQ command opcode
5201 * @cmd_details: pointer to command details structure or NULL
5203 * Generic command handler for Tx scheduler AQ commands
5205 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5206 void *buff, u16 buff_size,
5207 enum i40e_admin_queue_opc opcode,
5208 struct i40e_asq_cmd_details *cmd_details)
5210 struct i40e_aq_desc desc;
5211 struct i40e_aqc_tx_sched_ind *cmd =
5212 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5213 enum i40e_status_code status;
5214 bool cmd_param_flag = false;
5217 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5218 case i40e_aqc_opc_configure_vsi_tc_bw:
5219 case i40e_aqc_opc_enable_switching_comp_ets:
5220 case i40e_aqc_opc_modify_switching_comp_ets:
5221 case i40e_aqc_opc_disable_switching_comp_ets:
5222 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5223 case i40e_aqc_opc_configure_switching_comp_bw_config:
5224 cmd_param_flag = true;
5226 case i40e_aqc_opc_query_vsi_bw_config:
5227 case i40e_aqc_opc_query_vsi_ets_sla_config:
5228 case i40e_aqc_opc_query_switching_comp_ets_config:
5229 case i40e_aqc_opc_query_port_ets_config:
5230 case i40e_aqc_opc_query_switching_comp_bw_config:
5231 cmd_param_flag = false;
5234 return I40E_ERR_PARAM;
5237 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5239 /* Indirect command */
5240 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5242 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5243 if (buff_size > I40E_AQ_LARGE_BUF)
5244 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5246 desc.datalen = CPU_TO_LE16(buff_size);
5248 cmd->vsi_seid = CPU_TO_LE16(seid);
5250 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5256 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5257 * @hw: pointer to the hw struct
5259 * @credit: BW limit credits (0 = disabled)
5260 * @max_credit: Max BW limit credits
5261 * @cmd_details: pointer to command details structure or NULL
5263 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5264 u16 seid, u16 credit, u8 max_credit,
5265 struct i40e_asq_cmd_details *cmd_details)
5267 struct i40e_aq_desc desc;
5268 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5269 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5270 enum i40e_status_code status;
5272 i40e_fill_default_direct_cmd_desc(&desc,
5273 i40e_aqc_opc_configure_vsi_bw_limit);
5275 cmd->vsi_seid = CPU_TO_LE16(seid);
5276 cmd->credit = CPU_TO_LE16(credit);
5277 cmd->max_credit = max_credit;
5279 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5285 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5286 * @hw: pointer to the hw struct
5287 * @seid: switching component seid
5288 * @credit: BW limit credits (0 = disabled)
5289 * @max_bw: Max BW limit credits
5290 * @cmd_details: pointer to command details structure or NULL
5292 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5293 u16 seid, u16 credit, u8 max_bw,
5294 struct i40e_asq_cmd_details *cmd_details)
5296 struct i40e_aq_desc desc;
5297 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5298 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5299 enum i40e_status_code status;
5301 i40e_fill_default_direct_cmd_desc(&desc,
5302 i40e_aqc_opc_configure_switching_comp_bw_limit);
5304 cmd->seid = CPU_TO_LE16(seid);
5305 cmd->credit = CPU_TO_LE16(credit);
5306 cmd->max_bw = max_bw;
5308 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5314 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5315 * @hw: pointer to the hw struct
5317 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5318 * @cmd_details: pointer to command details structure or NULL
5320 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5322 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5323 struct i40e_asq_cmd_details *cmd_details)
5325 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5326 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5331 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5332 * @hw: pointer to the hw struct
5334 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5335 * @cmd_details: pointer to command details structure or NULL
5337 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5339 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5340 struct i40e_asq_cmd_details *cmd_details)
5342 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5343 i40e_aqc_opc_configure_vsi_tc_bw,
5348 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5349 * @hw: pointer to the hw struct
5350 * @seid: seid of the switching component connected to Physical Port
5351 * @ets_data: Buffer holding ETS parameters
5352 * @opcode: Tx scheduler AQ command opcode
5353 * @cmd_details: pointer to command details structure or NULL
5355 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5357 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5358 enum i40e_admin_queue_opc opcode,
5359 struct i40e_asq_cmd_details *cmd_details)
5361 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5362 sizeof(*ets_data), opcode, cmd_details);
5366 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5367 * @hw: pointer to the hw struct
5368 * @seid: seid of the switching component
5369 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5370 * @cmd_details: pointer to command details structure or NULL
5372 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5374 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5375 struct i40e_asq_cmd_details *cmd_details)
5377 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5378 i40e_aqc_opc_configure_switching_comp_bw_config,
5383 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5384 * @hw: pointer to the hw struct
5385 * @seid: seid of the switching component
5386 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5387 * @cmd_details: pointer to command details structure or NULL
5389 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5390 struct i40e_hw *hw, u16 seid,
5391 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5392 struct i40e_asq_cmd_details *cmd_details)
5394 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5395 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5400 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5401 * @hw: pointer to the hw struct
5402 * @seid: seid of the VSI
5403 * @bw_data: Buffer to hold VSI BW configuration
5404 * @cmd_details: pointer to command details structure or NULL
5406 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5408 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5409 struct i40e_asq_cmd_details *cmd_details)
5411 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5412 i40e_aqc_opc_query_vsi_bw_config,
5417 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5418 * @hw: pointer to the hw struct
5419 * @seid: seid of the VSI
5420 * @bw_data: Buffer to hold VSI BW configuration per TC
5421 * @cmd_details: pointer to command details structure or NULL
5423 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5425 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5426 struct i40e_asq_cmd_details *cmd_details)
5428 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5429 i40e_aqc_opc_query_vsi_ets_sla_config,
5434 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5435 * @hw: pointer to the hw struct
5436 * @seid: seid of the switching component
5437 * @bw_data: Buffer to hold switching component's per TC BW config
5438 * @cmd_details: pointer to command details structure or NULL
5440 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5442 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5443 struct i40e_asq_cmd_details *cmd_details)
5445 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5446 i40e_aqc_opc_query_switching_comp_ets_config,
5451 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5452 * @hw: pointer to the hw struct
5453 * @seid: seid of the VSI or switching component connected to Physical Port
5454 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5455 * @cmd_details: pointer to command details structure or NULL
5457 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5459 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5460 struct i40e_asq_cmd_details *cmd_details)
5462 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5463 i40e_aqc_opc_query_port_ets_config,
5468 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5469 * @hw: pointer to the hw struct
5470 * @seid: seid of the switching component
5471 * @bw_data: Buffer to hold switching component's BW configuration
5472 * @cmd_details: pointer to command details structure or NULL
5474 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5476 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5477 struct i40e_asq_cmd_details *cmd_details)
5479 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5480 i40e_aqc_opc_query_switching_comp_bw_config,
5485 * i40e_validate_filter_settings
5486 * @hw: pointer to the hardware structure
5487 * @settings: Filter control settings
5489 * Check and validate the filter control settings passed.
5490 * The function checks for the valid filter/context sizes being
5491 * passed for FCoE and PE.
5493 * Returns I40E_SUCCESS if the values passed are valid and within
5494 * range else returns an error.
5496 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5497 struct i40e_filter_control_settings *settings)
5499 u32 fcoe_cntx_size, fcoe_filt_size;
5500 u32 pe_cntx_size, pe_filt_size;
5505 /* Validate FCoE settings passed */
5506 switch (settings->fcoe_filt_num) {
5507 case I40E_HASH_FILTER_SIZE_1K:
5508 case I40E_HASH_FILTER_SIZE_2K:
5509 case I40E_HASH_FILTER_SIZE_4K:
5510 case I40E_HASH_FILTER_SIZE_8K:
5511 case I40E_HASH_FILTER_SIZE_16K:
5512 case I40E_HASH_FILTER_SIZE_32K:
5513 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5514 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5517 return I40E_ERR_PARAM;
5520 switch (settings->fcoe_cntx_num) {
5521 case I40E_DMA_CNTX_SIZE_512:
5522 case I40E_DMA_CNTX_SIZE_1K:
5523 case I40E_DMA_CNTX_SIZE_2K:
5524 case I40E_DMA_CNTX_SIZE_4K:
5525 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5526 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5529 return I40E_ERR_PARAM;
5532 /* Validate PE settings passed */
5533 switch (settings->pe_filt_num) {
5534 case I40E_HASH_FILTER_SIZE_1K:
5535 case I40E_HASH_FILTER_SIZE_2K:
5536 case I40E_HASH_FILTER_SIZE_4K:
5537 case I40E_HASH_FILTER_SIZE_8K:
5538 case I40E_HASH_FILTER_SIZE_16K:
5539 case I40E_HASH_FILTER_SIZE_32K:
5540 case I40E_HASH_FILTER_SIZE_64K:
5541 case I40E_HASH_FILTER_SIZE_128K:
5542 case I40E_HASH_FILTER_SIZE_256K:
5543 case I40E_HASH_FILTER_SIZE_512K:
5544 case I40E_HASH_FILTER_SIZE_1M:
5545 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5546 pe_filt_size <<= (u32)settings->pe_filt_num;
5549 return I40E_ERR_PARAM;
5552 switch (settings->pe_cntx_num) {
5553 case I40E_DMA_CNTX_SIZE_512:
5554 case I40E_DMA_CNTX_SIZE_1K:
5555 case I40E_DMA_CNTX_SIZE_2K:
5556 case I40E_DMA_CNTX_SIZE_4K:
5557 case I40E_DMA_CNTX_SIZE_8K:
5558 case I40E_DMA_CNTX_SIZE_16K:
5559 case I40E_DMA_CNTX_SIZE_32K:
5560 case I40E_DMA_CNTX_SIZE_64K:
5561 case I40E_DMA_CNTX_SIZE_128K:
5562 case I40E_DMA_CNTX_SIZE_256K:
5563 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5564 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5567 return I40E_ERR_PARAM;
5570 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5571 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5572 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5573 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5574 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5575 return I40E_ERR_INVALID_SIZE;
5577 return I40E_SUCCESS;
5581 * i40e_set_filter_control
5582 * @hw: pointer to the hardware structure
5583 * @settings: Filter control settings
5585 * Set the Queue Filters for PE/FCoE and enable filters required
5586 * for a single PF. It is expected that these settings are programmed
5587 * at the driver initialization time.
5589 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5590 struct i40e_filter_control_settings *settings)
5592 enum i40e_status_code ret = I40E_SUCCESS;
5593 u32 hash_lut_size = 0;
5597 return I40E_ERR_PARAM;
5599 /* Validate the input settings */
5600 ret = i40e_validate_filter_settings(hw, settings);
5604 /* Read the PF Queue Filter control register */
5605 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5607 /* Program required PE hash buckets for the PF */
5608 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5609 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5610 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5611 /* Program required PE contexts for the PF */
5612 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5613 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5614 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5616 /* Program required FCoE hash buckets for the PF */
5617 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5618 val |= ((u32)settings->fcoe_filt_num <<
5619 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5620 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5621 /* Program required FCoE DDP contexts for the PF */
5622 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5623 val |= ((u32)settings->fcoe_cntx_num <<
5624 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5625 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5627 /* Program Hash LUT size for the PF */
5628 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5629 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5631 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5632 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5634 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5635 if (settings->enable_fdir)
5636 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5637 if (settings->enable_ethtype)
5638 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5639 if (settings->enable_macvlan)
5640 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5642 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5644 return I40E_SUCCESS;
5648 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5649 * @hw: pointer to the hw struct
5650 * @mac_addr: MAC address to use in the filter
5651 * @ethtype: Ethertype to use in the filter
5652 * @flags: Flags that needs to be applied to the filter
5653 * @vsi_seid: seid of the control VSI
5654 * @queue: VSI queue number to send the packet to
5655 * @is_add: Add control packet filter if True else remove
5656 * @stats: Structure to hold information on control filter counts
5657 * @cmd_details: pointer to command details structure or NULL
5659 * This command will Add or Remove control packet filter for a control VSI.
5660 * In return it will update the total number of perfect filter count in
5663 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5664 u8 *mac_addr, u16 ethtype, u16 flags,
5665 u16 vsi_seid, u16 queue, bool is_add,
5666 struct i40e_control_filter_stats *stats,
5667 struct i40e_asq_cmd_details *cmd_details)
5669 struct i40e_aq_desc desc;
5670 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5671 (struct i40e_aqc_add_remove_control_packet_filter *)
5673 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5674 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5676 enum i40e_status_code status;
5679 return I40E_ERR_PARAM;
5682 i40e_fill_default_direct_cmd_desc(&desc,
5683 i40e_aqc_opc_add_control_packet_filter);
5684 cmd->queue = CPU_TO_LE16(queue);
5686 i40e_fill_default_direct_cmd_desc(&desc,
5687 i40e_aqc_opc_remove_control_packet_filter);
5691 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5692 I40E_NONDMA_TO_NONDMA);
5694 cmd->etype = CPU_TO_LE16(ethtype);
5695 cmd->flags = CPU_TO_LE16(flags);
5696 cmd->seid = CPU_TO_LE16(vsi_seid);
5698 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5700 if (!status && stats) {
5701 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5702 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5703 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5704 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5711 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5712 * @hw: pointer to the hw struct
5713 * @seid: VSI seid to add ethertype filter from
5715 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5718 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5719 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5720 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5721 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5722 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5723 enum i40e_status_code status;
5725 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5726 seid, 0, true, NULL,
5729 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5733 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5734 * @filters: list of cloud filters
5735 * @filter_count: length of list
5737 * There's an issue in the device where the Geneve VNI layout needs
5738 * to be shifted 1 byte over from the VxLAN VNI
5740 STATIC void i40e_fix_up_geneve_vni(
5741 struct i40e_aqc_cloud_filters_element_data *filters,
5744 struct i40e_aqc_cloud_filters_element_data *f = filters;
5747 for (i = 0; i < filter_count; i++) {
5751 tnl_type = (LE16_TO_CPU(f[i].flags) &
5752 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5753 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5754 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5755 ti = LE32_TO_CPU(f[i].tenant_id);
5756 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5762 * i40e_aq_add_cloud_filters
5763 * @hw: pointer to the hardware structure
5764 * @seid: VSI seid to add cloud filters from
5765 * @filters: Buffer which contains the filters to be added
5766 * @filter_count: number of filters contained in the buffer
5768 * Set the cloud filters for a given VSI. The contents of the
5769 * i40e_aqc_cloud_filters_element_data are filled
5770 * in by the caller of the function.
5773 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5775 struct i40e_aqc_cloud_filters_element_data *filters,
5778 struct i40e_aq_desc desc;
5779 struct i40e_aqc_add_remove_cloud_filters *cmd =
5780 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5781 enum i40e_status_code status;
5784 i40e_fill_default_direct_cmd_desc(&desc,
5785 i40e_aqc_opc_add_cloud_filters);
5787 buff_len = filter_count * sizeof(*filters);
5788 desc.datalen = CPU_TO_LE16(buff_len);
5789 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5790 cmd->num_filters = filter_count;
5791 cmd->seid = CPU_TO_LE16(seid);
5793 i40e_fix_up_geneve_vni(filters, filter_count);
5795 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5801 * i40e_aq_add_cloud_filters_bb
5802 * @hw: pointer to the hardware structure
5803 * @seid: VSI seid to add cloud filters from
5804 * @filters: Buffer which contains the filters in big buffer to be added
5805 * @filter_count: number of filters contained in the buffer
5807 * Set the cloud filters for a given VSI. The contents of the
5808 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5812 enum i40e_status_code
5813 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5814 struct i40e_aqc_cloud_filters_element_bb *filters,
5817 struct i40e_aq_desc desc;
5818 struct i40e_aqc_add_remove_cloud_filters *cmd =
5819 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5820 enum i40e_status_code status;
5824 i40e_fill_default_direct_cmd_desc(&desc,
5825 i40e_aqc_opc_add_cloud_filters);
5827 buff_len = filter_count * sizeof(*filters);
5828 desc.datalen = CPU_TO_LE16(buff_len);
5829 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5830 cmd->num_filters = filter_count;
5831 cmd->seid = CPU_TO_LE16(seid);
5832 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5834 for (i = 0; i < filter_count; i++) {
5838 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5839 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5840 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5842 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5843 * one more byte further than normally used for Tenant ID in
5844 * other tunnel types.
5846 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5847 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5848 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5852 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5858 * i40e_aq_rem_cloud_filters
5859 * @hw: pointer to the hardware structure
5860 * @seid: VSI seid to remove cloud filters from
5861 * @filters: Buffer which contains the filters to be removed
5862 * @filter_count: number of filters contained in the buffer
5864 * Remove the cloud filters for a given VSI. The contents of the
5865 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5869 enum i40e_status_code
5870 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5871 struct i40e_aqc_cloud_filters_element_data *filters,
5874 struct i40e_aq_desc desc;
5875 struct i40e_aqc_add_remove_cloud_filters *cmd =
5876 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5877 enum i40e_status_code status;
5880 i40e_fill_default_direct_cmd_desc(&desc,
5881 i40e_aqc_opc_remove_cloud_filters);
5883 buff_len = filter_count * sizeof(*filters);
5884 desc.datalen = CPU_TO_LE16(buff_len);
5885 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5886 cmd->num_filters = filter_count;
5887 cmd->seid = CPU_TO_LE16(seid);
5889 i40e_fix_up_geneve_vni(filters, filter_count);
5891 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5897 * i40e_aq_rem_cloud_filters_bb
5898 * @hw: pointer to the hardware structure
5899 * @seid: VSI seid to remove cloud filters from
5900 * @filters: Buffer which contains the filters in big buffer to be removed
5901 * @filter_count: number of filters contained in the buffer
5903 * Remove the big buffer cloud filters for a given VSI. The contents of the
5904 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5908 enum i40e_status_code
5909 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5910 struct i40e_aqc_cloud_filters_element_bb *filters,
5913 struct i40e_aq_desc desc;
5914 struct i40e_aqc_add_remove_cloud_filters *cmd =
5915 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5916 enum i40e_status_code status;
5920 i40e_fill_default_direct_cmd_desc(&desc,
5921 i40e_aqc_opc_remove_cloud_filters);
5923 buff_len = filter_count * sizeof(*filters);
5924 desc.datalen = CPU_TO_LE16(buff_len);
5925 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5926 cmd->num_filters = filter_count;
5927 cmd->seid = CPU_TO_LE16(seid);
5928 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5930 for (i = 0; i < filter_count; i++) {
5934 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5935 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5936 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5938 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5939 * one more byte further than normally used for Tenant ID in
5940 * other tunnel types.
5942 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5943 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5944 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5948 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5954 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5955 * @hw: pointer to the hw struct
5956 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5957 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5961 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5962 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5963 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5965 struct i40e_aq_desc desc;
5966 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5967 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5968 enum i40e_status_code status = I40E_SUCCESS;
5971 /* X722 doesn't support this command */
5972 if (hw->mac.type == I40E_MAC_X722)
5973 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5975 /* need FW version greater than 6.00 */
5976 if (hw->aq.fw_maj_ver < 6)
5977 return I40E_NOT_SUPPORTED;
5979 i40e_fill_default_direct_cmd_desc(&desc,
5980 i40e_aqc_opc_replace_cloud_filters);
5982 desc.datalen = CPU_TO_LE16(32);
5983 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5984 cmd->old_filter_type = filters->old_filter_type;
5985 cmd->new_filter_type = filters->new_filter_type;
5986 cmd->valid_flags = filters->valid_flags;
5987 cmd->tr_bit = filters->tr_bit;
5988 cmd->tr_bit2 = filters->tr_bit2;
5990 status = i40e_asq_send_command(hw, &desc, cmd_buf,
5991 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
5993 /* for get cloud filters command */
5994 for (i = 0; i < 32; i += 4) {
5995 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5996 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5997 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5998 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
6006 * i40e_aq_alternate_write
6007 * @hw: pointer to the hardware structure
6008 * @reg_addr0: address of first dword to be read
6009 * @reg_val0: value to be written under 'reg_addr0'
6010 * @reg_addr1: address of second dword to be read
6011 * @reg_val1: value to be written under 'reg_addr1'
6013 * Write one or two dwords to alternate structure. Fields are indicated
6014 * by 'reg_addr0' and 'reg_addr1' register numbers.
6017 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6018 u32 reg_addr0, u32 reg_val0,
6019 u32 reg_addr1, u32 reg_val1)
6021 struct i40e_aq_desc desc;
6022 struct i40e_aqc_alternate_write *cmd_resp =
6023 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6024 enum i40e_status_code status;
6026 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6027 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6028 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6029 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6030 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6032 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6038 * i40e_aq_alternate_write_indirect
6039 * @hw: pointer to the hardware structure
6040 * @addr: address of a first register to be modified
6041 * @dw_count: number of alternate structure fields to write
6042 * @buffer: pointer to the command buffer
6044 * Write 'dw_count' dwords from 'buffer' to alternate structure
6045 * starting at 'addr'.
6048 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6049 u32 addr, u32 dw_count, void *buffer)
6051 struct i40e_aq_desc desc;
6052 struct i40e_aqc_alternate_ind_write *cmd_resp =
6053 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6054 enum i40e_status_code status;
6057 return I40E_ERR_PARAM;
6059 /* Indirect command */
6060 i40e_fill_default_direct_cmd_desc(&desc,
6061 i40e_aqc_opc_alternate_write_indirect);
6063 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6064 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6065 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6066 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6068 cmd_resp->address = CPU_TO_LE32(addr);
6069 cmd_resp->length = CPU_TO_LE32(dw_count);
6071 status = i40e_asq_send_command(hw, &desc, buffer,
6072 I40E_LO_DWORD(4*dw_count), NULL);
6078 * i40e_aq_alternate_read
6079 * @hw: pointer to the hardware structure
6080 * @reg_addr0: address of first dword to be read
6081 * @reg_val0: pointer for data read from 'reg_addr0'
6082 * @reg_addr1: address of second dword to be read
6083 * @reg_val1: pointer for data read from 'reg_addr1'
6085 * Read one or two dwords from alternate structure. Fields are indicated
6086 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6087 * is not passed then only register at 'reg_addr0' is read.
6090 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6091 u32 reg_addr0, u32 *reg_val0,
6092 u32 reg_addr1, u32 *reg_val1)
6094 struct i40e_aq_desc desc;
6095 struct i40e_aqc_alternate_write *cmd_resp =
6096 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6097 enum i40e_status_code status;
6099 if (reg_val0 == NULL)
6100 return I40E_ERR_PARAM;
6102 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6103 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6104 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6106 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6108 if (status == I40E_SUCCESS) {
6109 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6111 if (reg_val1 != NULL)
6112 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6119 * i40e_aq_alternate_read_indirect
6120 * @hw: pointer to the hardware structure
6121 * @addr: address of the alternate structure field
6122 * @dw_count: number of alternate structure fields to read
6123 * @buffer: pointer to the command buffer
6125 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6126 * place them in 'buffer'. The buffer should be allocated by caller.
6129 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6130 u32 addr, u32 dw_count, void *buffer)
6132 struct i40e_aq_desc desc;
6133 struct i40e_aqc_alternate_ind_write *cmd_resp =
6134 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6135 enum i40e_status_code status;
6138 return I40E_ERR_PARAM;
6140 /* Indirect command */
6141 i40e_fill_default_direct_cmd_desc(&desc,
6142 i40e_aqc_opc_alternate_read_indirect);
6144 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6145 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6146 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6147 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6149 cmd_resp->address = CPU_TO_LE32(addr);
6150 cmd_resp->length = CPU_TO_LE32(dw_count);
6152 status = i40e_asq_send_command(hw, &desc, buffer,
6153 I40E_LO_DWORD(4*dw_count), NULL);
6159 * i40e_aq_alternate_clear
6160 * @hw: pointer to the HW structure.
6162 * Clear the alternate structures of the port from which the function
6166 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6168 struct i40e_aq_desc desc;
6169 enum i40e_status_code status;
6171 i40e_fill_default_direct_cmd_desc(&desc,
6172 i40e_aqc_opc_alternate_clear_port);
6174 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6180 * i40e_aq_alternate_write_done
6181 * @hw: pointer to the HW structure.
6182 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6183 * @reset_needed: indicates the SW should trigger GLOBAL reset
6185 * Indicates to the FW that alternate structures have been changed.
6188 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6189 u8 bios_mode, bool *reset_needed)
6191 struct i40e_aq_desc desc;
6192 struct i40e_aqc_alternate_write_done *cmd =
6193 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6194 enum i40e_status_code status;
6196 if (reset_needed == NULL)
6197 return I40E_ERR_PARAM;
6199 i40e_fill_default_direct_cmd_desc(&desc,
6200 i40e_aqc_opc_alternate_write_done);
6202 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6204 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6205 if (!status && reset_needed)
6206 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6207 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6213 * i40e_aq_set_oem_mode
6214 * @hw: pointer to the HW structure.
6215 * @oem_mode: the OEM mode to be used
6217 * Sets the device to a specific operating mode. Currently the only supported
6218 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6221 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6224 struct i40e_aq_desc desc;
6225 struct i40e_aqc_alternate_write_done *cmd =
6226 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6227 enum i40e_status_code status;
6229 i40e_fill_default_direct_cmd_desc(&desc,
6230 i40e_aqc_opc_alternate_set_mode);
6232 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6234 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6240 * i40e_aq_resume_port_tx
6241 * @hw: pointer to the hardware structure
6242 * @cmd_details: pointer to command details structure or NULL
6244 * Resume port's Tx traffic
6246 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6247 struct i40e_asq_cmd_details *cmd_details)
6249 struct i40e_aq_desc desc;
6250 enum i40e_status_code status;
6252 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6254 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6260 * i40e_set_pci_config_data - store PCI bus info
6261 * @hw: pointer to hardware structure
6262 * @link_status: the link status word from PCI config space
6264 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6266 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6268 hw->bus.type = i40e_bus_type_pci_express;
6270 switch (link_status & I40E_PCI_LINK_WIDTH) {
6271 case I40E_PCI_LINK_WIDTH_1:
6272 hw->bus.width = i40e_bus_width_pcie_x1;
6274 case I40E_PCI_LINK_WIDTH_2:
6275 hw->bus.width = i40e_bus_width_pcie_x2;
6277 case I40E_PCI_LINK_WIDTH_4:
6278 hw->bus.width = i40e_bus_width_pcie_x4;
6280 case I40E_PCI_LINK_WIDTH_8:
6281 hw->bus.width = i40e_bus_width_pcie_x8;
6284 hw->bus.width = i40e_bus_width_unknown;
6288 switch (link_status & I40E_PCI_LINK_SPEED) {
6289 case I40E_PCI_LINK_SPEED_2500:
6290 hw->bus.speed = i40e_bus_speed_2500;
6292 case I40E_PCI_LINK_SPEED_5000:
6293 hw->bus.speed = i40e_bus_speed_5000;
6295 case I40E_PCI_LINK_SPEED_8000:
6296 hw->bus.speed = i40e_bus_speed_8000;
6299 hw->bus.speed = i40e_bus_speed_unknown;
6305 * i40e_aq_debug_dump
6306 * @hw: pointer to the hardware structure
6307 * @cluster_id: specific cluster to dump
6308 * @table_id: table id within cluster
6309 * @start_index: index of line in the block to read
6310 * @buff_size: dump buffer size
6311 * @buff: dump buffer
6312 * @ret_buff_size: actual buffer size returned
6313 * @ret_next_table: next block to read
6314 * @ret_next_index: next index to read
6315 * @cmd_details: pointer to command details structure or NULL
6317 * Dump internal FW/HW data for debug purposes.
6320 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6321 u8 table_id, u32 start_index, u16 buff_size,
6322 void *buff, u16 *ret_buff_size,
6323 u8 *ret_next_table, u32 *ret_next_index,
6324 struct i40e_asq_cmd_details *cmd_details)
6326 struct i40e_aq_desc desc;
6327 struct i40e_aqc_debug_dump_internals *cmd =
6328 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6329 struct i40e_aqc_debug_dump_internals *resp =
6330 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6331 enum i40e_status_code status;
6333 if (buff_size == 0 || !buff)
6334 return I40E_ERR_PARAM;
6336 i40e_fill_default_direct_cmd_desc(&desc,
6337 i40e_aqc_opc_debug_dump_internals);
6338 /* Indirect Command */
6339 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6340 if (buff_size > I40E_AQ_LARGE_BUF)
6341 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6343 cmd->cluster_id = cluster_id;
6344 cmd->table_id = table_id;
6345 cmd->idx = CPU_TO_LE32(start_index);
6347 desc.datalen = CPU_TO_LE16(buff_size);
6349 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6351 if (ret_buff_size != NULL)
6352 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6353 if (ret_next_table != NULL)
6354 *ret_next_table = resp->table_id;
6355 if (ret_next_index != NULL)
6356 *ret_next_index = LE32_TO_CPU(resp->idx);
6365 * @hw: pointer to the hardware structure
6366 * @enable: state of Energy Efficient Ethernet mode to be set
6368 * Enables or disables Energy Efficient Ethernet (EEE) mode
6369 * accordingly to @enable parameter.
6371 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6373 struct i40e_aq_get_phy_abilities_resp abilities;
6374 struct i40e_aq_set_phy_config config;
6375 enum i40e_status_code status;
6376 __le16 eee_capability;
6378 /* Get initial PHY capabilities */
6379 status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6384 /* Check whether NIC configuration is compatible with Energy Efficient
6385 * Ethernet (EEE) mode.
6387 if (abilities.eee_capability == 0) {
6388 status = I40E_ERR_CONFIG;
6392 /* Cache initial EEE capability */
6393 eee_capability = abilities.eee_capability;
6395 /* Get current configuration */
6396 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6401 /* Cache current configuration */
6402 config.phy_type = abilities.phy_type;
6403 config.link_speed = abilities.link_speed;
6404 config.abilities = abilities.abilities |
6405 I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6406 config.eeer = abilities.eeer_val;
6407 config.low_power_ctrl = abilities.d3_lpan;
6408 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6409 I40E_AQ_PHY_FEC_CONFIG_MASK;
6411 /* Set desired EEE state */
6413 config.eee_capability = eee_capability;
6414 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6416 config.eee_capability = 0;
6417 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6420 /* Save modified config */
6421 status = i40e_aq_set_phy_config(hw, &config, NULL);
6427 * i40e_read_bw_from_alt_ram
6428 * @hw: pointer to the hardware structure
6429 * @max_bw: pointer for max_bw read
6430 * @min_bw: pointer for min_bw read
6431 * @min_valid: pointer for bool that is true if min_bw is a valid value
6432 * @max_valid: pointer for bool that is true if max_bw is a valid value
6434 * Read bw from the alternate ram for the given pf
6436 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6437 u32 *max_bw, u32 *min_bw,
6438 bool *min_valid, bool *max_valid)
6440 enum i40e_status_code status;
6441 u32 max_bw_addr, min_bw_addr;
6443 /* Calculate the address of the min/max bw registers */
6444 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6445 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6446 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6447 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6448 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6449 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6451 /* Read the bandwidths from alt ram */
6452 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6453 min_bw_addr, min_bw);
6455 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6460 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6469 * i40e_aq_configure_partition_bw
6470 * @hw: pointer to the hardware structure
6471 * @bw_data: Buffer holding valid pfs and bw limits
6472 * @cmd_details: pointer to command details
6474 * Configure partitions guaranteed/max bw
6476 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6477 struct i40e_aqc_configure_partition_bw_data *bw_data,
6478 struct i40e_asq_cmd_details *cmd_details)
6480 enum i40e_status_code status;
6481 struct i40e_aq_desc desc;
6482 u16 bwd_size = sizeof(*bw_data);
6484 i40e_fill_default_direct_cmd_desc(&desc,
6485 i40e_aqc_opc_configure_partition_bw);
6487 /* Indirect command */
6488 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6489 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6491 desc.datalen = CPU_TO_LE16(bwd_size);
6493 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6499 * i40e_read_phy_register_clause22
6500 * @hw: pointer to the HW structure
6501 * @reg: register address in the page
6502 * @phy_addr: PHY address on MDIO interface
6503 * @value: PHY register value
6505 * Reads specified PHY register value
6507 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6508 u16 reg, u8 phy_addr, u16 *value)
6510 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6511 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6515 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6516 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6517 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6518 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6519 (I40E_GLGEN_MSCA_MDICMD_MASK);
6520 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6522 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6523 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6524 status = I40E_SUCCESS;
6527 i40e_usec_delay(10);
6532 i40e_debug(hw, I40E_DEBUG_PHY,
6533 "PHY: Can't write command to external PHY.\n");
6535 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6536 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6537 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6544 * i40e_write_phy_register_clause22
6545 * @hw: pointer to the HW structure
6546 * @reg: register address in the page
6547 * @phy_addr: PHY address on MDIO interface
6548 * @value: PHY register value
6550 * Writes specified PHY register value
6552 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6553 u16 reg, u8 phy_addr, u16 value)
6555 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6556 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6560 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6561 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6563 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6564 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6565 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6566 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6567 (I40E_GLGEN_MSCA_MDICMD_MASK);
6569 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6571 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6572 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6573 status = I40E_SUCCESS;
6576 i40e_usec_delay(10);
6584 * i40e_read_phy_register_clause45
6585 * @hw: pointer to the HW structure
6586 * @page: registers page number
6587 * @reg: register address in the page
6588 * @phy_addr: PHY address on MDIO interface
6589 * @value: PHY register value
6591 * Reads specified PHY register value
6593 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6594 u8 page, u16 reg, u8 phy_addr, u16 *value)
6596 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6599 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6601 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6602 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6603 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6604 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6605 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6606 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6607 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6608 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6610 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6611 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6612 status = I40E_SUCCESS;
6615 i40e_usec_delay(10);
6620 i40e_debug(hw, I40E_DEBUG_PHY,
6621 "PHY: Can't write command to external PHY.\n");
6625 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6626 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6627 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6628 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6629 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6630 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6631 status = I40E_ERR_TIMEOUT;
6633 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6635 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6636 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6637 status = I40E_SUCCESS;
6640 i40e_usec_delay(10);
6645 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6646 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6647 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6649 i40e_debug(hw, I40E_DEBUG_PHY,
6650 "PHY: Can't read register value from external PHY.\n");
6658 * i40e_write_phy_register_clause45
6659 * @hw: pointer to the HW structure
6660 * @page: registers page number
6661 * @reg: register address in the page
6662 * @phy_addr: PHY address on MDIO interface
6663 * @value: PHY register value
6665 * Writes value to specified PHY register
6667 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6668 u8 page, u16 reg, u8 phy_addr, u16 value)
6670 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6673 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6675 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6676 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6677 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6678 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6679 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6680 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6681 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6682 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6684 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6685 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6686 status = I40E_SUCCESS;
6689 i40e_usec_delay(10);
6693 i40e_debug(hw, I40E_DEBUG_PHY,
6694 "PHY: Can't write command to external PHY.\n");
6698 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6699 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6701 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6702 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6703 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6704 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6705 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6706 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6707 status = I40E_ERR_TIMEOUT;
6709 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6711 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6712 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6713 status = I40E_SUCCESS;
6716 i40e_usec_delay(10);
6725 * i40e_write_phy_register
6726 * @hw: pointer to the HW structure
6727 * @page: registers page number
6728 * @reg: register address in the page
6729 * @phy_addr: PHY address on MDIO interface
6730 * @value: PHY register value
6732 * Writes value to specified PHY register
6734 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6735 u8 page, u16 reg, u8 phy_addr, u16 value)
6737 enum i40e_status_code status;
6739 switch (hw->device_id) {
6740 case I40E_DEV_ID_1G_BASE_T_X722:
6741 status = i40e_write_phy_register_clause22(hw,
6742 reg, phy_addr, value);
6744 case I40E_DEV_ID_10G_BASE_T:
6745 case I40E_DEV_ID_10G_BASE_T4:
6746 case I40E_DEV_ID_10G_BASE_T_BC:
6747 case I40E_DEV_ID_5G_BASE_T_BC:
6748 case I40E_DEV_ID_10G_BASE_T_X722:
6749 case I40E_DEV_ID_25G_B:
6750 case I40E_DEV_ID_25G_SFP28:
6751 status = i40e_write_phy_register_clause45(hw,
6752 page, reg, phy_addr, value);
6755 status = I40E_ERR_UNKNOWN_PHY;
6763 * i40e_read_phy_register
6764 * @hw: pointer to the HW structure
6765 * @page: registers page number
6766 * @reg: register address in the page
6767 * @phy_addr: PHY address on MDIO interface
6768 * @value: PHY register value
6770 * Reads specified PHY register value
6772 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6773 u8 page, u16 reg, u8 phy_addr, u16 *value)
6775 enum i40e_status_code status;
6777 switch (hw->device_id) {
6778 case I40E_DEV_ID_1G_BASE_T_X722:
6779 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6782 case I40E_DEV_ID_10G_BASE_T:
6783 case I40E_DEV_ID_10G_BASE_T4:
6784 case I40E_DEV_ID_5G_BASE_T_BC:
6785 case I40E_DEV_ID_10G_BASE_T_X722:
6786 case I40E_DEV_ID_25G_B:
6787 case I40E_DEV_ID_25G_SFP28:
6788 status = i40e_read_phy_register_clause45(hw, page, reg,
6792 status = I40E_ERR_UNKNOWN_PHY;
6800 * i40e_get_phy_address
6801 * @hw: pointer to the HW structure
6802 * @dev_num: PHY port num that address we want
6804 * Gets PHY address for current port
6806 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6808 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6809 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6811 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6815 * i40e_blink_phy_led
6816 * @hw: pointer to the HW structure
6817 * @time: time how long led will blinks in secs
6818 * @interval: gap between LED on and off in msecs
6820 * Blinks PHY link LED
6822 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6823 u32 time, u32 interval)
6825 enum i40e_status_code status = I40E_SUCCESS;
6830 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6834 i = rd32(hw, I40E_PFGEN_PORTNUM);
6835 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6836 phy_addr = i40e_get_phy_address(hw, port_num);
6838 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6840 status = i40e_read_phy_register_clause45(hw,
6841 I40E_PHY_COM_REG_PAGE,
6845 goto phy_blinking_end;
6847 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6849 status = i40e_write_phy_register_clause45(hw,
6850 I40E_PHY_COM_REG_PAGE,
6854 goto phy_blinking_end;
6859 if (time > 0 && interval > 0) {
6860 for (i = 0; i < time * 1000; i += interval) {
6861 status = i40e_read_phy_register_clause45(hw,
6862 I40E_PHY_COM_REG_PAGE,
6863 led_addr, phy_addr, &led_reg);
6865 goto restore_config;
6866 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6869 led_reg = I40E_PHY_LED_MANUAL_ON;
6870 status = i40e_write_phy_register_clause45(hw,
6871 I40E_PHY_COM_REG_PAGE,
6872 led_addr, phy_addr, led_reg);
6874 goto restore_config;
6875 i40e_msec_delay(interval);
6880 status = i40e_write_phy_register_clause45(hw,
6881 I40E_PHY_COM_REG_PAGE,
6882 led_addr, phy_addr, led_ctl);
6889 * i40e_led_get_reg - read LED register
6890 * @hw: pointer to the HW structure
6891 * @led_addr: LED register address
6892 * @reg_val: read register value
6894 enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6897 enum i40e_status_code status;
6901 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6902 status = i40e_aq_get_phy_register(hw,
6903 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6904 I40E_PHY_COM_REG_PAGE, true,
6905 I40E_PHY_LED_PROV_REG_1,
6908 phy_addr = i40e_get_phy_address(hw, hw->port);
6909 status = i40e_read_phy_register_clause45(hw,
6910 I40E_PHY_COM_REG_PAGE,
6918 * i40e_led_set_reg - write LED register
6919 * @hw: pointer to the HW structure
6920 * @led_addr: LED register address
6921 * @reg_val: register value to write
6923 enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6926 enum i40e_status_code status;
6929 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6930 status = i40e_aq_set_phy_register(hw,
6931 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6932 I40E_PHY_COM_REG_PAGE, true,
6933 I40E_PHY_LED_PROV_REG_1,
6936 phy_addr = i40e_get_phy_address(hw, hw->port);
6937 status = i40e_write_phy_register_clause45(hw,
6938 I40E_PHY_COM_REG_PAGE,
6947 * i40e_led_get_phy - return current on/off mode
6948 * @hw: pointer to the hw struct
6949 * @led_addr: address of led register to use
6950 * @val: original value of register to use
6953 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6956 enum i40e_status_code status = I40E_SUCCESS;
6963 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6964 status = i40e_aq_get_phy_register(hw,
6965 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6966 I40E_PHY_COM_REG_PAGE, true,
6967 I40E_PHY_LED_PROV_REG_1,
6969 if (status == I40E_SUCCESS)
6970 *val = (u16)reg_val_aq;
6973 temp_addr = I40E_PHY_LED_PROV_REG_1;
6974 phy_addr = i40e_get_phy_address(hw, hw->port);
6975 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6977 status = i40e_read_phy_register_clause45(hw,
6978 I40E_PHY_COM_REG_PAGE,
6979 temp_addr, phy_addr,
6984 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6985 *led_addr = temp_addr;
6994 * @hw: pointer to the HW structure
6995 * @on: true or false
6996 * @led_addr: address of led register to use
6997 * @mode: original val plus bit for set or ignore
6999 * Set led's on or off when controlled by the PHY
7002 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
7003 u16 led_addr, u32 mode)
7005 enum i40e_status_code status = I40E_SUCCESS;
7009 status = i40e_led_get_reg(hw, led_addr, &led_reg);
7013 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
7015 status = i40e_led_set_reg(hw, led_addr, led_reg);
7019 status = i40e_led_get_reg(hw, led_addr, &led_reg);
7021 goto restore_config;
7023 led_reg = I40E_PHY_LED_MANUAL_ON;
7026 status = i40e_led_set_reg(hw, led_addr, led_reg);
7028 goto restore_config;
7029 if (mode & I40E_PHY_LED_MODE_ORIG) {
7030 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
7031 status = i40e_led_set_reg(hw, led_addr, led_ctl);
7036 status = i40e_led_set_reg(hw, led_addr, led_ctl);
7039 #endif /* PF_DRIVER */
7041 * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
7042 * @hw: pointer to the hw struct
7043 * @stat: pointer to structure with status of rx and tx lpi
7045 * Read LPI state directly from external PHY register or from MAC
7046 * register, depending on device ID and current link speed.
7048 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
7049 struct i40e_hw_port_stats *stat)
7051 enum i40e_status_code ret = I40E_SUCCESS;
7054 stat->rx_lpi_status = 0;
7055 stat->tx_lpi_status = 0;
7057 if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7058 hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7059 (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7060 hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
7061 ret = i40e_aq_get_phy_register(hw,
7062 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7063 I40E_BCM_PHY_PCS_STATUS1_PAGE,
7065 I40E_BCM_PHY_PCS_STATUS1_REG,
7068 if (ret != I40E_SUCCESS)
7071 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7072 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7077 val = rd32(hw, I40E_PRTPM_EEE_STAT);
7078 stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7079 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7080 stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7081 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7087 * i40e_get_lpi_counters - read LPI counters from EEE statistics
7088 * @hw: pointer to the hw struct
7089 * @tx_counter: pointer to memory for TX LPI counter
7090 * @rx_counter: pointer to memory for RX LPI counter
7091 * @is_clear: returns true if counters are clear after read
7093 * Read Low Power Idle (LPI) mode counters from Energy Efficient
7094 * Ethernet (EEE) statistics.
7096 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7097 u32 *tx_counter, u32 *rx_counter,
7100 /* only X710-T*L requires special handling of counters
7101 * for other devices we just read the MAC registers
7103 if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7104 hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7105 hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7106 enum i40e_status_code retval;
7110 retval = i40e_aq_run_phy_activity(hw,
7111 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7112 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7113 &cmd_status, tx_counter, rx_counter, NULL);
7115 if (!retval && cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7116 retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7122 *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7123 *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7125 return I40E_SUCCESS;
7129 * i40e_get_lpi_duration - read LPI time duration from EEE statistics
7130 * @hw: pointer to the hw struct
7131 * @stat: pointer to structure with status of rx and tx lpi
7132 * @tx_duration: pointer to memory for TX LPI time duration
7133 * @rx_duration: pointer to memory for RX LPI time duration
7135 * Read Low Power Idle (LPI) mode time duration from Energy Efficient
7136 * Ethernet (EEE) statistics.
7138 enum i40e_status_code i40e_get_lpi_duration(struct i40e_hw *hw,
7139 struct i40e_hw_port_stats *stat,
7140 u64 *tx_duration, u64 *rx_duration)
7142 u32 tx_time_dur, rx_time_dur;
7143 enum i40e_status_code retval;
7146 if (hw->device_id != I40E_DEV_ID_10G_BASE_T_BC &&
7147 hw->device_id != I40E_DEV_ID_5G_BASE_T_BC)
7148 return I40E_ERR_NOT_IMPLEMENTED;
7150 retval = i40e_aq_run_phy_activity
7151 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7152 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR,
7153 &cmd_status, &tx_time_dur, &rx_time_dur, NULL);
7157 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7158 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7159 return I40E_ERR_ADMIN_QUEUE_ERROR;
7161 if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB &&
7162 !tx_time_dur && !rx_time_dur &&
7163 stat->tx_lpi_status && stat->rx_lpi_status) {
7164 retval = i40e_aq_run_phy_activity
7165 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7166 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR,
7168 &tx_time_dur, &rx_time_dur, NULL);
7172 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7173 I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7174 return I40E_ERR_ADMIN_QUEUE_ERROR;
7179 *tx_duration = tx_time_dur;
7180 *rx_duration = rx_time_dur;
7186 * i40e_lpi_stat_update - update LPI counters with values relative to offset
7187 * @hw: pointer to the hw struct
7188 * @offset_loaded: flag indicating need of writing current value to offset
7189 * @tx_offset: pointer to offset of TX LPI counter
7190 * @tx_stat: pointer to value of TX LPI counter
7191 * @rx_offset: pointer to offset of RX LPI counter
7192 * @rx_stat: pointer to value of RX LPI counter
7194 * Update Low Power Idle (LPI) mode counters while having regard to passed
7197 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7198 bool offset_loaded, u64 *tx_offset,
7199 u64 *tx_stat, u64 *rx_offset,
7202 enum i40e_status_code retval;
7203 u32 tx_counter, rx_counter;
7206 retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7211 *tx_stat += tx_counter;
7212 *rx_stat += rx_counter;
7214 if (!offset_loaded) {
7215 *tx_offset = tx_counter;
7216 *rx_offset = rx_counter;
7219 *tx_stat = (tx_counter >= *tx_offset) ?
7220 (u32)(tx_counter - *tx_offset) :
7221 (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7222 *rx_stat = (rx_counter >= *rx_offset) ?
7223 (u32)(rx_counter - *rx_offset) :
7224 (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7231 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7232 * @hw: pointer to the hw struct
7233 * @reg_addr: register address
7234 * @reg_val: ptr to register value
7235 * @cmd_details: pointer to command details structure or NULL
7237 * Use the firmware to read the Rx control register,
7238 * especially useful if the Rx unit is under heavy pressure
7240 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7241 u32 reg_addr, u32 *reg_val,
7242 struct i40e_asq_cmd_details *cmd_details)
7244 struct i40e_aq_desc desc;
7245 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7246 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7247 enum i40e_status_code status;
7249 if (reg_val == NULL)
7250 return I40E_ERR_PARAM;
7252 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7254 cmd_resp->address = CPU_TO_LE32(reg_addr);
7256 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7258 if (status == I40E_SUCCESS)
7259 *reg_val = LE32_TO_CPU(cmd_resp->value);
7265 * i40e_read_rx_ctl - read from an Rx control register
7266 * @hw: pointer to the hw struct
7267 * @reg_addr: register address
7269 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7271 enum i40e_status_code status = I40E_SUCCESS;
7276 use_register = (((hw->aq.api_maj_ver == 1) &&
7277 (hw->aq.api_min_ver < 5)) ||
7278 (hw->mac.type == I40E_MAC_X722));
7279 if (!use_register) {
7281 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7282 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7289 /* if the AQ access failed, try the old-fashioned way */
7290 if (status || use_register)
7291 val = rd32(hw, reg_addr);
7297 * i40e_aq_rx_ctl_write_register
7298 * @hw: pointer to the hw struct
7299 * @reg_addr: register address
7300 * @reg_val: register value
7301 * @cmd_details: pointer to command details structure or NULL
7303 * Use the firmware to write to an Rx control register,
7304 * especially useful if the Rx unit is under heavy pressure
7306 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7307 u32 reg_addr, u32 reg_val,
7308 struct i40e_asq_cmd_details *cmd_details)
7310 struct i40e_aq_desc desc;
7311 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7312 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7313 enum i40e_status_code status;
7315 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7317 cmd->address = CPU_TO_LE32(reg_addr);
7318 cmd->value = CPU_TO_LE32(reg_val);
7320 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7326 * i40e_write_rx_ctl - write to an Rx control register
7327 * @hw: pointer to the hw struct
7328 * @reg_addr: register address
7329 * @reg_val: register value
7331 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7333 enum i40e_status_code status = I40E_SUCCESS;
7337 use_register = (((hw->aq.api_maj_ver == 1) &&
7338 (hw->aq.api_min_ver < 5)) ||
7339 (hw->mac.type == I40E_MAC_X722));
7340 if (!use_register) {
7342 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7344 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7351 /* if the AQ access failed, try the old-fashioned way */
7352 if (status || use_register)
7353 wr32(hw, reg_addr, reg_val);
7357 * i40e_mdio_if_number_selection - MDIO I/F number selection
7358 * @hw: pointer to the hw struct
7359 * @set_mdio: use MDIO I/F number specified by mdio_num
7360 * @mdio_num: MDIO I/F number
7361 * @cmd: pointer to PHY Register command structure
7364 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7365 struct i40e_aqc_phy_register_access *cmd)
7367 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7368 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7370 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7372 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7373 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7375 i40e_debug(hw, I40E_DEBUG_PHY,
7376 "MDIO I/F number selection not supported by current FW version.\n");
7381 * i40e_aq_set_phy_register_ext
7382 * @hw: pointer to the hw struct
7383 * @phy_select: select which phy should be accessed
7384 * @dev_addr: PHY device address
7385 * @page_change: enable auto page change
7386 * @set_mdio: use MDIO I/F number specified by mdio_num
7387 * @mdio_num: MDIO I/F number
7388 * @reg_addr: PHY register address
7389 * @reg_val: new register value
7390 * @cmd_details: pointer to command details structure or NULL
7392 * Write the external PHY register.
7393 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7394 * may use simple wrapper i40e_aq_set_phy_register.
7396 enum i40e_status_code
7397 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7398 u8 phy_select, u8 dev_addr, bool page_change,
7399 bool set_mdio, u8 mdio_num,
7400 u32 reg_addr, u32 reg_val,
7401 struct i40e_asq_cmd_details *cmd_details)
7403 struct i40e_aq_desc desc;
7404 struct i40e_aqc_phy_register_access *cmd =
7405 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7406 enum i40e_status_code status;
7408 i40e_fill_default_direct_cmd_desc(&desc,
7409 i40e_aqc_opc_set_phy_register);
7411 cmd->phy_interface = phy_select;
7412 cmd->dev_addres = dev_addr;
7413 cmd->reg_address = CPU_TO_LE32(reg_addr);
7414 cmd->reg_value = CPU_TO_LE32(reg_val);
7417 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7419 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7421 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7427 * i40e_aq_get_phy_register_ext
7428 * @hw: pointer to the hw struct
7429 * @phy_select: select which phy should be accessed
7430 * @dev_addr: PHY device address
7431 * @page_change: enable auto page change
7432 * @set_mdio: use MDIO I/F number specified by mdio_num
7433 * @mdio_num: MDIO I/F number
7434 * @reg_addr: PHY register address
7435 * @reg_val: read register value
7436 * @cmd_details: pointer to command details structure or NULL
7438 * Read the external PHY register.
7439 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7440 * may use simple wrapper i40e_aq_get_phy_register.
7442 enum i40e_status_code
7443 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7444 u8 phy_select, u8 dev_addr, bool page_change,
7445 bool set_mdio, u8 mdio_num,
7446 u32 reg_addr, u32 *reg_val,
7447 struct i40e_asq_cmd_details *cmd_details)
7449 struct i40e_aq_desc desc;
7450 struct i40e_aqc_phy_register_access *cmd =
7451 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7452 enum i40e_status_code status;
7454 i40e_fill_default_direct_cmd_desc(&desc,
7455 i40e_aqc_opc_get_phy_register);
7457 cmd->phy_interface = phy_select;
7458 cmd->dev_addres = dev_addr;
7459 cmd->reg_address = CPU_TO_LE32(reg_addr);
7462 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7464 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7466 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7468 *reg_val = LE32_TO_CPU(cmd->reg_value);
7474 * i40e_aq_run_phy_activity
7475 * @hw: pointer to the hw struct
7476 * @activity_id: ID of DNL activity to run
7477 * @dnl_opcode: opcode passed to DNL script
7478 * @cmd_status: pointer to memory to write return value of DNL script
7479 * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7480 * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7481 * @cmd_details: pointer to command details structure or NULL
7483 * Run DNL admin command.
7485 enum i40e_status_code
7486 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7487 u32 *cmd_status, u32 *data0, u32 *data1,
7488 struct i40e_asq_cmd_details *cmd_details)
7490 struct i40e_aqc_run_phy_activity *cmd;
7491 enum i40e_status_code retval;
7492 struct i40e_aq_desc desc;
7494 cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7496 if (!cmd_status || !data0 || !data1) {
7497 retval = I40E_ERR_PARAM;
7501 i40e_fill_default_direct_cmd_desc(&desc,
7502 i40e_aqc_opc_run_phy_activity);
7504 cmd->activity_id = CPU_TO_LE16(activity_id);
7505 cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7507 retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7511 *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7512 *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7513 *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7521 * i40e_aq_send_msg_to_pf
7522 * @hw: pointer to the hardware structure
7523 * @v_opcode: opcodes for VF-PF communication
7524 * @v_retval: return error code
7525 * @msg: pointer to the msg buffer
7526 * @msglen: msg length
7527 * @cmd_details: pointer to command details
7529 * Send message to PF driver using admin queue. By default, this message
7530 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7531 * completion before returning.
7533 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7534 enum virtchnl_ops v_opcode,
7535 enum i40e_status_code v_retval,
7536 u8 *msg, u16 msglen,
7537 struct i40e_asq_cmd_details *cmd_details)
7539 struct i40e_aq_desc desc;
7540 struct i40e_asq_cmd_details details;
7541 enum i40e_status_code status;
7543 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7544 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7545 desc.cookie_high = CPU_TO_LE32(v_opcode);
7546 desc.cookie_low = CPU_TO_LE32(v_retval);
7548 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7549 | I40E_AQ_FLAG_RD));
7550 if (msglen > I40E_AQ_LARGE_BUF)
7551 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7552 desc.datalen = CPU_TO_LE16(msglen);
7555 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7556 details.async = true;
7557 cmd_details = &details;
7559 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7560 msglen, cmd_details);
7565 * i40e_vf_parse_hw_config
7566 * @hw: pointer to the hardware structure
7567 * @msg: pointer to the virtual channel VF resource structure
7569 * Given a VF resource message from the PF, populate the hw struct
7570 * with appropriate information.
7572 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7573 struct virtchnl_vf_resource *msg)
7575 struct virtchnl_vsi_resource *vsi_res;
7578 vsi_res = &msg->vsi_res[0];
7580 hw->dev_caps.num_vsis = msg->num_vsis;
7581 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7582 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7583 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7584 hw->dev_caps.dcb = msg->vf_cap_flags &
7585 VIRTCHNL_VF_OFFLOAD_L2;
7586 hw->dev_caps.iwarp = (msg->vf_cap_flags &
7587 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7588 for (i = 0; i < msg->num_vsis; i++) {
7589 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7590 i40e_memcpy(hw->mac.perm_addr,
7591 vsi_res->default_mac_addr,
7593 I40E_NONDMA_TO_NONDMA);
7594 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7596 I40E_NONDMA_TO_NONDMA);
7604 * @hw: pointer to the hardware structure
7606 * Send a VF_RESET message to the PF. Does not wait for response from PF
7607 * as none will be forthcoming. Immediately after calling this function,
7608 * the admin queue should be shut down and (optionally) reinitialized.
7610 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7612 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7613 I40E_SUCCESS, NULL, 0, NULL);
7615 #endif /* VF_DRIVER */
7618 * i40e_aq_set_arp_proxy_config
7619 * @hw: pointer to the HW structure
7620 * @proxy_config: pointer to proxy config command table struct
7621 * @cmd_details: pointer to command details
7623 * Set ARP offload parameters from pre-populated
7624 * i40e_aqc_arp_proxy_data struct
7626 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7627 struct i40e_aqc_arp_proxy_data *proxy_config,
7628 struct i40e_asq_cmd_details *cmd_details)
7630 struct i40e_aq_desc desc;
7631 enum i40e_status_code status;
7634 return I40E_ERR_PARAM;
7636 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7638 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7639 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7640 desc.params.external.addr_high =
7641 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7642 desc.params.external.addr_low =
7643 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7644 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7646 status = i40e_asq_send_command(hw, &desc, proxy_config,
7647 sizeof(struct i40e_aqc_arp_proxy_data),
7654 * i40e_aq_opc_set_ns_proxy_table_entry
7655 * @hw: pointer to the HW structure
7656 * @ns_proxy_table_entry: pointer to NS table entry command struct
7657 * @cmd_details: pointer to command details
7659 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7660 * from pre-populated i40e_aqc_ns_proxy_data struct
7662 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7663 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7664 struct i40e_asq_cmd_details *cmd_details)
7666 struct i40e_aq_desc desc;
7667 enum i40e_status_code status;
7669 if (!ns_proxy_table_entry)
7670 return I40E_ERR_PARAM;
7672 i40e_fill_default_direct_cmd_desc(&desc,
7673 i40e_aqc_opc_set_ns_proxy_table_entry);
7675 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7676 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7677 desc.params.external.addr_high =
7678 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7679 desc.params.external.addr_low =
7680 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7681 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7683 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7684 sizeof(struct i40e_aqc_ns_proxy_data),
7691 * i40e_aq_set_clear_wol_filter
7692 * @hw: pointer to the hw struct
7693 * @filter_index: index of filter to modify (0-7)
7694 * @filter: buffer containing filter to be set
7695 * @set_filter: true to set filter, false to clear filter
7696 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7697 * if false, pass through packets may cause wake-up
7698 * @filter_valid: true if filter action is valid
7699 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7700 * @cmd_details: pointer to command details structure or NULL
7702 * Set or clear WoL filter for port attached to the PF
7704 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7706 struct i40e_aqc_set_wol_filter_data *filter,
7707 bool set_filter, bool no_wol_tco,
7708 bool filter_valid, bool no_wol_tco_valid,
7709 struct i40e_asq_cmd_details *cmd_details)
7711 struct i40e_aq_desc desc;
7712 struct i40e_aqc_set_wol_filter *cmd =
7713 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7714 enum i40e_status_code status;
7716 u16 valid_flags = 0;
7719 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7721 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7722 return I40E_ERR_PARAM;
7723 cmd->filter_index = CPU_TO_LE16(filter_index);
7727 return I40E_ERR_PARAM;
7729 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7730 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7734 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7735 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7738 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7739 if (no_wol_tco_valid)
7740 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7741 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7743 buff_len = sizeof(*filter);
7744 desc.datalen = CPU_TO_LE16(buff_len);
7746 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7747 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7749 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7750 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7752 status = i40e_asq_send_command(hw, &desc, filter,
7753 buff_len, cmd_details);
7759 * i40e_aq_get_wake_event_reason
7760 * @hw: pointer to the hw struct
7761 * @wake_reason: return value, index of matching filter
7762 * @cmd_details: pointer to command details structure or NULL
7764 * Get information for the reason of a Wake Up event
7766 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7768 struct i40e_asq_cmd_details *cmd_details)
7770 struct i40e_aq_desc desc;
7771 struct i40e_aqc_get_wake_reason_completion *resp =
7772 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7773 enum i40e_status_code status;
7775 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7777 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7779 if (status == I40E_SUCCESS)
7780 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7786 * i40e_aq_clear_all_wol_filters
7787 * @hw: pointer to the hw struct
7788 * @cmd_details: pointer to command details structure or NULL
7790 * Get information for the reason of a Wake Up event
7792 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7793 struct i40e_asq_cmd_details *cmd_details)
7795 struct i40e_aq_desc desc;
7796 enum i40e_status_code status;
7798 i40e_fill_default_direct_cmd_desc(&desc,
7799 i40e_aqc_opc_clear_all_wol_filters);
7801 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7807 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7808 * @hw: pointer to the hw struct
7809 * @buff: command buffer (size in bytes = buff_size)
7810 * @buff_size: buffer size in bytes
7811 * @track_id: package tracking id
7812 * @error_offset: returns error offset
7813 * @error_info: returns error information
7814 * @cmd_details: pointer to command details structure or NULL
7817 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7818 u16 buff_size, u32 track_id,
7819 u32 *error_offset, u32 *error_info,
7820 struct i40e_asq_cmd_details *cmd_details)
7822 struct i40e_aq_desc desc;
7823 struct i40e_aqc_write_personalization_profile *cmd =
7824 (struct i40e_aqc_write_personalization_profile *)
7826 struct i40e_aqc_write_ddp_resp *resp;
7827 enum i40e_status_code status;
7829 i40e_fill_default_direct_cmd_desc(&desc,
7830 i40e_aqc_opc_write_personalization_profile);
7832 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7833 if (buff_size > I40E_AQ_LARGE_BUF)
7834 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7836 desc.datalen = CPU_TO_LE16(buff_size);
7838 cmd->profile_track_id = CPU_TO_LE32(track_id);
7840 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7842 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7844 *error_offset = LE32_TO_CPU(resp->error_offset);
7846 *error_info = LE32_TO_CPU(resp->error_info);
7853 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7854 * @hw: pointer to the hw struct
7855 * @buff: command buffer (size in bytes = buff_size)
7856 * @buff_size: buffer size in bytes
7857 * @flags: AdminQ command flags
7858 * @cmd_details: pointer to command details structure or NULL
7861 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7862 u16 buff_size, u8 flags,
7863 struct i40e_asq_cmd_details *cmd_details)
7865 struct i40e_aq_desc desc;
7866 struct i40e_aqc_get_applied_profiles *cmd =
7867 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7868 enum i40e_status_code status;
7870 i40e_fill_default_direct_cmd_desc(&desc,
7871 i40e_aqc_opc_get_personalization_profile_list);
7873 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7874 if (buff_size > I40E_AQ_LARGE_BUF)
7875 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7876 desc.datalen = CPU_TO_LE16(buff_size);
7880 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7886 * i40e_find_segment_in_package
7887 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7888 * @pkg_hdr: pointer to the package header to be searched
7890 * This function searches a package file for a particular segment type. On
7891 * success it returns a pointer to the segment header, otherwise it will
7894 struct i40e_generic_seg_header *
7895 i40e_find_segment_in_package(u32 segment_type,
7896 struct i40e_package_header *pkg_hdr)
7898 struct i40e_generic_seg_header *segment;
7901 /* Search all package segments for the requested segment type */
7902 for (i = 0; i < pkg_hdr->segment_count; i++) {
7904 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7905 pkg_hdr->segment_offset[i]);
7907 if (segment->type == segment_type)
7914 /* Get section table in profile */
7915 #define I40E_SECTION_TABLE(profile, sec_tbl) \
7917 struct i40e_profile_segment *p = (profile); \
7920 count = p->device_table_count; \
7921 nvm = (u32 *)&p->device_table[count]; \
7922 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7925 /* Get section header in profile */
7926 #define I40E_SECTION_HEADER(profile, offset) \
7927 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7930 * i40e_find_section_in_profile
7931 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7932 * @profile: pointer to the i40e segment header to be searched
7934 * This function searches i40e segment for a particular section type. On
7935 * success it returns a pointer to the section header, otherwise it will
7938 struct i40e_profile_section_header *
7939 i40e_find_section_in_profile(u32 section_type,
7940 struct i40e_profile_segment *profile)
7942 struct i40e_profile_section_header *sec;
7943 struct i40e_section_table *sec_tbl;
7947 if (profile->header.type != SEGMENT_TYPE_I40E)
7950 I40E_SECTION_TABLE(profile, sec_tbl);
7952 for (i = 0; i < sec_tbl->section_count; i++) {
7953 sec_off = sec_tbl->section_offset[i];
7954 sec = I40E_SECTION_HEADER(profile, sec_off);
7955 if (sec->section.type == section_type)
7963 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7964 * @hw: pointer to the hw struct
7965 * @aq: command buffer containing all data to execute AQ
7968 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7969 struct i40e_profile_aq_section *aq)
7971 enum i40e_status_code status;
7972 struct i40e_aq_desc desc;
7976 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7977 desc.flags |= CPU_TO_LE16(aq->flags);
7978 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7979 I40E_NONDMA_TO_NONDMA);
7981 msglen = aq->datalen;
7983 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7985 if (msglen > I40E_AQ_LARGE_BUF)
7986 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7987 desc.datalen = CPU_TO_LE16(msglen);
7991 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7993 if (status != I40E_SUCCESS) {
7994 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7995 "unable to exec DDP AQ opcode %u, error %d\n",
7996 aq->opcode, status);
8000 /* copy returned desc to aq_buf */
8001 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
8002 I40E_NONDMA_TO_NONDMA);
8004 return I40E_SUCCESS;
8008 * i40e_validate_profile
8009 * @hw: pointer to the hardware structure
8010 * @profile: pointer to the profile segment of the package to be validated
8011 * @track_id: package tracking id
8012 * @rollback: flag if the profile is for rollback.
8014 * Validates supported devices and profile's sections.
8016 STATIC enum i40e_status_code
8017 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8018 u32 track_id, bool rollback)
8020 struct i40e_profile_section_header *sec = NULL;
8021 enum i40e_status_code status = I40E_SUCCESS;
8022 struct i40e_section_table *sec_tbl;
8028 if (track_id == I40E_DDP_TRACKID_INVALID) {
8029 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
8030 return I40E_NOT_SUPPORTED;
8033 dev_cnt = profile->device_table_count;
8034 for (i = 0; i < dev_cnt; i++) {
8035 vendor_dev_id = profile->device_table[i].vendor_dev_id;
8036 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
8037 hw->device_id == (vendor_dev_id & 0xFFFF))
8040 if (dev_cnt && (i == dev_cnt)) {
8041 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8042 "Device doesn't support DDP\n");
8043 return I40E_ERR_DEVICE_NOT_SUPPORTED;
8046 I40E_SECTION_TABLE(profile, sec_tbl);
8048 /* Validate sections types */
8049 for (i = 0; i < sec_tbl->section_count; i++) {
8050 sec_off = sec_tbl->section_offset[i];
8051 sec = I40E_SECTION_HEADER(profile, sec_off);
8053 if (sec->section.type == SECTION_TYPE_MMIO ||
8054 sec->section.type == SECTION_TYPE_AQ ||
8055 sec->section.type == SECTION_TYPE_RB_AQ) {
8056 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8057 "Not a roll-back package\n");
8058 return I40E_NOT_SUPPORTED;
8061 if (sec->section.type == SECTION_TYPE_RB_AQ ||
8062 sec->section.type == SECTION_TYPE_RB_MMIO) {
8063 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8064 "Not an original package\n");
8065 return I40E_NOT_SUPPORTED;
8074 * i40e_write_profile
8075 * @hw: pointer to the hardware structure
8076 * @profile: pointer to the profile segment of the package to be downloaded
8077 * @track_id: package tracking id
8079 * Handles the download of a complete package.
8081 enum i40e_status_code
8082 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8085 enum i40e_status_code status = I40E_SUCCESS;
8086 struct i40e_section_table *sec_tbl;
8087 struct i40e_profile_section_header *sec = NULL;
8088 struct i40e_profile_aq_section *ddp_aq;
8089 u32 section_size = 0;
8090 u32 offset = 0, info = 0;
8094 status = i40e_validate_profile(hw, profile, track_id, false);
8098 I40E_SECTION_TABLE(profile, sec_tbl);
8100 for (i = 0; i < sec_tbl->section_count; i++) {
8101 sec_off = sec_tbl->section_offset[i];
8102 sec = I40E_SECTION_HEADER(profile, sec_off);
8103 /* Process generic admin command */
8104 if (sec->section.type == SECTION_TYPE_AQ) {
8105 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
8106 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
8108 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8109 "Failed to execute aq: section %d, opcode %u\n",
8113 sec->section.type = SECTION_TYPE_RB_AQ;
8116 /* Skip any non-mmio sections */
8117 if (sec->section.type != SECTION_TYPE_MMIO)
8120 section_size = sec->section.size +
8121 sizeof(struct i40e_profile_section_header);
8123 /* Write MMIO section */
8124 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8125 track_id, &offset, &info, NULL);
8127 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8128 "Failed to write profile: section %d, offset %d, info %d\n",
8137 * i40e_rollback_profile
8138 * @hw: pointer to the hardware structure
8139 * @profile: pointer to the profile segment of the package to be removed
8140 * @track_id: package tracking id
8142 * Rolls back previously loaded package.
8144 enum i40e_status_code
8145 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8148 struct i40e_profile_section_header *sec = NULL;
8149 enum i40e_status_code status = I40E_SUCCESS;
8150 struct i40e_section_table *sec_tbl;
8151 u32 offset = 0, info = 0;
8152 u32 section_size = 0;
8156 status = i40e_validate_profile(hw, profile, track_id, true);
8160 I40E_SECTION_TABLE(profile, sec_tbl);
8162 /* For rollback write sections in reverse */
8163 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8164 sec_off = sec_tbl->section_offset[i];
8165 sec = I40E_SECTION_HEADER(profile, sec_off);
8167 /* Skip any non-rollback sections */
8168 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8171 section_size = sec->section.size +
8172 sizeof(struct i40e_profile_section_header);
8174 /* Write roll-back MMIO section */
8175 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8176 track_id, &offset, &info, NULL);
8178 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8179 "Failed to write profile: section %d, offset %d, info %d\n",
8188 * i40e_add_pinfo_to_list
8189 * @hw: pointer to the hardware structure
8190 * @profile: pointer to the profile segment of the package
8191 * @profile_info_sec: buffer for information section
8192 * @track_id: package tracking id
8194 * Register a profile to the list of loaded profiles.
8196 enum i40e_status_code
8197 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8198 struct i40e_profile_segment *profile,
8199 u8 *profile_info_sec, u32 track_id)
8201 enum i40e_status_code status = I40E_SUCCESS;
8202 struct i40e_profile_section_header *sec = NULL;
8203 struct i40e_profile_info *pinfo;
8204 u32 offset = 0, info = 0;
8206 sec = (struct i40e_profile_section_header *)profile_info_sec;
8208 sec->data_end = sizeof(struct i40e_profile_section_header) +
8209 sizeof(struct i40e_profile_info);
8210 sec->section.type = SECTION_TYPE_INFO;
8211 sec->section.offset = sizeof(struct i40e_profile_section_header);
8212 sec->section.size = sizeof(struct i40e_profile_info);
8213 pinfo = (struct i40e_profile_info *)(profile_info_sec +
8214 sec->section.offset);
8215 pinfo->track_id = track_id;
8216 pinfo->version = profile->version;
8217 pinfo->op = I40E_DDP_ADD_TRACKID;
8218 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8219 I40E_NONDMA_TO_NONDMA);
8221 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8222 track_id, &offset, &info, NULL);