drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  18 {
  19         enum i40e_status_code status = I40E_SUCCESS;
  20
  21         DEBUGFUNC("i40e_set_mac_type\n");
  22
  23         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  24                 switch (hw->device_id) {
  25                 case I40E_DEV_ID_SFP_XL710:
  26                 case I40E_DEV_ID_QEMU:
  27                 case I40E_DEV_ID_KX_B:
  28                 case I40E_DEV_ID_KX_C:
  29                 case I40E_DEV_ID_QSFP_A:
  30                 case I40E_DEV_ID_QSFP_B:
  31                 case I40E_DEV_ID_QSFP_C:
  32                 case I40E_DEV_ID_10G_BASE_T:
  33                 case I40E_DEV_ID_10G_BASE_T4:
  34                 case I40E_DEV_ID_10G_BASE_T_BC:
  35                 case I40E_DEV_ID_10G_B:
  36                 case I40E_DEV_ID_10G_SFP:
  37                 case I40E_DEV_ID_20G_KR2:
  38                 case I40E_DEV_ID_20G_KR2_A:
  39                 case I40E_DEV_ID_25G_B:
  40                 case I40E_DEV_ID_25G_SFP28:
  41                 case I40E_DEV_ID_X710_N3000:
  42                 case I40E_DEV_ID_XXV710_N3000:
  43                         hw->mac.type = I40E_MAC_XL710;
  44                         break;
  45 #ifdef X722_A0_SUPPORT
  46                 case I40E_DEV_ID_X722_A0:
  47 #endif
  48                 case I40E_DEV_ID_KX_X722:
  49                 case I40E_DEV_ID_QSFP_X722:
  50                 case I40E_DEV_ID_SFP_X722:
  51                 case I40E_DEV_ID_1G_BASE_T_X722:
  52                 case I40E_DEV_ID_10G_BASE_T_X722:
  53                 case I40E_DEV_ID_SFP_I_X722:
  54                         hw->mac.type = I40E_MAC_X722;
  55                         break;
  56 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  57                 case I40E_DEV_ID_X722_VF:
  58 #ifdef X722_A0_SUPPORT
  59                 case I40E_DEV_ID_X722_A0_VF:
  60 #endif
  61                         hw->mac.type = I40E_MAC_X722_VF;
  62                         break;
  63 #endif /* INTEGRATED_VF || VF_DRIVER */
  64 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  65                 case I40E_DEV_ID_VF:
  66                 case I40E_DEV_ID_VF_HV:
  67                 case I40E_DEV_ID_ADAPTIVE_VF:
  68                         hw->mac.type = I40E_MAC_VF;
  69                         break;
  70 #endif
  71                 default:
  72                         hw->mac.type = I40E_MAC_GENERIC;
  73                         break;
  74                 }
  75         } else {
  76                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  77         }
  78
  79         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  80                   hw->mac.type, status);
  81         return status;
  82 }
  83
  84 /**
  85  * i40e_aq_str - convert AQ err code to a string
  86  * @hw: pointer to the HW structure
  87  * @aq_err: the AQ error code to convert
  88  **/
  89 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  90 {
  91         switch (aq_err) {
  92         case I40E_AQ_RC_OK:
  93                 return "OK";
  94         case I40E_AQ_RC_EPERM:
  95                 return "I40E_AQ_RC_EPERM";
  96         case I40E_AQ_RC_ENOENT:
  97                 return "I40E_AQ_RC_ENOENT";
  98         case I40E_AQ_RC_ESRCH:
  99                 return "I40E_AQ_RC_ESRCH";
 100         case I40E_AQ_RC_EINTR:
 101                 return "I40E_AQ_RC_EINTR";
 102         case I40E_AQ_RC_EIO:
 103                 return "I40E_AQ_RC_EIO";
 104         case I40E_AQ_RC_ENXIO:
 105                 return "I40E_AQ_RC_ENXIO";
 106         case I40E_AQ_RC_E2BIG:
 107                 return "I40E_AQ_RC_E2BIG";
 108         case I40E_AQ_RC_EAGAIN:
 109                 return "I40E_AQ_RC_EAGAIN";
 110         case I40E_AQ_RC_ENOMEM:
 111                 return "I40E_AQ_RC_ENOMEM";
 112         case I40E_AQ_RC_EACCES:
 113                 return "I40E_AQ_RC_EACCES";
 114         case I40E_AQ_RC_EFAULT:
 115                 return "I40E_AQ_RC_EFAULT";
 116         case I40E_AQ_RC_EBUSY:
 117                 return "I40E_AQ_RC_EBUSY";
 118         case I40E_AQ_RC_EEXIST:
 119                 return "I40E_AQ_RC_EEXIST";
 120         case I40E_AQ_RC_EINVAL:
 121                 return "I40E_AQ_RC_EINVAL";
 122         case I40E_AQ_RC_ENOTTY:
 123                 return "I40E_AQ_RC_ENOTTY";
 124         case I40E_AQ_RC_ENOSPC:
 125                 return "I40E_AQ_RC_ENOSPC";
 126         case I40E_AQ_RC_ENOSYS:
 127                 return "I40E_AQ_RC_ENOSYS";
 128         case I40E_AQ_RC_ERANGE:
 129                 return "I40E_AQ_RC_ERANGE";
 130         case I40E_AQ_RC_EFLUSHED:
 131                 return "I40E_AQ_RC_EFLUSHED";
 132         case I40E_AQ_RC_BAD_ADDR:
 133                 return "I40E_AQ_RC_BAD_ADDR";
 134         case I40E_AQ_RC_EMODE:
 135                 return "I40E_AQ_RC_EMODE";
 136         case I40E_AQ_RC_EFBIG:
 137                 return "I40E_AQ_RC_EFBIG";
 138         }
 139
 140         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 141         return hw->err_str;
 142 }
 143
 144 /**
 145  * i40e_stat_str - convert status err code to a string
 146  * @hw: pointer to the HW structure
 147  * @stat_err: the status error code to convert
 148  **/
 149 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 150 {
 151         switch (stat_err) {
 152         case I40E_SUCCESS:
 153                 return "OK";
 154         case I40E_ERR_NVM:
 155                 return "I40E_ERR_NVM";
 156         case I40E_ERR_NVM_CHECKSUM:
 157                 return "I40E_ERR_NVM_CHECKSUM";
 158         case I40E_ERR_PHY:
 159                 return "I40E_ERR_PHY";
 160         case I40E_ERR_CONFIG:
 161                 return "I40E_ERR_CONFIG";
 162         case I40E_ERR_PARAM:
 163                 return "I40E_ERR_PARAM";
 164         case I40E_ERR_MAC_TYPE:
 165                 return "I40E_ERR_MAC_TYPE";
 166         case I40E_ERR_UNKNOWN_PHY:
 167                 return "I40E_ERR_UNKNOWN_PHY";
 168         case I40E_ERR_LINK_SETUP:
 169                 return "I40E_ERR_LINK_SETUP";
 170         case I40E_ERR_ADAPTER_STOPPED:
 171                 return "I40E_ERR_ADAPTER_STOPPED";
 172         case I40E_ERR_INVALID_MAC_ADDR:
 173                 return "I40E_ERR_INVALID_MAC_ADDR";
 174         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 175                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 176         case I40E_ERR_MASTER_REQUESTS_PENDING:
 177                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 178         case I40E_ERR_INVALID_LINK_SETTINGS:
 179                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 180         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 181                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 182         case I40E_ERR_RESET_FAILED:
 183                 return "I40E_ERR_RESET_FAILED";
 184         case I40E_ERR_SWFW_SYNC:
 185                 return "I40E_ERR_SWFW_SYNC";
 186         case I40E_ERR_NO_AVAILABLE_VSI:
 187                 return "I40E_ERR_NO_AVAILABLE_VSI";
 188         case I40E_ERR_NO_MEMORY:
 189                 return "I40E_ERR_NO_MEMORY";
 190         case I40E_ERR_BAD_PTR:
 191                 return "I40E_ERR_BAD_PTR";
 192         case I40E_ERR_RING_FULL:
 193                 return "I40E_ERR_RING_FULL";
 194         case I40E_ERR_INVALID_PD_ID:
 195                 return "I40E_ERR_INVALID_PD_ID";
 196         case I40E_ERR_INVALID_QP_ID:
 197                 return "I40E_ERR_INVALID_QP_ID";
 198         case I40E_ERR_INVALID_CQ_ID:
 199                 return "I40E_ERR_INVALID_CQ_ID";
 200         case I40E_ERR_INVALID_CEQ_ID:
 201                 return "I40E_ERR_INVALID_CEQ_ID";
 202         case I40E_ERR_INVALID_AEQ_ID:
 203                 return "I40E_ERR_INVALID_AEQ_ID";
 204         case I40E_ERR_INVALID_SIZE:
 205                 return "I40E_ERR_INVALID_SIZE";
 206         case I40E_ERR_INVALID_ARP_INDEX:
 207                 return "I40E_ERR_INVALID_ARP_INDEX";
 208         case I40E_ERR_INVALID_FPM_FUNC_ID:
 209                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 210         case I40E_ERR_QP_INVALID_MSG_SIZE:
 211                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 212         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 213                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 214         case I40E_ERR_INVALID_FRAG_COUNT:
 215                 return "I40E_ERR_INVALID_FRAG_COUNT";
 216         case I40E_ERR_QUEUE_EMPTY:
 217                 return "I40E_ERR_QUEUE_EMPTY";
 218         case I40E_ERR_INVALID_ALIGNMENT:
 219                 return "I40E_ERR_INVALID_ALIGNMENT";
 220         case I40E_ERR_FLUSHED_QUEUE:
 221                 return "I40E_ERR_FLUSHED_QUEUE";
 222         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 223                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 224         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 225                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 226         case I40E_ERR_TIMEOUT:
 227                 return "I40E_ERR_TIMEOUT";
 228         case I40E_ERR_OPCODE_MISMATCH:
 229                 return "I40E_ERR_OPCODE_MISMATCH";
 230         case I40E_ERR_CQP_COMPL_ERROR:
 231                 return "I40E_ERR_CQP_COMPL_ERROR";
 232         case I40E_ERR_INVALID_VF_ID:
 233                 return "I40E_ERR_INVALID_VF_ID";
 234         case I40E_ERR_INVALID_HMCFN_ID:
 235                 return "I40E_ERR_INVALID_HMCFN_ID";
 236         case I40E_ERR_BACKING_PAGE_ERROR:
 237                 return "I40E_ERR_BACKING_PAGE_ERROR";
 238         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 239                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 240         case I40E_ERR_INVALID_PBLE_INDEX:
 241                 return "I40E_ERR_INVALID_PBLE_INDEX";
 242         case I40E_ERR_INVALID_SD_INDEX:
 243                 return "I40E_ERR_INVALID_SD_INDEX";
 244         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 245                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 246         case I40E_ERR_INVALID_SD_TYPE:
 247                 return "I40E_ERR_INVALID_SD_TYPE";
 248         case I40E_ERR_MEMCPY_FAILED:
 249                 return "I40E_ERR_MEMCPY_FAILED";
 250         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 251                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 252         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 253                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 254         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 255                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 256         case I40E_ERR_SRQ_ENABLED:
 257                 return "I40E_ERR_SRQ_ENABLED";
 258         case I40E_ERR_ADMIN_QUEUE_ERROR:
 259                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 260         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 261                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 262         case I40E_ERR_BUF_TOO_SHORT:
 263                 return "I40E_ERR_BUF_TOO_SHORT";
 264         case I40E_ERR_ADMIN_QUEUE_FULL:
 265                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 266         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 267                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 268         case I40E_ERR_BAD_IWARP_CQE:
 269                 return "I40E_ERR_BAD_IWARP_CQE";
 270         case I40E_ERR_NVM_BLANK_MODE:
 271                 return "I40E_ERR_NVM_BLANK_MODE";
 272         case I40E_ERR_NOT_IMPLEMENTED:
 273                 return "I40E_ERR_NOT_IMPLEMENTED";
 274         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 275                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 276         case I40E_ERR_DIAG_TEST_FAILED:
 277                 return "I40E_ERR_DIAG_TEST_FAILED";
 278         case I40E_ERR_NOT_READY:
 279                 return "I40E_ERR_NOT_READY";
 280         case I40E_NOT_SUPPORTED:
 281                 return "I40E_NOT_SUPPORTED";
 282         case I40E_ERR_FIRMWARE_API_VERSION:
 283                 return "I40E_ERR_FIRMWARE_API_VERSION";
 284         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 285                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 286         }
 287
 288         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 289         return hw->err_str;
 290 }
 291
 292 /**
 293  * i40e_debug_aq
 294  * @hw: debug mask related to admin queue
 295  * @mask: debug mask
 296  * @desc: pointer to admin queue descriptor
 297  * @buffer: pointer to command buffer
 298  * @buf_len: max length of buffer
 299  *
 300  * Dumps debug log about adminq command with descriptor contents.
 301  **/
 302 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 303                    void *buffer, u16 buf_len)
 304 {
 305         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 306         u32 effective_mask = hw->debug_mask & mask;
 307         u8 *buf = (u8 *)buffer;
 308         u16 len;
 309         u16 i;
 310
 311         if (!effective_mask || !desc)
 312                 return;
 313
 314         len = LE16_TO_CPU(aq_desc->datalen);
 315
 316         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 317                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 318                    LE16_TO_CPU(aq_desc->opcode),
 319                    LE16_TO_CPU(aq_desc->flags),
 320                    LE16_TO_CPU(aq_desc->datalen),
 321                    LE16_TO_CPU(aq_desc->retval));
 322         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 323                    "\tcookie (h,l) 0x%08X 0x%08X\n",
 324                    LE32_TO_CPU(aq_desc->cookie_high),
 325                    LE32_TO_CPU(aq_desc->cookie_low));
 326         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 327                    "\tparam (0,1)  0x%08X 0x%08X\n",
 328                    LE32_TO_CPU(aq_desc->params.internal.param0),
 329                    LE32_TO_CPU(aq_desc->params.internal.param1));
 330         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 331                    "\taddr (h,l)   0x%08X 0x%08X\n",
 332                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 333                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 334
 335         if (buffer && (buf_len != 0) && (len != 0) &&
 336             (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
 337                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 338                 if (buf_len < len)
 339                         len = buf_len;
 340                 /* write the full 16-byte chunks */
 341                 for (i = 0; i < (len - 16); i += 16)
 342                         i40e_debug(hw, mask,
 343                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 344                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 345                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 346                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 347                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 348                 /* the most we could have left is 16 bytes, pad with zeros */
 349                 if (i < len) {
 350                         char d_buf[16];
 351                         int j, i_sav;
 352
 353                         i_sav = i;
 354                         memset(d_buf, 0, sizeof(d_buf));
 355                         for (j = 0; i < len; j++, i++)
 356                                 d_buf[j] = buf[i];
 357                         i40e_debug(hw, mask,
 358                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 359                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 360                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 361                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 362                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 363                 }
 364         }
 365 }
 366
 367 /**
 368  * i40e_check_asq_alive
 369  * @hw: pointer to the hw struct
 370  *
 371  * Returns true if Queue is enabled else false.
 372  **/
 373 bool i40e_check_asq_alive(struct i40e_hw *hw)
 374 {
 375         if (hw->aq.asq.len)
 376 #ifdef PF_DRIVER
 377 #ifdef INTEGRATED_VF
 378                 if (!i40e_is_vf(hw))
 379                         return !!(rd32(hw, hw->aq.asq.len) &
 380                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 381 #else
 382                 return !!(rd32(hw, hw->aq.asq.len) &
 383                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 384 #endif /* INTEGRATED_VF */
 385 #endif /* PF_DRIVER */
 386 #ifdef VF_DRIVER
 387 #ifdef INTEGRATED_VF
 388                 if (i40e_is_vf(hw))
 389                         return !!(rd32(hw, hw->aq.asq.len) &
 390                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 391 #else
 392                 return !!(rd32(hw, hw->aq.asq.len) &
 393                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 394 #endif /* INTEGRATED_VF */
 395 #endif /* VF_DRIVER */
 396         return false;
 397 }
 398
 399 /**
 400  * i40e_aq_queue_shutdown
 401  * @hw: pointer to the hw struct
 402  * @unloading: is the driver unloading itself
 403  *
 404  * Tell the Firmware that we're shutting down the AdminQ and whether
 405  * or not the driver is unloading as well.
 406  **/
 407 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 408                                              bool unloading)
 409 {
 410         struct i40e_aq_desc desc;
 411         struct i40e_aqc_queue_shutdown *cmd =
 412                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 413         enum i40e_status_code status;
 414
 415         i40e_fill_default_direct_cmd_desc(&desc,
 416                                           i40e_aqc_opc_queue_shutdown);
 417
 418         if (unloading)
 419                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 420         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 421
 422         return status;
 423 }
 424
 425 /**
 426  * i40e_aq_get_set_rss_lut
 427  * @hw: pointer to the hardware structure
 428  * @vsi_id: vsi fw index
 429  * @pf_lut: for PF table set true, for VSI table set false
 430  * @lut: pointer to the lut buffer provided by the caller
 431  * @lut_size: size of the lut buffer
 432  * @set: set true to set the table, false to get the table
 433  *
 434  * Internal function to get or set RSS look up table
 435  **/
 436 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 437                                                      u16 vsi_id, bool pf_lut,
 438                                                      u8 *lut, u16 lut_size,
 439                                                      bool set)
 440 {
 441         enum i40e_status_code status;
 442         struct i40e_aq_desc desc;
 443         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 444                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 445
 446         if (set)
 447                 i40e_fill_default_direct_cmd_desc(&desc,
 448                                                   i40e_aqc_opc_set_rss_lut);
 449         else
 450                 i40e_fill_default_direct_cmd_desc(&desc,
 451                                                   i40e_aqc_opc_get_rss_lut);
 452
 453         /* Indirect command */
 454         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 455         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 456
 457         cmd_resp->vsi_id =
 458                         CPU_TO_LE16((u16)((vsi_id <<
 459                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 460                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 461         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 462
 463         if (pf_lut)
 464                 cmd_resp->flags |= CPU_TO_LE16((u16)
 465                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 466                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 467                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 468         else
 469                 cmd_resp->flags |= CPU_TO_LE16((u16)
 470                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 471                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 472                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 473
 474         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 475
 476         return status;
 477 }
 478
 479 /**
 480  * i40e_aq_get_rss_lut
 481  * @hw: pointer to the hardware structure
 482  * @vsi_id: vsi fw index
 483  * @pf_lut: for PF table set true, for VSI table set false
 484  * @lut: pointer to the lut buffer provided by the caller
 485  * @lut_size: size of the lut buffer
 486  *
 487  * get the RSS lookup table, PF or VSI type
 488  **/
 489 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 490                                           bool pf_lut, u8 *lut, u16 lut_size)
 491 {
 492         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 493                                        false);
 494 }
 495
 496 /**
 497  * i40e_aq_set_rss_lut
 498  * @hw: pointer to the hardware structure
 499  * @vsi_id: vsi fw index
 500  * @pf_lut: for PF table set true, for VSI table set false
 501  * @lut: pointer to the lut buffer provided by the caller
 502  * @lut_size: size of the lut buffer
 503  *
 504  * set the RSS lookup table, PF or VSI type
 505  **/
 506 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 507                                           bool pf_lut, u8 *lut, u16 lut_size)
 508 {
 509         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 510 }
 511
 512 /**
 513  * i40e_aq_get_set_rss_key
 514  * @hw: pointer to the hw struct
 515  * @vsi_id: vsi fw index
 516  * @key: pointer to key info struct
 517  * @set: set true to set the key, false to get the key
 518  *
 519  * get the RSS key per VSI
 520  **/
 521 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 522                                       u16 vsi_id,
 523                                       struct i40e_aqc_get_set_rss_key_data *key,
 524                                       bool set)
 525 {
 526         enum i40e_status_code status;
 527         struct i40e_aq_desc desc;
 528         struct i40e_aqc_get_set_rss_key *cmd_resp =
 529                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 530         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 531
 532         if (set)
 533                 i40e_fill_default_direct_cmd_desc(&desc,
 534                                                   i40e_aqc_opc_set_rss_key);
 535         else
 536                 i40e_fill_default_direct_cmd_desc(&desc,
 537                                                   i40e_aqc_opc_get_rss_key);
 538
 539         /* Indirect command */
 540         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 541         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 542
 543         cmd_resp->vsi_id =
 544                         CPU_TO_LE16((u16)((vsi_id <<
 545                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 546                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 547         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 548
 549         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 550
 551         return status;
 552 }
 553
 554 /**
 555  * i40e_aq_get_rss_key
 556  * @hw: pointer to the hw struct
 557  * @vsi_id: vsi fw index
 558  * @key: pointer to key info struct
 559  *
 560  **/
 561 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 562                                       u16 vsi_id,
 563                                       struct i40e_aqc_get_set_rss_key_data *key)
 564 {
 565         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 566 }
 567
 568 /**
 569  * i40e_aq_set_rss_key
 570  * @hw: pointer to the hw struct
 571  * @vsi_id: vsi fw index
 572  * @key: pointer to key info struct
 573  *
 574  * set the RSS key per VSI
 575  **/
 576 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 577                                       u16 vsi_id,
 578                                       struct i40e_aqc_get_set_rss_key_data *key)
 579 {
 580         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 581 }
 582
 583 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 584  * hardware to a bit-field that can be used by SW to more easily determine the
 585  * packet type.
 586  *
 587  * Macros are used to shorten the table lines and make this table human
 588  * readable.
 589  *
 590  * We store the PTYPE in the top byte of the bit field - this is just so that
 591  * we can check that the table doesn't have a row missing, as the index into
 592  * the table should be the PTYPE.
 593  *
 594  * Typical work flow:
 595  *
 596  * IF NOT i40e_ptype_lookup[ptype].known
 597  * THEN
 598  *      Packet is unknown
 599  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 600  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 601  * ELSE
 602  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 603  * ENDIF
 604  */
 605
 606 /* macro to make the table lines short */
 607 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 608         {       PTYPE, \
 609                 1, \
 610                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 611                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 612                 I40E_RX_PTYPE_##OUTER_FRAG, \
 613                 I40E_RX_PTYPE_TUNNEL_##T, \
 614                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 615                 I40E_RX_PTYPE_##TEF, \
 616                 I40E_RX_PTYPE_INNER_PROT_##I, \
 617                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 618
 619 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 620                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 621
 622 /* shorter macros makes the table fit but are terse */
 623 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 624 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 625 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 626
 627 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 628 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 629         /* L2 Packet types */
 630         I40E_PTT_UNUSED_ENTRY(0),
 631         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 632         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 633         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 634         I40E_PTT_UNUSED_ENTRY(4),
 635         I40E_PTT_UNUSED_ENTRY(5),
 636         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 637         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 638         I40E_PTT_UNUSED_ENTRY(8),
 639         I40E_PTT_UNUSED_ENTRY(9),
 640         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 641         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 642         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 651         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 652
 653         /* Non Tunneled IPv4 */
 654         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 655         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 656         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 657         I40E_PTT_UNUSED_ENTRY(25),
 658         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 659         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 660         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 661
 662         /* IPv4 --> IPv4 */
 663         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 664         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 665         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 666         I40E_PTT_UNUSED_ENTRY(32),
 667         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 668         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 669         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 670
 671         /* IPv4 --> IPv6 */
 672         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 673         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 674         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 675         I40E_PTT_UNUSED_ENTRY(39),
 676         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 677         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 678         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 679
 680         /* IPv4 --> GRE/NAT */
 681         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 682
 683         /* IPv4 --> GRE/NAT --> IPv4 */
 684         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 685         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 686         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 687         I40E_PTT_UNUSED_ENTRY(47),
 688         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 689         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 690         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 691
 692         /* IPv4 --> GRE/NAT --> IPv6 */
 693         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 694         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 695         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 696         I40E_PTT_UNUSED_ENTRY(54),
 697         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 698         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 699         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 700
 701         /* IPv4 --> GRE/NAT --> MAC */
 702         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 703
 704         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 705         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 706         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 707         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 708         I40E_PTT_UNUSED_ENTRY(62),
 709         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 710         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 711         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 712
 713         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 714         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 715         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 716         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 717         I40E_PTT_UNUSED_ENTRY(69),
 718         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 719         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 720         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 721
 722         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 723         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 724
 725         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 726         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 727         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 728         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 729         I40E_PTT_UNUSED_ENTRY(77),
 730         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 731         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 732         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 733
 734         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 735         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 736         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 737         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 738         I40E_PTT_UNUSED_ENTRY(84),
 739         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 740         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 741         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 742
 743         /* Non Tunneled IPv6 */
 744         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 745         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 746         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 747         I40E_PTT_UNUSED_ENTRY(91),
 748         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 749         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 750         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 751
 752         /* IPv6 --> IPv4 */
 753         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 754         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 755         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 756         I40E_PTT_UNUSED_ENTRY(98),
 757         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 758         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 759         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 760
 761         /* IPv6 --> IPv6 */
 762         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 763         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 764         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 765         I40E_PTT_UNUSED_ENTRY(105),
 766         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 767         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 768         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 769
 770         /* IPv6 --> GRE/NAT */
 771         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 772
 773         /* IPv6 --> GRE/NAT -> IPv4 */
 774         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 775         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 776         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 777         I40E_PTT_UNUSED_ENTRY(113),
 778         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 779         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 780         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 781
 782         /* IPv6 --> GRE/NAT -> IPv6 */
 783         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 784         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 785         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 786         I40E_PTT_UNUSED_ENTRY(120),
 787         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 788         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 789         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 790
 791         /* IPv6 --> GRE/NAT -> MAC */
 792         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 793
 794         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 795         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 796         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 797         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 798         I40E_PTT_UNUSED_ENTRY(128),
 799         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 800         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 801         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 802
 803         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 804         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 805         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 806         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 807         I40E_PTT_UNUSED_ENTRY(135),
 808         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 809         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 810         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 811
 812         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 813         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 814
 815         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 816         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 817         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 818         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 819         I40E_PTT_UNUSED_ENTRY(143),
 820         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 821         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 822         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 823
 824         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 825         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 826         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 827         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 828         I40E_PTT_UNUSED_ENTRY(150),
 829         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 830         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 831         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 832
 833         /* unused entries */
 834         I40E_PTT_UNUSED_ENTRY(154),
 835         I40E_PTT_UNUSED_ENTRY(155),
 836         I40E_PTT_UNUSED_ENTRY(156),
 837         I40E_PTT_UNUSED_ENTRY(157),
 838         I40E_PTT_UNUSED_ENTRY(158),
 839         I40E_PTT_UNUSED_ENTRY(159),
 840
 841         I40E_PTT_UNUSED_ENTRY(160),
 842         I40E_PTT_UNUSED_ENTRY(161),
 843         I40E_PTT_UNUSED_ENTRY(162),
 844         I40E_PTT_UNUSED_ENTRY(163),
 845         I40E_PTT_UNUSED_ENTRY(164),
 846         I40E_PTT_UNUSED_ENTRY(165),
 847         I40E_PTT_UNUSED_ENTRY(166),
 848         I40E_PTT_UNUSED_ENTRY(167),
 849         I40E_PTT_UNUSED_ENTRY(168),
 850         I40E_PTT_UNUSED_ENTRY(169),
 851
 852         I40E_PTT_UNUSED_ENTRY(170),
 853         I40E_PTT_UNUSED_ENTRY(171),
 854         I40E_PTT_UNUSED_ENTRY(172),
 855         I40E_PTT_UNUSED_ENTRY(173),
 856         I40E_PTT_UNUSED_ENTRY(174),
 857         I40E_PTT_UNUSED_ENTRY(175),
 858         I40E_PTT_UNUSED_ENTRY(176),
 859         I40E_PTT_UNUSED_ENTRY(177),
 860         I40E_PTT_UNUSED_ENTRY(178),
 861         I40E_PTT_UNUSED_ENTRY(179),
 862
 863         I40E_PTT_UNUSED_ENTRY(180),
 864         I40E_PTT_UNUSED_ENTRY(181),
 865         I40E_PTT_UNUSED_ENTRY(182),
 866         I40E_PTT_UNUSED_ENTRY(183),
 867         I40E_PTT_UNUSED_ENTRY(184),
 868         I40E_PTT_UNUSED_ENTRY(185),
 869         I40E_PTT_UNUSED_ENTRY(186),
 870         I40E_PTT_UNUSED_ENTRY(187),
 871         I40E_PTT_UNUSED_ENTRY(188),
 872         I40E_PTT_UNUSED_ENTRY(189),
 873
 874         I40E_PTT_UNUSED_ENTRY(190),
 875         I40E_PTT_UNUSED_ENTRY(191),
 876         I40E_PTT_UNUSED_ENTRY(192),
 877         I40E_PTT_UNUSED_ENTRY(193),
 878         I40E_PTT_UNUSED_ENTRY(194),
 879         I40E_PTT_UNUSED_ENTRY(195),
 880         I40E_PTT_UNUSED_ENTRY(196),
 881         I40E_PTT_UNUSED_ENTRY(197),
 882         I40E_PTT_UNUSED_ENTRY(198),
 883         I40E_PTT_UNUSED_ENTRY(199),
 884
 885         I40E_PTT_UNUSED_ENTRY(200),
 886         I40E_PTT_UNUSED_ENTRY(201),
 887         I40E_PTT_UNUSED_ENTRY(202),
 888         I40E_PTT_UNUSED_ENTRY(203),
 889         I40E_PTT_UNUSED_ENTRY(204),
 890         I40E_PTT_UNUSED_ENTRY(205),
 891         I40E_PTT_UNUSED_ENTRY(206),
 892         I40E_PTT_UNUSED_ENTRY(207),
 893         I40E_PTT_UNUSED_ENTRY(208),
 894         I40E_PTT_UNUSED_ENTRY(209),
 895
 896         I40E_PTT_UNUSED_ENTRY(210),
 897         I40E_PTT_UNUSED_ENTRY(211),
 898         I40E_PTT_UNUSED_ENTRY(212),
 899         I40E_PTT_UNUSED_ENTRY(213),
 900         I40E_PTT_UNUSED_ENTRY(214),
 901         I40E_PTT_UNUSED_ENTRY(215),
 902         I40E_PTT_UNUSED_ENTRY(216),
 903         I40E_PTT_UNUSED_ENTRY(217),
 904         I40E_PTT_UNUSED_ENTRY(218),
 905         I40E_PTT_UNUSED_ENTRY(219),
 906
 907         I40E_PTT_UNUSED_ENTRY(220),
 908         I40E_PTT_UNUSED_ENTRY(221),
 909         I40E_PTT_UNUSED_ENTRY(222),
 910         I40E_PTT_UNUSED_ENTRY(223),
 911         I40E_PTT_UNUSED_ENTRY(224),
 912         I40E_PTT_UNUSED_ENTRY(225),
 913         I40E_PTT_UNUSED_ENTRY(226),
 914         I40E_PTT_UNUSED_ENTRY(227),
 915         I40E_PTT_UNUSED_ENTRY(228),
 916         I40E_PTT_UNUSED_ENTRY(229),
 917
 918         I40E_PTT_UNUSED_ENTRY(230),
 919         I40E_PTT_UNUSED_ENTRY(231),
 920         I40E_PTT_UNUSED_ENTRY(232),
 921         I40E_PTT_UNUSED_ENTRY(233),
 922         I40E_PTT_UNUSED_ENTRY(234),
 923         I40E_PTT_UNUSED_ENTRY(235),
 924         I40E_PTT_UNUSED_ENTRY(236),
 925         I40E_PTT_UNUSED_ENTRY(237),
 926         I40E_PTT_UNUSED_ENTRY(238),
 927         I40E_PTT_UNUSED_ENTRY(239),
 928
 929         I40E_PTT_UNUSED_ENTRY(240),
 930         I40E_PTT_UNUSED_ENTRY(241),
 931         I40E_PTT_UNUSED_ENTRY(242),
 932         I40E_PTT_UNUSED_ENTRY(243),
 933         I40E_PTT_UNUSED_ENTRY(244),
 934         I40E_PTT_UNUSED_ENTRY(245),
 935         I40E_PTT_UNUSED_ENTRY(246),
 936         I40E_PTT_UNUSED_ENTRY(247),
 937         I40E_PTT_UNUSED_ENTRY(248),
 938         I40E_PTT_UNUSED_ENTRY(249),
 939
 940         I40E_PTT_UNUSED_ENTRY(250),
 941         I40E_PTT_UNUSED_ENTRY(251),
 942         I40E_PTT_UNUSED_ENTRY(252),
 943         I40E_PTT_UNUSED_ENTRY(253),
 944         I40E_PTT_UNUSED_ENTRY(254),
 945         I40E_PTT_UNUSED_ENTRY(255)
 946 };
 947
 948
 949 /**
 950  * i40e_validate_mac_addr - Validate unicast MAC address
 951  * @mac_addr: pointer to MAC address
 952  *
 953  * Tests a MAC address to ensure it is a valid Individual Address
 954  **/
 955 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 956 {
 957         enum i40e_status_code status = I40E_SUCCESS;
 958
 959         DEBUGFUNC("i40e_validate_mac_addr");
 960
 961         /* Broadcast addresses ARE multicast addresses
 962          * Make sure it is not a multicast address
 963          * Reject the zero address
 964          */
 965         if (I40E_IS_MULTICAST(mac_addr) ||
 966             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 967               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 968                 status = I40E_ERR_INVALID_MAC_ADDR;
 969
 970         return status;
 971 }
 972 #ifdef PF_DRIVER
 973
 974 /**
 975  * i40e_init_shared_code - Initialize the shared code
 976  * @hw: pointer to hardware structure
 977  *
 978  * This assigns the MAC type and PHY code and inits the NVM.
 979  * Does not touch the hardware. This function must be called prior to any
 980  * other function in the shared code. The i40e_hw structure should be
 981  * memset to 0 prior to calling this function.  The following fields in
 982  * hw structure should be filled in prior to calling this function:
 983  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 984  * subsystem_vendor_id, and revision_id
 985  **/
 986 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 987 {
 988         enum i40e_status_code status = I40E_SUCCESS;
 989         u32 port, ari, func_rid;
 990
 991         DEBUGFUNC("i40e_init_shared_code");
 992
 993         i40e_set_mac_type(hw);
 994
 995         switch (hw->mac.type) {
 996         case I40E_MAC_XL710:
 997         case I40E_MAC_X722:
 998                 break;
 999         default:
1000                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1001         }
1002
1003         hw->phy.get_link_info = true;
1004
1005         /* Determine port number and PF number*/
1006         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1007                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1008         hw->port = (u8)port;
1009         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1010                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1011         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1012         if (ari)
1013                 hw->pf_id = (u8)(func_rid & 0xff);
1014         else
1015                 hw->pf_id = (u8)(func_rid & 0x7);
1016
1017         if (hw->mac.type == I40E_MAC_X722)
1018                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1019                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1020         /* NVMUpdate features structure initialization */
1021         hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1022         hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1023         hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1024         i40e_memset(hw->nvmupd_features.features, 0x0,
1025                     I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1026                     sizeof(*hw->nvmupd_features.features),
1027                     I40E_NONDMA_MEM);
1028
1029         /* No features supported at the moment */
1030         hw->nvmupd_features.features[0] = 0;
1031
1032         status = i40e_init_nvm(hw);
1033         return status;
1034 }
1035
1036 /**
1037  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1038  * @hw: pointer to the hw struct
1039  * @flags: a return indicator of what addresses were added to the addr store
1040  * @addrs: the requestor's mac addr store
1041  * @cmd_details: pointer to command details structure or NULL
1042  **/
1043 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1044                                    u16 *flags,
1045                                    struct i40e_aqc_mac_address_read_data *addrs,
1046                                    struct i40e_asq_cmd_details *cmd_details)
1047 {
1048         struct i40e_aq_desc desc;
1049         struct i40e_aqc_mac_address_read *cmd_data =
1050                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1051         enum i40e_status_code status;
1052
1053         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1054         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1055
1056         status = i40e_asq_send_command(hw, &desc, addrs,
1057                                        sizeof(*addrs), cmd_details);
1058         *flags = LE16_TO_CPU(cmd_data->command_flags);
1059
1060         return status;
1061 }
1062
1063 /**
1064  * i40e_aq_mac_address_write - Change the MAC addresses
1065  * @hw: pointer to the hw struct
1066  * @flags: indicates which MAC to be written
1067  * @mac_addr: address to write
1068  * @cmd_details: pointer to command details structure or NULL
1069  **/
1070 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1071                                     u16 flags, u8 *mac_addr,
1072                                     struct i40e_asq_cmd_details *cmd_details)
1073 {
1074         struct i40e_aq_desc desc;
1075         struct i40e_aqc_mac_address_write *cmd_data =
1076                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1077         enum i40e_status_code status;
1078
1079         i40e_fill_default_direct_cmd_desc(&desc,
1080                                           i40e_aqc_opc_mac_address_write);
1081         cmd_data->command_flags = CPU_TO_LE16(flags);
1082         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1083         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1084                                         ((u32)mac_addr[3] << 16) |
1085                                         ((u32)mac_addr[4] << 8) |
1086                                         mac_addr[5]);
1087
1088         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1089
1090         return status;
1091 }
1092
1093 /**
1094  * i40e_get_mac_addr - get MAC address
1095  * @hw: pointer to the HW structure
1096  * @mac_addr: pointer to MAC address
1097  *
1098  * Reads the adapter's MAC address from register
1099  **/
1100 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1101 {
1102         struct i40e_aqc_mac_address_read_data addrs;
1103         enum i40e_status_code status;
1104         u16 flags = 0;
1105
1106         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1107
1108         if (flags & I40E_AQC_LAN_ADDR_VALID)
1109                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1110                         I40E_NONDMA_TO_NONDMA);
1111
1112         return status;
1113 }
1114
1115 /**
1116  * i40e_get_port_mac_addr - get Port MAC address
1117  * @hw: pointer to the HW structure
1118  * @mac_addr: pointer to Port MAC address
1119  *
1120  * Reads the adapter's Port MAC address
1121  **/
1122 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1123 {
1124         struct i40e_aqc_mac_address_read_data addrs;
1125         enum i40e_status_code status;
1126         u16 flags = 0;
1127
1128         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1129         if (status)
1130                 return status;
1131
1132         if (flags & I40E_AQC_PORT_ADDR_VALID)
1133                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1134                         I40E_NONDMA_TO_NONDMA);
1135         else
1136                 status = I40E_ERR_INVALID_MAC_ADDR;
1137
1138         return status;
1139 }
1140
1141 /**
1142  * i40e_pre_tx_queue_cfg - pre tx queue configure
1143  * @hw: pointer to the HW structure
1144  * @queue: target pf queue index
1145  * @enable: state change request
1146  *
1147  * Handles hw requirement to indicate intention to enable
1148  * or disable target queue.
1149  **/
1150 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1151 {
1152         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1153         u32 reg_block = 0;
1154         u32 reg_val;
1155
1156         if (abs_queue_idx >= 128) {
1157                 reg_block = abs_queue_idx / 128;
1158                 abs_queue_idx %= 128;
1159         }
1160
1161         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1162         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1163         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1164
1165         if (enable)
1166                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1167         else
1168                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1169
1170         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1171 }
1172
1173 /**
1174  * i40e_get_san_mac_addr - get SAN MAC address
1175  * @hw: pointer to the HW structure
1176  * @mac_addr: pointer to SAN MAC address
1177  *
1178  * Reads the adapter's SAN MAC address from NVM
1179  **/
1180 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1181                                             u8 *mac_addr)
1182 {
1183         struct i40e_aqc_mac_address_read_data addrs;
1184         enum i40e_status_code status;
1185         u16 flags = 0;
1186
1187         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1188         if (status)
1189                 return status;
1190
1191         if (flags & I40E_AQC_SAN_ADDR_VALID)
1192                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1193                         I40E_NONDMA_TO_NONDMA);
1194         else
1195                 status = I40E_ERR_INVALID_MAC_ADDR;
1196
1197         return status;
1198 }
1199
1200 /**
1201  *  i40e_read_pba_string - Reads part number string from EEPROM
1202  *  @hw: pointer to hardware structure
1203  *  @pba_num: stores the part number string from the EEPROM
1204  *  @pba_num_size: part number string buffer length
1205  *
1206  *  Reads the part number string from the EEPROM.
1207  **/
1208 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1209                                             u32 pba_num_size)
1210 {
1211         enum i40e_status_code status = I40E_SUCCESS;
1212         u16 pba_word = 0;
1213         u16 pba_size = 0;
1214         u16 pba_ptr = 0;
1215         u16 i = 0;
1216
1217         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1218         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1219                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1220                 return status;
1221         }
1222
1223         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1224         if (status != I40E_SUCCESS) {
1225                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1226                 return status;
1227         }
1228
1229         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1230         if (status != I40E_SUCCESS) {
1231                 DEBUGOUT("Failed to read PBA Block size.\n");
1232                 return status;
1233         }
1234
1235         /* Subtract one to get PBA word count (PBA Size word is included in
1236          * total size)
1237          */
1238         pba_size--;
1239         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1240                 DEBUGOUT("Buffer to small for PBA data.\n");
1241                 return I40E_ERR_PARAM;
1242         }
1243
1244         for (i = 0; i < pba_size; i++) {
1245                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1246                 if (status != I40E_SUCCESS) {
1247                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1248                         return status;
1249                 }
1250
1251                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1252                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1253         }
1254         pba_num[(pba_size * 2)] = '\0';
1255
1256         return status;
1257 }
1258
1259 /**
1260  * i40e_get_media_type - Gets media type
1261  * @hw: pointer to the hardware structure
1262  **/
1263 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1264 {
1265         enum i40e_media_type media;
1266
1267         switch (hw->phy.link_info.phy_type) {
1268         case I40E_PHY_TYPE_10GBASE_SR:
1269         case I40E_PHY_TYPE_10GBASE_LR:
1270         case I40E_PHY_TYPE_1000BASE_SX:
1271         case I40E_PHY_TYPE_1000BASE_LX:
1272         case I40E_PHY_TYPE_40GBASE_SR4:
1273         case I40E_PHY_TYPE_40GBASE_LR4:
1274         case I40E_PHY_TYPE_25GBASE_LR:
1275         case I40E_PHY_TYPE_25GBASE_SR:
1276                 media = I40E_MEDIA_TYPE_FIBER;
1277                 break;
1278         case I40E_PHY_TYPE_100BASE_TX:
1279         case I40E_PHY_TYPE_1000BASE_T:
1280         case I40E_PHY_TYPE_2_5GBASE_T:
1281         case I40E_PHY_TYPE_5GBASE_T:
1282         case I40E_PHY_TYPE_10GBASE_T:
1283                 media = I40E_MEDIA_TYPE_BASET;
1284                 break;
1285         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1286         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1287         case I40E_PHY_TYPE_10GBASE_CR1:
1288         case I40E_PHY_TYPE_40GBASE_CR4:
1289         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1290         case I40E_PHY_TYPE_40GBASE_AOC:
1291         case I40E_PHY_TYPE_10GBASE_AOC:
1292         case I40E_PHY_TYPE_25GBASE_CR:
1293         case I40E_PHY_TYPE_25GBASE_AOC:
1294         case I40E_PHY_TYPE_25GBASE_ACC:
1295                 media = I40E_MEDIA_TYPE_DA;
1296                 break;
1297         case I40E_PHY_TYPE_1000BASE_KX:
1298         case I40E_PHY_TYPE_10GBASE_KX4:
1299         case I40E_PHY_TYPE_10GBASE_KR:
1300         case I40E_PHY_TYPE_40GBASE_KR4:
1301         case I40E_PHY_TYPE_20GBASE_KR2:
1302         case I40E_PHY_TYPE_25GBASE_KR:
1303                 media = I40E_MEDIA_TYPE_BACKPLANE;
1304                 break;
1305         case I40E_PHY_TYPE_SGMII:
1306         case I40E_PHY_TYPE_XAUI:
1307         case I40E_PHY_TYPE_XFI:
1308         case I40E_PHY_TYPE_XLAUI:
1309         case I40E_PHY_TYPE_XLPPI:
1310         default:
1311                 media = I40E_MEDIA_TYPE_UNKNOWN;
1312                 break;
1313         }
1314
1315         return media;
1316 }
1317
1318 /**
1319  * i40e_poll_globr - Poll for Global Reset completion
1320  * @hw: pointer to the hardware structure
1321  * @retry_limit: how many times to retry before failure
1322  **/
1323 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1324                                              u32 retry_limit)
1325 {
1326         u32 cnt, reg = 0;
1327
1328         for (cnt = 0; cnt < retry_limit; cnt++) {
1329                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1330                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1331                         return I40E_SUCCESS;
1332                 i40e_msec_delay(100);
1333         }
1334
1335         DEBUGOUT("Global reset failed.\n");
1336         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1337
1338         return I40E_ERR_RESET_FAILED;
1339 }
1340
1341 #define I40E_PF_RESET_WAIT_COUNT        200
1342 /**
1343  * i40e_pf_reset - Reset the PF
1344  * @hw: pointer to the hardware structure
1345  *
1346  * Assuming someone else has triggered a global reset,
1347  * assure the global reset is complete and then reset the PF
1348  **/
1349 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1350 {
1351         u32 cnt = 0;
1352         u32 cnt1 = 0;
1353         u32 reg = 0;
1354         u32 grst_del;
1355
1356         /* Poll for Global Reset steady state in case of recent GRST.
1357          * The grst delay value is in 100ms units, and we'll wait a
1358          * couple counts longer to be sure we don't just miss the end.
1359          */
1360         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1361                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1362                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1363
1364         grst_del = min(grst_del * 20, 160U);
1365
1366         for (cnt = 0; cnt < grst_del; cnt++) {
1367                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1368                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1369                         break;
1370                 i40e_msec_delay(100);
1371         }
1372         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1373                 DEBUGOUT("Global reset polling failed to complete.\n");
1374                 return I40E_ERR_RESET_FAILED;
1375         }
1376
1377         /* Now Wait for the FW to be ready */
1378         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1379                 reg = rd32(hw, I40E_GLNVM_ULD);
1380                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1381                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1382                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1383                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1384                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1385                         break;
1386                 }
1387                 i40e_msec_delay(10);
1388         }
1389         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1390                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1391                 DEBUGOUT("wait for FW Reset complete timedout\n");
1392                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1393                 return I40E_ERR_RESET_FAILED;
1394         }
1395
1396         /* If there was a Global Reset in progress when we got here,
1397          * we don't need to do the PF Reset
1398          */
1399         if (!cnt) {
1400                 u32 reg2 = 0;
1401
1402                 reg = rd32(hw, I40E_PFGEN_CTRL);
1403                 wr32(hw, I40E_PFGEN_CTRL,
1404                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1405                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1406                         reg = rd32(hw, I40E_PFGEN_CTRL);
1407                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1408                                 break;
1409                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1410                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1411                                 break;
1412                         i40e_msec_delay(1);
1413                 }
1414                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1415                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1416                                 return I40E_ERR_RESET_FAILED;
1417                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1418                         DEBUGOUT("PF reset polling failed to complete.\n");
1419                         return I40E_ERR_RESET_FAILED;
1420                 }
1421         }
1422
1423         i40e_clear_pxe_mode(hw);
1424
1425
1426         return I40E_SUCCESS;
1427 }
1428
1429 /**
1430  * i40e_clear_hw - clear out any left over hw state
1431  * @hw: pointer to the hw struct
1432  *
1433  * Clear queues and interrupts, typically called at init time,
1434  * but after the capabilities have been found so we know how many
1435  * queues and msix vectors have been allocated.
1436  **/
1437 void i40e_clear_hw(struct i40e_hw *hw)
1438 {
1439         u32 num_queues, base_queue;
1440         u32 num_pf_int;
1441         u32 num_vf_int;
1442         u32 num_vfs;
1443         u32 i, j;
1444         u32 val;
1445         u32 eol = 0x7ff;
1446
1447         /* get number of interrupts, queues, and vfs */
1448         val = rd32(hw, I40E_GLPCI_CNF2);
1449         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1450                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1451         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1452                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1453
1454         val = rd32(hw, I40E_PFLAN_QALLOC);
1455         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1456                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1457         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1458                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1459         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1460                 num_queues = (j - base_queue) + 1;
1461         else
1462                 num_queues = 0;
1463
1464         val = rd32(hw, I40E_PF_VT_PFALLOC);
1465         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1466                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1467         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1468                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1469         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1470                 num_vfs = (j - i) + 1;
1471         else
1472                 num_vfs = 0;
1473
1474         /* stop all the interrupts */
1475         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1476         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1477         for (i = 0; i < num_pf_int - 2; i++)
1478                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1479
1480         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1481         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1482         wr32(hw, I40E_PFINT_LNKLST0, val);
1483         for (i = 0; i < num_pf_int - 2; i++)
1484                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1485         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1486         for (i = 0; i < num_vfs; i++)
1487                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1488         for (i = 0; i < num_vf_int - 2; i++)
1489                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1490
1491         /* warn the HW of the coming Tx disables */
1492         for (i = 0; i < num_queues; i++) {
1493                 u32 abs_queue_idx = base_queue + i;
1494                 u32 reg_block = 0;
1495
1496                 if (abs_queue_idx >= 128) {
1497                         reg_block = abs_queue_idx / 128;
1498                         abs_queue_idx %= 128;
1499                 }
1500
1501                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1502                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1503                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1504                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1505
1506                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1507         }
1508         i40e_usec_delay(400);
1509
1510         /* stop all the queues */
1511         for (i = 0; i < num_queues; i++) {
1512                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1513                 wr32(hw, I40E_QTX_ENA(i), 0);
1514                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1515                 wr32(hw, I40E_QRX_ENA(i), 0);
1516         }
1517
1518         /* short wait for all queue disables to settle */
1519         i40e_usec_delay(50);
1520 }
1521
1522 /**
1523  * i40e_clear_pxe_mode - clear pxe operations mode
1524  * @hw: pointer to the hw struct
1525  *
1526  * Make sure all PXE mode settings are cleared, including things
1527  * like descriptor fetch/write-back mode.
1528  **/
1529 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1530 {
1531         if (i40e_check_asq_alive(hw))
1532                 i40e_aq_clear_pxe_mode(hw, NULL);
1533 }
1534
1535 /**
1536  * i40e_led_is_mine - helper to find matching led
1537  * @hw: pointer to the hw struct
1538  * @idx: index into GPIO registers
1539  *
1540  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1541  */
1542 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1543 {
1544         u32 gpio_val = 0;
1545         u32 port;
1546
1547         if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1548             !hw->func_caps.led[idx])
1549                 return 0;
1550         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1551         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1552                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1553
1554         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1555          * if it is not our port then ignore
1556          */
1557         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1558             (port != hw->port))
1559                 return 0;
1560
1561         return gpio_val;
1562 }
1563
1564 #define I40E_COMBINED_ACTIVITY 0xA
1565 #define I40E_FILTER_ACTIVITY 0xE
1566 #define I40E_LINK_ACTIVITY 0xC
1567 #define I40E_MAC_ACTIVITY 0xD
1568 #define I40E_FW_LED BIT(4)
1569 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1570                              I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1571
1572 #define I40E_LED0 22
1573
1574 #define I40E_PIN_FUNC_SDP 0x0
1575 #define I40E_PIN_FUNC_LED 0x1
1576
1577 /**
1578  * i40e_led_get - return current on/off mode
1579  * @hw: pointer to the hw struct
1580  *
1581  * The value returned is the 'mode' field as defined in the
1582  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1583  * values are variations of possible behaviors relating to
1584  * blink, link, and wire.
1585  **/
1586 u32 i40e_led_get(struct i40e_hw *hw)
1587 {
1588         u32 current_mode = 0;
1589         u32 mode = 0;
1590         int i;
1591
1592         /* as per the documentation GPIO 22-29 are the LED
1593          * GPIO pins named LED0..LED7
1594          */
1595         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1596                 u32 gpio_val = i40e_led_is_mine(hw, i);
1597
1598                 if (!gpio_val)
1599                         continue;
1600
1601                 /* ignore gpio LED src mode entries related to the activity
1602                  *  LEDs
1603                  */
1604                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1605                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1606                 switch (current_mode) {
1607                 case I40E_COMBINED_ACTIVITY:
1608                 case I40E_FILTER_ACTIVITY:
1609                 case I40E_MAC_ACTIVITY:
1610                 case I40E_LINK_ACTIVITY:
1611                         continue;
1612                 default:
1613                         break;
1614                 }
1615
1616                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1617                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1618                 break;
1619         }
1620
1621         return mode;
1622 }
1623
1624 /**
1625  * i40e_led_set - set new on/off mode
1626  * @hw: pointer to the hw struct
1627  * @mode: 0=off, 0xf=on (else see manual for mode details)
1628  * @blink: true if the LED should blink when on, false if steady
1629  *
1630  * if this function is used to turn on the blink it should
1631  * be used to disable the blink when restoring the original state.
1632  **/
1633 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1634 {
1635         u32 current_mode = 0;
1636         int i;
1637
1638         if (mode & ~I40E_LED_MODE_VALID) {
1639                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1640                 return;
1641         }
1642
1643         /* as per the documentation GPIO 22-29 are the LED
1644          * GPIO pins named LED0..LED7
1645          */
1646         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1647                 u32 gpio_val = i40e_led_is_mine(hw, i);
1648
1649                 if (!gpio_val)
1650                         continue;
1651
1652                 /* ignore gpio LED src mode entries related to the activity
1653                  * LEDs
1654                  */
1655                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1656                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1657                 switch (current_mode) {
1658                 case I40E_COMBINED_ACTIVITY:
1659                 case I40E_FILTER_ACTIVITY:
1660                 case I40E_MAC_ACTIVITY:
1661                 case I40E_LINK_ACTIVITY:
1662                         continue;
1663                 default:
1664                         break;
1665                 }
1666
1667                 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1668                         u32 pin_func = 0;
1669
1670                         if (mode & I40E_FW_LED)
1671                                 pin_func = I40E_PIN_FUNC_SDP;
1672                         else
1673                                 pin_func = I40E_PIN_FUNC_LED;
1674
1675                         gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1676                         gpio_val |= ((pin_func <<
1677                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1678                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1679                 }
1680                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1681                 /* this & is a bit of paranoia, but serves as a range check */
1682                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1683                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1684
1685                 if (blink)
1686                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1687                 else
1688                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1689
1690                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1691                 break;
1692         }
1693 }
1694
1695 /* Admin command wrappers */
1696
1697 /**
1698  * i40e_aq_get_phy_capabilities
1699  * @hw: pointer to the hw struct
1700  * @abilities: structure for PHY capabilities to be filled
1701  * @qualified_modules: report Qualified Modules
1702  * @report_init: report init capabilities (active are default)
1703  * @cmd_details: pointer to command details structure or NULL
1704  *
1705  * Returns the various PHY abilities supported on the Port.
1706  **/
1707 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1708                         bool qualified_modules, bool report_init,
1709                         struct i40e_aq_get_phy_abilities_resp *abilities,
1710                         struct i40e_asq_cmd_details *cmd_details)
1711 {
1712         struct i40e_aq_desc desc;
1713         enum i40e_status_code status;
1714         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1715         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1716
1717         if (!abilities)
1718                 return I40E_ERR_PARAM;
1719
1720         do {
1721                 i40e_fill_default_direct_cmd_desc(&desc,
1722                                                i40e_aqc_opc_get_phy_abilities);
1723
1724                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1725                 if (abilities_size > I40E_AQ_LARGE_BUF)
1726                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1727
1728                 if (qualified_modules)
1729                         desc.params.external.param0 |=
1730                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1731
1732                 if (report_init)
1733                         desc.params.external.param0 |=
1734                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1735
1736                 status = i40e_asq_send_command(hw, &desc, abilities,
1737                                                abilities_size, cmd_details);
1738
1739                 switch (hw->aq.asq_last_status) {
1740                 case I40E_AQ_RC_EIO:
1741                         status = I40E_ERR_UNKNOWN_PHY;
1742                         break;
1743                 case I40E_AQ_RC_EAGAIN:
1744                         i40e_msec_delay(1);
1745                         total_delay++;
1746                         status = I40E_ERR_TIMEOUT;
1747                         break;
1748                 /* also covers I40E_AQ_RC_OK */
1749                 default:
1750                         break;
1751                 }
1752
1753         } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1754                 (total_delay < max_delay));
1755
1756         if (status != I40E_SUCCESS)
1757                 return status;
1758
1759         if (report_init) {
1760                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1761                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1762                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1763                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1764                 } else {
1765                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1766                         hw->phy.phy_types |=
1767                                         ((u64)abilities->phy_type_ext << 32);
1768                 }
1769         }
1770
1771         return status;
1772 }
1773
1774 /**
1775  * i40e_aq_set_phy_config
1776  * @hw: pointer to the hw struct
1777  * @config: structure with PHY configuration to be set
1778  * @cmd_details: pointer to command details structure or NULL
1779  *
1780  * Set the various PHY configuration parameters
1781  * supported on the Port.One or more of the Set PHY config parameters may be
1782  * ignored in an MFP mode as the PF may not have the privilege to set some
1783  * of the PHY Config parameters. This status will be indicated by the
1784  * command response.
1785  **/
1786 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1787                                 struct i40e_aq_set_phy_config *config,
1788                                 struct i40e_asq_cmd_details *cmd_details)
1789 {
1790         struct i40e_aq_desc desc;
1791         struct i40e_aq_set_phy_config *cmd =
1792                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1793         enum i40e_status_code status;
1794
1795         if (!config)
1796                 return I40E_ERR_PARAM;
1797
1798         i40e_fill_default_direct_cmd_desc(&desc,
1799                                           i40e_aqc_opc_set_phy_config);
1800
1801         *cmd = *config;
1802
1803         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1804
1805         return status;
1806 }
1807
1808 /**
1809  * i40e_set_fc
1810  * @hw: pointer to the hw struct
1811  * @aq_failures: buffer to return AdminQ failure information
1812  * @atomic_restart: whether to enable atomic link restart
1813  *
1814  * Set the requested flow control mode using set_phy_config.
1815  **/
1816 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1817                                   bool atomic_restart)
1818 {
1819         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1820         struct i40e_aq_get_phy_abilities_resp abilities;
1821         struct i40e_aq_set_phy_config config;
1822         enum i40e_status_code status;
1823         u8 pause_mask = 0x0;
1824
1825         *aq_failures = 0x0;
1826
1827         switch (fc_mode) {
1828         case I40E_FC_FULL:
1829                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1830                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1831                 break;
1832         case I40E_FC_RX_PAUSE:
1833                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1834                 break;
1835         case I40E_FC_TX_PAUSE:
1836                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1837                 break;
1838         default:
1839                 break;
1840         }
1841
1842         /* Get the current phy config */
1843         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1844                                               NULL);
1845         if (status) {
1846                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1847                 return status;
1848         }
1849
1850         memset(&config, 0, sizeof(config));
1851         /* clear the old pause settings */
1852         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1853                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1854         /* set the new abilities */
1855         config.abilities |= pause_mask;
1856         /* If the abilities have changed, then set the new config */
1857         if (config.abilities != abilities.abilities) {
1858                 /* Auto restart link so settings take effect */
1859                 if (atomic_restart)
1860                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1861                 /* Copy over all the old settings */
1862                 config.phy_type = abilities.phy_type;
1863                 config.phy_type_ext = abilities.phy_type_ext;
1864                 config.link_speed = abilities.link_speed;
1865                 config.eee_capability = abilities.eee_capability;
1866                 config.eeer = abilities.eeer_val;
1867                 config.low_power_ctrl = abilities.d3_lpan;
1868                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1869                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1870                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1871
1872                 if (status)
1873                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1874         }
1875         /* Update the link info */
1876         status = i40e_update_link_info(hw);
1877         if (status) {
1878                 /* Wait a little bit (on 40G cards it sometimes takes a really
1879                  * long time for link to come back from the atomic reset)
1880                  * and try once more
1881                  */
1882                 i40e_msec_delay(1000);
1883                 status = i40e_update_link_info(hw);
1884         }
1885         if (status)
1886                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1887
1888         return status;
1889 }
1890
1891 /**
1892  * i40e_aq_set_mac_config
1893  * @hw: pointer to the hw struct
1894  * @max_frame_size: Maximum Frame Size to be supported by the port
1895  * @crc_en: Tell HW to append a CRC to outgoing frames
1896  * @pacing: Pacing configurations
1897  * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1898  * @cmd_details: pointer to command details structure or NULL
1899  *
1900  * Configure MAC settings for frame size, jumbo frame support and the
1901  * addition of a CRC by the hardware.
1902  **/
1903 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1904                                 u16 max_frame_size,
1905                                 bool crc_en, u16 pacing,
1906                                 bool auto_drop_blocking_packets,
1907                                 struct i40e_asq_cmd_details *cmd_details)
1908 {
1909         struct i40e_aq_desc desc;
1910         struct i40e_aq_set_mac_config *cmd =
1911                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1912         enum i40e_status_code status;
1913
1914         if (max_frame_size == 0)
1915                 return I40E_ERR_PARAM;
1916
1917         i40e_fill_default_direct_cmd_desc(&desc,
1918                                           i40e_aqc_opc_set_mac_config);
1919
1920         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1921         cmd->params = ((u8)pacing & 0x0F) << 3;
1922         if (crc_en)
1923                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1924
1925         if (auto_drop_blocking_packets) {
1926                 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1927                         cmd->params |=
1928                                 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1929                 else
1930                         i40e_debug(hw, I40E_DEBUG_ALL,
1931                                    "This FW api version does not support drop mode.\n");
1932         }
1933
1934 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1935         cmd->fc_refresh_threshold =
1936                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1937
1938         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1939
1940         return status;
1941 }
1942
1943 /**
1944  * i40e_aq_clear_pxe_mode
1945  * @hw: pointer to the hw struct
1946  * @cmd_details: pointer to command details structure or NULL
1947  *
1948  * Tell the firmware that the driver is taking over from PXE
1949  **/
1950 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1951                         struct i40e_asq_cmd_details *cmd_details)
1952 {
1953         enum i40e_status_code status;
1954         struct i40e_aq_desc desc;
1955         struct i40e_aqc_clear_pxe *cmd =
1956                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1957
1958         i40e_fill_default_direct_cmd_desc(&desc,
1959                                           i40e_aqc_opc_clear_pxe_mode);
1960
1961         cmd->rx_cnt = 0x2;
1962
1963         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1964
1965         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1966
1967         return status;
1968 }
1969
1970 /**
1971  * i40e_aq_set_link_restart_an
1972  * @hw: pointer to the hw struct
1973  * @enable_link: if true: enable link, if false: disable link
1974  * @cmd_details: pointer to command details structure or NULL
1975  *
1976  * Sets up the link and restarts the Auto-Negotiation over the link.
1977  **/
1978 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1979                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1980 {
1981         struct i40e_aq_desc desc;
1982         struct i40e_aqc_set_link_restart_an *cmd =
1983                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1984         enum i40e_status_code status;
1985
1986         i40e_fill_default_direct_cmd_desc(&desc,
1987                                           i40e_aqc_opc_set_link_restart_an);
1988
1989         cmd->command = I40E_AQ_PHY_RESTART_AN;
1990         if (enable_link)
1991                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1992         else
1993                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1994
1995         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1996
1997         return status;
1998 }
1999
2000 /**
2001  * i40e_aq_get_link_info
2002  * @hw: pointer to the hw struct
2003  * @enable_lse: enable/disable LinkStatusEvent reporting
2004  * @link: pointer to link status structure - optional
2005  * @cmd_details: pointer to command details structure or NULL
2006  *
2007  * Returns the link status of the adapter.
2008  **/
2009 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
2010                                 bool enable_lse, struct i40e_link_status *link,
2011                                 struct i40e_asq_cmd_details *cmd_details)
2012 {
2013         struct i40e_aq_desc desc;
2014         struct i40e_aqc_get_link_status *resp =
2015                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
2016         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
2017         enum i40e_status_code status;
2018         bool tx_pause, rx_pause;
2019         u16 command_flags;
2020
2021         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2022
2023         if (enable_lse)
2024                 command_flags = I40E_AQ_LSE_ENABLE;
2025         else
2026                 command_flags = I40E_AQ_LSE_DISABLE;
2027         resp->command_flags = CPU_TO_LE16(command_flags);
2028
2029         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2030
2031         if (status != I40E_SUCCESS)
2032                 goto aq_get_link_info_exit;
2033
2034         /* save off old link status information */
2035         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2036                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2037
2038         /* update link status */
2039         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2040         hw->phy.media_type = i40e_get_media_type(hw);
2041         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2042         hw_link_info->link_info = resp->link_info;
2043         hw_link_info->an_info = resp->an_info;
2044         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2045                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
2046         hw_link_info->ext_info = resp->ext_info;
2047         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2048         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2049         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2050
2051         /* update fc info */
2052         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2053         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2054         if (tx_pause & rx_pause)
2055                 hw->fc.current_mode = I40E_FC_FULL;
2056         else if (tx_pause)
2057                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2058         else if (rx_pause)
2059                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2060         else
2061                 hw->fc.current_mode = I40E_FC_NONE;
2062
2063         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2064                 hw_link_info->crc_enable = true;
2065         else
2066                 hw_link_info->crc_enable = false;
2067
2068         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2069                 hw_link_info->lse_enable = true;
2070         else
2071                 hw_link_info->lse_enable = false;
2072
2073         if ((hw->mac.type == I40E_MAC_XL710) &&
2074             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2075              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2076                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2077
2078         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2079             hw->mac.type != I40E_MAC_X722) {
2080                 __le32 tmp;
2081
2082                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2083                             I40E_NONDMA_TO_NONDMA);
2084                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2085                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2086         }
2087
2088         /* save link status information */
2089         if (link)
2090                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2091                             I40E_NONDMA_TO_NONDMA);
2092
2093         /* flag cleared so helper functions don't call AQ again */
2094         hw->phy.get_link_info = false;
2095
2096 aq_get_link_info_exit:
2097         return status;
2098 }
2099
2100 /**
2101  * i40e_aq_set_phy_int_mask
2102  * @hw: pointer to the hw struct
2103  * @mask: interrupt mask to be set
2104  * @cmd_details: pointer to command details structure or NULL
2105  *
2106  * Set link interrupt mask.
2107  **/
2108 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2109                                 u16 mask,
2110                                 struct i40e_asq_cmd_details *cmd_details)
2111 {
2112         struct i40e_aq_desc desc;
2113         struct i40e_aqc_set_phy_int_mask *cmd =
2114                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2115         enum i40e_status_code status;
2116
2117         i40e_fill_default_direct_cmd_desc(&desc,
2118                                           i40e_aqc_opc_set_phy_int_mask);
2119
2120         cmd->event_mask = CPU_TO_LE16(mask);
2121
2122         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2123
2124         return status;
2125 }
2126
2127 /**
2128  * i40e_aq_get_local_advt_reg
2129  * @hw: pointer to the hw struct
2130  * @advt_reg: local AN advertisement register value
2131  * @cmd_details: pointer to command details structure or NULL
2132  *
2133  * Get the Local AN advertisement register value.
2134  **/
2135 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2136                                 u64 *advt_reg,
2137                                 struct i40e_asq_cmd_details *cmd_details)
2138 {
2139         struct i40e_aq_desc desc;
2140         struct i40e_aqc_an_advt_reg *resp =
2141                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2142         enum i40e_status_code status;
2143
2144         i40e_fill_default_direct_cmd_desc(&desc,
2145                                           i40e_aqc_opc_get_local_advt_reg);
2146
2147         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2148
2149         if (status != I40E_SUCCESS)
2150                 goto aq_get_local_advt_reg_exit;
2151
2152         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2153         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2154
2155 aq_get_local_advt_reg_exit:
2156         return status;
2157 }
2158
2159 /**
2160  * i40e_aq_set_local_advt_reg
2161  * @hw: pointer to the hw struct
2162  * @advt_reg: local AN advertisement register value
2163  * @cmd_details: pointer to command details structure or NULL
2164  *
2165  * Get the Local AN advertisement register value.
2166  **/
2167 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2168                                 u64 advt_reg,
2169                                 struct i40e_asq_cmd_details *cmd_details)
2170 {
2171         struct i40e_aq_desc desc;
2172         struct i40e_aqc_an_advt_reg *cmd =
2173                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2174         enum i40e_status_code status;
2175
2176         i40e_fill_default_direct_cmd_desc(&desc,
2177                                           i40e_aqc_opc_get_local_advt_reg);
2178
2179         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2180         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2181
2182         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2183
2184         return status;
2185 }
2186
2187 /**
2188  * i40e_aq_get_partner_advt
2189  * @hw: pointer to the hw struct
2190  * @advt_reg: AN partner advertisement register value
2191  * @cmd_details: pointer to command details structure or NULL
2192  *
2193  * Get the link partner AN advertisement register value.
2194  **/
2195 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2196                                 u64 *advt_reg,
2197                                 struct i40e_asq_cmd_details *cmd_details)
2198 {
2199         struct i40e_aq_desc desc;
2200         struct i40e_aqc_an_advt_reg *resp =
2201                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2202         enum i40e_status_code status;
2203
2204         i40e_fill_default_direct_cmd_desc(&desc,
2205                                           i40e_aqc_opc_get_partner_advt);
2206
2207         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2208
2209         if (status != I40E_SUCCESS)
2210                 goto aq_get_partner_advt_exit;
2211
2212         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2213         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2214
2215 aq_get_partner_advt_exit:
2216         return status;
2217 }
2218
2219 /**
2220  * i40e_aq_set_lb_modes
2221  * @hw: pointer to the hw struct
2222  * @lb_modes: loopback mode to be set
2223  * @cmd_details: pointer to command details structure or NULL
2224  *
2225  * Sets loopback modes.
2226  **/
2227 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2228                                 u16 lb_modes,
2229                                 struct i40e_asq_cmd_details *cmd_details)
2230 {
2231         struct i40e_aq_desc desc;
2232         struct i40e_aqc_set_lb_mode *cmd =
2233                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2234         enum i40e_status_code status;
2235
2236         i40e_fill_default_direct_cmd_desc(&desc,
2237                                           i40e_aqc_opc_set_lb_modes);
2238
2239         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2240
2241         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2242
2243         return status;
2244 }
2245
2246 /**
2247  * i40e_aq_set_phy_debug
2248  * @hw: pointer to the hw struct
2249  * @cmd_flags: debug command flags
2250  * @cmd_details: pointer to command details structure or NULL
2251  *
2252  * Reset the external PHY.
2253  **/
2254 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2255                                 struct i40e_asq_cmd_details *cmd_details)
2256 {
2257         struct i40e_aq_desc desc;
2258         struct i40e_aqc_set_phy_debug *cmd =
2259                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2260         enum i40e_status_code status;
2261
2262         i40e_fill_default_direct_cmd_desc(&desc,
2263                                           i40e_aqc_opc_set_phy_debug);
2264
2265         cmd->command_flags = cmd_flags;
2266
2267         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2268
2269         return status;
2270 }
2271
2272 /**
2273  * i40e_aq_add_vsi
2274  * @hw: pointer to the hw struct
2275  * @vsi_ctx: pointer to a vsi context struct
2276  * @cmd_details: pointer to command details structure or NULL
2277  *
2278  * Add a VSI context to the hardware.
2279 **/
2280 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2281                                 struct i40e_vsi_context *vsi_ctx,
2282                                 struct i40e_asq_cmd_details *cmd_details)
2283 {
2284         struct i40e_aq_desc desc;
2285         struct i40e_aqc_add_get_update_vsi *cmd =
2286                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2287         struct i40e_aqc_add_get_update_vsi_completion *resp =
2288                 (struct i40e_aqc_add_get_update_vsi_completion *)
2289                 &desc.params.raw;
2290         enum i40e_status_code status;
2291
2292         i40e_fill_default_direct_cmd_desc(&desc,
2293                                           i40e_aqc_opc_add_vsi);
2294
2295         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2296         cmd->connection_type = vsi_ctx->connection_type;
2297         cmd->vf_id = vsi_ctx->vf_num;
2298         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2299
2300         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2301
2302         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2303                                     sizeof(vsi_ctx->info), cmd_details);
2304
2305         if (status != I40E_SUCCESS)
2306                 goto aq_add_vsi_exit;
2307
2308         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2309         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2310         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2311         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2312
2313 aq_add_vsi_exit:
2314         return status;
2315 }
2316
2317 /**
2318  * i40e_aq_set_default_vsi
2319  * @hw: pointer to the hw struct
2320  * @seid: vsi number
2321  * @cmd_details: pointer to command details structure or NULL
2322  **/
2323 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2324                                 u16 seid,
2325                                 struct i40e_asq_cmd_details *cmd_details)
2326 {
2327         struct i40e_aq_desc desc;
2328         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2329                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2330                 &desc.params.raw;
2331         enum i40e_status_code status;
2332
2333         i40e_fill_default_direct_cmd_desc(&desc,
2334                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2335
2336         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2337         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2338         cmd->seid = CPU_TO_LE16(seid);
2339
2340         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2341
2342         return status;
2343 }
2344
2345 /**
2346  * i40e_aq_clear_default_vsi
2347  * @hw: pointer to the hw struct
2348  * @seid: vsi number
2349  * @cmd_details: pointer to command details structure or NULL
2350  **/
2351 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2352                                 u16 seid,
2353                                 struct i40e_asq_cmd_details *cmd_details)
2354 {
2355         struct i40e_aq_desc desc;
2356         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2357                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2358                 &desc.params.raw;
2359         enum i40e_status_code status;
2360
2361         i40e_fill_default_direct_cmd_desc(&desc,
2362                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2363
2364         cmd->promiscuous_flags = CPU_TO_LE16(0);
2365         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2366         cmd->seid = CPU_TO_LE16(seid);
2367
2368         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2369
2370         return status;
2371 }
2372
2373 /**
2374  * i40e_aq_set_vsi_unicast_promiscuous
2375  * @hw: pointer to the hw struct
2376  * @seid: vsi number
2377  * @set: set unicast promiscuous enable/disable
2378  * @cmd_details: pointer to command details structure or NULL
2379  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2380  **/
2381 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2382                                 u16 seid, bool set,
2383                                 struct i40e_asq_cmd_details *cmd_details,
2384                                 bool rx_only_promisc)
2385 {
2386         struct i40e_aq_desc desc;
2387         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2388                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2389         enum i40e_status_code status;
2390         u16 flags = 0;
2391
2392         i40e_fill_default_direct_cmd_desc(&desc,
2393                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2394
2395         if (set) {
2396                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2397                 if (rx_only_promisc &&
2398                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2399                      (hw->aq.api_maj_ver > 1)))
2400                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2401         }
2402
2403         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2404
2405         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2406         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2407              (hw->aq.api_maj_ver > 1))
2408                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2409
2410         cmd->seid = CPU_TO_LE16(seid);
2411         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2412
2413         return status;
2414 }
2415
2416 /**
2417  * i40e_aq_set_vsi_multicast_promiscuous
2418  * @hw: pointer to the hw struct
2419  * @seid: vsi number
2420  * @set: set multicast promiscuous enable/disable
2421  * @cmd_details: pointer to command details structure or NULL
2422  **/
2423 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2424                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2425 {
2426         struct i40e_aq_desc desc;
2427         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2428                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2429         enum i40e_status_code status;
2430         u16 flags = 0;
2431
2432         i40e_fill_default_direct_cmd_desc(&desc,
2433                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2434
2435         if (set)
2436                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2437
2438         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2439
2440         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2441
2442         cmd->seid = CPU_TO_LE16(seid);
2443         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2444
2445         return status;
2446 }
2447
2448 /**
2449 * i40e_aq_set_vsi_full_promiscuous
2450 * @hw: pointer to the hw struct
2451 * @seid: VSI number
2452 * @set: set promiscuous enable/disable
2453 * @cmd_details: pointer to command details structure or NULL
2454 **/
2455 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2456                                 u16 seid, bool set,
2457                                 struct i40e_asq_cmd_details *cmd_details)
2458 {
2459         struct i40e_aq_desc desc;
2460         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2461                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2462         enum i40e_status_code status;
2463         u16 flags = 0;
2464
2465         i40e_fill_default_direct_cmd_desc(&desc,
2466                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2467
2468         if (set)
2469                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2470                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2471                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2472
2473         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2474
2475         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2476                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2477                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2478
2479         cmd->seid = CPU_TO_LE16(seid);
2480         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2481
2482         return status;
2483 }
2484
2485 /**
2486  * i40e_aq_set_vsi_mc_promisc_on_vlan
2487  * @hw: pointer to the hw struct
2488  * @seid: vsi number
2489  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2490  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2491  * @cmd_details: pointer to command details structure or NULL
2492  **/
2493 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2494                                 u16 seid, bool enable, u16 vid,
2495                                 struct i40e_asq_cmd_details *cmd_details)
2496 {
2497         struct i40e_aq_desc desc;
2498         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2499                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2500         enum i40e_status_code status;
2501         u16 flags = 0;
2502
2503         i40e_fill_default_direct_cmd_desc(&desc,
2504                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2505
2506         if (enable)
2507                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2508
2509         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2510         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2511         cmd->seid = CPU_TO_LE16(seid);
2512         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2513
2514         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2515
2516         return status;
2517 }
2518
2519 /**
2520  * i40e_aq_set_vsi_uc_promisc_on_vlan
2521  * @hw: pointer to the hw struct
2522  * @seid: vsi number
2523  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2524  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2525  * @cmd_details: pointer to command details structure or NULL
2526  **/
2527 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2528                                 u16 seid, bool enable, u16 vid,
2529                                 struct i40e_asq_cmd_details *cmd_details)
2530 {
2531         struct i40e_aq_desc desc;
2532         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2533                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2534         enum i40e_status_code status;
2535         u16 flags = 0;
2536
2537         i40e_fill_default_direct_cmd_desc(&desc,
2538                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2539
2540         if (enable)
2541                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2542
2543         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2544         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2545         cmd->seid = CPU_TO_LE16(seid);
2546         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2547
2548         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2549
2550         return status;
2551 }
2552
2553 /**
2554  * i40e_aq_set_vsi_bc_promisc_on_vlan
2555  * @hw: pointer to the hw struct
2556  * @seid: vsi number
2557  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2558  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2559  * @cmd_details: pointer to command details structure or NULL
2560  **/
2561 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2562                                 u16 seid, bool enable, u16 vid,
2563                                 struct i40e_asq_cmd_details *cmd_details)
2564 {
2565         struct i40e_aq_desc desc;
2566         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2567                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2568         enum i40e_status_code status;
2569         u16 flags = 0;
2570
2571         i40e_fill_default_direct_cmd_desc(&desc,
2572                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2573
2574         if (enable)
2575                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2576
2577         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2578         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2579         cmd->seid = CPU_TO_LE16(seid);
2580         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2581
2582         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2583
2584         return status;
2585 }
2586
2587 /**
2588  * i40e_aq_set_vsi_broadcast
2589  * @hw: pointer to the hw struct
2590  * @seid: vsi number
2591  * @set_filter: true to set filter, false to clear filter
2592  * @cmd_details: pointer to command details structure or NULL
2593  *
2594  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2595  **/
2596 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2597                                 u16 seid, bool set_filter,
2598                                 struct i40e_asq_cmd_details *cmd_details)
2599 {
2600         struct i40e_aq_desc desc;
2601         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2602                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2603         enum i40e_status_code status;
2604
2605         i40e_fill_default_direct_cmd_desc(&desc,
2606                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2607
2608         if (set_filter)
2609                 cmd->promiscuous_flags
2610                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2611         else
2612                 cmd->promiscuous_flags
2613                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2614
2615         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2616         cmd->seid = CPU_TO_LE16(seid);
2617         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2618
2619         return status;
2620 }
2621
2622 /**
2623  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2624  * @hw: pointer to the hw struct
2625  * @seid: vsi number
2626  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2627  * @cmd_details: pointer to command details structure or NULL
2628  **/
2629 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2630                                 u16 seid, bool enable,
2631                                 struct i40e_asq_cmd_details *cmd_details)
2632 {
2633         struct i40e_aq_desc desc;
2634         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2635                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2636         enum i40e_status_code status;
2637         u16 flags = 0;
2638
2639         i40e_fill_default_direct_cmd_desc(&desc,
2640                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2641         if (enable)
2642                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2643
2644         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2645         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2646         cmd->seid = CPU_TO_LE16(seid);
2647
2648         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2649
2650         return status;
2651 }
2652
2653 /**
2654  * i40e_get_vsi_params - get VSI configuration info
2655  * @hw: pointer to the hw struct
2656  * @vsi_ctx: pointer to a vsi context struct
2657  * @cmd_details: pointer to command details structure or NULL
2658  **/
2659 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2660                                 struct i40e_vsi_context *vsi_ctx,
2661                                 struct i40e_asq_cmd_details *cmd_details)
2662 {
2663         struct i40e_aq_desc desc;
2664         struct i40e_aqc_add_get_update_vsi *cmd =
2665                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2666         struct i40e_aqc_add_get_update_vsi_completion *resp =
2667                 (struct i40e_aqc_add_get_update_vsi_completion *)
2668                 &desc.params.raw;
2669         enum i40e_status_code status;
2670
2671         UNREFERENCED_1PARAMETER(cmd_details);
2672         i40e_fill_default_direct_cmd_desc(&desc,
2673                                           i40e_aqc_opc_get_vsi_parameters);
2674
2675         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2676
2677         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2678
2679         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2680                                     sizeof(vsi_ctx->info), NULL);
2681
2682         if (status != I40E_SUCCESS)
2683                 goto aq_get_vsi_params_exit;
2684
2685         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2686         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2687         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2688         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2689
2690 aq_get_vsi_params_exit:
2691         return status;
2692 }
2693
2694 /**
2695  * i40e_aq_update_vsi_params
2696  * @hw: pointer to the hw struct
2697  * @vsi_ctx: pointer to a vsi context struct
2698  * @cmd_details: pointer to command details structure or NULL
2699  *
2700  * Update a VSI context.
2701  **/
2702 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2703                                 struct i40e_vsi_context *vsi_ctx,
2704                                 struct i40e_asq_cmd_details *cmd_details)
2705 {
2706         struct i40e_aq_desc desc;
2707         struct i40e_aqc_add_get_update_vsi *cmd =
2708                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2709         struct i40e_aqc_add_get_update_vsi_completion *resp =
2710                 (struct i40e_aqc_add_get_update_vsi_completion *)
2711                 &desc.params.raw;
2712         enum i40e_status_code status;
2713
2714         i40e_fill_default_direct_cmd_desc(&desc,
2715                                           i40e_aqc_opc_update_vsi_parameters);
2716         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2717
2718         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2719
2720         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2721                                     sizeof(vsi_ctx->info), cmd_details);
2722
2723         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2724         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2725
2726         return status;
2727 }
2728
2729 /**
2730  * i40e_aq_get_switch_config
2731  * @hw: pointer to the hardware structure
2732  * @buf: pointer to the result buffer
2733  * @buf_size: length of input buffer
2734  * @start_seid: seid to start for the report, 0 == beginning
2735  * @cmd_details: pointer to command details structure or NULL
2736  *
2737  * Fill the buf with switch configuration returned from AdminQ command
2738  **/
2739 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2740                                 struct i40e_aqc_get_switch_config_resp *buf,
2741                                 u16 buf_size, u16 *start_seid,
2742                                 struct i40e_asq_cmd_details *cmd_details)
2743 {
2744         struct i40e_aq_desc desc;
2745         struct i40e_aqc_switch_seid *scfg =
2746                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2747         enum i40e_status_code status;
2748
2749         i40e_fill_default_direct_cmd_desc(&desc,
2750                                           i40e_aqc_opc_get_switch_config);
2751         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2752         if (buf_size > I40E_AQ_LARGE_BUF)
2753                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2754         scfg->seid = CPU_TO_LE16(*start_seid);
2755
2756         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2757         *start_seid = LE16_TO_CPU(scfg->seid);
2758
2759         return status;
2760 }
2761
2762 /**
2763  * i40e_aq_set_switch_config
2764  * @hw: pointer to the hardware structure
2765  * @flags: bit flag values to set
2766  * @mode: cloud filter mode
2767  * @valid_flags: which bit flags to set
2768  * @cmd_details: pointer to command details structure or NULL
2769  *
2770  * Set switch configuration bits
2771  **/
2772 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2773                                 u16 flags, u16 valid_flags, u8 mode,
2774                                 struct i40e_asq_cmd_details *cmd_details)
2775 {
2776         struct i40e_aq_desc desc;
2777         struct i40e_aqc_set_switch_config *scfg =
2778                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2779         enum i40e_status_code status;
2780
2781         i40e_fill_default_direct_cmd_desc(&desc,
2782                                           i40e_aqc_opc_set_switch_config);
2783         scfg->flags = CPU_TO_LE16(flags);
2784         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2785         scfg->mode = mode;
2786         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2787                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2788                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2789                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2790         }
2791         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2792
2793         return status;
2794 }
2795
2796 /**
2797  * i40e_aq_get_firmware_version
2798  * @hw: pointer to the hw struct
2799  * @fw_major_version: firmware major version
2800  * @fw_minor_version: firmware minor version
2801  * @fw_build: firmware build number
2802  * @api_major_version: major queue version
2803  * @api_minor_version: minor queue version
2804  * @cmd_details: pointer to command details structure or NULL
2805  *
2806  * Get the firmware version from the admin queue commands
2807  **/
2808 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2809                                 u16 *fw_major_version, u16 *fw_minor_version,
2810                                 u32 *fw_build,
2811                                 u16 *api_major_version, u16 *api_minor_version,
2812                                 struct i40e_asq_cmd_details *cmd_details)
2813 {
2814         struct i40e_aq_desc desc;
2815         struct i40e_aqc_get_version *resp =
2816                 (struct i40e_aqc_get_version *)&desc.params.raw;
2817         enum i40e_status_code status;
2818
2819         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2820
2821         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2822
2823         if (status == I40E_SUCCESS) {
2824                 if (fw_major_version != NULL)
2825                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2826                 if (fw_minor_version != NULL)
2827                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2828                 if (fw_build != NULL)
2829                         *fw_build = LE32_TO_CPU(resp->fw_build);
2830                 if (api_major_version != NULL)
2831                         *api_major_version = LE16_TO_CPU(resp->api_major);
2832                 if (api_minor_version != NULL)
2833                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2834
2835                 /* A workaround to fix the API version in SW */
2836                 if (api_major_version && api_minor_version &&
2837                     fw_major_version && fw_minor_version &&
2838                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2839                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2840                      (*fw_major_version > 4)))
2841                         *api_minor_version = 2;
2842         }
2843
2844         return status;
2845 }
2846
2847 /**
2848  * i40e_aq_send_driver_version
2849  * @hw: pointer to the hw struct
2850  * @dv: driver's major, minor version
2851  * @cmd_details: pointer to command details structure or NULL
2852  *
2853  * Send the driver version to the firmware
2854  **/
2855 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2856                                 struct i40e_driver_version *dv,
2857                                 struct i40e_asq_cmd_details *cmd_details)
2858 {
2859         struct i40e_aq_desc desc;
2860         struct i40e_aqc_driver_version *cmd =
2861                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2862         enum i40e_status_code status;
2863         u16 len;
2864
2865         if (dv == NULL)
2866                 return I40E_ERR_PARAM;
2867
2868         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2869
2870         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2871         cmd->driver_major_ver = dv->major_version;
2872         cmd->driver_minor_ver = dv->minor_version;
2873         cmd->driver_build_ver = dv->build_version;
2874         cmd->driver_subbuild_ver = dv->subbuild_version;
2875
2876         len = 0;
2877         while (len < sizeof(dv->driver_string) &&
2878                (dv->driver_string[len] < 0x80) &&
2879                dv->driver_string[len])
2880                 len++;
2881         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2882                                        len, cmd_details);
2883
2884         return status;
2885 }
2886
2887 /**
2888  * i40e_get_link_status - get status of the HW network link
2889  * @hw: pointer to the hw struct
2890  * @link_up: pointer to bool (true/false = linkup/linkdown)
2891  *
2892  * Variable link_up true if link is up, false if link is down.
2893  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2894  *
2895  * Side effect: LinkStatusEvent reporting becomes enabled
2896  **/
2897 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2898 {
2899         enum i40e_status_code status = I40E_SUCCESS;
2900
2901         if (hw->phy.get_link_info) {
2902                 status = i40e_update_link_info(hw);
2903
2904                 if (status != I40E_SUCCESS)
2905                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2906                                    status);
2907         }
2908
2909         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2910
2911         return status;
2912 }
2913
2914 /**
2915  * i40e_updatelink_status - update status of the HW network link
2916  * @hw: pointer to the hw struct
2917  **/
2918 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2919 {
2920         struct i40e_aq_get_phy_abilities_resp abilities;
2921         enum i40e_status_code status = I40E_SUCCESS;
2922
2923         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2924         if (status)
2925                 return status;
2926
2927         /* extra checking needed to ensure link info to user is timely */
2928         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2929             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2930              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2931                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2932                                                       &abilities, NULL);
2933                 if (status)
2934                         return status;
2935
2936                 if (abilities.fec_cfg_curr_mod_ext_info &
2937                     I40E_AQ_ENABLE_FEC_AUTO)
2938                         hw->phy.link_info.req_fec_info =
2939                                 (I40E_AQ_REQUEST_FEC_KR |
2940                                  I40E_AQ_REQUEST_FEC_RS);
2941                 else
2942                         hw->phy.link_info.req_fec_info =
2943                                 abilities.fec_cfg_curr_mod_ext_info &
2944                                 (I40E_AQ_REQUEST_FEC_KR |
2945                                  I40E_AQ_REQUEST_FEC_RS);
2946
2947                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2948                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2949         }
2950         return status;
2951 }
2952
2953
2954 /**
2955  * i40e_get_link_speed
2956  * @hw: pointer to the hw struct
2957  *
2958  * Returns the link speed of the adapter.
2959  **/
2960 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2961 {
2962         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2963         enum i40e_status_code status = I40E_SUCCESS;
2964
2965         if (hw->phy.get_link_info) {
2966                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2967
2968                 if (status != I40E_SUCCESS)
2969                         goto i40e_link_speed_exit;
2970         }
2971
2972         speed = hw->phy.link_info.link_speed;
2973
2974 i40e_link_speed_exit:
2975         return speed;
2976 }
2977
2978 /**
2979  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2980  * @hw: pointer to the hw struct
2981  * @uplink_seid: the MAC or other gizmo SEID
2982  * @downlink_seid: the VSI SEID
2983  * @enabled_tc: bitmap of TCs to be enabled
2984  * @default_port: true for default port VSI, false for control port
2985  * @veb_seid: pointer to where to put the resulting VEB SEID
2986  * @enable_stats: true to turn on VEB stats
2987  * @cmd_details: pointer to command details structure or NULL
2988  *
2989  * This asks the FW to add a VEB between the uplink and downlink
2990  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2991  **/
2992 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2993                                 u16 downlink_seid, u8 enabled_tc,
2994                                 bool default_port, u16 *veb_seid,
2995                                 bool enable_stats,
2996                                 struct i40e_asq_cmd_details *cmd_details)
2997 {
2998         struct i40e_aq_desc desc;
2999         struct i40e_aqc_add_veb *cmd =
3000                 (struct i40e_aqc_add_veb *)&desc.params.raw;
3001         struct i40e_aqc_add_veb_completion *resp =
3002                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
3003         enum i40e_status_code status;
3004         u16 veb_flags = 0;
3005
3006         /* SEIDs need to either both be set or both be 0 for floating VEB */
3007         if (!!uplink_seid != !!downlink_seid)
3008                 return I40E_ERR_PARAM;
3009
3010         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
3011
3012         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
3013         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
3014         cmd->enable_tcs = enabled_tc;
3015         if (!uplink_seid)
3016                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
3017         if (default_port)
3018                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
3019         else
3020                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
3021
3022         /* reverse logic here: set the bitflag to disable the stats */
3023         if (!enable_stats)
3024                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
3025
3026         cmd->veb_flags = CPU_TO_LE16(veb_flags);
3027
3028         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3029
3030         if (!status && veb_seid)
3031                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
3032
3033         return status;
3034 }
3035
3036 /**
3037  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
3038  * @hw: pointer to the hw struct
3039  * @veb_seid: the SEID of the VEB to query
3040  * @switch_id: the uplink switch id
3041  * @floating: set to true if the VEB is floating
3042  * @statistic_index: index of the stats counter block for this VEB
3043  * @vebs_used: number of VEB's used by function
3044  * @vebs_free: total VEB's not reserved by any function
3045  * @cmd_details: pointer to command details structure or NULL
3046  *
3047  * This retrieves the parameters for a particular VEB, specified by
3048  * uplink_seid, and returns them to the caller.
3049  **/
3050 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3051                                 u16 veb_seid, u16 *switch_id,
3052                                 bool *floating, u16 *statistic_index,
3053                                 u16 *vebs_used, u16 *vebs_free,
3054                                 struct i40e_asq_cmd_details *cmd_details)
3055 {
3056         struct i40e_aq_desc desc;
3057         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3058                 (struct i40e_aqc_get_veb_parameters_completion *)
3059                 &desc.params.raw;
3060         enum i40e_status_code status;
3061
3062         if (veb_seid == 0)
3063                 return I40E_ERR_PARAM;
3064
3065         i40e_fill_default_direct_cmd_desc(&desc,
3066                                           i40e_aqc_opc_get_veb_parameters);
3067         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3068
3069         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3070         if (status)
3071                 goto get_veb_exit;
3072
3073         if (switch_id)
3074                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3075         if (statistic_index)
3076                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3077         if (vebs_used)
3078                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3079         if (vebs_free)
3080                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3081         if (floating) {
3082                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3083
3084                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3085                         *floating = true;
3086                 else
3087                         *floating = false;
3088         }
3089
3090 get_veb_exit:
3091         return status;
3092 }
3093
3094 /**
3095  * i40e_aq_add_macvlan
3096  * @hw: pointer to the hw struct
3097  * @seid: VSI for the mac address
3098  * @mv_list: list of macvlans to be added
3099  * @count: length of the list
3100  * @cmd_details: pointer to command details structure or NULL
3101  *
3102  * Add MAC/VLAN addresses to the HW filtering
3103  **/
3104 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3105                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3106                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3107 {
3108         struct i40e_aq_desc desc;
3109         struct i40e_aqc_macvlan *cmd =
3110                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3111         enum i40e_status_code status;
3112         u16 buf_size;
3113         int i;
3114
3115         if (count == 0 || !mv_list || !hw)
3116                 return I40E_ERR_PARAM;
3117
3118         buf_size = count * sizeof(*mv_list);
3119
3120         /* prep the rest of the request */
3121         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3122         cmd->num_addresses = CPU_TO_LE16(count);
3123         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3124         cmd->seid[1] = 0;
3125         cmd->seid[2] = 0;
3126
3127         for (i = 0; i < count; i++)
3128                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3129                         mv_list[i].flags |=
3130                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3131
3132         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3133         if (buf_size > I40E_AQ_LARGE_BUF)
3134                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3135
3136         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3137                                        cmd_details);
3138
3139         return status;
3140 }
3141
3142 /**
3143  * i40e_aq_remove_macvlan
3144  * @hw: pointer to the hw struct
3145  * @seid: VSI for the mac address
3146  * @mv_list: list of macvlans to be removed
3147  * @count: length of the list
3148  * @cmd_details: pointer to command details structure or NULL
3149  *
3150  * Remove MAC/VLAN addresses from the HW filtering
3151  **/
3152 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3153                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3154                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3155 {
3156         struct i40e_aq_desc desc;
3157         struct i40e_aqc_macvlan *cmd =
3158                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3159         enum i40e_status_code status;
3160         u16 buf_size;
3161
3162         if (count == 0 || !mv_list || !hw)
3163                 return I40E_ERR_PARAM;
3164
3165         buf_size = count * sizeof(*mv_list);
3166
3167         /* prep the rest of the request */
3168         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3169         cmd->num_addresses = CPU_TO_LE16(count);
3170         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3171         cmd->seid[1] = 0;
3172         cmd->seid[2] = 0;
3173
3174         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3175         if (buf_size > I40E_AQ_LARGE_BUF)
3176                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3177
3178         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3179                                        cmd_details);
3180
3181         return status;
3182 }
3183
3184 /**
3185  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3186  * @hw: pointer to the hw struct
3187  * @opcode: AQ opcode for add or delete mirror rule
3188  * @sw_seid: Switch SEID (to which rule refers)
3189  * @rule_type: Rule Type (ingress/egress/VLAN)
3190  * @id: Destination VSI SEID or Rule ID
3191  * @count: length of the list
3192  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3193  * @cmd_details: pointer to command details structure or NULL
3194  * @rule_id: Rule ID returned from FW
3195  * @rules_used: Number of rules used in internal switch
3196  * @rules_free: Number of rules free in internal switch
3197  *
3198  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3199  * VEBs/VEPA elements only
3200  **/
3201 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3202                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3203                         u16 count, __le16 *mr_list,
3204                         struct i40e_asq_cmd_details *cmd_details,
3205                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3206 {
3207         struct i40e_aq_desc desc;
3208         struct i40e_aqc_add_delete_mirror_rule *cmd =
3209                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3210         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3211         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3212         enum i40e_status_code status;
3213         u16 buf_size;
3214
3215         buf_size = count * sizeof(*mr_list);
3216
3217         /* prep the rest of the request */
3218         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3219         cmd->seid = CPU_TO_LE16(sw_seid);
3220         cmd->rule_type = CPU_TO_LE16(rule_type &
3221                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3222         cmd->num_entries = CPU_TO_LE16(count);
3223         /* Dest VSI for add, rule_id for delete */
3224         cmd->destination = CPU_TO_LE16(id);
3225         if (mr_list) {
3226                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3227                                                 I40E_AQ_FLAG_RD));
3228                 if (buf_size > I40E_AQ_LARGE_BUF)
3229                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3230         }
3231
3232         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3233                                        cmd_details);
3234         if (status == I40E_SUCCESS ||
3235             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3236                 if (rule_id)
3237                         *rule_id = LE16_TO_CPU(resp->rule_id);
3238                 if (rules_used)
3239                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3240                 if (rules_free)
3241                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3242         }
3243         return status;
3244 }
3245
3246 /**
3247  * i40e_aq_add_mirrorrule - add a mirror rule
3248  * @hw: pointer to the hw struct
3249  * @sw_seid: Switch SEID (to which rule refers)
3250  * @rule_type: Rule Type (ingress/egress/VLAN)
3251  * @dest_vsi: SEID of VSI to which packets will be mirrored
3252  * @count: length of the list
3253  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3254  * @cmd_details: pointer to command details structure or NULL
3255  * @rule_id: Rule ID returned from FW
3256  * @rules_used: Number of rules used in internal switch
3257  * @rules_free: Number of rules free in internal switch
3258  *
3259  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3260  **/
3261 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3262                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3263                         struct i40e_asq_cmd_details *cmd_details,
3264                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3265 {
3266         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3267             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3268                 if (count == 0 || !mr_list)
3269                         return I40E_ERR_PARAM;
3270         }
3271
3272         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3273                                   rule_type, dest_vsi, count, mr_list,
3274                                   cmd_details, rule_id, rules_used, rules_free);
3275 }
3276
3277 /**
3278  * i40e_aq_delete_mirrorrule - delete a mirror rule
3279  * @hw: pointer to the hw struct
3280  * @sw_seid: Switch SEID (to which rule refers)
3281  * @rule_type: Rule Type (ingress/egress/VLAN)
3282  * @count: length of the list
3283  * @rule_id: Rule ID that is returned in the receive desc as part of
3284  *              add_mirrorrule.
3285  * @mr_list: list of mirrored VLAN IDs to be removed
3286  * @cmd_details: pointer to command details structure or NULL
3287  * @rules_used: Number of rules used in internal switch
3288  * @rules_free: Number of rules free in internal switch
3289  *
3290  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3291  **/
3292 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3293                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3294                         struct i40e_asq_cmd_details *cmd_details,
3295                         u16 *rules_used, u16 *rules_free)
3296 {
3297         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3298         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3299                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3300                  * mirroring. For other rule_type, count and rule_type should
3301                  * not matter.
3302                  */
3303                 if (count == 0 || !mr_list)
3304                         return I40E_ERR_PARAM;
3305         }
3306
3307         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3308                                   rule_type, rule_id, count, mr_list,
3309                                   cmd_details, NULL, rules_used, rules_free);
3310 }
3311
3312 /**
3313  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3314  * @hw: pointer to the hw struct
3315  * @seid: VSI for the vlan filters
3316  * @v_list: list of vlan filters to be added
3317  * @count: length of the list
3318  * @cmd_details: pointer to command details structure or NULL
3319  **/
3320 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3321                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3322                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3323 {
3324         struct i40e_aq_desc desc;
3325         struct i40e_aqc_macvlan *cmd =
3326                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3327         enum i40e_status_code status;
3328         u16 buf_size;
3329
3330         if (count == 0 || !v_list || !hw)
3331                 return I40E_ERR_PARAM;
3332
3333         buf_size = count * sizeof(*v_list);
3334
3335         /* prep the rest of the request */
3336         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3337         cmd->num_addresses = CPU_TO_LE16(count);
3338         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3339         cmd->seid[1] = 0;
3340         cmd->seid[2] = 0;
3341
3342         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3343         if (buf_size > I40E_AQ_LARGE_BUF)
3344                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3345
3346         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3347                                        cmd_details);
3348
3349         return status;
3350 }
3351
3352 /**
3353  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3354  * @hw: pointer to the hw struct
3355  * @seid: VSI for the vlan filters
3356  * @v_list: list of macvlans to be removed
3357  * @count: length of the list
3358  * @cmd_details: pointer to command details structure or NULL
3359  **/
3360 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3361                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3362                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3363 {
3364         struct i40e_aq_desc desc;
3365         struct i40e_aqc_macvlan *cmd =
3366                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3367         enum i40e_status_code status;
3368         u16 buf_size;
3369
3370         if (count == 0 || !v_list || !hw)
3371                 return I40E_ERR_PARAM;
3372
3373         buf_size = count * sizeof(*v_list);
3374
3375         /* prep the rest of the request */
3376         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3377         cmd->num_addresses = CPU_TO_LE16(count);
3378         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3379         cmd->seid[1] = 0;
3380         cmd->seid[2] = 0;
3381
3382         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3383         if (buf_size > I40E_AQ_LARGE_BUF)
3384                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3385
3386         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3387                                        cmd_details);
3388
3389         return status;
3390 }
3391
3392 /**
3393  * i40e_aq_send_msg_to_vf
3394  * @hw: pointer to the hardware structure
3395  * @vfid: vf id to send msg
3396  * @v_opcode: opcodes for VF-PF communication
3397  * @v_retval: return error code
3398  * @msg: pointer to the msg buffer
3399  * @msglen: msg length
3400  * @cmd_details: pointer to command details
3401  *
3402  * send msg to vf
3403  **/
3404 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3405                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3406                                 struct i40e_asq_cmd_details *cmd_details)
3407 {
3408         struct i40e_aq_desc desc;
3409         struct i40e_aqc_pf_vf_message *cmd =
3410                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3411         enum i40e_status_code status;
3412
3413         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3414         cmd->id = CPU_TO_LE32(vfid);
3415         desc.cookie_high = CPU_TO_LE32(v_opcode);
3416         desc.cookie_low = CPU_TO_LE32(v_retval);
3417         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3418         if (msglen) {
3419                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3420                                                 I40E_AQ_FLAG_RD));
3421                 if (msglen > I40E_AQ_LARGE_BUF)
3422                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3423                 desc.datalen = CPU_TO_LE16(msglen);
3424         }
3425         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3426
3427         return status;
3428 }
3429
3430 /**
3431  * i40e_aq_debug_read_register
3432  * @hw: pointer to the hw struct
3433  * @reg_addr: register address
3434  * @reg_val: register value
3435  * @cmd_details: pointer to command details structure or NULL
3436  *
3437  * Read the register using the admin queue commands
3438  **/
3439 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3440                                 u32 reg_addr, u64 *reg_val,
3441                                 struct i40e_asq_cmd_details *cmd_details)
3442 {
3443         struct i40e_aq_desc desc;
3444         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3445                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3446         enum i40e_status_code status;
3447
3448         if (reg_val == NULL)
3449                 return I40E_ERR_PARAM;
3450
3451         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3452
3453         cmd_resp->address = CPU_TO_LE32(reg_addr);
3454
3455         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3456
3457         if (status == I40E_SUCCESS) {
3458                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3459                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3460         }
3461
3462         return status;
3463 }
3464
3465 /**
3466  * i40e_aq_debug_write_register
3467  * @hw: pointer to the hw struct
3468  * @reg_addr: register address
3469  * @reg_val: register value
3470  * @cmd_details: pointer to command details structure or NULL
3471  *
3472  * Write to a register using the admin queue commands
3473  **/
3474 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3475                                 u32 reg_addr, u64 reg_val,
3476                                 struct i40e_asq_cmd_details *cmd_details)
3477 {
3478         struct i40e_aq_desc desc;
3479         struct i40e_aqc_debug_reg_read_write *cmd =
3480                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3481         enum i40e_status_code status;
3482
3483         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3484
3485         cmd->address = CPU_TO_LE32(reg_addr);
3486         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3487         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3488
3489         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3490
3491         return status;
3492 }
3493
3494 /**
3495  * i40e_aq_request_resource
3496  * @hw: pointer to the hw struct
3497  * @resource: resource id
3498  * @access: access type
3499  * @sdp_number: resource number
3500  * @timeout: the maximum time in ms that the driver may hold the resource
3501  * @cmd_details: pointer to command details structure or NULL
3502  *
3503  * requests common resource using the admin queue commands
3504  **/
3505 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3506                                 enum i40e_aq_resources_ids resource,
3507                                 enum i40e_aq_resource_access_type access,
3508                                 u8 sdp_number, u64 *timeout,
3509                                 struct i40e_asq_cmd_details *cmd_details)
3510 {
3511         struct i40e_aq_desc desc;
3512         struct i40e_aqc_request_resource *cmd_resp =
3513                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3514         enum i40e_status_code status;
3515
3516         DEBUGFUNC("i40e_aq_request_resource");
3517
3518         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3519
3520         cmd_resp->resource_id = CPU_TO_LE16(resource);
3521         cmd_resp->access_type = CPU_TO_LE16(access);
3522         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3523
3524         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3525         /* The completion specifies the maximum time in ms that the driver
3526          * may hold the resource in the Timeout field.
3527          * If the resource is held by someone else, the command completes with
3528          * busy return value and the timeout field indicates the maximum time
3529          * the current owner of the resource has to free it.
3530          */
3531         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3532                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3533
3534         return status;
3535 }
3536
3537 /**
3538  * i40e_aq_release_resource
3539  * @hw: pointer to the hw struct
3540  * @resource: resource id
3541  * @sdp_number: resource number
3542  * @cmd_details: pointer to command details structure or NULL
3543  *
3544  * release common resource using the admin queue commands
3545  **/
3546 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3547                                 enum i40e_aq_resources_ids resource,
3548                                 u8 sdp_number,
3549                                 struct i40e_asq_cmd_details *cmd_details)
3550 {
3551         struct i40e_aq_desc desc;
3552         struct i40e_aqc_request_resource *cmd =
3553                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3554         enum i40e_status_code status;
3555
3556         DEBUGFUNC("i40e_aq_release_resource");
3557
3558         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3559
3560         cmd->resource_id = CPU_TO_LE16(resource);
3561         cmd->resource_number = CPU_TO_LE32(sdp_number);
3562
3563         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3564
3565         return status;
3566 }
3567
3568 /**
3569  * i40e_aq_read_nvm
3570  * @hw: pointer to the hw struct
3571  * @module_pointer: module pointer location in words from the NVM beginning
3572  * @offset: byte offset from the module beginning
3573  * @length: length of the section to be read (in bytes from the offset)
3574  * @data: command buffer (size [bytes] = length)
3575  * @last_command: tells if this is the last command in a series
3576  * @cmd_details: pointer to command details structure or NULL
3577  *
3578  * Read the NVM using the admin queue commands
3579  **/
3580 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3581                                 u32 offset, u16 length, void *data,
3582                                 bool last_command,
3583                                 struct i40e_asq_cmd_details *cmd_details)
3584 {
3585         struct i40e_aq_desc desc;
3586         struct i40e_aqc_nvm_update *cmd =
3587                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3588         enum i40e_status_code status;
3589
3590         DEBUGFUNC("i40e_aq_read_nvm");
3591
3592         /* In offset the highest byte must be zeroed. */
3593         if (offset & 0xFF000000) {
3594                 status = I40E_ERR_PARAM;
3595                 goto i40e_aq_read_nvm_exit;
3596         }
3597
3598         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3599
3600         /* If this is the last command in a series, set the proper flag. */
3601         if (last_command)
3602                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3603         cmd->module_pointer = module_pointer;
3604         cmd->offset = CPU_TO_LE32(offset);
3605         cmd->length = CPU_TO_LE16(length);
3606
3607         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3608         if (length > I40E_AQ_LARGE_BUF)
3609                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3610
3611         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3612
3613 i40e_aq_read_nvm_exit:
3614         return status;
3615 }
3616
3617 /**
3618  * i40e_aq_read_nvm_config - read an nvm config block
3619  * @hw: pointer to the hw struct
3620  * @cmd_flags: NVM access admin command bits
3621  * @field_id: field or feature id
3622  * @data: buffer for result
3623  * @buf_size: buffer size
3624  * @element_count: pointer to count of elements read by FW
3625  * @cmd_details: pointer to command details structure or NULL
3626  **/
3627 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3628                                 u8 cmd_flags, u32 field_id, void *data,
3629                                 u16 buf_size, u16 *element_count,
3630                                 struct i40e_asq_cmd_details *cmd_details)
3631 {
3632         struct i40e_aq_desc desc;
3633         struct i40e_aqc_nvm_config_read *cmd =
3634                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3635         enum i40e_status_code status;
3636
3637         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3638         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3639         if (buf_size > I40E_AQ_LARGE_BUF)
3640                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3641
3642         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3643         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3644         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3645                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3646         else
3647                 cmd->element_id_msw = 0;
3648
3649         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3650
3651         if (!status && element_count)
3652                 *element_count = LE16_TO_CPU(cmd->element_count);
3653
3654         return status;
3655 }
3656
3657 /**
3658  * i40e_aq_write_nvm_config - write an nvm config block
3659  * @hw: pointer to the hw struct
3660  * @cmd_flags: NVM access admin command bits
3661  * @data: buffer for result
3662  * @buf_size: buffer size
3663  * @element_count: count of elements to be written
3664  * @cmd_details: pointer to command details structure or NULL
3665  **/
3666 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3667                                 u8 cmd_flags, void *data, u16 buf_size,
3668                                 u16 element_count,
3669                                 struct i40e_asq_cmd_details *cmd_details)
3670 {
3671         struct i40e_aq_desc desc;
3672         struct i40e_aqc_nvm_config_write *cmd =
3673                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3674         enum i40e_status_code status;
3675
3676         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3677         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3678         if (buf_size > I40E_AQ_LARGE_BUF)
3679                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3680
3681         cmd->element_count = CPU_TO_LE16(element_count);
3682         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3683         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3684
3685         return status;
3686 }
3687
3688 /**
3689  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3690  * @hw: pointer to the hw struct
3691  * @buff: buffer for result
3692  * @buff_size: buffer size
3693  * @cmd_details: pointer to command details structure or NULL
3694  **/
3695 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3696                                 void *buff, u16 buff_size,
3697                                 struct i40e_asq_cmd_details *cmd_details)
3698 {
3699         struct i40e_aq_desc desc;
3700         enum i40e_status_code status;
3701
3702         UNREFERENCED_2PARAMETER(buff, buff_size);
3703
3704         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3705         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3706         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3707                 status = I40E_ERR_NOT_IMPLEMENTED;
3708
3709         return status;
3710 }
3711
3712 /**
3713  * i40e_aq_erase_nvm
3714  * @hw: pointer to the hw struct
3715  * @module_pointer: module pointer location in words from the NVM beginning
3716  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3717  * @length: length of the section to be erased (expressed in 4 KB)
3718  * @last_command: tells if this is the last command in a series
3719  * @cmd_details: pointer to command details structure or NULL
3720  *
3721  * Erase the NVM sector using the admin queue commands
3722  **/
3723 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3724                                 u32 offset, u16 length, bool last_command,
3725                                 struct i40e_asq_cmd_details *cmd_details)
3726 {
3727         struct i40e_aq_desc desc;
3728         struct i40e_aqc_nvm_update *cmd =
3729                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3730         enum i40e_status_code status;
3731
3732         DEBUGFUNC("i40e_aq_erase_nvm");
3733
3734         /* In offset the highest byte must be zeroed. */
3735         if (offset & 0xFF000000) {
3736                 status = I40E_ERR_PARAM;
3737                 goto i40e_aq_erase_nvm_exit;
3738         }
3739
3740         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3741
3742         /* If this is the last command in a series, set the proper flag. */
3743         if (last_command)
3744                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3745         cmd->module_pointer = module_pointer;
3746         cmd->offset = CPU_TO_LE32(offset);
3747         cmd->length = CPU_TO_LE16(length);
3748
3749         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3750
3751 i40e_aq_erase_nvm_exit:
3752         return status;
3753 }
3754
3755 /**
3756  * i40e_parse_discover_capabilities
3757  * @hw: pointer to the hw struct
3758  * @buff: pointer to a buffer containing device/function capability records
3759  * @cap_count: number of capability records in the list
3760  * @list_type_opc: type of capabilities list to parse
3761  *
3762  * Parse the device/function capabilities list.
3763  **/
3764 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3765                                      u32 cap_count,
3766                                      enum i40e_admin_queue_opc list_type_opc)
3767 {
3768         struct i40e_aqc_list_capabilities_element_resp *cap;
3769         u32 valid_functions, num_functions;
3770         u32 number, logical_id, phys_id;
3771         struct i40e_hw_capabilities *p;
3772         enum i40e_status_code status;
3773         u16 id, ocp_cfg_word0;
3774         u8 major_rev;
3775         u32 i = 0;
3776
3777         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3778
3779         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3780                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3781         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3782                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3783         else
3784                 return;
3785
3786         for (i = 0; i < cap_count; i++, cap++) {
3787                 id = LE16_TO_CPU(cap->id);
3788                 number = LE32_TO_CPU(cap->number);
3789                 logical_id = LE32_TO_CPU(cap->logical_id);
3790                 phys_id = LE32_TO_CPU(cap->phys_id);
3791                 major_rev = cap->major_rev;
3792
3793                 switch (id) {
3794                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3795                         p->switch_mode = number;
3796                         i40e_debug(hw, I40E_DEBUG_INIT,
3797                                    "HW Capability: Switch mode = %d\n",
3798                                    p->switch_mode);
3799                         break;
3800                 case I40E_AQ_CAP_ID_MNG_MODE:
3801                         p->management_mode = number;
3802                         if (major_rev > 1) {
3803                                 p->mng_protocols_over_mctp = logical_id;
3804                                 i40e_debug(hw, I40E_DEBUG_INIT,
3805                                            "HW Capability: Protocols over MCTP = %d\n",
3806                                            p->mng_protocols_over_mctp);
3807                         } else {
3808                                 p->mng_protocols_over_mctp = 0;
3809                         }
3810                         i40e_debug(hw, I40E_DEBUG_INIT,
3811                                    "HW Capability: Management Mode = %d\n",
3812                                    p->management_mode);
3813                         break;
3814                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3815                         p->npar_enable = number;
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: NPAR enable = %d\n",
3818                                    p->npar_enable);
3819                         break;
3820                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3821                         p->os2bmc = number;
3822                         i40e_debug(hw, I40E_DEBUG_INIT,
3823                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3824                         break;
3825                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3826                         p->valid_functions = number;
3827                         i40e_debug(hw, I40E_DEBUG_INIT,
3828                                    "HW Capability: Valid Functions = %d\n",
3829                                    p->valid_functions);
3830                         break;
3831                 case I40E_AQ_CAP_ID_SRIOV:
3832                         if (number == 1)
3833                                 p->sr_iov_1_1 = true;
3834                         i40e_debug(hw, I40E_DEBUG_INIT,
3835                                    "HW Capability: SR-IOV = %d\n",
3836                                    p->sr_iov_1_1);
3837                         break;
3838                 case I40E_AQ_CAP_ID_VF:
3839                         p->num_vfs = number;
3840                         p->vf_base_id = logical_id;
3841                         i40e_debug(hw, I40E_DEBUG_INIT,
3842                                    "HW Capability: VF count = %d\n",
3843                                    p->num_vfs);
3844                         i40e_debug(hw, I40E_DEBUG_INIT,
3845                                    "HW Capability: VF base_id = %d\n",
3846                                    p->vf_base_id);
3847                         break;
3848                 case I40E_AQ_CAP_ID_VMDQ:
3849                         if (number == 1)
3850                                 p->vmdq = true;
3851                         i40e_debug(hw, I40E_DEBUG_INIT,
3852                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3853                         break;
3854                 case I40E_AQ_CAP_ID_8021QBG:
3855                         if (number == 1)
3856                                 p->evb_802_1_qbg = true;
3857                         i40e_debug(hw, I40E_DEBUG_INIT,
3858                                    "HW Capability: 802.1Qbg = %d\n", number);
3859                         break;
3860                 case I40E_AQ_CAP_ID_8021QBR:
3861                         if (number == 1)
3862                                 p->evb_802_1_qbh = true;
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: 802.1Qbh = %d\n", number);
3865                         break;
3866                 case I40E_AQ_CAP_ID_VSI:
3867                         p->num_vsis = number;
3868                         i40e_debug(hw, I40E_DEBUG_INIT,
3869                                    "HW Capability: VSI count = %d\n",
3870                                    p->num_vsis);
3871                         break;
3872                 case I40E_AQ_CAP_ID_DCB:
3873                         if (number == 1) {
3874                                 p->dcb = true;
3875                                 p->enabled_tcmap = logical_id;
3876                                 p->maxtc = phys_id;
3877                         }
3878                         i40e_debug(hw, I40E_DEBUG_INIT,
3879                                    "HW Capability: DCB = %d\n", p->dcb);
3880                         i40e_debug(hw, I40E_DEBUG_INIT,
3881                                    "HW Capability: TC Mapping = %d\n",
3882                                    logical_id);
3883                         i40e_debug(hw, I40E_DEBUG_INIT,
3884                                    "HW Capability: TC Max = %d\n", p->maxtc);
3885                         break;
3886                 case I40E_AQ_CAP_ID_FCOE:
3887                         if (number == 1)
3888                                 p->fcoe = true;
3889                         i40e_debug(hw, I40E_DEBUG_INIT,
3890                                    "HW Capability: FCOE = %d\n", p->fcoe);
3891                         break;
3892                 case I40E_AQ_CAP_ID_ISCSI:
3893                         if (number == 1)
3894                                 p->iscsi = true;
3895                         i40e_debug(hw, I40E_DEBUG_INIT,
3896                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3897                         break;
3898                 case I40E_AQ_CAP_ID_RSS:
3899                         p->rss = true;
3900                         p->rss_table_size = number;
3901                         p->rss_table_entry_width = logical_id;
3902                         i40e_debug(hw, I40E_DEBUG_INIT,
3903                                    "HW Capability: RSS = %d\n", p->rss);
3904                         i40e_debug(hw, I40E_DEBUG_INIT,
3905                                    "HW Capability: RSS table size = %d\n",
3906                                    p->rss_table_size);
3907                         i40e_debug(hw, I40E_DEBUG_INIT,
3908                                    "HW Capability: RSS table width = %d\n",
3909                                    p->rss_table_entry_width);
3910                         break;
3911                 case I40E_AQ_CAP_ID_RXQ:
3912                         p->num_rx_qp = number;
3913                         p->base_queue = phys_id;
3914                         i40e_debug(hw, I40E_DEBUG_INIT,
3915                                    "HW Capability: Rx QP = %d\n", number);
3916                         i40e_debug(hw, I40E_DEBUG_INIT,
3917                                    "HW Capability: base_queue = %d\n",
3918                                    p->base_queue);
3919                         break;
3920                 case I40E_AQ_CAP_ID_TXQ:
3921                         p->num_tx_qp = number;
3922                         p->base_queue = phys_id;
3923                         i40e_debug(hw, I40E_DEBUG_INIT,
3924                                    "HW Capability: Tx QP = %d\n", number);
3925                         i40e_debug(hw, I40E_DEBUG_INIT,
3926                                    "HW Capability: base_queue = %d\n",
3927                                    p->base_queue);
3928                         break;
3929                 case I40E_AQ_CAP_ID_MSIX:
3930                         p->num_msix_vectors = number;
3931                         i40e_debug(hw, I40E_DEBUG_INIT,
3932                                    "HW Capability: MSIX vector count = %d\n",
3933                                    p->num_msix_vectors);
3934                         break;
3935                 case I40E_AQ_CAP_ID_VF_MSIX:
3936                         p->num_msix_vectors_vf = number;
3937                         i40e_debug(hw, I40E_DEBUG_INIT,
3938                                    "HW Capability: MSIX VF vector count = %d\n",
3939                                    p->num_msix_vectors_vf);
3940                         break;
3941                 case I40E_AQ_CAP_ID_FLEX10:
3942                         if (major_rev == 1) {
3943                                 if (number == 1) {
3944                                         p->flex10_enable = true;
3945                                         p->flex10_capable = true;
3946                                 }
3947                         } else {
3948                                 /* Capability revision >= 2 */
3949                                 if (number & 1)
3950                                         p->flex10_enable = true;
3951                                 if (number & 2)
3952                                         p->flex10_capable = true;
3953                         }
3954                         p->flex10_mode = logical_id;
3955                         p->flex10_status = phys_id;
3956                         i40e_debug(hw, I40E_DEBUG_INIT,
3957                                    "HW Capability: Flex10 mode = %d\n",
3958                                    p->flex10_mode);
3959                         i40e_debug(hw, I40E_DEBUG_INIT,
3960                                    "HW Capability: Flex10 status = %d\n",
3961                                    p->flex10_status);
3962                         break;
3963                 case I40E_AQ_CAP_ID_CEM:
3964                         if (number == 1)
3965                                 p->mgmt_cem = true;
3966                         i40e_debug(hw, I40E_DEBUG_INIT,
3967                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3968                         break;
3969                 case I40E_AQ_CAP_ID_IWARP:
3970                         if (number == 1)
3971                                 p->iwarp = true;
3972                         i40e_debug(hw, I40E_DEBUG_INIT,
3973                                    "HW Capability: iWARP = %d\n", p->iwarp);
3974                         break;
3975                 case I40E_AQ_CAP_ID_LED:
3976                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3977                                 p->led[phys_id] = true;
3978                         i40e_debug(hw, I40E_DEBUG_INIT,
3979                                    "HW Capability: LED - PIN %d\n", phys_id);
3980                         break;
3981                 case I40E_AQ_CAP_ID_SDP:
3982                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3983                                 p->sdp[phys_id] = true;
3984                         i40e_debug(hw, I40E_DEBUG_INIT,
3985                                    "HW Capability: SDP - PIN %d\n", phys_id);
3986                         break;
3987                 case I40E_AQ_CAP_ID_MDIO:
3988                         if (number == 1) {
3989                                 p->mdio_port_num = phys_id;
3990                                 p->mdio_port_mode = logical_id;
3991                         }
3992                         i40e_debug(hw, I40E_DEBUG_INIT,
3993                                    "HW Capability: MDIO port number = %d\n",
3994                                    p->mdio_port_num);
3995                         i40e_debug(hw, I40E_DEBUG_INIT,
3996                                    "HW Capability: MDIO port mode = %d\n",
3997                                    p->mdio_port_mode);
3998                         break;
3999                 case I40E_AQ_CAP_ID_1588:
4000                         if (number == 1)
4001                                 p->ieee_1588 = true;
4002                         i40e_debug(hw, I40E_DEBUG_INIT,
4003                                    "HW Capability: IEEE 1588 = %d\n",
4004                                    p->ieee_1588);
4005                         break;
4006                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
4007                         p->fd = true;
4008                         p->fd_filters_guaranteed = number;
4009                         p->fd_filters_best_effort = logical_id;
4010                         i40e_debug(hw, I40E_DEBUG_INIT,
4011                                    "HW Capability: Flow Director = 1\n");
4012                         i40e_debug(hw, I40E_DEBUG_INIT,
4013                                    "HW Capability: Guaranteed FD filters = %d\n",
4014                                    p->fd_filters_guaranteed);
4015                         break;
4016                 case I40E_AQ_CAP_ID_WSR_PROT:
4017                         p->wr_csr_prot = (u64)number;
4018                         p->wr_csr_prot |= (u64)logical_id << 32;
4019                         i40e_debug(hw, I40E_DEBUG_INIT,
4020                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
4021                                    (p->wr_csr_prot & 0xffff));
4022                         break;
4023                 case I40E_AQ_CAP_ID_NVM_MGMT:
4024                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
4025                                 p->sec_rev_disabled = true;
4026                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
4027                                 p->update_disabled = true;
4028                         break;
4029                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
4030                         hw->num_wol_proxy_filters = (u16)number;
4031                         hw->wol_proxy_vsi_seid = (u16)logical_id;
4032                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
4033                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
4034                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
4035                         else
4036                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
4037                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
4038                         i40e_debug(hw, I40E_DEBUG_INIT,
4039                                    "HW Capability: WOL proxy filters = %d\n",
4040                                    hw->num_wol_proxy_filters);
4041                         break;
4042                 default:
4043                         break;
4044                 }
4045         }
4046
4047         if (p->fcoe)
4048                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4049
4050         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4051         p->fcoe = false;
4052
4053         /* count the enabled ports (aka the "not disabled" ports) */
4054         hw->num_ports = 0;
4055         for (i = 0; i < 4; i++) {
4056                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4057                 u64 port_cfg = 0;
4058
4059                 /* use AQ read to get the physical register offset instead
4060                  * of the port relative offset
4061                  */
4062                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4063                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4064                         hw->num_ports++;
4065         }
4066
4067         /* OCP cards case: if a mezz is removed the ethernet port is at
4068          * disabled state in PRTGEN_CNF register. Additional NVM read is
4069          * needed in order to check if we are dealing with OCP card.
4070          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4071          * physical ports results in wrong partition id calculation and thus
4072          * not supporting WoL.
4073          */
4074         if (hw->mac.type == I40E_MAC_X722) {
4075                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4076                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4077                                                   2 * I40E_SR_OCP_CFG_WORD0,
4078                                                   sizeof(ocp_cfg_word0),
4079                                                   &ocp_cfg_word0, true, NULL);
4080                         if (status == I40E_SUCCESS &&
4081                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4082                                 hw->num_ports = 4;
4083                         i40e_release_nvm(hw);
4084                 }
4085         }
4086
4087         valid_functions = p->valid_functions;
4088         num_functions = 0;
4089         while (valid_functions) {
4090                 if (valid_functions & 1)
4091                         num_functions++;
4092                 valid_functions >>= 1;
4093         }
4094
4095         /* partition id is 1-based, and functions are evenly spread
4096          * across the ports as partitions
4097          */
4098         if (hw->num_ports != 0) {
4099                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4100                 hw->num_partitions = num_functions / hw->num_ports;
4101         }
4102
4103         /* additional HW specific goodies that might
4104          * someday be HW version specific
4105          */
4106         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4107 }
4108
4109 /**
4110  * i40e_aq_discover_capabilities
4111  * @hw: pointer to the hw struct
4112  * @buff: a virtual buffer to hold the capabilities
4113  * @buff_size: Size of the virtual buffer
4114  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4115  * @list_type_opc: capabilities type to discover - pass in the command opcode
4116  * @cmd_details: pointer to command details structure or NULL
4117  *
4118  * Get the device capabilities descriptions from the firmware
4119  **/
4120 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4121                                 void *buff, u16 buff_size, u16 *data_size,
4122                                 enum i40e_admin_queue_opc list_type_opc,
4123                                 struct i40e_asq_cmd_details *cmd_details)
4124 {
4125         struct i40e_aqc_list_capabilites *cmd;
4126         struct i40e_aq_desc desc;
4127         enum i40e_status_code status = I40E_SUCCESS;
4128
4129         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4130
4131         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4132                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4133                 status = I40E_ERR_PARAM;
4134                 goto exit;
4135         }
4136
4137         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4138
4139         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4140         if (buff_size > I40E_AQ_LARGE_BUF)
4141                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4142
4143         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4144         *data_size = LE16_TO_CPU(desc.datalen);
4145
4146         if (status)
4147                 goto exit;
4148
4149         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4150                                          list_type_opc);
4151
4152 exit:
4153         return status;
4154 }
4155
4156 /**
4157  * i40e_aq_update_nvm
4158  * @hw: pointer to the hw struct
4159  * @module_pointer: module pointer location in words from the NVM beginning
4160  * @offset: byte offset from the module beginning
4161  * @length: length of the section to be written (in bytes from the offset)
4162  * @data: command buffer (size [bytes] = length)
4163  * @last_command: tells if this is the last command in a series
4164  * @preservation_flags: Preservation mode flags
4165  * @cmd_details: pointer to command details structure or NULL
4166  *
4167  * Update the NVM using the admin queue commands
4168  **/
4169 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4170                                 u32 offset, u16 length, void *data,
4171                                 bool last_command, u8 preservation_flags,
4172                                 struct i40e_asq_cmd_details *cmd_details)
4173 {
4174         struct i40e_aq_desc desc;
4175         struct i40e_aqc_nvm_update *cmd =
4176                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4177         enum i40e_status_code status;
4178
4179         DEBUGFUNC("i40e_aq_update_nvm");
4180
4181         /* In offset the highest byte must be zeroed. */
4182         if (offset & 0xFF000000) {
4183                 status = I40E_ERR_PARAM;
4184                 goto i40e_aq_update_nvm_exit;
4185         }
4186
4187         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4188
4189         /* If this is the last command in a series, set the proper flag. */
4190         if (last_command)
4191                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4192         if (hw->mac.type == I40E_MAC_X722) {
4193                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4194                         cmd->command_flags |=
4195                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4196                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4197                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4198                         cmd->command_flags |=
4199                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4200                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4201         }
4202         cmd->module_pointer = module_pointer;
4203         cmd->offset = CPU_TO_LE32(offset);
4204         cmd->length = CPU_TO_LE16(length);
4205
4206         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4207         if (length > I40E_AQ_LARGE_BUF)
4208                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4209
4210         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4211
4212 i40e_aq_update_nvm_exit:
4213         return status;
4214 }
4215
4216 /**
4217  * i40e_aq_rearrange_nvm
4218  * @hw: pointer to the hw struct
4219  * @rearrange_nvm: defines direction of rearrangement
4220  * @cmd_details: pointer to command details structure or NULL
4221  *
4222  * Rearrange NVM structure, available only for transition FW
4223  **/
4224 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4225                                 u8 rearrange_nvm,
4226                                 struct i40e_asq_cmd_details *cmd_details)
4227 {
4228         struct i40e_aqc_nvm_update *cmd;
4229         enum i40e_status_code status;
4230         struct i40e_aq_desc desc;
4231
4232         DEBUGFUNC("i40e_aq_rearrange_nvm");
4233
4234         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4235
4236         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4237
4238         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4239                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4240
4241         if (!rearrange_nvm) {
4242                 status = I40E_ERR_PARAM;
4243                 goto i40e_aq_rearrange_nvm_exit;
4244         }
4245
4246         cmd->command_flags |= rearrange_nvm;
4247         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4248
4249 i40e_aq_rearrange_nvm_exit:
4250         return status;
4251 }
4252
4253 /**
4254  * i40e_aq_nvm_progress
4255  * @hw: pointer to the hw struct
4256  * @progress: pointer to progress returned from AQ
4257  * @cmd_details: pointer to command details structure or NULL
4258  *
4259  * Gets progress of flash rearrangement process
4260  **/
4261 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4262                                 struct i40e_asq_cmd_details *cmd_details)
4263 {
4264         enum i40e_status_code status;
4265         struct i40e_aq_desc desc;
4266
4267         DEBUGFUNC("i40e_aq_nvm_progress");
4268
4269         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4270         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4271         *progress = desc.params.raw[0];
4272         return status;
4273 }
4274
4275 /**
4276  * i40e_aq_get_lldp_mib
4277  * @hw: pointer to the hw struct
4278  * @bridge_type: type of bridge requested
4279  * @mib_type: Local, Remote or both Local and Remote MIBs
4280  * @buff: pointer to a user supplied buffer to store the MIB block
4281  * @buff_size: size of the buffer (in bytes)
4282  * @local_len : length of the returned Local LLDP MIB
4283  * @remote_len: length of the returned Remote LLDP MIB
4284  * @cmd_details: pointer to command details structure or NULL
4285  *
4286  * Requests the complete LLDP MIB (entire packet).
4287  **/
4288 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4289                                 u8 mib_type, void *buff, u16 buff_size,
4290                                 u16 *local_len, u16 *remote_len,
4291                                 struct i40e_asq_cmd_details *cmd_details)
4292 {
4293         struct i40e_aq_desc desc;
4294         struct i40e_aqc_lldp_get_mib *cmd =
4295                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4296         struct i40e_aqc_lldp_get_mib *resp =
4297                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4298         enum i40e_status_code status;
4299
4300         if (buff_size == 0 || !buff)
4301                 return I40E_ERR_PARAM;
4302
4303         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4304         /* Indirect Command */
4305         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4306
4307         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4308         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4309                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4310
4311         desc.datalen = CPU_TO_LE16(buff_size);
4312
4313         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4314         if (buff_size > I40E_AQ_LARGE_BUF)
4315                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4316
4317         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4318         if (!status) {
4319                 if (local_len != NULL)
4320                         *local_len = LE16_TO_CPU(resp->local_len);
4321                 if (remote_len != NULL)
4322                         *remote_len = LE16_TO_CPU(resp->remote_len);
4323         }
4324
4325         return status;
4326 }
4327
4328  /**
4329  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4330  * @hw: pointer to the hw struct
4331  * @mib_type: Local, Remote or both Local and Remote MIBs
4332  * @buff: pointer to a user supplied buffer to store the MIB block
4333  * @buff_size: size of the buffer (in bytes)
4334  * @cmd_details: pointer to command details structure or NULL
4335  *
4336  * Set the LLDP MIB.
4337  **/
4338 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4339                                 u8 mib_type, void *buff, u16 buff_size,
4340                                 struct i40e_asq_cmd_details *cmd_details)
4341 {
4342         struct i40e_aq_desc desc;
4343         struct i40e_aqc_lldp_set_local_mib *cmd =
4344                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4345         enum i40e_status_code status;
4346
4347         if (buff_size == 0 || !buff)
4348                 return I40E_ERR_PARAM;
4349
4350         i40e_fill_default_direct_cmd_desc(&desc,
4351                                 i40e_aqc_opc_lldp_set_local_mib);
4352         /* Indirect Command */
4353         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4354         if (buff_size > I40E_AQ_LARGE_BUF)
4355                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4356         desc.datalen = CPU_TO_LE16(buff_size);
4357
4358         cmd->type = mib_type;
4359         cmd->length = CPU_TO_LE16(buff_size);
4360         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4361         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4362
4363         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4364         return status;
4365 }
4366
4367 /**
4368  * i40e_aq_cfg_lldp_mib_change_event
4369  * @hw: pointer to the hw struct
4370  * @enable_update: Enable or Disable event posting
4371  * @cmd_details: pointer to command details structure or NULL
4372  *
4373  * Enable or Disable posting of an event on ARQ when LLDP MIB
4374  * associated with the interface changes
4375  **/
4376 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4377                                 bool enable_update,
4378                                 struct i40e_asq_cmd_details *cmd_details)
4379 {
4380         struct i40e_aq_desc desc;
4381         struct i40e_aqc_lldp_update_mib *cmd =
4382                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4383         enum i40e_status_code status;
4384
4385         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4386
4387         if (!enable_update)
4388                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4389
4390         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4391
4392         return status;
4393 }
4394
4395 /**
4396  * i40e_aq_restore_lldp
4397  * @hw: pointer to the hw struct
4398  * @setting: pointer to factory setting variable or NULL
4399  * @restore: True if factory settings should be restored
4400  * @cmd_details: pointer to command details structure or NULL
4401  *
4402  * Restore LLDP Agent factory settings if @restore set to True. In other case
4403  * only returns factory setting in AQ response.
4404  **/
4405 enum i40e_status_code
4406 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4407                      struct i40e_asq_cmd_details *cmd_details)
4408 {
4409         struct i40e_aq_desc desc;
4410         struct i40e_aqc_lldp_restore *cmd =
4411                 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4412         enum i40e_status_code status;
4413
4414         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4415                 i40e_debug(hw, I40E_DEBUG_ALL,
4416                            "Restore LLDP not supported by current FW version.\n");
4417                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4418         }
4419
4420         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4421
4422         if (restore)
4423                 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4424
4425         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4426
4427         if (setting)
4428                 *setting = cmd->command & 1;
4429
4430         return status;
4431 }
4432
4433 /**
4434  * i40e_aq_stop_lldp
4435  * @hw: pointer to the hw struct
4436  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4437  * @persist: True if stop of LLDP should be persistent across power cycles
4438  * @cmd_details: pointer to command details structure or NULL
4439  *
4440  * Stop or Shutdown the embedded LLDP Agent
4441  **/
4442 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4443                                 bool persist,
4444                                 struct i40e_asq_cmd_details *cmd_details)
4445 {
4446         struct i40e_aq_desc desc;
4447         struct i40e_aqc_lldp_stop *cmd =
4448                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4449         enum i40e_status_code status;
4450
4451         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4452
4453         if (shutdown_agent)
4454                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4455
4456         if (persist) {
4457                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4458                         cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4459                 else
4460                         i40e_debug(hw, I40E_DEBUG_ALL,
4461                                    "Persistent Stop LLDP not supported by current FW version.\n");
4462         }
4463
4464         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4465
4466         return status;
4467 }
4468
4469 /**
4470  * i40e_aq_start_lldp
4471  * @hw: pointer to the hw struct
4472  * @persist: True if start of LLDP should be persistent across power cycles
4473  * @cmd_details: pointer to command details structure or NULL
4474  *
4475  * Start the embedded LLDP Agent on all ports.
4476  **/
4477 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4478                                 bool persist,
4479                                 struct i40e_asq_cmd_details *cmd_details)
4480 {
4481         struct i40e_aq_desc desc;
4482         struct i40e_aqc_lldp_start *cmd =
4483                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4484         enum i40e_status_code status;
4485
4486         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4487
4488         cmd->command = I40E_AQ_LLDP_AGENT_START;
4489
4490         if (persist) {
4491                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4492                         cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4493                 else
4494                         i40e_debug(hw, I40E_DEBUG_ALL,
4495                                    "Persistent Start LLDP not supported by current FW version.\n");
4496         }
4497
4498         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4499
4500         return status;
4501 }
4502
4503 /**
4504  * i40e_aq_set_dcb_parameters
4505  * @hw: pointer to the hw struct
4506  * @cmd_details: pointer to command details structure or NULL
4507  * @dcb_enable: True if DCB configuration needs to be applied
4508  *
4509  **/
4510 enum i40e_status_code
4511 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4512                            struct i40e_asq_cmd_details *cmd_details)
4513 {
4514         struct i40e_aq_desc desc;
4515         struct i40e_aqc_set_dcb_parameters *cmd =
4516                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4517         enum i40e_status_code status;
4518
4519         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4520                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4521
4522         i40e_fill_default_direct_cmd_desc(&desc,
4523                                           i40e_aqc_opc_set_dcb_parameters);
4524
4525         if (dcb_enable) {
4526                 cmd->valid_flags = I40E_DCB_VALID;
4527                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4528         }
4529         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4530
4531         return status;
4532 }
4533
4534 /**
4535  * i40e_aq_get_cee_dcb_config
4536  * @hw: pointer to the hw struct
4537  * @buff: response buffer that stores CEE operational configuration
4538  * @buff_size: size of the buffer passed
4539  * @cmd_details: pointer to command details structure or NULL
4540  *
4541  * Get CEE DCBX mode operational configuration from firmware
4542  **/
4543 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4544                                 void *buff, u16 buff_size,
4545                                 struct i40e_asq_cmd_details *cmd_details)
4546 {
4547         struct i40e_aq_desc desc;
4548         enum i40e_status_code status;
4549
4550         if (buff_size == 0 || !buff)
4551                 return I40E_ERR_PARAM;
4552
4553         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4554
4555         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4556         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4557                                        cmd_details);
4558
4559         return status;
4560 }
4561
4562 /**
4563  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4564  * @hw: pointer to the hw struct
4565  * @start_agent: True if DCBx Agent needs to be Started
4566  *                              False if DCBx Agent needs to be Stopped
4567  * @cmd_details: pointer to command details structure or NULL
4568  *
4569  * Start/Stop the embedded dcbx Agent
4570  **/
4571 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4572                                 bool start_agent,
4573                                 struct i40e_asq_cmd_details *cmd_details)
4574 {
4575         struct i40e_aq_desc desc;
4576         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4577                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4578                                 &desc.params.raw;
4579         enum i40e_status_code status;
4580
4581         i40e_fill_default_direct_cmd_desc(&desc,
4582                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4583
4584         if (start_agent)
4585                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4586
4587         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4588
4589         return status;
4590 }
4591
4592 /**
4593  * i40e_aq_add_udp_tunnel
4594  * @hw: pointer to the hw struct
4595  * @udp_port: the UDP port to add in Host byte order
4596  * @protocol_index: protocol index type
4597  * @filter_index: pointer to filter index
4598  * @cmd_details: pointer to command details structure or NULL
4599  *
4600  * Note: Firmware expects the udp_port value to be in Little Endian format,
4601  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4602  * Little Endian order.
4603  **/
4604 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4605                                 u16 udp_port, u8 protocol_index,
4606                                 u8 *filter_index,
4607                                 struct i40e_asq_cmd_details *cmd_details)
4608 {
4609         struct i40e_aq_desc desc;
4610         struct i40e_aqc_add_udp_tunnel *cmd =
4611                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4612         struct i40e_aqc_del_udp_tunnel_completion *resp =
4613                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4614         enum i40e_status_code status;
4615
4616         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4617
4618         cmd->udp_port = CPU_TO_LE16(udp_port);
4619         cmd->protocol_type = protocol_index;
4620
4621         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4622
4623         if (!status && filter_index)
4624                 *filter_index = resp->index;
4625
4626         return status;
4627 }
4628
4629 /**
4630  * i40e_aq_del_udp_tunnel
4631  * @hw: pointer to the hw struct
4632  * @index: filter index
4633  * @cmd_details: pointer to command details structure or NULL
4634  **/
4635 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4636                                 struct i40e_asq_cmd_details *cmd_details)
4637 {
4638         struct i40e_aq_desc desc;
4639         struct i40e_aqc_remove_udp_tunnel *cmd =
4640                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4641         enum i40e_status_code status;
4642
4643         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4644
4645         cmd->index = index;
4646
4647         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4648
4649         return status;
4650 }
4651
4652 /**
4653  * i40e_aq_get_switch_resource_alloc (0x0204)
4654  * @hw: pointer to the hw struct
4655  * @num_entries: pointer to u8 to store the number of resource entries returned
4656  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4657  *        to store the resource information for all resource types.  Each
4658  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4659  * @count: size, in bytes, of the buffer provided
4660  * @cmd_details: pointer to command details structure or NULL
4661  *
4662  * Query the resources allocated to a function.
4663  **/
4664 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4665                         u8 *num_entries,
4666                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4667                         u16 count,
4668                         struct i40e_asq_cmd_details *cmd_details)
4669 {
4670         struct i40e_aq_desc desc;
4671         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4672                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4673         enum i40e_status_code status;
4674         u16 length = count * sizeof(*buf);
4675
4676         i40e_fill_default_direct_cmd_desc(&desc,
4677                                         i40e_aqc_opc_get_switch_resource_alloc);
4678
4679         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4680         if (length > I40E_AQ_LARGE_BUF)
4681                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4682
4683         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4684
4685         if (!status && num_entries)
4686                 *num_entries = cmd_resp->num_entries;
4687
4688         return status;
4689 }
4690
4691 /**
4692  * i40e_aq_delete_element - Delete switch element
4693  * @hw: pointer to the hw struct
4694  * @seid: the SEID to delete from the switch
4695  * @cmd_details: pointer to command details structure or NULL
4696  *
4697  * This deletes a switch element from the switch.
4698  **/
4699 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4700                                 struct i40e_asq_cmd_details *cmd_details)
4701 {
4702         struct i40e_aq_desc desc;
4703         struct i40e_aqc_switch_seid *cmd =
4704                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4705         enum i40e_status_code status;
4706
4707         if (seid == 0)
4708                 return I40E_ERR_PARAM;
4709
4710         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4711
4712         cmd->seid = CPU_TO_LE16(seid);
4713
4714         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4715
4716         return status;
4717 }
4718
4719 /**
4720  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4721  * @hw: pointer to the hw struct
4722  * @flags: component flags
4723  * @mac_seid: uplink seid (MAC SEID)
4724  * @vsi_seid: connected vsi seid
4725  * @ret_seid: seid of create pv component
4726  *
4727  * This instantiates an i40e port virtualizer with specified flags.
4728  * Depending on specified flags the port virtualizer can act as a
4729  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4730  */
4731 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4732                                        u16 mac_seid, u16 vsi_seid,
4733                                        u16 *ret_seid)
4734 {
4735         struct i40e_aq_desc desc;
4736         struct i40e_aqc_add_update_pv *cmd =
4737                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4738         struct i40e_aqc_add_update_pv_completion *resp =
4739                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4740         enum i40e_status_code status;
4741
4742         if (vsi_seid == 0)
4743                 return I40E_ERR_PARAM;
4744
4745         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4746         cmd->command_flags = CPU_TO_LE16(flags);
4747         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4748         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4749
4750         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4751         if (!status && ret_seid)
4752                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4753
4754         return status;
4755 }
4756
4757 /**
4758  * i40e_aq_add_tag - Add an S/E-tag
4759  * @hw: pointer to the hw struct
4760  * @direct_to_queue: should s-tag direct flow to a specific queue
4761  * @vsi_seid: VSI SEID to use this tag
4762  * @tag: value of the tag
4763  * @queue_num: queue number, only valid is direct_to_queue is true
4764  * @tags_used: return value, number of tags in use by this PF
4765  * @tags_free: return value, number of unallocated tags
4766  * @cmd_details: pointer to command details structure or NULL
4767  *
4768  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4769  * the number of tags allocated by the PF, and the number of unallocated
4770  * tags available.
4771  **/
4772 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4773                                 u16 vsi_seid, u16 tag, u16 queue_num,
4774                                 u16 *tags_used, u16 *tags_free,
4775                                 struct i40e_asq_cmd_details *cmd_details)
4776 {
4777         struct i40e_aq_desc desc;
4778         struct i40e_aqc_add_tag *cmd =
4779                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4780         struct i40e_aqc_add_remove_tag_completion *resp =
4781                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4782         enum i40e_status_code status;
4783
4784         if (vsi_seid == 0)
4785                 return I40E_ERR_PARAM;
4786
4787         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4788
4789         cmd->seid = CPU_TO_LE16(vsi_seid);
4790         cmd->tag = CPU_TO_LE16(tag);
4791         if (direct_to_queue) {
4792                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4793                 cmd->queue_number = CPU_TO_LE16(queue_num);
4794         }
4795
4796         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4797
4798         if (!status) {
4799                 if (tags_used != NULL)
4800                         *tags_used = LE16_TO_CPU(resp->tags_used);
4801                 if (tags_free != NULL)
4802                         *tags_free = LE16_TO_CPU(resp->tags_free);
4803         }
4804
4805         return status;
4806 }
4807
4808 /**
4809  * i40e_aq_remove_tag - Remove an S- or E-tag
4810  * @hw: pointer to the hw struct
4811  * @vsi_seid: VSI SEID this tag is associated with
4812  * @tag: value of the S-tag to delete
4813  * @tags_used: return value, number of tags in use by this PF
4814  * @tags_free: return value, number of unallocated tags
4815  * @cmd_details: pointer to command details structure or NULL
4816  *
4817  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4818  * the number of tags allocated by the PF, and the number of unallocated
4819  * tags available.
4820  **/
4821 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4822                                 u16 tag, u16 *tags_used, u16 *tags_free,
4823                                 struct i40e_asq_cmd_details *cmd_details)
4824 {
4825         struct i40e_aq_desc desc;
4826         struct i40e_aqc_remove_tag *cmd =
4827                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4828         struct i40e_aqc_add_remove_tag_completion *resp =
4829                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4830         enum i40e_status_code status;
4831
4832         if (vsi_seid == 0)
4833                 return I40E_ERR_PARAM;
4834
4835         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4836
4837         cmd->seid = CPU_TO_LE16(vsi_seid);
4838         cmd->tag = CPU_TO_LE16(tag);
4839
4840         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4841
4842         if (!status) {
4843                 if (tags_used != NULL)
4844                         *tags_used = LE16_TO_CPU(resp->tags_used);
4845                 if (tags_free != NULL)
4846                         *tags_free = LE16_TO_CPU(resp->tags_free);
4847         }
4848
4849         return status;
4850 }
4851
4852 /**
4853  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4854  * @hw: pointer to the hw struct
4855  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4856  * @etag: value of E-tag to add
4857  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4858  * @buf: address of indirect buffer
4859  * @tags_used: return value, number of E-tags in use by this port
4860  * @tags_free: return value, number of unallocated M-tags
4861  * @cmd_details: pointer to command details structure or NULL
4862  *
4863  * This associates a multicast E-tag to a port virtualizer.  It will return
4864  * the number of tags allocated by the PF, and the number of unallocated
4865  * tags available.
4866  *
4867  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4868  * num_tags_in_buf long.
4869  **/
4870 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4871                                 u16 etag, u8 num_tags_in_buf, void *buf,
4872                                 u16 *tags_used, u16 *tags_free,
4873                                 struct i40e_asq_cmd_details *cmd_details)
4874 {
4875         struct i40e_aq_desc desc;
4876         struct i40e_aqc_add_remove_mcast_etag *cmd =
4877                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4878         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4879            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4880         enum i40e_status_code status;
4881         u16 length = sizeof(u16) * num_tags_in_buf;
4882
4883         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4884                 return I40E_ERR_PARAM;
4885
4886         i40e_fill_default_direct_cmd_desc(&desc,
4887                                           i40e_aqc_opc_add_multicast_etag);
4888
4889         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4890         cmd->etag = CPU_TO_LE16(etag);
4891         cmd->num_unicast_etags = num_tags_in_buf;
4892
4893         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4894
4895         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4896
4897         if (!status) {
4898                 if (tags_used != NULL)
4899                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4900                 if (tags_free != NULL)
4901                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4902         }
4903
4904         return status;
4905 }
4906
4907 /**
4908  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4909  * @hw: pointer to the hw struct
4910  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4911  * @etag: value of the E-tag to remove
4912  * @tags_used: return value, number of tags in use by this port
4913  * @tags_free: return value, number of unallocated tags
4914  * @cmd_details: pointer to command details structure or NULL
4915  *
4916  * This deletes an E-tag from the port virtualizer.  It will return
4917  * the number of tags allocated by the port, and the number of unallocated
4918  * tags available.
4919  **/
4920 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4921                                 u16 etag, u16 *tags_used, u16 *tags_free,
4922                                 struct i40e_asq_cmd_details *cmd_details)
4923 {
4924         struct i40e_aq_desc desc;
4925         struct i40e_aqc_add_remove_mcast_etag *cmd =
4926                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4927         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4928            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4929         enum i40e_status_code status;
4930
4931
4932         if (pv_seid == 0)
4933                 return I40E_ERR_PARAM;
4934
4935         i40e_fill_default_direct_cmd_desc(&desc,
4936                                           i40e_aqc_opc_remove_multicast_etag);
4937
4938         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4939         cmd->etag = CPU_TO_LE16(etag);
4940
4941         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4942
4943         if (!status) {
4944                 if (tags_used != NULL)
4945                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4946                 if (tags_free != NULL)
4947                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4948         }
4949
4950         return status;
4951 }
4952
4953 /**
4954  * i40e_aq_update_tag - Update an S/E-tag
4955  * @hw: pointer to the hw struct
4956  * @vsi_seid: VSI SEID using this S-tag
4957  * @old_tag: old tag value
4958  * @new_tag: new tag value
4959  * @tags_used: return value, number of tags in use by this PF
4960  * @tags_free: return value, number of unallocated tags
4961  * @cmd_details: pointer to command details structure or NULL
4962  *
4963  * This updates the value of the tag currently attached to this VSI
4964  * in the switch complex.  It will return the number of tags allocated
4965  * by the PF, and the number of unallocated tags available.
4966  **/
4967 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4968                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4969                                 u16 *tags_free,
4970                                 struct i40e_asq_cmd_details *cmd_details)
4971 {
4972         struct i40e_aq_desc desc;
4973         struct i40e_aqc_update_tag *cmd =
4974                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4975         struct i40e_aqc_update_tag_completion *resp =
4976                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4977         enum i40e_status_code status;
4978
4979         if (vsi_seid == 0)
4980                 return I40E_ERR_PARAM;
4981
4982         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4983
4984         cmd->seid = CPU_TO_LE16(vsi_seid);
4985         cmd->old_tag = CPU_TO_LE16(old_tag);
4986         cmd->new_tag = CPU_TO_LE16(new_tag);
4987
4988         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4989
4990         if (!status) {
4991                 if (tags_used != NULL)
4992                         *tags_used = LE16_TO_CPU(resp->tags_used);
4993                 if (tags_free != NULL)
4994                         *tags_free = LE16_TO_CPU(resp->tags_free);
4995         }
4996
4997         return status;
4998 }
4999
5000 /**
5001  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5002  * @hw: pointer to the hw struct
5003  * @tcmap: TC map for request/release any ignore PFC condition
5004  * @request: request or release ignore PFC condition
5005  * @tcmap_ret: return TCs for which PFC is currently ignored
5006  * @cmd_details: pointer to command details structure or NULL
5007  *
5008  * This sends out request/release to ignore PFC condition for a TC.
5009  * It will return the TCs for which PFC is currently ignored.
5010  **/
5011 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5012                                 bool request, u8 *tcmap_ret,
5013                                 struct i40e_asq_cmd_details *cmd_details)
5014 {
5015         struct i40e_aq_desc desc;
5016         struct i40e_aqc_pfc_ignore *cmd_resp =
5017                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5018         enum i40e_status_code status;
5019
5020         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5021
5022         if (request)
5023                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5024
5025         cmd_resp->tc_bitmap = tcmap;
5026
5027         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5028
5029         if (!status) {
5030                 if (tcmap_ret != NULL)
5031                         *tcmap_ret = cmd_resp->tc_bitmap;
5032         }
5033
5034         return status;
5035 }
5036
5037 /**
5038  * i40e_aq_dcb_updated - DCB Updated Command
5039  * @hw: pointer to the hw struct
5040  * @cmd_details: pointer to command details structure or NULL
5041  *
5042  * When LLDP is handled in PF this command is used by the PF
5043  * to notify EMP that a DCB setting is modified.
5044  * When LLDP is handled in EMP this command is used by the PF
5045  * to notify EMP whenever one of the following parameters get
5046  * modified:
5047  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5048  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5049  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5050  * EMP will return when the shared RPB settings have been
5051  * recomputed and modified. The retval field in the descriptor
5052  * will be set to 0 when RPB is modified.
5053  **/
5054 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5055                                 struct i40e_asq_cmd_details *cmd_details)
5056 {
5057         struct i40e_aq_desc desc;
5058         enum i40e_status_code status;
5059
5060         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5061
5062         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5063
5064         return status;
5065 }
5066
5067 /**
5068  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5069  * @hw: pointer to the hw struct
5070  * @seid: defines the SEID of the switch for which the stats are requested
5071  * @vlan_id: the VLAN ID for which the statistics are requested
5072  * @stat_index: index of the statistics counters block assigned to this VLAN
5073  * @cmd_details: pointer to command details structure or NULL
5074  *
5075  * XL710 supports 128 smonVlanStats counters.This command is used to
5076  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5077  * switch.
5078  **/
5079 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5080                                 u16 vlan_id, u16 *stat_index,
5081                                 struct i40e_asq_cmd_details *cmd_details)
5082 {
5083         struct i40e_aq_desc desc;
5084         struct i40e_aqc_add_remove_statistics *cmd_resp =
5085                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5086         enum i40e_status_code status;
5087
5088         if ((seid == 0) || (stat_index == NULL))
5089                 return I40E_ERR_PARAM;
5090
5091         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5092
5093         cmd_resp->seid = CPU_TO_LE16(seid);
5094         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5095
5096         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5097
5098         if (!status && stat_index)
5099                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5100
5101         return status;
5102 }
5103
5104 /**
5105  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5106  * @hw: pointer to the hw struct
5107  * @seid: defines the SEID of the switch for which the stats are requested
5108  * @vlan_id: the VLAN ID for which the statistics are requested
5109  * @stat_index: index of the statistics counters block assigned to this VLAN
5110  * @cmd_details: pointer to command details structure or NULL
5111  *
5112  * XL710 supports 128 smonVlanStats counters.This command is used to
5113  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5114  * switch.
5115  **/
5116 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5117                                 u16 vlan_id, u16 stat_index,
5118                                 struct i40e_asq_cmd_details *cmd_details)
5119 {
5120         struct i40e_aq_desc desc;
5121         struct i40e_aqc_add_remove_statistics *cmd =
5122                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5123         enum i40e_status_code status;
5124
5125         if (seid == 0)
5126                 return I40E_ERR_PARAM;
5127
5128         i40e_fill_default_direct_cmd_desc(&desc,
5129                                           i40e_aqc_opc_remove_statistics);
5130
5131         cmd->seid = CPU_TO_LE16(seid);
5132         cmd->vlan  = CPU_TO_LE16(vlan_id);
5133         cmd->stat_index = CPU_TO_LE16(stat_index);
5134
5135         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5136
5137         return status;
5138 }
5139
5140 /**
5141  * i40e_aq_set_port_parameters - set physical port parameters.
5142  * @hw: pointer to the hw struct
5143  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5144  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5145  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5146  * @double_vlan: if set double VLAN is enabled
5147  * @cmd_details: pointer to command details structure or NULL
5148  **/
5149 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5150                                 u16 bad_frame_vsi, bool save_bad_pac,
5151                                 bool pad_short_pac, bool double_vlan,
5152                                 struct i40e_asq_cmd_details *cmd_details)
5153 {
5154         struct i40e_aqc_set_port_parameters *cmd;
5155         enum i40e_status_code status;
5156         struct i40e_aq_desc desc;
5157         u16 command_flags = 0;
5158
5159         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5160
5161         i40e_fill_default_direct_cmd_desc(&desc,
5162                                           i40e_aqc_opc_set_port_parameters);
5163
5164         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5165         if (save_bad_pac)
5166                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5167         if (pad_short_pac)
5168                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5169         if (double_vlan)
5170                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5171         cmd->command_flags = CPU_TO_LE16(command_flags);
5172
5173         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5174
5175         return status;
5176 }
5177
5178 /**
5179  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5180  * @hw: pointer to the hw struct
5181  * @seid: seid for the physical port/switching component/vsi
5182  * @buff: Indirect buffer to hold data parameters and response
5183  * @buff_size: Indirect buffer size
5184  * @opcode: Tx scheduler AQ command opcode
5185  * @cmd_details: pointer to command details structure or NULL
5186  *
5187  * Generic command handler for Tx scheduler AQ commands
5188  **/
5189 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5190                                 void *buff, u16 buff_size,
5191                                  enum i40e_admin_queue_opc opcode,
5192                                 struct i40e_asq_cmd_details *cmd_details)
5193 {
5194         struct i40e_aq_desc desc;
5195         struct i40e_aqc_tx_sched_ind *cmd =
5196                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5197         enum i40e_status_code status;
5198         bool cmd_param_flag = false;
5199
5200         switch (opcode) {
5201         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5202         case i40e_aqc_opc_configure_vsi_tc_bw:
5203         case i40e_aqc_opc_enable_switching_comp_ets:
5204         case i40e_aqc_opc_modify_switching_comp_ets:
5205         case i40e_aqc_opc_disable_switching_comp_ets:
5206         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5207         case i40e_aqc_opc_configure_switching_comp_bw_config:
5208                 cmd_param_flag = true;
5209                 break;
5210         case i40e_aqc_opc_query_vsi_bw_config:
5211         case i40e_aqc_opc_query_vsi_ets_sla_config:
5212         case i40e_aqc_opc_query_switching_comp_ets_config:
5213         case i40e_aqc_opc_query_port_ets_config:
5214         case i40e_aqc_opc_query_switching_comp_bw_config:
5215                 cmd_param_flag = false;
5216                 break;
5217         default:
5218                 return I40E_ERR_PARAM;
5219         }
5220
5221         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5222
5223         /* Indirect command */
5224         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5225         if (cmd_param_flag)
5226                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5227         if (buff_size > I40E_AQ_LARGE_BUF)
5228                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5229
5230         desc.datalen = CPU_TO_LE16(buff_size);
5231
5232         cmd->vsi_seid = CPU_TO_LE16(seid);
5233
5234         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5235
5236         return status;
5237 }
5238
5239 /**
5240  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5241  * @hw: pointer to the hw struct
5242  * @seid: VSI seid
5243  * @credit: BW limit credits (0 = disabled)
5244  * @max_credit: Max BW limit credits
5245  * @cmd_details: pointer to command details structure or NULL
5246  **/
5247 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5248                                 u16 seid, u16 credit, u8 max_credit,
5249                                 struct i40e_asq_cmd_details *cmd_details)
5250 {
5251         struct i40e_aq_desc desc;
5252         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5253                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5254         enum i40e_status_code status;
5255
5256         i40e_fill_default_direct_cmd_desc(&desc,
5257                                           i40e_aqc_opc_configure_vsi_bw_limit);
5258
5259         cmd->vsi_seid = CPU_TO_LE16(seid);
5260         cmd->credit = CPU_TO_LE16(credit);
5261         cmd->max_credit = max_credit;
5262
5263         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5264
5265         return status;
5266 }
5267
5268 /**
5269  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5270  * @hw: pointer to the hw struct
5271  * @seid: switching component seid
5272  * @credit: BW limit credits (0 = disabled)
5273  * @max_bw: Max BW limit credits
5274  * @cmd_details: pointer to command details structure or NULL
5275  **/
5276 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5277                                 u16 seid, u16 credit, u8 max_bw,
5278                                 struct i40e_asq_cmd_details *cmd_details)
5279 {
5280         struct i40e_aq_desc desc;
5281         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5282           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5283         enum i40e_status_code status;
5284
5285         i40e_fill_default_direct_cmd_desc(&desc,
5286                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5287
5288         cmd->seid = CPU_TO_LE16(seid);
5289         cmd->credit = CPU_TO_LE16(credit);
5290         cmd->max_bw = max_bw;
5291
5292         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5293
5294         return status;
5295 }
5296
5297 /**
5298  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5299  * @hw: pointer to the hw struct
5300  * @seid: VSI seid
5301  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5302  * @cmd_details: pointer to command details structure or NULL
5303  **/
5304 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5305                         u16 seid,
5306                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5307                         struct i40e_asq_cmd_details *cmd_details)
5308 {
5309         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5310                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5311                                     cmd_details);
5312 }
5313
5314 /**
5315  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5316  * @hw: pointer to the hw struct
5317  * @seid: VSI seid
5318  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5319  * @cmd_details: pointer to command details structure or NULL
5320  **/
5321 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5322                         u16 seid,
5323                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5324                         struct i40e_asq_cmd_details *cmd_details)
5325 {
5326         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5327                                     i40e_aqc_opc_configure_vsi_tc_bw,
5328                                     cmd_details);
5329 }
5330
5331 /**
5332  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5333  * @hw: pointer to the hw struct
5334  * @seid: seid of the switching component connected to Physical Port
5335  * @ets_data: Buffer holding ETS parameters
5336  * @opcode: Tx scheduler AQ command opcode
5337  * @cmd_details: pointer to command details structure or NULL
5338  **/
5339 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5340                 u16 seid,
5341                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5342                 enum i40e_admin_queue_opc opcode,
5343                 struct i40e_asq_cmd_details *cmd_details)
5344 {
5345         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5346                                     sizeof(*ets_data), opcode, cmd_details);
5347 }
5348
5349 /**
5350  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5351  * @hw: pointer to the hw struct
5352  * @seid: seid of the switching component
5353  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5354  * @cmd_details: pointer to command details structure or NULL
5355  **/
5356 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5357         u16 seid,
5358         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5359         struct i40e_asq_cmd_details *cmd_details)
5360 {
5361         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5362                             i40e_aqc_opc_configure_switching_comp_bw_config,
5363                             cmd_details);
5364 }
5365
5366 /**
5367  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5368  * @hw: pointer to the hw struct
5369  * @seid: seid of the switching component
5370  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5371  * @cmd_details: pointer to command details structure or NULL
5372  **/
5373 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5374         struct i40e_hw *hw, u16 seid,
5375         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5376         struct i40e_asq_cmd_details *cmd_details)
5377 {
5378         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5379                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5380                             cmd_details);
5381 }
5382
5383 /**
5384  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5385  * @hw: pointer to the hw struct
5386  * @seid: seid of the VSI
5387  * @bw_data: Buffer to hold VSI BW configuration
5388  * @cmd_details: pointer to command details structure or NULL
5389  **/
5390 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5391                         u16 seid,
5392                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5393                         struct i40e_asq_cmd_details *cmd_details)
5394 {
5395         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5396                                     i40e_aqc_opc_query_vsi_bw_config,
5397                                     cmd_details);
5398 }
5399
5400 /**
5401  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5402  * @hw: pointer to the hw struct
5403  * @seid: seid of the VSI
5404  * @bw_data: Buffer to hold VSI BW configuration per TC
5405  * @cmd_details: pointer to command details structure or NULL
5406  **/
5407 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5408                         u16 seid,
5409                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5410                         struct i40e_asq_cmd_details *cmd_details)
5411 {
5412         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5413                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5414                                     cmd_details);
5415 }
5416
5417 /**
5418  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5419  * @hw: pointer to the hw struct
5420  * @seid: seid of the switching component
5421  * @bw_data: Buffer to hold switching component's per TC BW config
5422  * @cmd_details: pointer to command details structure or NULL
5423  **/
5424 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5425                 u16 seid,
5426                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5427                 struct i40e_asq_cmd_details *cmd_details)
5428 {
5429         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5430                                    i40e_aqc_opc_query_switching_comp_ets_config,
5431                                    cmd_details);
5432 }
5433
5434 /**
5435  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5436  * @hw: pointer to the hw struct
5437  * @seid: seid of the VSI or switching component connected to Physical Port
5438  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5439  * @cmd_details: pointer to command details structure or NULL
5440  **/
5441 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5442                         u16 seid,
5443                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5444                         struct i40e_asq_cmd_details *cmd_details)
5445 {
5446         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5447                                     i40e_aqc_opc_query_port_ets_config,
5448                                     cmd_details);
5449 }
5450
5451 /**
5452  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5453  * @hw: pointer to the hw struct
5454  * @seid: seid of the switching component
5455  * @bw_data: Buffer to hold switching component's BW configuration
5456  * @cmd_details: pointer to command details structure or NULL
5457  **/
5458 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5459                 u16 seid,
5460                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5461                 struct i40e_asq_cmd_details *cmd_details)
5462 {
5463         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5464                                     i40e_aqc_opc_query_switching_comp_bw_config,
5465                                     cmd_details);
5466 }
5467
5468 /**
5469  * i40e_validate_filter_settings
5470  * @hw: pointer to the hardware structure
5471  * @settings: Filter control settings
5472  *
5473  * Check and validate the filter control settings passed.
5474  * The function checks for the valid filter/context sizes being
5475  * passed for FCoE and PE.
5476  *
5477  * Returns I40E_SUCCESS if the values passed are valid and within
5478  * range else returns an error.
5479  **/
5480 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5481                                 struct i40e_filter_control_settings *settings)
5482 {
5483         u32 fcoe_cntx_size, fcoe_filt_size;
5484         u32 pe_cntx_size, pe_filt_size;
5485         u32 fcoe_fmax;
5486
5487         u32 val;
5488
5489         /* Validate FCoE settings passed */
5490         switch (settings->fcoe_filt_num) {
5491         case I40E_HASH_FILTER_SIZE_1K:
5492         case I40E_HASH_FILTER_SIZE_2K:
5493         case I40E_HASH_FILTER_SIZE_4K:
5494         case I40E_HASH_FILTER_SIZE_8K:
5495         case I40E_HASH_FILTER_SIZE_16K:
5496         case I40E_HASH_FILTER_SIZE_32K:
5497                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5498                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5499                 break;
5500         default:
5501                 return I40E_ERR_PARAM;
5502         }
5503
5504         switch (settings->fcoe_cntx_num) {
5505         case I40E_DMA_CNTX_SIZE_512:
5506         case I40E_DMA_CNTX_SIZE_1K:
5507         case I40E_DMA_CNTX_SIZE_2K:
5508         case I40E_DMA_CNTX_SIZE_4K:
5509                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5510                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5511                 break;
5512         default:
5513                 return I40E_ERR_PARAM;
5514         }
5515
5516         /* Validate PE settings passed */
5517         switch (settings->pe_filt_num) {
5518         case I40E_HASH_FILTER_SIZE_1K:
5519         case I40E_HASH_FILTER_SIZE_2K:
5520         case I40E_HASH_FILTER_SIZE_4K:
5521         case I40E_HASH_FILTER_SIZE_8K:
5522         case I40E_HASH_FILTER_SIZE_16K:
5523         case I40E_HASH_FILTER_SIZE_32K:
5524         case I40E_HASH_FILTER_SIZE_64K:
5525         case I40E_HASH_FILTER_SIZE_128K:
5526         case I40E_HASH_FILTER_SIZE_256K:
5527         case I40E_HASH_FILTER_SIZE_512K:
5528         case I40E_HASH_FILTER_SIZE_1M:
5529                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5530                 pe_filt_size <<= (u32)settings->pe_filt_num;
5531                 break;
5532         default:
5533                 return I40E_ERR_PARAM;
5534         }
5535
5536         switch (settings->pe_cntx_num) {
5537         case I40E_DMA_CNTX_SIZE_512:
5538         case I40E_DMA_CNTX_SIZE_1K:
5539         case I40E_DMA_CNTX_SIZE_2K:
5540         case I40E_DMA_CNTX_SIZE_4K:
5541         case I40E_DMA_CNTX_SIZE_8K:
5542         case I40E_DMA_CNTX_SIZE_16K:
5543         case I40E_DMA_CNTX_SIZE_32K:
5544         case I40E_DMA_CNTX_SIZE_64K:
5545         case I40E_DMA_CNTX_SIZE_128K:
5546         case I40E_DMA_CNTX_SIZE_256K:
5547                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5548                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5549                 break;
5550         default:
5551                 return I40E_ERR_PARAM;
5552         }
5553
5554         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5555         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5556         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5557                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5558         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5559                 return I40E_ERR_INVALID_SIZE;
5560
5561         return I40E_SUCCESS;
5562 }
5563
5564 /**
5565  * i40e_set_filter_control
5566  * @hw: pointer to the hardware structure
5567  * @settings: Filter control settings
5568  *
5569  * Set the Queue Filters for PE/FCoE and enable filters required
5570  * for a single PF. It is expected that these settings are programmed
5571  * at the driver initialization time.
5572  **/
5573 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5574                                 struct i40e_filter_control_settings *settings)
5575 {
5576         enum i40e_status_code ret = I40E_SUCCESS;
5577         u32 hash_lut_size = 0;
5578         u32 val;
5579
5580         if (!settings)
5581                 return I40E_ERR_PARAM;
5582
5583         /* Validate the input settings */
5584         ret = i40e_validate_filter_settings(hw, settings);
5585         if (ret)
5586                 return ret;
5587
5588         /* Read the PF Queue Filter control register */
5589         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5590
5591         /* Program required PE hash buckets for the PF */
5592         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5593         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5594                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5595         /* Program required PE contexts for the PF */
5596         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5597         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5598                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5599
5600         /* Program required FCoE hash buckets for the PF */
5601         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5602         val |= ((u32)settings->fcoe_filt_num <<
5603                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5604                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5605         /* Program required FCoE DDP contexts for the PF */
5606         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5607         val |= ((u32)settings->fcoe_cntx_num <<
5608                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5609                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5610
5611         /* Program Hash LUT size for the PF */
5612         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5613         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5614                 hash_lut_size = 1;
5615         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5616                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5617
5618         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5619         if (settings->enable_fdir)
5620                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5621         if (settings->enable_ethtype)
5622                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5623         if (settings->enable_macvlan)
5624                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5625
5626         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5627
5628         return I40E_SUCCESS;
5629 }
5630
5631 /**
5632  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5633  * @hw: pointer to the hw struct
5634  * @mac_addr: MAC address to use in the filter
5635  * @ethtype: Ethertype to use in the filter
5636  * @flags: Flags that needs to be applied to the filter
5637  * @vsi_seid: seid of the control VSI
5638  * @queue: VSI queue number to send the packet to
5639  * @is_add: Add control packet filter if True else remove
5640  * @stats: Structure to hold information on control filter counts
5641  * @cmd_details: pointer to command details structure or NULL
5642  *
5643  * This command will Add or Remove control packet filter for a control VSI.
5644  * In return it will update the total number of perfect filter count in
5645  * the stats member.
5646  **/
5647 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5648                                 u8 *mac_addr, u16 ethtype, u16 flags,
5649                                 u16 vsi_seid, u16 queue, bool is_add,
5650                                 struct i40e_control_filter_stats *stats,
5651                                 struct i40e_asq_cmd_details *cmd_details)
5652 {
5653         struct i40e_aq_desc desc;
5654         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5655                 (struct i40e_aqc_add_remove_control_packet_filter *)
5656                 &desc.params.raw;
5657         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5658                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5659                 &desc.params.raw;
5660         enum i40e_status_code status;
5661
5662         if (vsi_seid == 0)
5663                 return I40E_ERR_PARAM;
5664
5665         if (is_add) {
5666                 i40e_fill_default_direct_cmd_desc(&desc,
5667                                 i40e_aqc_opc_add_control_packet_filter);
5668                 cmd->queue = CPU_TO_LE16(queue);
5669         } else {
5670                 i40e_fill_default_direct_cmd_desc(&desc,
5671                                 i40e_aqc_opc_remove_control_packet_filter);
5672         }
5673
5674         if (mac_addr)
5675                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5676                             I40E_NONDMA_TO_NONDMA);
5677
5678         cmd->etype = CPU_TO_LE16(ethtype);
5679         cmd->flags = CPU_TO_LE16(flags);
5680         cmd->seid = CPU_TO_LE16(vsi_seid);
5681
5682         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5683
5684         if (!status && stats) {
5685                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5686                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5687                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5688                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5689         }
5690
5691         return status;
5692 }
5693
5694 /**
5695  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5696  * @hw: pointer to the hw struct
5697  * @seid: VSI seid to add ethertype filter from
5698  **/
5699 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5700                                                     u16 seid)
5701 {
5702 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5703         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5704                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5705                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5706         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5707         enum i40e_status_code status;
5708
5709         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5710                                                        seid, 0, true, NULL,
5711                                                        NULL);
5712         if (status)
5713                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5714 }
5715
5716 /**
5717  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5718  * @filters: list of cloud filters
5719  * @filter_count: length of list
5720  *
5721  * There's an issue in the device where the Geneve VNI layout needs
5722  * to be shifted 1 byte over from the VxLAN VNI
5723  **/
5724 STATIC void i40e_fix_up_geneve_vni(
5725         struct i40e_aqc_cloud_filters_element_data *filters,
5726         u8 filter_count)
5727 {
5728         struct i40e_aqc_cloud_filters_element_data *f = filters;
5729         int i;
5730
5731         for (i = 0; i < filter_count; i++) {
5732                 u16 tnl_type;
5733                 u32 ti;
5734
5735                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5736                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5737                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5738                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5739                         ti = LE32_TO_CPU(f[i].tenant_id);
5740                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5741                 }
5742         }
5743 }
5744
5745 /**
5746  * i40e_aq_add_cloud_filters
5747  * @hw: pointer to the hardware structure
5748  * @seid: VSI seid to add cloud filters from
5749  * @filters: Buffer which contains the filters to be added
5750  * @filter_count: number of filters contained in the buffer
5751  *
5752  * Set the cloud filters for a given VSI.  The contents of the
5753  * i40e_aqc_cloud_filters_element_data are filled
5754  * in by the caller of the function.
5755  *
5756  **/
5757 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5758         u16 seid,
5759         struct i40e_aqc_cloud_filters_element_data *filters,
5760         u8 filter_count)
5761 {
5762         struct i40e_aq_desc desc;
5763         struct i40e_aqc_add_remove_cloud_filters *cmd =
5764         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5765         enum i40e_status_code status;
5766         u16 buff_len;
5767
5768         i40e_fill_default_direct_cmd_desc(&desc,
5769                                           i40e_aqc_opc_add_cloud_filters);
5770
5771         buff_len = filter_count * sizeof(*filters);
5772         desc.datalen = CPU_TO_LE16(buff_len);
5773         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5774         cmd->num_filters = filter_count;
5775         cmd->seid = CPU_TO_LE16(seid);
5776
5777         i40e_fix_up_geneve_vni(filters, filter_count);
5778
5779         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5780
5781         return status;
5782 }
5783
5784 /**
5785  * i40e_aq_add_cloud_filters_bb
5786  * @hw: pointer to the hardware structure
5787  * @seid: VSI seid to add cloud filters from
5788  * @filters: Buffer which contains the filters in big buffer to be added
5789  * @filter_count: number of filters contained in the buffer
5790  *
5791  * Set the cloud filters for a given VSI.  The contents of the
5792  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5793  * the function.
5794  *
5795  **/
5796 enum i40e_status_code
5797 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5798                              struct i40e_aqc_cloud_filters_element_bb *filters,
5799                              u8 filter_count)
5800 {
5801         struct i40e_aq_desc desc;
5802         struct i40e_aqc_add_remove_cloud_filters *cmd =
5803         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5804         enum i40e_status_code status;
5805         u16 buff_len;
5806         int i;
5807
5808         i40e_fill_default_direct_cmd_desc(&desc,
5809                                           i40e_aqc_opc_add_cloud_filters);
5810
5811         buff_len = filter_count * sizeof(*filters);
5812         desc.datalen = CPU_TO_LE16(buff_len);
5813         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5814         cmd->num_filters = filter_count;
5815         cmd->seid = CPU_TO_LE16(seid);
5816         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5817
5818         for (i = 0; i < filter_count; i++) {
5819                 u16 tnl_type;
5820                 u32 ti;
5821
5822                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5823                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5824                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5825
5826                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5827                  * one more byte further than normally used for Tenant ID in
5828                  * other tunnel types.
5829                  */
5830                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5831                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5832                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5833                 }
5834         }
5835
5836         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5837
5838         return status;
5839 }
5840
5841 /**
5842  * i40e_aq_rem_cloud_filters
5843  * @hw: pointer to the hardware structure
5844  * @seid: VSI seid to remove cloud filters from
5845  * @filters: Buffer which contains the filters to be removed
5846  * @filter_count: number of filters contained in the buffer
5847  *
5848  * Remove the cloud filters for a given VSI.  The contents of the
5849  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5850  * of the function.
5851  *
5852  **/
5853 enum i40e_status_code
5854 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5855                           struct i40e_aqc_cloud_filters_element_data *filters,
5856                           u8 filter_count)
5857 {
5858         struct i40e_aq_desc desc;
5859         struct i40e_aqc_add_remove_cloud_filters *cmd =
5860         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5861         enum i40e_status_code status;
5862         u16 buff_len;
5863
5864         i40e_fill_default_direct_cmd_desc(&desc,
5865                                           i40e_aqc_opc_remove_cloud_filters);
5866
5867         buff_len = filter_count * sizeof(*filters);
5868         desc.datalen = CPU_TO_LE16(buff_len);
5869         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5870         cmd->num_filters = filter_count;
5871         cmd->seid = CPU_TO_LE16(seid);
5872
5873         i40e_fix_up_geneve_vni(filters, filter_count);
5874
5875         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5876
5877         return status;
5878 }
5879
5880 /**
5881  * i40e_aq_rem_cloud_filters_bb
5882  * @hw: pointer to the hardware structure
5883  * @seid: VSI seid to remove cloud filters from
5884  * @filters: Buffer which contains the filters in big buffer to be removed
5885  * @filter_count: number of filters contained in the buffer
5886  *
5887  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5888  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5889  * function.
5890  *
5891  **/
5892 enum i40e_status_code
5893 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5894                              struct i40e_aqc_cloud_filters_element_bb *filters,
5895                              u8 filter_count)
5896 {
5897         struct i40e_aq_desc desc;
5898         struct i40e_aqc_add_remove_cloud_filters *cmd =
5899         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5900         enum i40e_status_code status;
5901         u16 buff_len;
5902         int i;
5903
5904         i40e_fill_default_direct_cmd_desc(&desc,
5905                                           i40e_aqc_opc_remove_cloud_filters);
5906
5907         buff_len = filter_count * sizeof(*filters);
5908         desc.datalen = CPU_TO_LE16(buff_len);
5909         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5910         cmd->num_filters = filter_count;
5911         cmd->seid = CPU_TO_LE16(seid);
5912         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5913
5914         for (i = 0; i < filter_count; i++) {
5915                 u16 tnl_type;
5916                 u32 ti;
5917
5918                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5919                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5920                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5921
5922                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5923                  * one more byte further than normally used for Tenant ID in
5924                  * other tunnel types.
5925                  */
5926                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5927                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5928                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5929                 }
5930         }
5931
5932         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5933
5934         return status;
5935 }
5936
5937 /**
5938  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5939  * @hw: pointer to the hw struct
5940  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5941  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5942  *
5943  **/
5944 enum
5945 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5946         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5947         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5948 {
5949         struct i40e_aq_desc desc;
5950         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5951                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5952         enum i40e_status_code status = I40E_SUCCESS;
5953         int i = 0;
5954
5955         /* X722 doesn't support this command */
5956         if (hw->mac.type == I40E_MAC_X722)
5957                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5958
5959         /* need FW version greater than 6.00 */
5960         if (hw->aq.fw_maj_ver < 6)
5961                 return I40E_NOT_SUPPORTED;
5962
5963         i40e_fill_default_direct_cmd_desc(&desc,
5964                                           i40e_aqc_opc_replace_cloud_filters);
5965
5966         desc.datalen = CPU_TO_LE16(32);
5967         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5968         cmd->old_filter_type = filters->old_filter_type;
5969         cmd->new_filter_type = filters->new_filter_type;
5970         cmd->valid_flags = filters->valid_flags;
5971         cmd->tr_bit = filters->tr_bit;
5972         cmd->tr_bit2 = filters->tr_bit2;
5973
5974         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5975                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5976
5977         /* for get cloud filters command */
5978         for (i = 0; i < 32; i += 4) {
5979                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5980                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5981                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5982                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5983         }
5984
5985         return status;
5986 }
5987
5988
5989 /**
5990  * i40e_aq_alternate_write
5991  * @hw: pointer to the hardware structure
5992  * @reg_addr0: address of first dword to be read
5993  * @reg_val0: value to be written under 'reg_addr0'
5994  * @reg_addr1: address of second dword to be read
5995  * @reg_val1: value to be written under 'reg_addr1'
5996  *
5997  * Write one or two dwords to alternate structure. Fields are indicated
5998  * by 'reg_addr0' and 'reg_addr1' register numbers.
5999  *
6000  **/
6001 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6002                                 u32 reg_addr0, u32 reg_val0,
6003                                 u32 reg_addr1, u32 reg_val1)
6004 {
6005         struct i40e_aq_desc desc;
6006         struct i40e_aqc_alternate_write *cmd_resp =
6007                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6008         enum i40e_status_code status;
6009
6010         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6011         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6012         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6013         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6014         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6015
6016         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6017
6018         return status;
6019 }
6020
6021 /**
6022  * i40e_aq_alternate_write_indirect
6023  * @hw: pointer to the hardware structure
6024  * @addr: address of a first register to be modified
6025  * @dw_count: number of alternate structure fields to write
6026  * @buffer: pointer to the command buffer
6027  *
6028  * Write 'dw_count' dwords from 'buffer' to alternate structure
6029  * starting at 'addr'.
6030  *
6031  **/
6032 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6033                                 u32 addr, u32 dw_count, void *buffer)
6034 {
6035         struct i40e_aq_desc desc;
6036         struct i40e_aqc_alternate_ind_write *cmd_resp =
6037                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6038         enum i40e_status_code status;
6039
6040         if (buffer == NULL)
6041                 return I40E_ERR_PARAM;
6042
6043         /* Indirect command */
6044         i40e_fill_default_direct_cmd_desc(&desc,
6045                                          i40e_aqc_opc_alternate_write_indirect);
6046
6047         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6048         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6049         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6050                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6051
6052         cmd_resp->address = CPU_TO_LE32(addr);
6053         cmd_resp->length = CPU_TO_LE32(dw_count);
6054
6055         status = i40e_asq_send_command(hw, &desc, buffer,
6056                                        I40E_LO_DWORD(4*dw_count), NULL);
6057
6058         return status;
6059 }
6060
6061 /**
6062  * i40e_aq_alternate_read
6063  * @hw: pointer to the hardware structure
6064  * @reg_addr0: address of first dword to be read
6065  * @reg_val0: pointer for data read from 'reg_addr0'
6066  * @reg_addr1: address of second dword to be read
6067  * @reg_val1: pointer for data read from 'reg_addr1'
6068  *
6069  * Read one or two dwords from alternate structure. Fields are indicated
6070  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6071  * is not passed then only register at 'reg_addr0' is read.
6072  *
6073  **/
6074 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6075                                 u32 reg_addr0, u32 *reg_val0,
6076                                 u32 reg_addr1, u32 *reg_val1)
6077 {
6078         struct i40e_aq_desc desc;
6079         struct i40e_aqc_alternate_write *cmd_resp =
6080                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6081         enum i40e_status_code status;
6082
6083         if (reg_val0 == NULL)
6084                 return I40E_ERR_PARAM;
6085
6086         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6087         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6088         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6089
6090         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6091
6092         if (status == I40E_SUCCESS) {
6093                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6094
6095                 if (reg_val1 != NULL)
6096                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6097         }
6098
6099         return status;
6100 }
6101
6102 /**
6103  * i40e_aq_alternate_read_indirect
6104  * @hw: pointer to the hardware structure
6105  * @addr: address of the alternate structure field
6106  * @dw_count: number of alternate structure fields to read
6107  * @buffer: pointer to the command buffer
6108  *
6109  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6110  * place them in 'buffer'. The buffer should be allocated by caller.
6111  *
6112  **/
6113 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6114                                 u32 addr, u32 dw_count, void *buffer)
6115 {
6116         struct i40e_aq_desc desc;
6117         struct i40e_aqc_alternate_ind_write *cmd_resp =
6118                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6119         enum i40e_status_code status;
6120
6121         if (buffer == NULL)
6122                 return I40E_ERR_PARAM;
6123
6124         /* Indirect command */
6125         i40e_fill_default_direct_cmd_desc(&desc,
6126                 i40e_aqc_opc_alternate_read_indirect);
6127
6128         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6129         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6130         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6131                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6132
6133         cmd_resp->address = CPU_TO_LE32(addr);
6134         cmd_resp->length = CPU_TO_LE32(dw_count);
6135
6136         status = i40e_asq_send_command(hw, &desc, buffer,
6137                                        I40E_LO_DWORD(4*dw_count), NULL);
6138
6139         return status;
6140 }
6141
6142 /**
6143  *  i40e_aq_alternate_clear
6144  *  @hw: pointer to the HW structure.
6145  *
6146  *  Clear the alternate structures of the port from which the function
6147  *  is called.
6148  *
6149  **/
6150 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6151 {
6152         struct i40e_aq_desc desc;
6153         enum i40e_status_code status;
6154
6155         i40e_fill_default_direct_cmd_desc(&desc,
6156                                           i40e_aqc_opc_alternate_clear_port);
6157
6158         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6159
6160         return status;
6161 }
6162
6163 /**
6164  *  i40e_aq_alternate_write_done
6165  *  @hw: pointer to the HW structure.
6166  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6167  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6168  *
6169  *  Indicates to the FW that alternate structures have been changed.
6170  *
6171  **/
6172 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6173                 u8 bios_mode, bool *reset_needed)
6174 {
6175         struct i40e_aq_desc desc;
6176         struct i40e_aqc_alternate_write_done *cmd =
6177                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6178         enum i40e_status_code status;
6179
6180         if (reset_needed == NULL)
6181                 return I40E_ERR_PARAM;
6182
6183         i40e_fill_default_direct_cmd_desc(&desc,
6184                                           i40e_aqc_opc_alternate_write_done);
6185
6186         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6187
6188         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6189         if (!status && reset_needed)
6190                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6191                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6192
6193         return status;
6194 }
6195
6196 /**
6197  *  i40e_aq_set_oem_mode
6198  *  @hw: pointer to the HW structure.
6199  *  @oem_mode: the OEM mode to be used
6200  *
6201  *  Sets the device to a specific operating mode. Currently the only supported
6202  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6203  *
6204  **/
6205 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6206                 u8 oem_mode)
6207 {
6208         struct i40e_aq_desc desc;
6209         struct i40e_aqc_alternate_write_done *cmd =
6210                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6211         enum i40e_status_code status;
6212
6213         i40e_fill_default_direct_cmd_desc(&desc,
6214                                           i40e_aqc_opc_alternate_set_mode);
6215
6216         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6217
6218         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6219
6220         return status;
6221 }
6222
6223 /**
6224  * i40e_aq_resume_port_tx
6225  * @hw: pointer to the hardware structure
6226  * @cmd_details: pointer to command details structure or NULL
6227  *
6228  * Resume port's Tx traffic
6229  **/
6230 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6231                                 struct i40e_asq_cmd_details *cmd_details)
6232 {
6233         struct i40e_aq_desc desc;
6234         enum i40e_status_code status;
6235
6236         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6237
6238         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6239
6240         return status;
6241 }
6242
6243 /**
6244  * i40e_set_pci_config_data - store PCI bus info
6245  * @hw: pointer to hardware structure
6246  * @link_status: the link status word from PCI config space
6247  *
6248  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6249  **/
6250 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6251 {
6252         hw->bus.type = i40e_bus_type_pci_express;
6253
6254         switch (link_status & I40E_PCI_LINK_WIDTH) {
6255         case I40E_PCI_LINK_WIDTH_1:
6256                 hw->bus.width = i40e_bus_width_pcie_x1;
6257                 break;
6258         case I40E_PCI_LINK_WIDTH_2:
6259                 hw->bus.width = i40e_bus_width_pcie_x2;
6260                 break;
6261         case I40E_PCI_LINK_WIDTH_4:
6262                 hw->bus.width = i40e_bus_width_pcie_x4;
6263                 break;
6264         case I40E_PCI_LINK_WIDTH_8:
6265                 hw->bus.width = i40e_bus_width_pcie_x8;
6266                 break;
6267         default:
6268                 hw->bus.width = i40e_bus_width_unknown;
6269                 break;
6270         }
6271
6272         switch (link_status & I40E_PCI_LINK_SPEED) {
6273         case I40E_PCI_LINK_SPEED_2500:
6274                 hw->bus.speed = i40e_bus_speed_2500;
6275                 break;
6276         case I40E_PCI_LINK_SPEED_5000:
6277                 hw->bus.speed = i40e_bus_speed_5000;
6278                 break;
6279         case I40E_PCI_LINK_SPEED_8000:
6280                 hw->bus.speed = i40e_bus_speed_8000;
6281                 break;
6282         default:
6283                 hw->bus.speed = i40e_bus_speed_unknown;
6284                 break;
6285         }
6286 }
6287
6288 /**
6289  * i40e_aq_debug_dump
6290  * @hw: pointer to the hardware structure
6291  * @cluster_id: specific cluster to dump
6292  * @table_id: table id within cluster
6293  * @start_index: index of line in the block to read
6294  * @buff_size: dump buffer size
6295  * @buff: dump buffer
6296  * @ret_buff_size: actual buffer size returned
6297  * @ret_next_table: next block to read
6298  * @ret_next_index: next index to read
6299  * @cmd_details: pointer to command details structure or NULL
6300  *
6301  * Dump internal FW/HW data for debug purposes.
6302  *
6303  **/
6304 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6305                                 u8 table_id, u32 start_index, u16 buff_size,
6306                                 void *buff, u16 *ret_buff_size,
6307                                 u8 *ret_next_table, u32 *ret_next_index,
6308                                 struct i40e_asq_cmd_details *cmd_details)
6309 {
6310         struct i40e_aq_desc desc;
6311         struct i40e_aqc_debug_dump_internals *cmd =
6312                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6313         struct i40e_aqc_debug_dump_internals *resp =
6314                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6315         enum i40e_status_code status;
6316
6317         if (buff_size == 0 || !buff)
6318                 return I40E_ERR_PARAM;
6319
6320         i40e_fill_default_direct_cmd_desc(&desc,
6321                                           i40e_aqc_opc_debug_dump_internals);
6322         /* Indirect Command */
6323         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6324         if (buff_size > I40E_AQ_LARGE_BUF)
6325                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6326
6327         cmd->cluster_id = cluster_id;
6328         cmd->table_id = table_id;
6329         cmd->idx = CPU_TO_LE32(start_index);
6330
6331         desc.datalen = CPU_TO_LE16(buff_size);
6332
6333         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6334         if (!status) {
6335                 if (ret_buff_size != NULL)
6336                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6337                 if (ret_next_table != NULL)
6338                         *ret_next_table = resp->table_id;
6339                 if (ret_next_index != NULL)
6340                         *ret_next_index = LE32_TO_CPU(resp->idx);
6341         }
6342
6343         return status;
6344 }
6345
6346
6347 /**
6348  * i40e_enable_eee
6349  * @hw: pointer to the hardware structure
6350  * @enable: state of Energy Efficient Ethernet mode to be set
6351  *
6352  * Enables or disables Energy Efficient Ethernet (EEE) mode
6353  * accordingly to @enable parameter.
6354  **/
6355 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6356 {
6357         struct i40e_aq_get_phy_abilities_resp abilities;
6358         struct i40e_aq_set_phy_config config;
6359         enum i40e_status_code status;
6360         __le16 eee_capability;
6361
6362         /* Get initial PHY capabilities */
6363         status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6364                                               NULL);
6365         if (status)
6366                 goto err;
6367
6368         /* Check whether NIC configuration is compatible with Energy Efficient
6369          * Ethernet (EEE) mode.
6370          */
6371         if (abilities.eee_capability == 0) {
6372                 status = I40E_ERR_CONFIG;
6373                 goto err;
6374         }
6375
6376         /* Cache initial EEE capability */
6377         eee_capability = abilities.eee_capability;
6378
6379         /* Get current configuration */
6380         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6381                                               NULL);
6382         if (status)
6383                 goto err;
6384
6385         /* Cache current configuration */
6386         config.phy_type = abilities.phy_type;
6387         config.link_speed = abilities.link_speed;
6388         config.abilities = abilities.abilities |
6389                            I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6390         config.eeer = abilities.eeer_val;
6391         config.low_power_ctrl = abilities.d3_lpan;
6392         config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6393                             I40E_AQ_PHY_FEC_CONFIG_MASK;
6394
6395         /* Set desired EEE state */
6396         if (enable) {
6397                 config.eee_capability = eee_capability;
6398                 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6399         } else {
6400                 config.eee_capability = 0;
6401                 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6402         }
6403
6404         /* Save modified config */
6405         status = i40e_aq_set_phy_config(hw, &config, NULL);
6406 err:
6407         return status;
6408 }
6409
6410 /**
6411  * i40e_read_bw_from_alt_ram
6412  * @hw: pointer to the hardware structure
6413  * @max_bw: pointer for max_bw read
6414  * @min_bw: pointer for min_bw read
6415  * @min_valid: pointer for bool that is true if min_bw is a valid value
6416  * @max_valid: pointer for bool that is true if max_bw is a valid value
6417  *
6418  * Read bw from the alternate ram for the given pf
6419  **/
6420 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6421                                         u32 *max_bw, u32 *min_bw,
6422                                         bool *min_valid, bool *max_valid)
6423 {
6424         enum i40e_status_code status;
6425         u32 max_bw_addr, min_bw_addr;
6426
6427         /* Calculate the address of the min/max bw registers */
6428         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6429                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6430                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6431         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6432                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6433                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6434
6435         /* Read the bandwidths from alt ram */
6436         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6437                                         min_bw_addr, min_bw);
6438
6439         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6440                 *min_valid = true;
6441         else
6442                 *min_valid = false;
6443
6444         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6445                 *max_valid = true;
6446         else
6447                 *max_valid = false;
6448
6449         return status;
6450 }
6451
6452 /**
6453  * i40e_aq_configure_partition_bw
6454  * @hw: pointer to the hardware structure
6455  * @bw_data: Buffer holding valid pfs and bw limits
6456  * @cmd_details: pointer to command details
6457  *
6458  * Configure partitions guaranteed/max bw
6459  **/
6460 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6461                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6462                         struct i40e_asq_cmd_details *cmd_details)
6463 {
6464         enum i40e_status_code status;
6465         struct i40e_aq_desc desc;
6466         u16 bwd_size = sizeof(*bw_data);
6467
6468         i40e_fill_default_direct_cmd_desc(&desc,
6469                                 i40e_aqc_opc_configure_partition_bw);
6470
6471         /* Indirect command */
6472         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6473         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6474
6475         desc.datalen = CPU_TO_LE16(bwd_size);
6476
6477         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6478
6479         return status;
6480 }
6481
6482 /**
6483  * i40e_read_phy_register_clause22
6484  * @hw: pointer to the HW structure
6485  * @reg: register address in the page
6486  * @phy_addr: PHY address on MDIO interface
6487  * @value: PHY register value
6488  *
6489  * Reads specified PHY register value
6490  **/
6491 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6492                                         u16 reg, u8 phy_addr, u16 *value)
6493 {
6494         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6495         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6496         u32 command = 0;
6497         u16 retry = 1000;
6498
6499         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6500                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6501                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6502                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6503                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6504         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6505         do {
6506                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6507                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6508                         status = I40E_SUCCESS;
6509                         break;
6510                 }
6511                 i40e_usec_delay(10);
6512                 retry--;
6513         } while (retry);
6514
6515         if (status) {
6516                 i40e_debug(hw, I40E_DEBUG_PHY,
6517                            "PHY: Can't write command to external PHY.\n");
6518         } else {
6519                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6520                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6521                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6522         }
6523
6524         return status;
6525 }
6526
6527 /**
6528  * i40e_write_phy_register_clause22
6529  * @hw: pointer to the HW structure
6530  * @reg: register address in the page
6531  * @phy_addr: PHY address on MDIO interface
6532  * @value: PHY register value
6533  *
6534  * Writes specified PHY register value
6535  **/
6536 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6537                                         u16 reg, u8 phy_addr, u16 value)
6538 {
6539         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6540         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6541         u32 command  = 0;
6542         u16 retry = 1000;
6543
6544         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6545         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6546
6547         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6548                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6549                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6550                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6551                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6552
6553         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6554         do {
6555                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6556                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6557                         status = I40E_SUCCESS;
6558                         break;
6559                 }
6560                 i40e_usec_delay(10);
6561                 retry--;
6562         } while (retry);
6563
6564         return status;
6565 }
6566
6567 /**
6568  * i40e_read_phy_register_clause45
6569  * @hw: pointer to the HW structure
6570  * @page: registers page number
6571  * @reg: register address in the page
6572  * @phy_addr: PHY address on MDIO interface
6573  * @value: PHY register value
6574  *
6575  * Reads specified PHY register value
6576  **/
6577 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6578                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6579 {
6580         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6581         u32 command  = 0;
6582         u16 retry = 1000;
6583         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6584
6585         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6586                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6587                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6588                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6589                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6590                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6591                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6592         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6593         do {
6594                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6595                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6596                         status = I40E_SUCCESS;
6597                         break;
6598                 }
6599                 i40e_usec_delay(10);
6600                 retry--;
6601         } while (retry);
6602
6603         if (status) {
6604                 i40e_debug(hw, I40E_DEBUG_PHY,
6605                            "PHY: Can't write command to external PHY.\n");
6606                 goto phy_read_end;
6607         }
6608
6609         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6610                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6611                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6612                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6613                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6614                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6615         status = I40E_ERR_TIMEOUT;
6616         retry = 1000;
6617         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6618         do {
6619                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6620                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6621                         status = I40E_SUCCESS;
6622                         break;
6623                 }
6624                 i40e_usec_delay(10);
6625                 retry--;
6626         } while (retry);
6627
6628         if (!status) {
6629                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6630                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6631                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6632         } else {
6633                 i40e_debug(hw, I40E_DEBUG_PHY,
6634                            "PHY: Can't read register value from external PHY.\n");
6635         }
6636
6637 phy_read_end:
6638         return status;
6639 }
6640
6641 /**
6642  * i40e_write_phy_register_clause45
6643  * @hw: pointer to the HW structure
6644  * @page: registers page number
6645  * @reg: register address in the page
6646  * @phy_addr: PHY address on MDIO interface
6647  * @value: PHY register value
6648  *
6649  * Writes value to specified PHY register
6650  **/
6651 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6652                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6653 {
6654         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6655         u32 command  = 0;
6656         u16 retry = 1000;
6657         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6658
6659         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6660                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6661                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6662                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6663                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6664                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6665                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6666         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6667         do {
6668                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6669                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6670                         status = I40E_SUCCESS;
6671                         break;
6672                 }
6673                 i40e_usec_delay(10);
6674                 retry--;
6675         } while (retry);
6676         if (status) {
6677                 i40e_debug(hw, I40E_DEBUG_PHY,
6678                            "PHY: Can't write command to external PHY.\n");
6679                 goto phy_write_end;
6680         }
6681
6682         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6683         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6684
6685         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6686                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6687                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6688                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6689                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6690                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6691         status = I40E_ERR_TIMEOUT;
6692         retry = 1000;
6693         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6694         do {
6695                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6696                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6697                         status = I40E_SUCCESS;
6698                         break;
6699                 }
6700                 i40e_usec_delay(10);
6701                 retry--;
6702         } while (retry);
6703
6704 phy_write_end:
6705         return status;
6706 }
6707
6708 /**
6709  * i40e_write_phy_register
6710  * @hw: pointer to the HW structure
6711  * @page: registers page number
6712  * @reg: register address in the page
6713  * @phy_addr: PHY address on MDIO interface
6714  * @value: PHY register value
6715  *
6716  * Writes value to specified PHY register
6717  **/
6718 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6719                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6720 {
6721         enum i40e_status_code status;
6722
6723         switch (hw->device_id) {
6724         case I40E_DEV_ID_1G_BASE_T_X722:
6725                 status = i40e_write_phy_register_clause22(hw,
6726                         reg, phy_addr, value);
6727                 break;
6728         case I40E_DEV_ID_10G_BASE_T:
6729         case I40E_DEV_ID_10G_BASE_T4:
6730         case I40E_DEV_ID_10G_BASE_T_BC:
6731         case I40E_DEV_ID_10G_BASE_T_X722:
6732         case I40E_DEV_ID_25G_B:
6733         case I40E_DEV_ID_25G_SFP28:
6734                 status = i40e_write_phy_register_clause45(hw,
6735                         page, reg, phy_addr, value);
6736                 break;
6737         default:
6738                 status = I40E_ERR_UNKNOWN_PHY;
6739                 break;
6740         }
6741
6742         return status;
6743 }
6744
6745 /**
6746  * i40e_read_phy_register
6747  * @hw: pointer to the HW structure
6748  * @page: registers page number
6749  * @reg: register address in the page
6750  * @phy_addr: PHY address on MDIO interface
6751  * @value: PHY register value
6752  *
6753  * Reads specified PHY register value
6754  **/
6755 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6756                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6757 {
6758         enum i40e_status_code status;
6759
6760         switch (hw->device_id) {
6761         case I40E_DEV_ID_1G_BASE_T_X722:
6762                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6763                                                          value);
6764                 break;
6765         case I40E_DEV_ID_10G_BASE_T:
6766         case I40E_DEV_ID_10G_BASE_T4:
6767         case I40E_DEV_ID_10G_BASE_T_X722:
6768         case I40E_DEV_ID_25G_B:
6769         case I40E_DEV_ID_25G_SFP28:
6770                 status = i40e_read_phy_register_clause45(hw, page, reg,
6771                                                          phy_addr, value);
6772                 break;
6773         default:
6774                 status = I40E_ERR_UNKNOWN_PHY;
6775                 break;
6776         }
6777
6778         return status;
6779 }
6780
6781 /**
6782  * i40e_get_phy_address
6783  * @hw: pointer to the HW structure
6784  * @dev_num: PHY port num that address we want
6785  *
6786  * Gets PHY address for current port
6787  **/
6788 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6789 {
6790         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6791         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6792
6793         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6794 }
6795
6796 /**
6797  * i40e_blink_phy_led
6798  * @hw: pointer to the HW structure
6799  * @time: time how long led will blinks in secs
6800  * @interval: gap between LED on and off in msecs
6801  *
6802  * Blinks PHY link LED
6803  **/
6804 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6805                                               u32 time, u32 interval)
6806 {
6807         enum i40e_status_code status = I40E_SUCCESS;
6808         u32 i;
6809         u16 led_ctl = 0;
6810         u16 gpio_led_port;
6811         u16 led_reg;
6812         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6813         u8 phy_addr = 0;
6814         u8 port_num;
6815
6816         i = rd32(hw, I40E_PFGEN_PORTNUM);
6817         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6818         phy_addr = i40e_get_phy_address(hw, port_num);
6819
6820         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6821              led_addr++) {
6822                 status = i40e_read_phy_register_clause45(hw,
6823                                                          I40E_PHY_COM_REG_PAGE,
6824                                                          led_addr, phy_addr,
6825                                                          &led_reg);
6826                 if (status)
6827                         goto phy_blinking_end;
6828                 led_ctl = led_reg;
6829                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6830                         led_reg = 0;
6831                         status = i40e_write_phy_register_clause45(hw,
6832                                                          I40E_PHY_COM_REG_PAGE,
6833                                                          led_addr, phy_addr,
6834                                                          led_reg);
6835                         if (status)
6836                                 goto phy_blinking_end;
6837                         break;
6838                 }
6839         }
6840
6841         if (time > 0 && interval > 0) {
6842                 for (i = 0; i < time * 1000; i += interval) {
6843                         status = i40e_read_phy_register_clause45(hw,
6844                                                 I40E_PHY_COM_REG_PAGE,
6845                                                 led_addr, phy_addr, &led_reg);
6846                         if (status)
6847                                 goto restore_config;
6848                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6849                                 led_reg = 0;
6850                         else
6851                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6852                         status = i40e_write_phy_register_clause45(hw,
6853                                                 I40E_PHY_COM_REG_PAGE,
6854                                                 led_addr, phy_addr, led_reg);
6855                         if (status)
6856                                 goto restore_config;
6857                         i40e_msec_delay(interval);
6858                 }
6859         }
6860
6861 restore_config:
6862         status = i40e_write_phy_register_clause45(hw,
6863                                                   I40E_PHY_COM_REG_PAGE,
6864                                                   led_addr, phy_addr, led_ctl);
6865
6866 phy_blinking_end:
6867         return status;
6868 }
6869
6870 /**
6871  * i40e_led_get_reg - read LED register
6872  * @hw: pointer to the HW structure
6873  * @led_addr: LED register address
6874  * @reg_val: read register value
6875  **/
6876 enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6877                                        u32 *reg_val)
6878 {
6879         enum i40e_status_code status;
6880         u8 phy_addr = 0;
6881
6882         *reg_val = 0;
6883         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6884                 status = i40e_aq_get_phy_register(hw,
6885                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6886                                                 I40E_PHY_COM_REG_PAGE, true,
6887                                                 I40E_PHY_LED_PROV_REG_1,
6888                                                 reg_val, NULL);
6889         } else {
6890                 phy_addr = i40e_get_phy_address(hw, hw->port);
6891                 status = i40e_read_phy_register_clause45(hw,
6892                                                          I40E_PHY_COM_REG_PAGE,
6893                                                          led_addr, phy_addr,
6894                                                          (u16 *)reg_val);
6895         }
6896         return status;
6897 }
6898
6899 /**
6900  * i40e_led_set_reg - write LED register
6901  * @hw: pointer to the HW structure
6902  * @led_addr: LED register address
6903  * @reg_val: register value to write
6904  **/
6905 enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6906                                        u32 reg_val)
6907 {
6908         enum i40e_status_code status;
6909         u8 phy_addr = 0;
6910
6911         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6912                 status = i40e_aq_set_phy_register(hw,
6913                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6914                                                 I40E_PHY_COM_REG_PAGE, true,
6915                                                 I40E_PHY_LED_PROV_REG_1,
6916                                                 reg_val, NULL);
6917         } else {
6918                 phy_addr = i40e_get_phy_address(hw, hw->port);
6919                 status = i40e_write_phy_register_clause45(hw,
6920                                                           I40E_PHY_COM_REG_PAGE,
6921                                                           led_addr, phy_addr,
6922                                                           (u16)reg_val);
6923         }
6924
6925         return status;
6926 }
6927
6928 /**
6929  * i40e_led_get_phy - return current on/off mode
6930  * @hw: pointer to the hw struct
6931  * @led_addr: address of led register to use
6932  * @val: original value of register to use
6933  *
6934  **/
6935 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6936                                        u16 *val)
6937 {
6938         enum i40e_status_code status = I40E_SUCCESS;
6939         u16 gpio_led_port;
6940         u32 reg_val_aq;
6941         u16 temp_addr;
6942         u8 phy_addr = 0;
6943         u16 reg_val;
6944
6945         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6946                 status = i40e_aq_get_phy_register(hw,
6947                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6948                                                 I40E_PHY_COM_REG_PAGE, true,
6949                                                 I40E_PHY_LED_PROV_REG_1,
6950                                                 &reg_val_aq, NULL);
6951                 if (status == I40E_SUCCESS)
6952                         *val = (u16)reg_val_aq;
6953                 return status;
6954         }
6955         temp_addr = I40E_PHY_LED_PROV_REG_1;
6956         phy_addr = i40e_get_phy_address(hw, hw->port);
6957         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6958              temp_addr++) {
6959                 status = i40e_read_phy_register_clause45(hw,
6960                                                          I40E_PHY_COM_REG_PAGE,
6961                                                          temp_addr, phy_addr,
6962                                                          &reg_val);
6963                 if (status)
6964                         return status;
6965                 *val = reg_val;
6966                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6967                         *led_addr = temp_addr;
6968                         break;
6969                 }
6970         }
6971         return status;
6972 }
6973
6974 /**
6975  * i40e_led_set_phy
6976  * @hw: pointer to the HW structure
6977  * @on: true or false
6978  * @led_addr: address of led register to use
6979  * @mode: original val plus bit for set or ignore
6980  *
6981  * Set led's on or off when controlled by the PHY
6982  *
6983  **/
6984 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6985                                        u16 led_addr, u32 mode)
6986 {
6987         enum i40e_status_code status = I40E_SUCCESS;
6988         u32 led_ctl = 0;
6989         u32 led_reg = 0;
6990
6991         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6992         if (status)
6993                 return status;
6994         led_ctl = led_reg;
6995         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6996                 led_reg = 0;
6997                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6998                 if (status)
6999                         return status;
7000         }
7001         status = i40e_led_get_reg(hw, led_addr, &led_reg);
7002         if (status)
7003                 goto restore_config;
7004         if (on)
7005                 led_reg = I40E_PHY_LED_MANUAL_ON;
7006         else
7007                 led_reg = 0;
7008         status = i40e_led_set_reg(hw, led_addr, led_reg);
7009         if (status)
7010                 goto restore_config;
7011         if (mode & I40E_PHY_LED_MODE_ORIG) {
7012                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
7013                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
7014         }
7015         return status;
7016
7017 restore_config:
7018         status = i40e_led_set_reg(hw, led_addr, led_ctl);
7019         return status;
7020 }
7021 #endif /* PF_DRIVER */
7022 /**
7023  * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
7024  * @hw: pointer to the hw struct
7025  * @stat: pointer to structure with status of rx and tx lpi
7026  *
7027  * Read LPI state directly from external PHY register or from MAC
7028  * register, depending on device ID and current link speed.
7029  */
7030 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
7031                                               struct i40e_hw_port_stats *stat)
7032 {
7033         enum i40e_status_code ret = I40E_SUCCESS;
7034         u32 val;
7035
7036         stat->rx_lpi_status = 0;
7037         stat->tx_lpi_status = 0;
7038
7039         if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7040             (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7041              hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
7042                 ret = i40e_aq_get_phy_register(hw,
7043                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7044                                                I40E_BCM_PHY_PCS_STATUS1_PAGE,
7045                                                true,
7046                                                I40E_BCM_PHY_PCS_STATUS1_REG,
7047                                                &val, NULL);
7048
7049                 if (ret != I40E_SUCCESS)
7050                         return ret;
7051
7052                 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7053                 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7054
7055                 return ret;
7056         }
7057
7058         val = rd32(hw, I40E_PRTPM_EEE_STAT);
7059         stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7060                                I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7061         stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7062                                I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7063
7064         return ret;
7065 }
7066
7067 /**
7068  * i40e_get_lpi_counters - read LPI counters from EEE statistics
7069  * @hw: pointer to the hw struct
7070  * @tx_counter: pointer to memory for TX LPI counter
7071  * @rx_counter: pointer to memory for RX LPI counter
7072  * @is_clear:   returns true if counters are clear after read
7073  *
7074  * Read Low Power Idle (LPI) mode counters from Energy Efficient
7075  * Ethernet (EEE) statistics.
7076  **/
7077 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7078                                             u32 *tx_counter, u32 *rx_counter,
7079                                             bool *is_clear)
7080 {
7081         /* only X710-T*L requires special handling of counters
7082          * for other devices we just read the MAC registers
7083          */
7084         if (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC &&
7085             hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7086                 enum i40e_status_code retval;
7087                 u32 cmd_status = 0;
7088
7089                 *is_clear = false;
7090                 retval = i40e_aq_run_phy_activity(hw,
7091                                 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7092                                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7093                                 &cmd_status, tx_counter, rx_counter, NULL);
7094
7095                 if (cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7096                         retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7097
7098                 return retval;
7099         }
7100
7101         *is_clear = true;
7102         *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7103         *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7104
7105         return I40E_SUCCESS;
7106 }
7107
7108 /**
7109  * i40e_get_lpi_duration - read LPI time duration from EEE statistics
7110  * @hw: pointer to the hw struct
7111  * @stat: pointer to structure with status of rx and tx lpi
7112  * @tx_duration: pointer to memory for TX LPI time duration
7113  * @rx_duration: pointer to memory for RX LPI time duration
7114  *
7115  * Read Low Power Idle (LPI) mode time duration from Energy Efficient
7116  * Ethernet (EEE) statistics.
7117  */
7118 enum i40e_status_code i40e_get_lpi_duration(struct i40e_hw *hw,
7119                                             struct i40e_hw_port_stats *stat,
7120                                             u64 *tx_duration, u64 *rx_duration)
7121 {
7122         u32 tx_time_dur, rx_time_dur;
7123         enum i40e_status_code retval;
7124         u32 cmd_status;
7125
7126         if (hw->device_id != I40E_DEV_ID_10G_BASE_T_BC)
7127                 return I40E_ERR_NOT_IMPLEMENTED;
7128
7129         retval = i40e_aq_run_phy_activity
7130                 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7131                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR,
7132                 &cmd_status, &tx_time_dur, &rx_time_dur, NULL);
7133
7134         if (retval)
7135                 return retval;
7136         if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7137             I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7138                 return I40E_ERR_ADMIN_QUEUE_ERROR;
7139
7140         if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB &&
7141             !tx_time_dur && !rx_time_dur &&
7142             stat->tx_lpi_status && stat->rx_lpi_status) {
7143                 retval = i40e_aq_run_phy_activity
7144                         (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7145                         I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR,
7146                         &cmd_status,
7147                         &tx_time_dur, &rx_time_dur, NULL);
7148
7149                 if (retval)
7150                         return retval;
7151                 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7152                     I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7153                         return I40E_ERR_ADMIN_QUEUE_ERROR;
7154                 tx_time_dur = 0;
7155                 rx_time_dur = 0;
7156         }
7157
7158         *tx_duration = tx_time_dur;
7159         *rx_duration = rx_time_dur;
7160
7161         return retval;
7162 }
7163
7164 /**
7165  * i40e_lpi_stat_update - update LPI counters with values relative to offset
7166  * @hw: pointer to the hw struct
7167  * @offset_loaded: flag indicating need of writing current value to offset
7168  * @tx_offset: pointer to offset of TX LPI counter
7169  * @tx_stat: pointer to value of TX LPI counter
7170  * @rx_offset: pointer to offset of RX LPI counter
7171  * @rx_stat: pointer to value of RX LPI counter
7172  *
7173  * Update Low Power Idle (LPI) mode counters while having regard to passed
7174  * offsets.
7175  **/
7176 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7177                                            bool offset_loaded, u64 *tx_offset,
7178                                            u64 *tx_stat, u64 *rx_offset,
7179                                            u64 *rx_stat)
7180 {
7181         enum i40e_status_code retval;
7182         u32 tx_counter, rx_counter;
7183         bool is_clear;
7184
7185         retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7186         if (retval)
7187                 goto err;
7188
7189         if (is_clear) {
7190                 *tx_stat += tx_counter;
7191                 *rx_stat += rx_counter;
7192         } else {
7193                 if (!offset_loaded) {
7194                         *tx_offset = tx_counter;
7195                         *rx_offset = rx_counter;
7196                 }
7197
7198                 *tx_stat = (tx_counter >= *tx_offset) ?
7199                         (u32)(tx_counter - *tx_offset) :
7200                         (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7201                 *rx_stat = (rx_counter >= *rx_offset) ?
7202                         (u32)(rx_counter - *rx_offset) :
7203                         (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7204         }
7205 err:
7206         return retval;
7207 }
7208
7209 /**
7210  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7211  * @hw: pointer to the hw struct
7212  * @reg_addr: register address
7213  * @reg_val: ptr to register value
7214  * @cmd_details: pointer to command details structure or NULL
7215  *
7216  * Use the firmware to read the Rx control register,
7217  * especially useful if the Rx unit is under heavy pressure
7218  **/
7219 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7220                                 u32 reg_addr, u32 *reg_val,
7221                                 struct i40e_asq_cmd_details *cmd_details)
7222 {
7223         struct i40e_aq_desc desc;
7224         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7225                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7226         enum i40e_status_code status;
7227
7228         if (reg_val == NULL)
7229                 return I40E_ERR_PARAM;
7230
7231         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7232
7233         cmd_resp->address = CPU_TO_LE32(reg_addr);
7234
7235         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7236
7237         if (status == I40E_SUCCESS)
7238                 *reg_val = LE32_TO_CPU(cmd_resp->value);
7239
7240         return status;
7241 }
7242
7243 /**
7244  * i40e_read_rx_ctl - read from an Rx control register
7245  * @hw: pointer to the hw struct
7246  * @reg_addr: register address
7247  **/
7248 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7249 {
7250         enum i40e_status_code status = I40E_SUCCESS;
7251         bool use_register;
7252         int retry = 5;
7253         u32 val = 0;
7254
7255         use_register = (((hw->aq.api_maj_ver == 1) &&
7256                         (hw->aq.api_min_ver < 5)) ||
7257                         (hw->mac.type == I40E_MAC_X722));
7258         if (!use_register) {
7259 do_retry:
7260                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7261                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7262                         i40e_msec_delay(1);
7263                         retry--;
7264                         goto do_retry;
7265                 }
7266         }
7267
7268         /* if the AQ access failed, try the old-fashioned way */
7269         if (status || use_register)
7270                 val = rd32(hw, reg_addr);
7271
7272         return val;
7273 }
7274
7275 /**
7276  * i40e_aq_rx_ctl_write_register
7277  * @hw: pointer to the hw struct
7278  * @reg_addr: register address
7279  * @reg_val: register value
7280  * @cmd_details: pointer to command details structure or NULL
7281  *
7282  * Use the firmware to write to an Rx control register,
7283  * especially useful if the Rx unit is under heavy pressure
7284  **/
7285 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7286                                 u32 reg_addr, u32 reg_val,
7287                                 struct i40e_asq_cmd_details *cmd_details)
7288 {
7289         struct i40e_aq_desc desc;
7290         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7291                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7292         enum i40e_status_code status;
7293
7294         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7295
7296         cmd->address = CPU_TO_LE32(reg_addr);
7297         cmd->value = CPU_TO_LE32(reg_val);
7298
7299         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7300
7301         return status;
7302 }
7303
7304 /**
7305  * i40e_write_rx_ctl - write to an Rx control register
7306  * @hw: pointer to the hw struct
7307  * @reg_addr: register address
7308  * @reg_val: register value
7309  **/
7310 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7311 {
7312         enum i40e_status_code status = I40E_SUCCESS;
7313         bool use_register;
7314         int retry = 5;
7315
7316         use_register = (((hw->aq.api_maj_ver == 1) &&
7317                         (hw->aq.api_min_ver < 5)) ||
7318                         (hw->mac.type == I40E_MAC_X722));
7319         if (!use_register) {
7320 do_retry:
7321                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7322                                                        reg_val, NULL);
7323                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7324                         i40e_msec_delay(1);
7325                         retry--;
7326                         goto do_retry;
7327                 }
7328         }
7329
7330         /* if the AQ access failed, try the old-fashioned way */
7331         if (status || use_register)
7332                 wr32(hw, reg_addr, reg_val);
7333 }
7334
7335 /**
7336  * i40e_mdio_if_number_selection - MDIO I/F number selection
7337  * @hw: pointer to the hw struct
7338  * @set_mdio: use MDIO I/F number specified by mdio_num
7339  * @mdio_num: MDIO I/F number
7340  * @cmd: pointer to PHY Register command structure
7341  **/
7342 static void
7343 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7344                               struct i40e_aqc_phy_register_access *cmd)
7345 {
7346         if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7347                 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7348                         cmd->cmd_flags |=
7349                                 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7350                                 ((mdio_num <<
7351                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7352                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7353                 else
7354                         i40e_debug(hw, I40E_DEBUG_PHY,
7355                                    "MDIO I/F number selection not supported by current FW version.\n");
7356         }
7357 }
7358
7359 /**
7360  * i40e_aq_set_phy_register_ext
7361  * @hw: pointer to the hw struct
7362  * @phy_select: select which phy should be accessed
7363  * @dev_addr: PHY device address
7364  * @page_change: enable auto page change
7365  * @set_mdio: use MDIO I/F number specified by mdio_num
7366  * @mdio_num: MDIO I/F number
7367  * @reg_addr: PHY register address
7368  * @reg_val: new register value
7369  * @cmd_details: pointer to command details structure or NULL
7370  *
7371  * Write the external PHY register.
7372  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7373  * may use simple wrapper i40e_aq_set_phy_register.
7374  **/
7375 enum i40e_status_code
7376 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7377                              u8 phy_select, u8 dev_addr, bool page_change,
7378                              bool set_mdio, u8 mdio_num,
7379                              u32 reg_addr, u32 reg_val,
7380                              struct i40e_asq_cmd_details *cmd_details)
7381 {
7382         struct i40e_aq_desc desc;
7383         struct i40e_aqc_phy_register_access *cmd =
7384                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7385         enum i40e_status_code status;
7386
7387         i40e_fill_default_direct_cmd_desc(&desc,
7388                                           i40e_aqc_opc_set_phy_register);
7389
7390         cmd->phy_interface = phy_select;
7391         cmd->dev_addres = dev_addr;
7392         cmd->reg_address = CPU_TO_LE32(reg_addr);
7393         cmd->reg_value = CPU_TO_LE32(reg_val);
7394
7395         if (!page_change)
7396                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7397
7398         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7399
7400         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7401
7402         return status;
7403 }
7404
7405 /**
7406  * i40e_aq_get_phy_register_ext
7407  * @hw: pointer to the hw struct
7408  * @phy_select: select which phy should be accessed
7409  * @dev_addr: PHY device address
7410  * @page_change: enable auto page change
7411  * @set_mdio: use MDIO I/F number specified by mdio_num
7412  * @mdio_num: MDIO I/F number
7413  * @reg_addr: PHY register address
7414  * @reg_val: read register value
7415  * @cmd_details: pointer to command details structure or NULL
7416  *
7417  * Read the external PHY register.
7418  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7419  * may use simple wrapper i40e_aq_get_phy_register.
7420  **/
7421 enum i40e_status_code
7422 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7423                              u8 phy_select, u8 dev_addr, bool page_change,
7424                              bool set_mdio, u8 mdio_num,
7425                              u32 reg_addr, u32 *reg_val,
7426                              struct i40e_asq_cmd_details *cmd_details)
7427 {
7428         struct i40e_aq_desc desc;
7429         struct i40e_aqc_phy_register_access *cmd =
7430                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7431         enum i40e_status_code status;
7432
7433         i40e_fill_default_direct_cmd_desc(&desc,
7434                                           i40e_aqc_opc_get_phy_register);
7435
7436         cmd->phy_interface = phy_select;
7437         cmd->dev_addres = dev_addr;
7438         cmd->reg_address = CPU_TO_LE32(reg_addr);
7439
7440         if (!page_change)
7441                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7442
7443         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7444
7445         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7446         if (!status)
7447                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7448
7449         return status;
7450 }
7451
7452 /**
7453  * i40e_aq_run_phy_activity
7454  * @hw: pointer to the hw struct
7455  * @activity_id: ID of DNL activity to run
7456  * @dnl_opcode: opcode passed to DNL script
7457  * @cmd_status: pointer to memory to write return value of DNL script
7458  * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7459  * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7460  * @cmd_details: pointer to command details structure or NULL
7461  *
7462  * Run DNL admin command.
7463  **/
7464 enum i40e_status_code
7465 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7466                          u32 *cmd_status, u32 *data0, u32 *data1,
7467                          struct i40e_asq_cmd_details *cmd_details)
7468 {
7469         struct i40e_aqc_run_phy_activity *cmd;
7470         enum i40e_status_code retval;
7471         struct i40e_aq_desc desc;
7472
7473         cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7474
7475         if (!cmd_status || !data0 || !data1) {
7476                 retval = I40E_ERR_PARAM;
7477                 goto err;
7478         }
7479
7480         i40e_fill_default_direct_cmd_desc(&desc,
7481                                           i40e_aqc_opc_run_phy_activity);
7482
7483         cmd->activity_id = CPU_TO_LE16(activity_id);
7484         cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7485
7486         retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7487         if (retval)
7488                 goto err;
7489
7490         *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7491         *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7492         *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7493 err:
7494         return retval;
7495 }
7496
7497 #ifdef VF_DRIVER
7498
7499 /**
7500  * i40e_aq_send_msg_to_pf
7501  * @hw: pointer to the hardware structure
7502  * @v_opcode: opcodes for VF-PF communication
7503  * @v_retval: return error code
7504  * @msg: pointer to the msg buffer
7505  * @msglen: msg length
7506  * @cmd_details: pointer to command details
7507  *
7508  * Send message to PF driver using admin queue. By default, this message
7509  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7510  * completion before returning.
7511  **/
7512 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7513                                 enum virtchnl_ops v_opcode,
7514                                 enum i40e_status_code v_retval,
7515                                 u8 *msg, u16 msglen,
7516                                 struct i40e_asq_cmd_details *cmd_details)
7517 {
7518         struct i40e_aq_desc desc;
7519         struct i40e_asq_cmd_details details;
7520         enum i40e_status_code status;
7521
7522         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7523         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7524         desc.cookie_high = CPU_TO_LE32(v_opcode);
7525         desc.cookie_low = CPU_TO_LE32(v_retval);
7526         if (msglen) {
7527                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7528                                                 | I40E_AQ_FLAG_RD));
7529                 if (msglen > I40E_AQ_LARGE_BUF)
7530                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7531                 desc.datalen = CPU_TO_LE16(msglen);
7532         }
7533         if (!cmd_details) {
7534                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7535                 details.async = true;
7536                 cmd_details = &details;
7537         }
7538         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7539                                        msglen, cmd_details);
7540         return status;
7541 }
7542
7543 /**
7544  * i40e_vf_parse_hw_config
7545  * @hw: pointer to the hardware structure
7546  * @msg: pointer to the virtual channel VF resource structure
7547  *
7548  * Given a VF resource message from the PF, populate the hw struct
7549  * with appropriate information.
7550  **/
7551 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7552                              struct virtchnl_vf_resource *msg)
7553 {
7554         struct virtchnl_vsi_resource *vsi_res;
7555         int i;
7556
7557         vsi_res = &msg->vsi_res[0];
7558
7559         hw->dev_caps.num_vsis = msg->num_vsis;
7560         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7561         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7562         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7563         hw->dev_caps.dcb = msg->vf_cap_flags &
7564                            VIRTCHNL_VF_OFFLOAD_L2;
7565         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7566                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7567         for (i = 0; i < msg->num_vsis; i++) {
7568                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7569                         i40e_memcpy(hw->mac.perm_addr,
7570                                     vsi_res->default_mac_addr,
7571                                     ETH_ALEN,
7572                                     I40E_NONDMA_TO_NONDMA);
7573                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7574                                     ETH_ALEN,
7575                                     I40E_NONDMA_TO_NONDMA);
7576                 }
7577                 vsi_res++;
7578         }
7579 }
7580
7581 /**
7582  * i40e_vf_reset
7583  * @hw: pointer to the hardware structure
7584  *
7585  * Send a VF_RESET message to the PF. Does not wait for response from PF
7586  * as none will be forthcoming. Immediately after calling this function,
7587  * the admin queue should be shut down and (optionally) reinitialized.
7588  **/
7589 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7590 {
7591         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7592                                       I40E_SUCCESS, NULL, 0, NULL);
7593 }
7594 #endif /* VF_DRIVER */
7595
7596 /**
7597  * i40e_aq_set_arp_proxy_config
7598  * @hw: pointer to the HW structure
7599  * @proxy_config: pointer to proxy config command table struct
7600  * @cmd_details: pointer to command details
7601  *
7602  * Set ARP offload parameters from pre-populated
7603  * i40e_aqc_arp_proxy_data struct
7604  **/
7605 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7606                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7607                                 struct i40e_asq_cmd_details *cmd_details)
7608 {
7609         struct i40e_aq_desc desc;
7610         enum i40e_status_code status;
7611
7612         if (!proxy_config)
7613                 return I40E_ERR_PARAM;
7614
7615         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7616
7617         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7618         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7619         desc.params.external.addr_high =
7620                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7621         desc.params.external.addr_low =
7622                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7623         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7624
7625         status = i40e_asq_send_command(hw, &desc, proxy_config,
7626                                        sizeof(struct i40e_aqc_arp_proxy_data),
7627                                        cmd_details);
7628
7629         return status;
7630 }
7631
7632 /**
7633  * i40e_aq_opc_set_ns_proxy_table_entry
7634  * @hw: pointer to the HW structure
7635  * @ns_proxy_table_entry: pointer to NS table entry command struct
7636  * @cmd_details: pointer to command details
7637  *
7638  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7639  * from pre-populated i40e_aqc_ns_proxy_data struct
7640  **/
7641 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7642                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7643                         struct i40e_asq_cmd_details *cmd_details)
7644 {
7645         struct i40e_aq_desc desc;
7646         enum i40e_status_code status;
7647
7648         if (!ns_proxy_table_entry)
7649                 return I40E_ERR_PARAM;
7650
7651         i40e_fill_default_direct_cmd_desc(&desc,
7652                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7653
7654         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7655         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7656         desc.params.external.addr_high =
7657                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7658         desc.params.external.addr_low =
7659                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7660         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7661
7662         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7663                                        sizeof(struct i40e_aqc_ns_proxy_data),
7664                                        cmd_details);
7665
7666         return status;
7667 }
7668
7669 /**
7670  * i40e_aq_set_clear_wol_filter
7671  * @hw: pointer to the hw struct
7672  * @filter_index: index of filter to modify (0-7)
7673  * @filter: buffer containing filter to be set
7674  * @set_filter: true to set filter, false to clear filter
7675  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7676  *              if false, pass through packets may cause wake-up
7677  * @filter_valid: true if filter action is valid
7678  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7679  * @cmd_details: pointer to command details structure or NULL
7680  *
7681  * Set or clear WoL filter for port attached to the PF
7682  **/
7683 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7684                                 u8 filter_index,
7685                                 struct i40e_aqc_set_wol_filter_data *filter,
7686                                 bool set_filter, bool no_wol_tco,
7687                                 bool filter_valid, bool no_wol_tco_valid,
7688                                 struct i40e_asq_cmd_details *cmd_details)
7689 {
7690         struct i40e_aq_desc desc;
7691         struct i40e_aqc_set_wol_filter *cmd =
7692                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7693         enum i40e_status_code status;
7694         u16 cmd_flags = 0;
7695         u16 valid_flags = 0;
7696         u16 buff_len = 0;
7697
7698         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7699
7700         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7701                 return  I40E_ERR_PARAM;
7702         cmd->filter_index = CPU_TO_LE16(filter_index);
7703
7704         if (set_filter) {
7705                 if (!filter)
7706                         return  I40E_ERR_PARAM;
7707
7708                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7709                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7710         }
7711
7712         if (no_wol_tco)
7713                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7714         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7715
7716         if (filter_valid)
7717                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7718         if (no_wol_tco_valid)
7719                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7720         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7721
7722         buff_len = sizeof(*filter);
7723         desc.datalen = CPU_TO_LE16(buff_len);
7724
7725         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7726         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7727
7728         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7729         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7730
7731         status = i40e_asq_send_command(hw, &desc, filter,
7732                                        buff_len, cmd_details);
7733
7734         return status;
7735 }
7736
7737 /**
7738  * i40e_aq_get_wake_event_reason
7739  * @hw: pointer to the hw struct
7740  * @wake_reason: return value, index of matching filter
7741  * @cmd_details: pointer to command details structure or NULL
7742  *
7743  * Get information for the reason of a Wake Up event
7744  **/
7745 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7746                                 u16 *wake_reason,
7747                                 struct i40e_asq_cmd_details *cmd_details)
7748 {
7749         struct i40e_aq_desc desc;
7750         struct i40e_aqc_get_wake_reason_completion *resp =
7751                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7752         enum i40e_status_code status;
7753
7754         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7755
7756         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7757
7758         if (status == I40E_SUCCESS)
7759                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7760
7761         return status;
7762 }
7763
7764 /**
7765 * i40e_aq_clear_all_wol_filters
7766 * @hw: pointer to the hw struct
7767 * @cmd_details: pointer to command details structure or NULL
7768 *
7769 * Get information for the reason of a Wake Up event
7770 **/
7771 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7772         struct i40e_asq_cmd_details *cmd_details)
7773 {
7774         struct i40e_aq_desc desc;
7775         enum i40e_status_code status;
7776
7777         i40e_fill_default_direct_cmd_desc(&desc,
7778                                           i40e_aqc_opc_clear_all_wol_filters);
7779
7780         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7781
7782         return status;
7783 }
7784
7785 /**
7786  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7787  * @hw: pointer to the hw struct
7788  * @buff: command buffer (size in bytes = buff_size)
7789  * @buff_size: buffer size in bytes
7790  * @track_id: package tracking id
7791  * @error_offset: returns error offset
7792  * @error_info: returns error information
7793  * @cmd_details: pointer to command details structure or NULL
7794  **/
7795 enum
7796 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7797                                    u16 buff_size, u32 track_id,
7798                                    u32 *error_offset, u32 *error_info,
7799                                    struct i40e_asq_cmd_details *cmd_details)
7800 {
7801         struct i40e_aq_desc desc;
7802         struct i40e_aqc_write_personalization_profile *cmd =
7803                 (struct i40e_aqc_write_personalization_profile *)
7804                 &desc.params.raw;
7805         struct i40e_aqc_write_ddp_resp *resp;
7806         enum i40e_status_code status;
7807
7808         i40e_fill_default_direct_cmd_desc(&desc,
7809                                   i40e_aqc_opc_write_personalization_profile);
7810
7811         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7812         if (buff_size > I40E_AQ_LARGE_BUF)
7813                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7814
7815         desc.datalen = CPU_TO_LE16(buff_size);
7816
7817         cmd->profile_track_id = CPU_TO_LE32(track_id);
7818
7819         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7820         if (!status) {
7821                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7822                 if (error_offset)
7823                         *error_offset = LE32_TO_CPU(resp->error_offset);
7824                 if (error_info)
7825                         *error_info = LE32_TO_CPU(resp->error_info);
7826         }
7827
7828         return status;
7829 }
7830
7831 /**
7832  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7833  * @hw: pointer to the hw struct
7834  * @buff: command buffer (size in bytes = buff_size)
7835  * @buff_size: buffer size in bytes
7836  * @flags: AdminQ command flags
7837  * @cmd_details: pointer to command details structure or NULL
7838  **/
7839 enum
7840 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7841                                       u16 buff_size, u8 flags,
7842                                       struct i40e_asq_cmd_details *cmd_details)
7843 {
7844         struct i40e_aq_desc desc;
7845         struct i40e_aqc_get_applied_profiles *cmd =
7846                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7847         enum i40e_status_code status;
7848
7849         i40e_fill_default_direct_cmd_desc(&desc,
7850                           i40e_aqc_opc_get_personalization_profile_list);
7851
7852         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7853         if (buff_size > I40E_AQ_LARGE_BUF)
7854                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7855         desc.datalen = CPU_TO_LE16(buff_size);
7856
7857         cmd->flags = flags;
7858
7859         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7860
7861         return status;
7862 }
7863
7864 /**
7865  * i40e_find_segment_in_package
7866  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7867  * @pkg_hdr: pointer to the package header to be searched
7868  *
7869  * This function searches a package file for a particular segment type. On
7870  * success it returns a pointer to the segment header, otherwise it will
7871  * return NULL.
7872  **/
7873 struct i40e_generic_seg_header *
7874 i40e_find_segment_in_package(u32 segment_type,
7875                              struct i40e_package_header *pkg_hdr)
7876 {
7877         struct i40e_generic_seg_header *segment;
7878         u32 i;
7879
7880         /* Search all package segments for the requested segment type */
7881         for (i = 0; i < pkg_hdr->segment_count; i++) {
7882                 segment =
7883                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7884                          pkg_hdr->segment_offset[i]);
7885
7886                 if (segment->type == segment_type)
7887                         return segment;
7888         }
7889
7890         return NULL;
7891 }
7892
7893 /* Get section table in profile */
7894 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7895         do {                                                            \
7896                 struct i40e_profile_segment *p = (profile);             \
7897                 u32 count;                                              \
7898                 u32 *nvm;                                               \
7899                 count = p->device_table_count;                          \
7900                 nvm = (u32 *)&p->device_table[count];                   \
7901                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7902         } while (0)
7903
7904 /* Get section header in profile */
7905 #define I40E_SECTION_HEADER(profile, offset)                            \
7906         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7907
7908 /**
7909  * i40e_find_section_in_profile
7910  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7911  * @profile: pointer to the i40e segment header to be searched
7912  *
7913  * This function searches i40e segment for a particular section type. On
7914  * success it returns a pointer to the section header, otherwise it will
7915  * return NULL.
7916  **/
7917 struct i40e_profile_section_header *
7918 i40e_find_section_in_profile(u32 section_type,
7919                              struct i40e_profile_segment *profile)
7920 {
7921         struct i40e_profile_section_header *sec;
7922         struct i40e_section_table *sec_tbl;
7923         u32 sec_off;
7924         u32 i;
7925
7926         if (profile->header.type != SEGMENT_TYPE_I40E)
7927                 return NULL;
7928
7929         I40E_SECTION_TABLE(profile, sec_tbl);
7930
7931         for (i = 0; i < sec_tbl->section_count; i++) {
7932                 sec_off = sec_tbl->section_offset[i];
7933                 sec = I40E_SECTION_HEADER(profile, sec_off);
7934                 if (sec->section.type == section_type)
7935                         return sec;
7936         }
7937
7938         return NULL;
7939 }
7940
7941 /**
7942  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7943  * @hw: pointer to the hw struct
7944  * @aq: command buffer containing all data to execute AQ
7945  **/
7946 STATIC enum
7947 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7948                                           struct i40e_profile_aq_section *aq)
7949 {
7950         enum i40e_status_code status;
7951         struct i40e_aq_desc desc;
7952         u8 *msg = NULL;
7953         u16 msglen;
7954
7955         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7956         desc.flags |= CPU_TO_LE16(aq->flags);
7957         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7958                     I40E_NONDMA_TO_NONDMA);
7959
7960         msglen = aq->datalen;
7961         if (msglen) {
7962                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7963                                                 I40E_AQ_FLAG_RD));
7964                 if (msglen > I40E_AQ_LARGE_BUF)
7965                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7966                 desc.datalen = CPU_TO_LE16(msglen);
7967                 msg = &aq->data[0];
7968         }
7969
7970         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7971
7972         if (status != I40E_SUCCESS) {
7973                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7974                            "unable to exec DDP AQ opcode %u, error %d\n",
7975                            aq->opcode, status);
7976                 return status;
7977         }
7978
7979         /* copy returned desc to aq_buf */
7980         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7981                     I40E_NONDMA_TO_NONDMA);
7982
7983         return I40E_SUCCESS;
7984 }
7985
7986 /**
7987  * i40e_validate_profile
7988  * @hw: pointer to the hardware structure
7989  * @profile: pointer to the profile segment of the package to be validated
7990  * @track_id: package tracking id
7991  * @rollback: flag if the profile is for rollback.
7992  *
7993  * Validates supported devices and profile's sections.
7994  */
7995 STATIC enum i40e_status_code
7996 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7997                       u32 track_id, bool rollback)
7998 {
7999         struct i40e_profile_section_header *sec = NULL;
8000         enum i40e_status_code status = I40E_SUCCESS;
8001         struct i40e_section_table *sec_tbl;
8002         u32 vendor_dev_id;
8003         u32 dev_cnt;
8004         u32 sec_off;
8005         u32 i;
8006
8007         if (track_id == I40E_DDP_TRACKID_INVALID) {
8008                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
8009                 return I40E_NOT_SUPPORTED;
8010         }
8011
8012         dev_cnt = profile->device_table_count;
8013         for (i = 0; i < dev_cnt; i++) {
8014                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
8015                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
8016                     hw->device_id == (vendor_dev_id & 0xFFFF))
8017                         break;
8018         }
8019         if (dev_cnt && (i == dev_cnt)) {
8020                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8021                            "Device doesn't support DDP\n");
8022                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
8023         }
8024
8025         I40E_SECTION_TABLE(profile, sec_tbl);
8026
8027         /* Validate sections types */
8028         for (i = 0; i < sec_tbl->section_count; i++) {
8029                 sec_off = sec_tbl->section_offset[i];
8030                 sec = I40E_SECTION_HEADER(profile, sec_off);
8031                 if (rollback) {
8032                         if (sec->section.type == SECTION_TYPE_MMIO ||
8033                             sec->section.type == SECTION_TYPE_AQ ||
8034                             sec->section.type == SECTION_TYPE_RB_AQ) {
8035                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8036                                            "Not a roll-back package\n");
8037                                 return I40E_NOT_SUPPORTED;
8038                         }
8039                 } else {
8040                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
8041                             sec->section.type == SECTION_TYPE_RB_MMIO) {
8042                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8043                                            "Not an original package\n");
8044                                 return I40E_NOT_SUPPORTED;
8045                         }
8046                 }
8047         }
8048
8049         return status;
8050 }
8051
8052 /**
8053  * i40e_write_profile
8054  * @hw: pointer to the hardware structure
8055  * @profile: pointer to the profile segment of the package to be downloaded
8056  * @track_id: package tracking id
8057  *
8058  * Handles the download of a complete package.
8059  */
8060 enum i40e_status_code
8061 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8062                    u32 track_id)
8063 {
8064         enum i40e_status_code status = I40E_SUCCESS;
8065         struct i40e_section_table *sec_tbl;
8066         struct i40e_profile_section_header *sec = NULL;
8067         struct i40e_profile_aq_section *ddp_aq;
8068         u32 section_size = 0;
8069         u32 offset = 0, info = 0;
8070         u32 sec_off;
8071         u32 i;
8072
8073         status = i40e_validate_profile(hw, profile, track_id, false);
8074         if (status)
8075                 return status;
8076
8077         I40E_SECTION_TABLE(profile, sec_tbl);
8078
8079         for (i = 0; i < sec_tbl->section_count; i++) {
8080                 sec_off = sec_tbl->section_offset[i];
8081                 sec = I40E_SECTION_HEADER(profile, sec_off);
8082                 /* Process generic admin command */
8083                 if (sec->section.type == SECTION_TYPE_AQ) {
8084                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
8085                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
8086                         if (status) {
8087                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8088                                            "Failed to execute aq: section %d, opcode %u\n",
8089                                            i, ddp_aq->opcode);
8090                                 break;
8091                         }
8092                         sec->section.type = SECTION_TYPE_RB_AQ;
8093                 }
8094
8095                 /* Skip any non-mmio sections */
8096                 if (sec->section.type != SECTION_TYPE_MMIO)
8097                         continue;
8098
8099                 section_size = sec->section.size +
8100                         sizeof(struct i40e_profile_section_header);
8101
8102                 /* Write MMIO section */
8103                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8104                                            track_id, &offset, &info, NULL);
8105                 if (status) {
8106                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8107                                    "Failed to write profile: section %d, offset %d, info %d\n",
8108                                    i, offset, info);
8109                         break;
8110                 }
8111         }
8112         return status;
8113 }
8114
8115 /**
8116  * i40e_rollback_profile
8117  * @hw: pointer to the hardware structure
8118  * @profile: pointer to the profile segment of the package to be removed
8119  * @track_id: package tracking id
8120  *
8121  * Rolls back previously loaded package.
8122  */
8123 enum i40e_status_code
8124 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8125                       u32 track_id)
8126 {
8127         struct i40e_profile_section_header *sec = NULL;
8128         enum i40e_status_code status = I40E_SUCCESS;
8129         struct i40e_section_table *sec_tbl;
8130         u32 offset = 0, info = 0;
8131         u32 section_size = 0;
8132         u32 sec_off;
8133         int i;
8134
8135         status = i40e_validate_profile(hw, profile, track_id, true);
8136         if (status)
8137                 return status;
8138
8139         I40E_SECTION_TABLE(profile, sec_tbl);
8140
8141         /* For rollback write sections in reverse */
8142         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8143                 sec_off = sec_tbl->section_offset[i];
8144                 sec = I40E_SECTION_HEADER(profile, sec_off);
8145
8146                 /* Skip any non-rollback sections */
8147                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8148                         continue;
8149
8150                 section_size = sec->section.size +
8151                         sizeof(struct i40e_profile_section_header);
8152
8153                 /* Write roll-back MMIO section */
8154                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8155                                            track_id, &offset, &info, NULL);
8156                 if (status) {
8157                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8158                                    "Failed to write profile: section %d, offset %d, info %d\n",
8159                                    i, offset, info);
8160                         break;
8161                 }
8162         }
8163         return status;
8164 }
8165
8166 /**
8167  * i40e_add_pinfo_to_list
8168  * @hw: pointer to the hardware structure
8169  * @profile: pointer to the profile segment of the package
8170  * @profile_info_sec: buffer for information section
8171  * @track_id: package tracking id
8172  *
8173  * Register a profile to the list of loaded profiles.
8174  */
8175 enum i40e_status_code
8176 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8177                        struct i40e_profile_segment *profile,
8178                        u8 *profile_info_sec, u32 track_id)
8179 {
8180         enum i40e_status_code status = I40E_SUCCESS;
8181         struct i40e_profile_section_header *sec = NULL;
8182         struct i40e_profile_info *pinfo;
8183         u32 offset = 0, info = 0;
8184
8185         sec = (struct i40e_profile_section_header *)profile_info_sec;
8186         sec->tbl_size = 1;
8187         sec->data_end = sizeof(struct i40e_profile_section_header) +
8188                         sizeof(struct i40e_profile_info);
8189         sec->section.type = SECTION_TYPE_INFO;
8190         sec->section.offset = sizeof(struct i40e_profile_section_header);
8191         sec->section.size = sizeof(struct i40e_profile_info);
8192         pinfo = (struct i40e_profile_info *)(profile_info_sec +
8193                                              sec->section.offset);
8194         pinfo->track_id = track_id;
8195         pinfo->version = profile->version;
8196         pinfo->op = I40E_DDP_ADD_TRACKID;
8197         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8198                     I40E_NONDMA_TO_NONDMA);
8199
8200         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8201                                    track_id, &offset, &info, NULL);
8202         return status;
8203 }