drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u8 *buf = (u8 *)buffer;
 334         u16 len;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         len = LE16_TO_CPU(aq_desc->datalen);
 341
 342         i40e_debug(hw, mask,
 343                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 344                    LE16_TO_CPU(aq_desc->opcode),
 345                    LE16_TO_CPU(aq_desc->flags),
 346                    LE16_TO_CPU(aq_desc->datalen),
 347                    LE16_TO_CPU(aq_desc->retval));
 348         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 349                    LE32_TO_CPU(aq_desc->cookie_high),
 350                    LE32_TO_CPU(aq_desc->cookie_low));
 351         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->params.internal.param0),
 353                    LE32_TO_CPU(aq_desc->params.internal.param1));
 354         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 355                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 356                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 357
 358         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 359                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 360                 if (buf_len < len)
 361                         len = buf_len;
 362                 /* write the full 16-byte chunks */
 363                 for (i = 0; i < (len - 16); i += 16)
 364                         i40e_debug(hw, mask,
 365                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 366                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 367                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 368                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 369                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 370                 /* the most we could have left is 16 bytes, pad with zeros */
 371                 if (i < len) {
 372                         char d_buf[16];
 373                         int j, i_sav;
 374
 375                         i_sav = i;
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446
 447 /**
 448  * i40e_aq_get_set_rss_lut
 449  * @hw: pointer to the hardware structure
 450  * @vsi_id: vsi fw index
 451  * @pf_lut: for PF table set true, for VSI table set false
 452  * @lut: pointer to the lut buffer provided by the caller
 453  * @lut_size: size of the lut buffer
 454  * @set: set true to set the table, false to get the table
 455  *
 456  * Internal function to get or set RSS look up table
 457  **/
 458 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 459                                                      u16 vsi_id, bool pf_lut,
 460                                                      u8 *lut, u16 lut_size,
 461                                                      bool set)
 462 {
 463         enum i40e_status_code status;
 464         struct i40e_aq_desc desc;
 465         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 466                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 467
 468         if (set)
 469                 i40e_fill_default_direct_cmd_desc(&desc,
 470                                                   i40e_aqc_opc_set_rss_lut);
 471         else
 472                 i40e_fill_default_direct_cmd_desc(&desc,
 473                                                   i40e_aqc_opc_get_rss_lut);
 474
 475         /* Indirect command */
 476         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 478
 479         cmd_resp->vsi_id =
 480                         CPU_TO_LE16((u16)((vsi_id <<
 481                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 483         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 484
 485         if (pf_lut)
 486                 cmd_resp->flags |= CPU_TO_LE16((u16)
 487                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 488                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 490         else
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495
 496         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 497
 498         return status;
 499 }
 500
 501 /**
 502  * i40e_aq_get_rss_lut
 503  * @hw: pointer to the hardware structure
 504  * @vsi_id: vsi fw index
 505  * @pf_lut: for PF table set true, for VSI table set false
 506  * @lut: pointer to the lut buffer provided by the caller
 507  * @lut_size: size of the lut buffer
 508  *
 509  * get the RSS lookup table, PF or VSI type
 510  **/
 511 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 512                                           bool pf_lut, u8 *lut, u16 lut_size)
 513 {
 514         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 515                                        false);
 516 }
 517
 518 /**
 519  * i40e_aq_set_rss_lut
 520  * @hw: pointer to the hardware structure
 521  * @vsi_id: vsi fw index
 522  * @pf_lut: for PF table set true, for VSI table set false
 523  * @lut: pointer to the lut buffer provided by the caller
 524  * @lut_size: size of the lut buffer
 525  *
 526  * set the RSS lookup table, PF or VSI type
 527  **/
 528 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 529                                           bool pf_lut, u8 *lut, u16 lut_size)
 530 {
 531         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 532 }
 533
 534 /**
 535  * i40e_aq_get_set_rss_key
 536  * @hw: pointer to the hw struct
 537  * @vsi_id: vsi fw index
 538  * @key: pointer to key info struct
 539  * @set: set true to set the key, false to get the key
 540  *
 541  * get the RSS key per VSI
 542  **/
 543 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 544                                       u16 vsi_id,
 545                                       struct i40e_aqc_get_set_rss_key_data *key,
 546                                       bool set)
 547 {
 548         enum i40e_status_code status;
 549         struct i40e_aq_desc desc;
 550         struct i40e_aqc_get_set_rss_key *cmd_resp =
 551                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 552         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 553
 554         if (set)
 555                 i40e_fill_default_direct_cmd_desc(&desc,
 556                                                   i40e_aqc_opc_set_rss_key);
 557         else
 558                 i40e_fill_default_direct_cmd_desc(&desc,
 559                                                   i40e_aqc_opc_get_rss_key);
 560
 561         /* Indirect command */
 562         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 564
 565         cmd_resp->vsi_id =
 566                         CPU_TO_LE16((u16)((vsi_id <<
 567                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 569         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 570
 571         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 572
 573         return status;
 574 }
 575
 576 /**
 577  * i40e_aq_get_rss_key
 578  * @hw: pointer to the hw struct
 579  * @vsi_id: vsi fw index
 580  * @key: pointer to key info struct
 581  *
 582  **/
 583 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 584                                       u16 vsi_id,
 585                                       struct i40e_aqc_get_set_rss_key_data *key)
 586 {
 587         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 588 }
 589
 590 /**
 591  * i40e_aq_set_rss_key
 592  * @hw: pointer to the hw struct
 593  * @vsi_id: vsi fw index
 594  * @key: pointer to key info struct
 595  *
 596  * set the RSS key per VSI
 597  **/
 598 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 599                                       u16 vsi_id,
 600                                       struct i40e_aqc_get_set_rss_key_data *key)
 601 {
 602         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 603 }
 604
 605 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 606  * hardware to a bit-field that can be used by SW to more easily determine the
 607  * packet type.
 608  *
 609  * Macros are used to shorten the table lines and make this table human
 610  * readable.
 611  *
 612  * We store the PTYPE in the top byte of the bit field - this is just so that
 613  * we can check that the table doesn't have a row missing, as the index into
 614  * the table should be the PTYPE.
 615  *
 616  * Typical work flow:
 617  *
 618  * IF NOT i40e_ptype_lookup[ptype].known
 619  * THEN
 620  *      Packet is unknown
 621  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 622  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 623  * ELSE
 624  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 625  * ENDIF
 626  */
 627
 628 /* macro to make the table lines short */
 629 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 630         {       PTYPE, \
 631                 1, \
 632                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 633                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 634                 I40E_RX_PTYPE_##OUTER_FRAG, \
 635                 I40E_RX_PTYPE_TUNNEL_##T, \
 636                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 637                 I40E_RX_PTYPE_##TEF, \
 638                 I40E_RX_PTYPE_INNER_PROT_##I, \
 639                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 640
 641 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 642                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 643
 644 /* shorter macros makes the table fit but are terse */
 645 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 646 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 647 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 648
 649 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 650 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 651         /* L2 Packet types */
 652         I40E_PTT_UNUSED_ENTRY(0),
 653         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 655         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT_UNUSED_ENTRY(4),
 657         I40E_PTT_UNUSED_ENTRY(5),
 658         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 659         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT_UNUSED_ENTRY(8),
 661         I40E_PTT_UNUSED_ENTRY(9),
 662         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 663         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 664         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674
 675         /* Non Tunneled IPv4 */
 676         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 679         I40E_PTT_UNUSED_ENTRY(25),
 680         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 681         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 682         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 683
 684         /* IPv4 --> IPv4 */
 685         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 686         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 687         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 688         I40E_PTT_UNUSED_ENTRY(32),
 689         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 690         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 691         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 692
 693         /* IPv4 --> IPv6 */
 694         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 695         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 696         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 697         I40E_PTT_UNUSED_ENTRY(39),
 698         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 699         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 700         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 701
 702         /* IPv4 --> GRE/NAT */
 703         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 704
 705         /* IPv4 --> GRE/NAT --> IPv4 */
 706         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 707         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 708         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 709         I40E_PTT_UNUSED_ENTRY(47),
 710         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 711         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 712         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 713
 714         /* IPv4 --> GRE/NAT --> IPv6 */
 715         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 716         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 717         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 718         I40E_PTT_UNUSED_ENTRY(54),
 719         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 720         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 721         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 722
 723         /* IPv4 --> GRE/NAT --> MAC */
 724         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 725
 726         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 727         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 728         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 729         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 730         I40E_PTT_UNUSED_ENTRY(62),
 731         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 732         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 733         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 734
 735         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 736         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 737         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 738         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 739         I40E_PTT_UNUSED_ENTRY(69),
 740         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 741         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 742         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 743
 744         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 745         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 746
 747         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 748         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 749         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 750         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 751         I40E_PTT_UNUSED_ENTRY(77),
 752         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 753         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 754         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 755
 756         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 757         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 758         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 759         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 760         I40E_PTT_UNUSED_ENTRY(84),
 761         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 762         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 763         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 764
 765         /* Non Tunneled IPv6 */
 766         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 767         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 768         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 769         I40E_PTT_UNUSED_ENTRY(91),
 770         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 771         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 772         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 773
 774         /* IPv6 --> IPv4 */
 775         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 776         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 777         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 778         I40E_PTT_UNUSED_ENTRY(98),
 779         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 780         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 781         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 782
 783         /* IPv6 --> IPv6 */
 784         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 785         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 786         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 787         I40E_PTT_UNUSED_ENTRY(105),
 788         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 789         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 790         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 791
 792         /* IPv6 --> GRE/NAT */
 793         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 794
 795         /* IPv6 --> GRE/NAT -> IPv4 */
 796         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 797         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 798         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 799         I40E_PTT_UNUSED_ENTRY(113),
 800         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 801         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 802         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 803
 804         /* IPv6 --> GRE/NAT -> IPv6 */
 805         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 806         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 807         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 808         I40E_PTT_UNUSED_ENTRY(120),
 809         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 810         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 811         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 812
 813         /* IPv6 --> GRE/NAT -> MAC */
 814         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 815
 816         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 817         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 818         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 819         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 820         I40E_PTT_UNUSED_ENTRY(128),
 821         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 822         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 823         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 824
 825         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 826         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 827         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 828         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 829         I40E_PTT_UNUSED_ENTRY(135),
 830         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 831         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 832         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 833
 834         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 835         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 836
 837         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 838         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 839         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 840         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 841         I40E_PTT_UNUSED_ENTRY(143),
 842         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 843         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 844         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 845
 846         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 847         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 848         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 849         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 850         I40E_PTT_UNUSED_ENTRY(150),
 851         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 852         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 853         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 854
 855         /* unused entries */
 856         I40E_PTT_UNUSED_ENTRY(154),
 857         I40E_PTT_UNUSED_ENTRY(155),
 858         I40E_PTT_UNUSED_ENTRY(156),
 859         I40E_PTT_UNUSED_ENTRY(157),
 860         I40E_PTT_UNUSED_ENTRY(158),
 861         I40E_PTT_UNUSED_ENTRY(159),
 862
 863         I40E_PTT_UNUSED_ENTRY(160),
 864         I40E_PTT_UNUSED_ENTRY(161),
 865         I40E_PTT_UNUSED_ENTRY(162),
 866         I40E_PTT_UNUSED_ENTRY(163),
 867         I40E_PTT_UNUSED_ENTRY(164),
 868         I40E_PTT_UNUSED_ENTRY(165),
 869         I40E_PTT_UNUSED_ENTRY(166),
 870         I40E_PTT_UNUSED_ENTRY(167),
 871         I40E_PTT_UNUSED_ENTRY(168),
 872         I40E_PTT_UNUSED_ENTRY(169),
 873
 874         I40E_PTT_UNUSED_ENTRY(170),
 875         I40E_PTT_UNUSED_ENTRY(171),
 876         I40E_PTT_UNUSED_ENTRY(172),
 877         I40E_PTT_UNUSED_ENTRY(173),
 878         I40E_PTT_UNUSED_ENTRY(174),
 879         I40E_PTT_UNUSED_ENTRY(175),
 880         I40E_PTT_UNUSED_ENTRY(176),
 881         I40E_PTT_UNUSED_ENTRY(177),
 882         I40E_PTT_UNUSED_ENTRY(178),
 883         I40E_PTT_UNUSED_ENTRY(179),
 884
 885         I40E_PTT_UNUSED_ENTRY(180),
 886         I40E_PTT_UNUSED_ENTRY(181),
 887         I40E_PTT_UNUSED_ENTRY(182),
 888         I40E_PTT_UNUSED_ENTRY(183),
 889         I40E_PTT_UNUSED_ENTRY(184),
 890         I40E_PTT_UNUSED_ENTRY(185),
 891         I40E_PTT_UNUSED_ENTRY(186),
 892         I40E_PTT_UNUSED_ENTRY(187),
 893         I40E_PTT_UNUSED_ENTRY(188),
 894         I40E_PTT_UNUSED_ENTRY(189),
 895
 896         I40E_PTT_UNUSED_ENTRY(190),
 897         I40E_PTT_UNUSED_ENTRY(191),
 898         I40E_PTT_UNUSED_ENTRY(192),
 899         I40E_PTT_UNUSED_ENTRY(193),
 900         I40E_PTT_UNUSED_ENTRY(194),
 901         I40E_PTT_UNUSED_ENTRY(195),
 902         I40E_PTT_UNUSED_ENTRY(196),
 903         I40E_PTT_UNUSED_ENTRY(197),
 904         I40E_PTT_UNUSED_ENTRY(198),
 905         I40E_PTT_UNUSED_ENTRY(199),
 906
 907         I40E_PTT_UNUSED_ENTRY(200),
 908         I40E_PTT_UNUSED_ENTRY(201),
 909         I40E_PTT_UNUSED_ENTRY(202),
 910         I40E_PTT_UNUSED_ENTRY(203),
 911         I40E_PTT_UNUSED_ENTRY(204),
 912         I40E_PTT_UNUSED_ENTRY(205),
 913         I40E_PTT_UNUSED_ENTRY(206),
 914         I40E_PTT_UNUSED_ENTRY(207),
 915         I40E_PTT_UNUSED_ENTRY(208),
 916         I40E_PTT_UNUSED_ENTRY(209),
 917
 918         I40E_PTT_UNUSED_ENTRY(210),
 919         I40E_PTT_UNUSED_ENTRY(211),
 920         I40E_PTT_UNUSED_ENTRY(212),
 921         I40E_PTT_UNUSED_ENTRY(213),
 922         I40E_PTT_UNUSED_ENTRY(214),
 923         I40E_PTT_UNUSED_ENTRY(215),
 924         I40E_PTT_UNUSED_ENTRY(216),
 925         I40E_PTT_UNUSED_ENTRY(217),
 926         I40E_PTT_UNUSED_ENTRY(218),
 927         I40E_PTT_UNUSED_ENTRY(219),
 928
 929         I40E_PTT_UNUSED_ENTRY(220),
 930         I40E_PTT_UNUSED_ENTRY(221),
 931         I40E_PTT_UNUSED_ENTRY(222),
 932         I40E_PTT_UNUSED_ENTRY(223),
 933         I40E_PTT_UNUSED_ENTRY(224),
 934         I40E_PTT_UNUSED_ENTRY(225),
 935         I40E_PTT_UNUSED_ENTRY(226),
 936         I40E_PTT_UNUSED_ENTRY(227),
 937         I40E_PTT_UNUSED_ENTRY(228),
 938         I40E_PTT_UNUSED_ENTRY(229),
 939
 940         I40E_PTT_UNUSED_ENTRY(230),
 941         I40E_PTT_UNUSED_ENTRY(231),
 942         I40E_PTT_UNUSED_ENTRY(232),
 943         I40E_PTT_UNUSED_ENTRY(233),
 944         I40E_PTT_UNUSED_ENTRY(234),
 945         I40E_PTT_UNUSED_ENTRY(235),
 946         I40E_PTT_UNUSED_ENTRY(236),
 947         I40E_PTT_UNUSED_ENTRY(237),
 948         I40E_PTT_UNUSED_ENTRY(238),
 949         I40E_PTT_UNUSED_ENTRY(239),
 950
 951         I40E_PTT_UNUSED_ENTRY(240),
 952         I40E_PTT_UNUSED_ENTRY(241),
 953         I40E_PTT_UNUSED_ENTRY(242),
 954         I40E_PTT_UNUSED_ENTRY(243),
 955         I40E_PTT_UNUSED_ENTRY(244),
 956         I40E_PTT_UNUSED_ENTRY(245),
 957         I40E_PTT_UNUSED_ENTRY(246),
 958         I40E_PTT_UNUSED_ENTRY(247),
 959         I40E_PTT_UNUSED_ENTRY(248),
 960         I40E_PTT_UNUSED_ENTRY(249),
 961
 962         I40E_PTT_UNUSED_ENTRY(250),
 963         I40E_PTT_UNUSED_ENTRY(251),
 964         I40E_PTT_UNUSED_ENTRY(252),
 965         I40E_PTT_UNUSED_ENTRY(253),
 966         I40E_PTT_UNUSED_ENTRY(254),
 967         I40E_PTT_UNUSED_ENTRY(255)
 968 };
 969
 970
 971 /**
 972  * i40e_validate_mac_addr - Validate unicast MAC address
 973  * @mac_addr: pointer to MAC address
 974  *
 975  * Tests a MAC address to ensure it is a valid Individual Address
 976  **/
 977 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 978 {
 979         enum i40e_status_code status = I40E_SUCCESS;
 980
 981         DEBUGFUNC("i40e_validate_mac_addr");
 982
 983         /* Broadcast addresses ARE multicast addresses
 984          * Make sure it is not a multicast address
 985          * Reject the zero address
 986          */
 987         if (I40E_IS_MULTICAST(mac_addr) ||
 988             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 989               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 990                 status = I40E_ERR_INVALID_MAC_ADDR;
 991
 992         return status;
 993 }
 994 #ifdef PF_DRIVER
 995
 996 /**
 997  * i40e_init_shared_code - Initialize the shared code
 998  * @hw: pointer to hardware structure
 999  *
1000  * This assigns the MAC type and PHY code and inits the NVM.
1001  * Does not touch the hardware. This function must be called prior to any
1002  * other function in the shared code. The i40e_hw structure should be
1003  * memset to 0 prior to calling this function.  The following fields in
1004  * hw structure should be filled in prior to calling this function:
1005  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1006  * subsystem_vendor_id, and revision_id
1007  **/
1008 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1009 {
1010         enum i40e_status_code status = I40E_SUCCESS;
1011         u32 port, ari, func_rid;
1012
1013         DEBUGFUNC("i40e_init_shared_code");
1014
1015         i40e_set_mac_type(hw);
1016
1017         switch (hw->mac.type) {
1018         case I40E_MAC_XL710:
1019         case I40E_MAC_X722:
1020                 break;
1021         default:
1022                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1023         }
1024
1025         hw->phy.get_link_info = true;
1026
1027         /* Determine port number and PF number*/
1028         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1029                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1030         hw->port = (u8)port;
1031         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1032                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1033         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1034         if (ari)
1035                 hw->pf_id = (u8)(func_rid & 0xff);
1036         else
1037                 hw->pf_id = (u8)(func_rid & 0x7);
1038
1039         if (hw->mac.type == I40E_MAC_X722)
1040                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1041                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1042
1043         status = i40e_init_nvm(hw);
1044         return status;
1045 }
1046
1047 /**
1048  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1049  * @hw: pointer to the hw struct
1050  * @flags: a return indicator of what addresses were added to the addr store
1051  * @addrs: the requestor's mac addr store
1052  * @cmd_details: pointer to command details structure or NULL
1053  **/
1054 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1055                                    u16 *flags,
1056                                    struct i40e_aqc_mac_address_read_data *addrs,
1057                                    struct i40e_asq_cmd_details *cmd_details)
1058 {
1059         struct i40e_aq_desc desc;
1060         struct i40e_aqc_mac_address_read *cmd_data =
1061                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1062         enum i40e_status_code status;
1063
1064         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1065         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1066
1067         status = i40e_asq_send_command(hw, &desc, addrs,
1068                                        sizeof(*addrs), cmd_details);
1069         *flags = LE16_TO_CPU(cmd_data->command_flags);
1070
1071         return status;
1072 }
1073
1074 /**
1075  * i40e_aq_mac_address_write - Change the MAC addresses
1076  * @hw: pointer to the hw struct
1077  * @flags: indicates which MAC to be written
1078  * @mac_addr: address to write
1079  * @cmd_details: pointer to command details structure or NULL
1080  **/
1081 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1082                                     u16 flags, u8 *mac_addr,
1083                                     struct i40e_asq_cmd_details *cmd_details)
1084 {
1085         struct i40e_aq_desc desc;
1086         struct i40e_aqc_mac_address_write *cmd_data =
1087                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1088         enum i40e_status_code status;
1089
1090         i40e_fill_default_direct_cmd_desc(&desc,
1091                                           i40e_aqc_opc_mac_address_write);
1092         cmd_data->command_flags = CPU_TO_LE16(flags);
1093         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1094         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1095                                         ((u32)mac_addr[3] << 16) |
1096                                         ((u32)mac_addr[4] << 8) |
1097                                         mac_addr[5]);
1098
1099         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1100
1101         return status;
1102 }
1103
1104 /**
1105  * i40e_get_mac_addr - get MAC address
1106  * @hw: pointer to the HW structure
1107  * @mac_addr: pointer to MAC address
1108  *
1109  * Reads the adapter's MAC address from register
1110  **/
1111 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1112 {
1113         struct i40e_aqc_mac_address_read_data addrs;
1114         enum i40e_status_code status;
1115         u16 flags = 0;
1116
1117         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1118
1119         if (flags & I40E_AQC_LAN_ADDR_VALID)
1120                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1121                         I40E_NONDMA_TO_NONDMA);
1122
1123         return status;
1124 }
1125
1126 /**
1127  * i40e_get_port_mac_addr - get Port MAC address
1128  * @hw: pointer to the HW structure
1129  * @mac_addr: pointer to Port MAC address
1130  *
1131  * Reads the adapter's Port MAC address
1132  **/
1133 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1134 {
1135         struct i40e_aqc_mac_address_read_data addrs;
1136         enum i40e_status_code status;
1137         u16 flags = 0;
1138
1139         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1140         if (status)
1141                 return status;
1142
1143         if (flags & I40E_AQC_PORT_ADDR_VALID)
1144                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1145                         I40E_NONDMA_TO_NONDMA);
1146         else
1147                 status = I40E_ERR_INVALID_MAC_ADDR;
1148
1149         return status;
1150 }
1151
1152 /**
1153  * i40e_pre_tx_queue_cfg - pre tx queue configure
1154  * @hw: pointer to the HW structure
1155  * @queue: target pf queue index
1156  * @enable: state change request
1157  *
1158  * Handles hw requirement to indicate intention to enable
1159  * or disable target queue.
1160  **/
1161 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1162 {
1163         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1164         u32 reg_block = 0;
1165         u32 reg_val;
1166
1167         if (abs_queue_idx >= 128) {
1168                 reg_block = abs_queue_idx / 128;
1169                 abs_queue_idx %= 128;
1170         }
1171
1172         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1173         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1174         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1175
1176         if (enable)
1177                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1178         else
1179                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1180
1181         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1182 }
1183
1184 /**
1185  * i40e_get_san_mac_addr - get SAN MAC address
1186  * @hw: pointer to the HW structure
1187  * @mac_addr: pointer to SAN MAC address
1188  *
1189  * Reads the adapter's SAN MAC address from NVM
1190  **/
1191 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1192                                             u8 *mac_addr)
1193 {
1194         struct i40e_aqc_mac_address_read_data addrs;
1195         enum i40e_status_code status;
1196         u16 flags = 0;
1197
1198         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1199         if (status)
1200                 return status;
1201
1202         if (flags & I40E_AQC_SAN_ADDR_VALID)
1203                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1204                         I40E_NONDMA_TO_NONDMA);
1205         else
1206                 status = I40E_ERR_INVALID_MAC_ADDR;
1207
1208         return status;
1209 }
1210
1211 /**
1212  *  i40e_read_pba_string - Reads part number string from EEPROM
1213  *  @hw: pointer to hardware structure
1214  *  @pba_num: stores the part number string from the EEPROM
1215  *  @pba_num_size: part number string buffer length
1216  *
1217  *  Reads the part number string from the EEPROM.
1218  **/
1219 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1220                                             u32 pba_num_size)
1221 {
1222         enum i40e_status_code status = I40E_SUCCESS;
1223         u16 pba_word = 0;
1224         u16 pba_size = 0;
1225         u16 pba_ptr = 0;
1226         u16 i = 0;
1227
1228         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1229         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1230                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1231                 return status;
1232         }
1233
1234         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1235         if (status != I40E_SUCCESS) {
1236                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1237                 return status;
1238         }
1239
1240         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1241         if (status != I40E_SUCCESS) {
1242                 DEBUGOUT("Failed to read PBA Block size.\n");
1243                 return status;
1244         }
1245
1246         /* Subtract one to get PBA word count (PBA Size word is included in
1247          * total size)
1248          */
1249         pba_size--;
1250         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1251                 DEBUGOUT("Buffer to small for PBA data.\n");
1252                 return I40E_ERR_PARAM;
1253         }
1254
1255         for (i = 0; i < pba_size; i++) {
1256                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1257                 if (status != I40E_SUCCESS) {
1258                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1259                         return status;
1260                 }
1261
1262                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1263                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1264         }
1265         pba_num[(pba_size * 2)] = '\0';
1266
1267         return status;
1268 }
1269
1270 /**
1271  * i40e_get_media_type - Gets media type
1272  * @hw: pointer to the hardware structure
1273  **/
1274 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1275 {
1276         enum i40e_media_type media;
1277
1278         switch (hw->phy.link_info.phy_type) {
1279         case I40E_PHY_TYPE_10GBASE_SR:
1280         case I40E_PHY_TYPE_10GBASE_LR:
1281         case I40E_PHY_TYPE_1000BASE_SX:
1282         case I40E_PHY_TYPE_1000BASE_LX:
1283         case I40E_PHY_TYPE_40GBASE_SR4:
1284         case I40E_PHY_TYPE_40GBASE_LR4:
1285         case I40E_PHY_TYPE_25GBASE_LR:
1286         case I40E_PHY_TYPE_25GBASE_SR:
1287                 media = I40E_MEDIA_TYPE_FIBER;
1288                 break;
1289         case I40E_PHY_TYPE_100BASE_TX:
1290         case I40E_PHY_TYPE_1000BASE_T:
1291         case I40E_PHY_TYPE_10GBASE_T:
1292                 media = I40E_MEDIA_TYPE_BASET;
1293                 break;
1294         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1295         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1296         case I40E_PHY_TYPE_10GBASE_CR1:
1297         case I40E_PHY_TYPE_40GBASE_CR4:
1298         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1299         case I40E_PHY_TYPE_40GBASE_AOC:
1300         case I40E_PHY_TYPE_10GBASE_AOC:
1301         case I40E_PHY_TYPE_25GBASE_CR:
1302         case I40E_PHY_TYPE_25GBASE_AOC:
1303         case I40E_PHY_TYPE_25GBASE_ACC:
1304                 media = I40E_MEDIA_TYPE_DA;
1305                 break;
1306         case I40E_PHY_TYPE_1000BASE_KX:
1307         case I40E_PHY_TYPE_10GBASE_KX4:
1308         case I40E_PHY_TYPE_10GBASE_KR:
1309         case I40E_PHY_TYPE_40GBASE_KR4:
1310         case I40E_PHY_TYPE_20GBASE_KR2:
1311         case I40E_PHY_TYPE_25GBASE_KR:
1312                 media = I40E_MEDIA_TYPE_BACKPLANE;
1313                 break;
1314         case I40E_PHY_TYPE_SGMII:
1315         case I40E_PHY_TYPE_XAUI:
1316         case I40E_PHY_TYPE_XFI:
1317         case I40E_PHY_TYPE_XLAUI:
1318         case I40E_PHY_TYPE_XLPPI:
1319         default:
1320                 media = I40E_MEDIA_TYPE_UNKNOWN;
1321                 break;
1322         }
1323
1324         return media;
1325 }
1326
1327 #define I40E_PF_RESET_WAIT_COUNT        200
1328 /**
1329  * i40e_pf_reset - Reset the PF
1330  * @hw: pointer to the hardware structure
1331  *
1332  * Assuming someone else has triggered a global reset,
1333  * assure the global reset is complete and then reset the PF
1334  **/
1335 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1336 {
1337         u32 cnt = 0;
1338         u32 cnt1 = 0;
1339         u32 reg = 0;
1340         u32 grst_del;
1341
1342         /* Poll for Global Reset steady state in case of recent GRST.
1343          * The grst delay value is in 100ms units, and we'll wait a
1344          * couple counts longer to be sure we don't just miss the end.
1345          */
1346         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1347                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1348                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1349
1350         grst_del = grst_del * 20;
1351
1352         for (cnt = 0; cnt < grst_del; cnt++) {
1353                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1354                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1355                         break;
1356                 i40e_msec_delay(100);
1357         }
1358         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1359                 DEBUGOUT("Global reset polling failed to complete.\n");
1360                 return I40E_ERR_RESET_FAILED;
1361         }
1362
1363         /* Now Wait for the FW to be ready */
1364         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1365                 reg = rd32(hw, I40E_GLNVM_ULD);
1366                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1367                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1368                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1369                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1370                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1371                         break;
1372                 }
1373                 i40e_msec_delay(10);
1374         }
1375         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1376                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1377                 DEBUGOUT("wait for FW Reset complete timedout\n");
1378                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1379                 return I40E_ERR_RESET_FAILED;
1380         }
1381
1382         /* If there was a Global Reset in progress when we got here,
1383          * we don't need to do the PF Reset
1384          */
1385         if (!cnt) {
1386                 u32 reg2 = 0;
1387
1388                 reg = rd32(hw, I40E_PFGEN_CTRL);
1389                 wr32(hw, I40E_PFGEN_CTRL,
1390                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1391                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1392                         reg = rd32(hw, I40E_PFGEN_CTRL);
1393                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1394                                 break;
1395                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1396                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1397                                 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");
1398                                 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1399                                 return I40E_ERR_NOT_READY;
1400                         }
1401                         i40e_msec_delay(1);
1402                 }
1403                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1404                         DEBUGOUT("PF reset polling failed to complete.\n");
1405                         return I40E_ERR_RESET_FAILED;
1406                 }
1407         }
1408
1409         i40e_clear_pxe_mode(hw);
1410
1411
1412         return I40E_SUCCESS;
1413 }
1414
1415 /**
1416  * i40e_clear_hw - clear out any left over hw state
1417  * @hw: pointer to the hw struct
1418  *
1419  * Clear queues and interrupts, typically called at init time,
1420  * but after the capabilities have been found so we know how many
1421  * queues and msix vectors have been allocated.
1422  **/
1423 void i40e_clear_hw(struct i40e_hw *hw)
1424 {
1425         u32 num_queues, base_queue;
1426         u32 num_pf_int;
1427         u32 num_vf_int;
1428         u32 num_vfs;
1429         u32 i, j;
1430         u32 val;
1431         u32 eol = 0x7ff;
1432
1433         /* get number of interrupts, queues, and vfs */
1434         val = rd32(hw, I40E_GLPCI_CNF2);
1435         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1436                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1437         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1438                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1439
1440         val = rd32(hw, I40E_PFLAN_QALLOC);
1441         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1442                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1443         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1444                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1445         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1446                 num_queues = (j - base_queue) + 1;
1447         else
1448                 num_queues = 0;
1449
1450         val = rd32(hw, I40E_PF_VT_PFALLOC);
1451         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1452                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1453         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1454                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1455         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1456                 num_vfs = (j - i) + 1;
1457         else
1458                 num_vfs = 0;
1459
1460         /* stop all the interrupts */
1461         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1462         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1463         for (i = 0; i < num_pf_int - 2; i++)
1464                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1465
1466         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1467         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1468         wr32(hw, I40E_PFINT_LNKLST0, val);
1469         for (i = 0; i < num_pf_int - 2; i++)
1470                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1471         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1472         for (i = 0; i < num_vfs; i++)
1473                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1474         for (i = 0; i < num_vf_int - 2; i++)
1475                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1476
1477         /* warn the HW of the coming Tx disables */
1478         for (i = 0; i < num_queues; i++) {
1479                 u32 abs_queue_idx = base_queue + i;
1480                 u32 reg_block = 0;
1481
1482                 if (abs_queue_idx >= 128) {
1483                         reg_block = abs_queue_idx / 128;
1484                         abs_queue_idx %= 128;
1485                 }
1486
1487                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1488                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1489                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1490                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1491
1492                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1493         }
1494         i40e_usec_delay(400);
1495
1496         /* stop all the queues */
1497         for (i = 0; i < num_queues; i++) {
1498                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1499                 wr32(hw, I40E_QTX_ENA(i), 0);
1500                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1501                 wr32(hw, I40E_QRX_ENA(i), 0);
1502         }
1503
1504         /* short wait for all queue disables to settle */
1505         i40e_usec_delay(50);
1506 }
1507
1508 /**
1509  * i40e_clear_pxe_mode - clear pxe operations mode
1510  * @hw: pointer to the hw struct
1511  *
1512  * Make sure all PXE mode settings are cleared, including things
1513  * like descriptor fetch/write-back mode.
1514  **/
1515 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1516 {
1517         if (i40e_check_asq_alive(hw))
1518                 i40e_aq_clear_pxe_mode(hw, NULL);
1519 }
1520
1521 /**
1522  * i40e_led_is_mine - helper to find matching led
1523  * @hw: pointer to the hw struct
1524  * @idx: index into GPIO registers
1525  *
1526  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1527  */
1528 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1529 {
1530         u32 gpio_val = 0;
1531         u32 port;
1532
1533         if (!hw->func_caps.led[idx])
1534                 return 0;
1535
1536         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1537         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1538                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1539
1540         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1541          * if it is not our port then ignore
1542          */
1543         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1544             (port != hw->port))
1545                 return 0;
1546
1547         return gpio_val;
1548 }
1549
1550 #define I40E_COMBINED_ACTIVITY 0xA
1551 #define I40E_FILTER_ACTIVITY 0xE
1552 #define I40E_LINK_ACTIVITY 0xC
1553 #define I40E_MAC_ACTIVITY 0xD
1554 #define I40E_LED0 22
1555
1556 /**
1557  * i40e_led_get - return current on/off mode
1558  * @hw: pointer to the hw struct
1559  *
1560  * The value returned is the 'mode' field as defined in the
1561  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1562  * values are variations of possible behaviors relating to
1563  * blink, link, and wire.
1564  **/
1565 u32 i40e_led_get(struct i40e_hw *hw)
1566 {
1567         u32 current_mode = 0;
1568         u32 mode = 0;
1569         int i;
1570
1571         /* as per the documentation GPIO 22-29 are the LED
1572          * GPIO pins named LED0..LED7
1573          */
1574         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1575                 u32 gpio_val = i40e_led_is_mine(hw, i);
1576
1577                 if (!gpio_val)
1578                         continue;
1579
1580                 /* ignore gpio LED src mode entries related to the activity
1581                  *  LEDs
1582                  */
1583                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1584                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1585                 switch (current_mode) {
1586                 case I40E_COMBINED_ACTIVITY:
1587                 case I40E_FILTER_ACTIVITY:
1588                 case I40E_MAC_ACTIVITY:
1589                         continue;
1590                 default:
1591                         break;
1592                 }
1593
1594                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1595                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1596                 break;
1597         }
1598
1599         return mode;
1600 }
1601
1602 /**
1603  * i40e_led_set - set new on/off mode
1604  * @hw: pointer to the hw struct
1605  * @mode: 0=off, 0xf=on (else see manual for mode details)
1606  * @blink: true if the LED should blink when on, false if steady
1607  *
1608  * if this function is used to turn on the blink it should
1609  * be used to disable the blink when restoring the original state.
1610  **/
1611 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1612 {
1613         u32 current_mode = 0;
1614         int i;
1615
1616         if (mode & 0xfffffff0)
1617                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1618
1619         /* as per the documentation GPIO 22-29 are the LED
1620          * GPIO pins named LED0..LED7
1621          */
1622         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1623                 u32 gpio_val = i40e_led_is_mine(hw, i);
1624
1625                 if (!gpio_val)
1626                         continue;
1627
1628                 /* ignore gpio LED src mode entries related to the activity
1629                  * LEDs
1630                  */
1631                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1632                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1633                 switch (current_mode) {
1634                 case I40E_COMBINED_ACTIVITY:
1635                 case I40E_FILTER_ACTIVITY:
1636                 case I40E_MAC_ACTIVITY:
1637                         continue;
1638                 default:
1639                         break;
1640                 }
1641
1642                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1643                 /* this & is a bit of paranoia, but serves as a range check */
1644                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1645                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1646
1647                 if (mode == I40E_LINK_ACTIVITY)
1648                         blink = false;
1649
1650                 if (blink)
1651                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1652                 else
1653                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1654
1655                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1656                 break;
1657         }
1658 }
1659
1660 /* Admin command wrappers */
1661
1662 /**
1663  * i40e_aq_get_phy_capabilities
1664  * @hw: pointer to the hw struct
1665  * @abilities: structure for PHY capabilities to be filled
1666  * @qualified_modules: report Qualified Modules
1667  * @report_init: report init capabilities (active are default)
1668  * @cmd_details: pointer to command details structure or NULL
1669  *
1670  * Returns the various PHY abilities supported on the Port.
1671  **/
1672 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1673                         bool qualified_modules, bool report_init,
1674                         struct i40e_aq_get_phy_abilities_resp *abilities,
1675                         struct i40e_asq_cmd_details *cmd_details)
1676 {
1677         struct i40e_aq_desc desc;
1678         enum i40e_status_code status;
1679         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1680         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1681
1682         if (!abilities)
1683                 return I40E_ERR_PARAM;
1684
1685         do {
1686                 i40e_fill_default_direct_cmd_desc(&desc,
1687                                                i40e_aqc_opc_get_phy_abilities);
1688
1689                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1690                 if (abilities_size > I40E_AQ_LARGE_BUF)
1691                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1692
1693                 if (qualified_modules)
1694                         desc.params.external.param0 |=
1695                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1696
1697                 if (report_init)
1698                         desc.params.external.param0 |=
1699                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1700
1701                 status = i40e_asq_send_command(hw, &desc, abilities,
1702                                                abilities_size, cmd_details);
1703
1704                 if (status != I40E_SUCCESS)
1705                         break;
1706
1707                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1708                         status = I40E_ERR_UNKNOWN_PHY;
1709                         break;
1710                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1711                         i40e_msec_delay(1);
1712                         total_delay++;
1713                         status = I40E_ERR_TIMEOUT;
1714                 }
1715         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1716                  (total_delay < max_delay));
1717
1718         if (status != I40E_SUCCESS)
1719                 return status;
1720
1721         if (report_init) {
1722                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1723                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1724                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1725                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1726                 } else {
1727                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1728                         hw->phy.phy_types |=
1729                                         ((u64)abilities->phy_type_ext << 32);
1730                 }
1731         }
1732
1733         return status;
1734 }
1735
1736 /**
1737  * i40e_aq_set_phy_config
1738  * @hw: pointer to the hw struct
1739  * @config: structure with PHY configuration to be set
1740  * @cmd_details: pointer to command details structure or NULL
1741  *
1742  * Set the various PHY configuration parameters
1743  * supported on the Port.One or more of the Set PHY config parameters may be
1744  * ignored in an MFP mode as the PF may not have the privilege to set some
1745  * of the PHY Config parameters. This status will be indicated by the
1746  * command response.
1747  **/
1748 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1749                                 struct i40e_aq_set_phy_config *config,
1750                                 struct i40e_asq_cmd_details *cmd_details)
1751 {
1752         struct i40e_aq_desc desc;
1753         struct i40e_aq_set_phy_config *cmd =
1754                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1755         enum i40e_status_code status;
1756
1757         if (!config)
1758                 return I40E_ERR_PARAM;
1759
1760         i40e_fill_default_direct_cmd_desc(&desc,
1761                                           i40e_aqc_opc_set_phy_config);
1762
1763         *cmd = *config;
1764
1765         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1766
1767         return status;
1768 }
1769
1770 /**
1771  * i40e_set_fc
1772  * @hw: pointer to the hw struct
1773  * @aq_failures: buffer to return AdminQ failure information
1774  * @atomic_restart: whether to enable atomic link restart
1775  *
1776  * Set the requested flow control mode using set_phy_config.
1777  **/
1778 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1779                                   bool atomic_restart)
1780 {
1781         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1782         struct i40e_aq_get_phy_abilities_resp abilities;
1783         struct i40e_aq_set_phy_config config;
1784         enum i40e_status_code status;
1785         u8 pause_mask = 0x0;
1786
1787         *aq_failures = 0x0;
1788
1789         switch (fc_mode) {
1790         case I40E_FC_FULL:
1791                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1792                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1793                 break;
1794         case I40E_FC_RX_PAUSE:
1795                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1796                 break;
1797         case I40E_FC_TX_PAUSE:
1798                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1799                 break;
1800         default:
1801                 break;
1802         }
1803
1804         /* Get the current phy config */
1805         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1806                                               NULL);
1807         if (status) {
1808                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1809                 return status;
1810         }
1811
1812         memset(&config, 0, sizeof(config));
1813         /* clear the old pause settings */
1814         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1815                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1816         /* set the new abilities */
1817         config.abilities |= pause_mask;
1818         /* If the abilities have changed, then set the new config */
1819         if (config.abilities != abilities.abilities) {
1820                 /* Auto restart link so settings take effect */
1821                 if (atomic_restart)
1822                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1823                 /* Copy over all the old settings */
1824                 config.phy_type = abilities.phy_type;
1825                 config.phy_type_ext = abilities.phy_type_ext;
1826                 config.link_speed = abilities.link_speed;
1827                 config.eee_capability = abilities.eee_capability;
1828                 config.eeer = abilities.eeer_val;
1829                 config.low_power_ctrl = abilities.d3_lpan;
1830                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1831                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1832                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1833
1834                 if (status)
1835                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1836         }
1837         /* Update the link info */
1838         status = i40e_update_link_info(hw);
1839         if (status) {
1840                 /* Wait a little bit (on 40G cards it sometimes takes a really
1841                  * long time for link to come back from the atomic reset)
1842                  * and try once more
1843                  */
1844                 i40e_msec_delay(1000);
1845                 status = i40e_update_link_info(hw);
1846         }
1847         if (status)
1848                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1849
1850         return status;
1851 }
1852
1853 /**
1854  * i40e_aq_set_mac_config
1855  * @hw: pointer to the hw struct
1856  * @max_frame_size: Maximum Frame Size to be supported by the port
1857  * @crc_en: Tell HW to append a CRC to outgoing frames
1858  * @pacing: Pacing configurations
1859  * @cmd_details: pointer to command details structure or NULL
1860  *
1861  * Configure MAC settings for frame size, jumbo frame support and the
1862  * addition of a CRC by the hardware.
1863  **/
1864 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1865                                 u16 max_frame_size,
1866                                 bool crc_en, u16 pacing,
1867                                 struct i40e_asq_cmd_details *cmd_details)
1868 {
1869         struct i40e_aq_desc desc;
1870         struct i40e_aq_set_mac_config *cmd =
1871                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1872         enum i40e_status_code status;
1873
1874         if (max_frame_size == 0)
1875                 return I40E_ERR_PARAM;
1876
1877         i40e_fill_default_direct_cmd_desc(&desc,
1878                                           i40e_aqc_opc_set_mac_config);
1879
1880         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1881         cmd->params = ((u8)pacing & 0x0F) << 3;
1882         if (crc_en)
1883                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1884
1885         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1886
1887         return status;
1888 }
1889
1890 /**
1891  * i40e_aq_clear_pxe_mode
1892  * @hw: pointer to the hw struct
1893  * @cmd_details: pointer to command details structure or NULL
1894  *
1895  * Tell the firmware that the driver is taking over from PXE
1896  **/
1897 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1898                         struct i40e_asq_cmd_details *cmd_details)
1899 {
1900         enum i40e_status_code status;
1901         struct i40e_aq_desc desc;
1902         struct i40e_aqc_clear_pxe *cmd =
1903                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1904
1905         i40e_fill_default_direct_cmd_desc(&desc,
1906                                           i40e_aqc_opc_clear_pxe_mode);
1907
1908         cmd->rx_cnt = 0x2;
1909
1910         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1911
1912         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1913
1914         return status;
1915 }
1916
1917 /**
1918  * i40e_aq_set_link_restart_an
1919  * @hw: pointer to the hw struct
1920  * @enable_link: if true: enable link, if false: disable link
1921  * @cmd_details: pointer to command details structure or NULL
1922  *
1923  * Sets up the link and restarts the Auto-Negotiation over the link.
1924  **/
1925 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1926                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1927 {
1928         struct i40e_aq_desc desc;
1929         struct i40e_aqc_set_link_restart_an *cmd =
1930                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1931         enum i40e_status_code status;
1932
1933         i40e_fill_default_direct_cmd_desc(&desc,
1934                                           i40e_aqc_opc_set_link_restart_an);
1935
1936         cmd->command = I40E_AQ_PHY_RESTART_AN;
1937         if (enable_link)
1938                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1939         else
1940                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1941
1942         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1943
1944         return status;
1945 }
1946
1947 /**
1948  * i40e_aq_get_link_info
1949  * @hw: pointer to the hw struct
1950  * @enable_lse: enable/disable LinkStatusEvent reporting
1951  * @link: pointer to link status structure - optional
1952  * @cmd_details: pointer to command details structure or NULL
1953  *
1954  * Returns the link status of the adapter.
1955  **/
1956 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1957                                 bool enable_lse, struct i40e_link_status *link,
1958                                 struct i40e_asq_cmd_details *cmd_details)
1959 {
1960         struct i40e_aq_desc desc;
1961         struct i40e_aqc_get_link_status *resp =
1962                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1963         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1964         enum i40e_status_code status;
1965         bool tx_pause, rx_pause;
1966         u16 command_flags;
1967
1968         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1969
1970         if (enable_lse)
1971                 command_flags = I40E_AQ_LSE_ENABLE;
1972         else
1973                 command_flags = I40E_AQ_LSE_DISABLE;
1974         resp->command_flags = CPU_TO_LE16(command_flags);
1975
1976         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1977
1978         if (status != I40E_SUCCESS)
1979                 goto aq_get_link_info_exit;
1980
1981         /* save off old link status information */
1982         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1983                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1984
1985         /* update link status */
1986         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1987         hw->phy.media_type = i40e_get_media_type(hw);
1988         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1989         hw_link_info->link_info = resp->link_info;
1990         hw_link_info->an_info = resp->an_info;
1991         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1992                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1993         hw_link_info->ext_info = resp->ext_info;
1994         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1995         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1996         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1997
1998         /* update fc info */
1999         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2000         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2001         if (tx_pause & rx_pause)
2002                 hw->fc.current_mode = I40E_FC_FULL;
2003         else if (tx_pause)
2004                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2005         else if (rx_pause)
2006                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2007         else
2008                 hw->fc.current_mode = I40E_FC_NONE;
2009
2010         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2011                 hw_link_info->crc_enable = true;
2012         else
2013                 hw_link_info->crc_enable = false;
2014
2015         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2016                 hw_link_info->lse_enable = true;
2017         else
2018                 hw_link_info->lse_enable = false;
2019
2020         if ((hw->mac.type == I40E_MAC_XL710) &&
2021             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2022              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2023                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2024
2025         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2026             hw->aq.api_min_ver >= 7) {
2027                 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type);
2028                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2029         }
2030
2031         /* save link status information */
2032         if (link)
2033                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2034                             I40E_NONDMA_TO_NONDMA);
2035
2036         /* flag cleared so helper functions don't call AQ again */
2037         hw->phy.get_link_info = false;
2038
2039 aq_get_link_info_exit:
2040         return status;
2041 }
2042
2043 /**
2044  * i40e_aq_set_phy_int_mask
2045  * @hw: pointer to the hw struct
2046  * @mask: interrupt mask to be set
2047  * @cmd_details: pointer to command details structure or NULL
2048  *
2049  * Set link interrupt mask.
2050  **/
2051 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2052                                 u16 mask,
2053                                 struct i40e_asq_cmd_details *cmd_details)
2054 {
2055         struct i40e_aq_desc desc;
2056         struct i40e_aqc_set_phy_int_mask *cmd =
2057                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2058         enum i40e_status_code status;
2059
2060         i40e_fill_default_direct_cmd_desc(&desc,
2061                                           i40e_aqc_opc_set_phy_int_mask);
2062
2063         cmd->event_mask = CPU_TO_LE16(mask);
2064
2065         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2066
2067         return status;
2068 }
2069
2070 /**
2071  * i40e_aq_get_local_advt_reg
2072  * @hw: pointer to the hw struct
2073  * @advt_reg: local AN advertisement register value
2074  * @cmd_details: pointer to command details structure or NULL
2075  *
2076  * Get the Local AN advertisement register value.
2077  **/
2078 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2079                                 u64 *advt_reg,
2080                                 struct i40e_asq_cmd_details *cmd_details)
2081 {
2082         struct i40e_aq_desc desc;
2083         struct i40e_aqc_an_advt_reg *resp =
2084                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2085         enum i40e_status_code status;
2086
2087         i40e_fill_default_direct_cmd_desc(&desc,
2088                                           i40e_aqc_opc_get_local_advt_reg);
2089
2090         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2091
2092         if (status != I40E_SUCCESS)
2093                 goto aq_get_local_advt_reg_exit;
2094
2095         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2096         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2097
2098 aq_get_local_advt_reg_exit:
2099         return status;
2100 }
2101
2102 /**
2103  * i40e_aq_set_local_advt_reg
2104  * @hw: pointer to the hw struct
2105  * @advt_reg: local AN advertisement register value
2106  * @cmd_details: pointer to command details structure or NULL
2107  *
2108  * Get the Local AN advertisement register value.
2109  **/
2110 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2111                                 u64 advt_reg,
2112                                 struct i40e_asq_cmd_details *cmd_details)
2113 {
2114         struct i40e_aq_desc desc;
2115         struct i40e_aqc_an_advt_reg *cmd =
2116                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2117         enum i40e_status_code status;
2118
2119         i40e_fill_default_direct_cmd_desc(&desc,
2120                                           i40e_aqc_opc_get_local_advt_reg);
2121
2122         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2123         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2124
2125         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2126
2127         return status;
2128 }
2129
2130 /**
2131  * i40e_aq_get_partner_advt
2132  * @hw: pointer to the hw struct
2133  * @advt_reg: AN partner advertisement register value
2134  * @cmd_details: pointer to command details structure or NULL
2135  *
2136  * Get the link partner AN advertisement register value.
2137  **/
2138 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2139                                 u64 *advt_reg,
2140                                 struct i40e_asq_cmd_details *cmd_details)
2141 {
2142         struct i40e_aq_desc desc;
2143         struct i40e_aqc_an_advt_reg *resp =
2144                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2145         enum i40e_status_code status;
2146
2147         i40e_fill_default_direct_cmd_desc(&desc,
2148                                           i40e_aqc_opc_get_partner_advt);
2149
2150         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2151
2152         if (status != I40E_SUCCESS)
2153                 goto aq_get_partner_advt_exit;
2154
2155         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2156         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2157
2158 aq_get_partner_advt_exit:
2159         return status;
2160 }
2161
2162 /**
2163  * i40e_aq_set_lb_modes
2164  * @hw: pointer to the hw struct
2165  * @lb_modes: loopback mode to be set
2166  * @cmd_details: pointer to command details structure or NULL
2167  *
2168  * Sets loopback modes.
2169  **/
2170 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2171                                 u16 lb_modes,
2172                                 struct i40e_asq_cmd_details *cmd_details)
2173 {
2174         struct i40e_aq_desc desc;
2175         struct i40e_aqc_set_lb_mode *cmd =
2176                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2177         enum i40e_status_code status;
2178
2179         i40e_fill_default_direct_cmd_desc(&desc,
2180                                           i40e_aqc_opc_set_lb_modes);
2181
2182         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2183
2184         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2185
2186         return status;
2187 }
2188
2189 /**
2190  * i40e_aq_set_phy_debug
2191  * @hw: pointer to the hw struct
2192  * @cmd_flags: debug command flags
2193  * @cmd_details: pointer to command details structure or NULL
2194  *
2195  * Reset the external PHY.
2196  **/
2197 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2198                                 struct i40e_asq_cmd_details *cmd_details)
2199 {
2200         struct i40e_aq_desc desc;
2201         struct i40e_aqc_set_phy_debug *cmd =
2202                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2203         enum i40e_status_code status;
2204
2205         i40e_fill_default_direct_cmd_desc(&desc,
2206                                           i40e_aqc_opc_set_phy_debug);
2207
2208         cmd->command_flags = cmd_flags;
2209
2210         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2211
2212         return status;
2213 }
2214
2215 /**
2216  * i40e_aq_add_vsi
2217  * @hw: pointer to the hw struct
2218  * @vsi_ctx: pointer to a vsi context struct
2219  * @cmd_details: pointer to command details structure or NULL
2220  *
2221  * Add a VSI context to the hardware.
2222 **/
2223 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2224                                 struct i40e_vsi_context *vsi_ctx,
2225                                 struct i40e_asq_cmd_details *cmd_details)
2226 {
2227         struct i40e_aq_desc desc;
2228         struct i40e_aqc_add_get_update_vsi *cmd =
2229                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2230         struct i40e_aqc_add_get_update_vsi_completion *resp =
2231                 (struct i40e_aqc_add_get_update_vsi_completion *)
2232                 &desc.params.raw;
2233         enum i40e_status_code status;
2234
2235         i40e_fill_default_direct_cmd_desc(&desc,
2236                                           i40e_aqc_opc_add_vsi);
2237
2238         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2239         cmd->connection_type = vsi_ctx->connection_type;
2240         cmd->vf_id = vsi_ctx->vf_num;
2241         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2242
2243         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2244
2245         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2246                                     sizeof(vsi_ctx->info), cmd_details);
2247
2248         if (status != I40E_SUCCESS)
2249                 goto aq_add_vsi_exit;
2250
2251         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2252         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2253         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2254         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2255
2256 aq_add_vsi_exit:
2257         return status;
2258 }
2259
2260 /**
2261  * i40e_aq_set_default_vsi
2262  * @hw: pointer to the hw struct
2263  * @seid: vsi number
2264  * @cmd_details: pointer to command details structure or NULL
2265  **/
2266 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2267                                 u16 seid,
2268                                 struct i40e_asq_cmd_details *cmd_details)
2269 {
2270         struct i40e_aq_desc desc;
2271         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2272                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2273                 &desc.params.raw;
2274         enum i40e_status_code status;
2275
2276         i40e_fill_default_direct_cmd_desc(&desc,
2277                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2278
2279         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2280         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2281         cmd->seid = CPU_TO_LE16(seid);
2282
2283         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2284
2285         return status;
2286 }
2287
2288 /**
2289  * i40e_aq_clear_default_vsi
2290  * @hw: pointer to the hw struct
2291  * @seid: vsi number
2292  * @cmd_details: pointer to command details structure or NULL
2293  **/
2294 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2295                                 u16 seid,
2296                                 struct i40e_asq_cmd_details *cmd_details)
2297 {
2298         struct i40e_aq_desc desc;
2299         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2300                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2301                 &desc.params.raw;
2302         enum i40e_status_code status;
2303
2304         i40e_fill_default_direct_cmd_desc(&desc,
2305                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2306
2307         cmd->promiscuous_flags = CPU_TO_LE16(0);
2308         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2309         cmd->seid = CPU_TO_LE16(seid);
2310
2311         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2312
2313         return status;
2314 }
2315
2316 /**
2317  * i40e_aq_set_vsi_unicast_promiscuous
2318  * @hw: pointer to the hw struct
2319  * @seid: vsi number
2320  * @set: set unicast promiscuous enable/disable
2321  * @cmd_details: pointer to command details structure or NULL
2322  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2323  **/
2324 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2325                                 u16 seid, bool set,
2326                                 struct i40e_asq_cmd_details *cmd_details,
2327                                 bool rx_only_promisc)
2328 {
2329         struct i40e_aq_desc desc;
2330         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2331                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2332         enum i40e_status_code status;
2333         u16 flags = 0;
2334
2335         i40e_fill_default_direct_cmd_desc(&desc,
2336                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2337
2338         if (set) {
2339                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2340                 if (rx_only_promisc &&
2341                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2342                      (hw->aq.api_maj_ver > 1)))
2343                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2344         }
2345
2346         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2347
2348         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2349         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2350              (hw->aq.api_maj_ver > 1))
2351                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2352
2353         cmd->seid = CPU_TO_LE16(seid);
2354         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2355
2356         return status;
2357 }
2358
2359 /**
2360  * i40e_aq_set_vsi_multicast_promiscuous
2361  * @hw: pointer to the hw struct
2362  * @seid: vsi number
2363  * @set: set multicast promiscuous enable/disable
2364  * @cmd_details: pointer to command details structure or NULL
2365  **/
2366 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2367                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2368 {
2369         struct i40e_aq_desc desc;
2370         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2371                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2372         enum i40e_status_code status;
2373         u16 flags = 0;
2374
2375         i40e_fill_default_direct_cmd_desc(&desc,
2376                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2377
2378         if (set)
2379                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2380
2381         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2382
2383         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2384
2385         cmd->seid = CPU_TO_LE16(seid);
2386         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2387
2388         return status;
2389 }
2390
2391 /**
2392 * i40e_aq_set_vsi_full_promiscuous
2393 * @hw: pointer to the hw struct
2394 * @seid: VSI number
2395 * @set: set promiscuous enable/disable
2396 * @cmd_details: pointer to command details structure or NULL
2397 **/
2398 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2399                                 u16 seid, bool set,
2400                                 struct i40e_asq_cmd_details *cmd_details)
2401 {
2402         struct i40e_aq_desc desc;
2403         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2404                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2405         enum i40e_status_code status;
2406         u16 flags = 0;
2407
2408         i40e_fill_default_direct_cmd_desc(&desc,
2409                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2410
2411         if (set)
2412                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2413                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2414                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2415
2416         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2417
2418         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2419                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2420                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2421
2422         cmd->seid = CPU_TO_LE16(seid);
2423         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2424
2425         return status;
2426 }
2427
2428 /**
2429  * i40e_aq_set_vsi_mc_promisc_on_vlan
2430  * @hw: pointer to the hw struct
2431  * @seid: vsi number
2432  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2433  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2434  * @cmd_details: pointer to command details structure or NULL
2435  **/
2436 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2437                                 u16 seid, bool enable, u16 vid,
2438                                 struct i40e_asq_cmd_details *cmd_details)
2439 {
2440         struct i40e_aq_desc desc;
2441         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2442                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2443         enum i40e_status_code status;
2444         u16 flags = 0;
2445
2446         i40e_fill_default_direct_cmd_desc(&desc,
2447                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2448
2449         if (enable)
2450                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2451
2452         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2453         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2454         cmd->seid = CPU_TO_LE16(seid);
2455         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2456
2457         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2458
2459         return status;
2460 }
2461
2462 /**
2463  * i40e_aq_set_vsi_uc_promisc_on_vlan
2464  * @hw: pointer to the hw struct
2465  * @seid: vsi number
2466  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2467  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2468  * @cmd_details: pointer to command details structure or NULL
2469  **/
2470 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2471                                 u16 seid, bool enable, u16 vid,
2472                                 struct i40e_asq_cmd_details *cmd_details)
2473 {
2474         struct i40e_aq_desc desc;
2475         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2476                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2477         enum i40e_status_code status;
2478         u16 flags = 0;
2479
2480         i40e_fill_default_direct_cmd_desc(&desc,
2481                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2482
2483         if (enable)
2484                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2485
2486         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2487         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2488         cmd->seid = CPU_TO_LE16(seid);
2489         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2490
2491         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2492
2493         return status;
2494 }
2495
2496 /**
2497  * i40e_aq_set_vsi_bc_promisc_on_vlan
2498  * @hw: pointer to the hw struct
2499  * @seid: vsi number
2500  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2501  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2502  * @cmd_details: pointer to command details structure or NULL
2503  **/
2504 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2505                                 u16 seid, bool enable, u16 vid,
2506                                 struct i40e_asq_cmd_details *cmd_details)
2507 {
2508         struct i40e_aq_desc desc;
2509         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2510                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2511         enum i40e_status_code status;
2512         u16 flags = 0;
2513
2514         i40e_fill_default_direct_cmd_desc(&desc,
2515                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2516
2517         if (enable)
2518                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2519
2520         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2521         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2522         cmd->seid = CPU_TO_LE16(seid);
2523         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2524
2525         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2526
2527         return status;
2528 }
2529
2530 /**
2531  * i40e_aq_set_vsi_broadcast
2532  * @hw: pointer to the hw struct
2533  * @seid: vsi number
2534  * @set_filter: true to set filter, false to clear filter
2535  * @cmd_details: pointer to command details structure or NULL
2536  *
2537  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2538  **/
2539 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2540                                 u16 seid, bool set_filter,
2541                                 struct i40e_asq_cmd_details *cmd_details)
2542 {
2543         struct i40e_aq_desc desc;
2544         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2545                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2546         enum i40e_status_code status;
2547
2548         i40e_fill_default_direct_cmd_desc(&desc,
2549                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2550
2551         if (set_filter)
2552                 cmd->promiscuous_flags
2553                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2554         else
2555                 cmd->promiscuous_flags
2556                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2557
2558         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2559         cmd->seid = CPU_TO_LE16(seid);
2560         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2561
2562         return status;
2563 }
2564
2565 /**
2566  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2567  * @hw: pointer to the hw struct
2568  * @seid: vsi number
2569  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2570  * @cmd_details: pointer to command details structure or NULL
2571  **/
2572 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2573                                 u16 seid, bool enable,
2574                                 struct i40e_asq_cmd_details *cmd_details)
2575 {
2576         struct i40e_aq_desc desc;
2577         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2578                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2579         enum i40e_status_code status;
2580         u16 flags = 0;
2581
2582         i40e_fill_default_direct_cmd_desc(&desc,
2583                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2584         if (enable)
2585                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2586
2587         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2588         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2589         cmd->seid = CPU_TO_LE16(seid);
2590
2591         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2592
2593         return status;
2594 }
2595
2596 /**
2597  * i40e_get_vsi_params - get VSI configuration info
2598  * @hw: pointer to the hw struct
2599  * @vsi_ctx: pointer to a vsi context struct
2600  * @cmd_details: pointer to command details structure or NULL
2601  **/
2602 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2603                                 struct i40e_vsi_context *vsi_ctx,
2604                                 struct i40e_asq_cmd_details *cmd_details)
2605 {
2606         struct i40e_aq_desc desc;
2607         struct i40e_aqc_add_get_update_vsi *cmd =
2608                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2609         struct i40e_aqc_add_get_update_vsi_completion *resp =
2610                 (struct i40e_aqc_add_get_update_vsi_completion *)
2611                 &desc.params.raw;
2612         enum i40e_status_code status;
2613
2614         UNREFERENCED_1PARAMETER(cmd_details);
2615         i40e_fill_default_direct_cmd_desc(&desc,
2616                                           i40e_aqc_opc_get_vsi_parameters);
2617
2618         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2619
2620         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2621
2622         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2623                                     sizeof(vsi_ctx->info), NULL);
2624
2625         if (status != I40E_SUCCESS)
2626                 goto aq_get_vsi_params_exit;
2627
2628         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2629         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2630         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2631         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2632
2633 aq_get_vsi_params_exit:
2634         return status;
2635 }
2636
2637 /**
2638  * i40e_aq_update_vsi_params
2639  * @hw: pointer to the hw struct
2640  * @vsi_ctx: pointer to a vsi context struct
2641  * @cmd_details: pointer to command details structure or NULL
2642  *
2643  * Update a VSI context.
2644  **/
2645 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2646                                 struct i40e_vsi_context *vsi_ctx,
2647                                 struct i40e_asq_cmd_details *cmd_details)
2648 {
2649         struct i40e_aq_desc desc;
2650         struct i40e_aqc_add_get_update_vsi *cmd =
2651                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2652         struct i40e_aqc_add_get_update_vsi_completion *resp =
2653                 (struct i40e_aqc_add_get_update_vsi_completion *)
2654                 &desc.params.raw;
2655         enum i40e_status_code status;
2656
2657         i40e_fill_default_direct_cmd_desc(&desc,
2658                                           i40e_aqc_opc_update_vsi_parameters);
2659         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2660
2661         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2662
2663         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2664                                     sizeof(vsi_ctx->info), cmd_details);
2665
2666         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2667         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2668
2669         return status;
2670 }
2671
2672 /**
2673  * i40e_aq_get_switch_config
2674  * @hw: pointer to the hardware structure
2675  * @buf: pointer to the result buffer
2676  * @buf_size: length of input buffer
2677  * @start_seid: seid to start for the report, 0 == beginning
2678  * @cmd_details: pointer to command details structure or NULL
2679  *
2680  * Fill the buf with switch configuration returned from AdminQ command
2681  **/
2682 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2683                                 struct i40e_aqc_get_switch_config_resp *buf,
2684                                 u16 buf_size, u16 *start_seid,
2685                                 struct i40e_asq_cmd_details *cmd_details)
2686 {
2687         struct i40e_aq_desc desc;
2688         struct i40e_aqc_switch_seid *scfg =
2689                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2690         enum i40e_status_code status;
2691
2692         i40e_fill_default_direct_cmd_desc(&desc,
2693                                           i40e_aqc_opc_get_switch_config);
2694         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2695         if (buf_size > I40E_AQ_LARGE_BUF)
2696                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2697         scfg->seid = CPU_TO_LE16(*start_seid);
2698
2699         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2700         *start_seid = LE16_TO_CPU(scfg->seid);
2701
2702         return status;
2703 }
2704
2705 /**
2706  * i40e_aq_set_switch_config
2707  * @hw: pointer to the hardware structure
2708  * @flags: bit flag values to set
2709  * @valid_flags: which bit flags to set
2710  * @cmd_details: pointer to command details structure or NULL
2711  *
2712  * Set switch configuration bits
2713  **/
2714 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2715                                 u16 flags, u16 valid_flags,
2716                                 struct i40e_asq_cmd_details *cmd_details)
2717 {
2718         struct i40e_aq_desc desc;
2719         struct i40e_aqc_set_switch_config *scfg =
2720                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2721         enum i40e_status_code status;
2722
2723         i40e_fill_default_direct_cmd_desc(&desc,
2724                                           i40e_aqc_opc_set_switch_config);
2725         scfg->flags = CPU_TO_LE16(flags);
2726         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2727         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2728                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2729                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2730                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2731         }
2732         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2733
2734         return status;
2735 }
2736
2737 /**
2738  * i40e_aq_get_firmware_version
2739  * @hw: pointer to the hw struct
2740  * @fw_major_version: firmware major version
2741  * @fw_minor_version: firmware minor version
2742  * @fw_build: firmware build number
2743  * @api_major_version: major queue version
2744  * @api_minor_version: minor queue version
2745  * @cmd_details: pointer to command details structure or NULL
2746  *
2747  * Get the firmware version from the admin queue commands
2748  **/
2749 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2750                                 u16 *fw_major_version, u16 *fw_minor_version,
2751                                 u32 *fw_build,
2752                                 u16 *api_major_version, u16 *api_minor_version,
2753                                 struct i40e_asq_cmd_details *cmd_details)
2754 {
2755         struct i40e_aq_desc desc;
2756         struct i40e_aqc_get_version *resp =
2757                 (struct i40e_aqc_get_version *)&desc.params.raw;
2758         enum i40e_status_code status;
2759
2760         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2761
2762         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2763
2764         if (status == I40E_SUCCESS) {
2765                 if (fw_major_version != NULL)
2766                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2767                 if (fw_minor_version != NULL)
2768                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2769                 if (fw_build != NULL)
2770                         *fw_build = LE32_TO_CPU(resp->fw_build);
2771                 if (api_major_version != NULL)
2772                         *api_major_version = LE16_TO_CPU(resp->api_major);
2773                 if (api_minor_version != NULL)
2774                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2775
2776                 /* A workaround to fix the API version in SW */
2777                 if (api_major_version && api_minor_version &&
2778                     fw_major_version && fw_minor_version &&
2779                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2780                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2781                      (*fw_major_version > 4)))
2782                         *api_minor_version = 2;
2783         }
2784
2785         return status;
2786 }
2787
2788 /**
2789  * i40e_aq_send_driver_version
2790  * @hw: pointer to the hw struct
2791  * @dv: driver's major, minor version
2792  * @cmd_details: pointer to command details structure or NULL
2793  *
2794  * Send the driver version to the firmware
2795  **/
2796 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2797                                 struct i40e_driver_version *dv,
2798                                 struct i40e_asq_cmd_details *cmd_details)
2799 {
2800         struct i40e_aq_desc desc;
2801         struct i40e_aqc_driver_version *cmd =
2802                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2803         enum i40e_status_code status;
2804         u16 len;
2805
2806         if (dv == NULL)
2807                 return I40E_ERR_PARAM;
2808
2809         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2810
2811         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2812         cmd->driver_major_ver = dv->major_version;
2813         cmd->driver_minor_ver = dv->minor_version;
2814         cmd->driver_build_ver = dv->build_version;
2815         cmd->driver_subbuild_ver = dv->subbuild_version;
2816
2817         len = 0;
2818         while (len < sizeof(dv->driver_string) &&
2819                (dv->driver_string[len] < 0x80) &&
2820                dv->driver_string[len])
2821                 len++;
2822         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2823                                        len, cmd_details);
2824
2825         return status;
2826 }
2827
2828 /**
2829  * i40e_get_link_status - get status of the HW network link
2830  * @hw: pointer to the hw struct
2831  * @link_up: pointer to bool (true/false = linkup/linkdown)
2832  *
2833  * Variable link_up true if link is up, false if link is down.
2834  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2835  *
2836  * Side effect: LinkStatusEvent reporting becomes enabled
2837  **/
2838 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2839 {
2840         enum i40e_status_code status = I40E_SUCCESS;
2841
2842         if (hw->phy.get_link_info) {
2843                 status = i40e_update_link_info(hw);
2844
2845                 if (status != I40E_SUCCESS)
2846                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2847                                    status);
2848         }
2849
2850         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2851
2852         return status;
2853 }
2854
2855 /**
2856  * i40e_updatelink_status - update status of the HW network link
2857  * @hw: pointer to the hw struct
2858  **/
2859 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2860 {
2861         struct i40e_aq_get_phy_abilities_resp abilities;
2862         enum i40e_status_code status = I40E_SUCCESS;
2863
2864         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2865         if (status)
2866                 return status;
2867
2868         /* extra checking needed to ensure link info to user is timely */
2869         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2870             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2871              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2872                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2873                                                       &abilities, NULL);
2874                 if (status)
2875                         return status;
2876
2877                 hw->phy.link_info.req_fec_info =
2878                         abilities.fec_cfg_curr_mod_ext_info &
2879                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2880
2881                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2882                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2883         }
2884         return status;
2885 }
2886
2887
2888 /**
2889  * i40e_get_link_speed
2890  * @hw: pointer to the hw struct
2891  *
2892  * Returns the link speed of the adapter.
2893  **/
2894 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2895 {
2896         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2897         enum i40e_status_code status = I40E_SUCCESS;
2898
2899         if (hw->phy.get_link_info) {
2900                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2901
2902                 if (status != I40E_SUCCESS)
2903                         goto i40e_link_speed_exit;
2904         }
2905
2906         speed = hw->phy.link_info.link_speed;
2907
2908 i40e_link_speed_exit:
2909         return speed;
2910 }
2911
2912 /**
2913  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2914  * @hw: pointer to the hw struct
2915  * @uplink_seid: the MAC or other gizmo SEID
2916  * @downlink_seid: the VSI SEID
2917  * @enabled_tc: bitmap of TCs to be enabled
2918  * @default_port: true for default port VSI, false for control port
2919  * @veb_seid: pointer to where to put the resulting VEB SEID
2920  * @enable_stats: true to turn on VEB stats
2921  * @cmd_details: pointer to command details structure or NULL
2922  *
2923  * This asks the FW to add a VEB between the uplink and downlink
2924  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2925  **/
2926 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2927                                 u16 downlink_seid, u8 enabled_tc,
2928                                 bool default_port, u16 *veb_seid,
2929                                 bool enable_stats,
2930                                 struct i40e_asq_cmd_details *cmd_details)
2931 {
2932         struct i40e_aq_desc desc;
2933         struct i40e_aqc_add_veb *cmd =
2934                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2935         struct i40e_aqc_add_veb_completion *resp =
2936                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2937         enum i40e_status_code status;
2938         u16 veb_flags = 0;
2939
2940         /* SEIDs need to either both be set or both be 0 for floating VEB */
2941         if (!!uplink_seid != !!downlink_seid)
2942                 return I40E_ERR_PARAM;
2943
2944         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2945
2946         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2947         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2948         cmd->enable_tcs = enabled_tc;
2949         if (!uplink_seid)
2950                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2951         if (default_port)
2952                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2953         else
2954                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2955
2956         /* reverse logic here: set the bitflag to disable the stats */
2957         if (!enable_stats)
2958                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2959
2960         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2961
2962         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2963
2964         if (!status && veb_seid)
2965                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2966
2967         return status;
2968 }
2969
2970 /**
2971  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2972  * @hw: pointer to the hw struct
2973  * @veb_seid: the SEID of the VEB to query
2974  * @switch_id: the uplink switch id
2975  * @floating: set to true if the VEB is floating
2976  * @statistic_index: index of the stats counter block for this VEB
2977  * @vebs_used: number of VEB's used by function
2978  * @vebs_free: total VEB's not reserved by any function
2979  * @cmd_details: pointer to command details structure or NULL
2980  *
2981  * This retrieves the parameters for a particular VEB, specified by
2982  * uplink_seid, and returns them to the caller.
2983  **/
2984 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2985                                 u16 veb_seid, u16 *switch_id,
2986                                 bool *floating, u16 *statistic_index,
2987                                 u16 *vebs_used, u16 *vebs_free,
2988                                 struct i40e_asq_cmd_details *cmd_details)
2989 {
2990         struct i40e_aq_desc desc;
2991         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2992                 (struct i40e_aqc_get_veb_parameters_completion *)
2993                 &desc.params.raw;
2994         enum i40e_status_code status;
2995
2996         if (veb_seid == 0)
2997                 return I40E_ERR_PARAM;
2998
2999         i40e_fill_default_direct_cmd_desc(&desc,
3000                                           i40e_aqc_opc_get_veb_parameters);
3001         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3002
3003         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3004         if (status)
3005                 goto get_veb_exit;
3006
3007         if (switch_id)
3008                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3009         if (statistic_index)
3010                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3011         if (vebs_used)
3012                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3013         if (vebs_free)
3014                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3015         if (floating) {
3016                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3017
3018                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3019                         *floating = true;
3020                 else
3021                         *floating = false;
3022         }
3023
3024 get_veb_exit:
3025         return status;
3026 }
3027
3028 /**
3029  * i40e_aq_add_macvlan
3030  * @hw: pointer to the hw struct
3031  * @seid: VSI for the mac address
3032  * @mv_list: list of macvlans to be added
3033  * @count: length of the list
3034  * @cmd_details: pointer to command details structure or NULL
3035  *
3036  * Add MAC/VLAN addresses to the HW filtering
3037  **/
3038 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3039                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3040                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3041 {
3042         struct i40e_aq_desc desc;
3043         struct i40e_aqc_macvlan *cmd =
3044                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3045         enum i40e_status_code status;
3046         u16 buf_size;
3047         int i;
3048
3049         if (count == 0 || !mv_list || !hw)
3050                 return I40E_ERR_PARAM;
3051
3052         buf_size = count * sizeof(*mv_list);
3053
3054         /* prep the rest of the request */
3055         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3056         cmd->num_addresses = CPU_TO_LE16(count);
3057         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3058         cmd->seid[1] = 0;
3059         cmd->seid[2] = 0;
3060
3061         for (i = 0; i < count; i++)
3062                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3063                         mv_list[i].flags |=
3064                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3065
3066         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3067         if (buf_size > I40E_AQ_LARGE_BUF)
3068                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3069
3070         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3071                                        cmd_details);
3072
3073         return status;
3074 }
3075
3076 /**
3077  * i40e_aq_remove_macvlan
3078  * @hw: pointer to the hw struct
3079  * @seid: VSI for the mac address
3080  * @mv_list: list of macvlans to be removed
3081  * @count: length of the list
3082  * @cmd_details: pointer to command details structure or NULL
3083  *
3084  * Remove MAC/VLAN addresses from the HW filtering
3085  **/
3086 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3087                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3088                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3089 {
3090         struct i40e_aq_desc desc;
3091         struct i40e_aqc_macvlan *cmd =
3092                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3093         enum i40e_status_code status;
3094         u16 buf_size;
3095
3096         if (count == 0 || !mv_list || !hw)
3097                 return I40E_ERR_PARAM;
3098
3099         buf_size = count * sizeof(*mv_list);
3100
3101         /* prep the rest of the request */
3102         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3103         cmd->num_addresses = CPU_TO_LE16(count);
3104         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3105         cmd->seid[1] = 0;
3106         cmd->seid[2] = 0;
3107
3108         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3109         if (buf_size > I40E_AQ_LARGE_BUF)
3110                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3111
3112         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3113                                        cmd_details);
3114
3115         return status;
3116 }
3117
3118 /**
3119  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3120  * @hw: pointer to the hw struct
3121  * @opcode: AQ opcode for add or delete mirror rule
3122  * @sw_seid: Switch SEID (to which rule refers)
3123  * @rule_type: Rule Type (ingress/egress/VLAN)
3124  * @id: Destination VSI SEID or Rule ID
3125  * @count: length of the list
3126  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3127  * @cmd_details: pointer to command details structure or NULL
3128  * @rule_id: Rule ID returned from FW
3129  * @rules_used: Number of rules used in internal switch
3130  * @rules_free: Number of rules free in internal switch
3131  *
3132  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3133  * VEBs/VEPA elements only
3134  **/
3135 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3136                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3137                         u16 count, __le16 *mr_list,
3138                         struct i40e_asq_cmd_details *cmd_details,
3139                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3140 {
3141         struct i40e_aq_desc desc;
3142         struct i40e_aqc_add_delete_mirror_rule *cmd =
3143                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3144         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3145         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3146         enum i40e_status_code status;
3147         u16 buf_size;
3148
3149         buf_size = count * sizeof(*mr_list);
3150
3151         /* prep the rest of the request */
3152         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3153         cmd->seid = CPU_TO_LE16(sw_seid);
3154         cmd->rule_type = CPU_TO_LE16(rule_type &
3155                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3156         cmd->num_entries = CPU_TO_LE16(count);
3157         /* Dest VSI for add, rule_id for delete */
3158         cmd->destination = CPU_TO_LE16(id);
3159         if (mr_list) {
3160                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3161                                                 I40E_AQ_FLAG_RD));
3162                 if (buf_size > I40E_AQ_LARGE_BUF)
3163                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3164         }
3165
3166         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3167                                        cmd_details);
3168         if (status == I40E_SUCCESS ||
3169             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3170                 if (rule_id)
3171                         *rule_id = LE16_TO_CPU(resp->rule_id);
3172                 if (rules_used)
3173                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3174                 if (rules_free)
3175                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3176         }
3177         return status;
3178 }
3179
3180 /**
3181  * i40e_aq_add_mirrorrule - add a mirror rule
3182  * @hw: pointer to the hw struct
3183  * @sw_seid: Switch SEID (to which rule refers)
3184  * @rule_type: Rule Type (ingress/egress/VLAN)
3185  * @dest_vsi: SEID of VSI to which packets will be mirrored
3186  * @count: length of the list
3187  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3188  * @cmd_details: pointer to command details structure or NULL
3189  * @rule_id: Rule ID returned from FW
3190  * @rules_used: Number of rules used in internal switch
3191  * @rules_free: Number of rules free in internal switch
3192  *
3193  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3194  **/
3195 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3196                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3197                         struct i40e_asq_cmd_details *cmd_details,
3198                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3199 {
3200         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3201             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3202                 if (count == 0 || !mr_list)
3203                         return I40E_ERR_PARAM;
3204         }
3205
3206         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3207                                   rule_type, dest_vsi, count, mr_list,
3208                                   cmd_details, rule_id, rules_used, rules_free);
3209 }
3210
3211 /**
3212  * i40e_aq_delete_mirrorrule - delete a mirror rule
3213  * @hw: pointer to the hw struct
3214  * @sw_seid: Switch SEID (to which rule refers)
3215  * @rule_type: Rule Type (ingress/egress/VLAN)
3216  * @count: length of the list
3217  * @rule_id: Rule ID that is returned in the receive desc as part of
3218  *              add_mirrorrule.
3219  * @mr_list: list of mirrored VLAN IDs to be removed
3220  * @cmd_details: pointer to command details structure or NULL
3221  * @rules_used: Number of rules used in internal switch
3222  * @rules_free: Number of rules free in internal switch
3223  *
3224  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3225  **/
3226 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3227                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3228                         struct i40e_asq_cmd_details *cmd_details,
3229                         u16 *rules_used, u16 *rules_free)
3230 {
3231         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3232         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3233                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3234                  * mirroring. For other rule_type, count and rule_type should
3235                  * not matter.
3236                  */
3237                 if (count == 0 || !mr_list)
3238                         return I40E_ERR_PARAM;
3239         }
3240
3241         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3242                                   rule_type, rule_id, count, mr_list,
3243                                   cmd_details, NULL, rules_used, rules_free);
3244 }
3245
3246 /**
3247  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3248  * @hw: pointer to the hw struct
3249  * @seid: VSI for the vlan filters
3250  * @v_list: list of vlan filters to be added
3251  * @count: length of the list
3252  * @cmd_details: pointer to command details structure or NULL
3253  **/
3254 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3255                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3256                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3257 {
3258         struct i40e_aq_desc desc;
3259         struct i40e_aqc_macvlan *cmd =
3260                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3261         enum i40e_status_code status;
3262         u16 buf_size;
3263
3264         if (count == 0 || !v_list || !hw)
3265                 return I40E_ERR_PARAM;
3266
3267         buf_size = count * sizeof(*v_list);
3268
3269         /* prep the rest of the request */
3270         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3271         cmd->num_addresses = CPU_TO_LE16(count);
3272         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3273         cmd->seid[1] = 0;
3274         cmd->seid[2] = 0;
3275
3276         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3277         if (buf_size > I40E_AQ_LARGE_BUF)
3278                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3279
3280         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3281                                        cmd_details);
3282
3283         return status;
3284 }
3285
3286 /**
3287  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3288  * @hw: pointer to the hw struct
3289  * @seid: VSI for the vlan filters
3290  * @v_list: list of macvlans to be removed
3291  * @count: length of the list
3292  * @cmd_details: pointer to command details structure or NULL
3293  **/
3294 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3295                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3296                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3297 {
3298         struct i40e_aq_desc desc;
3299         struct i40e_aqc_macvlan *cmd =
3300                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3301         enum i40e_status_code status;
3302         u16 buf_size;
3303
3304         if (count == 0 || !v_list || !hw)
3305                 return I40E_ERR_PARAM;
3306
3307         buf_size = count * sizeof(*v_list);
3308
3309         /* prep the rest of the request */
3310         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3311         cmd->num_addresses = CPU_TO_LE16(count);
3312         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3313         cmd->seid[1] = 0;
3314         cmd->seid[2] = 0;
3315
3316         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3317         if (buf_size > I40E_AQ_LARGE_BUF)
3318                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3319
3320         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3321                                        cmd_details);
3322
3323         return status;
3324 }
3325
3326 /**
3327  * i40e_aq_send_msg_to_vf
3328  * @hw: pointer to the hardware structure
3329  * @vfid: vf id to send msg
3330  * @v_opcode: opcodes for VF-PF communication
3331  * @v_retval: return error code
3332  * @msg: pointer to the msg buffer
3333  * @msglen: msg length
3334  * @cmd_details: pointer to command details
3335  *
3336  * send msg to vf
3337  **/
3338 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3339                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3340                                 struct i40e_asq_cmd_details *cmd_details)
3341 {
3342         struct i40e_aq_desc desc;
3343         struct i40e_aqc_pf_vf_message *cmd =
3344                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3345         enum i40e_status_code status;
3346
3347         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3348         cmd->id = CPU_TO_LE32(vfid);
3349         desc.cookie_high = CPU_TO_LE32(v_opcode);
3350         desc.cookie_low = CPU_TO_LE32(v_retval);
3351         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3352         if (msglen) {
3353                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3354                                                 I40E_AQ_FLAG_RD));
3355                 if (msglen > I40E_AQ_LARGE_BUF)
3356                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3357                 desc.datalen = CPU_TO_LE16(msglen);
3358         }
3359         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3360
3361         return status;
3362 }
3363
3364 /**
3365  * i40e_aq_debug_read_register
3366  * @hw: pointer to the hw struct
3367  * @reg_addr: register address
3368  * @reg_val: register value
3369  * @cmd_details: pointer to command details structure or NULL
3370  *
3371  * Read the register using the admin queue commands
3372  **/
3373 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3374                                 u32 reg_addr, u64 *reg_val,
3375                                 struct i40e_asq_cmd_details *cmd_details)
3376 {
3377         struct i40e_aq_desc desc;
3378         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3379                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3380         enum i40e_status_code status;
3381
3382         if (reg_val == NULL)
3383                 return I40E_ERR_PARAM;
3384
3385         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3386
3387         cmd_resp->address = CPU_TO_LE32(reg_addr);
3388
3389         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3390
3391         if (status == I40E_SUCCESS) {
3392                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3393                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3394         }
3395
3396         return status;
3397 }
3398
3399 /**
3400  * i40e_aq_debug_write_register
3401  * @hw: pointer to the hw struct
3402  * @reg_addr: register address
3403  * @reg_val: register value
3404  * @cmd_details: pointer to command details structure or NULL
3405  *
3406  * Write to a register using the admin queue commands
3407  **/
3408 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3409                                 u32 reg_addr, u64 reg_val,
3410                                 struct i40e_asq_cmd_details *cmd_details)
3411 {
3412         struct i40e_aq_desc desc;
3413         struct i40e_aqc_debug_reg_read_write *cmd =
3414                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3415         enum i40e_status_code status;
3416
3417         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3418
3419         cmd->address = CPU_TO_LE32(reg_addr);
3420         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3421         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3422
3423         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3424
3425         return status;
3426 }
3427
3428 /**
3429  * i40e_aq_request_resource
3430  * @hw: pointer to the hw struct
3431  * @resource: resource id
3432  * @access: access type
3433  * @sdp_number: resource number
3434  * @timeout: the maximum time in ms that the driver may hold the resource
3435  * @cmd_details: pointer to command details structure or NULL
3436  *
3437  * requests common resource using the admin queue commands
3438  **/
3439 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3440                                 enum i40e_aq_resources_ids resource,
3441                                 enum i40e_aq_resource_access_type access,
3442                                 u8 sdp_number, u64 *timeout,
3443                                 struct i40e_asq_cmd_details *cmd_details)
3444 {
3445         struct i40e_aq_desc desc;
3446         struct i40e_aqc_request_resource *cmd_resp =
3447                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3448         enum i40e_status_code status;
3449
3450         DEBUGFUNC("i40e_aq_request_resource");
3451
3452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3453
3454         cmd_resp->resource_id = CPU_TO_LE16(resource);
3455         cmd_resp->access_type = CPU_TO_LE16(access);
3456         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3457
3458         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3459         /* The completion specifies the maximum time in ms that the driver
3460          * may hold the resource in the Timeout field.
3461          * If the resource is held by someone else, the command completes with
3462          * busy return value and the timeout field indicates the maximum time
3463          * the current owner of the resource has to free it.
3464          */
3465         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3466                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3467
3468         return status;
3469 }
3470
3471 /**
3472  * i40e_aq_release_resource
3473  * @hw: pointer to the hw struct
3474  * @resource: resource id
3475  * @sdp_number: resource number
3476  * @cmd_details: pointer to command details structure or NULL
3477  *
3478  * release common resource using the admin queue commands
3479  **/
3480 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3481                                 enum i40e_aq_resources_ids resource,
3482                                 u8 sdp_number,
3483                                 struct i40e_asq_cmd_details *cmd_details)
3484 {
3485         struct i40e_aq_desc desc;
3486         struct i40e_aqc_request_resource *cmd =
3487                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3488         enum i40e_status_code status;
3489
3490         DEBUGFUNC("i40e_aq_release_resource");
3491
3492         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3493
3494         cmd->resource_id = CPU_TO_LE16(resource);
3495         cmd->resource_number = CPU_TO_LE32(sdp_number);
3496
3497         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3498
3499         return status;
3500 }
3501
3502 /**
3503  * i40e_aq_read_nvm
3504  * @hw: pointer to the hw struct
3505  * @module_pointer: module pointer location in words from the NVM beginning
3506  * @offset: byte offset from the module beginning
3507  * @length: length of the section to be read (in bytes from the offset)
3508  * @data: command buffer (size [bytes] = length)
3509  * @last_command: tells if this is the last command in a series
3510  * @cmd_details: pointer to command details structure or NULL
3511  *
3512  * Read the NVM using the admin queue commands
3513  **/
3514 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3515                                 u32 offset, u16 length, void *data,
3516                                 bool last_command,
3517                                 struct i40e_asq_cmd_details *cmd_details)
3518 {
3519         struct i40e_aq_desc desc;
3520         struct i40e_aqc_nvm_update *cmd =
3521                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3522         enum i40e_status_code status;
3523
3524         DEBUGFUNC("i40e_aq_read_nvm");
3525
3526         /* In offset the highest byte must be zeroed. */
3527         if (offset & 0xFF000000) {
3528                 status = I40E_ERR_PARAM;
3529                 goto i40e_aq_read_nvm_exit;
3530         }
3531
3532         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3533
3534         /* If this is the last command in a series, set the proper flag. */
3535         if (last_command)
3536                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3537         cmd->module_pointer = module_pointer;
3538         cmd->offset = CPU_TO_LE32(offset);
3539         cmd->length = CPU_TO_LE16(length);
3540
3541         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3542         if (length > I40E_AQ_LARGE_BUF)
3543                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3544
3545         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3546
3547 i40e_aq_read_nvm_exit:
3548         return status;
3549 }
3550
3551 /**
3552  * i40e_aq_read_nvm_config - read an nvm config block
3553  * @hw: pointer to the hw struct
3554  * @cmd_flags: NVM access admin command bits
3555  * @field_id: field or feature id
3556  * @data: buffer for result
3557  * @buf_size: buffer size
3558  * @element_count: pointer to count of elements read by FW
3559  * @cmd_details: pointer to command details structure or NULL
3560  **/
3561 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3562                                 u8 cmd_flags, u32 field_id, void *data,
3563                                 u16 buf_size, u16 *element_count,
3564                                 struct i40e_asq_cmd_details *cmd_details)
3565 {
3566         struct i40e_aq_desc desc;
3567         struct i40e_aqc_nvm_config_read *cmd =
3568                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3569         enum i40e_status_code status;
3570
3571         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3572         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3573         if (buf_size > I40E_AQ_LARGE_BUF)
3574                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3575
3576         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3577         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3578         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3579                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3580         else
3581                 cmd->element_id_msw = 0;
3582
3583         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3584
3585         if (!status && element_count)
3586                 *element_count = LE16_TO_CPU(cmd->element_count);
3587
3588         return status;
3589 }
3590
3591 /**
3592  * i40e_aq_write_nvm_config - write an nvm config block
3593  * @hw: pointer to the hw struct
3594  * @cmd_flags: NVM access admin command bits
3595  * @data: buffer for result
3596  * @buf_size: buffer size
3597  * @element_count: count of elements to be written
3598  * @cmd_details: pointer to command details structure or NULL
3599  **/
3600 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3601                                 u8 cmd_flags, void *data, u16 buf_size,
3602                                 u16 element_count,
3603                                 struct i40e_asq_cmd_details *cmd_details)
3604 {
3605         struct i40e_aq_desc desc;
3606         struct i40e_aqc_nvm_config_write *cmd =
3607                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3608         enum i40e_status_code status;
3609
3610         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3611         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3612         if (buf_size > I40E_AQ_LARGE_BUF)
3613                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3614
3615         cmd->element_count = CPU_TO_LE16(element_count);
3616         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3617         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3618
3619         return status;
3620 }
3621
3622 /**
3623  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3624  * @hw: pointer to the hw struct
3625  * @buff: buffer for result
3626  * @buff_size: buffer size
3627  * @cmd_details: pointer to command details structure or NULL
3628  **/
3629 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3630                                 void *buff, u16 buff_size,
3631                                 struct i40e_asq_cmd_details *cmd_details)
3632 {
3633         struct i40e_aq_desc desc;
3634         enum i40e_status_code status;
3635
3636         UNREFERENCED_2PARAMETER(buff, buff_size);
3637
3638         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3639         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3640         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3641                 status = I40E_ERR_NOT_IMPLEMENTED;
3642
3643         return status;
3644 }
3645
3646 /**
3647  * i40e_aq_erase_nvm
3648  * @hw: pointer to the hw struct
3649  * @module_pointer: module pointer location in words from the NVM beginning
3650  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3651  * @length: length of the section to be erased (expressed in 4 KB)
3652  * @last_command: tells if this is the last command in a series
3653  * @cmd_details: pointer to command details structure or NULL
3654  *
3655  * Erase the NVM sector using the admin queue commands
3656  **/
3657 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3658                                 u32 offset, u16 length, bool last_command,
3659                                 struct i40e_asq_cmd_details *cmd_details)
3660 {
3661         struct i40e_aq_desc desc;
3662         struct i40e_aqc_nvm_update *cmd =
3663                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3664         enum i40e_status_code status;
3665
3666         DEBUGFUNC("i40e_aq_erase_nvm");
3667
3668         /* In offset the highest byte must be zeroed. */
3669         if (offset & 0xFF000000) {
3670                 status = I40E_ERR_PARAM;
3671                 goto i40e_aq_erase_nvm_exit;
3672         }
3673
3674         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3675
3676         /* If this is the last command in a series, set the proper flag. */
3677         if (last_command)
3678                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3679         cmd->module_pointer = module_pointer;
3680         cmd->offset = CPU_TO_LE32(offset);
3681         cmd->length = CPU_TO_LE16(length);
3682
3683         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3684
3685 i40e_aq_erase_nvm_exit:
3686         return status;
3687 }
3688
3689 /**
3690  * i40e_parse_discover_capabilities
3691  * @hw: pointer to the hw struct
3692  * @buff: pointer to a buffer containing device/function capability records
3693  * @cap_count: number of capability records in the list
3694  * @list_type_opc: type of capabilities list to parse
3695  *
3696  * Parse the device/function capabilities list.
3697  **/
3698 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3699                                      u32 cap_count,
3700                                      enum i40e_admin_queue_opc list_type_opc)
3701 {
3702         struct i40e_aqc_list_capabilities_element_resp *cap;
3703         u32 valid_functions, num_functions;
3704         u32 number, logical_id, phys_id;
3705         struct i40e_hw_capabilities *p;
3706         u8 major_rev;
3707         u32 i = 0;
3708         u16 id;
3709
3710         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3711
3712         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3713                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3714         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3715                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3716         else
3717                 return;
3718
3719         for (i = 0; i < cap_count; i++, cap++) {
3720                 id = LE16_TO_CPU(cap->id);
3721                 number = LE32_TO_CPU(cap->number);
3722                 logical_id = LE32_TO_CPU(cap->logical_id);
3723                 phys_id = LE32_TO_CPU(cap->phys_id);
3724                 major_rev = cap->major_rev;
3725
3726                 switch (id) {
3727                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3728                         p->switch_mode = number;
3729                         i40e_debug(hw, I40E_DEBUG_INIT,
3730                                    "HW Capability: Switch mode = %d\n",
3731                                    p->switch_mode);
3732                         break;
3733                 case I40E_AQ_CAP_ID_MNG_MODE:
3734                         p->management_mode = number;
3735                         if (major_rev > 1) {
3736                                 p->mng_protocols_over_mctp = logical_id;
3737                                 i40e_debug(hw, I40E_DEBUG_INIT,
3738                                            "HW Capability: Protocols over MCTP = %d\n",
3739                                            p->mng_protocols_over_mctp);
3740                         } else {
3741                                 p->mng_protocols_over_mctp = 0;
3742                         }
3743                         i40e_debug(hw, I40E_DEBUG_INIT,
3744                                    "HW Capability: Management Mode = %d\n",
3745                                    p->management_mode);
3746                         break;
3747                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3748                         p->npar_enable = number;
3749                         i40e_debug(hw, I40E_DEBUG_INIT,
3750                                    "HW Capability: NPAR enable = %d\n",
3751                                    p->npar_enable);
3752                         break;
3753                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3754                         p->os2bmc = number;
3755                         i40e_debug(hw, I40E_DEBUG_INIT,
3756                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3757                         break;
3758                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3759                         p->valid_functions = number;
3760                         i40e_debug(hw, I40E_DEBUG_INIT,
3761                                    "HW Capability: Valid Functions = %d\n",
3762                                    p->valid_functions);
3763                         break;
3764                 case I40E_AQ_CAP_ID_SRIOV:
3765                         if (number == 1)
3766                                 p->sr_iov_1_1 = true;
3767                         i40e_debug(hw, I40E_DEBUG_INIT,
3768                                    "HW Capability: SR-IOV = %d\n",
3769                                    p->sr_iov_1_1);
3770                         break;
3771                 case I40E_AQ_CAP_ID_VF:
3772                         p->num_vfs = number;
3773                         p->vf_base_id = logical_id;
3774                         i40e_debug(hw, I40E_DEBUG_INIT,
3775                                    "HW Capability: VF count = %d\n",
3776                                    p->num_vfs);
3777                         i40e_debug(hw, I40E_DEBUG_INIT,
3778                                    "HW Capability: VF base_id = %d\n",
3779                                    p->vf_base_id);
3780                         break;
3781                 case I40E_AQ_CAP_ID_VMDQ:
3782                         if (number == 1)
3783                                 p->vmdq = true;
3784                         i40e_debug(hw, I40E_DEBUG_INIT,
3785                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3786                         break;
3787                 case I40E_AQ_CAP_ID_8021QBG:
3788                         if (number == 1)
3789                                 p->evb_802_1_qbg = true;
3790                         i40e_debug(hw, I40E_DEBUG_INIT,
3791                                    "HW Capability: 802.1Qbg = %d\n", number);
3792                         break;
3793                 case I40E_AQ_CAP_ID_8021QBR:
3794                         if (number == 1)
3795                                 p->evb_802_1_qbh = true;
3796                         i40e_debug(hw, I40E_DEBUG_INIT,
3797                                    "HW Capability: 802.1Qbh = %d\n", number);
3798                         break;
3799                 case I40E_AQ_CAP_ID_VSI:
3800                         p->num_vsis = number;
3801                         i40e_debug(hw, I40E_DEBUG_INIT,
3802                                    "HW Capability: VSI count = %d\n",
3803                                    p->num_vsis);
3804                         break;
3805                 case I40E_AQ_CAP_ID_DCB:
3806                         if (number == 1) {
3807                                 p->dcb = true;
3808                                 p->enabled_tcmap = logical_id;
3809                                 p->maxtc = phys_id;
3810                         }
3811                         i40e_debug(hw, I40E_DEBUG_INIT,
3812                                    "HW Capability: DCB = %d\n", p->dcb);
3813                         i40e_debug(hw, I40E_DEBUG_INIT,
3814                                    "HW Capability: TC Mapping = %d\n",
3815                                    logical_id);
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: TC Max = %d\n", p->maxtc);
3818                         break;
3819                 case I40E_AQ_CAP_ID_FCOE:
3820                         if (number == 1)
3821                                 p->fcoe = true;
3822                         i40e_debug(hw, I40E_DEBUG_INIT,
3823                                    "HW Capability: FCOE = %d\n", p->fcoe);
3824                         break;
3825                 case I40E_AQ_CAP_ID_ISCSI:
3826                         if (number == 1)
3827                                 p->iscsi = true;
3828                         i40e_debug(hw, I40E_DEBUG_INIT,
3829                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3830                         break;
3831                 case I40E_AQ_CAP_ID_RSS:
3832                         p->rss = true;
3833                         p->rss_table_size = number;
3834                         p->rss_table_entry_width = logical_id;
3835                         i40e_debug(hw, I40E_DEBUG_INIT,
3836                                    "HW Capability: RSS = %d\n", p->rss);
3837                         i40e_debug(hw, I40E_DEBUG_INIT,
3838                                    "HW Capability: RSS table size = %d\n",
3839                                    p->rss_table_size);
3840                         i40e_debug(hw, I40E_DEBUG_INIT,
3841                                    "HW Capability: RSS table width = %d\n",
3842                                    p->rss_table_entry_width);
3843                         break;
3844                 case I40E_AQ_CAP_ID_RXQ:
3845                         p->num_rx_qp = number;
3846                         p->base_queue = phys_id;
3847                         i40e_debug(hw, I40E_DEBUG_INIT,
3848                                    "HW Capability: Rx QP = %d\n", number);
3849                         i40e_debug(hw, I40E_DEBUG_INIT,
3850                                    "HW Capability: base_queue = %d\n",
3851                                    p->base_queue);
3852                         break;
3853                 case I40E_AQ_CAP_ID_TXQ:
3854                         p->num_tx_qp = number;
3855                         p->base_queue = phys_id;
3856                         i40e_debug(hw, I40E_DEBUG_INIT,
3857                                    "HW Capability: Tx QP = %d\n", number);
3858                         i40e_debug(hw, I40E_DEBUG_INIT,
3859                                    "HW Capability: base_queue = %d\n",
3860                                    p->base_queue);
3861                         break;
3862                 case I40E_AQ_CAP_ID_MSIX:
3863                         p->num_msix_vectors = number;
3864                         i40e_debug(hw, I40E_DEBUG_INIT,
3865                                    "HW Capability: MSIX vector count = %d\n",
3866                                    p->num_msix_vectors);
3867                         break;
3868                 case I40E_AQ_CAP_ID_VF_MSIX:
3869                         p->num_msix_vectors_vf = number;
3870                         i40e_debug(hw, I40E_DEBUG_INIT,
3871                                    "HW Capability: MSIX VF vector count = %d\n",
3872                                    p->num_msix_vectors_vf);
3873                         break;
3874                 case I40E_AQ_CAP_ID_FLEX10:
3875                         if (major_rev == 1) {
3876                                 if (number == 1) {
3877                                         p->flex10_enable = true;
3878                                         p->flex10_capable = true;
3879                                 }
3880                         } else {
3881                                 /* Capability revision >= 2 */
3882                                 if (number & 1)
3883                                         p->flex10_enable = true;
3884                                 if (number & 2)
3885                                         p->flex10_capable = true;
3886                         }
3887                         p->flex10_mode = logical_id;
3888                         p->flex10_status = phys_id;
3889                         i40e_debug(hw, I40E_DEBUG_INIT,
3890                                    "HW Capability: Flex10 mode = %d\n",
3891                                    p->flex10_mode);
3892                         i40e_debug(hw, I40E_DEBUG_INIT,
3893                                    "HW Capability: Flex10 status = %d\n",
3894                                    p->flex10_status);
3895                         break;
3896                 case I40E_AQ_CAP_ID_CEM:
3897                         if (number == 1)
3898                                 p->mgmt_cem = true;
3899                         i40e_debug(hw, I40E_DEBUG_INIT,
3900                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3901                         break;
3902                 case I40E_AQ_CAP_ID_IWARP:
3903                         if (number == 1)
3904                                 p->iwarp = true;
3905                         i40e_debug(hw, I40E_DEBUG_INIT,
3906                                    "HW Capability: iWARP = %d\n", p->iwarp);
3907                         break;
3908                 case I40E_AQ_CAP_ID_LED:
3909                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3910                                 p->led[phys_id] = true;
3911                         i40e_debug(hw, I40E_DEBUG_INIT,
3912                                    "HW Capability: LED - PIN %d\n", phys_id);
3913                         break;
3914                 case I40E_AQ_CAP_ID_SDP:
3915                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3916                                 p->sdp[phys_id] = true;
3917                         i40e_debug(hw, I40E_DEBUG_INIT,
3918                                    "HW Capability: SDP - PIN %d\n", phys_id);
3919                         break;
3920                 case I40E_AQ_CAP_ID_MDIO:
3921                         if (number == 1) {
3922                                 p->mdio_port_num = phys_id;
3923                                 p->mdio_port_mode = logical_id;
3924                         }
3925                         i40e_debug(hw, I40E_DEBUG_INIT,
3926                                    "HW Capability: MDIO port number = %d\n",
3927                                    p->mdio_port_num);
3928                         i40e_debug(hw, I40E_DEBUG_INIT,
3929                                    "HW Capability: MDIO port mode = %d\n",
3930                                    p->mdio_port_mode);
3931                         break;
3932                 case I40E_AQ_CAP_ID_1588:
3933                         if (number == 1)
3934                                 p->ieee_1588 = true;
3935                         i40e_debug(hw, I40E_DEBUG_INIT,
3936                                    "HW Capability: IEEE 1588 = %d\n",
3937                                    p->ieee_1588);
3938                         break;
3939                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3940                         p->fd = true;
3941                         p->fd_filters_guaranteed = number;
3942                         p->fd_filters_best_effort = logical_id;
3943                         i40e_debug(hw, I40E_DEBUG_INIT,
3944                                    "HW Capability: Flow Director = 1\n");
3945                         i40e_debug(hw, I40E_DEBUG_INIT,
3946                                    "HW Capability: Guaranteed FD filters = %d\n",
3947                                    p->fd_filters_guaranteed);
3948                         break;
3949                 case I40E_AQ_CAP_ID_WSR_PROT:
3950                         p->wr_csr_prot = (u64)number;
3951                         p->wr_csr_prot |= (u64)logical_id << 32;
3952                         i40e_debug(hw, I40E_DEBUG_INIT,
3953                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3954                                    (p->wr_csr_prot & 0xffff));
3955                         break;
3956                 case I40E_AQ_CAP_ID_NVM_MGMT:
3957                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3958                                 p->sec_rev_disabled = true;
3959                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3960                                 p->update_disabled = true;
3961                         break;
3962                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3963                         hw->num_wol_proxy_filters = (u16)number;
3964                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3965                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3966                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3967                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3968                         else
3969                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3970                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3971                         i40e_debug(hw, I40E_DEBUG_INIT,
3972                                    "HW Capability: WOL proxy filters = %d\n",
3973                                    hw->num_wol_proxy_filters);
3974                         break;
3975                 default:
3976                         break;
3977                 }
3978         }
3979
3980         if (p->fcoe)
3981                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3982
3983         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3984         p->fcoe = false;
3985
3986         /* count the enabled ports (aka the "not disabled" ports) */
3987         hw->num_ports = 0;
3988         for (i = 0; i < 4; i++) {
3989                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3990                 u64 port_cfg = 0;
3991
3992                 /* use AQ read to get the physical register offset instead
3993                  * of the port relative offset
3994                  */
3995                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3996                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3997                         hw->num_ports++;
3998         }
3999
4000         valid_functions = p->valid_functions;
4001         num_functions = 0;
4002         while (valid_functions) {
4003                 if (valid_functions & 1)
4004                         num_functions++;
4005                 valid_functions >>= 1;
4006         }
4007
4008         /* partition id is 1-based, and functions are evenly spread
4009          * across the ports as partitions
4010          */
4011         if (hw->num_ports != 0) {
4012                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4013                 hw->num_partitions = num_functions / hw->num_ports;
4014         }
4015
4016         /* additional HW specific goodies that might
4017          * someday be HW version specific
4018          */
4019         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4020 }
4021
4022 /**
4023  * i40e_aq_discover_capabilities
4024  * @hw: pointer to the hw struct
4025  * @buff: a virtual buffer to hold the capabilities
4026  * @buff_size: Size of the virtual buffer
4027  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4028  * @list_type_opc: capabilities type to discover - pass in the command opcode
4029  * @cmd_details: pointer to command details structure or NULL
4030  *
4031  * Get the device capabilities descriptions from the firmware
4032  **/
4033 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4034                                 void *buff, u16 buff_size, u16 *data_size,
4035                                 enum i40e_admin_queue_opc list_type_opc,
4036                                 struct i40e_asq_cmd_details *cmd_details)
4037 {
4038         struct i40e_aqc_list_capabilites *cmd;
4039         struct i40e_aq_desc desc;
4040         enum i40e_status_code status = I40E_SUCCESS;
4041
4042         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4043
4044         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4045                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4046                 status = I40E_ERR_PARAM;
4047                 goto exit;
4048         }
4049
4050         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4051
4052         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4053         if (buff_size > I40E_AQ_LARGE_BUF)
4054                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4055
4056         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4057         *data_size = LE16_TO_CPU(desc.datalen);
4058
4059         if (status)
4060                 goto exit;
4061
4062         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4063                                          list_type_opc);
4064
4065 exit:
4066         return status;
4067 }
4068
4069 /**
4070  * i40e_aq_update_nvm
4071  * @hw: pointer to the hw struct
4072  * @module_pointer: module pointer location in words from the NVM beginning
4073  * @offset: byte offset from the module beginning
4074  * @length: length of the section to be written (in bytes from the offset)
4075  * @data: command buffer (size [bytes] = length)
4076  * @last_command: tells if this is the last command in a series
4077  * @cmd_details: pointer to command details structure or NULL
4078  *
4079  * Update the NVM using the admin queue commands
4080  **/
4081 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4082                                 u32 offset, u16 length, void *data,
4083                                 bool last_command,
4084                                 struct i40e_asq_cmd_details *cmd_details)
4085 {
4086         struct i40e_aq_desc desc;
4087         struct i40e_aqc_nvm_update *cmd =
4088                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4089         enum i40e_status_code status;
4090
4091         DEBUGFUNC("i40e_aq_update_nvm");
4092
4093         /* In offset the highest byte must be zeroed. */
4094         if (offset & 0xFF000000) {
4095                 status = I40E_ERR_PARAM;
4096                 goto i40e_aq_update_nvm_exit;
4097         }
4098
4099         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4100
4101         /* If this is the last command in a series, set the proper flag. */
4102         if (last_command)
4103                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4104         cmd->module_pointer = module_pointer;
4105         cmd->offset = CPU_TO_LE32(offset);
4106         cmd->length = CPU_TO_LE16(length);
4107
4108         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4109         if (length > I40E_AQ_LARGE_BUF)
4110                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4111
4112         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4113
4114 i40e_aq_update_nvm_exit:
4115         return status;
4116 }
4117
4118 /**
4119  * i40e_aq_get_lldp_mib
4120  * @hw: pointer to the hw struct
4121  * @bridge_type: type of bridge requested
4122  * @mib_type: Local, Remote or both Local and Remote MIBs
4123  * @buff: pointer to a user supplied buffer to store the MIB block
4124  * @buff_size: size of the buffer (in bytes)
4125  * @local_len : length of the returned Local LLDP MIB
4126  * @remote_len: length of the returned Remote LLDP MIB
4127  * @cmd_details: pointer to command details structure or NULL
4128  *
4129  * Requests the complete LLDP MIB (entire packet).
4130  **/
4131 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4132                                 u8 mib_type, void *buff, u16 buff_size,
4133                                 u16 *local_len, u16 *remote_len,
4134                                 struct i40e_asq_cmd_details *cmd_details)
4135 {
4136         struct i40e_aq_desc desc;
4137         struct i40e_aqc_lldp_get_mib *cmd =
4138                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4139         struct i40e_aqc_lldp_get_mib *resp =
4140                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4141         enum i40e_status_code status;
4142
4143         if (buff_size == 0 || !buff)
4144                 return I40E_ERR_PARAM;
4145
4146         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4147         /* Indirect Command */
4148         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4149
4150         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4151         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4152                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4153
4154         desc.datalen = CPU_TO_LE16(buff_size);
4155
4156         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4157         if (buff_size > I40E_AQ_LARGE_BUF)
4158                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4159
4160         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4161         if (!status) {
4162                 if (local_len != NULL)
4163                         *local_len = LE16_TO_CPU(resp->local_len);
4164                 if (remote_len != NULL)
4165                         *remote_len = LE16_TO_CPU(resp->remote_len);
4166         }
4167
4168         return status;
4169 }
4170
4171  /**
4172  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4173  * @hw: pointer to the hw struct
4174  * @mib_type: Local, Remote or both Local and Remote MIBs
4175  * @buff: pointer to a user supplied buffer to store the MIB block
4176  * @buff_size: size of the buffer (in bytes)
4177  * @cmd_details: pointer to command details structure or NULL
4178  *
4179  * Set the LLDP MIB.
4180  **/
4181 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4182                                 u8 mib_type, void *buff, u16 buff_size,
4183                                 struct i40e_asq_cmd_details *cmd_details)
4184 {
4185         struct i40e_aq_desc desc;
4186         struct i40e_aqc_lldp_set_local_mib *cmd =
4187                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4188         enum i40e_status_code status;
4189
4190         if (buff_size == 0 || !buff)
4191                 return I40E_ERR_PARAM;
4192
4193         i40e_fill_default_direct_cmd_desc(&desc,
4194                                 i40e_aqc_opc_lldp_set_local_mib);
4195         /* Indirect Command */
4196         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4197         if (buff_size > I40E_AQ_LARGE_BUF)
4198                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4199         desc.datalen = CPU_TO_LE16(buff_size);
4200
4201         cmd->type = mib_type;
4202         cmd->length = CPU_TO_LE16(buff_size);
4203         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4204         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4205
4206         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4207         return status;
4208 }
4209
4210 /**
4211  * i40e_aq_cfg_lldp_mib_change_event
4212  * @hw: pointer to the hw struct
4213  * @enable_update: Enable or Disable event posting
4214  * @cmd_details: pointer to command details structure or NULL
4215  *
4216  * Enable or Disable posting of an event on ARQ when LLDP MIB
4217  * associated with the interface changes
4218  **/
4219 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4220                                 bool enable_update,
4221                                 struct i40e_asq_cmd_details *cmd_details)
4222 {
4223         struct i40e_aq_desc desc;
4224         struct i40e_aqc_lldp_update_mib *cmd =
4225                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4226         enum i40e_status_code status;
4227
4228         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4229
4230         if (!enable_update)
4231                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4232
4233         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4234
4235         return status;
4236 }
4237
4238 /**
4239  * i40e_aq_add_lldp_tlv
4240  * @hw: pointer to the hw struct
4241  * @bridge_type: type of bridge
4242  * @buff: buffer with TLV to add
4243  * @buff_size: length of the buffer
4244  * @tlv_len: length of the TLV to be added
4245  * @mib_len: length of the LLDP MIB returned in response
4246  * @cmd_details: pointer to command details structure or NULL
4247  *
4248  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4249  * it is responsibility of the caller to make sure that the TLV is not
4250  * already present in the LLDPDU.
4251  * In return firmware will write the complete LLDP MIB with the newly
4252  * added TLV in the response buffer.
4253  **/
4254 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4255                                 void *buff, u16 buff_size, u16 tlv_len,
4256                                 u16 *mib_len,
4257                                 struct i40e_asq_cmd_details *cmd_details)
4258 {
4259         struct i40e_aq_desc desc;
4260         struct i40e_aqc_lldp_add_tlv *cmd =
4261                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4262         enum i40e_status_code status;
4263
4264         if (buff_size == 0 || !buff || tlv_len == 0)
4265                 return I40E_ERR_PARAM;
4266
4267         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4268
4269         /* Indirect Command */
4270         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4271         if (buff_size > I40E_AQ_LARGE_BUF)
4272                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4273         desc.datalen = CPU_TO_LE16(buff_size);
4274
4275         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4276                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4277         cmd->len = CPU_TO_LE16(tlv_len);
4278
4279         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4280         if (!status) {
4281                 if (mib_len != NULL)
4282                         *mib_len = LE16_TO_CPU(desc.datalen);
4283         }
4284
4285         return status;
4286 }
4287
4288 /**
4289  * i40e_aq_update_lldp_tlv
4290  * @hw: pointer to the hw struct
4291  * @bridge_type: type of bridge
4292  * @buff: buffer with TLV to update
4293  * @buff_size: size of the buffer holding original and updated TLVs
4294  * @old_len: Length of the Original TLV
4295  * @new_len: Length of the Updated TLV
4296  * @offset: offset of the updated TLV in the buff
4297  * @mib_len: length of the returned LLDP MIB
4298  * @cmd_details: pointer to command details structure or NULL
4299  *
4300  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4301  * Firmware will place the complete LLDP MIB in response buffer with the
4302  * updated TLV.
4303  **/
4304 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4305                                 u8 bridge_type, void *buff, u16 buff_size,
4306                                 u16 old_len, u16 new_len, u16 offset,
4307                                 u16 *mib_len,
4308                                 struct i40e_asq_cmd_details *cmd_details)
4309 {
4310         struct i40e_aq_desc desc;
4311         struct i40e_aqc_lldp_update_tlv *cmd =
4312                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4313         enum i40e_status_code status;
4314
4315         if (buff_size == 0 || !buff || offset == 0 ||
4316             old_len == 0 || new_len == 0)
4317                 return I40E_ERR_PARAM;
4318
4319         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4320
4321         /* Indirect Command */
4322         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4323         if (buff_size > I40E_AQ_LARGE_BUF)
4324                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4325         desc.datalen = CPU_TO_LE16(buff_size);
4326
4327         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4328                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4329         cmd->old_len = CPU_TO_LE16(old_len);
4330         cmd->new_offset = CPU_TO_LE16(offset);
4331         cmd->new_len = CPU_TO_LE16(new_len);
4332
4333         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4334         if (!status) {
4335                 if (mib_len != NULL)
4336                         *mib_len = LE16_TO_CPU(desc.datalen);
4337         }
4338
4339         return status;
4340 }
4341
4342 /**
4343  * i40e_aq_delete_lldp_tlv
4344  * @hw: pointer to the hw struct
4345  * @bridge_type: type of bridge
4346  * @buff: pointer to a user supplied buffer that has the TLV
4347  * @buff_size: length of the buffer
4348  * @tlv_len: length of the TLV to be deleted
4349  * @mib_len: length of the returned LLDP MIB
4350  * @cmd_details: pointer to command details structure or NULL
4351  *
4352  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4353  * The firmware places the entire LLDP MIB in the response buffer.
4354  **/
4355 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4356                                 u8 bridge_type, void *buff, u16 buff_size,
4357                                 u16 tlv_len, u16 *mib_len,
4358                                 struct i40e_asq_cmd_details *cmd_details)
4359 {
4360         struct i40e_aq_desc desc;
4361         struct i40e_aqc_lldp_add_tlv *cmd =
4362                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4363         enum i40e_status_code status;
4364
4365         if (buff_size == 0 || !buff)
4366                 return I40E_ERR_PARAM;
4367
4368         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4369
4370         /* Indirect Command */
4371         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4372         if (buff_size > I40E_AQ_LARGE_BUF)
4373                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4374         desc.datalen = CPU_TO_LE16(buff_size);
4375         cmd->len = CPU_TO_LE16(tlv_len);
4376         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4377                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4378
4379         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4380         if (!status) {
4381                 if (mib_len != NULL)
4382                         *mib_len = LE16_TO_CPU(desc.datalen);
4383         }
4384
4385         return status;
4386 }
4387
4388 /**
4389  * i40e_aq_stop_lldp
4390  * @hw: pointer to the hw struct
4391  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4392  * @cmd_details: pointer to command details structure or NULL
4393  *
4394  * Stop or Shutdown the embedded LLDP Agent
4395  **/
4396 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4397                                 struct i40e_asq_cmd_details *cmd_details)
4398 {
4399         struct i40e_aq_desc desc;
4400         struct i40e_aqc_lldp_stop *cmd =
4401                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4402         enum i40e_status_code status;
4403
4404         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4405
4406         if (shutdown_agent)
4407                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4408
4409         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4410
4411         return status;
4412 }
4413
4414 /**
4415  * i40e_aq_start_lldp
4416  * @hw: pointer to the hw struct
4417  * @cmd_details: pointer to command details structure or NULL
4418  *
4419  * Start the embedded LLDP Agent on all ports.
4420  **/
4421 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4422                                 struct i40e_asq_cmd_details *cmd_details)
4423 {
4424         struct i40e_aq_desc desc;
4425         struct i40e_aqc_lldp_start *cmd =
4426                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4427         enum i40e_status_code status;
4428
4429         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4430
4431         cmd->command = I40E_AQ_LLDP_AGENT_START;
4432         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4433
4434         return status;
4435 }
4436
4437 /**
4438  * i40e_aq_set_dcb_parameters
4439  * @hw: pointer to the hw struct
4440  * @cmd_details: pointer to command details structure or NULL
4441  * @dcb_enable: True if DCB configuration needs to be applied
4442  *
4443  **/
4444 enum i40e_status_code
4445 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4446                            struct i40e_asq_cmd_details *cmd_details)
4447 {
4448         struct i40e_aq_desc desc;
4449         struct i40e_aqc_set_dcb_parameters *cmd =
4450                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4451         enum i40e_status_code status;
4452
4453         i40e_fill_default_direct_cmd_desc(&desc,
4454                                           i40e_aqc_opc_set_dcb_parameters);
4455
4456         if (dcb_enable) {
4457                 cmd->valid_flags = I40E_DCB_VALID;
4458                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4459         }
4460         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4461
4462         return status;
4463 }
4464
4465 /**
4466  * i40e_aq_get_cee_dcb_config
4467  * @hw: pointer to the hw struct
4468  * @buff: response buffer that stores CEE operational configuration
4469  * @buff_size: size of the buffer passed
4470  * @cmd_details: pointer to command details structure or NULL
4471  *
4472  * Get CEE DCBX mode operational configuration from firmware
4473  **/
4474 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4475                                 void *buff, u16 buff_size,
4476                                 struct i40e_asq_cmd_details *cmd_details)
4477 {
4478         struct i40e_aq_desc desc;
4479         enum i40e_status_code status;
4480
4481         if (buff_size == 0 || !buff)
4482                 return I40E_ERR_PARAM;
4483
4484         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4485
4486         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4487         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4488                                        cmd_details);
4489
4490         return status;
4491 }
4492
4493 /**
4494  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4495  * @hw: pointer to the hw struct
4496  * @start_agent: True if DCBx Agent needs to be Started
4497  *                              False if DCBx Agent needs to be Stopped
4498  * @cmd_details: pointer to command details structure or NULL
4499  *
4500  * Start/Stop the embedded dcbx Agent
4501  **/
4502 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4503                                 bool start_agent,
4504                                 struct i40e_asq_cmd_details *cmd_details)
4505 {
4506         struct i40e_aq_desc desc;
4507         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4508                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4509                                 &desc.params.raw;
4510         enum i40e_status_code status;
4511
4512         i40e_fill_default_direct_cmd_desc(&desc,
4513                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4514
4515         if (start_agent)
4516                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4517
4518         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4519
4520         return status;
4521 }
4522
4523 /**
4524  * i40e_aq_add_udp_tunnel
4525  * @hw: pointer to the hw struct
4526  * @udp_port: the UDP port to add in Host byte order
4527  * @protocol_index: protocol index type
4528  * @filter_index: pointer to filter index
4529  * @cmd_details: pointer to command details structure or NULL
4530  *
4531  * Note: Firmware expects the udp_port value to be in Little Endian format,
4532  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4533  * Little Endian order.
4534  **/
4535 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4536                                 u16 udp_port, u8 protocol_index,
4537                                 u8 *filter_index,
4538                                 struct i40e_asq_cmd_details *cmd_details)
4539 {
4540         struct i40e_aq_desc desc;
4541         struct i40e_aqc_add_udp_tunnel *cmd =
4542                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4543         struct i40e_aqc_del_udp_tunnel_completion *resp =
4544                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4545         enum i40e_status_code status;
4546
4547         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4548
4549         cmd->udp_port = CPU_TO_LE16(udp_port);
4550         cmd->protocol_type = protocol_index;
4551
4552         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4553
4554         if (!status && filter_index)
4555                 *filter_index = resp->index;
4556
4557         return status;
4558 }
4559
4560 /**
4561  * i40e_aq_del_udp_tunnel
4562  * @hw: pointer to the hw struct
4563  * @index: filter index
4564  * @cmd_details: pointer to command details structure or NULL
4565  **/
4566 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4567                                 struct i40e_asq_cmd_details *cmd_details)
4568 {
4569         struct i40e_aq_desc desc;
4570         struct i40e_aqc_remove_udp_tunnel *cmd =
4571                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4572         enum i40e_status_code status;
4573
4574         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4575
4576         cmd->index = index;
4577
4578         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4579
4580         return status;
4581 }
4582
4583 /**
4584  * i40e_aq_get_switch_resource_alloc (0x0204)
4585  * @hw: pointer to the hw struct
4586  * @num_entries: pointer to u8 to store the number of resource entries returned
4587  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4588  *        to store the resource information for all resource types.  Each
4589  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4590  * @count: size, in bytes, of the buffer provided
4591  * @cmd_details: pointer to command details structure or NULL
4592  *
4593  * Query the resources allocated to a function.
4594  **/
4595 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4596                         u8 *num_entries,
4597                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4598                         u16 count,
4599                         struct i40e_asq_cmd_details *cmd_details)
4600 {
4601         struct i40e_aq_desc desc;
4602         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4603                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4604         enum i40e_status_code status;
4605         u16 length = count * sizeof(*buf);
4606
4607         i40e_fill_default_direct_cmd_desc(&desc,
4608                                         i40e_aqc_opc_get_switch_resource_alloc);
4609
4610         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4611         if (length > I40E_AQ_LARGE_BUF)
4612                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4613
4614         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4615
4616         if (!status && num_entries)
4617                 *num_entries = cmd_resp->num_entries;
4618
4619         return status;
4620 }
4621
4622 /**
4623  * i40e_aq_delete_element - Delete switch element
4624  * @hw: pointer to the hw struct
4625  * @seid: the SEID to delete from the switch
4626  * @cmd_details: pointer to command details structure or NULL
4627  *
4628  * This deletes a switch element from the switch.
4629  **/
4630 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4631                                 struct i40e_asq_cmd_details *cmd_details)
4632 {
4633         struct i40e_aq_desc desc;
4634         struct i40e_aqc_switch_seid *cmd =
4635                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4636         enum i40e_status_code status;
4637
4638         if (seid == 0)
4639                 return I40E_ERR_PARAM;
4640
4641         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4642
4643         cmd->seid = CPU_TO_LE16(seid);
4644
4645         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4646
4647         return status;
4648 }
4649
4650 /**
4651  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4652  * @hw: pointer to the hw struct
4653  * @flags: component flags
4654  * @mac_seid: uplink seid (MAC SEID)
4655  * @vsi_seid: connected vsi seid
4656  * @ret_seid: seid of create pv component
4657  *
4658  * This instantiates an i40e port virtualizer with specified flags.
4659  * Depending on specified flags the port virtualizer can act as a
4660  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4661  */
4662 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4663                                        u16 mac_seid, u16 vsi_seid,
4664                                        u16 *ret_seid)
4665 {
4666         struct i40e_aq_desc desc;
4667         struct i40e_aqc_add_update_pv *cmd =
4668                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4669         struct i40e_aqc_add_update_pv_completion *resp =
4670                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4671         enum i40e_status_code status;
4672
4673         if (vsi_seid == 0)
4674                 return I40E_ERR_PARAM;
4675
4676         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4677         cmd->command_flags = CPU_TO_LE16(flags);
4678         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4679         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4680
4681         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4682         if (!status && ret_seid)
4683                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4684
4685         return status;
4686 }
4687
4688 /**
4689  * i40e_aq_add_tag - Add an S/E-tag
4690  * @hw: pointer to the hw struct
4691  * @direct_to_queue: should s-tag direct flow to a specific queue
4692  * @vsi_seid: VSI SEID to use this tag
4693  * @tag: value of the tag
4694  * @queue_num: queue number, only valid is direct_to_queue is true
4695  * @tags_used: return value, number of tags in use by this PF
4696  * @tags_free: return value, number of unallocated tags
4697  * @cmd_details: pointer to command details structure or NULL
4698  *
4699  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4700  * the number of tags allocated by the PF, and the number of unallocated
4701  * tags available.
4702  **/
4703 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4704                                 u16 vsi_seid, u16 tag, u16 queue_num,
4705                                 u16 *tags_used, u16 *tags_free,
4706                                 struct i40e_asq_cmd_details *cmd_details)
4707 {
4708         struct i40e_aq_desc desc;
4709         struct i40e_aqc_add_tag *cmd =
4710                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4711         struct i40e_aqc_add_remove_tag_completion *resp =
4712                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4713         enum i40e_status_code status;
4714
4715         if (vsi_seid == 0)
4716                 return I40E_ERR_PARAM;
4717
4718         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4719
4720         cmd->seid = CPU_TO_LE16(vsi_seid);
4721         cmd->tag = CPU_TO_LE16(tag);
4722         if (direct_to_queue) {
4723                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4724                 cmd->queue_number = CPU_TO_LE16(queue_num);
4725         }
4726
4727         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4728
4729         if (!status) {
4730                 if (tags_used != NULL)
4731                         *tags_used = LE16_TO_CPU(resp->tags_used);
4732                 if (tags_free != NULL)
4733                         *tags_free = LE16_TO_CPU(resp->tags_free);
4734         }
4735
4736         return status;
4737 }
4738
4739 /**
4740  * i40e_aq_remove_tag - Remove an S- or E-tag
4741  * @hw: pointer to the hw struct
4742  * @vsi_seid: VSI SEID this tag is associated with
4743  * @tag: value of the S-tag to delete
4744  * @tags_used: return value, number of tags in use by this PF
4745  * @tags_free: return value, number of unallocated tags
4746  * @cmd_details: pointer to command details structure or NULL
4747  *
4748  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4749  * the number of tags allocated by the PF, and the number of unallocated
4750  * tags available.
4751  **/
4752 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4753                                 u16 tag, u16 *tags_used, u16 *tags_free,
4754                                 struct i40e_asq_cmd_details *cmd_details)
4755 {
4756         struct i40e_aq_desc desc;
4757         struct i40e_aqc_remove_tag *cmd =
4758                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4759         struct i40e_aqc_add_remove_tag_completion *resp =
4760                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4761         enum i40e_status_code status;
4762
4763         if (vsi_seid == 0)
4764                 return I40E_ERR_PARAM;
4765
4766         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4767
4768         cmd->seid = CPU_TO_LE16(vsi_seid);
4769         cmd->tag = CPU_TO_LE16(tag);
4770
4771         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4772
4773         if (!status) {
4774                 if (tags_used != NULL)
4775                         *tags_used = LE16_TO_CPU(resp->tags_used);
4776                 if (tags_free != NULL)
4777                         *tags_free = LE16_TO_CPU(resp->tags_free);
4778         }
4779
4780         return status;
4781 }
4782
4783 /**
4784  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4785  * @hw: pointer to the hw struct
4786  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4787  * @etag: value of E-tag to add
4788  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4789  * @buf: address of indirect buffer
4790  * @tags_used: return value, number of E-tags in use by this port
4791  * @tags_free: return value, number of unallocated M-tags
4792  * @cmd_details: pointer to command details structure or NULL
4793  *
4794  * This associates a multicast E-tag to a port virtualizer.  It will return
4795  * the number of tags allocated by the PF, and the number of unallocated
4796  * tags available.
4797  *
4798  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4799  * num_tags_in_buf long.
4800  **/
4801 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4802                                 u16 etag, u8 num_tags_in_buf, void *buf,
4803                                 u16 *tags_used, u16 *tags_free,
4804                                 struct i40e_asq_cmd_details *cmd_details)
4805 {
4806         struct i40e_aq_desc desc;
4807         struct i40e_aqc_add_remove_mcast_etag *cmd =
4808                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4809         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4810            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4811         enum i40e_status_code status;
4812         u16 length = sizeof(u16) * num_tags_in_buf;
4813
4814         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4815                 return I40E_ERR_PARAM;
4816
4817         i40e_fill_default_direct_cmd_desc(&desc,
4818                                           i40e_aqc_opc_add_multicast_etag);
4819
4820         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4821         cmd->etag = CPU_TO_LE16(etag);
4822         cmd->num_unicast_etags = num_tags_in_buf;
4823
4824         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4825         if (length > I40E_AQ_LARGE_BUF)
4826                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4827
4828         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4829
4830         if (!status) {
4831                 if (tags_used != NULL)
4832                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4833                 if (tags_free != NULL)
4834                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4835         }
4836
4837         return status;
4838 }
4839
4840 /**
4841  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4842  * @hw: pointer to the hw struct
4843  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4844  * @etag: value of the E-tag to remove
4845  * @tags_used: return value, number of tags in use by this port
4846  * @tags_free: return value, number of unallocated tags
4847  * @cmd_details: pointer to command details structure or NULL
4848  *
4849  * This deletes an E-tag from the port virtualizer.  It will return
4850  * the number of tags allocated by the port, and the number of unallocated
4851  * tags available.
4852  **/
4853 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4854                                 u16 etag, u16 *tags_used, u16 *tags_free,
4855                                 struct i40e_asq_cmd_details *cmd_details)
4856 {
4857         struct i40e_aq_desc desc;
4858         struct i40e_aqc_add_remove_mcast_etag *cmd =
4859                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4860         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4861            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4862         enum i40e_status_code status;
4863
4864
4865         if (pv_seid == 0)
4866                 return I40E_ERR_PARAM;
4867
4868         i40e_fill_default_direct_cmd_desc(&desc,
4869                                           i40e_aqc_opc_remove_multicast_etag);
4870
4871         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4872         cmd->etag = CPU_TO_LE16(etag);
4873
4874         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4875
4876         if (!status) {
4877                 if (tags_used != NULL)
4878                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4879                 if (tags_free != NULL)
4880                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4881         }
4882
4883         return status;
4884 }
4885
4886 /**
4887  * i40e_aq_update_tag - Update an S/E-tag
4888  * @hw: pointer to the hw struct
4889  * @vsi_seid: VSI SEID using this S-tag
4890  * @old_tag: old tag value
4891  * @new_tag: new tag value
4892  * @tags_used: return value, number of tags in use by this PF
4893  * @tags_free: return value, number of unallocated tags
4894  * @cmd_details: pointer to command details structure or NULL
4895  *
4896  * This updates the value of the tag currently attached to this VSI
4897  * in the switch complex.  It will return the number of tags allocated
4898  * by the PF, and the number of unallocated tags available.
4899  **/
4900 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4901                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4902                                 u16 *tags_free,
4903                                 struct i40e_asq_cmd_details *cmd_details)
4904 {
4905         struct i40e_aq_desc desc;
4906         struct i40e_aqc_update_tag *cmd =
4907                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4908         struct i40e_aqc_update_tag_completion *resp =
4909                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4910         enum i40e_status_code status;
4911
4912         if (vsi_seid == 0)
4913                 return I40E_ERR_PARAM;
4914
4915         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4916
4917         cmd->seid = CPU_TO_LE16(vsi_seid);
4918         cmd->old_tag = CPU_TO_LE16(old_tag);
4919         cmd->new_tag = CPU_TO_LE16(new_tag);
4920
4921         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4922
4923         if (!status) {
4924                 if (tags_used != NULL)
4925                         *tags_used = LE16_TO_CPU(resp->tags_used);
4926                 if (tags_free != NULL)
4927                         *tags_free = LE16_TO_CPU(resp->tags_free);
4928         }
4929
4930         return status;
4931 }
4932
4933 /**
4934  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4935  * @hw: pointer to the hw struct
4936  * @tcmap: TC map for request/release any ignore PFC condition
4937  * @request: request or release ignore PFC condition
4938  * @tcmap_ret: return TCs for which PFC is currently ignored
4939  * @cmd_details: pointer to command details structure or NULL
4940  *
4941  * This sends out request/release to ignore PFC condition for a TC.
4942  * It will return the TCs for which PFC is currently ignored.
4943  **/
4944 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4945                                 bool request, u8 *tcmap_ret,
4946                                 struct i40e_asq_cmd_details *cmd_details)
4947 {
4948         struct i40e_aq_desc desc;
4949         struct i40e_aqc_pfc_ignore *cmd_resp =
4950                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4951         enum i40e_status_code status;
4952
4953         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4954
4955         if (request)
4956                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4957
4958         cmd_resp->tc_bitmap = tcmap;
4959
4960         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4961
4962         if (!status) {
4963                 if (tcmap_ret != NULL)
4964                         *tcmap_ret = cmd_resp->tc_bitmap;
4965         }
4966
4967         return status;
4968 }
4969
4970 /**
4971  * i40e_aq_dcb_updated - DCB Updated Command
4972  * @hw: pointer to the hw struct
4973  * @cmd_details: pointer to command details structure or NULL
4974  *
4975  * When LLDP is handled in PF this command is used by the PF
4976  * to notify EMP that a DCB setting is modified.
4977  * When LLDP is handled in EMP this command is used by the PF
4978  * to notify EMP whenever one of the following parameters get
4979  * modified:
4980  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4981  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4982  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4983  * EMP will return when the shared RPB settings have been
4984  * recomputed and modified. The retval field in the descriptor
4985  * will be set to 0 when RPB is modified.
4986  **/
4987 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4988                                 struct i40e_asq_cmd_details *cmd_details)
4989 {
4990         struct i40e_aq_desc desc;
4991         enum i40e_status_code status;
4992
4993         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4994
4995         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4996
4997         return status;
4998 }
4999
5000 /**
5001  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5002  * @hw: pointer to the hw struct
5003  * @seid: defines the SEID of the switch for which the stats are requested
5004  * @vlan_id: the VLAN ID for which the statistics are requested
5005  * @stat_index: index of the statistics counters block assigned to this VLAN
5006  * @cmd_details: pointer to command details structure or NULL
5007  *
5008  * XL710 supports 128 smonVlanStats counters.This command is used to
5009  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5010  * switch.
5011  **/
5012 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5013                                 u16 vlan_id, u16 *stat_index,
5014                                 struct i40e_asq_cmd_details *cmd_details)
5015 {
5016         struct i40e_aq_desc desc;
5017         struct i40e_aqc_add_remove_statistics *cmd_resp =
5018                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5019         enum i40e_status_code status;
5020
5021         if ((seid == 0) || (stat_index == NULL))
5022                 return I40E_ERR_PARAM;
5023
5024         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5025
5026         cmd_resp->seid = CPU_TO_LE16(seid);
5027         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5028
5029         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5030
5031         if (!status && stat_index)
5032                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5033
5034         return status;
5035 }
5036
5037 /**
5038  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5039  * @hw: pointer to the hw struct
5040  * @seid: defines the SEID of the switch for which the stats are requested
5041  * @vlan_id: the VLAN ID for which the statistics are requested
5042  * @stat_index: index of the statistics counters block assigned to this VLAN
5043  * @cmd_details: pointer to command details structure or NULL
5044  *
5045  * XL710 supports 128 smonVlanStats counters.This command is used to
5046  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5047  * switch.
5048  **/
5049 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5050                                 u16 vlan_id, u16 stat_index,
5051                                 struct i40e_asq_cmd_details *cmd_details)
5052 {
5053         struct i40e_aq_desc desc;
5054         struct i40e_aqc_add_remove_statistics *cmd =
5055                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5056         enum i40e_status_code status;
5057
5058         if (seid == 0)
5059                 return I40E_ERR_PARAM;
5060
5061         i40e_fill_default_direct_cmd_desc(&desc,
5062                                           i40e_aqc_opc_remove_statistics);
5063
5064         cmd->seid = CPU_TO_LE16(seid);
5065         cmd->vlan  = CPU_TO_LE16(vlan_id);
5066         cmd->stat_index = CPU_TO_LE16(stat_index);
5067
5068         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5069
5070         return status;
5071 }
5072
5073 /**
5074  * i40e_aq_set_port_parameters - set physical port parameters.
5075  * @hw: pointer to the hw struct
5076  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5077  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5078  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5079  * @double_vlan: if set double VLAN is enabled
5080  * @cmd_details: pointer to command details structure or NULL
5081  **/
5082 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5083                                 u16 bad_frame_vsi, bool save_bad_pac,
5084                                 bool pad_short_pac, bool double_vlan,
5085                                 struct i40e_asq_cmd_details *cmd_details)
5086 {
5087         struct i40e_aqc_set_port_parameters *cmd;
5088         enum i40e_status_code status;
5089         struct i40e_aq_desc desc;
5090         u16 command_flags = 0;
5091
5092         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5093
5094         i40e_fill_default_direct_cmd_desc(&desc,
5095                                           i40e_aqc_opc_set_port_parameters);
5096
5097         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5098         if (save_bad_pac)
5099                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5100         if (pad_short_pac)
5101                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5102         if (double_vlan)
5103                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5104         cmd->command_flags = CPU_TO_LE16(command_flags);
5105
5106         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5107
5108         return status;
5109 }
5110
5111 /**
5112  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5113  * @hw: pointer to the hw struct
5114  * @seid: seid for the physical port/switching component/vsi
5115  * @buff: Indirect buffer to hold data parameters and response
5116  * @buff_size: Indirect buffer size
5117  * @opcode: Tx scheduler AQ command opcode
5118  * @cmd_details: pointer to command details structure or NULL
5119  *
5120  * Generic command handler for Tx scheduler AQ commands
5121  **/
5122 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5123                                 void *buff, u16 buff_size,
5124                                  enum i40e_admin_queue_opc opcode,
5125                                 struct i40e_asq_cmd_details *cmd_details)
5126 {
5127         struct i40e_aq_desc desc;
5128         struct i40e_aqc_tx_sched_ind *cmd =
5129                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5130         enum i40e_status_code status;
5131         bool cmd_param_flag = false;
5132
5133         switch (opcode) {
5134         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5135         case i40e_aqc_opc_configure_vsi_tc_bw:
5136         case i40e_aqc_opc_enable_switching_comp_ets:
5137         case i40e_aqc_opc_modify_switching_comp_ets:
5138         case i40e_aqc_opc_disable_switching_comp_ets:
5139         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5140         case i40e_aqc_opc_configure_switching_comp_bw_config:
5141                 cmd_param_flag = true;
5142                 break;
5143         case i40e_aqc_opc_query_vsi_bw_config:
5144         case i40e_aqc_opc_query_vsi_ets_sla_config:
5145         case i40e_aqc_opc_query_switching_comp_ets_config:
5146         case i40e_aqc_opc_query_port_ets_config:
5147         case i40e_aqc_opc_query_switching_comp_bw_config:
5148                 cmd_param_flag = false;
5149                 break;
5150         default:
5151                 return I40E_ERR_PARAM;
5152         }
5153
5154         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5155
5156         /* Indirect command */
5157         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5158         if (cmd_param_flag)
5159                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5160         if (buff_size > I40E_AQ_LARGE_BUF)
5161                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5162
5163         desc.datalen = CPU_TO_LE16(buff_size);
5164
5165         cmd->vsi_seid = CPU_TO_LE16(seid);
5166
5167         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5168
5169         return status;
5170 }
5171
5172 /**
5173  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5174  * @hw: pointer to the hw struct
5175  * @seid: VSI seid
5176  * @credit: BW limit credits (0 = disabled)
5177  * @max_credit: Max BW limit credits
5178  * @cmd_details: pointer to command details structure or NULL
5179  **/
5180 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5181                                 u16 seid, u16 credit, u8 max_credit,
5182                                 struct i40e_asq_cmd_details *cmd_details)
5183 {
5184         struct i40e_aq_desc desc;
5185         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5186                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5187         enum i40e_status_code status;
5188
5189         i40e_fill_default_direct_cmd_desc(&desc,
5190                                           i40e_aqc_opc_configure_vsi_bw_limit);
5191
5192         cmd->vsi_seid = CPU_TO_LE16(seid);
5193         cmd->credit = CPU_TO_LE16(credit);
5194         cmd->max_credit = max_credit;
5195
5196         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5197
5198         return status;
5199 }
5200
5201 /**
5202  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5203  * @hw: pointer to the hw struct
5204  * @seid: switching component seid
5205  * @credit: BW limit credits (0 = disabled)
5206  * @max_bw: Max BW limit credits
5207  * @cmd_details: pointer to command details structure or NULL
5208  **/
5209 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5210                                 u16 seid, u16 credit, u8 max_bw,
5211                                 struct i40e_asq_cmd_details *cmd_details)
5212 {
5213         struct i40e_aq_desc desc;
5214         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5215           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5216         enum i40e_status_code status;
5217
5218         i40e_fill_default_direct_cmd_desc(&desc,
5219                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5220
5221         cmd->seid = CPU_TO_LE16(seid);
5222         cmd->credit = CPU_TO_LE16(credit);
5223         cmd->max_bw = max_bw;
5224
5225         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5226
5227         return status;
5228 }
5229
5230 /**
5231  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5232  * @hw: pointer to the hw struct
5233  * @seid: VSI seid
5234  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5235  * @cmd_details: pointer to command details structure or NULL
5236  **/
5237 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5238                         u16 seid,
5239                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5240                         struct i40e_asq_cmd_details *cmd_details)
5241 {
5242         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5243                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5244                                     cmd_details);
5245 }
5246
5247 /**
5248  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5249  * @hw: pointer to the hw struct
5250  * @seid: VSI seid
5251  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5252  * @cmd_details: pointer to command details structure or NULL
5253  **/
5254 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5255                         u16 seid,
5256                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5257                         struct i40e_asq_cmd_details *cmd_details)
5258 {
5259         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5260                                     i40e_aqc_opc_configure_vsi_tc_bw,
5261                                     cmd_details);
5262 }
5263
5264 /**
5265  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5266  * @hw: pointer to the hw struct
5267  * @seid: seid of the switching component connected to Physical Port
5268  * @ets_data: Buffer holding ETS parameters
5269  * @opcode: Tx scheduler AQ command opcode
5270  * @cmd_details: pointer to command details structure or NULL
5271  **/
5272 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5273                 u16 seid,
5274                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5275                 enum i40e_admin_queue_opc opcode,
5276                 struct i40e_asq_cmd_details *cmd_details)
5277 {
5278         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5279                                     sizeof(*ets_data), opcode, cmd_details);
5280 }
5281
5282 /**
5283  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5284  * @hw: pointer to the hw struct
5285  * @seid: seid of the switching component
5286  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5287  * @cmd_details: pointer to command details structure or NULL
5288  **/
5289 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5290         u16 seid,
5291         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5292         struct i40e_asq_cmd_details *cmd_details)
5293 {
5294         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5295                             i40e_aqc_opc_configure_switching_comp_bw_config,
5296                             cmd_details);
5297 }
5298
5299 /**
5300  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5301  * @hw: pointer to the hw struct
5302  * @seid: seid of the switching component
5303  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5304  * @cmd_details: pointer to command details structure or NULL
5305  **/
5306 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5307         struct i40e_hw *hw, u16 seid,
5308         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5309         struct i40e_asq_cmd_details *cmd_details)
5310 {
5311         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5312                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5313                             cmd_details);
5314 }
5315
5316 /**
5317  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5318  * @hw: pointer to the hw struct
5319  * @seid: seid of the VSI
5320  * @bw_data: Buffer to hold VSI BW configuration
5321  * @cmd_details: pointer to command details structure or NULL
5322  **/
5323 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5324                         u16 seid,
5325                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5326                         struct i40e_asq_cmd_details *cmd_details)
5327 {
5328         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5329                                     i40e_aqc_opc_query_vsi_bw_config,
5330                                     cmd_details);
5331 }
5332
5333 /**
5334  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5335  * @hw: pointer to the hw struct
5336  * @seid: seid of the VSI
5337  * @bw_data: Buffer to hold VSI BW configuration per TC
5338  * @cmd_details: pointer to command details structure or NULL
5339  **/
5340 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5341                         u16 seid,
5342                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5343                         struct i40e_asq_cmd_details *cmd_details)
5344 {
5345         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5346                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5347                                     cmd_details);
5348 }
5349
5350 /**
5351  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5352  * @hw: pointer to the hw struct
5353  * @seid: seid of the switching component
5354  * @bw_data: Buffer to hold switching component's per TC BW config
5355  * @cmd_details: pointer to command details structure or NULL
5356  **/
5357 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5358                 u16 seid,
5359                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5360                 struct i40e_asq_cmd_details *cmd_details)
5361 {
5362         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5363                                    i40e_aqc_opc_query_switching_comp_ets_config,
5364                                    cmd_details);
5365 }
5366
5367 /**
5368  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5369  * @hw: pointer to the hw struct
5370  * @seid: seid of the VSI or switching component connected to Physical Port
5371  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5372  * @cmd_details: pointer to command details structure or NULL
5373  **/
5374 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5375                         u16 seid,
5376                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5377                         struct i40e_asq_cmd_details *cmd_details)
5378 {
5379         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5380                                     i40e_aqc_opc_query_port_ets_config,
5381                                     cmd_details);
5382 }
5383
5384 /**
5385  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5386  * @hw: pointer to the hw struct
5387  * @seid: seid of the switching component
5388  * @bw_data: Buffer to hold switching component's BW configuration
5389  * @cmd_details: pointer to command details structure or NULL
5390  **/
5391 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5392                 u16 seid,
5393                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5394                 struct i40e_asq_cmd_details *cmd_details)
5395 {
5396         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5397                                     i40e_aqc_opc_query_switching_comp_bw_config,
5398                                     cmd_details);
5399 }
5400
5401 /**
5402  * i40e_validate_filter_settings
5403  * @hw: pointer to the hardware structure
5404  * @settings: Filter control settings
5405  *
5406  * Check and validate the filter control settings passed.
5407  * The function checks for the valid filter/context sizes being
5408  * passed for FCoE and PE.
5409  *
5410  * Returns I40E_SUCCESS if the values passed are valid and within
5411  * range else returns an error.
5412  **/
5413 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5414                                 struct i40e_filter_control_settings *settings)
5415 {
5416         u32 fcoe_cntx_size, fcoe_filt_size;
5417         u32 pe_cntx_size, pe_filt_size;
5418         u32 fcoe_fmax;
5419
5420         u32 val;
5421
5422         /* Validate FCoE settings passed */
5423         switch (settings->fcoe_filt_num) {
5424         case I40E_HASH_FILTER_SIZE_1K:
5425         case I40E_HASH_FILTER_SIZE_2K:
5426         case I40E_HASH_FILTER_SIZE_4K:
5427         case I40E_HASH_FILTER_SIZE_8K:
5428         case I40E_HASH_FILTER_SIZE_16K:
5429         case I40E_HASH_FILTER_SIZE_32K:
5430                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5431                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5432                 break;
5433         default:
5434                 return I40E_ERR_PARAM;
5435         }
5436
5437         switch (settings->fcoe_cntx_num) {
5438         case I40E_DMA_CNTX_SIZE_512:
5439         case I40E_DMA_CNTX_SIZE_1K:
5440         case I40E_DMA_CNTX_SIZE_2K:
5441         case I40E_DMA_CNTX_SIZE_4K:
5442                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5443                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5444                 break;
5445         default:
5446                 return I40E_ERR_PARAM;
5447         }
5448
5449         /* Validate PE settings passed */
5450         switch (settings->pe_filt_num) {
5451         case I40E_HASH_FILTER_SIZE_1K:
5452         case I40E_HASH_FILTER_SIZE_2K:
5453         case I40E_HASH_FILTER_SIZE_4K:
5454         case I40E_HASH_FILTER_SIZE_8K:
5455         case I40E_HASH_FILTER_SIZE_16K:
5456         case I40E_HASH_FILTER_SIZE_32K:
5457         case I40E_HASH_FILTER_SIZE_64K:
5458         case I40E_HASH_FILTER_SIZE_128K:
5459         case I40E_HASH_FILTER_SIZE_256K:
5460         case I40E_HASH_FILTER_SIZE_512K:
5461         case I40E_HASH_FILTER_SIZE_1M:
5462                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5463                 pe_filt_size <<= (u32)settings->pe_filt_num;
5464                 break;
5465         default:
5466                 return I40E_ERR_PARAM;
5467         }
5468
5469         switch (settings->pe_cntx_num) {
5470         case I40E_DMA_CNTX_SIZE_512:
5471         case I40E_DMA_CNTX_SIZE_1K:
5472         case I40E_DMA_CNTX_SIZE_2K:
5473         case I40E_DMA_CNTX_SIZE_4K:
5474         case I40E_DMA_CNTX_SIZE_8K:
5475         case I40E_DMA_CNTX_SIZE_16K:
5476         case I40E_DMA_CNTX_SIZE_32K:
5477         case I40E_DMA_CNTX_SIZE_64K:
5478         case I40E_DMA_CNTX_SIZE_128K:
5479         case I40E_DMA_CNTX_SIZE_256K:
5480                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5481                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5482                 break;
5483         default:
5484                 return I40E_ERR_PARAM;
5485         }
5486
5487         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5488         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5489         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5490                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5491         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5492                 return I40E_ERR_INVALID_SIZE;
5493
5494         return I40E_SUCCESS;
5495 }
5496
5497 /**
5498  * i40e_set_filter_control
5499  * @hw: pointer to the hardware structure
5500  * @settings: Filter control settings
5501  *
5502  * Set the Queue Filters for PE/FCoE and enable filters required
5503  * for a single PF. It is expected that these settings are programmed
5504  * at the driver initialization time.
5505  **/
5506 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5507                                 struct i40e_filter_control_settings *settings)
5508 {
5509         enum i40e_status_code ret = I40E_SUCCESS;
5510         u32 hash_lut_size = 0;
5511         u32 val;
5512
5513         if (!settings)
5514                 return I40E_ERR_PARAM;
5515
5516         /* Validate the input settings */
5517         ret = i40e_validate_filter_settings(hw, settings);
5518         if (ret)
5519                 return ret;
5520
5521         /* Read the PF Queue Filter control register */
5522         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5523
5524         /* Program required PE hash buckets for the PF */
5525         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5526         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5527                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5528         /* Program required PE contexts for the PF */
5529         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5530         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5531                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5532
5533         /* Program required FCoE hash buckets for the PF */
5534         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5535         val |= ((u32)settings->fcoe_filt_num <<
5536                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5537                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5538         /* Program required FCoE DDP contexts for the PF */
5539         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5540         val |= ((u32)settings->fcoe_cntx_num <<
5541                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5542                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5543
5544         /* Program Hash LUT size for the PF */
5545         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5546         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5547                 hash_lut_size = 1;
5548         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5549                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5550
5551         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5552         if (settings->enable_fdir)
5553                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5554         if (settings->enable_ethtype)
5555                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5556         if (settings->enable_macvlan)
5557                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5558
5559         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5560
5561         return I40E_SUCCESS;
5562 }
5563
5564 /**
5565  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5566  * @hw: pointer to the hw struct
5567  * @mac_addr: MAC address to use in the filter
5568  * @ethtype: Ethertype to use in the filter
5569  * @flags: Flags that needs to be applied to the filter
5570  * @vsi_seid: seid of the control VSI
5571  * @queue: VSI queue number to send the packet to
5572  * @is_add: Add control packet filter if True else remove
5573  * @stats: Structure to hold information on control filter counts
5574  * @cmd_details: pointer to command details structure or NULL
5575  *
5576  * This command will Add or Remove control packet filter for a control VSI.
5577  * In return it will update the total number of perfect filter count in
5578  * the stats member.
5579  **/
5580 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5581                                 u8 *mac_addr, u16 ethtype, u16 flags,
5582                                 u16 vsi_seid, u16 queue, bool is_add,
5583                                 struct i40e_control_filter_stats *stats,
5584                                 struct i40e_asq_cmd_details *cmd_details)
5585 {
5586         struct i40e_aq_desc desc;
5587         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5588                 (struct i40e_aqc_add_remove_control_packet_filter *)
5589                 &desc.params.raw;
5590         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5591                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5592                 &desc.params.raw;
5593         enum i40e_status_code status;
5594
5595         if (vsi_seid == 0)
5596                 return I40E_ERR_PARAM;
5597
5598         if (is_add) {
5599                 i40e_fill_default_direct_cmd_desc(&desc,
5600                                 i40e_aqc_opc_add_control_packet_filter);
5601                 cmd->queue = CPU_TO_LE16(queue);
5602         } else {
5603                 i40e_fill_default_direct_cmd_desc(&desc,
5604                                 i40e_aqc_opc_remove_control_packet_filter);
5605         }
5606
5607         if (mac_addr)
5608                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5609                             I40E_NONDMA_TO_NONDMA);
5610
5611         cmd->etype = CPU_TO_LE16(ethtype);
5612         cmd->flags = CPU_TO_LE16(flags);
5613         cmd->seid = CPU_TO_LE16(vsi_seid);
5614
5615         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5616
5617         if (!status && stats) {
5618                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5619                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5620                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5621                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5622         }
5623
5624         return status;
5625 }
5626
5627 /**
5628  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5629  * @hw: pointer to the hw struct
5630  * @seid: VSI seid to add ethertype filter from
5631  **/
5632 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5633                                                     u16 seid)
5634 {
5635 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5636         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5637                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5638                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5639         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5640         enum i40e_status_code status;
5641
5642         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5643                                                        seid, 0, true, NULL,
5644                                                        NULL);
5645         if (status)
5646                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5647 }
5648
5649 /**
5650  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5651  * @filters: list of cloud filters
5652  * @filter_count: length of list
5653  *
5654  * There's an issue in the device where the Geneve VNI layout needs
5655  * to be shifted 1 byte over from the VxLAN VNI
5656  **/
5657 STATIC void i40e_fix_up_geneve_vni(
5658         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5659         u8 filter_count)
5660 {
5661         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5662         int i;
5663
5664         for (i = 0; i < filter_count; i++) {
5665                 u16 tnl_type;
5666                 u32 ti;
5667
5668                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5669                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5670                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5671                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5672                         ti = LE32_TO_CPU(f[i].tenant_id);
5673                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5674                 }
5675         }
5676 }
5677
5678 /**
5679  * i40e_aq_add_cloud_filters
5680  * @hw: pointer to the hardware structure
5681  * @seid: VSI seid to add cloud filters from
5682  * @filters: Buffer which contains the filters to be added
5683  * @filter_count: number of filters contained in the buffer
5684  *
5685  * Set the cloud filters for a given VSI.  The contents of the
5686  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5687  * in by the caller of the function.
5688  *
5689  **/
5690 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5691         u16 seid,
5692         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5693         u8 filter_count)
5694 {
5695         struct i40e_aq_desc desc;
5696         struct i40e_aqc_add_remove_cloud_filters *cmd =
5697         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5698         enum i40e_status_code status;
5699         u16 buff_len;
5700
5701         i40e_fill_default_direct_cmd_desc(&desc,
5702                                           i40e_aqc_opc_add_cloud_filters);
5703
5704         buff_len = filter_count * sizeof(*filters);
5705         desc.datalen = CPU_TO_LE16(buff_len);
5706         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5707         cmd->num_filters = filter_count;
5708         cmd->seid = CPU_TO_LE16(seid);
5709
5710         i40e_fix_up_geneve_vni(filters, filter_count);
5711
5712         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5713
5714         return status;
5715 }
5716
5717 /**
5718  * i40e_aq_add_cloud_filters_big_buffer
5719  * @hw: pointer to the hardware structure
5720  * @seid: VSI seid to add cloud filters from
5721  * @filters: Buffer which contains the filters in big buffer to be added
5722  * @filter_count: number of filters contained in the buffer
5723  *
5724  * Set the cloud filters for a given VSI.  The contents of the
5725  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5726  * the function.
5727  *
5728  **/
5729 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5730         u16 seid,
5731         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5732         u8 filter_count)
5733 {
5734         struct i40e_aq_desc desc;
5735         struct i40e_aqc_add_remove_cloud_filters *cmd =
5736         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5737         enum i40e_status_code status;
5738         u16 buff_len;
5739         int i;
5740
5741         i40e_fill_default_direct_cmd_desc(&desc,
5742                                           i40e_aqc_opc_add_cloud_filters);
5743
5744         buff_len = filter_count * sizeof(*filters);
5745         desc.datalen = CPU_TO_LE16(buff_len);
5746         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5747         cmd->num_filters = filter_count;
5748         cmd->seid = CPU_TO_LE16(seid);
5749         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5750
5751         /* adjust Geneve VNI for HW issue */
5752         for (i = 0; i < filter_count; i++) {
5753                 u16 tnl_type;
5754                 u32 ti;
5755
5756                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5757                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5758                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5759                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5760                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5761                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5762                 }
5763         }
5764
5765         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5766
5767         return status;
5768 }
5769
5770 /**
5771  * i40e_aq_remove_cloud_filters
5772  * @hw: pointer to the hardware structure
5773  * @seid: VSI seid to remove cloud filters from
5774  * @filters: Buffer which contains the filters to be removed
5775  * @filter_count: number of filters contained in the buffer
5776  *
5777  * Remove the cloud filters for a given VSI.  The contents of the
5778  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5779  * in by the caller of the function.
5780  *
5781  **/
5782 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5783         u16 seid,
5784         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5785         u8 filter_count)
5786 {
5787         struct i40e_aq_desc desc;
5788         struct i40e_aqc_add_remove_cloud_filters *cmd =
5789         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5790         enum i40e_status_code status;
5791         u16 buff_len;
5792
5793         i40e_fill_default_direct_cmd_desc(&desc,
5794                                           i40e_aqc_opc_remove_cloud_filters);
5795
5796         buff_len = filter_count * sizeof(*filters);
5797         desc.datalen = CPU_TO_LE16(buff_len);
5798         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5799         cmd->num_filters = filter_count;
5800         cmd->seid = CPU_TO_LE16(seid);
5801
5802         i40e_fix_up_geneve_vni(filters, filter_count);
5803
5804         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5805
5806         return status;
5807 }
5808
5809 /**
5810  * i40e_aq_remove_cloud_filters_big_buffer
5811  * @hw: pointer to the hardware structure
5812  * @seid: VSI seid to remove cloud filters from
5813  * @filters: Buffer which contains the filters in big buffer to be removed
5814  * @filter_count: number of filters contained in the buffer
5815  *
5816  * Remove the cloud filters for a given VSI.  The contents of the
5817  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5818  * the function.
5819  *
5820  **/
5821 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5822         struct i40e_hw *hw,
5823         u16 seid,
5824         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5825         u8 filter_count)
5826 {
5827         struct i40e_aq_desc desc;
5828         struct i40e_aqc_add_remove_cloud_filters *cmd =
5829         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5830         enum i40e_status_code status;
5831         u16 buff_len;
5832         int i;
5833
5834         i40e_fill_default_direct_cmd_desc(&desc,
5835                                           i40e_aqc_opc_remove_cloud_filters);
5836
5837         buff_len = filter_count * sizeof(*filters);
5838         desc.datalen = CPU_TO_LE16(buff_len);
5839         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5840         cmd->num_filters = filter_count;
5841         cmd->seid = CPU_TO_LE16(seid);
5842         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5843
5844         /* adjust Geneve VNI for HW issue */
5845         for (i = 0; i < filter_count; i++) {
5846                 u16 tnl_type;
5847                 u32 ti;
5848
5849                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5850                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5851                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5852                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5853                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5854                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5855                 }
5856         }
5857
5858         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5859
5860         return status;
5861 }
5862
5863 /**
5864  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5865  * @hw: pointer to the hw struct
5866  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5867  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5868  *
5869  **/
5870 enum
5871 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5872         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5873         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5874 {
5875         struct i40e_aq_desc desc;
5876         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5877                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5878         enum i40e_status_code status = I40E_SUCCESS;
5879         int i = 0;
5880
5881         i40e_fill_default_direct_cmd_desc(&desc,
5882                                           i40e_aqc_opc_replace_cloud_filters);
5883
5884         desc.datalen = CPU_TO_LE16(32);
5885         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5886         cmd->old_filter_type = filters->old_filter_type;
5887         cmd->new_filter_type = filters->new_filter_type;
5888         cmd->valid_flags = filters->valid_flags;
5889         cmd->tr_bit = filters->tr_bit;
5890
5891         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5892                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5893
5894         /* for get cloud filters command */
5895         for (i = 0; i < 32; i += 4) {
5896                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5897                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5898                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5899                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5900         }
5901
5902         return status;
5903 }
5904
5905
5906 /**
5907  * i40e_aq_alternate_write
5908  * @hw: pointer to the hardware structure
5909  * @reg_addr0: address of first dword to be read
5910  * @reg_val0: value to be written under 'reg_addr0'
5911  * @reg_addr1: address of second dword to be read
5912  * @reg_val1: value to be written under 'reg_addr1'
5913  *
5914  * Write one or two dwords to alternate structure. Fields are indicated
5915  * by 'reg_addr0' and 'reg_addr1' register numbers.
5916  *
5917  **/
5918 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5919                                 u32 reg_addr0, u32 reg_val0,
5920                                 u32 reg_addr1, u32 reg_val1)
5921 {
5922         struct i40e_aq_desc desc;
5923         struct i40e_aqc_alternate_write *cmd_resp =
5924                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5925         enum i40e_status_code status;
5926
5927         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5928         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5929         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5930         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5931         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5932
5933         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5934
5935         return status;
5936 }
5937
5938 /**
5939  * i40e_aq_alternate_write_indirect
5940  * @hw: pointer to the hardware structure
5941  * @addr: address of a first register to be modified
5942  * @dw_count: number of alternate structure fields to write
5943  * @buffer: pointer to the command buffer
5944  *
5945  * Write 'dw_count' dwords from 'buffer' to alternate structure
5946  * starting at 'addr'.
5947  *
5948  **/
5949 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5950                                 u32 addr, u32 dw_count, void *buffer)
5951 {
5952         struct i40e_aq_desc desc;
5953         struct i40e_aqc_alternate_ind_write *cmd_resp =
5954                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5955         enum i40e_status_code status;
5956
5957         if (buffer == NULL)
5958                 return I40E_ERR_PARAM;
5959
5960         /* Indirect command */
5961         i40e_fill_default_direct_cmd_desc(&desc,
5962                                          i40e_aqc_opc_alternate_write_indirect);
5963
5964         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5965         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5966         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5967                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5968
5969         cmd_resp->address = CPU_TO_LE32(addr);
5970         cmd_resp->length = CPU_TO_LE32(dw_count);
5971
5972         status = i40e_asq_send_command(hw, &desc, buffer,
5973                                        I40E_LO_DWORD(4*dw_count), NULL);
5974
5975         return status;
5976 }
5977
5978 /**
5979  * i40e_aq_alternate_read
5980  * @hw: pointer to the hardware structure
5981  * @reg_addr0: address of first dword to be read
5982  * @reg_val0: pointer for data read from 'reg_addr0'
5983  * @reg_addr1: address of second dword to be read
5984  * @reg_val1: pointer for data read from 'reg_addr1'
5985  *
5986  * Read one or two dwords from alternate structure. Fields are indicated
5987  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5988  * is not passed then only register at 'reg_addr0' is read.
5989  *
5990  **/
5991 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5992                                 u32 reg_addr0, u32 *reg_val0,
5993                                 u32 reg_addr1, u32 *reg_val1)
5994 {
5995         struct i40e_aq_desc desc;
5996         struct i40e_aqc_alternate_write *cmd_resp =
5997                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5998         enum i40e_status_code status;
5999
6000         if (reg_val0 == NULL)
6001                 return I40E_ERR_PARAM;
6002
6003         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6004         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6005         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6006
6007         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6008
6009         if (status == I40E_SUCCESS) {
6010                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6011
6012                 if (reg_val1 != NULL)
6013                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6014         }
6015
6016         return status;
6017 }
6018
6019 /**
6020  * i40e_aq_alternate_read_indirect
6021  * @hw: pointer to the hardware structure
6022  * @addr: address of the alternate structure field
6023  * @dw_count: number of alternate structure fields to read
6024  * @buffer: pointer to the command buffer
6025  *
6026  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6027  * place them in 'buffer'. The buffer should be allocated by caller.
6028  *
6029  **/
6030 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6031                                 u32 addr, u32 dw_count, void *buffer)
6032 {
6033         struct i40e_aq_desc desc;
6034         struct i40e_aqc_alternate_ind_write *cmd_resp =
6035                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6036         enum i40e_status_code status;
6037
6038         if (buffer == NULL)
6039                 return I40E_ERR_PARAM;
6040
6041         /* Indirect command */
6042         i40e_fill_default_direct_cmd_desc(&desc,
6043                 i40e_aqc_opc_alternate_read_indirect);
6044
6045         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6046         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6047         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6048                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6049
6050         cmd_resp->address = CPU_TO_LE32(addr);
6051         cmd_resp->length = CPU_TO_LE32(dw_count);
6052
6053         status = i40e_asq_send_command(hw, &desc, buffer,
6054                                        I40E_LO_DWORD(4*dw_count), NULL);
6055
6056         return status;
6057 }
6058
6059 /**
6060  *  i40e_aq_alternate_clear
6061  *  @hw: pointer to the HW structure.
6062  *
6063  *  Clear the alternate structures of the port from which the function
6064  *  is called.
6065  *
6066  **/
6067 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6068 {
6069         struct i40e_aq_desc desc;
6070         enum i40e_status_code status;
6071
6072         i40e_fill_default_direct_cmd_desc(&desc,
6073                                           i40e_aqc_opc_alternate_clear_port);
6074
6075         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6076
6077         return status;
6078 }
6079
6080 /**
6081  *  i40e_aq_alternate_write_done
6082  *  @hw: pointer to the HW structure.
6083  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6084  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6085  *
6086  *  Indicates to the FW that alternate structures have been changed.
6087  *
6088  **/
6089 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6090                 u8 bios_mode, bool *reset_needed)
6091 {
6092         struct i40e_aq_desc desc;
6093         struct i40e_aqc_alternate_write_done *cmd =
6094                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6095         enum i40e_status_code status;
6096
6097         if (reset_needed == NULL)
6098                 return I40E_ERR_PARAM;
6099
6100         i40e_fill_default_direct_cmd_desc(&desc,
6101                                           i40e_aqc_opc_alternate_write_done);
6102
6103         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6104
6105         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6106         if (!status && reset_needed)
6107                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6108                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6109
6110         return status;
6111 }
6112
6113 /**
6114  *  i40e_aq_set_oem_mode
6115  *  @hw: pointer to the HW structure.
6116  *  @oem_mode: the OEM mode to be used
6117  *
6118  *  Sets the device to a specific operating mode. Currently the only supported
6119  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6120  *
6121  **/
6122 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6123                 u8 oem_mode)
6124 {
6125         struct i40e_aq_desc desc;
6126         struct i40e_aqc_alternate_write_done *cmd =
6127                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6128         enum i40e_status_code status;
6129
6130         i40e_fill_default_direct_cmd_desc(&desc,
6131                                           i40e_aqc_opc_alternate_set_mode);
6132
6133         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6134
6135         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6136
6137         return status;
6138 }
6139
6140 /**
6141  * i40e_aq_resume_port_tx
6142  * @hw: pointer to the hardware structure
6143  * @cmd_details: pointer to command details structure or NULL
6144  *
6145  * Resume port's Tx traffic
6146  **/
6147 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6148                                 struct i40e_asq_cmd_details *cmd_details)
6149 {
6150         struct i40e_aq_desc desc;
6151         enum i40e_status_code status;
6152
6153         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6154
6155         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6156
6157         return status;
6158 }
6159
6160 /**
6161  * i40e_set_pci_config_data - store PCI bus info
6162  * @hw: pointer to hardware structure
6163  * @link_status: the link status word from PCI config space
6164  *
6165  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6166  **/
6167 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6168 {
6169         hw->bus.type = i40e_bus_type_pci_express;
6170
6171         switch (link_status & I40E_PCI_LINK_WIDTH) {
6172         case I40E_PCI_LINK_WIDTH_1:
6173                 hw->bus.width = i40e_bus_width_pcie_x1;
6174                 break;
6175         case I40E_PCI_LINK_WIDTH_2:
6176                 hw->bus.width = i40e_bus_width_pcie_x2;
6177                 break;
6178         case I40E_PCI_LINK_WIDTH_4:
6179                 hw->bus.width = i40e_bus_width_pcie_x4;
6180                 break;
6181         case I40E_PCI_LINK_WIDTH_8:
6182                 hw->bus.width = i40e_bus_width_pcie_x8;
6183                 break;
6184         default:
6185                 hw->bus.width = i40e_bus_width_unknown;
6186                 break;
6187         }
6188
6189         switch (link_status & I40E_PCI_LINK_SPEED) {
6190         case I40E_PCI_LINK_SPEED_2500:
6191                 hw->bus.speed = i40e_bus_speed_2500;
6192                 break;
6193         case I40E_PCI_LINK_SPEED_5000:
6194                 hw->bus.speed = i40e_bus_speed_5000;
6195                 break;
6196         case I40E_PCI_LINK_SPEED_8000:
6197                 hw->bus.speed = i40e_bus_speed_8000;
6198                 break;
6199         default:
6200                 hw->bus.speed = i40e_bus_speed_unknown;
6201                 break;
6202         }
6203 }
6204
6205 /**
6206  * i40e_aq_debug_dump
6207  * @hw: pointer to the hardware structure
6208  * @cluster_id: specific cluster to dump
6209  * @table_id: table id within cluster
6210  * @start_index: index of line in the block to read
6211  * @buff_size: dump buffer size
6212  * @buff: dump buffer
6213  * @ret_buff_size: actual buffer size returned
6214  * @ret_next_table: next block to read
6215  * @ret_next_index: next index to read
6216  * @cmd_details: pointer to command details structure or NULL
6217  *
6218  * Dump internal FW/HW data for debug purposes.
6219  *
6220  **/
6221 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6222                                 u8 table_id, u32 start_index, u16 buff_size,
6223                                 void *buff, u16 *ret_buff_size,
6224                                 u8 *ret_next_table, u32 *ret_next_index,
6225                                 struct i40e_asq_cmd_details *cmd_details)
6226 {
6227         struct i40e_aq_desc desc;
6228         struct i40e_aqc_debug_dump_internals *cmd =
6229                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6230         struct i40e_aqc_debug_dump_internals *resp =
6231                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6232         enum i40e_status_code status;
6233
6234         if (buff_size == 0 || !buff)
6235                 return I40E_ERR_PARAM;
6236
6237         i40e_fill_default_direct_cmd_desc(&desc,
6238                                           i40e_aqc_opc_debug_dump_internals);
6239         /* Indirect Command */
6240         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6241         if (buff_size > I40E_AQ_LARGE_BUF)
6242                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6243
6244         cmd->cluster_id = cluster_id;
6245         cmd->table_id = table_id;
6246         cmd->idx = CPU_TO_LE32(start_index);
6247
6248         desc.datalen = CPU_TO_LE16(buff_size);
6249
6250         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6251         if (!status) {
6252                 if (ret_buff_size != NULL)
6253                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6254                 if (ret_next_table != NULL)
6255                         *ret_next_table = resp->table_id;
6256                 if (ret_next_index != NULL)
6257                         *ret_next_index = LE32_TO_CPU(resp->idx);
6258         }
6259
6260         return status;
6261 }
6262
6263 /**
6264  * i40e_read_bw_from_alt_ram
6265  * @hw: pointer to the hardware structure
6266  * @max_bw: pointer for max_bw read
6267  * @min_bw: pointer for min_bw read
6268  * @min_valid: pointer for bool that is true if min_bw is a valid value
6269  * @max_valid: pointer for bool that is true if max_bw is a valid value
6270  *
6271  * Read bw from the alternate ram for the given pf
6272  **/
6273 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6274                                         u32 *max_bw, u32 *min_bw,
6275                                         bool *min_valid, bool *max_valid)
6276 {
6277         enum i40e_status_code status;
6278         u32 max_bw_addr, min_bw_addr;
6279
6280         /* Calculate the address of the min/max bw registers */
6281         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6282                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6283                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6284         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6285                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6286                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6287
6288         /* Read the bandwidths from alt ram */
6289         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6290                                         min_bw_addr, min_bw);
6291
6292         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6293                 *min_valid = true;
6294         else
6295                 *min_valid = false;
6296
6297         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6298                 *max_valid = true;
6299         else
6300                 *max_valid = false;
6301
6302         return status;
6303 }
6304
6305 /**
6306  * i40e_aq_configure_partition_bw
6307  * @hw: pointer to the hardware structure
6308  * @bw_data: Buffer holding valid pfs and bw limits
6309  * @cmd_details: pointer to command details
6310  *
6311  * Configure partitions guaranteed/max bw
6312  **/
6313 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6314                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6315                         struct i40e_asq_cmd_details *cmd_details)
6316 {
6317         enum i40e_status_code status;
6318         struct i40e_aq_desc desc;
6319         u16 bwd_size = sizeof(*bw_data);
6320
6321         i40e_fill_default_direct_cmd_desc(&desc,
6322                                 i40e_aqc_opc_configure_partition_bw);
6323
6324         /* Indirect command */
6325         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6326         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6327
6328         desc.datalen = CPU_TO_LE16(bwd_size);
6329
6330         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6331
6332         return status;
6333 }
6334
6335 /**
6336  * i40e_read_phy_register_clause22
6337  * @hw: pointer to the HW structure
6338  * @reg: register address in the page
6339  * @phy_addr: PHY address on MDIO interface
6340  * @value: PHY register value
6341  *
6342  * Reads specified PHY register value
6343  **/
6344 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6345                                         u16 reg, u8 phy_addr, u16 *value)
6346 {
6347         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6348         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6349         u32 command = 0;
6350         u16 retry = 1000;
6351
6352         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6353                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6354                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6355                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6356                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6357         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6358         do {
6359                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6360                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6361                         status = I40E_SUCCESS;
6362                         break;
6363                 }
6364                 i40e_usec_delay(10);
6365                 retry--;
6366         } while (retry);
6367
6368         if (status) {
6369                 i40e_debug(hw, I40E_DEBUG_PHY,
6370                            "PHY: Can't write command to external PHY.\n");
6371         } else {
6372                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6373                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6374                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6375         }
6376
6377         return status;
6378 }
6379
6380 /**
6381  * i40e_write_phy_register_clause22
6382  * @hw: pointer to the HW structure
6383  * @reg: register address in the page
6384  * @phy_addr: PHY address on MDIO interface
6385  * @value: PHY register value
6386  *
6387  * Writes specified PHY register value
6388  **/
6389 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6390                                         u16 reg, u8 phy_addr, u16 value)
6391 {
6392         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6393         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6394         u32 command  = 0;
6395         u16 retry = 1000;
6396
6397         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6398         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6399
6400         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6401                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6402                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6403                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6404                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6405
6406         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6407         do {
6408                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6409                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6410                         status = I40E_SUCCESS;
6411                         break;
6412                 }
6413                 i40e_usec_delay(10);
6414                 retry--;
6415         } while (retry);
6416
6417         return status;
6418 }
6419
6420 /**
6421  * i40e_read_phy_register_clause45
6422  * @hw: pointer to the HW structure
6423  * @page: registers page number
6424  * @reg: register address in the page
6425  * @phy_addr: PHY address on MDIO interface
6426  * @value: PHY register value
6427  *
6428  * Reads specified PHY register value
6429  **/
6430 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6431                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6432 {
6433         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6434         u32 command  = 0;
6435         u16 retry = 1000;
6436         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6437
6438         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6439                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6440                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6441                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6442                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6443                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6444                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6445         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6446         do {
6447                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6448                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6449                         status = I40E_SUCCESS;
6450                         break;
6451                 }
6452                 i40e_usec_delay(10);
6453                 retry--;
6454         } while (retry);
6455
6456         if (status) {
6457                 i40e_debug(hw, I40E_DEBUG_PHY,
6458                            "PHY: Can't write command to external PHY.\n");
6459                 goto phy_read_end;
6460         }
6461
6462         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6463                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6464                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6465                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6466                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6467                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6468         status = I40E_ERR_TIMEOUT;
6469         retry = 1000;
6470         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6471         do {
6472                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6473                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6474                         status = I40E_SUCCESS;
6475                         break;
6476                 }
6477                 i40e_usec_delay(10);
6478                 retry--;
6479         } while (retry);
6480
6481         if (!status) {
6482                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6483                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6484                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6485         } else {
6486                 i40e_debug(hw, I40E_DEBUG_PHY,
6487                            "PHY: Can't read register value from external PHY.\n");
6488         }
6489
6490 phy_read_end:
6491         return status;
6492 }
6493
6494 /**
6495  * i40e_write_phy_register_clause45
6496  * @hw: pointer to the HW structure
6497  * @page: registers page number
6498  * @reg: register address in the page
6499  * @phy_addr: PHY address on MDIO interface
6500  * @value: PHY register value
6501  *
6502  * Writes value to specified PHY register
6503  **/
6504 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6505                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6506 {
6507         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6508         u32 command  = 0;
6509         u16 retry = 1000;
6510         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6511
6512         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6513                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6514                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6515                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6516                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6517                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6518                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6519         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6520         do {
6521                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6522                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6523                         status = I40E_SUCCESS;
6524                         break;
6525                 }
6526                 i40e_usec_delay(10);
6527                 retry--;
6528         } while (retry);
6529         if (status) {
6530                 i40e_debug(hw, I40E_DEBUG_PHY,
6531                            "PHY: Can't write command to external PHY.\n");
6532                 goto phy_write_end;
6533         }
6534
6535         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6536         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6537
6538         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6539                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6540                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6541                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6542                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6543                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6544         status = I40E_ERR_TIMEOUT;
6545         retry = 1000;
6546         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6547         do {
6548                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6549                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6550                         status = I40E_SUCCESS;
6551                         break;
6552                 }
6553                 i40e_usec_delay(10);
6554                 retry--;
6555         } while (retry);
6556
6557 phy_write_end:
6558         return status;
6559 }
6560
6561 /**
6562  * i40e_write_phy_register
6563  * @hw: pointer to the HW structure
6564  * @page: registers page number
6565  * @reg: register address in the page
6566  * @phy_addr: PHY address on MDIO interface
6567  * @value: PHY register value
6568  *
6569  * Writes value to specified PHY register
6570  **/
6571 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6572                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6573 {
6574         enum i40e_status_code status;
6575
6576         switch (hw->device_id) {
6577         case I40E_DEV_ID_1G_BASE_T_X722:
6578                 status = i40e_write_phy_register_clause22(hw,
6579                         reg, phy_addr, value);
6580                 break;
6581         case I40E_DEV_ID_10G_BASE_T:
6582         case I40E_DEV_ID_10G_BASE_T4:
6583         case I40E_DEV_ID_10G_BASE_T_X722:
6584         case I40E_DEV_ID_25G_B:
6585         case I40E_DEV_ID_25G_SFP28:
6586                 status = i40e_write_phy_register_clause45(hw,
6587                         page, reg, phy_addr, value);
6588                 break;
6589         default:
6590                 status = I40E_ERR_UNKNOWN_PHY;
6591                 break;
6592         }
6593
6594         return status;
6595 }
6596
6597 /**
6598  * i40e_read_phy_register
6599  * @hw: pointer to the HW structure
6600  * @page: registers page number
6601  * @reg: register address in the page
6602  * @phy_addr: PHY address on MDIO interface
6603  * @value: PHY register value
6604  *
6605  * Reads specified PHY register value
6606  **/
6607 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6608                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6609 {
6610         enum i40e_status_code status;
6611
6612         switch (hw->device_id) {
6613         case I40E_DEV_ID_1G_BASE_T_X722:
6614                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6615                                                          value);
6616                 break;
6617         case I40E_DEV_ID_10G_BASE_T:
6618         case I40E_DEV_ID_10G_BASE_T4:
6619         case I40E_DEV_ID_10G_BASE_T_X722:
6620         case I40E_DEV_ID_25G_B:
6621         case I40E_DEV_ID_25G_SFP28:
6622                 status = i40e_read_phy_register_clause45(hw, page, reg,
6623                                                          phy_addr, value);
6624                 break;
6625         default:
6626                 status = I40E_ERR_UNKNOWN_PHY;
6627                 break;
6628         }
6629
6630         return status;
6631 }
6632
6633 /**
6634  * i40e_get_phy_address
6635  * @hw: pointer to the HW structure
6636  * @dev_num: PHY port num that address we want
6637  *
6638  * Gets PHY address for current port
6639  **/
6640 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6641 {
6642         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6643         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6644
6645         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6646 }
6647
6648 /**
6649  * i40e_blink_phy_led
6650  * @hw: pointer to the HW structure
6651  * @time: time how long led will blinks in secs
6652  * @interval: gap between LED on and off in msecs
6653  *
6654  * Blinks PHY link LED
6655  **/
6656 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6657                                               u32 time, u32 interval)
6658 {
6659         enum i40e_status_code status = I40E_SUCCESS;
6660         u32 i;
6661         u16 led_ctl = 0;
6662         u16 gpio_led_port;
6663         u16 led_reg;
6664         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6665         u8 phy_addr = 0;
6666         u8 port_num;
6667
6668         i = rd32(hw, I40E_PFGEN_PORTNUM);
6669         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6670         phy_addr = i40e_get_phy_address(hw, port_num);
6671
6672         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6673              led_addr++) {
6674                 status = i40e_read_phy_register_clause45(hw,
6675                                                          I40E_PHY_COM_REG_PAGE,
6676                                                          led_addr, phy_addr,
6677                                                          &led_reg);
6678                 if (status)
6679                         goto phy_blinking_end;
6680                 led_ctl = led_reg;
6681                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6682                         led_reg = 0;
6683                         status = i40e_write_phy_register_clause45(hw,
6684                                                          I40E_PHY_COM_REG_PAGE,
6685                                                          led_addr, phy_addr,
6686                                                          led_reg);
6687                         if (status)
6688                                 goto phy_blinking_end;
6689                         break;
6690                 }
6691         }
6692
6693         if (time > 0 && interval > 0) {
6694                 for (i = 0; i < time * 1000; i += interval) {
6695                         status = i40e_read_phy_register_clause45(hw,
6696                                                 I40E_PHY_COM_REG_PAGE,
6697                                                 led_addr, phy_addr, &led_reg);
6698                         if (status)
6699                                 goto restore_config;
6700                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6701                                 led_reg = 0;
6702                         else
6703                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6704                         status = i40e_write_phy_register_clause45(hw,
6705                                                 I40E_PHY_COM_REG_PAGE,
6706                                                 led_addr, phy_addr, led_reg);
6707                         if (status)
6708                                 goto restore_config;
6709                         i40e_msec_delay(interval);
6710                 }
6711         }
6712
6713 restore_config:
6714         status = i40e_write_phy_register_clause45(hw,
6715                                                   I40E_PHY_COM_REG_PAGE,
6716                                                   led_addr, phy_addr, led_ctl);
6717
6718 phy_blinking_end:
6719         return status;
6720 }
6721
6722 /**
6723  * i40e_led_get_reg - read LED register
6724  * @hw: pointer to the HW structure
6725  * @led_addr: LED register address
6726  * @reg_val: read register value
6727  **/
6728 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6729                                               u32 *reg_val)
6730 {
6731         enum i40e_status_code status;
6732         u8 phy_addr = 0;
6733
6734         *reg_val = 0;
6735         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6736                 status = i40e_aq_get_phy_register(hw,
6737                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6738                                                 I40E_PHY_COM_REG_PAGE,
6739                                                 I40E_PHY_LED_PROV_REG_1,
6740                                                 reg_val, NULL);
6741         } else {
6742                 phy_addr = i40e_get_phy_address(hw, hw->port);
6743                 status = i40e_read_phy_register_clause45(hw,
6744                                                          I40E_PHY_COM_REG_PAGE,
6745                                                          led_addr, phy_addr,
6746                                                          (u16 *)reg_val);
6747         }
6748         return status;
6749 }
6750
6751 /**
6752  * i40e_led_set_reg - write LED register
6753  * @hw: pointer to the HW structure
6754  * @led_addr: LED register address
6755  * @reg_val: register value to write
6756  **/
6757 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6758                                               u32 reg_val)
6759 {
6760         enum i40e_status_code status;
6761         u8 phy_addr = 0;
6762
6763         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6764                 status = i40e_aq_set_phy_register(hw,
6765                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6766                                                 I40E_PHY_COM_REG_PAGE,
6767                                                 I40E_PHY_LED_PROV_REG_1,
6768                                                 reg_val, NULL);
6769         } else {
6770                 phy_addr = i40e_get_phy_address(hw, hw->port);
6771                 status = i40e_write_phy_register_clause45(hw,
6772                                                           I40E_PHY_COM_REG_PAGE,
6773                                                           led_addr, phy_addr,
6774                                                           (u16)reg_val);
6775         }
6776
6777         return status;
6778 }
6779
6780 /**
6781  * i40e_led_get_phy - return current on/off mode
6782  * @hw: pointer to the hw struct
6783  * @led_addr: address of led register to use
6784  * @val: original value of register to use
6785  *
6786  **/
6787 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6788                                        u16 *val)
6789 {
6790         enum i40e_status_code status = I40E_SUCCESS;
6791         u16 gpio_led_port;
6792         u32 reg_val_aq;
6793         u16 temp_addr;
6794         u8 phy_addr = 0;
6795         u16 reg_val;
6796
6797         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6798                 status = i40e_aq_get_phy_register(hw,
6799                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6800                                                 I40E_PHY_COM_REG_PAGE,
6801                                                 I40E_PHY_LED_PROV_REG_1,
6802                                                 &reg_val_aq, NULL);
6803                 if (status == I40E_SUCCESS)
6804                         *val = (u16)reg_val_aq;
6805                 return status;
6806         }
6807         temp_addr = I40E_PHY_LED_PROV_REG_1;
6808         phy_addr = i40e_get_phy_address(hw, hw->port);
6809         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6810              temp_addr++) {
6811                 status = i40e_read_phy_register_clause45(hw,
6812                                                          I40E_PHY_COM_REG_PAGE,
6813                                                          temp_addr, phy_addr,
6814                                                          &reg_val);
6815                 if (status)
6816                         return status;
6817                 *val = reg_val;
6818                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6819                         *led_addr = temp_addr;
6820                         break;
6821                 }
6822         }
6823         return status;
6824 }
6825
6826 /**
6827  * i40e_led_set_phy
6828  * @hw: pointer to the HW structure
6829  * @on: true or false
6830  * @led_addr: address of led register to use
6831  * @mode: original val plus bit for set or ignore
6832  *
6833  * Set led's on or off when controlled by the PHY
6834  *
6835  **/
6836 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6837                                        u16 led_addr, u32 mode)
6838 {
6839         enum i40e_status_code status = I40E_SUCCESS;
6840         u32 led_ctl = 0;
6841         u32 led_reg = 0;
6842
6843         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6844         if (status)
6845                 return status;
6846         led_ctl = led_reg;
6847         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6848                 led_reg = 0;
6849                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6850                 if (status)
6851                         return status;
6852         }
6853         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6854         if (status)
6855                 goto restore_config;
6856         if (on)
6857                 led_reg = I40E_PHY_LED_MANUAL_ON;
6858         else
6859                 led_reg = 0;
6860         status = i40e_led_set_reg(hw, led_addr, led_reg);
6861         if (status)
6862                 goto restore_config;
6863         if (mode & I40E_PHY_LED_MODE_ORIG) {
6864                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6865                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6866         }
6867         return status;
6868
6869 restore_config:
6870         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6871         return status;
6872 }
6873 #endif /* PF_DRIVER */
6874
6875 /**
6876  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6877  * @hw: pointer to the hw struct
6878  * @reg_addr: register address
6879  * @reg_val: ptr to register value
6880  * @cmd_details: pointer to command details structure or NULL
6881  *
6882  * Use the firmware to read the Rx control register,
6883  * especially useful if the Rx unit is under heavy pressure
6884  **/
6885 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6886                                 u32 reg_addr, u32 *reg_val,
6887                                 struct i40e_asq_cmd_details *cmd_details)
6888 {
6889         struct i40e_aq_desc desc;
6890         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6891                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6892         enum i40e_status_code status;
6893
6894         if (reg_val == NULL)
6895                 return I40E_ERR_PARAM;
6896
6897         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6898
6899         cmd_resp->address = CPU_TO_LE32(reg_addr);
6900
6901         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6902
6903         if (status == I40E_SUCCESS)
6904                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6905
6906         return status;
6907 }
6908
6909 /**
6910  * i40e_read_rx_ctl - read from an Rx control register
6911  * @hw: pointer to the hw struct
6912  * @reg_addr: register address
6913  **/
6914 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6915 {
6916         enum i40e_status_code status = I40E_SUCCESS;
6917         bool use_register;
6918         int retry = 5;
6919         u32 val = 0;
6920
6921         use_register = (((hw->aq.api_maj_ver == 1) &&
6922                         (hw->aq.api_min_ver < 5)) ||
6923                         (hw->mac.type == I40E_MAC_X722));
6924         if (!use_register) {
6925 do_retry:
6926                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6927                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6928                         i40e_msec_delay(1);
6929                         retry--;
6930                         goto do_retry;
6931                 }
6932         }
6933
6934         /* if the AQ access failed, try the old-fashioned way */
6935         if (status || use_register)
6936                 val = rd32(hw, reg_addr);
6937
6938         return val;
6939 }
6940
6941 /**
6942  * i40e_aq_rx_ctl_write_register
6943  * @hw: pointer to the hw struct
6944  * @reg_addr: register address
6945  * @reg_val: register value
6946  * @cmd_details: pointer to command details structure or NULL
6947  *
6948  * Use the firmware to write to an Rx control register,
6949  * especially useful if the Rx unit is under heavy pressure
6950  **/
6951 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6952                                 u32 reg_addr, u32 reg_val,
6953                                 struct i40e_asq_cmd_details *cmd_details)
6954 {
6955         struct i40e_aq_desc desc;
6956         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6957                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6958         enum i40e_status_code status;
6959
6960         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6961
6962         cmd->address = CPU_TO_LE32(reg_addr);
6963         cmd->value = CPU_TO_LE32(reg_val);
6964
6965         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6966
6967         return status;
6968 }
6969
6970 /**
6971  * i40e_write_rx_ctl - write to an Rx control register
6972  * @hw: pointer to the hw struct
6973  * @reg_addr: register address
6974  * @reg_val: register value
6975  **/
6976 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6977 {
6978         enum i40e_status_code status = I40E_SUCCESS;
6979         bool use_register;
6980         int retry = 5;
6981
6982         use_register = (((hw->aq.api_maj_ver == 1) &&
6983                         (hw->aq.api_min_ver < 5)) ||
6984                         (hw->mac.type == I40E_MAC_X722));
6985         if (!use_register) {
6986 do_retry:
6987                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6988                                                        reg_val, NULL);
6989                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6990                         i40e_msec_delay(1);
6991                         retry--;
6992                         goto do_retry;
6993                 }
6994         }
6995
6996         /* if the AQ access failed, try the old-fashioned way */
6997         if (status || use_register)
6998                 wr32(hw, reg_addr, reg_val);
6999 }
7000
7001 /**
7002  * i40e_aq_set_phy_register
7003  * @hw: pointer to the hw struct
7004  * @phy_select: select which phy should be accessed
7005  * @dev_addr: PHY device address
7006  * @reg_addr: PHY register address
7007  * @reg_val: new register value
7008  * @cmd_details: pointer to command details structure or NULL
7009  *
7010  * Write the external PHY register.
7011  **/
7012 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7013                                 u8 phy_select, u8 dev_addr,
7014                                 u32 reg_addr, u32 reg_val,
7015                                 struct i40e_asq_cmd_details *cmd_details)
7016 {
7017         struct i40e_aq_desc desc;
7018         struct i40e_aqc_phy_register_access *cmd =
7019                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7020         enum i40e_status_code status;
7021
7022         i40e_fill_default_direct_cmd_desc(&desc,
7023                                           i40e_aqc_opc_set_phy_register);
7024
7025         cmd->phy_interface = phy_select;
7026         cmd->dev_addres = dev_addr;
7027         cmd->reg_address = CPU_TO_LE32(reg_addr);
7028         cmd->reg_value = CPU_TO_LE32(reg_val);
7029
7030         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7031
7032         return status;
7033 }
7034
7035 /**
7036  * i40e_aq_get_phy_register
7037  * @hw: pointer to the hw struct
7038  * @phy_select: select which phy should be accessed
7039  * @dev_addr: PHY device address
7040  * @reg_addr: PHY register address
7041  * @reg_val: read register value
7042  * @cmd_details: pointer to command details structure or NULL
7043  *
7044  * Read the external PHY register.
7045  **/
7046 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7047                                 u8 phy_select, u8 dev_addr,
7048                                 u32 reg_addr, u32 *reg_val,
7049                                 struct i40e_asq_cmd_details *cmd_details)
7050 {
7051         struct i40e_aq_desc desc;
7052         struct i40e_aqc_phy_register_access *cmd =
7053                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7054         enum i40e_status_code status;
7055
7056         i40e_fill_default_direct_cmd_desc(&desc,
7057                                           i40e_aqc_opc_get_phy_register);
7058
7059         cmd->phy_interface = phy_select;
7060         cmd->dev_addres = dev_addr;
7061         cmd->reg_address = CPU_TO_LE32(reg_addr);
7062
7063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7064         if (!status)
7065                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7066
7067         return status;
7068 }
7069
7070 #ifdef VF_DRIVER
7071
7072 /**
7073  * i40e_aq_send_msg_to_pf
7074  * @hw: pointer to the hardware structure
7075  * @v_opcode: opcodes for VF-PF communication
7076  * @v_retval: return error code
7077  * @msg: pointer to the msg buffer
7078  * @msglen: msg length
7079  * @cmd_details: pointer to command details
7080  *
7081  * Send message to PF driver using admin queue. By default, this message
7082  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7083  * completion before returning.
7084  **/
7085 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7086                                 enum virtchnl_ops v_opcode,
7087                                 enum i40e_status_code v_retval,
7088                                 u8 *msg, u16 msglen,
7089                                 struct i40e_asq_cmd_details *cmd_details)
7090 {
7091         struct i40e_aq_desc desc;
7092         struct i40e_asq_cmd_details details;
7093         enum i40e_status_code status;
7094
7095         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7096         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7097         desc.cookie_high = CPU_TO_LE32(v_opcode);
7098         desc.cookie_low = CPU_TO_LE32(v_retval);
7099         if (msglen) {
7100                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7101                                                 | I40E_AQ_FLAG_RD));
7102                 if (msglen > I40E_AQ_LARGE_BUF)
7103                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7104                 desc.datalen = CPU_TO_LE16(msglen);
7105         }
7106         if (!cmd_details) {
7107                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7108                 details.async = true;
7109                 cmd_details = &details;
7110         }
7111         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7112                                        msglen, cmd_details);
7113         return status;
7114 }
7115
7116 /**
7117  * i40e_vf_parse_hw_config
7118  * @hw: pointer to the hardware structure
7119  * @msg: pointer to the virtual channel VF resource structure
7120  *
7121  * Given a VF resource message from the PF, populate the hw struct
7122  * with appropriate information.
7123  **/
7124 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7125                              struct virtchnl_vf_resource *msg)
7126 {
7127         struct virtchnl_vsi_resource *vsi_res;
7128         int i;
7129
7130         vsi_res = &msg->vsi_res[0];
7131
7132         hw->dev_caps.num_vsis = msg->num_vsis;
7133         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7134         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7135         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7136         hw->dev_caps.dcb = msg->vf_offload_flags &
7137                            VIRTCHNL_VF_OFFLOAD_L2;
7138         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7139                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7140         for (i = 0; i < msg->num_vsis; i++) {
7141                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7142                         i40e_memcpy(hw->mac.perm_addr,
7143                                     vsi_res->default_mac_addr,
7144                                     ETH_ALEN,
7145                                     I40E_NONDMA_TO_NONDMA);
7146                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7147                                     ETH_ALEN,
7148                                     I40E_NONDMA_TO_NONDMA);
7149                 }
7150                 vsi_res++;
7151         }
7152 }
7153
7154 /**
7155  * i40e_vf_reset
7156  * @hw: pointer to the hardware structure
7157  *
7158  * Send a VF_RESET message to the PF. Does not wait for response from PF
7159  * as none will be forthcoming. Immediately after calling this function,
7160  * the admin queue should be shut down and (optionally) reinitialized.
7161  **/
7162 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7163 {
7164         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7165                                       I40E_SUCCESS, NULL, 0, NULL);
7166 }
7167 #endif /* VF_DRIVER */
7168
7169 /**
7170  * i40e_aq_set_arp_proxy_config
7171  * @hw: pointer to the HW structure
7172  * @proxy_config: pointer to proxy config command table struct
7173  * @cmd_details: pointer to command details
7174  *
7175  * Set ARP offload parameters from pre-populated
7176  * i40e_aqc_arp_proxy_data struct
7177  **/
7178 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7179                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7180                                 struct i40e_asq_cmd_details *cmd_details)
7181 {
7182         struct i40e_aq_desc desc;
7183         enum i40e_status_code status;
7184
7185         if (!proxy_config)
7186                 return I40E_ERR_PARAM;
7187
7188         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7189
7190         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7191         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7192         desc.params.external.addr_high =
7193                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7194         desc.params.external.addr_low =
7195                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7196         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7197
7198         status = i40e_asq_send_command(hw, &desc, proxy_config,
7199                                        sizeof(struct i40e_aqc_arp_proxy_data),
7200                                        cmd_details);
7201
7202         return status;
7203 }
7204
7205 /**
7206  * i40e_aq_opc_set_ns_proxy_table_entry
7207  * @hw: pointer to the HW structure
7208  * @ns_proxy_table_entry: pointer to NS table entry command struct
7209  * @cmd_details: pointer to command details
7210  *
7211  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7212  * from pre-populated i40e_aqc_ns_proxy_data struct
7213  **/
7214 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7215                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7216                         struct i40e_asq_cmd_details *cmd_details)
7217 {
7218         struct i40e_aq_desc desc;
7219         enum i40e_status_code status;
7220
7221         if (!ns_proxy_table_entry)
7222                 return I40E_ERR_PARAM;
7223
7224         i40e_fill_default_direct_cmd_desc(&desc,
7225                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7226
7227         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7228         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7229         desc.params.external.addr_high =
7230                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7231         desc.params.external.addr_low =
7232                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7233         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7234
7235         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7236                                        sizeof(struct i40e_aqc_ns_proxy_data),
7237                                        cmd_details);
7238
7239         return status;
7240 }
7241
7242 /**
7243  * i40e_aq_set_clear_wol_filter
7244  * @hw: pointer to the hw struct
7245  * @filter_index: index of filter to modify (0-7)
7246  * @filter: buffer containing filter to be set
7247  * @set_filter: true to set filter, false to clear filter
7248  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7249  *              if false, pass through packets may cause wake-up
7250  * @filter_valid: true if filter action is valid
7251  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7252  * @cmd_details: pointer to command details structure or NULL
7253  *
7254  * Set or clear WoL filter for port attached to the PF
7255  **/
7256 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7257                                 u8 filter_index,
7258                                 struct i40e_aqc_set_wol_filter_data *filter,
7259                                 bool set_filter, bool no_wol_tco,
7260                                 bool filter_valid, bool no_wol_tco_valid,
7261                                 struct i40e_asq_cmd_details *cmd_details)
7262 {
7263         struct i40e_aq_desc desc;
7264         struct i40e_aqc_set_wol_filter *cmd =
7265                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7266         enum i40e_status_code status;
7267         u16 cmd_flags = 0;
7268         u16 valid_flags = 0;
7269         u16 buff_len = 0;
7270
7271         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7272
7273         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7274                 return  I40E_ERR_PARAM;
7275         cmd->filter_index = CPU_TO_LE16(filter_index);
7276
7277         if (set_filter) {
7278                 if (!filter)
7279                         return  I40E_ERR_PARAM;
7280
7281                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7282                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7283         }
7284
7285         if (no_wol_tco)
7286                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7287         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7288
7289         if (filter_valid)
7290                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7291         if (no_wol_tco_valid)
7292                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7293         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7294
7295         buff_len = sizeof(*filter);
7296         desc.datalen = CPU_TO_LE16(buff_len);
7297
7298         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7299         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7300
7301         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7302         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7303
7304         status = i40e_asq_send_command(hw, &desc, filter,
7305                                        buff_len, cmd_details);
7306
7307         return status;
7308 }
7309
7310 /**
7311  * i40e_aq_get_wake_event_reason
7312  * @hw: pointer to the hw struct
7313  * @wake_reason: return value, index of matching filter
7314  * @cmd_details: pointer to command details structure or NULL
7315  *
7316  * Get information for the reason of a Wake Up event
7317  **/
7318 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7319                                 u16 *wake_reason,
7320                                 struct i40e_asq_cmd_details *cmd_details)
7321 {
7322         struct i40e_aq_desc desc;
7323         struct i40e_aqc_get_wake_reason_completion *resp =
7324                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7325         enum i40e_status_code status;
7326
7327         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7328
7329         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7330
7331         if (status == I40E_SUCCESS)
7332                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7333
7334         return status;
7335 }
7336
7337 /**
7338 * i40e_aq_clear_all_wol_filters
7339 * @hw: pointer to the hw struct
7340 * @cmd_details: pointer to command details structure or NULL
7341 *
7342 * Get information for the reason of a Wake Up event
7343 **/
7344 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7345         struct i40e_asq_cmd_details *cmd_details)
7346 {
7347         struct i40e_aq_desc desc;
7348         enum i40e_status_code status;
7349
7350         i40e_fill_default_direct_cmd_desc(&desc,
7351                                           i40e_aqc_opc_clear_all_wol_filters);
7352
7353         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7354
7355         return status;
7356 }
7357
7358 /**
7359  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7360  * @hw: pointer to the hw struct
7361  * @buff: command buffer (size in bytes = buff_size)
7362  * @buff_size: buffer size in bytes
7363  * @track_id: package tracking id
7364  * @error_offset: returns error offset
7365  * @error_info: returns error information
7366  * @cmd_details: pointer to command details structure or NULL
7367  **/
7368 enum
7369 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7370                                    u16 buff_size, u32 track_id,
7371                                    u32 *error_offset, u32 *error_info,
7372                                    struct i40e_asq_cmd_details *cmd_details)
7373 {
7374         struct i40e_aq_desc desc;
7375         struct i40e_aqc_write_personalization_profile *cmd =
7376                 (struct i40e_aqc_write_personalization_profile *)
7377                 &desc.params.raw;
7378         struct i40e_aqc_write_ddp_resp *resp;
7379         enum i40e_status_code status;
7380
7381         i40e_fill_default_direct_cmd_desc(&desc,
7382                                   i40e_aqc_opc_write_personalization_profile);
7383
7384         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7385         if (buff_size > I40E_AQ_LARGE_BUF)
7386                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7387
7388         desc.datalen = CPU_TO_LE16(buff_size);
7389
7390         cmd->profile_track_id = CPU_TO_LE32(track_id);
7391
7392         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7393         if (!status) {
7394                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7395                 if (error_offset)
7396                         *error_offset = LE32_TO_CPU(resp->error_offset);
7397                 if (error_info)
7398                         *error_info = LE32_TO_CPU(resp->error_info);
7399         }
7400
7401         return status;
7402 }
7403
7404 /**
7405  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7406  * @hw: pointer to the hw struct
7407  * @buff: command buffer (size in bytes = buff_size)
7408  * @buff_size: buffer size in bytes
7409  * @flags: AdminQ command flags
7410  * @cmd_details: pointer to command details structure or NULL
7411  **/
7412 enum
7413 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7414                                       u16 buff_size, u8 flags,
7415                                       struct i40e_asq_cmd_details *cmd_details)
7416 {
7417         struct i40e_aq_desc desc;
7418         struct i40e_aqc_get_applied_profiles *cmd =
7419                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7420         enum i40e_status_code status;
7421
7422         i40e_fill_default_direct_cmd_desc(&desc,
7423                           i40e_aqc_opc_get_personalization_profile_list);
7424
7425         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7426         if (buff_size > I40E_AQ_LARGE_BUF)
7427                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7428         desc.datalen = CPU_TO_LE16(buff_size);
7429
7430         cmd->flags = flags;
7431
7432         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7433
7434         return status;
7435 }
7436
7437 /**
7438  * i40e_find_segment_in_package
7439  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7440  * @pkg_hdr: pointer to the package header to be searched
7441  *
7442  * This function searches a package file for a particular segment type. On
7443  * success it returns a pointer to the segment header, otherwise it will
7444  * return NULL.
7445  **/
7446 struct i40e_generic_seg_header *
7447 i40e_find_segment_in_package(u32 segment_type,
7448                              struct i40e_package_header *pkg_hdr)
7449 {
7450         struct i40e_generic_seg_header *segment;
7451         u32 i;
7452
7453         /* Search all package segments for the requested segment type */
7454         for (i = 0; i < pkg_hdr->segment_count; i++) {
7455                 segment =
7456                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7457                          pkg_hdr->segment_offset[i]);
7458
7459                 if (segment->type == segment_type)
7460                         return segment;
7461         }
7462
7463         return NULL;
7464 }
7465
7466 /* Get section table in profile */
7467 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7468         do {                                                            \
7469                 struct i40e_profile_segment *p = (profile);             \
7470                 u32 count;                                              \
7471                 u32 *nvm;                                               \
7472                 count = p->device_table_count;                          \
7473                 nvm = (u32 *)&p->device_table[count];                   \
7474                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7475         } while (0)
7476
7477 /* Get section header in profile */
7478 #define I40E_SECTION_HEADER(profile, offset)                            \
7479         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7480
7481 /**
7482  * i40e_find_section_in_profile
7483  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7484  * @profile: pointer to the i40e segment header to be searched
7485  *
7486  * This function searches i40e segment for a particular section type. On
7487  * success it returns a pointer to the section header, otherwise it will
7488  * return NULL.
7489  **/
7490 struct i40e_profile_section_header *
7491 i40e_find_section_in_profile(u32 section_type,
7492                              struct i40e_profile_segment *profile)
7493 {
7494         struct i40e_profile_section_header *sec;
7495         struct i40e_section_table *sec_tbl;
7496         u32 sec_off;
7497         u32 i;
7498
7499         if (profile->header.type != SEGMENT_TYPE_I40E)
7500                 return NULL;
7501
7502         I40E_SECTION_TABLE(profile, sec_tbl);
7503
7504         for (i = 0; i < sec_tbl->section_count; i++) {
7505                 sec_off = sec_tbl->section_offset[i];
7506                 sec = I40E_SECTION_HEADER(profile, sec_off);
7507                 if (sec->section.type == section_type)
7508                         return sec;
7509         }
7510
7511         return NULL;
7512 }
7513
7514 /**
7515  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7516  * @hw: pointer to the hw struct
7517  * @aq: command buffer containing all data to execute AQ
7518  **/
7519 STATIC enum
7520 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7521                                           struct i40e_profile_aq_section *aq)
7522 {
7523         enum i40e_status_code status;
7524         struct i40e_aq_desc desc;
7525         u8 *msg = NULL;
7526         u16 msglen;
7527
7528         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7529         desc.flags |= CPU_TO_LE16(aq->flags);
7530         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7531                     I40E_NONDMA_TO_NONDMA);
7532
7533         msglen = aq->datalen;
7534         if (msglen) {
7535                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7536                                                 I40E_AQ_FLAG_RD));
7537                 if (msglen > I40E_AQ_LARGE_BUF)
7538                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7539                 desc.datalen = CPU_TO_LE16(msglen);
7540                 msg = &aq->data[0];
7541         }
7542
7543         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7544
7545         if (status != I40E_SUCCESS) {
7546                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7547                            "unable to exec DDP AQ opcode %u, error %d\n",
7548                            aq->opcode, status);
7549                 return status;
7550         }
7551
7552         /* copy returned desc to aq_buf */
7553         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7554                     I40E_NONDMA_TO_NONDMA);
7555
7556         return I40E_SUCCESS;
7557 }
7558
7559 /**
7560  * i40e_validate_profile
7561  * @hw: pointer to the hardware structure
7562  * @profile: pointer to the profile segment of the package to be validated
7563  * @track_id: package tracking id
7564  * @rollback: flag if the profile is for rollback.
7565  *
7566  * Validates supported devices and profile's sections.
7567  */
7568 STATIC enum i40e_status_code
7569 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7570                       u32 track_id, bool rollback)
7571 {
7572         struct i40e_profile_section_header *sec = NULL;
7573         enum i40e_status_code status = I40E_SUCCESS;
7574         struct i40e_section_table *sec_tbl;
7575         u32 vendor_dev_id;
7576         u32 dev_cnt;
7577         u32 sec_off;
7578         u32 i;
7579
7580         if (track_id == I40E_DDP_TRACKID_INVALID) {
7581                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7582                 return I40E_NOT_SUPPORTED;
7583         }
7584
7585         dev_cnt = profile->device_table_count;
7586         for (i = 0; i < dev_cnt; i++) {
7587                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7588                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7589                     hw->device_id == (vendor_dev_id & 0xFFFF))
7590                         break;
7591         }
7592         if (dev_cnt && (i == dev_cnt)) {
7593                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7594                            "Device doesn't support DDP\n");
7595                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7596         }
7597
7598         I40E_SECTION_TABLE(profile, sec_tbl);
7599
7600         /* Validate sections types */
7601         for (i = 0; i < sec_tbl->section_count; i++) {
7602                 sec_off = sec_tbl->section_offset[i];
7603                 sec = I40E_SECTION_HEADER(profile, sec_off);
7604                 if (rollback) {
7605                         if (sec->section.type == SECTION_TYPE_MMIO ||
7606                             sec->section.type == SECTION_TYPE_AQ ||
7607                             sec->section.type == SECTION_TYPE_RB_AQ) {
7608                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7609                                            "Not a roll-back package\n");
7610                                 return I40E_NOT_SUPPORTED;
7611                         }
7612                 } else {
7613                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7614                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7615                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7616                                            "Not an original package\n");
7617                                 return I40E_NOT_SUPPORTED;
7618                         }
7619                 }
7620         }
7621
7622         return status;
7623 }
7624
7625 /**
7626  * i40e_write_profile
7627  * @hw: pointer to the hardware structure
7628  * @profile: pointer to the profile segment of the package to be downloaded
7629  * @track_id: package tracking id
7630  *
7631  * Handles the download of a complete package.
7632  */
7633 enum i40e_status_code
7634 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7635                    u32 track_id)
7636 {
7637         enum i40e_status_code status = I40E_SUCCESS;
7638         struct i40e_section_table *sec_tbl;
7639         struct i40e_profile_section_header *sec = NULL;
7640         struct i40e_profile_aq_section *ddp_aq;
7641         u32 section_size = 0;
7642         u32 offset = 0, info = 0;
7643         u32 sec_off;
7644         u32 i;
7645
7646         status = i40e_validate_profile(hw, profile, track_id, false);
7647         if (status)
7648                 return status;
7649
7650         I40E_SECTION_TABLE(profile, sec_tbl);
7651
7652         for (i = 0; i < sec_tbl->section_count; i++) {
7653                 sec_off = sec_tbl->section_offset[i];
7654                 sec = I40E_SECTION_HEADER(profile, sec_off);
7655                 /* Process generic admin command */
7656                 if (sec->section.type == SECTION_TYPE_AQ) {
7657                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7658                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7659                         if (status) {
7660                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7661                                            "Failed to execute aq: section %d, opcode %u\n",
7662                                            i, ddp_aq->opcode);
7663                                 break;
7664                         }
7665                         sec->section.type = SECTION_TYPE_RB_AQ;
7666                 }
7667
7668                 /* Skip any non-mmio sections */
7669                 if (sec->section.type != SECTION_TYPE_MMIO)
7670                         continue;
7671
7672                 section_size = sec->section.size +
7673                         sizeof(struct i40e_profile_section_header);
7674
7675                 /* Write MMIO section */
7676                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7677                                            track_id, &offset, &info, NULL);
7678                 if (status) {
7679                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7680                                    "Failed to write profile: section %d, offset %d, info %d\n",
7681                                    i, offset, info);
7682                         break;
7683                 }
7684         }
7685         return status;
7686 }
7687
7688 /**
7689  * i40e_rollback_profile
7690  * @hw: pointer to the hardware structure
7691  * @profile: pointer to the profile segment of the package to be removed
7692  * @track_id: package tracking id
7693  *
7694  * Rolls back previously loaded package.
7695  */
7696 enum i40e_status_code
7697 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7698                       u32 track_id)
7699 {
7700         struct i40e_profile_section_header *sec = NULL;
7701         enum i40e_status_code status = I40E_SUCCESS;
7702         struct i40e_section_table *sec_tbl;
7703         u32 offset = 0, info = 0;
7704         u32 section_size = 0;
7705         u32 sec_off;
7706         int i;
7707
7708         status = i40e_validate_profile(hw, profile, track_id, true);
7709         if (status)
7710                 return status;
7711
7712         I40E_SECTION_TABLE(profile, sec_tbl);
7713
7714         /* For rollback write sections in reverse */
7715         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7716                 sec_off = sec_tbl->section_offset[i];
7717                 sec = I40E_SECTION_HEADER(profile, sec_off);
7718
7719                 /* Skip any non-rollback sections */
7720                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7721                         continue;
7722
7723                 section_size = sec->section.size +
7724                         sizeof(struct i40e_profile_section_header);
7725
7726                 /* Write roll-back MMIO section */
7727                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7728                                            track_id, &offset, &info, NULL);
7729                 if (status) {
7730                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7731                                    "Failed to write profile: section %d, offset %d, info %d\n",
7732                                    i, offset, info);
7733                         break;
7734                 }
7735         }
7736         return status;
7737 }
7738
7739 /**
7740  * i40e_add_pinfo_to_list
7741  * @hw: pointer to the hardware structure
7742  * @profile: pointer to the profile segment of the package
7743  * @profile_info_sec: buffer for information section
7744  * @track_id: package tracking id
7745  *
7746  * Register a profile to the list of loaded profiles.
7747  */
7748 enum i40e_status_code
7749 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7750                        struct i40e_profile_segment *profile,
7751                        u8 *profile_info_sec, u32 track_id)
7752 {
7753         enum i40e_status_code status = I40E_SUCCESS;
7754         struct i40e_profile_section_header *sec = NULL;
7755         struct i40e_profile_info *pinfo;
7756         u32 offset = 0, info = 0;
7757
7758         sec = (struct i40e_profile_section_header *)profile_info_sec;
7759         sec->tbl_size = 1;
7760         sec->data_end = sizeof(struct i40e_profile_section_header) +
7761                         sizeof(struct i40e_profile_info);
7762         sec->section.type = SECTION_TYPE_INFO;
7763         sec->section.offset = sizeof(struct i40e_profile_section_header);
7764         sec->section.size = sizeof(struct i40e_profile_info);
7765         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7766                                              sec->section.offset);
7767         pinfo->track_id = track_id;
7768         pinfo->version = profile->version;
7769         pinfo->op = I40E_DDP_ADD_TRACKID;
7770         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7771                     I40E_NONDMA_TO_NONDMA);
7772
7773         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7774                                    track_id, &offset, &info, NULL);
7775         return status;
7776 }