drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u8 *buf = (u8 *)buffer;
 334         u16 len;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         len = LE16_TO_CPU(aq_desc->datalen);
 341
 342         i40e_debug(hw, mask,
 343                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 344                    LE16_TO_CPU(aq_desc->opcode),
 345                    LE16_TO_CPU(aq_desc->flags),
 346                    LE16_TO_CPU(aq_desc->datalen),
 347                    LE16_TO_CPU(aq_desc->retval));
 348         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 349                    LE32_TO_CPU(aq_desc->cookie_high),
 350                    LE32_TO_CPU(aq_desc->cookie_low));
 351         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->params.internal.param0),
 353                    LE32_TO_CPU(aq_desc->params.internal.param1));
 354         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 355                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 356                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 357
 358         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 359                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 360                 if (buf_len < len)
 361                         len = buf_len;
 362                 /* write the full 16-byte chunks */
 363                 for (i = 0; i < (len - 16); i += 16)
 364                         i40e_debug(hw, mask,
 365                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 366                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 367                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 368                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 369                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 370                 /* the most we could have left is 16 bytes, pad with zeros */
 371                 if (i < len) {
 372                         char d_buf[16];
 373                         int j, i_sav;
 374
 375                         i_sav = i;
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446
 447 /**
 448  * i40e_aq_get_set_rss_lut
 449  * @hw: pointer to the hardware structure
 450  * @vsi_id: vsi fw index
 451  * @pf_lut: for PF table set true, for VSI table set false
 452  * @lut: pointer to the lut buffer provided by the caller
 453  * @lut_size: size of the lut buffer
 454  * @set: set true to set the table, false to get the table
 455  *
 456  * Internal function to get or set RSS look up table
 457  **/
 458 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 459                                                      u16 vsi_id, bool pf_lut,
 460                                                      u8 *lut, u16 lut_size,
 461                                                      bool set)
 462 {
 463         enum i40e_status_code status;
 464         struct i40e_aq_desc desc;
 465         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 466                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 467
 468         if (set)
 469                 i40e_fill_default_direct_cmd_desc(&desc,
 470                                                   i40e_aqc_opc_set_rss_lut);
 471         else
 472                 i40e_fill_default_direct_cmd_desc(&desc,
 473                                                   i40e_aqc_opc_get_rss_lut);
 474
 475         /* Indirect command */
 476         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 478
 479         cmd_resp->vsi_id =
 480                         CPU_TO_LE16((u16)((vsi_id <<
 481                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 483         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 484
 485         if (pf_lut)
 486                 cmd_resp->flags |= CPU_TO_LE16((u16)
 487                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 488                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 490         else
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495
 496         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 497
 498         return status;
 499 }
 500
 501 /**
 502  * i40e_aq_get_rss_lut
 503  * @hw: pointer to the hardware structure
 504  * @vsi_id: vsi fw index
 505  * @pf_lut: for PF table set true, for VSI table set false
 506  * @lut: pointer to the lut buffer provided by the caller
 507  * @lut_size: size of the lut buffer
 508  *
 509  * get the RSS lookup table, PF or VSI type
 510  **/
 511 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 512                                           bool pf_lut, u8 *lut, u16 lut_size)
 513 {
 514         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 515                                        false);
 516 }
 517
 518 /**
 519  * i40e_aq_set_rss_lut
 520  * @hw: pointer to the hardware structure
 521  * @vsi_id: vsi fw index
 522  * @pf_lut: for PF table set true, for VSI table set false
 523  * @lut: pointer to the lut buffer provided by the caller
 524  * @lut_size: size of the lut buffer
 525  *
 526  * set the RSS lookup table, PF or VSI type
 527  **/
 528 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 529                                           bool pf_lut, u8 *lut, u16 lut_size)
 530 {
 531         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 532 }
 533
 534 /**
 535  * i40e_aq_get_set_rss_key
 536  * @hw: pointer to the hw struct
 537  * @vsi_id: vsi fw index
 538  * @key: pointer to key info struct
 539  * @set: set true to set the key, false to get the key
 540  *
 541  * get the RSS key per VSI
 542  **/
 543 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 544                                       u16 vsi_id,
 545                                       struct i40e_aqc_get_set_rss_key_data *key,
 546                                       bool set)
 547 {
 548         enum i40e_status_code status;
 549         struct i40e_aq_desc desc;
 550         struct i40e_aqc_get_set_rss_key *cmd_resp =
 551                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 552         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 553
 554         if (set)
 555                 i40e_fill_default_direct_cmd_desc(&desc,
 556                                                   i40e_aqc_opc_set_rss_key);
 557         else
 558                 i40e_fill_default_direct_cmd_desc(&desc,
 559                                                   i40e_aqc_opc_get_rss_key);
 560
 561         /* Indirect command */
 562         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 564
 565         cmd_resp->vsi_id =
 566                         CPU_TO_LE16((u16)((vsi_id <<
 567                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 569         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 570
 571         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 572
 573         return status;
 574 }
 575
 576 /**
 577  * i40e_aq_get_rss_key
 578  * @hw: pointer to the hw struct
 579  * @vsi_id: vsi fw index
 580  * @key: pointer to key info struct
 581  *
 582  **/
 583 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 584                                       u16 vsi_id,
 585                                       struct i40e_aqc_get_set_rss_key_data *key)
 586 {
 587         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 588 }
 589
 590 /**
 591  * i40e_aq_set_rss_key
 592  * @hw: pointer to the hw struct
 593  * @vsi_id: vsi fw index
 594  * @key: pointer to key info struct
 595  *
 596  * set the RSS key per VSI
 597  **/
 598 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 599                                       u16 vsi_id,
 600                                       struct i40e_aqc_get_set_rss_key_data *key)
 601 {
 602         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 603 }
 604
 605 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 606  * hardware to a bit-field that can be used by SW to more easily determine the
 607  * packet type.
 608  *
 609  * Macros are used to shorten the table lines and make this table human
 610  * readable.
 611  *
 612  * We store the PTYPE in the top byte of the bit field - this is just so that
 613  * we can check that the table doesn't have a row missing, as the index into
 614  * the table should be the PTYPE.
 615  *
 616  * Typical work flow:
 617  *
 618  * IF NOT i40e_ptype_lookup[ptype].known
 619  * THEN
 620  *      Packet is unknown
 621  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 622  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 623  * ELSE
 624  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 625  * ENDIF
 626  */
 627
 628 /* macro to make the table lines short */
 629 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 630         {       PTYPE, \
 631                 1, \
 632                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 633                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 634                 I40E_RX_PTYPE_##OUTER_FRAG, \
 635                 I40E_RX_PTYPE_TUNNEL_##T, \
 636                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 637                 I40E_RX_PTYPE_##TEF, \
 638                 I40E_RX_PTYPE_INNER_PROT_##I, \
 639                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 640
 641 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 642                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 643
 644 /* shorter macros makes the table fit but are terse */
 645 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 646 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 647 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 648
 649 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 650 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 651         /* L2 Packet types */
 652         I40E_PTT_UNUSED_ENTRY(0),
 653         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 655         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT_UNUSED_ENTRY(4),
 657         I40E_PTT_UNUSED_ENTRY(5),
 658         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 659         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT_UNUSED_ENTRY(8),
 661         I40E_PTT_UNUSED_ENTRY(9),
 662         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 663         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 664         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674
 675         /* Non Tunneled IPv4 */
 676         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 679         I40E_PTT_UNUSED_ENTRY(25),
 680         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 681         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 682         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 683
 684         /* IPv4 --> IPv4 */
 685         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 686         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 687         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 688         I40E_PTT_UNUSED_ENTRY(32),
 689         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 690         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 691         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 692
 693         /* IPv4 --> IPv6 */
 694         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 695         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 696         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 697         I40E_PTT_UNUSED_ENTRY(39),
 698         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 699         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 700         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 701
 702         /* IPv4 --> GRE/NAT */
 703         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 704
 705         /* IPv4 --> GRE/NAT --> IPv4 */
 706         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 707         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 708         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 709         I40E_PTT_UNUSED_ENTRY(47),
 710         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 711         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 712         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 713
 714         /* IPv4 --> GRE/NAT --> IPv6 */
 715         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 716         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 717         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 718         I40E_PTT_UNUSED_ENTRY(54),
 719         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 720         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 721         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 722
 723         /* IPv4 --> GRE/NAT --> MAC */
 724         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 725
 726         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 727         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 728         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 729         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 730         I40E_PTT_UNUSED_ENTRY(62),
 731         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 732         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 733         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 734
 735         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 736         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 737         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 738         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 739         I40E_PTT_UNUSED_ENTRY(69),
 740         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 741         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 742         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 743
 744         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 745         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 746
 747         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 748         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 749         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 750         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 751         I40E_PTT_UNUSED_ENTRY(77),
 752         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 753         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 754         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 755
 756         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 757         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 758         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 759         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 760         I40E_PTT_UNUSED_ENTRY(84),
 761         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 762         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 763         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 764
 765         /* Non Tunneled IPv6 */
 766         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 767         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 768         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 769         I40E_PTT_UNUSED_ENTRY(91),
 770         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 771         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 772         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 773
 774         /* IPv6 --> IPv4 */
 775         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 776         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 777         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 778         I40E_PTT_UNUSED_ENTRY(98),
 779         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 780         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 781         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 782
 783         /* IPv6 --> IPv6 */
 784         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 785         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 786         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 787         I40E_PTT_UNUSED_ENTRY(105),
 788         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 789         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 790         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 791
 792         /* IPv6 --> GRE/NAT */
 793         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 794
 795         /* IPv6 --> GRE/NAT -> IPv4 */
 796         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 797         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 798         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 799         I40E_PTT_UNUSED_ENTRY(113),
 800         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 801         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 802         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 803
 804         /* IPv6 --> GRE/NAT -> IPv6 */
 805         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 806         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 807         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 808         I40E_PTT_UNUSED_ENTRY(120),
 809         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 810         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 811         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 812
 813         /* IPv6 --> GRE/NAT -> MAC */
 814         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 815
 816         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 817         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 818         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 819         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 820         I40E_PTT_UNUSED_ENTRY(128),
 821         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 822         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 823         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 824
 825         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 826         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 827         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 828         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 829         I40E_PTT_UNUSED_ENTRY(135),
 830         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 831         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 832         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 833
 834         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 835         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 836
 837         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 838         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 839         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 840         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 841         I40E_PTT_UNUSED_ENTRY(143),
 842         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 843         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 844         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 845
 846         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 847         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 848         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 849         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 850         I40E_PTT_UNUSED_ENTRY(150),
 851         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 852         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 853         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 854
 855         /* unused entries */
 856         I40E_PTT_UNUSED_ENTRY(154),
 857         I40E_PTT_UNUSED_ENTRY(155),
 858         I40E_PTT_UNUSED_ENTRY(156),
 859         I40E_PTT_UNUSED_ENTRY(157),
 860         I40E_PTT_UNUSED_ENTRY(158),
 861         I40E_PTT_UNUSED_ENTRY(159),
 862
 863         I40E_PTT_UNUSED_ENTRY(160),
 864         I40E_PTT_UNUSED_ENTRY(161),
 865         I40E_PTT_UNUSED_ENTRY(162),
 866         I40E_PTT_UNUSED_ENTRY(163),
 867         I40E_PTT_UNUSED_ENTRY(164),
 868         I40E_PTT_UNUSED_ENTRY(165),
 869         I40E_PTT_UNUSED_ENTRY(166),
 870         I40E_PTT_UNUSED_ENTRY(167),
 871         I40E_PTT_UNUSED_ENTRY(168),
 872         I40E_PTT_UNUSED_ENTRY(169),
 873
 874         I40E_PTT_UNUSED_ENTRY(170),
 875         I40E_PTT_UNUSED_ENTRY(171),
 876         I40E_PTT_UNUSED_ENTRY(172),
 877         I40E_PTT_UNUSED_ENTRY(173),
 878         I40E_PTT_UNUSED_ENTRY(174),
 879         I40E_PTT_UNUSED_ENTRY(175),
 880         I40E_PTT_UNUSED_ENTRY(176),
 881         I40E_PTT_UNUSED_ENTRY(177),
 882         I40E_PTT_UNUSED_ENTRY(178),
 883         I40E_PTT_UNUSED_ENTRY(179),
 884
 885         I40E_PTT_UNUSED_ENTRY(180),
 886         I40E_PTT_UNUSED_ENTRY(181),
 887         I40E_PTT_UNUSED_ENTRY(182),
 888         I40E_PTT_UNUSED_ENTRY(183),
 889         I40E_PTT_UNUSED_ENTRY(184),
 890         I40E_PTT_UNUSED_ENTRY(185),
 891         I40E_PTT_UNUSED_ENTRY(186),
 892         I40E_PTT_UNUSED_ENTRY(187),
 893         I40E_PTT_UNUSED_ENTRY(188),
 894         I40E_PTT_UNUSED_ENTRY(189),
 895
 896         I40E_PTT_UNUSED_ENTRY(190),
 897         I40E_PTT_UNUSED_ENTRY(191),
 898         I40E_PTT_UNUSED_ENTRY(192),
 899         I40E_PTT_UNUSED_ENTRY(193),
 900         I40E_PTT_UNUSED_ENTRY(194),
 901         I40E_PTT_UNUSED_ENTRY(195),
 902         I40E_PTT_UNUSED_ENTRY(196),
 903         I40E_PTT_UNUSED_ENTRY(197),
 904         I40E_PTT_UNUSED_ENTRY(198),
 905         I40E_PTT_UNUSED_ENTRY(199),
 906
 907         I40E_PTT_UNUSED_ENTRY(200),
 908         I40E_PTT_UNUSED_ENTRY(201),
 909         I40E_PTT_UNUSED_ENTRY(202),
 910         I40E_PTT_UNUSED_ENTRY(203),
 911         I40E_PTT_UNUSED_ENTRY(204),
 912         I40E_PTT_UNUSED_ENTRY(205),
 913         I40E_PTT_UNUSED_ENTRY(206),
 914         I40E_PTT_UNUSED_ENTRY(207),
 915         I40E_PTT_UNUSED_ENTRY(208),
 916         I40E_PTT_UNUSED_ENTRY(209),
 917
 918         I40E_PTT_UNUSED_ENTRY(210),
 919         I40E_PTT_UNUSED_ENTRY(211),
 920         I40E_PTT_UNUSED_ENTRY(212),
 921         I40E_PTT_UNUSED_ENTRY(213),
 922         I40E_PTT_UNUSED_ENTRY(214),
 923         I40E_PTT_UNUSED_ENTRY(215),
 924         I40E_PTT_UNUSED_ENTRY(216),
 925         I40E_PTT_UNUSED_ENTRY(217),
 926         I40E_PTT_UNUSED_ENTRY(218),
 927         I40E_PTT_UNUSED_ENTRY(219),
 928
 929         I40E_PTT_UNUSED_ENTRY(220),
 930         I40E_PTT_UNUSED_ENTRY(221),
 931         I40E_PTT_UNUSED_ENTRY(222),
 932         I40E_PTT_UNUSED_ENTRY(223),
 933         I40E_PTT_UNUSED_ENTRY(224),
 934         I40E_PTT_UNUSED_ENTRY(225),
 935         I40E_PTT_UNUSED_ENTRY(226),
 936         I40E_PTT_UNUSED_ENTRY(227),
 937         I40E_PTT_UNUSED_ENTRY(228),
 938         I40E_PTT_UNUSED_ENTRY(229),
 939
 940         I40E_PTT_UNUSED_ENTRY(230),
 941         I40E_PTT_UNUSED_ENTRY(231),
 942         I40E_PTT_UNUSED_ENTRY(232),
 943         I40E_PTT_UNUSED_ENTRY(233),
 944         I40E_PTT_UNUSED_ENTRY(234),
 945         I40E_PTT_UNUSED_ENTRY(235),
 946         I40E_PTT_UNUSED_ENTRY(236),
 947         I40E_PTT_UNUSED_ENTRY(237),
 948         I40E_PTT_UNUSED_ENTRY(238),
 949         I40E_PTT_UNUSED_ENTRY(239),
 950
 951         I40E_PTT_UNUSED_ENTRY(240),
 952         I40E_PTT_UNUSED_ENTRY(241),
 953         I40E_PTT_UNUSED_ENTRY(242),
 954         I40E_PTT_UNUSED_ENTRY(243),
 955         I40E_PTT_UNUSED_ENTRY(244),
 956         I40E_PTT_UNUSED_ENTRY(245),
 957         I40E_PTT_UNUSED_ENTRY(246),
 958         I40E_PTT_UNUSED_ENTRY(247),
 959         I40E_PTT_UNUSED_ENTRY(248),
 960         I40E_PTT_UNUSED_ENTRY(249),
 961
 962         I40E_PTT_UNUSED_ENTRY(250),
 963         I40E_PTT_UNUSED_ENTRY(251),
 964         I40E_PTT_UNUSED_ENTRY(252),
 965         I40E_PTT_UNUSED_ENTRY(253),
 966         I40E_PTT_UNUSED_ENTRY(254),
 967         I40E_PTT_UNUSED_ENTRY(255)
 968 };
 969
 970
 971 /**
 972  * i40e_validate_mac_addr - Validate unicast MAC address
 973  * @mac_addr: pointer to MAC address
 974  *
 975  * Tests a MAC address to ensure it is a valid Individual Address
 976  **/
 977 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 978 {
 979         enum i40e_status_code status = I40E_SUCCESS;
 980
 981         DEBUGFUNC("i40e_validate_mac_addr");
 982
 983         /* Broadcast addresses ARE multicast addresses
 984          * Make sure it is not a multicast address
 985          * Reject the zero address
 986          */
 987         if (I40E_IS_MULTICAST(mac_addr) ||
 988             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 989               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 990                 status = I40E_ERR_INVALID_MAC_ADDR;
 991
 992         return status;
 993 }
 994 #ifdef PF_DRIVER
 995
 996 /**
 997  * i40e_init_shared_code - Initialize the shared code
 998  * @hw: pointer to hardware structure
 999  *
1000  * This assigns the MAC type and PHY code and inits the NVM.
1001  * Does not touch the hardware. This function must be called prior to any
1002  * other function in the shared code. The i40e_hw structure should be
1003  * memset to 0 prior to calling this function.  The following fields in
1004  * hw structure should be filled in prior to calling this function:
1005  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1006  * subsystem_vendor_id, and revision_id
1007  **/
1008 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1009 {
1010         enum i40e_status_code status = I40E_SUCCESS;
1011         u32 port, ari, func_rid;
1012
1013         DEBUGFUNC("i40e_init_shared_code");
1014
1015         i40e_set_mac_type(hw);
1016
1017         switch (hw->mac.type) {
1018         case I40E_MAC_XL710:
1019         case I40E_MAC_X722:
1020                 break;
1021         default:
1022                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1023         }
1024
1025         hw->phy.get_link_info = true;
1026
1027         /* Determine port number and PF number*/
1028         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1029                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1030         hw->port = (u8)port;
1031         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1032                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1033         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1034         if (ari)
1035                 hw->pf_id = (u8)(func_rid & 0xff);
1036         else
1037                 hw->pf_id = (u8)(func_rid & 0x7);
1038
1039         if (hw->mac.type == I40E_MAC_X722)
1040                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1041
1042         status = i40e_init_nvm(hw);
1043         return status;
1044 }
1045
1046 /**
1047  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1048  * @hw: pointer to the hw struct
1049  * @flags: a return indicator of what addresses were added to the addr store
1050  * @addrs: the requestor's mac addr store
1051  * @cmd_details: pointer to command details structure or NULL
1052  **/
1053 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1054                                    u16 *flags,
1055                                    struct i40e_aqc_mac_address_read_data *addrs,
1056                                    struct i40e_asq_cmd_details *cmd_details)
1057 {
1058         struct i40e_aq_desc desc;
1059         struct i40e_aqc_mac_address_read *cmd_data =
1060                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1061         enum i40e_status_code status;
1062
1063         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1064         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1065
1066         status = i40e_asq_send_command(hw, &desc, addrs,
1067                                        sizeof(*addrs), cmd_details);
1068         *flags = LE16_TO_CPU(cmd_data->command_flags);
1069
1070         return status;
1071 }
1072
1073 /**
1074  * i40e_aq_mac_address_write - Change the MAC addresses
1075  * @hw: pointer to the hw struct
1076  * @flags: indicates which MAC to be written
1077  * @mac_addr: address to write
1078  * @cmd_details: pointer to command details structure or NULL
1079  **/
1080 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1081                                     u16 flags, u8 *mac_addr,
1082                                     struct i40e_asq_cmd_details *cmd_details)
1083 {
1084         struct i40e_aq_desc desc;
1085         struct i40e_aqc_mac_address_write *cmd_data =
1086                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1087         enum i40e_status_code status;
1088
1089         i40e_fill_default_direct_cmd_desc(&desc,
1090                                           i40e_aqc_opc_mac_address_write);
1091         cmd_data->command_flags = CPU_TO_LE16(flags);
1092         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1093         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1094                                         ((u32)mac_addr[3] << 16) |
1095                                         ((u32)mac_addr[4] << 8) |
1096                                         mac_addr[5]);
1097
1098         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1099
1100         return status;
1101 }
1102
1103 /**
1104  * i40e_get_mac_addr - get MAC address
1105  * @hw: pointer to the HW structure
1106  * @mac_addr: pointer to MAC address
1107  *
1108  * Reads the adapter's MAC address from register
1109  **/
1110 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1111 {
1112         struct i40e_aqc_mac_address_read_data addrs;
1113         enum i40e_status_code status;
1114         u16 flags = 0;
1115
1116         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1117
1118         if (flags & I40E_AQC_LAN_ADDR_VALID)
1119                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1120                         I40E_NONDMA_TO_NONDMA);
1121
1122         return status;
1123 }
1124
1125 /**
1126  * i40e_get_port_mac_addr - get Port MAC address
1127  * @hw: pointer to the HW structure
1128  * @mac_addr: pointer to Port MAC address
1129  *
1130  * Reads the adapter's Port MAC address
1131  **/
1132 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1133 {
1134         struct i40e_aqc_mac_address_read_data addrs;
1135         enum i40e_status_code status;
1136         u16 flags = 0;
1137
1138         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1139         if (status)
1140                 return status;
1141
1142         if (flags & I40E_AQC_PORT_ADDR_VALID)
1143                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1144                         I40E_NONDMA_TO_NONDMA);
1145         else
1146                 status = I40E_ERR_INVALID_MAC_ADDR;
1147
1148         return status;
1149 }
1150
1151 /**
1152  * i40e_pre_tx_queue_cfg - pre tx queue configure
1153  * @hw: pointer to the HW structure
1154  * @queue: target pf queue index
1155  * @enable: state change request
1156  *
1157  * Handles hw requirement to indicate intention to enable
1158  * or disable target queue.
1159  **/
1160 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1161 {
1162         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1163         u32 reg_block = 0;
1164         u32 reg_val;
1165
1166         if (abs_queue_idx >= 128) {
1167                 reg_block = abs_queue_idx / 128;
1168                 abs_queue_idx %= 128;
1169         }
1170
1171         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1172         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1173         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1174
1175         if (enable)
1176                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1177         else
1178                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1179
1180         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1181 }
1182
1183 /**
1184  * i40e_get_san_mac_addr - get SAN MAC address
1185  * @hw: pointer to the HW structure
1186  * @mac_addr: pointer to SAN MAC address
1187  *
1188  * Reads the adapter's SAN MAC address from NVM
1189  **/
1190 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1191                                             u8 *mac_addr)
1192 {
1193         struct i40e_aqc_mac_address_read_data addrs;
1194         enum i40e_status_code status;
1195         u16 flags = 0;
1196
1197         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1198         if (status)
1199                 return status;
1200
1201         if (flags & I40E_AQC_SAN_ADDR_VALID)
1202                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1203                         I40E_NONDMA_TO_NONDMA);
1204         else
1205                 status = I40E_ERR_INVALID_MAC_ADDR;
1206
1207         return status;
1208 }
1209
1210 /**
1211  *  i40e_read_pba_string - Reads part number string from EEPROM
1212  *  @hw: pointer to hardware structure
1213  *  @pba_num: stores the part number string from the EEPROM
1214  *  @pba_num_size: part number string buffer length
1215  *
1216  *  Reads the part number string from the EEPROM.
1217  **/
1218 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1219                                             u32 pba_num_size)
1220 {
1221         enum i40e_status_code status = I40E_SUCCESS;
1222         u16 pba_word = 0;
1223         u16 pba_size = 0;
1224         u16 pba_ptr = 0;
1225         u16 i = 0;
1226
1227         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1228         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1229                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1230                 return status;
1231         }
1232
1233         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1234         if (status != I40E_SUCCESS) {
1235                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1236                 return status;
1237         }
1238
1239         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1240         if (status != I40E_SUCCESS) {
1241                 DEBUGOUT("Failed to read PBA Block size.\n");
1242                 return status;
1243         }
1244
1245         /* Subtract one to get PBA word count (PBA Size word is included in
1246          * total size)
1247          */
1248         pba_size--;
1249         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1250                 DEBUGOUT("Buffer to small for PBA data.\n");
1251                 return I40E_ERR_PARAM;
1252         }
1253
1254         for (i = 0; i < pba_size; i++) {
1255                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1256                 if (status != I40E_SUCCESS) {
1257                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1258                         return status;
1259                 }
1260
1261                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1262                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1263         }
1264         pba_num[(pba_size * 2)] = '\0';
1265
1266         return status;
1267 }
1268
1269 /**
1270  * i40e_get_media_type - Gets media type
1271  * @hw: pointer to the hardware structure
1272  **/
1273 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1274 {
1275         enum i40e_media_type media;
1276
1277         switch (hw->phy.link_info.phy_type) {
1278         case I40E_PHY_TYPE_10GBASE_SR:
1279         case I40E_PHY_TYPE_10GBASE_LR:
1280         case I40E_PHY_TYPE_1000BASE_SX:
1281         case I40E_PHY_TYPE_1000BASE_LX:
1282         case I40E_PHY_TYPE_40GBASE_SR4:
1283         case I40E_PHY_TYPE_40GBASE_LR4:
1284         case I40E_PHY_TYPE_25GBASE_LR:
1285         case I40E_PHY_TYPE_25GBASE_SR:
1286                 media = I40E_MEDIA_TYPE_FIBER;
1287                 break;
1288         case I40E_PHY_TYPE_100BASE_TX:
1289         case I40E_PHY_TYPE_1000BASE_T:
1290         case I40E_PHY_TYPE_10GBASE_T:
1291                 media = I40E_MEDIA_TYPE_BASET;
1292                 break;
1293         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1294         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1295         case I40E_PHY_TYPE_10GBASE_CR1:
1296         case I40E_PHY_TYPE_40GBASE_CR4:
1297         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1298         case I40E_PHY_TYPE_40GBASE_AOC:
1299         case I40E_PHY_TYPE_10GBASE_AOC:
1300         case I40E_PHY_TYPE_25GBASE_CR:
1301         case I40E_PHY_TYPE_25GBASE_AOC:
1302         case I40E_PHY_TYPE_25GBASE_ACC:
1303                 media = I40E_MEDIA_TYPE_DA;
1304                 break;
1305         case I40E_PHY_TYPE_1000BASE_KX:
1306         case I40E_PHY_TYPE_10GBASE_KX4:
1307         case I40E_PHY_TYPE_10GBASE_KR:
1308         case I40E_PHY_TYPE_40GBASE_KR4:
1309         case I40E_PHY_TYPE_20GBASE_KR2:
1310         case I40E_PHY_TYPE_25GBASE_KR:
1311                 media = I40E_MEDIA_TYPE_BACKPLANE;
1312                 break;
1313         case I40E_PHY_TYPE_SGMII:
1314         case I40E_PHY_TYPE_XAUI:
1315         case I40E_PHY_TYPE_XFI:
1316         case I40E_PHY_TYPE_XLAUI:
1317         case I40E_PHY_TYPE_XLPPI:
1318         default:
1319                 media = I40E_MEDIA_TYPE_UNKNOWN;
1320                 break;
1321         }
1322
1323         return media;
1324 }
1325
1326 #define I40E_PF_RESET_WAIT_COUNT        200
1327 /**
1328  * i40e_pf_reset - Reset the PF
1329  * @hw: pointer to the hardware structure
1330  *
1331  * Assuming someone else has triggered a global reset,
1332  * assure the global reset is complete and then reset the PF
1333  **/
1334 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1335 {
1336         u32 cnt = 0;
1337         u32 cnt1 = 0;
1338         u32 reg = 0;
1339         u32 grst_del;
1340
1341         /* Poll for Global Reset steady state in case of recent GRST.
1342          * The grst delay value is in 100ms units, and we'll wait a
1343          * couple counts longer to be sure we don't just miss the end.
1344          */
1345         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1346                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1347                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1348
1349         grst_del = grst_del * 20;
1350
1351         for (cnt = 0; cnt < grst_del; cnt++) {
1352                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1353                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1354                         break;
1355                 i40e_msec_delay(100);
1356         }
1357         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1358                 DEBUGOUT("Global reset polling failed to complete.\n");
1359                 return I40E_ERR_RESET_FAILED;
1360         }
1361
1362         /* Now Wait for the FW to be ready */
1363         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1364                 reg = rd32(hw, I40E_GLNVM_ULD);
1365                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1366                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1367                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1368                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1369                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1370                         break;
1371                 }
1372                 i40e_msec_delay(10);
1373         }
1374         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1375                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1376                 DEBUGOUT("wait for FW Reset complete timedout\n");
1377                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1378                 return I40E_ERR_RESET_FAILED;
1379         }
1380
1381         /* If there was a Global Reset in progress when we got here,
1382          * we don't need to do the PF Reset
1383          */
1384         if (!cnt) {
1385                 u32 reg2 = 0;
1386
1387                 reg = rd32(hw, I40E_PFGEN_CTRL);
1388                 wr32(hw, I40E_PFGEN_CTRL,
1389                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1390                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1391                         reg = rd32(hw, I40E_PFGEN_CTRL);
1392                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1393                                 break;
1394                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1395                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1396                                 DEBUGOUT("Core reset upcoming.\n");
1397                                 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1398                                 return I40E_ERR_NOT_READY;
1399                         }
1400                         i40e_msec_delay(1);
1401                 }
1402                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1403                         DEBUGOUT("PF reset polling failed to complete.\n");
1404                         return I40E_ERR_RESET_FAILED;
1405                 }
1406         }
1407
1408         i40e_clear_pxe_mode(hw);
1409
1410
1411         return I40E_SUCCESS;
1412 }
1413
1414 /**
1415  * i40e_clear_hw - clear out any left over hw state
1416  * @hw: pointer to the hw struct
1417  *
1418  * Clear queues and interrupts, typically called at init time,
1419  * but after the capabilities have been found so we know how many
1420  * queues and msix vectors have been allocated.
1421  **/
1422 void i40e_clear_hw(struct i40e_hw *hw)
1423 {
1424         u32 num_queues, base_queue;
1425         u32 num_pf_int;
1426         u32 num_vf_int;
1427         u32 num_vfs;
1428         u32 i, j;
1429         u32 val;
1430         u32 eol = 0x7ff;
1431
1432         /* get number of interrupts, queues, and vfs */
1433         val = rd32(hw, I40E_GLPCI_CNF2);
1434         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1435                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1436         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1437                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1438
1439         val = rd32(hw, I40E_PFLAN_QALLOC);
1440         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1441                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1442         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1443                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1444         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1445                 num_queues = (j - base_queue) + 1;
1446         else
1447                 num_queues = 0;
1448
1449         val = rd32(hw, I40E_PF_VT_PFALLOC);
1450         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1451                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1452         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1453                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1454         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1455                 num_vfs = (j - i) + 1;
1456         else
1457                 num_vfs = 0;
1458
1459         /* stop all the interrupts */
1460         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1461         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1462         for (i = 0; i < num_pf_int - 2; i++)
1463                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1464
1465         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1466         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1467         wr32(hw, I40E_PFINT_LNKLST0, val);
1468         for (i = 0; i < num_pf_int - 2; i++)
1469                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1470         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1471         for (i = 0; i < num_vfs; i++)
1472                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1473         for (i = 0; i < num_vf_int - 2; i++)
1474                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1475
1476         /* warn the HW of the coming Tx disables */
1477         for (i = 0; i < num_queues; i++) {
1478                 u32 abs_queue_idx = base_queue + i;
1479                 u32 reg_block = 0;
1480
1481                 if (abs_queue_idx >= 128) {
1482                         reg_block = abs_queue_idx / 128;
1483                         abs_queue_idx %= 128;
1484                 }
1485
1486                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1487                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1488                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1489                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1490
1491                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1492         }
1493         i40e_usec_delay(400);
1494
1495         /* stop all the queues */
1496         for (i = 0; i < num_queues; i++) {
1497                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1498                 wr32(hw, I40E_QTX_ENA(i), 0);
1499                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1500                 wr32(hw, I40E_QRX_ENA(i), 0);
1501         }
1502
1503         /* short wait for all queue disables to settle */
1504         i40e_usec_delay(50);
1505 }
1506
1507 /**
1508  * i40e_clear_pxe_mode - clear pxe operations mode
1509  * @hw: pointer to the hw struct
1510  *
1511  * Make sure all PXE mode settings are cleared, including things
1512  * like descriptor fetch/write-back mode.
1513  **/
1514 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1515 {
1516         if (i40e_check_asq_alive(hw))
1517                 i40e_aq_clear_pxe_mode(hw, NULL);
1518 }
1519
1520 /**
1521  * i40e_led_is_mine - helper to find matching led
1522  * @hw: pointer to the hw struct
1523  * @idx: index into GPIO registers
1524  *
1525  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1526  */
1527 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1528 {
1529         u32 gpio_val = 0;
1530         u32 port;
1531
1532         if (!hw->func_caps.led[idx])
1533                 return 0;
1534
1535         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1536         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1537                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1538
1539         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1540          * if it is not our port then ignore
1541          */
1542         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1543             (port != hw->port))
1544                 return 0;
1545
1546         return gpio_val;
1547 }
1548
1549 #define I40E_COMBINED_ACTIVITY 0xA
1550 #define I40E_FILTER_ACTIVITY 0xE
1551 #define I40E_LINK_ACTIVITY 0xC
1552 #define I40E_MAC_ACTIVITY 0xD
1553 #define I40E_LED0 22
1554
1555 /**
1556  * i40e_led_get - return current on/off mode
1557  * @hw: pointer to the hw struct
1558  *
1559  * The value returned is the 'mode' field as defined in the
1560  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1561  * values are variations of possible behaviors relating to
1562  * blink, link, and wire.
1563  **/
1564 u32 i40e_led_get(struct i40e_hw *hw)
1565 {
1566         u32 current_mode = 0;
1567         u32 mode = 0;
1568         int i;
1569
1570         /* as per the documentation GPIO 22-29 are the LED
1571          * GPIO pins named LED0..LED7
1572          */
1573         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1574                 u32 gpio_val = i40e_led_is_mine(hw, i);
1575
1576                 if (!gpio_val)
1577                         continue;
1578
1579                 /* ignore gpio LED src mode entries related to the activity
1580                  *  LEDs
1581                  */
1582                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1583                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1584                 switch (current_mode) {
1585                 case I40E_COMBINED_ACTIVITY:
1586                 case I40E_FILTER_ACTIVITY:
1587                 case I40E_MAC_ACTIVITY:
1588                         continue;
1589                 default:
1590                         break;
1591                 }
1592
1593                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1594                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1595                 break;
1596         }
1597
1598         return mode;
1599 }
1600
1601 /**
1602  * i40e_led_set - set new on/off mode
1603  * @hw: pointer to the hw struct
1604  * @mode: 0=off, 0xf=on (else see manual for mode details)
1605  * @blink: true if the LED should blink when on, false if steady
1606  *
1607  * if this function is used to turn on the blink it should
1608  * be used to disable the blink when restoring the original state.
1609  **/
1610 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1611 {
1612         u32 current_mode = 0;
1613         int i;
1614
1615         if (mode & 0xfffffff0)
1616                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1617
1618         /* as per the documentation GPIO 22-29 are the LED
1619          * GPIO pins named LED0..LED7
1620          */
1621         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1622                 u32 gpio_val = i40e_led_is_mine(hw, i);
1623
1624                 if (!gpio_val)
1625                         continue;
1626
1627                 /* ignore gpio LED src mode entries related to the activity
1628                  * LEDs
1629                  */
1630                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1631                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1632                 switch (current_mode) {
1633                 case I40E_COMBINED_ACTIVITY:
1634                 case I40E_FILTER_ACTIVITY:
1635                 case I40E_MAC_ACTIVITY:
1636                         continue;
1637                 default:
1638                         break;
1639                 }
1640
1641                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1642                 /* this & is a bit of paranoia, but serves as a range check */
1643                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1644                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1645
1646                 if (mode == I40E_LINK_ACTIVITY)
1647                         blink = false;
1648
1649                 if (blink)
1650                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1651                 else
1652                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1653
1654                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1655                 break;
1656         }
1657 }
1658
1659 /* Admin command wrappers */
1660
1661 /**
1662  * i40e_aq_get_phy_capabilities
1663  * @hw: pointer to the hw struct
1664  * @abilities: structure for PHY capabilities to be filled
1665  * @qualified_modules: report Qualified Modules
1666  * @report_init: report init capabilities (active are default)
1667  * @cmd_details: pointer to command details structure or NULL
1668  *
1669  * Returns the various PHY abilities supported on the Port.
1670  **/
1671 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1672                         bool qualified_modules, bool report_init,
1673                         struct i40e_aq_get_phy_abilities_resp *abilities,
1674                         struct i40e_asq_cmd_details *cmd_details)
1675 {
1676         struct i40e_aq_desc desc;
1677         enum i40e_status_code status;
1678         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1679         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1680
1681         if (!abilities)
1682                 return I40E_ERR_PARAM;
1683
1684         do {
1685                 i40e_fill_default_direct_cmd_desc(&desc,
1686                                                i40e_aqc_opc_get_phy_abilities);
1687
1688                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1689                 if (abilities_size > I40E_AQ_LARGE_BUF)
1690                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1691
1692                 if (qualified_modules)
1693                         desc.params.external.param0 |=
1694                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1695
1696                 if (report_init)
1697                         desc.params.external.param0 |=
1698                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1699
1700                 status = i40e_asq_send_command(hw, &desc, abilities,
1701                                                abilities_size, cmd_details);
1702
1703                 if (status != I40E_SUCCESS)
1704                         break;
1705
1706                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1707                         status = I40E_ERR_UNKNOWN_PHY;
1708                         break;
1709                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1710                         i40e_msec_delay(1);
1711                         total_delay++;
1712                         status = I40E_ERR_TIMEOUT;
1713                 }
1714         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1715                  (total_delay < max_delay));
1716
1717         if (status != I40E_SUCCESS)
1718                 return status;
1719
1720         if (report_init) {
1721                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1722                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1723                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1724                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1725                 } else {
1726                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1727                         hw->phy.phy_types |=
1728                                         ((u64)abilities->phy_type_ext << 32);
1729                 }
1730         }
1731
1732         return status;
1733 }
1734
1735 /**
1736  * i40e_aq_set_phy_config
1737  * @hw: pointer to the hw struct
1738  * @config: structure with PHY configuration to be set
1739  * @cmd_details: pointer to command details structure or NULL
1740  *
1741  * Set the various PHY configuration parameters
1742  * supported on the Port.One or more of the Set PHY config parameters may be
1743  * ignored in an MFP mode as the PF may not have the privilege to set some
1744  * of the PHY Config parameters. This status will be indicated by the
1745  * command response.
1746  **/
1747 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1748                                 struct i40e_aq_set_phy_config *config,
1749                                 struct i40e_asq_cmd_details *cmd_details)
1750 {
1751         struct i40e_aq_desc desc;
1752         struct i40e_aq_set_phy_config *cmd =
1753                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1754         enum i40e_status_code status;
1755
1756         if (!config)
1757                 return I40E_ERR_PARAM;
1758
1759         i40e_fill_default_direct_cmd_desc(&desc,
1760                                           i40e_aqc_opc_set_phy_config);
1761
1762         *cmd = *config;
1763
1764         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1765
1766         return status;
1767 }
1768
1769 /**
1770  * i40e_set_fc
1771  * @hw: pointer to the hw struct
1772  *
1773  * Set the requested flow control mode using set_phy_config.
1774  **/
1775 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1776                                   bool atomic_restart)
1777 {
1778         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1779         struct i40e_aq_get_phy_abilities_resp abilities;
1780         struct i40e_aq_set_phy_config config;
1781         enum i40e_status_code status;
1782         u8 pause_mask = 0x0;
1783
1784         *aq_failures = 0x0;
1785
1786         switch (fc_mode) {
1787         case I40E_FC_FULL:
1788                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1789                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1790                 break;
1791         case I40E_FC_RX_PAUSE:
1792                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1793                 break;
1794         case I40E_FC_TX_PAUSE:
1795                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1796                 break;
1797         default:
1798                 break;
1799         }
1800
1801         /* Get the current phy config */
1802         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1803                                               NULL);
1804         if (status) {
1805                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1806                 return status;
1807         }
1808
1809         memset(&config, 0, sizeof(config));
1810         /* clear the old pause settings */
1811         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1812                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1813         /* set the new abilities */
1814         config.abilities |= pause_mask;
1815         /* If the abilities have changed, then set the new config */
1816         if (config.abilities != abilities.abilities) {
1817                 /* Auto restart link so settings take effect */
1818                 if (atomic_restart)
1819                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1820                 /* Copy over all the old settings */
1821                 config.phy_type = abilities.phy_type;
1822                 config.phy_type_ext = abilities.phy_type_ext;
1823                 config.link_speed = abilities.link_speed;
1824                 config.eee_capability = abilities.eee_capability;
1825                 config.eeer = abilities.eeer_val;
1826                 config.low_power_ctrl = abilities.d3_lpan;
1827                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1828                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1829                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1830
1831                 if (status)
1832                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1833         }
1834         /* Update the link info */
1835         status = i40e_update_link_info(hw);
1836         if (status) {
1837                 /* Wait a little bit (on 40G cards it sometimes takes a really
1838                  * long time for link to come back from the atomic reset)
1839                  * and try once more
1840                  */
1841                 i40e_msec_delay(1000);
1842                 status = i40e_update_link_info(hw);
1843         }
1844         if (status)
1845                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1846
1847         return status;
1848 }
1849
1850 /**
1851  * i40e_aq_set_mac_config
1852  * @hw: pointer to the hw struct
1853  * @max_frame_size: Maximum Frame Size to be supported by the port
1854  * @crc_en: Tell HW to append a CRC to outgoing frames
1855  * @pacing: Pacing configurations
1856  * @cmd_details: pointer to command details structure or NULL
1857  *
1858  * Configure MAC settings for frame size, jumbo frame support and the
1859  * addition of a CRC by the hardware.
1860  **/
1861 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1862                                 u16 max_frame_size,
1863                                 bool crc_en, u16 pacing,
1864                                 struct i40e_asq_cmd_details *cmd_details)
1865 {
1866         struct i40e_aq_desc desc;
1867         struct i40e_aq_set_mac_config *cmd =
1868                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1869         enum i40e_status_code status;
1870
1871         if (max_frame_size == 0)
1872                 return I40E_ERR_PARAM;
1873
1874         i40e_fill_default_direct_cmd_desc(&desc,
1875                                           i40e_aqc_opc_set_mac_config);
1876
1877         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1878         cmd->params = ((u8)pacing & 0x0F) << 3;
1879         if (crc_en)
1880                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1881
1882         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1883
1884         return status;
1885 }
1886
1887 /**
1888  * i40e_aq_clear_pxe_mode
1889  * @hw: pointer to the hw struct
1890  * @cmd_details: pointer to command details structure or NULL
1891  *
1892  * Tell the firmware that the driver is taking over from PXE
1893  **/
1894 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1895                         struct i40e_asq_cmd_details *cmd_details)
1896 {
1897         enum i40e_status_code status;
1898         struct i40e_aq_desc desc;
1899         struct i40e_aqc_clear_pxe *cmd =
1900                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1901
1902         i40e_fill_default_direct_cmd_desc(&desc,
1903                                           i40e_aqc_opc_clear_pxe_mode);
1904
1905         cmd->rx_cnt = 0x2;
1906
1907         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1908
1909         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1910
1911         return status;
1912 }
1913
1914 /**
1915  * i40e_aq_set_link_restart_an
1916  * @hw: pointer to the hw struct
1917  * @enable_link: if true: enable link, if false: disable link
1918  * @cmd_details: pointer to command details structure or NULL
1919  *
1920  * Sets up the link and restarts the Auto-Negotiation over the link.
1921  **/
1922 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1923                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1924 {
1925         struct i40e_aq_desc desc;
1926         struct i40e_aqc_set_link_restart_an *cmd =
1927                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1928         enum i40e_status_code status;
1929
1930         i40e_fill_default_direct_cmd_desc(&desc,
1931                                           i40e_aqc_opc_set_link_restart_an);
1932
1933         cmd->command = I40E_AQ_PHY_RESTART_AN;
1934         if (enable_link)
1935                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1936         else
1937                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1938
1939         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1940
1941         return status;
1942 }
1943
1944 /**
1945  * i40e_aq_get_link_info
1946  * @hw: pointer to the hw struct
1947  * @enable_lse: enable/disable LinkStatusEvent reporting
1948  * @link: pointer to link status structure - optional
1949  * @cmd_details: pointer to command details structure or NULL
1950  *
1951  * Returns the link status of the adapter.
1952  **/
1953 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1954                                 bool enable_lse, struct i40e_link_status *link,
1955                                 struct i40e_asq_cmd_details *cmd_details)
1956 {
1957         struct i40e_aq_desc desc;
1958         struct i40e_aqc_get_link_status *resp =
1959                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1960         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1961         enum i40e_status_code status;
1962         bool tx_pause, rx_pause;
1963         u16 command_flags;
1964
1965         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1966
1967         if (enable_lse)
1968                 command_flags = I40E_AQ_LSE_ENABLE;
1969         else
1970                 command_flags = I40E_AQ_LSE_DISABLE;
1971         resp->command_flags = CPU_TO_LE16(command_flags);
1972
1973         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1974
1975         if (status != I40E_SUCCESS)
1976                 goto aq_get_link_info_exit;
1977
1978         /* save off old link status information */
1979         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1980                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1981
1982         /* update link status */
1983         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1984         hw->phy.media_type = i40e_get_media_type(hw);
1985         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1986         hw_link_info->link_info = resp->link_info;
1987         hw_link_info->an_info = resp->an_info;
1988         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1989                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1990         hw_link_info->ext_info = resp->ext_info;
1991         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1992         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1993         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1994
1995         /* update fc info */
1996         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1997         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1998         if (tx_pause & rx_pause)
1999                 hw->fc.current_mode = I40E_FC_FULL;
2000         else if (tx_pause)
2001                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2002         else if (rx_pause)
2003                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2004         else
2005                 hw->fc.current_mode = I40E_FC_NONE;
2006
2007         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2008                 hw_link_info->crc_enable = true;
2009         else
2010                 hw_link_info->crc_enable = false;
2011
2012         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2013                 hw_link_info->lse_enable = true;
2014         else
2015                 hw_link_info->lse_enable = false;
2016
2017         if ((hw->mac.type == I40E_MAC_XL710) &&
2018             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2019              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2020                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2021
2022         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2023             hw->aq.api_min_ver >= 7) {
2024                 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type);
2025                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2026         }
2027
2028         /* save link status information */
2029         if (link)
2030                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2031                             I40E_NONDMA_TO_NONDMA);
2032
2033         /* flag cleared so helper functions don't call AQ again */
2034         hw->phy.get_link_info = false;
2035
2036 aq_get_link_info_exit:
2037         return status;
2038 }
2039
2040 /**
2041  * i40e_aq_set_phy_int_mask
2042  * @hw: pointer to the hw struct
2043  * @mask: interrupt mask to be set
2044  * @cmd_details: pointer to command details structure or NULL
2045  *
2046  * Set link interrupt mask.
2047  **/
2048 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2049                                 u16 mask,
2050                                 struct i40e_asq_cmd_details *cmd_details)
2051 {
2052         struct i40e_aq_desc desc;
2053         struct i40e_aqc_set_phy_int_mask *cmd =
2054                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2055         enum i40e_status_code status;
2056
2057         i40e_fill_default_direct_cmd_desc(&desc,
2058                                           i40e_aqc_opc_set_phy_int_mask);
2059
2060         cmd->event_mask = CPU_TO_LE16(mask);
2061
2062         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2063
2064         return status;
2065 }
2066
2067 /**
2068  * i40e_aq_get_local_advt_reg
2069  * @hw: pointer to the hw struct
2070  * @advt_reg: local AN advertisement register value
2071  * @cmd_details: pointer to command details structure or NULL
2072  *
2073  * Get the Local AN advertisement register value.
2074  **/
2075 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2076                                 u64 *advt_reg,
2077                                 struct i40e_asq_cmd_details *cmd_details)
2078 {
2079         struct i40e_aq_desc desc;
2080         struct i40e_aqc_an_advt_reg *resp =
2081                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2082         enum i40e_status_code status;
2083
2084         i40e_fill_default_direct_cmd_desc(&desc,
2085                                           i40e_aqc_opc_get_local_advt_reg);
2086
2087         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2088
2089         if (status != I40E_SUCCESS)
2090                 goto aq_get_local_advt_reg_exit;
2091
2092         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2093         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2094
2095 aq_get_local_advt_reg_exit:
2096         return status;
2097 }
2098
2099 /**
2100  * i40e_aq_set_local_advt_reg
2101  * @hw: pointer to the hw struct
2102  * @advt_reg: local AN advertisement register value
2103  * @cmd_details: pointer to command details structure or NULL
2104  *
2105  * Get the Local AN advertisement register value.
2106  **/
2107 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2108                                 u64 advt_reg,
2109                                 struct i40e_asq_cmd_details *cmd_details)
2110 {
2111         struct i40e_aq_desc desc;
2112         struct i40e_aqc_an_advt_reg *cmd =
2113                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2114         enum i40e_status_code status;
2115
2116         i40e_fill_default_direct_cmd_desc(&desc,
2117                                           i40e_aqc_opc_get_local_advt_reg);
2118
2119         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2120         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2121
2122         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2123
2124         return status;
2125 }
2126
2127 /**
2128  * i40e_aq_get_partner_advt
2129  * @hw: pointer to the hw struct
2130  * @advt_reg: AN partner advertisement register value
2131  * @cmd_details: pointer to command details structure or NULL
2132  *
2133  * Get the link partner AN advertisement register value.
2134  **/
2135 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2136                                 u64 *advt_reg,
2137                                 struct i40e_asq_cmd_details *cmd_details)
2138 {
2139         struct i40e_aq_desc desc;
2140         struct i40e_aqc_an_advt_reg *resp =
2141                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2142         enum i40e_status_code status;
2143
2144         i40e_fill_default_direct_cmd_desc(&desc,
2145                                           i40e_aqc_opc_get_partner_advt);
2146
2147         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2148
2149         if (status != I40E_SUCCESS)
2150                 goto aq_get_partner_advt_exit;
2151
2152         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2153         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2154
2155 aq_get_partner_advt_exit:
2156         return status;
2157 }
2158
2159 /**
2160  * i40e_aq_set_lb_modes
2161  * @hw: pointer to the hw struct
2162  * @lb_modes: loopback mode to be set
2163  * @cmd_details: pointer to command details structure or NULL
2164  *
2165  * Sets loopback modes.
2166  **/
2167 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2168                                 u16 lb_modes,
2169                                 struct i40e_asq_cmd_details *cmd_details)
2170 {
2171         struct i40e_aq_desc desc;
2172         struct i40e_aqc_set_lb_mode *cmd =
2173                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2174         enum i40e_status_code status;
2175
2176         i40e_fill_default_direct_cmd_desc(&desc,
2177                                           i40e_aqc_opc_set_lb_modes);
2178
2179         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2180
2181         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2182
2183         return status;
2184 }
2185
2186 /**
2187  * i40e_aq_set_phy_debug
2188  * @hw: pointer to the hw struct
2189  * @cmd_flags: debug command flags
2190  * @cmd_details: pointer to command details structure or NULL
2191  *
2192  * Reset the external PHY.
2193  **/
2194 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2195                                 struct i40e_asq_cmd_details *cmd_details)
2196 {
2197         struct i40e_aq_desc desc;
2198         struct i40e_aqc_set_phy_debug *cmd =
2199                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2200         enum i40e_status_code status;
2201
2202         i40e_fill_default_direct_cmd_desc(&desc,
2203                                           i40e_aqc_opc_set_phy_debug);
2204
2205         cmd->command_flags = cmd_flags;
2206
2207         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2208
2209         return status;
2210 }
2211
2212 /**
2213  * i40e_aq_add_vsi
2214  * @hw: pointer to the hw struct
2215  * @vsi_ctx: pointer to a vsi context struct
2216  * @cmd_details: pointer to command details structure or NULL
2217  *
2218  * Add a VSI context to the hardware.
2219 **/
2220 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2221                                 struct i40e_vsi_context *vsi_ctx,
2222                                 struct i40e_asq_cmd_details *cmd_details)
2223 {
2224         struct i40e_aq_desc desc;
2225         struct i40e_aqc_add_get_update_vsi *cmd =
2226                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2227         struct i40e_aqc_add_get_update_vsi_completion *resp =
2228                 (struct i40e_aqc_add_get_update_vsi_completion *)
2229                 &desc.params.raw;
2230         enum i40e_status_code status;
2231
2232         i40e_fill_default_direct_cmd_desc(&desc,
2233                                           i40e_aqc_opc_add_vsi);
2234
2235         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2236         cmd->connection_type = vsi_ctx->connection_type;
2237         cmd->vf_id = vsi_ctx->vf_num;
2238         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2239
2240         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2241
2242         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2243                                     sizeof(vsi_ctx->info), cmd_details);
2244
2245         if (status != I40E_SUCCESS)
2246                 goto aq_add_vsi_exit;
2247
2248         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2249         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2250         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2251         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2252
2253 aq_add_vsi_exit:
2254         return status;
2255 }
2256
2257 /**
2258  * i40e_aq_set_default_vsi
2259  * @hw: pointer to the hw struct
2260  * @seid: vsi number
2261  * @cmd_details: pointer to command details structure or NULL
2262  **/
2263 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2264                                 u16 seid,
2265                                 struct i40e_asq_cmd_details *cmd_details)
2266 {
2267         struct i40e_aq_desc desc;
2268         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2269                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2270                 &desc.params.raw;
2271         enum i40e_status_code status;
2272
2273         i40e_fill_default_direct_cmd_desc(&desc,
2274                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2275
2276         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2277         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2278         cmd->seid = CPU_TO_LE16(seid);
2279
2280         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2281
2282         return status;
2283 }
2284
2285 /**
2286  * i40e_aq_clear_default_vsi
2287  * @hw: pointer to the hw struct
2288  * @seid: vsi number
2289  * @cmd_details: pointer to command details structure or NULL
2290  **/
2291 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2292                                 u16 seid,
2293                                 struct i40e_asq_cmd_details *cmd_details)
2294 {
2295         struct i40e_aq_desc desc;
2296         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2297                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2298                 &desc.params.raw;
2299         enum i40e_status_code status;
2300
2301         i40e_fill_default_direct_cmd_desc(&desc,
2302                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2303
2304         cmd->promiscuous_flags = CPU_TO_LE16(0);
2305         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2306         cmd->seid = CPU_TO_LE16(seid);
2307
2308         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2309
2310         return status;
2311 }
2312
2313 /**
2314  * i40e_aq_set_vsi_unicast_promiscuous
2315  * @hw: pointer to the hw struct
2316  * @seid: vsi number
2317  * @set: set unicast promiscuous enable/disable
2318  * @cmd_details: pointer to command details structure or NULL
2319  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2320  **/
2321 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2322                                 u16 seid, bool set,
2323                                 struct i40e_asq_cmd_details *cmd_details,
2324                                 bool rx_only_promisc)
2325 {
2326         struct i40e_aq_desc desc;
2327         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2328                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2329         enum i40e_status_code status;
2330         u16 flags = 0;
2331
2332         i40e_fill_default_direct_cmd_desc(&desc,
2333                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2334
2335         if (set) {
2336                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2337                 if (rx_only_promisc &&
2338                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2339                      (hw->aq.api_maj_ver > 1)))
2340                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2341         }
2342
2343         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2344
2345         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2346         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2347              (hw->aq.api_maj_ver > 1))
2348                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2349
2350         cmd->seid = CPU_TO_LE16(seid);
2351         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2352
2353         return status;
2354 }
2355
2356 /**
2357  * i40e_aq_set_vsi_multicast_promiscuous
2358  * @hw: pointer to the hw struct
2359  * @seid: vsi number
2360  * @set: set multicast promiscuous enable/disable
2361  * @cmd_details: pointer to command details structure or NULL
2362  **/
2363 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2364                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2365 {
2366         struct i40e_aq_desc desc;
2367         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2368                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2369         enum i40e_status_code status;
2370         u16 flags = 0;
2371
2372         i40e_fill_default_direct_cmd_desc(&desc,
2373                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2374
2375         if (set)
2376                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2377
2378         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2379
2380         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2381
2382         cmd->seid = CPU_TO_LE16(seid);
2383         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2384
2385         return status;
2386 }
2387
2388 /**
2389 * i40e_aq_set_vsi_full_promiscuous
2390 * @hw: pointer to the hw struct
2391 * @seid: VSI number
2392 * @set: set promiscuous enable/disable
2393 * @cmd_details: pointer to command details structure or NULL
2394 **/
2395 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2396                                 u16 seid, bool set,
2397                                 struct i40e_asq_cmd_details *cmd_details)
2398 {
2399         struct i40e_aq_desc desc;
2400         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2401                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2402         enum i40e_status_code status;
2403         u16 flags = 0;
2404
2405         i40e_fill_default_direct_cmd_desc(&desc,
2406                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2407
2408         if (set)
2409                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2410                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2411                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2412
2413         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2414
2415         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2416                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2417                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2418
2419         cmd->seid = CPU_TO_LE16(seid);
2420         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2421
2422         return status;
2423 }
2424
2425 /**
2426  * i40e_aq_set_vsi_mc_promisc_on_vlan
2427  * @hw: pointer to the hw struct
2428  * @seid: vsi number
2429  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2430  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2431  * @cmd_details: pointer to command details structure or NULL
2432  **/
2433 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2434                                 u16 seid, bool enable, u16 vid,
2435                                 struct i40e_asq_cmd_details *cmd_details)
2436 {
2437         struct i40e_aq_desc desc;
2438         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2439                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2440         enum i40e_status_code status;
2441         u16 flags = 0;
2442
2443         i40e_fill_default_direct_cmd_desc(&desc,
2444                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2445
2446         if (enable)
2447                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2448
2449         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2450         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2451         cmd->seid = CPU_TO_LE16(seid);
2452         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2453
2454         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2455
2456         return status;
2457 }
2458
2459 /**
2460  * i40e_aq_set_vsi_uc_promisc_on_vlan
2461  * @hw: pointer to the hw struct
2462  * @seid: vsi number
2463  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2464  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2465  * @cmd_details: pointer to command details structure or NULL
2466  **/
2467 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2468                                 u16 seid, bool enable, u16 vid,
2469                                 struct i40e_asq_cmd_details *cmd_details)
2470 {
2471         struct i40e_aq_desc desc;
2472         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2473                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2474         enum i40e_status_code status;
2475         u16 flags = 0;
2476
2477         i40e_fill_default_direct_cmd_desc(&desc,
2478                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2479
2480         if (enable)
2481                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2482
2483         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2484         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2485         cmd->seid = CPU_TO_LE16(seid);
2486         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2487
2488         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2489
2490         return status;
2491 }
2492
2493 /**
2494  * i40e_aq_set_vsi_bc_promisc_on_vlan
2495  * @hw: pointer to the hw struct
2496  * @seid: vsi number
2497  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2498  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2499  * @cmd_details: pointer to command details structure or NULL
2500  **/
2501 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2502                                 u16 seid, bool enable, u16 vid,
2503                                 struct i40e_asq_cmd_details *cmd_details)
2504 {
2505         struct i40e_aq_desc desc;
2506         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2507                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2508         enum i40e_status_code status;
2509         u16 flags = 0;
2510
2511         i40e_fill_default_direct_cmd_desc(&desc,
2512                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2513
2514         if (enable)
2515                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2516
2517         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2518         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2519         cmd->seid = CPU_TO_LE16(seid);
2520         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2521
2522         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2523
2524         return status;
2525 }
2526
2527 /**
2528  * i40e_aq_set_vsi_broadcast
2529  * @hw: pointer to the hw struct
2530  * @seid: vsi number
2531  * @set_filter: true to set filter, false to clear filter
2532  * @cmd_details: pointer to command details structure or NULL
2533  *
2534  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2535  **/
2536 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2537                                 u16 seid, bool set_filter,
2538                                 struct i40e_asq_cmd_details *cmd_details)
2539 {
2540         struct i40e_aq_desc desc;
2541         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2542                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2543         enum i40e_status_code status;
2544
2545         i40e_fill_default_direct_cmd_desc(&desc,
2546                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2547
2548         if (set_filter)
2549                 cmd->promiscuous_flags
2550                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2551         else
2552                 cmd->promiscuous_flags
2553                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2554
2555         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2556         cmd->seid = CPU_TO_LE16(seid);
2557         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2558
2559         return status;
2560 }
2561
2562 /**
2563  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2564  * @hw: pointer to the hw struct
2565  * @seid: vsi number
2566  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2567  * @cmd_details: pointer to command details structure or NULL
2568  **/
2569 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2570                                 u16 seid, bool enable,
2571                                 struct i40e_asq_cmd_details *cmd_details)
2572 {
2573         struct i40e_aq_desc desc;
2574         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2575                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2576         enum i40e_status_code status;
2577         u16 flags = 0;
2578
2579         i40e_fill_default_direct_cmd_desc(&desc,
2580                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2581         if (enable)
2582                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2583
2584         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2585         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2586         cmd->seid = CPU_TO_LE16(seid);
2587
2588         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2589
2590         return status;
2591 }
2592
2593 /**
2594  * i40e_get_vsi_params - get VSI configuration info
2595  * @hw: pointer to the hw struct
2596  * @vsi_ctx: pointer to a vsi context struct
2597  * @cmd_details: pointer to command details structure or NULL
2598  **/
2599 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2600                                 struct i40e_vsi_context *vsi_ctx,
2601                                 struct i40e_asq_cmd_details *cmd_details)
2602 {
2603         struct i40e_aq_desc desc;
2604         struct i40e_aqc_add_get_update_vsi *cmd =
2605                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2606         struct i40e_aqc_add_get_update_vsi_completion *resp =
2607                 (struct i40e_aqc_add_get_update_vsi_completion *)
2608                 &desc.params.raw;
2609         enum i40e_status_code status;
2610
2611         UNREFERENCED_1PARAMETER(cmd_details);
2612         i40e_fill_default_direct_cmd_desc(&desc,
2613                                           i40e_aqc_opc_get_vsi_parameters);
2614
2615         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2616
2617         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2618
2619         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2620                                     sizeof(vsi_ctx->info), NULL);
2621
2622         if (status != I40E_SUCCESS)
2623                 goto aq_get_vsi_params_exit;
2624
2625         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2626         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2627         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2628         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2629
2630 aq_get_vsi_params_exit:
2631         return status;
2632 }
2633
2634 /**
2635  * i40e_aq_update_vsi_params
2636  * @hw: pointer to the hw struct
2637  * @vsi_ctx: pointer to a vsi context struct
2638  * @cmd_details: pointer to command details structure or NULL
2639  *
2640  * Update a VSI context.
2641  **/
2642 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2643                                 struct i40e_vsi_context *vsi_ctx,
2644                                 struct i40e_asq_cmd_details *cmd_details)
2645 {
2646         struct i40e_aq_desc desc;
2647         struct i40e_aqc_add_get_update_vsi *cmd =
2648                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2649         struct i40e_aqc_add_get_update_vsi_completion *resp =
2650                 (struct i40e_aqc_add_get_update_vsi_completion *)
2651                 &desc.params.raw;
2652         enum i40e_status_code status;
2653
2654         i40e_fill_default_direct_cmd_desc(&desc,
2655                                           i40e_aqc_opc_update_vsi_parameters);
2656         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2657
2658         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2659
2660         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2661                                     sizeof(vsi_ctx->info), cmd_details);
2662
2663         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2664         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2665
2666         return status;
2667 }
2668
2669 /**
2670  * i40e_aq_get_switch_config
2671  * @hw: pointer to the hardware structure
2672  * @buf: pointer to the result buffer
2673  * @buf_size: length of input buffer
2674  * @start_seid: seid to start for the report, 0 == beginning
2675  * @cmd_details: pointer to command details structure or NULL
2676  *
2677  * Fill the buf with switch configuration returned from AdminQ command
2678  **/
2679 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2680                                 struct i40e_aqc_get_switch_config_resp *buf,
2681                                 u16 buf_size, u16 *start_seid,
2682                                 struct i40e_asq_cmd_details *cmd_details)
2683 {
2684         struct i40e_aq_desc desc;
2685         struct i40e_aqc_switch_seid *scfg =
2686                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2687         enum i40e_status_code status;
2688
2689         i40e_fill_default_direct_cmd_desc(&desc,
2690                                           i40e_aqc_opc_get_switch_config);
2691         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2692         if (buf_size > I40E_AQ_LARGE_BUF)
2693                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2694         scfg->seid = CPU_TO_LE16(*start_seid);
2695
2696         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2697         *start_seid = LE16_TO_CPU(scfg->seid);
2698
2699         return status;
2700 }
2701
2702 /**
2703  * i40e_aq_set_switch_config
2704  * @hw: pointer to the hardware structure
2705  * @flags: bit flag values to set
2706  * @valid_flags: which bit flags to set
2707  * @cmd_details: pointer to command details structure or NULL
2708  *
2709  * Set switch configuration bits
2710  **/
2711 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2712                                 u16 flags, u16 valid_flags,
2713                                 struct i40e_asq_cmd_details *cmd_details)
2714 {
2715         struct i40e_aq_desc desc;
2716         struct i40e_aqc_set_switch_config *scfg =
2717                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2718         enum i40e_status_code status;
2719
2720         i40e_fill_default_direct_cmd_desc(&desc,
2721                                           i40e_aqc_opc_set_switch_config);
2722         scfg->flags = CPU_TO_LE16(flags);
2723         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2724         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2725                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2726                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2727                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2728         }
2729         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2730
2731         return status;
2732 }
2733
2734 /**
2735  * i40e_aq_get_firmware_version
2736  * @hw: pointer to the hw struct
2737  * @fw_major_version: firmware major version
2738  * @fw_minor_version: firmware minor version
2739  * @fw_build: firmware build number
2740  * @api_major_version: major queue version
2741  * @api_minor_version: minor queue version
2742  * @cmd_details: pointer to command details structure or NULL
2743  *
2744  * Get the firmware version from the admin queue commands
2745  **/
2746 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2747                                 u16 *fw_major_version, u16 *fw_minor_version,
2748                                 u32 *fw_build,
2749                                 u16 *api_major_version, u16 *api_minor_version,
2750                                 struct i40e_asq_cmd_details *cmd_details)
2751 {
2752         struct i40e_aq_desc desc;
2753         struct i40e_aqc_get_version *resp =
2754                 (struct i40e_aqc_get_version *)&desc.params.raw;
2755         enum i40e_status_code status;
2756
2757         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2758
2759         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2760
2761         if (status == I40E_SUCCESS) {
2762                 if (fw_major_version != NULL)
2763                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2764                 if (fw_minor_version != NULL)
2765                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2766                 if (fw_build != NULL)
2767                         *fw_build = LE32_TO_CPU(resp->fw_build);
2768                 if (api_major_version != NULL)
2769                         *api_major_version = LE16_TO_CPU(resp->api_major);
2770                 if (api_minor_version != NULL)
2771                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2772
2773                 /* A workaround to fix the API version in SW */
2774                 if (api_major_version && api_minor_version &&
2775                     fw_major_version && fw_minor_version &&
2776                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2777                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2778                      (*fw_major_version > 4)))
2779                         *api_minor_version = 2;
2780         }
2781
2782         return status;
2783 }
2784
2785 /**
2786  * i40e_aq_send_driver_version
2787  * @hw: pointer to the hw struct
2788  * @dv: driver's major, minor version
2789  * @cmd_details: pointer to command details structure or NULL
2790  *
2791  * Send the driver version to the firmware
2792  **/
2793 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2794                                 struct i40e_driver_version *dv,
2795                                 struct i40e_asq_cmd_details *cmd_details)
2796 {
2797         struct i40e_aq_desc desc;
2798         struct i40e_aqc_driver_version *cmd =
2799                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2800         enum i40e_status_code status;
2801         u16 len;
2802
2803         if (dv == NULL)
2804                 return I40E_ERR_PARAM;
2805
2806         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2807
2808         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2809         cmd->driver_major_ver = dv->major_version;
2810         cmd->driver_minor_ver = dv->minor_version;
2811         cmd->driver_build_ver = dv->build_version;
2812         cmd->driver_subbuild_ver = dv->subbuild_version;
2813
2814         len = 0;
2815         while (len < sizeof(dv->driver_string) &&
2816                (dv->driver_string[len] < 0x80) &&
2817                dv->driver_string[len])
2818                 len++;
2819         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2820                                        len, cmd_details);
2821
2822         return status;
2823 }
2824
2825 /**
2826  * i40e_get_link_status - get status of the HW network link
2827  * @hw: pointer to the hw struct
2828  * @link_up: pointer to bool (true/false = linkup/linkdown)
2829  *
2830  * Variable link_up true if link is up, false if link is down.
2831  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2832  *
2833  * Side effect: LinkStatusEvent reporting becomes enabled
2834  **/
2835 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2836 {
2837         enum i40e_status_code status = I40E_SUCCESS;
2838
2839         if (hw->phy.get_link_info) {
2840                 status = i40e_update_link_info(hw);
2841
2842                 if (status != I40E_SUCCESS)
2843                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2844                                    status);
2845         }
2846
2847         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2848
2849         return status;
2850 }
2851
2852 /**
2853  * i40e_updatelink_status - update status of the HW network link
2854  * @hw: pointer to the hw struct
2855  **/
2856 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2857 {
2858         struct i40e_aq_get_phy_abilities_resp abilities;
2859         enum i40e_status_code status = I40E_SUCCESS;
2860
2861         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2862         if (status)
2863                 return status;
2864
2865         /* extra checking needed to ensure link info to user is timely */
2866         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2867             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2868              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2869                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2870                                                       &abilities, NULL);
2871                 if (status)
2872                         return status;
2873
2874                 hw->phy.link_info.req_fec_info =
2875                         abilities.fec_cfg_curr_mod_ext_info &
2876                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2877
2878                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2879                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2880         }
2881         return status;
2882 }
2883
2884
2885 /**
2886  * i40e_get_link_speed
2887  * @hw: pointer to the hw struct
2888  *
2889  * Returns the link speed of the adapter.
2890  **/
2891 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2892 {
2893         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2894         enum i40e_status_code status = I40E_SUCCESS;
2895
2896         if (hw->phy.get_link_info) {
2897                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2898
2899                 if (status != I40E_SUCCESS)
2900                         goto i40e_link_speed_exit;
2901         }
2902
2903         speed = hw->phy.link_info.link_speed;
2904
2905 i40e_link_speed_exit:
2906         return speed;
2907 }
2908
2909 /**
2910  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2911  * @hw: pointer to the hw struct
2912  * @uplink_seid: the MAC or other gizmo SEID
2913  * @downlink_seid: the VSI SEID
2914  * @enabled_tc: bitmap of TCs to be enabled
2915  * @default_port: true for default port VSI, false for control port
2916  * @veb_seid: pointer to where to put the resulting VEB SEID
2917  * @enable_stats: true to turn on VEB stats
2918  * @cmd_details: pointer to command details structure or NULL
2919  *
2920  * This asks the FW to add a VEB between the uplink and downlink
2921  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2922  **/
2923 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2924                                 u16 downlink_seid, u8 enabled_tc,
2925                                 bool default_port, u16 *veb_seid,
2926                                 bool enable_stats,
2927                                 struct i40e_asq_cmd_details *cmd_details)
2928 {
2929         struct i40e_aq_desc desc;
2930         struct i40e_aqc_add_veb *cmd =
2931                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2932         struct i40e_aqc_add_veb_completion *resp =
2933                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2934         enum i40e_status_code status;
2935         u16 veb_flags = 0;
2936
2937         /* SEIDs need to either both be set or both be 0 for floating VEB */
2938         if (!!uplink_seid != !!downlink_seid)
2939                 return I40E_ERR_PARAM;
2940
2941         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2942
2943         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2944         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2945         cmd->enable_tcs = enabled_tc;
2946         if (!uplink_seid)
2947                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2948         if (default_port)
2949                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2950         else
2951                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2952
2953         /* reverse logic here: set the bitflag to disable the stats */
2954         if (!enable_stats)
2955                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2956
2957         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2958
2959         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2960
2961         if (!status && veb_seid)
2962                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2963
2964         return status;
2965 }
2966
2967 /**
2968  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2969  * @hw: pointer to the hw struct
2970  * @veb_seid: the SEID of the VEB to query
2971  * @switch_id: the uplink switch id
2972  * @floating: set to true if the VEB is floating
2973  * @statistic_index: index of the stats counter block for this VEB
2974  * @vebs_used: number of VEB's used by function
2975  * @vebs_free: total VEB's not reserved by any function
2976  * @cmd_details: pointer to command details structure or NULL
2977  *
2978  * This retrieves the parameters for a particular VEB, specified by
2979  * uplink_seid, and returns them to the caller.
2980  **/
2981 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2982                                 u16 veb_seid, u16 *switch_id,
2983                                 bool *floating, u16 *statistic_index,
2984                                 u16 *vebs_used, u16 *vebs_free,
2985                                 struct i40e_asq_cmd_details *cmd_details)
2986 {
2987         struct i40e_aq_desc desc;
2988         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2989                 (struct i40e_aqc_get_veb_parameters_completion *)
2990                 &desc.params.raw;
2991         enum i40e_status_code status;
2992
2993         if (veb_seid == 0)
2994                 return I40E_ERR_PARAM;
2995
2996         i40e_fill_default_direct_cmd_desc(&desc,
2997                                           i40e_aqc_opc_get_veb_parameters);
2998         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2999
3000         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3001         if (status)
3002                 goto get_veb_exit;
3003
3004         if (switch_id)
3005                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3006         if (statistic_index)
3007                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3008         if (vebs_used)
3009                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3010         if (vebs_free)
3011                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3012         if (floating) {
3013                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3014
3015                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3016                         *floating = true;
3017                 else
3018                         *floating = false;
3019         }
3020
3021 get_veb_exit:
3022         return status;
3023 }
3024
3025 /**
3026  * i40e_aq_add_macvlan
3027  * @hw: pointer to the hw struct
3028  * @seid: VSI for the mac address
3029  * @mv_list: list of macvlans to be added
3030  * @count: length of the list
3031  * @cmd_details: pointer to command details structure or NULL
3032  *
3033  * Add MAC/VLAN addresses to the HW filtering
3034  **/
3035 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3036                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3037                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3038 {
3039         struct i40e_aq_desc desc;
3040         struct i40e_aqc_macvlan *cmd =
3041                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3042         enum i40e_status_code status;
3043         u16 buf_size;
3044         int i;
3045
3046         if (count == 0 || !mv_list || !hw)
3047                 return I40E_ERR_PARAM;
3048
3049         buf_size = count * sizeof(*mv_list);
3050
3051         /* prep the rest of the request */
3052         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3053         cmd->num_addresses = CPU_TO_LE16(count);
3054         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3055         cmd->seid[1] = 0;
3056         cmd->seid[2] = 0;
3057
3058         for (i = 0; i < count; i++)
3059                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3060                         mv_list[i].flags |=
3061                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3062
3063         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3064         if (buf_size > I40E_AQ_LARGE_BUF)
3065                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3066
3067         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3068                                        cmd_details);
3069
3070         return status;
3071 }
3072
3073 /**
3074  * i40e_aq_remove_macvlan
3075  * @hw: pointer to the hw struct
3076  * @seid: VSI for the mac address
3077  * @mv_list: list of macvlans to be removed
3078  * @count: length of the list
3079  * @cmd_details: pointer to command details structure or NULL
3080  *
3081  * Remove MAC/VLAN addresses from the HW filtering
3082  **/
3083 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3084                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3085                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3086 {
3087         struct i40e_aq_desc desc;
3088         struct i40e_aqc_macvlan *cmd =
3089                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3090         enum i40e_status_code status;
3091         u16 buf_size;
3092
3093         if (count == 0 || !mv_list || !hw)
3094                 return I40E_ERR_PARAM;
3095
3096         buf_size = count * sizeof(*mv_list);
3097
3098         /* prep the rest of the request */
3099         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3100         cmd->num_addresses = CPU_TO_LE16(count);
3101         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3102         cmd->seid[1] = 0;
3103         cmd->seid[2] = 0;
3104
3105         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3106         if (buf_size > I40E_AQ_LARGE_BUF)
3107                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3108
3109         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3110                                        cmd_details);
3111
3112         return status;
3113 }
3114
3115 /**
3116  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3117  * @hw: pointer to the hw struct
3118  * @opcode: AQ opcode for add or delete mirror rule
3119  * @sw_seid: Switch SEID (to which rule refers)
3120  * @rule_type: Rule Type (ingress/egress/VLAN)
3121  * @id: Destination VSI SEID or Rule ID
3122  * @count: length of the list
3123  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3124  * @cmd_details: pointer to command details structure or NULL
3125  * @rule_id: Rule ID returned from FW
3126  * @rule_used: Number of rules used in internal switch
3127  * @rule_free: Number of rules free in internal switch
3128  *
3129  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3130  * VEBs/VEPA elements only
3131  **/
3132 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3133                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3134                         u16 count, __le16 *mr_list,
3135                         struct i40e_asq_cmd_details *cmd_details,
3136                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3137 {
3138         struct i40e_aq_desc desc;
3139         struct i40e_aqc_add_delete_mirror_rule *cmd =
3140                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3141         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3142         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3143         enum i40e_status_code status;
3144         u16 buf_size;
3145
3146         buf_size = count * sizeof(*mr_list);
3147
3148         /* prep the rest of the request */
3149         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3150         cmd->seid = CPU_TO_LE16(sw_seid);
3151         cmd->rule_type = CPU_TO_LE16(rule_type &
3152                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3153         cmd->num_entries = CPU_TO_LE16(count);
3154         /* Dest VSI for add, rule_id for delete */
3155         cmd->destination = CPU_TO_LE16(id);
3156         if (mr_list) {
3157                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3158                                                 I40E_AQ_FLAG_RD));
3159                 if (buf_size > I40E_AQ_LARGE_BUF)
3160                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3161         }
3162
3163         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3164                                        cmd_details);
3165         if (status == I40E_SUCCESS ||
3166             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3167                 if (rule_id)
3168                         *rule_id = LE16_TO_CPU(resp->rule_id);
3169                 if (rules_used)
3170                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3171                 if (rules_free)
3172                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3173         }
3174         return status;
3175 }
3176
3177 /**
3178  * i40e_aq_add_mirrorrule - add a mirror rule
3179  * @hw: pointer to the hw struct
3180  * @sw_seid: Switch SEID (to which rule refers)
3181  * @rule_type: Rule Type (ingress/egress/VLAN)
3182  * @dest_vsi: SEID of VSI to which packets will be mirrored
3183  * @count: length of the list
3184  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3185  * @cmd_details: pointer to command details structure or NULL
3186  * @rule_id: Rule ID returned from FW
3187  * @rule_used: Number of rules used in internal switch
3188  * @rule_free: Number of rules free in internal switch
3189  *
3190  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3191  **/
3192 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3193                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3194                         struct i40e_asq_cmd_details *cmd_details,
3195                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3196 {
3197         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3198             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3199                 if (count == 0 || !mr_list)
3200                         return I40E_ERR_PARAM;
3201         }
3202
3203         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3204                                   rule_type, dest_vsi, count, mr_list,
3205                                   cmd_details, rule_id, rules_used, rules_free);
3206 }
3207
3208 /**
3209  * i40e_aq_delete_mirrorrule - delete a mirror rule
3210  * @hw: pointer to the hw struct
3211  * @sw_seid: Switch SEID (to which rule refers)
3212  * @rule_type: Rule Type (ingress/egress/VLAN)
3213  * @count: length of the list
3214  * @rule_id: Rule ID that is returned in the receive desc as part of
3215  *              add_mirrorrule.
3216  * @mr_list: list of mirrored VLAN IDs to be removed
3217  * @cmd_details: pointer to command details structure or NULL
3218  * @rule_used: Number of rules used in internal switch
3219  * @rule_free: Number of rules free in internal switch
3220  *
3221  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3222  **/
3223 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3224                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3225                         struct i40e_asq_cmd_details *cmd_details,
3226                         u16 *rules_used, u16 *rules_free)
3227 {
3228         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3229         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3230                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3231                  * mirroring. For other rule_type, count and rule_type should
3232                  * not matter.
3233                  */
3234                 if (count == 0 || !mr_list)
3235                         return I40E_ERR_PARAM;
3236         }
3237
3238         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3239                                   rule_type, rule_id, count, mr_list,
3240                                   cmd_details, NULL, rules_used, rules_free);
3241 }
3242
3243 /**
3244  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3245  * @hw: pointer to the hw struct
3246  * @seid: VSI for the vlan filters
3247  * @v_list: list of vlan filters to be added
3248  * @count: length of the list
3249  * @cmd_details: pointer to command details structure or NULL
3250  **/
3251 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3252                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3253                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3254 {
3255         struct i40e_aq_desc desc;
3256         struct i40e_aqc_macvlan *cmd =
3257                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3258         enum i40e_status_code status;
3259         u16 buf_size;
3260
3261         if (count == 0 || !v_list || !hw)
3262                 return I40E_ERR_PARAM;
3263
3264         buf_size = count * sizeof(*v_list);
3265
3266         /* prep the rest of the request */
3267         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3268         cmd->num_addresses = CPU_TO_LE16(count);
3269         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3270         cmd->seid[1] = 0;
3271         cmd->seid[2] = 0;
3272
3273         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3274         if (buf_size > I40E_AQ_LARGE_BUF)
3275                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3276
3277         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3278                                        cmd_details);
3279
3280         return status;
3281 }
3282
3283 /**
3284  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3285  * @hw: pointer to the hw struct
3286  * @seid: VSI for the vlan filters
3287  * @v_list: list of macvlans to be removed
3288  * @count: length of the list
3289  * @cmd_details: pointer to command details structure or NULL
3290  **/
3291 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3292                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3293                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3294 {
3295         struct i40e_aq_desc desc;
3296         struct i40e_aqc_macvlan *cmd =
3297                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3298         enum i40e_status_code status;
3299         u16 buf_size;
3300
3301         if (count == 0 || !v_list || !hw)
3302                 return I40E_ERR_PARAM;
3303
3304         buf_size = count * sizeof(*v_list);
3305
3306         /* prep the rest of the request */
3307         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3308         cmd->num_addresses = CPU_TO_LE16(count);
3309         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3310         cmd->seid[1] = 0;
3311         cmd->seid[2] = 0;
3312
3313         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3314         if (buf_size > I40E_AQ_LARGE_BUF)
3315                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3316
3317         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3318                                        cmd_details);
3319
3320         return status;
3321 }
3322
3323 /**
3324  * i40e_aq_send_msg_to_vf
3325  * @hw: pointer to the hardware structure
3326  * @vfid: vf id to send msg
3327  * @v_opcode: opcodes for VF-PF communication
3328  * @v_retval: return error code
3329  * @msg: pointer to the msg buffer
3330  * @msglen: msg length
3331  * @cmd_details: pointer to command details
3332  *
3333  * send msg to vf
3334  **/
3335 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3336                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3337                                 struct i40e_asq_cmd_details *cmd_details)
3338 {
3339         struct i40e_aq_desc desc;
3340         struct i40e_aqc_pf_vf_message *cmd =
3341                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3342         enum i40e_status_code status;
3343
3344         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3345         cmd->id = CPU_TO_LE32(vfid);
3346         desc.cookie_high = CPU_TO_LE32(v_opcode);
3347         desc.cookie_low = CPU_TO_LE32(v_retval);
3348         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3349         if (msglen) {
3350                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3351                                                 I40E_AQ_FLAG_RD));
3352                 if (msglen > I40E_AQ_LARGE_BUF)
3353                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3354                 desc.datalen = CPU_TO_LE16(msglen);
3355         }
3356         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3357
3358         return status;
3359 }
3360
3361 /**
3362  * i40e_aq_debug_read_register
3363  * @hw: pointer to the hw struct
3364  * @reg_addr: register address
3365  * @reg_val: register value
3366  * @cmd_details: pointer to command details structure or NULL
3367  *
3368  * Read the register using the admin queue commands
3369  **/
3370 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3371                                 u32 reg_addr, u64 *reg_val,
3372                                 struct i40e_asq_cmd_details *cmd_details)
3373 {
3374         struct i40e_aq_desc desc;
3375         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3376                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3377         enum i40e_status_code status;
3378
3379         if (reg_val == NULL)
3380                 return I40E_ERR_PARAM;
3381
3382         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3383
3384         cmd_resp->address = CPU_TO_LE32(reg_addr);
3385
3386         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3387
3388         if (status == I40E_SUCCESS) {
3389                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3390                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3391         }
3392
3393         return status;
3394 }
3395
3396 /**
3397  * i40e_aq_debug_write_register
3398  * @hw: pointer to the hw struct
3399  * @reg_addr: register address
3400  * @reg_val: register value
3401  * @cmd_details: pointer to command details structure or NULL
3402  *
3403  * Write to a register using the admin queue commands
3404  **/
3405 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3406                                 u32 reg_addr, u64 reg_val,
3407                                 struct i40e_asq_cmd_details *cmd_details)
3408 {
3409         struct i40e_aq_desc desc;
3410         struct i40e_aqc_debug_reg_read_write *cmd =
3411                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3412         enum i40e_status_code status;
3413
3414         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3415
3416         cmd->address = CPU_TO_LE32(reg_addr);
3417         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3418         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3419
3420         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3421
3422         return status;
3423 }
3424
3425 /**
3426  * i40e_aq_request_resource
3427  * @hw: pointer to the hw struct
3428  * @resource: resource id
3429  * @access: access type
3430  * @sdp_number: resource number
3431  * @timeout: the maximum time in ms that the driver may hold the resource
3432  * @cmd_details: pointer to command details structure or NULL
3433  *
3434  * requests common resource using the admin queue commands
3435  **/
3436 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3437                                 enum i40e_aq_resources_ids resource,
3438                                 enum i40e_aq_resource_access_type access,
3439                                 u8 sdp_number, u64 *timeout,
3440                                 struct i40e_asq_cmd_details *cmd_details)
3441 {
3442         struct i40e_aq_desc desc;
3443         struct i40e_aqc_request_resource *cmd_resp =
3444                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3445         enum i40e_status_code status;
3446
3447         DEBUGFUNC("i40e_aq_request_resource");
3448
3449         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3450
3451         cmd_resp->resource_id = CPU_TO_LE16(resource);
3452         cmd_resp->access_type = CPU_TO_LE16(access);
3453         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3454
3455         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3456         /* The completion specifies the maximum time in ms that the driver
3457          * may hold the resource in the Timeout field.
3458          * If the resource is held by someone else, the command completes with
3459          * busy return value and the timeout field indicates the maximum time
3460          * the current owner of the resource has to free it.
3461          */
3462         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3463                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3464
3465         return status;
3466 }
3467
3468 /**
3469  * i40e_aq_release_resource
3470  * @hw: pointer to the hw struct
3471  * @resource: resource id
3472  * @sdp_number: resource number
3473  * @cmd_details: pointer to command details structure or NULL
3474  *
3475  * release common resource using the admin queue commands
3476  **/
3477 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3478                                 enum i40e_aq_resources_ids resource,
3479                                 u8 sdp_number,
3480                                 struct i40e_asq_cmd_details *cmd_details)
3481 {
3482         struct i40e_aq_desc desc;
3483         struct i40e_aqc_request_resource *cmd =
3484                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3485         enum i40e_status_code status;
3486
3487         DEBUGFUNC("i40e_aq_release_resource");
3488
3489         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3490
3491         cmd->resource_id = CPU_TO_LE16(resource);
3492         cmd->resource_number = CPU_TO_LE32(sdp_number);
3493
3494         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3495
3496         return status;
3497 }
3498
3499 /**
3500  * i40e_aq_read_nvm
3501  * @hw: pointer to the hw struct
3502  * @module_pointer: module pointer location in words from the NVM beginning
3503  * @offset: byte offset from the module beginning
3504  * @length: length of the section to be read (in bytes from the offset)
3505  * @data: command buffer (size [bytes] = length)
3506  * @last_command: tells if this is the last command in a series
3507  * @cmd_details: pointer to command details structure or NULL
3508  *
3509  * Read the NVM using the admin queue commands
3510  **/
3511 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3512                                 u32 offset, u16 length, void *data,
3513                                 bool last_command,
3514                                 struct i40e_asq_cmd_details *cmd_details)
3515 {
3516         struct i40e_aq_desc desc;
3517         struct i40e_aqc_nvm_update *cmd =
3518                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3519         enum i40e_status_code status;
3520
3521         DEBUGFUNC("i40e_aq_read_nvm");
3522
3523         /* In offset the highest byte must be zeroed. */
3524         if (offset & 0xFF000000) {
3525                 status = I40E_ERR_PARAM;
3526                 goto i40e_aq_read_nvm_exit;
3527         }
3528
3529         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3530
3531         /* If this is the last command in a series, set the proper flag. */
3532         if (last_command)
3533                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3534         cmd->module_pointer = module_pointer;
3535         cmd->offset = CPU_TO_LE32(offset);
3536         cmd->length = CPU_TO_LE16(length);
3537
3538         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3539         if (length > I40E_AQ_LARGE_BUF)
3540                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3541
3542         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3543
3544 i40e_aq_read_nvm_exit:
3545         return status;
3546 }
3547
3548 /**
3549  * i40e_aq_read_nvm_config - read an nvm config block
3550  * @hw: pointer to the hw struct
3551  * @cmd_flags: NVM access admin command bits
3552  * @field_id: field or feature id
3553  * @data: buffer for result
3554  * @buf_size: buffer size
3555  * @element_count: pointer to count of elements read by FW
3556  * @cmd_details: pointer to command details structure or NULL
3557  **/
3558 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3559                                 u8 cmd_flags, u32 field_id, void *data,
3560                                 u16 buf_size, u16 *element_count,
3561                                 struct i40e_asq_cmd_details *cmd_details)
3562 {
3563         struct i40e_aq_desc desc;
3564         struct i40e_aqc_nvm_config_read *cmd =
3565                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3566         enum i40e_status_code status;
3567
3568         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3569         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3570         if (buf_size > I40E_AQ_LARGE_BUF)
3571                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3572
3573         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3574         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3575         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3576                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3577         else
3578                 cmd->element_id_msw = 0;
3579
3580         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3581
3582         if (!status && element_count)
3583                 *element_count = LE16_TO_CPU(cmd->element_count);
3584
3585         return status;
3586 }
3587
3588 /**
3589  * i40e_aq_write_nvm_config - write an nvm config block
3590  * @hw: pointer to the hw struct
3591  * @cmd_flags: NVM access admin command bits
3592  * @data: buffer for result
3593  * @buf_size: buffer size
3594  * @element_count: count of elements to be written
3595  * @cmd_details: pointer to command details structure or NULL
3596  **/
3597 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3598                                 u8 cmd_flags, void *data, u16 buf_size,
3599                                 u16 element_count,
3600                                 struct i40e_asq_cmd_details *cmd_details)
3601 {
3602         struct i40e_aq_desc desc;
3603         struct i40e_aqc_nvm_config_write *cmd =
3604                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3605         enum i40e_status_code status;
3606
3607         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3608         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3609         if (buf_size > I40E_AQ_LARGE_BUF)
3610                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3611
3612         cmd->element_count = CPU_TO_LE16(element_count);
3613         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3614         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3615
3616         return status;
3617 }
3618
3619 /**
3620  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3621  * @hw: pointer to the hw struct
3622  * @cmd_details: pointer to command details structure or NULL
3623  **/
3624 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3625                                 void *buff, u16 buff_size,
3626                                 struct i40e_asq_cmd_details *cmd_details)
3627 {
3628         struct i40e_aq_desc desc;
3629         enum i40e_status_code status;
3630
3631         UNREFERENCED_2PARAMETER(buff, buff_size);
3632
3633         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3634         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3635         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3636                 status = I40E_ERR_NOT_IMPLEMENTED;
3637
3638         return status;
3639 }
3640
3641 /**
3642  * i40e_aq_erase_nvm
3643  * @hw: pointer to the hw struct
3644  * @module_pointer: module pointer location in words from the NVM beginning
3645  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3646  * @length: length of the section to be erased (expressed in 4 KB)
3647  * @last_command: tells if this is the last command in a series
3648  * @cmd_details: pointer to command details structure or NULL
3649  *
3650  * Erase the NVM sector using the admin queue commands
3651  **/
3652 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3653                                 u32 offset, u16 length, bool last_command,
3654                                 struct i40e_asq_cmd_details *cmd_details)
3655 {
3656         struct i40e_aq_desc desc;
3657         struct i40e_aqc_nvm_update *cmd =
3658                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3659         enum i40e_status_code status;
3660
3661         DEBUGFUNC("i40e_aq_erase_nvm");
3662
3663         /* In offset the highest byte must be zeroed. */
3664         if (offset & 0xFF000000) {
3665                 status = I40E_ERR_PARAM;
3666                 goto i40e_aq_erase_nvm_exit;
3667         }
3668
3669         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3670
3671         /* If this is the last command in a series, set the proper flag. */
3672         if (last_command)
3673                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3674         cmd->module_pointer = module_pointer;
3675         cmd->offset = CPU_TO_LE32(offset);
3676         cmd->length = CPU_TO_LE16(length);
3677
3678         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3679
3680 i40e_aq_erase_nvm_exit:
3681         return status;
3682 }
3683
3684 /**
3685  * i40e_parse_discover_capabilities
3686  * @hw: pointer to the hw struct
3687  * @buff: pointer to a buffer containing device/function capability records
3688  * @cap_count: number of capability records in the list
3689  * @list_type_opc: type of capabilities list to parse
3690  *
3691  * Parse the device/function capabilities list.
3692  **/
3693 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3694                                      u32 cap_count,
3695                                      enum i40e_admin_queue_opc list_type_opc)
3696 {
3697         struct i40e_aqc_list_capabilities_element_resp *cap;
3698         u32 valid_functions, num_functions;
3699         u32 number, logical_id, phys_id;
3700         struct i40e_hw_capabilities *p;
3701         u8 major_rev;
3702         u32 i = 0;
3703         u16 id;
3704
3705         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3706
3707         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3708                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3709         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3710                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3711         else
3712                 return;
3713
3714         for (i = 0; i < cap_count; i++, cap++) {
3715                 id = LE16_TO_CPU(cap->id);
3716                 number = LE32_TO_CPU(cap->number);
3717                 logical_id = LE32_TO_CPU(cap->logical_id);
3718                 phys_id = LE32_TO_CPU(cap->phys_id);
3719                 major_rev = cap->major_rev;
3720
3721                 switch (id) {
3722                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3723                         p->switch_mode = number;
3724                         i40e_debug(hw, I40E_DEBUG_INIT,
3725                                    "HW Capability: Switch mode = %d\n",
3726                                    p->switch_mode);
3727                         break;
3728                 case I40E_AQ_CAP_ID_MNG_MODE:
3729                         p->management_mode = number;
3730                         if (major_rev > 1) {
3731                                 p->mng_protocols_over_mctp = logical_id;
3732                                 i40e_debug(hw, I40E_DEBUG_INIT,
3733                                            "HW Capability: Protocols over MCTP = %d\n",
3734                                            p->mng_protocols_over_mctp);
3735                         } else {
3736                                 p->mng_protocols_over_mctp = 0;
3737                         }
3738                         i40e_debug(hw, I40E_DEBUG_INIT,
3739                                    "HW Capability: Management Mode = %d\n",
3740                                    p->management_mode);
3741                         break;
3742                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3743                         p->npar_enable = number;
3744                         i40e_debug(hw, I40E_DEBUG_INIT,
3745                                    "HW Capability: NPAR enable = %d\n",
3746                                    p->npar_enable);
3747                         break;
3748                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3749                         p->os2bmc = number;
3750                         i40e_debug(hw, I40E_DEBUG_INIT,
3751                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3752                         break;
3753                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3754                         p->valid_functions = number;
3755                         i40e_debug(hw, I40E_DEBUG_INIT,
3756                                    "HW Capability: Valid Functions = %d\n",
3757                                    p->valid_functions);
3758                         break;
3759                 case I40E_AQ_CAP_ID_SRIOV:
3760                         if (number == 1)
3761                                 p->sr_iov_1_1 = true;
3762                         i40e_debug(hw, I40E_DEBUG_INIT,
3763                                    "HW Capability: SR-IOV = %d\n",
3764                                    p->sr_iov_1_1);
3765                         break;
3766                 case I40E_AQ_CAP_ID_VF:
3767                         p->num_vfs = number;
3768                         p->vf_base_id = logical_id;
3769                         i40e_debug(hw, I40E_DEBUG_INIT,
3770                                    "HW Capability: VF count = %d\n",
3771                                    p->num_vfs);
3772                         i40e_debug(hw, I40E_DEBUG_INIT,
3773                                    "HW Capability: VF base_id = %d\n",
3774                                    p->vf_base_id);
3775                         break;
3776                 case I40E_AQ_CAP_ID_VMDQ:
3777                         if (number == 1)
3778                                 p->vmdq = true;
3779                         i40e_debug(hw, I40E_DEBUG_INIT,
3780                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3781                         break;
3782                 case I40E_AQ_CAP_ID_8021QBG:
3783                         if (number == 1)
3784                                 p->evb_802_1_qbg = true;
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: 802.1Qbg = %d\n", number);
3787                         break;
3788                 case I40E_AQ_CAP_ID_8021QBR:
3789                         if (number == 1)
3790                                 p->evb_802_1_qbh = true;
3791                         i40e_debug(hw, I40E_DEBUG_INIT,
3792                                    "HW Capability: 802.1Qbh = %d\n", number);
3793                         break;
3794                 case I40E_AQ_CAP_ID_VSI:
3795                         p->num_vsis = number;
3796                         i40e_debug(hw, I40E_DEBUG_INIT,
3797                                    "HW Capability: VSI count = %d\n",
3798                                    p->num_vsis);
3799                         break;
3800                 case I40E_AQ_CAP_ID_DCB:
3801                         if (number == 1) {
3802                                 p->dcb = true;
3803                                 p->enabled_tcmap = logical_id;
3804                                 p->maxtc = phys_id;
3805                         }
3806                         i40e_debug(hw, I40E_DEBUG_INIT,
3807                                    "HW Capability: DCB = %d\n", p->dcb);
3808                         i40e_debug(hw, I40E_DEBUG_INIT,
3809                                    "HW Capability: TC Mapping = %d\n",
3810                                    logical_id);
3811                         i40e_debug(hw, I40E_DEBUG_INIT,
3812                                    "HW Capability: TC Max = %d\n", p->maxtc);
3813                         break;
3814                 case I40E_AQ_CAP_ID_FCOE:
3815                         if (number == 1)
3816                                 p->fcoe = true;
3817                         i40e_debug(hw, I40E_DEBUG_INIT,
3818                                    "HW Capability: FCOE = %d\n", p->fcoe);
3819                         break;
3820                 case I40E_AQ_CAP_ID_ISCSI:
3821                         if (number == 1)
3822                                 p->iscsi = true;
3823                         i40e_debug(hw, I40E_DEBUG_INIT,
3824                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3825                         break;
3826                 case I40E_AQ_CAP_ID_RSS:
3827                         p->rss = true;
3828                         p->rss_table_size = number;
3829                         p->rss_table_entry_width = logical_id;
3830                         i40e_debug(hw, I40E_DEBUG_INIT,
3831                                    "HW Capability: RSS = %d\n", p->rss);
3832                         i40e_debug(hw, I40E_DEBUG_INIT,
3833                                    "HW Capability: RSS table size = %d\n",
3834                                    p->rss_table_size);
3835                         i40e_debug(hw, I40E_DEBUG_INIT,
3836                                    "HW Capability: RSS table width = %d\n",
3837                                    p->rss_table_entry_width);
3838                         break;
3839                 case I40E_AQ_CAP_ID_RXQ:
3840                         p->num_rx_qp = number;
3841                         p->base_queue = phys_id;
3842                         i40e_debug(hw, I40E_DEBUG_INIT,
3843                                    "HW Capability: Rx QP = %d\n", number);
3844                         i40e_debug(hw, I40E_DEBUG_INIT,
3845                                    "HW Capability: base_queue = %d\n",
3846                                    p->base_queue);
3847                         break;
3848                 case I40E_AQ_CAP_ID_TXQ:
3849                         p->num_tx_qp = number;
3850                         p->base_queue = phys_id;
3851                         i40e_debug(hw, I40E_DEBUG_INIT,
3852                                    "HW Capability: Tx QP = %d\n", number);
3853                         i40e_debug(hw, I40E_DEBUG_INIT,
3854                                    "HW Capability: base_queue = %d\n",
3855                                    p->base_queue);
3856                         break;
3857                 case I40E_AQ_CAP_ID_MSIX:
3858                         p->num_msix_vectors = number;
3859                         i40e_debug(hw, I40E_DEBUG_INIT,
3860                                    "HW Capability: MSIX vector count = %d\n",
3861                                    p->num_msix_vectors);
3862                         break;
3863                 case I40E_AQ_CAP_ID_VF_MSIX:
3864                         p->num_msix_vectors_vf = number;
3865                         i40e_debug(hw, I40E_DEBUG_INIT,
3866                                    "HW Capability: MSIX VF vector count = %d\n",
3867                                    p->num_msix_vectors_vf);
3868                         break;
3869                 case I40E_AQ_CAP_ID_FLEX10:
3870                         if (major_rev == 1) {
3871                                 if (number == 1) {
3872                                         p->flex10_enable = true;
3873                                         p->flex10_capable = true;
3874                                 }
3875                         } else {
3876                                 /* Capability revision >= 2 */
3877                                 if (number & 1)
3878                                         p->flex10_enable = true;
3879                                 if (number & 2)
3880                                         p->flex10_capable = true;
3881                         }
3882                         p->flex10_mode = logical_id;
3883                         p->flex10_status = phys_id;
3884                         i40e_debug(hw, I40E_DEBUG_INIT,
3885                                    "HW Capability: Flex10 mode = %d\n",
3886                                    p->flex10_mode);
3887                         i40e_debug(hw, I40E_DEBUG_INIT,
3888                                    "HW Capability: Flex10 status = %d\n",
3889                                    p->flex10_status);
3890                         break;
3891                 case I40E_AQ_CAP_ID_CEM:
3892                         if (number == 1)
3893                                 p->mgmt_cem = true;
3894                         i40e_debug(hw, I40E_DEBUG_INIT,
3895                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3896                         break;
3897                 case I40E_AQ_CAP_ID_IWARP:
3898                         if (number == 1)
3899                                 p->iwarp = true;
3900                         i40e_debug(hw, I40E_DEBUG_INIT,
3901                                    "HW Capability: iWARP = %d\n", p->iwarp);
3902                         break;
3903                 case I40E_AQ_CAP_ID_LED:
3904                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3905                                 p->led[phys_id] = true;
3906                         i40e_debug(hw, I40E_DEBUG_INIT,
3907                                    "HW Capability: LED - PIN %d\n", phys_id);
3908                         break;
3909                 case I40E_AQ_CAP_ID_SDP:
3910                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3911                                 p->sdp[phys_id] = true;
3912                         i40e_debug(hw, I40E_DEBUG_INIT,
3913                                    "HW Capability: SDP - PIN %d\n", phys_id);
3914                         break;
3915                 case I40E_AQ_CAP_ID_MDIO:
3916                         if (number == 1) {
3917                                 p->mdio_port_num = phys_id;
3918                                 p->mdio_port_mode = logical_id;
3919                         }
3920                         i40e_debug(hw, I40E_DEBUG_INIT,
3921                                    "HW Capability: MDIO port number = %d\n",
3922                                    p->mdio_port_num);
3923                         i40e_debug(hw, I40E_DEBUG_INIT,
3924                                    "HW Capability: MDIO port mode = %d\n",
3925                                    p->mdio_port_mode);
3926                         break;
3927                 case I40E_AQ_CAP_ID_1588:
3928                         if (number == 1)
3929                                 p->ieee_1588 = true;
3930                         i40e_debug(hw, I40E_DEBUG_INIT,
3931                                    "HW Capability: IEEE 1588 = %d\n",
3932                                    p->ieee_1588);
3933                         break;
3934                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3935                         p->fd = true;
3936                         p->fd_filters_guaranteed = number;
3937                         p->fd_filters_best_effort = logical_id;
3938                         i40e_debug(hw, I40E_DEBUG_INIT,
3939                                    "HW Capability: Flow Director = 1\n");
3940                         i40e_debug(hw, I40E_DEBUG_INIT,
3941                                    "HW Capability: Guaranteed FD filters = %d\n",
3942                                    p->fd_filters_guaranteed);
3943                         break;
3944                 case I40E_AQ_CAP_ID_WSR_PROT:
3945                         p->wr_csr_prot = (u64)number;
3946                         p->wr_csr_prot |= (u64)logical_id << 32;
3947                         i40e_debug(hw, I40E_DEBUG_INIT,
3948                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3949                                    (p->wr_csr_prot & 0xffff));
3950                         break;
3951                 case I40E_AQ_CAP_ID_NVM_MGMT:
3952                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3953                                 p->sec_rev_disabled = true;
3954                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3955                                 p->update_disabled = true;
3956                         break;
3957                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3958                         hw->num_wol_proxy_filters = (u16)number;
3959                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3960                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3961                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3962                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3963                         else
3964                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3965                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3966                         i40e_debug(hw, I40E_DEBUG_INIT,
3967                                    "HW Capability: WOL proxy filters = %d\n",
3968                                    hw->num_wol_proxy_filters);
3969                         break;
3970                 default:
3971                         break;
3972                 }
3973         }
3974
3975         if (p->fcoe)
3976                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3977
3978         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3979         p->fcoe = false;
3980
3981         /* count the enabled ports (aka the "not disabled" ports) */
3982         hw->num_ports = 0;
3983         for (i = 0; i < 4; i++) {
3984                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3985                 u64 port_cfg = 0;
3986
3987                 /* use AQ read to get the physical register offset instead
3988                  * of the port relative offset
3989                  */
3990                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3991                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3992                         hw->num_ports++;
3993         }
3994
3995         valid_functions = p->valid_functions;
3996         num_functions = 0;
3997         while (valid_functions) {
3998                 if (valid_functions & 1)
3999                         num_functions++;
4000                 valid_functions >>= 1;
4001         }
4002
4003         /* partition id is 1-based, and functions are evenly spread
4004          * across the ports as partitions
4005          */
4006         if (hw->num_ports != 0) {
4007                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4008                 hw->num_partitions = num_functions / hw->num_ports;
4009         }
4010
4011         /* additional HW specific goodies that might
4012          * someday be HW version specific
4013          */
4014         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4015 }
4016
4017 /**
4018  * i40e_aq_discover_capabilities
4019  * @hw: pointer to the hw struct
4020  * @buff: a virtual buffer to hold the capabilities
4021  * @buff_size: Size of the virtual buffer
4022  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4023  * @list_type_opc: capabilities type to discover - pass in the command opcode
4024  * @cmd_details: pointer to command details structure or NULL
4025  *
4026  * Get the device capabilities descriptions from the firmware
4027  **/
4028 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4029                                 void *buff, u16 buff_size, u16 *data_size,
4030                                 enum i40e_admin_queue_opc list_type_opc,
4031                                 struct i40e_asq_cmd_details *cmd_details)
4032 {
4033         struct i40e_aqc_list_capabilites *cmd;
4034         struct i40e_aq_desc desc;
4035         enum i40e_status_code status = I40E_SUCCESS;
4036
4037         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4038
4039         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4040                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4041                 status = I40E_ERR_PARAM;
4042                 goto exit;
4043         }
4044
4045         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4046
4047         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4048         if (buff_size > I40E_AQ_LARGE_BUF)
4049                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4050
4051         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4052         *data_size = LE16_TO_CPU(desc.datalen);
4053
4054         if (status)
4055                 goto exit;
4056
4057         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4058                                          list_type_opc);
4059
4060 exit:
4061         return status;
4062 }
4063
4064 /**
4065  * i40e_aq_update_nvm
4066  * @hw: pointer to the hw struct
4067  * @module_pointer: module pointer location in words from the NVM beginning
4068  * @offset: byte offset from the module beginning
4069  * @length: length of the section to be written (in bytes from the offset)
4070  * @data: command buffer (size [bytes] = length)
4071  * @last_command: tells if this is the last command in a series
4072  * @cmd_details: pointer to command details structure or NULL
4073  *
4074  * Update the NVM using the admin queue commands
4075  **/
4076 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4077                                 u32 offset, u16 length, void *data,
4078                                 bool last_command,
4079                                 struct i40e_asq_cmd_details *cmd_details)
4080 {
4081         struct i40e_aq_desc desc;
4082         struct i40e_aqc_nvm_update *cmd =
4083                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4084         enum i40e_status_code status;
4085
4086         DEBUGFUNC("i40e_aq_update_nvm");
4087
4088         /* In offset the highest byte must be zeroed. */
4089         if (offset & 0xFF000000) {
4090                 status = I40E_ERR_PARAM;
4091                 goto i40e_aq_update_nvm_exit;
4092         }
4093
4094         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4095
4096         /* If this is the last command in a series, set the proper flag. */
4097         if (last_command)
4098                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4099         cmd->module_pointer = module_pointer;
4100         cmd->offset = CPU_TO_LE32(offset);
4101         cmd->length = CPU_TO_LE16(length);
4102
4103         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4104         if (length > I40E_AQ_LARGE_BUF)
4105                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4106
4107         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4108
4109 i40e_aq_update_nvm_exit:
4110         return status;
4111 }
4112
4113 /**
4114  * i40e_aq_get_lldp_mib
4115  * @hw: pointer to the hw struct
4116  * @bridge_type: type of bridge requested
4117  * @mib_type: Local, Remote or both Local and Remote MIBs
4118  * @buff: pointer to a user supplied buffer to store the MIB block
4119  * @buff_size: size of the buffer (in bytes)
4120  * @local_len : length of the returned Local LLDP MIB
4121  * @remote_len: length of the returned Remote LLDP MIB
4122  * @cmd_details: pointer to command details structure or NULL
4123  *
4124  * Requests the complete LLDP MIB (entire packet).
4125  **/
4126 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4127                                 u8 mib_type, void *buff, u16 buff_size,
4128                                 u16 *local_len, u16 *remote_len,
4129                                 struct i40e_asq_cmd_details *cmd_details)
4130 {
4131         struct i40e_aq_desc desc;
4132         struct i40e_aqc_lldp_get_mib *cmd =
4133                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4134         struct i40e_aqc_lldp_get_mib *resp =
4135                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4136         enum i40e_status_code status;
4137
4138         if (buff_size == 0 || !buff)
4139                 return I40E_ERR_PARAM;
4140
4141         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4142         /* Indirect Command */
4143         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4144
4145         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4146         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4147                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4148
4149         desc.datalen = CPU_TO_LE16(buff_size);
4150
4151         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4152         if (buff_size > I40E_AQ_LARGE_BUF)
4153                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4154
4155         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4156         if (!status) {
4157                 if (local_len != NULL)
4158                         *local_len = LE16_TO_CPU(resp->local_len);
4159                 if (remote_len != NULL)
4160                         *remote_len = LE16_TO_CPU(resp->remote_len);
4161         }
4162
4163         return status;
4164 }
4165
4166  /**
4167  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4168  * @hw: pointer to the hw struct
4169  * @mib_type: Local, Remote or both Local and Remote MIBs
4170  * @buff: pointer to a user supplied buffer to store the MIB block
4171  * @buff_size: size of the buffer (in bytes)
4172  * @cmd_details: pointer to command details structure or NULL
4173  *
4174  * Set the LLDP MIB.
4175  **/
4176 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4177                                 u8 mib_type, void *buff, u16 buff_size,
4178                                 struct i40e_asq_cmd_details *cmd_details)
4179 {
4180         struct i40e_aq_desc desc;
4181         struct i40e_aqc_lldp_set_local_mib *cmd =
4182                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4183         enum i40e_status_code status;
4184
4185         if (buff_size == 0 || !buff)
4186                 return I40E_ERR_PARAM;
4187
4188         i40e_fill_default_direct_cmd_desc(&desc,
4189                                 i40e_aqc_opc_lldp_set_local_mib);
4190         /* Indirect Command */
4191         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4192         if (buff_size > I40E_AQ_LARGE_BUF)
4193                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4194         desc.datalen = CPU_TO_LE16(buff_size);
4195
4196         cmd->type = mib_type;
4197         cmd->length = CPU_TO_LE16(buff_size);
4198         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4199         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4200
4201         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4202         return status;
4203 }
4204
4205 /**
4206  * i40e_aq_cfg_lldp_mib_change_event
4207  * @hw: pointer to the hw struct
4208  * @enable_update: Enable or Disable event posting
4209  * @cmd_details: pointer to command details structure or NULL
4210  *
4211  * Enable or Disable posting of an event on ARQ when LLDP MIB
4212  * associated with the interface changes
4213  **/
4214 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4215                                 bool enable_update,
4216                                 struct i40e_asq_cmd_details *cmd_details)
4217 {
4218         struct i40e_aq_desc desc;
4219         struct i40e_aqc_lldp_update_mib *cmd =
4220                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4221         enum i40e_status_code status;
4222
4223         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4224
4225         if (!enable_update)
4226                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4227
4228         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4229
4230         return status;
4231 }
4232
4233 /**
4234  * i40e_aq_add_lldp_tlv
4235  * @hw: pointer to the hw struct
4236  * @bridge_type: type of bridge
4237  * @buff: buffer with TLV to add
4238  * @buff_size: length of the buffer
4239  * @tlv_len: length of the TLV to be added
4240  * @mib_len: length of the LLDP MIB returned in response
4241  * @cmd_details: pointer to command details structure or NULL
4242  *
4243  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4244  * it is responsibility of the caller to make sure that the TLV is not
4245  * already present in the LLDPDU.
4246  * In return firmware will write the complete LLDP MIB with the newly
4247  * added TLV in the response buffer.
4248  **/
4249 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4250                                 void *buff, u16 buff_size, u16 tlv_len,
4251                                 u16 *mib_len,
4252                                 struct i40e_asq_cmd_details *cmd_details)
4253 {
4254         struct i40e_aq_desc desc;
4255         struct i40e_aqc_lldp_add_tlv *cmd =
4256                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4257         enum i40e_status_code status;
4258
4259         if (buff_size == 0 || !buff || tlv_len == 0)
4260                 return I40E_ERR_PARAM;
4261
4262         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4263
4264         /* Indirect Command */
4265         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4266         if (buff_size > I40E_AQ_LARGE_BUF)
4267                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4268         desc.datalen = CPU_TO_LE16(buff_size);
4269
4270         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4271                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4272         cmd->len = CPU_TO_LE16(tlv_len);
4273
4274         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4275         if (!status) {
4276                 if (mib_len != NULL)
4277                         *mib_len = LE16_TO_CPU(desc.datalen);
4278         }
4279
4280         return status;
4281 }
4282
4283 /**
4284  * i40e_aq_update_lldp_tlv
4285  * @hw: pointer to the hw struct
4286  * @bridge_type: type of bridge
4287  * @buff: buffer with TLV to update
4288  * @buff_size: size of the buffer holding original and updated TLVs
4289  * @old_len: Length of the Original TLV
4290  * @new_len: Length of the Updated TLV
4291  * @offset: offset of the updated TLV in the buff
4292  * @mib_len: length of the returned LLDP MIB
4293  * @cmd_details: pointer to command details structure or NULL
4294  *
4295  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4296  * Firmware will place the complete LLDP MIB in response buffer with the
4297  * updated TLV.
4298  **/
4299 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4300                                 u8 bridge_type, void *buff, u16 buff_size,
4301                                 u16 old_len, u16 new_len, u16 offset,
4302                                 u16 *mib_len,
4303                                 struct i40e_asq_cmd_details *cmd_details)
4304 {
4305         struct i40e_aq_desc desc;
4306         struct i40e_aqc_lldp_update_tlv *cmd =
4307                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4308         enum i40e_status_code status;
4309
4310         if (buff_size == 0 || !buff || offset == 0 ||
4311             old_len == 0 || new_len == 0)
4312                 return I40E_ERR_PARAM;
4313
4314         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4315
4316         /* Indirect Command */
4317         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4318         if (buff_size > I40E_AQ_LARGE_BUF)
4319                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4320         desc.datalen = CPU_TO_LE16(buff_size);
4321
4322         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4323                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4324         cmd->old_len = CPU_TO_LE16(old_len);
4325         cmd->new_offset = CPU_TO_LE16(offset);
4326         cmd->new_len = CPU_TO_LE16(new_len);
4327
4328         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4329         if (!status) {
4330                 if (mib_len != NULL)
4331                         *mib_len = LE16_TO_CPU(desc.datalen);
4332         }
4333
4334         return status;
4335 }
4336
4337 /**
4338  * i40e_aq_delete_lldp_tlv
4339  * @hw: pointer to the hw struct
4340  * @bridge_type: type of bridge
4341  * @buff: pointer to a user supplied buffer that has the TLV
4342  * @buff_size: length of the buffer
4343  * @tlv_len: length of the TLV to be deleted
4344  * @mib_len: length of the returned LLDP MIB
4345  * @cmd_details: pointer to command details structure or NULL
4346  *
4347  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4348  * The firmware places the entire LLDP MIB in the response buffer.
4349  **/
4350 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4351                                 u8 bridge_type, void *buff, u16 buff_size,
4352                                 u16 tlv_len, u16 *mib_len,
4353                                 struct i40e_asq_cmd_details *cmd_details)
4354 {
4355         struct i40e_aq_desc desc;
4356         struct i40e_aqc_lldp_add_tlv *cmd =
4357                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4358         enum i40e_status_code status;
4359
4360         if (buff_size == 0 || !buff)
4361                 return I40E_ERR_PARAM;
4362
4363         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4364
4365         /* Indirect Command */
4366         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4367         if (buff_size > I40E_AQ_LARGE_BUF)
4368                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4369         desc.datalen = CPU_TO_LE16(buff_size);
4370         cmd->len = CPU_TO_LE16(tlv_len);
4371         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4372                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4373
4374         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4375         if (!status) {
4376                 if (mib_len != NULL)
4377                         *mib_len = LE16_TO_CPU(desc.datalen);
4378         }
4379
4380         return status;
4381 }
4382
4383 /**
4384  * i40e_aq_stop_lldp
4385  * @hw: pointer to the hw struct
4386  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4387  * @cmd_details: pointer to command details structure or NULL
4388  *
4389  * Stop or Shutdown the embedded LLDP Agent
4390  **/
4391 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4392                                 struct i40e_asq_cmd_details *cmd_details)
4393 {
4394         struct i40e_aq_desc desc;
4395         struct i40e_aqc_lldp_stop *cmd =
4396                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4397         enum i40e_status_code status;
4398
4399         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4400
4401         if (shutdown_agent)
4402                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4403
4404         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4405
4406         return status;
4407 }
4408
4409 /**
4410  * i40e_aq_start_lldp
4411  * @hw: pointer to the hw struct
4412  * @cmd_details: pointer to command details structure or NULL
4413  *
4414  * Start the embedded LLDP Agent on all ports.
4415  **/
4416 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4417                                 struct i40e_asq_cmd_details *cmd_details)
4418 {
4419         struct i40e_aq_desc desc;
4420         struct i40e_aqc_lldp_start *cmd =
4421                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4422         enum i40e_status_code status;
4423
4424         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4425
4426         cmd->command = I40E_AQ_LLDP_AGENT_START;
4427
4428         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4429
4430         return status;
4431 }
4432
4433 /**
4434  * i40e_aq_get_cee_dcb_config
4435  * @hw: pointer to the hw struct
4436  * @buff: response buffer that stores CEE operational configuration
4437  * @buff_size: size of the buffer passed
4438  * @cmd_details: pointer to command details structure or NULL
4439  *
4440  * Get CEE DCBX mode operational configuration from firmware
4441  **/
4442 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4443                                 void *buff, u16 buff_size,
4444                                 struct i40e_asq_cmd_details *cmd_details)
4445 {
4446         struct i40e_aq_desc desc;
4447         enum i40e_status_code status;
4448
4449         if (buff_size == 0 || !buff)
4450                 return I40E_ERR_PARAM;
4451
4452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4453
4454         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4455         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4456                                        cmd_details);
4457
4458         return status;
4459 }
4460
4461 /**
4462  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4463  * @hw: pointer to the hw struct
4464  * @start_agent: True if DCBx Agent needs to be Started
4465  *                              False if DCBx Agent needs to be Stopped
4466  * @cmd_details: pointer to command details structure or NULL
4467  *
4468  * Start/Stop the embedded dcbx Agent
4469  **/
4470 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4471                                 bool start_agent,
4472                                 struct i40e_asq_cmd_details *cmd_details)
4473 {
4474         struct i40e_aq_desc desc;
4475         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4476                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4477                                 &desc.params.raw;
4478         enum i40e_status_code status;
4479
4480         i40e_fill_default_direct_cmd_desc(&desc,
4481                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4482
4483         if (start_agent)
4484                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4485
4486         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4487
4488         return status;
4489 }
4490
4491 /**
4492  * i40e_aq_add_udp_tunnel
4493  * @hw: pointer to the hw struct
4494  * @udp_port: the UDP port to add in Host byte order
4495  * @header_len: length of the tunneling header length in DWords
4496  * @protocol_index: protocol index type
4497  * @filter_index: pointer to filter index
4498  * @cmd_details: pointer to command details structure or NULL
4499  *
4500  * Note: Firmware expects the udp_port value to be in Little Endian format,
4501  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4502  * Little Endian order.
4503  **/
4504 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4505                                 u16 udp_port, u8 protocol_index,
4506                                 u8 *filter_index,
4507                                 struct i40e_asq_cmd_details *cmd_details)
4508 {
4509         struct i40e_aq_desc desc;
4510         struct i40e_aqc_add_udp_tunnel *cmd =
4511                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4512         struct i40e_aqc_del_udp_tunnel_completion *resp =
4513                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4514         enum i40e_status_code status;
4515
4516         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4517
4518         cmd->udp_port = CPU_TO_LE16(udp_port);
4519         cmd->protocol_type = protocol_index;
4520
4521         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4522
4523         if (!status && filter_index)
4524                 *filter_index = resp->index;
4525
4526         return status;
4527 }
4528
4529 /**
4530  * i40e_aq_del_udp_tunnel
4531  * @hw: pointer to the hw struct
4532  * @index: filter index
4533  * @cmd_details: pointer to command details structure or NULL
4534  **/
4535 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4536                                 struct i40e_asq_cmd_details *cmd_details)
4537 {
4538         struct i40e_aq_desc desc;
4539         struct i40e_aqc_remove_udp_tunnel *cmd =
4540                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4541         enum i40e_status_code status;
4542
4543         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4544
4545         cmd->index = index;
4546
4547         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4548
4549         return status;
4550 }
4551
4552 /**
4553  * i40e_aq_get_switch_resource_alloc (0x0204)
4554  * @hw: pointer to the hw struct
4555  * @num_entries: pointer to u8 to store the number of resource entries returned
4556  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4557  *        to store the resource information for all resource types.  Each
4558  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4559  * @count: size, in bytes, of the buffer provided
4560  * @cmd_details: pointer to command details structure or NULL
4561  *
4562  * Query the resources allocated to a function.
4563  **/
4564 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4565                         u8 *num_entries,
4566                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4567                         u16 count,
4568                         struct i40e_asq_cmd_details *cmd_details)
4569 {
4570         struct i40e_aq_desc desc;
4571         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4572                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4573         enum i40e_status_code status;
4574         u16 length = count * sizeof(*buf);
4575
4576         i40e_fill_default_direct_cmd_desc(&desc,
4577                                         i40e_aqc_opc_get_switch_resource_alloc);
4578
4579         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4580         if (length > I40E_AQ_LARGE_BUF)
4581                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4582
4583         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4584
4585         if (!status && num_entries)
4586                 *num_entries = cmd_resp->num_entries;
4587
4588         return status;
4589 }
4590
4591 /**
4592  * i40e_aq_delete_element - Delete switch element
4593  * @hw: pointer to the hw struct
4594  * @seid: the SEID to delete from the switch
4595  * @cmd_details: pointer to command details structure or NULL
4596  *
4597  * This deletes a switch element from the switch.
4598  **/
4599 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4600                                 struct i40e_asq_cmd_details *cmd_details)
4601 {
4602         struct i40e_aq_desc desc;
4603         struct i40e_aqc_switch_seid *cmd =
4604                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4605         enum i40e_status_code status;
4606
4607         if (seid == 0)
4608                 return I40E_ERR_PARAM;
4609
4610         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4611
4612         cmd->seid = CPU_TO_LE16(seid);
4613
4614         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4615
4616         return status;
4617 }
4618
4619 /**
4620  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4621  * @hw: pointer to the hw struct
4622  * @flags: component flags
4623  * @mac_seid: uplink seid (MAC SEID)
4624  * @vsi_seid: connected vsi seid
4625  * @ret_seid: seid of create pv component
4626  *
4627  * This instantiates an i40e port virtualizer with specified flags.
4628  * Depending on specified flags the port virtualizer can act as a
4629  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4630  */
4631 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4632                                        u16 mac_seid, u16 vsi_seid,
4633                                        u16 *ret_seid)
4634 {
4635         struct i40e_aq_desc desc;
4636         struct i40e_aqc_add_update_pv *cmd =
4637                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4638         struct i40e_aqc_add_update_pv_completion *resp =
4639                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4640         enum i40e_status_code status;
4641
4642         if (vsi_seid == 0)
4643                 return I40E_ERR_PARAM;
4644
4645         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4646         cmd->command_flags = CPU_TO_LE16(flags);
4647         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4648         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4649
4650         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4651         if (!status && ret_seid)
4652                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4653
4654         return status;
4655 }
4656
4657 /**
4658  * i40e_aq_add_tag - Add an S/E-tag
4659  * @hw: pointer to the hw struct
4660  * @direct_to_queue: should s-tag direct flow to a specific queue
4661  * @vsi_seid: VSI SEID to use this tag
4662  * @tag: value of the tag
4663  * @queue_num: queue number, only valid is direct_to_queue is true
4664  * @tags_used: return value, number of tags in use by this PF
4665  * @tags_free: return value, number of unallocated tags
4666  * @cmd_details: pointer to command details structure or NULL
4667  *
4668  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4669  * the number of tags allocated by the PF, and the number of unallocated
4670  * tags available.
4671  **/
4672 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4673                                 u16 vsi_seid, u16 tag, u16 queue_num,
4674                                 u16 *tags_used, u16 *tags_free,
4675                                 struct i40e_asq_cmd_details *cmd_details)
4676 {
4677         struct i40e_aq_desc desc;
4678         struct i40e_aqc_add_tag *cmd =
4679                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4680         struct i40e_aqc_add_remove_tag_completion *resp =
4681                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4682         enum i40e_status_code status;
4683
4684         if (vsi_seid == 0)
4685                 return I40E_ERR_PARAM;
4686
4687         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4688
4689         cmd->seid = CPU_TO_LE16(vsi_seid);
4690         cmd->tag = CPU_TO_LE16(tag);
4691         if (direct_to_queue) {
4692                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4693                 cmd->queue_number = CPU_TO_LE16(queue_num);
4694         }
4695
4696         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4697
4698         if (!status) {
4699                 if (tags_used != NULL)
4700                         *tags_used = LE16_TO_CPU(resp->tags_used);
4701                 if (tags_free != NULL)
4702                         *tags_free = LE16_TO_CPU(resp->tags_free);
4703         }
4704
4705         return status;
4706 }
4707
4708 /**
4709  * i40e_aq_remove_tag - Remove an S- or E-tag
4710  * @hw: pointer to the hw struct
4711  * @vsi_seid: VSI SEID this tag is associated with
4712  * @tag: value of the S-tag to delete
4713  * @tags_used: return value, number of tags in use by this PF
4714  * @tags_free: return value, number of unallocated tags
4715  * @cmd_details: pointer to command details structure or NULL
4716  *
4717  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4718  * the number of tags allocated by the PF, and the number of unallocated
4719  * tags available.
4720  **/
4721 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4722                                 u16 tag, u16 *tags_used, u16 *tags_free,
4723                                 struct i40e_asq_cmd_details *cmd_details)
4724 {
4725         struct i40e_aq_desc desc;
4726         struct i40e_aqc_remove_tag *cmd =
4727                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4728         struct i40e_aqc_add_remove_tag_completion *resp =
4729                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4730         enum i40e_status_code status;
4731
4732         if (vsi_seid == 0)
4733                 return I40E_ERR_PARAM;
4734
4735         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4736
4737         cmd->seid = CPU_TO_LE16(vsi_seid);
4738         cmd->tag = CPU_TO_LE16(tag);
4739
4740         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4741
4742         if (!status) {
4743                 if (tags_used != NULL)
4744                         *tags_used = LE16_TO_CPU(resp->tags_used);
4745                 if (tags_free != NULL)
4746                         *tags_free = LE16_TO_CPU(resp->tags_free);
4747         }
4748
4749         return status;
4750 }
4751
4752 /**
4753  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4754  * @hw: pointer to the hw struct
4755  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4756  * @etag: value of E-tag to add
4757  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4758  * @buf: address of indirect buffer
4759  * @tags_used: return value, number of E-tags in use by this port
4760  * @tags_free: return value, number of unallocated M-tags
4761  * @cmd_details: pointer to command details structure or NULL
4762  *
4763  * This associates a multicast E-tag to a port virtualizer.  It will return
4764  * the number of tags allocated by the PF, and the number of unallocated
4765  * tags available.
4766  *
4767  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4768  * num_tags_in_buf long.
4769  **/
4770 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4771                                 u16 etag, u8 num_tags_in_buf, void *buf,
4772                                 u16 *tags_used, u16 *tags_free,
4773                                 struct i40e_asq_cmd_details *cmd_details)
4774 {
4775         struct i40e_aq_desc desc;
4776         struct i40e_aqc_add_remove_mcast_etag *cmd =
4777                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4778         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4779            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4780         enum i40e_status_code status;
4781         u16 length = sizeof(u16) * num_tags_in_buf;
4782
4783         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4784                 return I40E_ERR_PARAM;
4785
4786         i40e_fill_default_direct_cmd_desc(&desc,
4787                                           i40e_aqc_opc_add_multicast_etag);
4788
4789         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4790         cmd->etag = CPU_TO_LE16(etag);
4791         cmd->num_unicast_etags = num_tags_in_buf;
4792
4793         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4794         if (length > I40E_AQ_LARGE_BUF)
4795                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4796
4797         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4798
4799         if (!status) {
4800                 if (tags_used != NULL)
4801                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4802                 if (tags_free != NULL)
4803                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4804         }
4805
4806         return status;
4807 }
4808
4809 /**
4810  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4811  * @hw: pointer to the hw struct
4812  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4813  * @etag: value of the E-tag to remove
4814  * @tags_used: return value, number of tags in use by this port
4815  * @tags_free: return value, number of unallocated tags
4816  * @cmd_details: pointer to command details structure or NULL
4817  *
4818  * This deletes an E-tag from the port virtualizer.  It will return
4819  * the number of tags allocated by the port, and the number of unallocated
4820  * tags available.
4821  **/
4822 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4823                                 u16 etag, u16 *tags_used, u16 *tags_free,
4824                                 struct i40e_asq_cmd_details *cmd_details)
4825 {
4826         struct i40e_aq_desc desc;
4827         struct i40e_aqc_add_remove_mcast_etag *cmd =
4828                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4829         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4830            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4831         enum i40e_status_code status;
4832
4833
4834         if (pv_seid == 0)
4835                 return I40E_ERR_PARAM;
4836
4837         i40e_fill_default_direct_cmd_desc(&desc,
4838                                           i40e_aqc_opc_remove_multicast_etag);
4839
4840         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4841         cmd->etag = CPU_TO_LE16(etag);
4842
4843         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4844
4845         if (!status) {
4846                 if (tags_used != NULL)
4847                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4848                 if (tags_free != NULL)
4849                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4850         }
4851
4852         return status;
4853 }
4854
4855 /**
4856  * i40e_aq_update_tag - Update an S/E-tag
4857  * @hw: pointer to the hw struct
4858  * @vsi_seid: VSI SEID using this S-tag
4859  * @old_tag: old tag value
4860  * @new_tag: new tag value
4861  * @tags_used: return value, number of tags in use by this PF
4862  * @tags_free: return value, number of unallocated tags
4863  * @cmd_details: pointer to command details structure or NULL
4864  *
4865  * This updates the value of the tag currently attached to this VSI
4866  * in the switch complex.  It will return the number of tags allocated
4867  * by the PF, and the number of unallocated tags available.
4868  **/
4869 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4870                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4871                                 u16 *tags_free,
4872                                 struct i40e_asq_cmd_details *cmd_details)
4873 {
4874         struct i40e_aq_desc desc;
4875         struct i40e_aqc_update_tag *cmd =
4876                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4877         struct i40e_aqc_update_tag_completion *resp =
4878                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4879         enum i40e_status_code status;
4880
4881         if (vsi_seid == 0)
4882                 return I40E_ERR_PARAM;
4883
4884         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4885
4886         cmd->seid = CPU_TO_LE16(vsi_seid);
4887         cmd->old_tag = CPU_TO_LE16(old_tag);
4888         cmd->new_tag = CPU_TO_LE16(new_tag);
4889
4890         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4891
4892         if (!status) {
4893                 if (tags_used != NULL)
4894                         *tags_used = LE16_TO_CPU(resp->tags_used);
4895                 if (tags_free != NULL)
4896                         *tags_free = LE16_TO_CPU(resp->tags_free);
4897         }
4898
4899         return status;
4900 }
4901
4902 /**
4903  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4904  * @hw: pointer to the hw struct
4905  * @tcmap: TC map for request/release any ignore PFC condition
4906  * @request: request or release ignore PFC condition
4907  * @tcmap_ret: return TCs for which PFC is currently ignored
4908  * @cmd_details: pointer to command details structure or NULL
4909  *
4910  * This sends out request/release to ignore PFC condition for a TC.
4911  * It will return the TCs for which PFC is currently ignored.
4912  **/
4913 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4914                                 bool request, u8 *tcmap_ret,
4915                                 struct i40e_asq_cmd_details *cmd_details)
4916 {
4917         struct i40e_aq_desc desc;
4918         struct i40e_aqc_pfc_ignore *cmd_resp =
4919                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4920         enum i40e_status_code status;
4921
4922         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4923
4924         if (request)
4925                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4926
4927         cmd_resp->tc_bitmap = tcmap;
4928
4929         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4930
4931         if (!status) {
4932                 if (tcmap_ret != NULL)
4933                         *tcmap_ret = cmd_resp->tc_bitmap;
4934         }
4935
4936         return status;
4937 }
4938
4939 /**
4940  * i40e_aq_dcb_updated - DCB Updated Command
4941  * @hw: pointer to the hw struct
4942  * @cmd_details: pointer to command details structure or NULL
4943  *
4944  * When LLDP is handled in PF this command is used by the PF
4945  * to notify EMP that a DCB setting is modified.
4946  * When LLDP is handled in EMP this command is used by the PF
4947  * to notify EMP whenever one of the following parameters get
4948  * modified:
4949  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4950  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4951  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4952  * EMP will return when the shared RPB settings have been
4953  * recomputed and modified. The retval field in the descriptor
4954  * will be set to 0 when RPB is modified.
4955  **/
4956 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4957                                 struct i40e_asq_cmd_details *cmd_details)
4958 {
4959         struct i40e_aq_desc desc;
4960         enum i40e_status_code status;
4961
4962         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4963
4964         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4965
4966         return status;
4967 }
4968
4969 /**
4970  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4971  * @hw: pointer to the hw struct
4972  * @seid: defines the SEID of the switch for which the stats are requested
4973  * @vlan_id: the VLAN ID for which the statistics are requested
4974  * @stat_index: index of the statistics counters block assigned to this VLAN
4975  * @cmd_details: pointer to command details structure or NULL
4976  *
4977  * XL710 supports 128 smonVlanStats counters.This command is used to
4978  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4979  * switch.
4980  **/
4981 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4982                                 u16 vlan_id, u16 *stat_index,
4983                                 struct i40e_asq_cmd_details *cmd_details)
4984 {
4985         struct i40e_aq_desc desc;
4986         struct i40e_aqc_add_remove_statistics *cmd_resp =
4987                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4988         enum i40e_status_code status;
4989
4990         if ((seid == 0) || (stat_index == NULL))
4991                 return I40E_ERR_PARAM;
4992
4993         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4994
4995         cmd_resp->seid = CPU_TO_LE16(seid);
4996         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4997
4998         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4999
5000         if (!status && stat_index)
5001                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5002
5003         return status;
5004 }
5005
5006 /**
5007  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5008  * @hw: pointer to the hw struct
5009  * @seid: defines the SEID of the switch for which the stats are requested
5010  * @vlan_id: the VLAN ID for which the statistics are requested
5011  * @stat_index: index of the statistics counters block assigned to this VLAN
5012  * @cmd_details: pointer to command details structure or NULL
5013  *
5014  * XL710 supports 128 smonVlanStats counters.This command is used to
5015  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5016  * switch.
5017  **/
5018 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5019                                 u16 vlan_id, u16 stat_index,
5020                                 struct i40e_asq_cmd_details *cmd_details)
5021 {
5022         struct i40e_aq_desc desc;
5023         struct i40e_aqc_add_remove_statistics *cmd =
5024                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5025         enum i40e_status_code status;
5026
5027         if (seid == 0)
5028                 return I40E_ERR_PARAM;
5029
5030         i40e_fill_default_direct_cmd_desc(&desc,
5031                                           i40e_aqc_opc_remove_statistics);
5032
5033         cmd->seid = CPU_TO_LE16(seid);
5034         cmd->vlan  = CPU_TO_LE16(vlan_id);
5035         cmd->stat_index = CPU_TO_LE16(stat_index);
5036
5037         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5038
5039         return status;
5040 }
5041
5042 /**
5043  * i40e_aq_set_port_parameters - set physical port parameters.
5044  * @hw: pointer to the hw struct
5045  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5046  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5047  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5048  * @double_vlan: if set double VLAN is enabled
5049  * @cmd_details: pointer to command details structure or NULL
5050  **/
5051 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5052                                 u16 bad_frame_vsi, bool save_bad_pac,
5053                                 bool pad_short_pac, bool double_vlan,
5054                                 struct i40e_asq_cmd_details *cmd_details)
5055 {
5056         struct i40e_aqc_set_port_parameters *cmd;
5057         enum i40e_status_code status;
5058         struct i40e_aq_desc desc;
5059         u16 command_flags = 0;
5060
5061         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5062
5063         i40e_fill_default_direct_cmd_desc(&desc,
5064                                           i40e_aqc_opc_set_port_parameters);
5065
5066         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5067         if (save_bad_pac)
5068                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5069         if (pad_short_pac)
5070                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5071         if (double_vlan)
5072                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5073         cmd->command_flags = CPU_TO_LE16(command_flags);
5074
5075         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5076
5077         return status;
5078 }
5079
5080 /**
5081  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5082  * @hw: pointer to the hw struct
5083  * @seid: seid for the physical port/switching component/vsi
5084  * @buff: Indirect buffer to hold data parameters and response
5085  * @buff_size: Indirect buffer size
5086  * @opcode: Tx scheduler AQ command opcode
5087  * @cmd_details: pointer to command details structure or NULL
5088  *
5089  * Generic command handler for Tx scheduler AQ commands
5090  **/
5091 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5092                                 void *buff, u16 buff_size,
5093                                  enum i40e_admin_queue_opc opcode,
5094                                 struct i40e_asq_cmd_details *cmd_details)
5095 {
5096         struct i40e_aq_desc desc;
5097         struct i40e_aqc_tx_sched_ind *cmd =
5098                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5099         enum i40e_status_code status;
5100         bool cmd_param_flag = false;
5101
5102         switch (opcode) {
5103         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5104         case i40e_aqc_opc_configure_vsi_tc_bw:
5105         case i40e_aqc_opc_enable_switching_comp_ets:
5106         case i40e_aqc_opc_modify_switching_comp_ets:
5107         case i40e_aqc_opc_disable_switching_comp_ets:
5108         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5109         case i40e_aqc_opc_configure_switching_comp_bw_config:
5110                 cmd_param_flag = true;
5111                 break;
5112         case i40e_aqc_opc_query_vsi_bw_config:
5113         case i40e_aqc_opc_query_vsi_ets_sla_config:
5114         case i40e_aqc_opc_query_switching_comp_ets_config:
5115         case i40e_aqc_opc_query_port_ets_config:
5116         case i40e_aqc_opc_query_switching_comp_bw_config:
5117                 cmd_param_flag = false;
5118                 break;
5119         default:
5120                 return I40E_ERR_PARAM;
5121         }
5122
5123         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5124
5125         /* Indirect command */
5126         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5127         if (cmd_param_flag)
5128                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5129         if (buff_size > I40E_AQ_LARGE_BUF)
5130                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5131
5132         desc.datalen = CPU_TO_LE16(buff_size);
5133
5134         cmd->vsi_seid = CPU_TO_LE16(seid);
5135
5136         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5137
5138         return status;
5139 }
5140
5141 /**
5142  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5143  * @hw: pointer to the hw struct
5144  * @seid: VSI seid
5145  * @credit: BW limit credits (0 = disabled)
5146  * @max_credit: Max BW limit credits
5147  * @cmd_details: pointer to command details structure or NULL
5148  **/
5149 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5150                                 u16 seid, u16 credit, u8 max_credit,
5151                                 struct i40e_asq_cmd_details *cmd_details)
5152 {
5153         struct i40e_aq_desc desc;
5154         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5155                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5156         enum i40e_status_code status;
5157
5158         i40e_fill_default_direct_cmd_desc(&desc,
5159                                           i40e_aqc_opc_configure_vsi_bw_limit);
5160
5161         cmd->vsi_seid = CPU_TO_LE16(seid);
5162         cmd->credit = CPU_TO_LE16(credit);
5163         cmd->max_credit = max_credit;
5164
5165         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5166
5167         return status;
5168 }
5169
5170 /**
5171  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5172  * @hw: pointer to the hw struct
5173  * @seid: switching component seid
5174  * @credit: BW limit credits (0 = disabled)
5175  * @max_bw: Max BW limit credits
5176  * @cmd_details: pointer to command details structure or NULL
5177  **/
5178 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5179                                 u16 seid, u16 credit, u8 max_bw,
5180                                 struct i40e_asq_cmd_details *cmd_details)
5181 {
5182         struct i40e_aq_desc desc;
5183         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5184           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5185         enum i40e_status_code status;
5186
5187         i40e_fill_default_direct_cmd_desc(&desc,
5188                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5189
5190         cmd->seid = CPU_TO_LE16(seid);
5191         cmd->credit = CPU_TO_LE16(credit);
5192         cmd->max_bw = max_bw;
5193
5194         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5195
5196         return status;
5197 }
5198
5199 /**
5200  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5201  * @hw: pointer to the hw struct
5202  * @seid: VSI seid
5203  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5204  * @cmd_details: pointer to command details structure or NULL
5205  **/
5206 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5207                         u16 seid,
5208                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5209                         struct i40e_asq_cmd_details *cmd_details)
5210 {
5211         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5212                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5213                                     cmd_details);
5214 }
5215
5216 /**
5217  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5218  * @hw: pointer to the hw struct
5219  * @seid: VSI seid
5220  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5221  * @cmd_details: pointer to command details structure or NULL
5222  **/
5223 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5224                         u16 seid,
5225                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5226                         struct i40e_asq_cmd_details *cmd_details)
5227 {
5228         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5229                                     i40e_aqc_opc_configure_vsi_tc_bw,
5230                                     cmd_details);
5231 }
5232
5233 /**
5234  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5235  * @hw: pointer to the hw struct
5236  * @seid: seid of the switching component connected to Physical Port
5237  * @ets_data: Buffer holding ETS parameters
5238  * @cmd_details: pointer to command details structure or NULL
5239  **/
5240 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5241                 u16 seid,
5242                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5243                 enum i40e_admin_queue_opc opcode,
5244                 struct i40e_asq_cmd_details *cmd_details)
5245 {
5246         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5247                                     sizeof(*ets_data), opcode, cmd_details);
5248 }
5249
5250 /**
5251  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5252  * @hw: pointer to the hw struct
5253  * @seid: seid of the switching component
5254  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5255  * @cmd_details: pointer to command details structure or NULL
5256  **/
5257 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5258         u16 seid,
5259         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5260         struct i40e_asq_cmd_details *cmd_details)
5261 {
5262         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5263                             i40e_aqc_opc_configure_switching_comp_bw_config,
5264                             cmd_details);
5265 }
5266
5267 /**
5268  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5269  * @hw: pointer to the hw struct
5270  * @seid: seid of the switching component
5271  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5272  * @cmd_details: pointer to command details structure or NULL
5273  **/
5274 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5275         struct i40e_hw *hw, u16 seid,
5276         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5277         struct i40e_asq_cmd_details *cmd_details)
5278 {
5279         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5280                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5281                             cmd_details);
5282 }
5283
5284 /**
5285  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5286  * @hw: pointer to the hw struct
5287  * @seid: seid of the VSI
5288  * @bw_data: Buffer to hold VSI BW configuration
5289  * @cmd_details: pointer to command details structure or NULL
5290  **/
5291 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5292                         u16 seid,
5293                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5294                         struct i40e_asq_cmd_details *cmd_details)
5295 {
5296         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5297                                     i40e_aqc_opc_query_vsi_bw_config,
5298                                     cmd_details);
5299 }
5300
5301 /**
5302  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5303  * @hw: pointer to the hw struct
5304  * @seid: seid of the VSI
5305  * @bw_data: Buffer to hold VSI BW configuration per TC
5306  * @cmd_details: pointer to command details structure or NULL
5307  **/
5308 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5309                         u16 seid,
5310                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5311                         struct i40e_asq_cmd_details *cmd_details)
5312 {
5313         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5314                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5315                                     cmd_details);
5316 }
5317
5318 /**
5319  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5320  * @hw: pointer to the hw struct
5321  * @seid: seid of the switching component
5322  * @bw_data: Buffer to hold switching component's per TC BW config
5323  * @cmd_details: pointer to command details structure or NULL
5324  **/
5325 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5326                 u16 seid,
5327                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5328                 struct i40e_asq_cmd_details *cmd_details)
5329 {
5330         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5331                                    i40e_aqc_opc_query_switching_comp_ets_config,
5332                                    cmd_details);
5333 }
5334
5335 /**
5336  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5337  * @hw: pointer to the hw struct
5338  * @seid: seid of the VSI or switching component connected to Physical Port
5339  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5340  * @cmd_details: pointer to command details structure or NULL
5341  **/
5342 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5343                         u16 seid,
5344                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5345                         struct i40e_asq_cmd_details *cmd_details)
5346 {
5347         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5348                                     i40e_aqc_opc_query_port_ets_config,
5349                                     cmd_details);
5350 }
5351
5352 /**
5353  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5354  * @hw: pointer to the hw struct
5355  * @seid: seid of the switching component
5356  * @bw_data: Buffer to hold switching component's BW configuration
5357  * @cmd_details: pointer to command details structure or NULL
5358  **/
5359 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5360                 u16 seid,
5361                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5362                 struct i40e_asq_cmd_details *cmd_details)
5363 {
5364         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5365                                     i40e_aqc_opc_query_switching_comp_bw_config,
5366                                     cmd_details);
5367 }
5368
5369 /**
5370  * i40e_validate_filter_settings
5371  * @hw: pointer to the hardware structure
5372  * @settings: Filter control settings
5373  *
5374  * Check and validate the filter control settings passed.
5375  * The function checks for the valid filter/context sizes being
5376  * passed for FCoE and PE.
5377  *
5378  * Returns I40E_SUCCESS if the values passed are valid and within
5379  * range else returns an error.
5380  **/
5381 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5382                                 struct i40e_filter_control_settings *settings)
5383 {
5384         u32 fcoe_cntx_size, fcoe_filt_size;
5385         u32 pe_cntx_size, pe_filt_size;
5386         u32 fcoe_fmax;
5387
5388         u32 val;
5389
5390         /* Validate FCoE settings passed */
5391         switch (settings->fcoe_filt_num) {
5392         case I40E_HASH_FILTER_SIZE_1K:
5393         case I40E_HASH_FILTER_SIZE_2K:
5394         case I40E_HASH_FILTER_SIZE_4K:
5395         case I40E_HASH_FILTER_SIZE_8K:
5396         case I40E_HASH_FILTER_SIZE_16K:
5397         case I40E_HASH_FILTER_SIZE_32K:
5398                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5399                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5400                 break;
5401         default:
5402                 return I40E_ERR_PARAM;
5403         }
5404
5405         switch (settings->fcoe_cntx_num) {
5406         case I40E_DMA_CNTX_SIZE_512:
5407         case I40E_DMA_CNTX_SIZE_1K:
5408         case I40E_DMA_CNTX_SIZE_2K:
5409         case I40E_DMA_CNTX_SIZE_4K:
5410                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5411                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5412                 break;
5413         default:
5414                 return I40E_ERR_PARAM;
5415         }
5416
5417         /* Validate PE settings passed */
5418         switch (settings->pe_filt_num) {
5419         case I40E_HASH_FILTER_SIZE_1K:
5420         case I40E_HASH_FILTER_SIZE_2K:
5421         case I40E_HASH_FILTER_SIZE_4K:
5422         case I40E_HASH_FILTER_SIZE_8K:
5423         case I40E_HASH_FILTER_SIZE_16K:
5424         case I40E_HASH_FILTER_SIZE_32K:
5425         case I40E_HASH_FILTER_SIZE_64K:
5426         case I40E_HASH_FILTER_SIZE_128K:
5427         case I40E_HASH_FILTER_SIZE_256K:
5428         case I40E_HASH_FILTER_SIZE_512K:
5429         case I40E_HASH_FILTER_SIZE_1M:
5430                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5431                 pe_filt_size <<= (u32)settings->pe_filt_num;
5432                 break;
5433         default:
5434                 return I40E_ERR_PARAM;
5435         }
5436
5437         switch (settings->pe_cntx_num) {
5438         case I40E_DMA_CNTX_SIZE_512:
5439         case I40E_DMA_CNTX_SIZE_1K:
5440         case I40E_DMA_CNTX_SIZE_2K:
5441         case I40E_DMA_CNTX_SIZE_4K:
5442         case I40E_DMA_CNTX_SIZE_8K:
5443         case I40E_DMA_CNTX_SIZE_16K:
5444         case I40E_DMA_CNTX_SIZE_32K:
5445         case I40E_DMA_CNTX_SIZE_64K:
5446         case I40E_DMA_CNTX_SIZE_128K:
5447         case I40E_DMA_CNTX_SIZE_256K:
5448                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5449                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5450                 break;
5451         default:
5452                 return I40E_ERR_PARAM;
5453         }
5454
5455         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5456         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5457         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5458                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5459         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5460                 return I40E_ERR_INVALID_SIZE;
5461
5462         return I40E_SUCCESS;
5463 }
5464
5465 /**
5466  * i40e_set_filter_control
5467  * @hw: pointer to the hardware structure
5468  * @settings: Filter control settings
5469  *
5470  * Set the Queue Filters for PE/FCoE and enable filters required
5471  * for a single PF. It is expected that these settings are programmed
5472  * at the driver initialization time.
5473  **/
5474 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5475                                 struct i40e_filter_control_settings *settings)
5476 {
5477         enum i40e_status_code ret = I40E_SUCCESS;
5478         u32 hash_lut_size = 0;
5479         u32 val;
5480
5481         if (!settings)
5482                 return I40E_ERR_PARAM;
5483
5484         /* Validate the input settings */
5485         ret = i40e_validate_filter_settings(hw, settings);
5486         if (ret)
5487                 return ret;
5488
5489         /* Read the PF Queue Filter control register */
5490         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5491
5492         /* Program required PE hash buckets for the PF */
5493         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5494         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5495                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5496         /* Program required PE contexts for the PF */
5497         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5498         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5499                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5500
5501         /* Program required FCoE hash buckets for the PF */
5502         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5503         val |= ((u32)settings->fcoe_filt_num <<
5504                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5505                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5506         /* Program required FCoE DDP contexts for the PF */
5507         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5508         val |= ((u32)settings->fcoe_cntx_num <<
5509                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5510                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5511
5512         /* Program Hash LUT size for the PF */
5513         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5514         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5515                 hash_lut_size = 1;
5516         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5517                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5518
5519         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5520         if (settings->enable_fdir)
5521                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5522         if (settings->enable_ethtype)
5523                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5524         if (settings->enable_macvlan)
5525                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5526
5527         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5528
5529         return I40E_SUCCESS;
5530 }
5531
5532 /**
5533  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5534  * @hw: pointer to the hw struct
5535  * @mac_addr: MAC address to use in the filter
5536  * @ethtype: Ethertype to use in the filter
5537  * @flags: Flags that needs to be applied to the filter
5538  * @vsi_seid: seid of the control VSI
5539  * @queue: VSI queue number to send the packet to
5540  * @is_add: Add control packet filter if True else remove
5541  * @stats: Structure to hold information on control filter counts
5542  * @cmd_details: pointer to command details structure or NULL
5543  *
5544  * This command will Add or Remove control packet filter for a control VSI.
5545  * In return it will update the total number of perfect filter count in
5546  * the stats member.
5547  **/
5548 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5549                                 u8 *mac_addr, u16 ethtype, u16 flags,
5550                                 u16 vsi_seid, u16 queue, bool is_add,
5551                                 struct i40e_control_filter_stats *stats,
5552                                 struct i40e_asq_cmd_details *cmd_details)
5553 {
5554         struct i40e_aq_desc desc;
5555         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5556                 (struct i40e_aqc_add_remove_control_packet_filter *)
5557                 &desc.params.raw;
5558         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5559                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5560                 &desc.params.raw;
5561         enum i40e_status_code status;
5562
5563         if (vsi_seid == 0)
5564                 return I40E_ERR_PARAM;
5565
5566         if (is_add) {
5567                 i40e_fill_default_direct_cmd_desc(&desc,
5568                                 i40e_aqc_opc_add_control_packet_filter);
5569                 cmd->queue = CPU_TO_LE16(queue);
5570         } else {
5571                 i40e_fill_default_direct_cmd_desc(&desc,
5572                                 i40e_aqc_opc_remove_control_packet_filter);
5573         }
5574
5575         if (mac_addr)
5576                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5577                             I40E_NONDMA_TO_NONDMA);
5578
5579         cmd->etype = CPU_TO_LE16(ethtype);
5580         cmd->flags = CPU_TO_LE16(flags);
5581         cmd->seid = CPU_TO_LE16(vsi_seid);
5582
5583         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5584
5585         if (!status && stats) {
5586                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5587                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5588                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5589                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5590         }
5591
5592         return status;
5593 }
5594
5595 /**
5596  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5597  * @hw: pointer to the hw struct
5598  * @seid: VSI seid to add ethertype filter from
5599  **/
5600 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5601 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5602                                                     u16 seid)
5603 {
5604         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5605                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5606                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5607         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5608         enum i40e_status_code status;
5609
5610         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5611                                                        seid, 0, true, NULL,
5612                                                        NULL);
5613         if (status)
5614                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5615 }
5616
5617 /**
5618  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5619  * @filters: list of cloud filters
5620  * @filter_count: length of list
5621  *
5622  * There's an issue in the device where the Geneve VNI layout needs
5623  * to be shifted 1 byte over from the VxLAN VNI
5624  **/
5625 STATIC void i40e_fix_up_geneve_vni(
5626         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5627         u8 filter_count)
5628 {
5629         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5630         int i;
5631
5632         for (i = 0; i < filter_count; i++) {
5633                 u16 tnl_type;
5634                 u32 ti;
5635
5636                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5637                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5638                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5639                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5640                         ti = LE32_TO_CPU(f[i].tenant_id);
5641                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5642                 }
5643         }
5644 }
5645
5646 /**
5647  * i40e_aq_add_cloud_filters
5648  * @hw: pointer to the hardware structure
5649  * @seid: VSI seid to add cloud filters from
5650  * @filters: Buffer which contains the filters to be added
5651  * @filter_count: number of filters contained in the buffer
5652  *
5653  * Set the cloud filters for a given VSI.  The contents of the
5654  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5655  * in by the caller of the function.
5656  *
5657  **/
5658 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5659         u16 seid,
5660         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5661         u8 filter_count)
5662 {
5663         struct i40e_aq_desc desc;
5664         struct i40e_aqc_add_remove_cloud_filters *cmd =
5665         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5666         enum i40e_status_code status;
5667         u16 buff_len;
5668
5669         i40e_fill_default_direct_cmd_desc(&desc,
5670                                           i40e_aqc_opc_add_cloud_filters);
5671
5672         buff_len = filter_count * sizeof(*filters);
5673         desc.datalen = CPU_TO_LE16(buff_len);
5674         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5675         cmd->num_filters = filter_count;
5676         cmd->seid = CPU_TO_LE16(seid);
5677
5678         i40e_fix_up_geneve_vni(filters, filter_count);
5679
5680         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5681
5682         return status;
5683 }
5684
5685 /**
5686  * i40e_aq_add_cloud_filters_big_buffer
5687  * @hw: pointer to the hardware structure
5688  * @seid: VSI seid to add cloud filters from
5689  * @filters: Buffer which contains the filters in big buffer to be added
5690  * @filter_count: number of filters contained in the buffer
5691  *
5692  * Set the cloud filters for a given VSI.  The contents of the
5693  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5694  * the function.
5695  *
5696  **/
5697 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5698         u16 seid,
5699         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5700         u8 filter_count)
5701 {
5702         struct i40e_aq_desc desc;
5703         struct i40e_aqc_add_remove_cloud_filters *cmd =
5704         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5705         enum i40e_status_code status;
5706         u16 buff_len;
5707         int i;
5708
5709         i40e_fill_default_direct_cmd_desc(&desc,
5710                                           i40e_aqc_opc_add_cloud_filters);
5711
5712         buff_len = filter_count * sizeof(*filters);
5713         desc.datalen = CPU_TO_LE16(buff_len);
5714         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5715         cmd->num_filters = filter_count;
5716         cmd->seid = CPU_TO_LE16(seid);
5717         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5718
5719         /* adjust Geneve VNI for HW issue */
5720         for (i = 0; i < filter_count; i++) {
5721                 u16 tnl_type;
5722                 u32 ti;
5723
5724                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5725                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5726                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5727                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5728                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5729                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5730                 }
5731         }
5732
5733         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5734
5735         return status;
5736 }
5737
5738 /**
5739  * i40e_aq_remove_cloud_filters
5740  * @hw: pointer to the hardware structure
5741  * @seid: VSI seid to remove cloud filters from
5742  * @filters: Buffer which contains the filters to be removed
5743  * @filter_count: number of filters contained in the buffer
5744  *
5745  * Remove the cloud filters for a given VSI.  The contents of the
5746  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5747  * in by the caller of the function.
5748  *
5749  **/
5750 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5751         u16 seid,
5752         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5753         u8 filter_count)
5754 {
5755         struct i40e_aq_desc desc;
5756         struct i40e_aqc_add_remove_cloud_filters *cmd =
5757         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5758         enum i40e_status_code status;
5759         u16 buff_len;
5760
5761         i40e_fill_default_direct_cmd_desc(&desc,
5762                                           i40e_aqc_opc_remove_cloud_filters);
5763
5764         buff_len = filter_count * sizeof(*filters);
5765         desc.datalen = CPU_TO_LE16(buff_len);
5766         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5767         cmd->num_filters = filter_count;
5768         cmd->seid = CPU_TO_LE16(seid);
5769
5770         i40e_fix_up_geneve_vni(filters, filter_count);
5771
5772         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5773
5774         return status;
5775 }
5776
5777 /**
5778  * i40e_aq_remove_cloud_filters_big_buffer
5779  * @hw: pointer to the hardware structure
5780  * @seid: VSI seid to remove cloud filters from
5781  * @filters: Buffer which contains the filters in big buffer to be removed
5782  * @filter_count: number of filters contained in the buffer
5783  *
5784  * Remove the cloud filters for a given VSI.  The contents of the
5785  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5786  * the function.
5787  *
5788  **/
5789 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5790         struct i40e_hw *hw,
5791         u16 seid,
5792         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5793         u8 filter_count)
5794 {
5795         struct i40e_aq_desc desc;
5796         struct i40e_aqc_add_remove_cloud_filters *cmd =
5797         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5798         enum i40e_status_code status;
5799         u16 buff_len;
5800         int i;
5801
5802         i40e_fill_default_direct_cmd_desc(&desc,
5803                                           i40e_aqc_opc_remove_cloud_filters);
5804
5805         buff_len = filter_count * sizeof(*filters);
5806         desc.datalen = CPU_TO_LE16(buff_len);
5807         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5808         cmd->num_filters = filter_count;
5809         cmd->seid = CPU_TO_LE16(seid);
5810         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5811
5812         /* adjust Geneve VNI for HW issue */
5813         for (i = 0; i < filter_count; i++) {
5814                 u16 tnl_type;
5815                 u32 ti;
5816
5817                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5818                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5819                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5820                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5821                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5822                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5823                 }
5824         }
5825
5826         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5827
5828         return status;
5829 }
5830
5831 /**
5832  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5833  * @hw: pointer to the hw struct
5834  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5835  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5836  *
5837  **/
5838 enum
5839 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5840         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5841         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5842 {
5843         struct i40e_aq_desc desc;
5844         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5845                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5846         enum i40e_status_code status = I40E_SUCCESS;
5847         int i = 0;
5848
5849         i40e_fill_default_direct_cmd_desc(&desc,
5850                                           i40e_aqc_opc_replace_cloud_filters);
5851
5852         desc.datalen = CPU_TO_LE16(32);
5853         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5854         cmd->old_filter_type = filters->old_filter_type;
5855         cmd->new_filter_type = filters->new_filter_type;
5856         cmd->valid_flags = filters->valid_flags;
5857         cmd->tr_bit = filters->tr_bit;
5858
5859         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5860                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5861
5862         /* for get cloud filters command */
5863         for (i = 0; i < 32; i += 4) {
5864                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5865                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5866                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5867                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5868         }
5869
5870         return status;
5871 }
5872
5873
5874 /**
5875  * i40e_aq_alternate_write
5876  * @hw: pointer to the hardware structure
5877  * @reg_addr0: address of first dword to be read
5878  * @reg_val0: value to be written under 'reg_addr0'
5879  * @reg_addr1: address of second dword to be read
5880  * @reg_val1: value to be written under 'reg_addr1'
5881  *
5882  * Write one or two dwords to alternate structure. Fields are indicated
5883  * by 'reg_addr0' and 'reg_addr1' register numbers.
5884  *
5885  **/
5886 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5887                                 u32 reg_addr0, u32 reg_val0,
5888                                 u32 reg_addr1, u32 reg_val1)
5889 {
5890         struct i40e_aq_desc desc;
5891         struct i40e_aqc_alternate_write *cmd_resp =
5892                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5893         enum i40e_status_code status;
5894
5895         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5896         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5897         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5898         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5899         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5900
5901         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5902
5903         return status;
5904 }
5905
5906 /**
5907  * i40e_aq_alternate_write_indirect
5908  * @hw: pointer to the hardware structure
5909  * @addr: address of a first register to be modified
5910  * @dw_count: number of alternate structure fields to write
5911  * @buffer: pointer to the command buffer
5912  *
5913  * Write 'dw_count' dwords from 'buffer' to alternate structure
5914  * starting at 'addr'.
5915  *
5916  **/
5917 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5918                                 u32 addr, u32 dw_count, void *buffer)
5919 {
5920         struct i40e_aq_desc desc;
5921         struct i40e_aqc_alternate_ind_write *cmd_resp =
5922                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5923         enum i40e_status_code status;
5924
5925         if (buffer == NULL)
5926                 return I40E_ERR_PARAM;
5927
5928         /* Indirect command */
5929         i40e_fill_default_direct_cmd_desc(&desc,
5930                                          i40e_aqc_opc_alternate_write_indirect);
5931
5932         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5933         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5934         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5935                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5936
5937         cmd_resp->address = CPU_TO_LE32(addr);
5938         cmd_resp->length = CPU_TO_LE32(dw_count);
5939
5940         status = i40e_asq_send_command(hw, &desc, buffer,
5941                                        I40E_LO_DWORD(4*dw_count), NULL);
5942
5943         return status;
5944 }
5945
5946 /**
5947  * i40e_aq_alternate_read
5948  * @hw: pointer to the hardware structure
5949  * @reg_addr0: address of first dword to be read
5950  * @reg_val0: pointer for data read from 'reg_addr0'
5951  * @reg_addr1: address of second dword to be read
5952  * @reg_val1: pointer for data read from 'reg_addr1'
5953  *
5954  * Read one or two dwords from alternate structure. Fields are indicated
5955  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5956  * is not passed then only register at 'reg_addr0' is read.
5957  *
5958  **/
5959 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5960                                 u32 reg_addr0, u32 *reg_val0,
5961                                 u32 reg_addr1, u32 *reg_val1)
5962 {
5963         struct i40e_aq_desc desc;
5964         struct i40e_aqc_alternate_write *cmd_resp =
5965                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5966         enum i40e_status_code status;
5967
5968         if (reg_val0 == NULL)
5969                 return I40E_ERR_PARAM;
5970
5971         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5972         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5973         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5974
5975         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5976
5977         if (status == I40E_SUCCESS) {
5978                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5979
5980                 if (reg_val1 != NULL)
5981                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5982         }
5983
5984         return status;
5985 }
5986
5987 /**
5988  * i40e_aq_alternate_read_indirect
5989  * @hw: pointer to the hardware structure
5990  * @addr: address of the alternate structure field
5991  * @dw_count: number of alternate structure fields to read
5992  * @buffer: pointer to the command buffer
5993  *
5994  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5995  * place them in 'buffer'. The buffer should be allocated by caller.
5996  *
5997  **/
5998 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5999                                 u32 addr, u32 dw_count, void *buffer)
6000 {
6001         struct i40e_aq_desc desc;
6002         struct i40e_aqc_alternate_ind_write *cmd_resp =
6003                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6004         enum i40e_status_code status;
6005
6006         if (buffer == NULL)
6007                 return I40E_ERR_PARAM;
6008
6009         /* Indirect command */
6010         i40e_fill_default_direct_cmd_desc(&desc,
6011                 i40e_aqc_opc_alternate_read_indirect);
6012
6013         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6014         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6015         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6016                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6017
6018         cmd_resp->address = CPU_TO_LE32(addr);
6019         cmd_resp->length = CPU_TO_LE32(dw_count);
6020
6021         status = i40e_asq_send_command(hw, &desc, buffer,
6022                                        I40E_LO_DWORD(4*dw_count), NULL);
6023
6024         return status;
6025 }
6026
6027 /**
6028  *  i40e_aq_alternate_clear
6029  *  @hw: pointer to the HW structure.
6030  *
6031  *  Clear the alternate structures of the port from which the function
6032  *  is called.
6033  *
6034  **/
6035 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6036 {
6037         struct i40e_aq_desc desc;
6038         enum i40e_status_code status;
6039
6040         i40e_fill_default_direct_cmd_desc(&desc,
6041                                           i40e_aqc_opc_alternate_clear_port);
6042
6043         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6044
6045         return status;
6046 }
6047
6048 /**
6049  *  i40e_aq_alternate_write_done
6050  *  @hw: pointer to the HW structure.
6051  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6052  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6053  *
6054  *  Indicates to the FW that alternate structures have been changed.
6055  *
6056  **/
6057 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6058                 u8 bios_mode, bool *reset_needed)
6059 {
6060         struct i40e_aq_desc desc;
6061         struct i40e_aqc_alternate_write_done *cmd =
6062                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6063         enum i40e_status_code status;
6064
6065         if (reset_needed == NULL)
6066                 return I40E_ERR_PARAM;
6067
6068         i40e_fill_default_direct_cmd_desc(&desc,
6069                                           i40e_aqc_opc_alternate_write_done);
6070
6071         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6072
6073         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6074         if (!status && reset_needed)
6075                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6076                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6077
6078         return status;
6079 }
6080
6081 /**
6082  *  i40e_aq_set_oem_mode
6083  *  @hw: pointer to the HW structure.
6084  *  @oem_mode: the OEM mode to be used
6085  *
6086  *  Sets the device to a specific operating mode. Currently the only supported
6087  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6088  *
6089  **/
6090 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6091                 u8 oem_mode)
6092 {
6093         struct i40e_aq_desc desc;
6094         struct i40e_aqc_alternate_write_done *cmd =
6095                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6096         enum i40e_status_code status;
6097
6098         i40e_fill_default_direct_cmd_desc(&desc,
6099                                           i40e_aqc_opc_alternate_set_mode);
6100
6101         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6102
6103         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6104
6105         return status;
6106 }
6107
6108 /**
6109  * i40e_aq_resume_port_tx
6110  * @hw: pointer to the hardware structure
6111  * @cmd_details: pointer to command details structure or NULL
6112  *
6113  * Resume port's Tx traffic
6114  **/
6115 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6116                                 struct i40e_asq_cmd_details *cmd_details)
6117 {
6118         struct i40e_aq_desc desc;
6119         enum i40e_status_code status;
6120
6121         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6122
6123         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6124
6125         return status;
6126 }
6127
6128 /**
6129  * i40e_set_pci_config_data - store PCI bus info
6130  * @hw: pointer to hardware structure
6131  * @link_status: the link status word from PCI config space
6132  *
6133  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6134  **/
6135 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6136 {
6137         hw->bus.type = i40e_bus_type_pci_express;
6138
6139         switch (link_status & I40E_PCI_LINK_WIDTH) {
6140         case I40E_PCI_LINK_WIDTH_1:
6141                 hw->bus.width = i40e_bus_width_pcie_x1;
6142                 break;
6143         case I40E_PCI_LINK_WIDTH_2:
6144                 hw->bus.width = i40e_bus_width_pcie_x2;
6145                 break;
6146         case I40E_PCI_LINK_WIDTH_4:
6147                 hw->bus.width = i40e_bus_width_pcie_x4;
6148                 break;
6149         case I40E_PCI_LINK_WIDTH_8:
6150                 hw->bus.width = i40e_bus_width_pcie_x8;
6151                 break;
6152         default:
6153                 hw->bus.width = i40e_bus_width_unknown;
6154                 break;
6155         }
6156
6157         switch (link_status & I40E_PCI_LINK_SPEED) {
6158         case I40E_PCI_LINK_SPEED_2500:
6159                 hw->bus.speed = i40e_bus_speed_2500;
6160                 break;
6161         case I40E_PCI_LINK_SPEED_5000:
6162                 hw->bus.speed = i40e_bus_speed_5000;
6163                 break;
6164         case I40E_PCI_LINK_SPEED_8000:
6165                 hw->bus.speed = i40e_bus_speed_8000;
6166                 break;
6167         default:
6168                 hw->bus.speed = i40e_bus_speed_unknown;
6169                 break;
6170         }
6171 }
6172
6173 /**
6174  * i40e_aq_debug_dump
6175  * @hw: pointer to the hardware structure
6176  * @cluster_id: specific cluster to dump
6177  * @table_id: table id within cluster
6178  * @start_index: index of line in the block to read
6179  * @buff_size: dump buffer size
6180  * @buff: dump buffer
6181  * @ret_buff_size: actual buffer size returned
6182  * @ret_next_table: next block to read
6183  * @ret_next_index: next index to read
6184  *
6185  * Dump internal FW/HW data for debug purposes.
6186  *
6187  **/
6188 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6189                                 u8 table_id, u32 start_index, u16 buff_size,
6190                                 void *buff, u16 *ret_buff_size,
6191                                 u8 *ret_next_table, u32 *ret_next_index,
6192                                 struct i40e_asq_cmd_details *cmd_details)
6193 {
6194         struct i40e_aq_desc desc;
6195         struct i40e_aqc_debug_dump_internals *cmd =
6196                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6197         struct i40e_aqc_debug_dump_internals *resp =
6198                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6199         enum i40e_status_code status;
6200
6201         if (buff_size == 0 || !buff)
6202                 return I40E_ERR_PARAM;
6203
6204         i40e_fill_default_direct_cmd_desc(&desc,
6205                                           i40e_aqc_opc_debug_dump_internals);
6206         /* Indirect Command */
6207         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6208         if (buff_size > I40E_AQ_LARGE_BUF)
6209                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6210
6211         cmd->cluster_id = cluster_id;
6212         cmd->table_id = table_id;
6213         cmd->idx = CPU_TO_LE32(start_index);
6214
6215         desc.datalen = CPU_TO_LE16(buff_size);
6216
6217         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6218         if (!status) {
6219                 if (ret_buff_size != NULL)
6220                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6221                 if (ret_next_table != NULL)
6222                         *ret_next_table = resp->table_id;
6223                 if (ret_next_index != NULL)
6224                         *ret_next_index = LE32_TO_CPU(resp->idx);
6225         }
6226
6227         return status;
6228 }
6229
6230 /**
6231  * i40e_read_bw_from_alt_ram
6232  * @hw: pointer to the hardware structure
6233  * @max_bw: pointer for max_bw read
6234  * @min_bw: pointer for min_bw read
6235  * @min_valid: pointer for bool that is true if min_bw is a valid value
6236  * @max_valid: pointer for bool that is true if max_bw is a valid value
6237  *
6238  * Read bw from the alternate ram for the given pf
6239  **/
6240 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6241                                         u32 *max_bw, u32 *min_bw,
6242                                         bool *min_valid, bool *max_valid)
6243 {
6244         enum i40e_status_code status;
6245         u32 max_bw_addr, min_bw_addr;
6246
6247         /* Calculate the address of the min/max bw registers */
6248         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6249                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6250                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6251         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6252                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6253                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6254
6255         /* Read the bandwidths from alt ram */
6256         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6257                                         min_bw_addr, min_bw);
6258
6259         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6260                 *min_valid = true;
6261         else
6262                 *min_valid = false;
6263
6264         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6265                 *max_valid = true;
6266         else
6267                 *max_valid = false;
6268
6269         return status;
6270 }
6271
6272 /**
6273  * i40e_aq_configure_partition_bw
6274  * @hw: pointer to the hardware structure
6275  * @bw_data: Buffer holding valid pfs and bw limits
6276  * @cmd_details: pointer to command details
6277  *
6278  * Configure partitions guaranteed/max bw
6279  **/
6280 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6281                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6282                         struct i40e_asq_cmd_details *cmd_details)
6283 {
6284         enum i40e_status_code status;
6285         struct i40e_aq_desc desc;
6286         u16 bwd_size = sizeof(*bw_data);
6287
6288         i40e_fill_default_direct_cmd_desc(&desc,
6289                                 i40e_aqc_opc_configure_partition_bw);
6290
6291         /* Indirect command */
6292         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6293         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6294
6295         desc.datalen = CPU_TO_LE16(bwd_size);
6296
6297         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6298
6299         return status;
6300 }
6301
6302 /**
6303  * i40e_read_phy_register_clause22
6304  * @hw: pointer to the HW structure
6305  * @reg: register address in the page
6306  * @phy_adr: PHY address on MDIO interface
6307  * @value: PHY register value
6308  *
6309  * Reads specified PHY register value
6310  **/
6311 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6312                                         u16 reg, u8 phy_addr, u16 *value)
6313 {
6314         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6315         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6316         u32 command = 0;
6317         u16 retry = 1000;
6318
6319         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6320                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6321                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6322                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6323                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6324         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6325         do {
6326                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6327                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6328                         status = I40E_SUCCESS;
6329                         break;
6330                 }
6331                 i40e_usec_delay(10);
6332                 retry--;
6333         } while (retry);
6334
6335         if (status) {
6336                 i40e_debug(hw, I40E_DEBUG_PHY,
6337                            "PHY: Can't write command to external PHY.\n");
6338         } else {
6339                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6340                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6341                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6342         }
6343
6344         return status;
6345 }
6346
6347 /**
6348  * i40e_write_phy_register_clause22
6349  * @hw: pointer to the HW structure
6350  * @reg: register address in the page
6351  * @phy_adr: PHY address on MDIO interface
6352  * @value: PHY register value
6353  *
6354  * Writes specified PHY register value
6355  **/
6356 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6357                                         u16 reg, u8 phy_addr, u16 value)
6358 {
6359         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6360         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6361         u32 command  = 0;
6362         u16 retry = 1000;
6363
6364         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6365         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6366
6367         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6368                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6369                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6370                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6371                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6372
6373         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6374         do {
6375                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6376                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6377                         status = I40E_SUCCESS;
6378                         break;
6379                 }
6380                 i40e_usec_delay(10);
6381                 retry--;
6382         } while (retry);
6383
6384         return status;
6385 }
6386
6387 /**
6388  * i40e_read_phy_register_clause45
6389  * @hw: pointer to the HW structure
6390  * @page: registers page number
6391  * @reg: register address in the page
6392  * @phy_adr: PHY address on MDIO interface
6393  * @value: PHY register value
6394  *
6395  * Reads specified PHY register value
6396  **/
6397 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6398                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6399 {
6400         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6401         u32 command  = 0;
6402         u16 retry = 1000;
6403         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6404
6405         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6406                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6407                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6408                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6409                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6410                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6411                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6412         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6413         do {
6414                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6415                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6416                         status = I40E_SUCCESS;
6417                         break;
6418                 }
6419                 i40e_usec_delay(10);
6420                 retry--;
6421         } while (retry);
6422
6423         if (status) {
6424                 i40e_debug(hw, I40E_DEBUG_PHY,
6425                            "PHY: Can't write command to external PHY.\n");
6426                 goto phy_read_end;
6427         }
6428
6429         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6430                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6431                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6432                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6433                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6434                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6435         status = I40E_ERR_TIMEOUT;
6436         retry = 1000;
6437         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6438         do {
6439                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6440                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6441                         status = I40E_SUCCESS;
6442                         break;
6443                 }
6444                 i40e_usec_delay(10);
6445                 retry--;
6446         } while (retry);
6447
6448         if (!status) {
6449                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6450                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6451                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6452         } else {
6453                 i40e_debug(hw, I40E_DEBUG_PHY,
6454                            "PHY: Can't read register value from external PHY.\n");
6455         }
6456
6457 phy_read_end:
6458         return status;
6459 }
6460
6461 /**
6462  * i40e_write_phy_register_clause45
6463  * @hw: pointer to the HW structure
6464  * @page: registers page number
6465  * @reg: register address in the page
6466  * @phy_adr: PHY address on MDIO interface
6467  * @value: PHY register value
6468  *
6469  * Writes value to specified PHY register
6470  **/
6471 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6472                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6473 {
6474         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6475         u32 command  = 0;
6476         u16 retry = 1000;
6477         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6478
6479         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6480                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6481                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6482                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6483                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6484                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6485                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6486         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6487         do {
6488                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6489                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6490                         status = I40E_SUCCESS;
6491                         break;
6492                 }
6493                 i40e_usec_delay(10);
6494                 retry--;
6495         } while (retry);
6496         if (status) {
6497                 i40e_debug(hw, I40E_DEBUG_PHY,
6498                            "PHY: Can't write command to external PHY.\n");
6499                 goto phy_write_end;
6500         }
6501
6502         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6503         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6504
6505         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6506                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6507                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6508                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6509                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6510                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6511         status = I40E_ERR_TIMEOUT;
6512         retry = 1000;
6513         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6514         do {
6515                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6516                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6517                         status = I40E_SUCCESS;
6518                         break;
6519                 }
6520                 i40e_usec_delay(10);
6521                 retry--;
6522         } while (retry);
6523
6524 phy_write_end:
6525         return status;
6526 }
6527
6528 /**
6529  * i40e_write_phy_register
6530  * @hw: pointer to the HW structure
6531  * @page: registers page number
6532  * @reg: register address in the page
6533  * @phy_adr: PHY address on MDIO interface
6534  * @value: PHY register value
6535  *
6536  * Writes value to specified PHY register
6537  **/
6538 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6539                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6540 {
6541         enum i40e_status_code status;
6542
6543         switch (hw->device_id) {
6544         case I40E_DEV_ID_1G_BASE_T_X722:
6545                 status = i40e_write_phy_register_clause22(hw,
6546                         reg, phy_addr, value);
6547                 break;
6548         case I40E_DEV_ID_10G_BASE_T:
6549         case I40E_DEV_ID_10G_BASE_T4:
6550         case I40E_DEV_ID_10G_BASE_T_X722:
6551         case I40E_DEV_ID_25G_B:
6552         case I40E_DEV_ID_25G_SFP28:
6553                 status = i40e_write_phy_register_clause45(hw,
6554                         page, reg, phy_addr, value);
6555                 break;
6556         default:
6557                 status = I40E_ERR_UNKNOWN_PHY;
6558                 break;
6559         }
6560
6561         return status;
6562 }
6563
6564 /**
6565  * i40e_read_phy_register
6566  * @hw: pointer to the HW structure
6567  * @page: registers page number
6568  * @reg: register address in the page
6569  * @phy_adr: PHY address on MDIO interface
6570  * @value: PHY register value
6571  *
6572  * Reads specified PHY register value
6573  **/
6574 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6575                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6576 {
6577         enum i40e_status_code status;
6578
6579         switch (hw->device_id) {
6580         case I40E_DEV_ID_1G_BASE_T_X722:
6581                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6582                                                          value);
6583                 break;
6584         case I40E_DEV_ID_10G_BASE_T:
6585         case I40E_DEV_ID_10G_BASE_T4:
6586         case I40E_DEV_ID_10G_BASE_T_X722:
6587         case I40E_DEV_ID_25G_B:
6588         case I40E_DEV_ID_25G_SFP28:
6589                 status = i40e_read_phy_register_clause45(hw, page, reg,
6590                                                          phy_addr, value);
6591                 break;
6592         default:
6593                 status = I40E_ERR_UNKNOWN_PHY;
6594                 break;
6595         }
6596
6597         return status;
6598 }
6599
6600 /**
6601  * i40e_get_phy_address
6602  * @hw: pointer to the HW structure
6603  * @dev_num: PHY port num that address we want
6604  * @phy_addr: Returned PHY address
6605  *
6606  * Gets PHY address for current port
6607  **/
6608 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6609 {
6610         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6611         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6612
6613         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6614 }
6615
6616 /**
6617  * i40e_blink_phy_led
6618  * @hw: pointer to the HW structure
6619  * @time: time how long led will blinks in secs
6620  * @interval: gap between LED on and off in msecs
6621  *
6622  * Blinks PHY link LED
6623  **/
6624 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6625                                               u32 time, u32 interval)
6626 {
6627         enum i40e_status_code status = I40E_SUCCESS;
6628         u32 i;
6629         u16 led_ctl = 0;
6630         u16 gpio_led_port;
6631         u16 led_reg;
6632         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6633         u8 phy_addr = 0;
6634         u8 port_num;
6635
6636         i = rd32(hw, I40E_PFGEN_PORTNUM);
6637         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6638         phy_addr = i40e_get_phy_address(hw, port_num);
6639
6640         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6641              led_addr++) {
6642                 status = i40e_read_phy_register_clause45(hw,
6643                                                          I40E_PHY_COM_REG_PAGE,
6644                                                          led_addr, phy_addr,
6645                                                          &led_reg);
6646                 if (status)
6647                         goto phy_blinking_end;
6648                 led_ctl = led_reg;
6649                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6650                         led_reg = 0;
6651                         status = i40e_write_phy_register_clause45(hw,
6652                                                          I40E_PHY_COM_REG_PAGE,
6653                                                          led_addr, phy_addr,
6654                                                          led_reg);
6655                         if (status)
6656                                 goto phy_blinking_end;
6657                         break;
6658                 }
6659         }
6660
6661         if (time > 0 && interval > 0) {
6662                 for (i = 0; i < time * 1000; i += interval) {
6663                         status = i40e_read_phy_register_clause45(hw,
6664                                                 I40E_PHY_COM_REG_PAGE,
6665                                                 led_addr, phy_addr, &led_reg);
6666                         if (status)
6667                                 goto restore_config;
6668                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6669                                 led_reg = 0;
6670                         else
6671                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6672                         status = i40e_write_phy_register_clause45(hw,
6673                                                 I40E_PHY_COM_REG_PAGE,
6674                                                 led_addr, phy_addr, led_reg);
6675                         if (status)
6676                                 goto restore_config;
6677                         i40e_msec_delay(interval);
6678                 }
6679         }
6680
6681 restore_config:
6682         status = i40e_write_phy_register_clause45(hw,
6683                                                   I40E_PHY_COM_REG_PAGE,
6684                                                   led_addr, phy_addr, led_ctl);
6685
6686 phy_blinking_end:
6687         return status;
6688 }
6689
6690 /**
6691  * i40e_led_get_reg - read LED register
6692  * @hw: pointer to the HW structure
6693  * @led_addr: LED register address
6694  * @reg_val: read register value
6695  **/
6696 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6697                                               u32 *reg_val)
6698 {
6699         enum i40e_status_code status;
6700         u8 phy_addr = 0;
6701
6702         *reg_val = 0;
6703         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6704                 status = i40e_aq_get_phy_register(hw,
6705                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6706                                                 I40E_PHY_COM_REG_PAGE,
6707                                                 I40E_PHY_LED_PROV_REG_1,
6708                                                 reg_val, NULL);
6709         } else {
6710                 phy_addr = i40e_get_phy_address(hw, hw->port);
6711                 status = i40e_read_phy_register_clause45(hw,
6712                                                          I40E_PHY_COM_REG_PAGE,
6713                                                          led_addr, phy_addr,
6714                                                          (u16 *)reg_val);
6715         }
6716         return status;
6717 }
6718
6719 /**
6720  * i40e_led_set_reg - write LED register
6721  * @hw: pointer to the HW structure
6722  * @led_addr: LED register address
6723  * @reg_val: register value to write
6724  **/
6725 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6726                                               u32 reg_val)
6727 {
6728         enum i40e_status_code status;
6729         u8 phy_addr = 0;
6730
6731         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6732                 status = i40e_aq_set_phy_register(hw,
6733                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6734                                                 I40E_PHY_COM_REG_PAGE,
6735                                                 I40E_PHY_LED_PROV_REG_1,
6736                                                 reg_val, NULL);
6737         } else {
6738                 phy_addr = i40e_get_phy_address(hw, hw->port);
6739                 status = i40e_write_phy_register_clause45(hw,
6740                                                           I40E_PHY_COM_REG_PAGE,
6741                                                           led_addr, phy_addr,
6742                                                           (u16)reg_val);
6743         }
6744
6745         return status;
6746 }
6747
6748 /**
6749  * i40e_led_get_phy - return current on/off mode
6750  * @hw: pointer to the hw struct
6751  * @led_addr: address of led register to use
6752  * @val: original value of register to use
6753  *
6754  **/
6755 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6756                                        u16 *val)
6757 {
6758         enum i40e_status_code status = I40E_SUCCESS;
6759         u16 gpio_led_port;
6760         u32 reg_val_aq;
6761         u16 temp_addr;
6762         u8 phy_addr = 0;
6763         u16 reg_val;
6764
6765         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6766                 status = i40e_aq_get_phy_register(hw,
6767                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6768                                                 I40E_PHY_COM_REG_PAGE,
6769                                                 I40E_PHY_LED_PROV_REG_1,
6770                                                 &reg_val_aq, NULL);
6771                 if (status == I40E_SUCCESS)
6772                         *val = (u16)reg_val_aq;
6773                 return status;
6774         }
6775         temp_addr = I40E_PHY_LED_PROV_REG_1;
6776         phy_addr = i40e_get_phy_address(hw, hw->port);
6777         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6778              temp_addr++) {
6779                 status = i40e_read_phy_register_clause45(hw,
6780                                                          I40E_PHY_COM_REG_PAGE,
6781                                                          temp_addr, phy_addr,
6782                                                          &reg_val);
6783                 if (status)
6784                         return status;
6785                 *val = reg_val;
6786                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6787                         *led_addr = temp_addr;
6788                         break;
6789                 }
6790         }
6791         return status;
6792 }
6793
6794 /**
6795  * i40e_led_set_phy
6796  * @hw: pointer to the HW structure
6797  * @on: true or false
6798  * @mode: original val plus bit for set or ignore
6799  * Set led's on or off when controlled by the PHY
6800  *
6801  **/
6802 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6803                                        u16 led_addr, u32 mode)
6804 {
6805         enum i40e_status_code status = I40E_SUCCESS;
6806         u32 led_ctl = 0;
6807         u32 led_reg = 0;
6808
6809         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6810         if (status)
6811                 return status;
6812         led_ctl = led_reg;
6813         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6814                 led_reg = 0;
6815                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6816                 if (status)
6817                         return status;
6818         }
6819         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6820         if (status)
6821                 goto restore_config;
6822         if (on)
6823                 led_reg = I40E_PHY_LED_MANUAL_ON;
6824         else
6825                 led_reg = 0;
6826         status = i40e_led_set_reg(hw, led_addr, led_reg);
6827         if (status)
6828                 goto restore_config;
6829         if (mode & I40E_PHY_LED_MODE_ORIG) {
6830                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6831                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6832         }
6833         return status;
6834
6835 restore_config:
6836         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6837         return status;
6838 }
6839 #endif /* PF_DRIVER */
6840
6841 /**
6842  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6843  * @hw: pointer to the hw struct
6844  * @reg_addr: register address
6845  * @reg_val: ptr to register value
6846  * @cmd_details: pointer to command details structure or NULL
6847  *
6848  * Use the firmware to read the Rx control register,
6849  * especially useful if the Rx unit is under heavy pressure
6850  **/
6851 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6852                                 u32 reg_addr, u32 *reg_val,
6853                                 struct i40e_asq_cmd_details *cmd_details)
6854 {
6855         struct i40e_aq_desc desc;
6856         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6857                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6858         enum i40e_status_code status;
6859
6860         if (reg_val == NULL)
6861                 return I40E_ERR_PARAM;
6862
6863         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6864
6865         cmd_resp->address = CPU_TO_LE32(reg_addr);
6866
6867         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6868
6869         if (status == I40E_SUCCESS)
6870                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6871
6872         return status;
6873 }
6874
6875 /**
6876  * i40e_read_rx_ctl - read from an Rx control register
6877  * @hw: pointer to the hw struct
6878  * @reg_addr: register address
6879  **/
6880 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6881 {
6882         enum i40e_status_code status = I40E_SUCCESS;
6883         bool use_register;
6884         int retry = 5;
6885         u32 val = 0;
6886
6887         use_register = (((hw->aq.api_maj_ver == 1) &&
6888                         (hw->aq.api_min_ver < 5)) ||
6889                         (hw->mac.type == I40E_MAC_X722));
6890         if (!use_register) {
6891 do_retry:
6892                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6893                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6894                         i40e_msec_delay(1);
6895                         retry--;
6896                         goto do_retry;
6897                 }
6898         }
6899
6900         /* if the AQ access failed, try the old-fashioned way */
6901         if (status || use_register)
6902                 val = rd32(hw, reg_addr);
6903
6904         return val;
6905 }
6906
6907 /**
6908  * i40e_aq_rx_ctl_write_register
6909  * @hw: pointer to the hw struct
6910  * @reg_addr: register address
6911  * @reg_val: register value
6912  * @cmd_details: pointer to command details structure or NULL
6913  *
6914  * Use the firmware to write to an Rx control register,
6915  * especially useful if the Rx unit is under heavy pressure
6916  **/
6917 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6918                                 u32 reg_addr, u32 reg_val,
6919                                 struct i40e_asq_cmd_details *cmd_details)
6920 {
6921         struct i40e_aq_desc desc;
6922         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6923                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6924         enum i40e_status_code status;
6925
6926         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6927
6928         cmd->address = CPU_TO_LE32(reg_addr);
6929         cmd->value = CPU_TO_LE32(reg_val);
6930
6931         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6932
6933         return status;
6934 }
6935
6936 /**
6937  * i40e_write_rx_ctl - write to an Rx control register
6938  * @hw: pointer to the hw struct
6939  * @reg_addr: register address
6940  * @reg_val: register value
6941  **/
6942 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6943 {
6944         enum i40e_status_code status = I40E_SUCCESS;
6945         bool use_register;
6946         int retry = 5;
6947
6948         use_register = (((hw->aq.api_maj_ver == 1) &&
6949                         (hw->aq.api_min_ver < 5)) ||
6950                         (hw->mac.type == I40E_MAC_X722));
6951         if (!use_register) {
6952 do_retry:
6953                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6954                                                        reg_val, NULL);
6955                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6956                         i40e_msec_delay(1);
6957                         retry--;
6958                         goto do_retry;
6959                 }
6960         }
6961
6962         /* if the AQ access failed, try the old-fashioned way */
6963         if (status || use_register)
6964                 wr32(hw, reg_addr, reg_val);
6965 }
6966
6967 /**
6968  * i40e_aq_set_phy_register
6969  * @hw: pointer to the hw struct
6970  * @phy_select: select which phy should be accessed
6971  * @dev_addr: PHY device address
6972  * @reg_addr: PHY register address
6973  * @reg_val: new register value
6974  * @cmd_details: pointer to command details structure or NULL
6975  *
6976  * Write the external PHY register.
6977  **/
6978 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
6979                                 u8 phy_select, u8 dev_addr,
6980                                 u32 reg_addr, u32 reg_val,
6981                                 struct i40e_asq_cmd_details *cmd_details)
6982 {
6983         struct i40e_aq_desc desc;
6984         struct i40e_aqc_phy_register_access *cmd =
6985                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6986         enum i40e_status_code status;
6987
6988         i40e_fill_default_direct_cmd_desc(&desc,
6989                                           i40e_aqc_opc_set_phy_register);
6990
6991         cmd->phy_interface = phy_select;
6992         cmd->dev_addres = dev_addr;
6993         cmd->reg_address = CPU_TO_LE32(reg_addr);
6994         cmd->reg_value = CPU_TO_LE32(reg_val);
6995
6996         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6997
6998         return status;
6999 }
7000
7001 /**
7002  * i40e_aq_get_phy_register
7003  * @hw: pointer to the hw struct
7004  * @phy_select: select which phy should be accessed
7005  * @dev_addr: PHY device address
7006  * @reg_addr: PHY register address
7007  * @reg_val: read register value
7008  * @cmd_details: pointer to command details structure or NULL
7009  *
7010  * Read the external PHY register.
7011  **/
7012 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7013                                 u8 phy_select, u8 dev_addr,
7014                                 u32 reg_addr, u32 *reg_val,
7015                                 struct i40e_asq_cmd_details *cmd_details)
7016 {
7017         struct i40e_aq_desc desc;
7018         struct i40e_aqc_phy_register_access *cmd =
7019                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7020         enum i40e_status_code status;
7021
7022         i40e_fill_default_direct_cmd_desc(&desc,
7023                                           i40e_aqc_opc_get_phy_register);
7024
7025         cmd->phy_interface = phy_select;
7026         cmd->dev_addres = dev_addr;
7027         cmd->reg_address = CPU_TO_LE32(reg_addr);
7028
7029         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7030         if (!status)
7031                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7032
7033         return status;
7034 }
7035
7036 #ifdef VF_DRIVER
7037
7038 /**
7039  * i40e_aq_send_msg_to_pf
7040  * @hw: pointer to the hardware structure
7041  * @v_opcode: opcodes for VF-PF communication
7042  * @v_retval: return error code
7043  * @msg: pointer to the msg buffer
7044  * @msglen: msg length
7045  * @cmd_details: pointer to command details
7046  *
7047  * Send message to PF driver using admin queue. By default, this message
7048  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7049  * completion before returning.
7050  **/
7051 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7052                                 enum virtchnl_ops v_opcode,
7053                                 enum i40e_status_code v_retval,
7054                                 u8 *msg, u16 msglen,
7055                                 struct i40e_asq_cmd_details *cmd_details)
7056 {
7057         struct i40e_aq_desc desc;
7058         struct i40e_asq_cmd_details details;
7059         enum i40e_status_code status;
7060
7061         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7062         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7063         desc.cookie_high = CPU_TO_LE32(v_opcode);
7064         desc.cookie_low = CPU_TO_LE32(v_retval);
7065         if (msglen) {
7066                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7067                                                 | I40E_AQ_FLAG_RD));
7068                 if (msglen > I40E_AQ_LARGE_BUF)
7069                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7070                 desc.datalen = CPU_TO_LE16(msglen);
7071         }
7072         if (!cmd_details) {
7073                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7074                 details.async = true;
7075                 cmd_details = &details;
7076         }
7077         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7078                                        msglen, cmd_details);
7079         return status;
7080 }
7081
7082 /**
7083  * i40e_vf_parse_hw_config
7084  * @hw: pointer to the hardware structure
7085  * @msg: pointer to the virtual channel VF resource structure
7086  *
7087  * Given a VF resource message from the PF, populate the hw struct
7088  * with appropriate information.
7089  **/
7090 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7091                              struct virtchnl_vf_resource *msg)
7092 {
7093         struct virtchnl_vsi_resource *vsi_res;
7094         int i;
7095
7096         vsi_res = &msg->vsi_res[0];
7097
7098         hw->dev_caps.num_vsis = msg->num_vsis;
7099         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7100         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7101         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7102         hw->dev_caps.dcb = msg->vf_offload_flags &
7103                            VIRTCHNL_VF_OFFLOAD_L2;
7104         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7105                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7106         for (i = 0; i < msg->num_vsis; i++) {
7107                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7108                         i40e_memcpy(hw->mac.perm_addr,
7109                                     vsi_res->default_mac_addr,
7110                                     ETH_ALEN,
7111                                     I40E_NONDMA_TO_NONDMA);
7112                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7113                                     ETH_ALEN,
7114                                     I40E_NONDMA_TO_NONDMA);
7115                 }
7116                 vsi_res++;
7117         }
7118 }
7119
7120 /**
7121  * i40e_vf_reset
7122  * @hw: pointer to the hardware structure
7123  *
7124  * Send a VF_RESET message to the PF. Does not wait for response from PF
7125  * as none will be forthcoming. Immediately after calling this function,
7126  * the admin queue should be shut down and (optionally) reinitialized.
7127  **/
7128 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7129 {
7130         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7131                                       I40E_SUCCESS, NULL, 0, NULL);
7132 }
7133 #endif /* VF_DRIVER */
7134
7135 /**
7136  * i40e_aq_set_arp_proxy_config
7137  * @hw: pointer to the HW structure
7138  * @proxy_config - pointer to proxy config command table struct
7139  * @cmd_details: pointer to command details
7140  *
7141  * Set ARP offload parameters from pre-populated
7142  * i40e_aqc_arp_proxy_data struct
7143  **/
7144 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7145                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7146                                 struct i40e_asq_cmd_details *cmd_details)
7147 {
7148         struct i40e_aq_desc desc;
7149         enum i40e_status_code status;
7150
7151         if (!proxy_config)
7152                 return I40E_ERR_PARAM;
7153
7154         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7155
7156         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7157         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7158         desc.params.external.addr_high =
7159                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7160         desc.params.external.addr_low =
7161                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7162         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7163
7164         status = i40e_asq_send_command(hw, &desc, proxy_config,
7165                                        sizeof(struct i40e_aqc_arp_proxy_data),
7166                                        cmd_details);
7167
7168         return status;
7169 }
7170
7171 /**
7172  * i40e_aq_opc_set_ns_proxy_table_entry
7173  * @hw: pointer to the HW structure
7174  * @ns_proxy_table_entry: pointer to NS table entry command struct
7175  * @cmd_details: pointer to command details
7176  *
7177  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7178  * from pre-populated i40e_aqc_ns_proxy_data struct
7179  **/
7180 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7181                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7182                         struct i40e_asq_cmd_details *cmd_details)
7183 {
7184         struct i40e_aq_desc desc;
7185         enum i40e_status_code status;
7186
7187         if (!ns_proxy_table_entry)
7188                 return I40E_ERR_PARAM;
7189
7190         i40e_fill_default_direct_cmd_desc(&desc,
7191                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7192
7193         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7194         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7195         desc.params.external.addr_high =
7196                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7197         desc.params.external.addr_low =
7198                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7199         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7200
7201         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7202                                        sizeof(struct i40e_aqc_ns_proxy_data),
7203                                        cmd_details);
7204
7205         return status;
7206 }
7207
7208 /**
7209  * i40e_aq_set_clear_wol_filter
7210  * @hw: pointer to the hw struct
7211  * @filter_index: index of filter to modify (0-7)
7212  * @filter: buffer containing filter to be set
7213  * @set_filter: true to set filter, false to clear filter
7214  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7215  *              if false, pass through packets may cause wake-up
7216  * @filter_valid: true if filter action is valid
7217  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7218  * @cmd_details: pointer to command details structure or NULL
7219  *
7220  * Set or clear WoL filter for port attached to the PF
7221  **/
7222 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7223                                 u8 filter_index,
7224                                 struct i40e_aqc_set_wol_filter_data *filter,
7225                                 bool set_filter, bool no_wol_tco,
7226                                 bool filter_valid, bool no_wol_tco_valid,
7227                                 struct i40e_asq_cmd_details *cmd_details)
7228 {
7229         struct i40e_aq_desc desc;
7230         struct i40e_aqc_set_wol_filter *cmd =
7231                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7232         enum i40e_status_code status;
7233         u16 cmd_flags = 0;
7234         u16 valid_flags = 0;
7235         u16 buff_len = 0;
7236
7237         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7238
7239         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7240                 return  I40E_ERR_PARAM;
7241         cmd->filter_index = CPU_TO_LE16(filter_index);
7242
7243         if (set_filter) {
7244                 if (!filter)
7245                         return  I40E_ERR_PARAM;
7246
7247                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7248                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7249         }
7250
7251         if (no_wol_tco)
7252                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7253         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7254
7255         if (filter_valid)
7256                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7257         if (no_wol_tco_valid)
7258                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7259         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7260
7261         buff_len = sizeof(*filter);
7262         desc.datalen = CPU_TO_LE16(buff_len);
7263
7264         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7265         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7266
7267         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7268         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7269
7270         status = i40e_asq_send_command(hw, &desc, filter,
7271                                        buff_len, cmd_details);
7272
7273         return status;
7274 }
7275
7276 /**
7277  * i40e_aq_get_wake_event_reason
7278  * @hw: pointer to the hw struct
7279  * @wake_reason: return value, index of matching filter
7280  * @cmd_details: pointer to command details structure or NULL
7281  *
7282  * Get information for the reason of a Wake Up event
7283  **/
7284 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7285                                 u16 *wake_reason,
7286                                 struct i40e_asq_cmd_details *cmd_details)
7287 {
7288         struct i40e_aq_desc desc;
7289         struct i40e_aqc_get_wake_reason_completion *resp =
7290                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7291         enum i40e_status_code status;
7292
7293         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7294
7295         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7296
7297         if (status == I40E_SUCCESS)
7298                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7299
7300         return status;
7301 }
7302
7303 /**
7304 * i40e_aq_clear_all_wol_filters
7305 * @hw: pointer to the hw struct
7306 * @cmd_details: pointer to command details structure or NULL
7307 *
7308 * Get information for the reason of a Wake Up event
7309 **/
7310 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7311         struct i40e_asq_cmd_details *cmd_details)
7312 {
7313         struct i40e_aq_desc desc;
7314         enum i40e_status_code status;
7315
7316         i40e_fill_default_direct_cmd_desc(&desc,
7317                                           i40e_aqc_opc_clear_all_wol_filters);
7318
7319         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7320
7321         return status;
7322 }
7323
7324
7325 /**
7326  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7327  * @hw: pointer to the hw struct
7328  * @buff: command buffer (size in bytes = buff_size)
7329  * @buff_size: buffer size in bytes
7330  * @track_id: package tracking id
7331  * @error_offset: returns error offset
7332  * @error_info: returns error information
7333  * @cmd_details: pointer to command details structure or NULL
7334  **/
7335 enum
7336 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7337                                    u16 buff_size, u32 track_id,
7338                                    u32 *error_offset, u32 *error_info,
7339                                    struct i40e_asq_cmd_details *cmd_details)
7340 {
7341         struct i40e_aq_desc desc;
7342         struct i40e_aqc_write_personalization_profile *cmd =
7343                 (struct i40e_aqc_write_personalization_profile *)
7344                 &desc.params.raw;
7345         struct i40e_aqc_write_ddp_resp *resp;
7346         enum i40e_status_code status;
7347
7348         i40e_fill_default_direct_cmd_desc(&desc,
7349                                   i40e_aqc_opc_write_personalization_profile);
7350
7351         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7352         if (buff_size > I40E_AQ_LARGE_BUF)
7353                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7354
7355         desc.datalen = CPU_TO_LE16(buff_size);
7356
7357         cmd->profile_track_id = CPU_TO_LE32(track_id);
7358
7359         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7360         if (!status) {
7361                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7362                 if (error_offset)
7363                         *error_offset = LE32_TO_CPU(resp->error_offset);
7364                 if (error_info)
7365                         *error_info = LE32_TO_CPU(resp->error_info);
7366         }
7367
7368         return status;
7369 }
7370
7371 /**
7372  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7373  * @hw: pointer to the hw struct
7374  * @buff: command buffer (size in bytes = buff_size)
7375  * @buff_size: buffer size in bytes
7376  * @cmd_details: pointer to command details structure or NULL
7377  **/
7378 enum
7379 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7380                                       u16 buff_size, u8 flags,
7381                                       struct i40e_asq_cmd_details *cmd_details)
7382 {
7383         struct i40e_aq_desc desc;
7384         struct i40e_aqc_get_applied_profiles *cmd =
7385                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7386         enum i40e_status_code status;
7387
7388         i40e_fill_default_direct_cmd_desc(&desc,
7389                           i40e_aqc_opc_get_personalization_profile_list);
7390
7391         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7392         if (buff_size > I40E_AQ_LARGE_BUF)
7393                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7394         desc.datalen = CPU_TO_LE16(buff_size);
7395
7396         cmd->flags = flags;
7397
7398         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7399
7400         return status;
7401 }
7402
7403 /**
7404  * i40e_find_segment_in_package
7405  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7406  * @pkg_hdr: pointer to the package header to be searched
7407  *
7408  * This function searches a package file for a particular segment type. On
7409  * success it returns a pointer to the segment header, otherwise it will
7410  * return NULL.
7411  **/
7412 struct i40e_generic_seg_header *
7413 i40e_find_segment_in_package(u32 segment_type,
7414                              struct i40e_package_header *pkg_hdr)
7415 {
7416         struct i40e_generic_seg_header *segment;
7417         u32 i;
7418
7419         /* Search all package segments for the requested segment type */
7420         for (i = 0; i < pkg_hdr->segment_count; i++) {
7421                 segment =
7422                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7423                          pkg_hdr->segment_offset[i]);
7424
7425                 if (segment->type == segment_type)
7426                         return segment;
7427         }
7428
7429         return NULL;
7430 }
7431
7432 /* Get section table in profile */
7433 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7434         do {                                                            \
7435                 struct i40e_profile_segment *p = (profile);             \
7436                 u32 count;                                              \
7437                 u32 *nvm;                                               \
7438                 count = p->device_table_count;                          \
7439                 nvm = (u32 *)&p->device_table[count];                   \
7440                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7441         } while (0)
7442
7443 /* Get section header in profile */
7444 #define I40E_SECTION_HEADER(profile, offset)                            \
7445         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7446
7447 /**
7448  * i40e_find_section_in_profile
7449  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7450  * @profile: pointer to the i40e segment header to be searched
7451  *
7452  * This function searches i40e segment for a particular section type. On
7453  * success it returns a pointer to the section header, otherwise it will
7454  * return NULL.
7455  **/
7456 struct i40e_profile_section_header *
7457 i40e_find_section_in_profile(u32 section_type,
7458                              struct i40e_profile_segment *profile)
7459 {
7460         struct i40e_profile_section_header *sec;
7461         struct i40e_section_table *sec_tbl;
7462         u32 sec_off;
7463         u32 i;
7464
7465         if (profile->header.type != SEGMENT_TYPE_I40E)
7466                 return NULL;
7467
7468         I40E_SECTION_TABLE(profile, sec_tbl);
7469
7470         for (i = 0; i < sec_tbl->section_count; i++) {
7471                 sec_off = sec_tbl->section_offset[i];
7472                 sec = I40E_SECTION_HEADER(profile, sec_off);
7473                 if (sec->section.type == section_type)
7474                         return sec;
7475         }
7476
7477         return NULL;
7478 }
7479
7480 /**
7481  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7482  * @hw: pointer to the hw struct
7483  * @aq: command buffer containing all data to execute AQ
7484  **/
7485 STATIC enum
7486 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7487                                           struct i40e_profile_aq_section *aq)
7488 {
7489         enum i40e_status_code status;
7490         struct i40e_aq_desc desc;
7491         u8 *msg = NULL;
7492         u16 msglen;
7493
7494         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7495         desc.flags |= CPU_TO_LE16(aq->flags);
7496         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7497                     I40E_NONDMA_TO_NONDMA);
7498
7499         msglen = aq->datalen;
7500         if (msglen) {
7501                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7502                                                 I40E_AQ_FLAG_RD));
7503                 if (msglen > I40E_AQ_LARGE_BUF)
7504                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7505                 desc.datalen = CPU_TO_LE16(msglen);
7506                 msg = &aq->data[0];
7507         }
7508
7509         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7510
7511         if (status != I40E_SUCCESS) {
7512                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7513                            "unable to exec DDP AQ opcode %u, error %d\n",
7514                            aq->opcode, status);
7515                 return status;
7516         }
7517
7518         /* copy returned desc to aq_buf */
7519         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7520                     I40E_NONDMA_TO_NONDMA);
7521
7522         return I40E_SUCCESS;
7523 }
7524
7525 /**
7526  * i40e_validate_profile
7527  * @hw: pointer to the hardware structure
7528  * @profile: pointer to the profile segment of the package to be validated
7529  * @track_id: package tracking id
7530  * @rollback: flag if the profile is for rollback.
7531  *
7532  * Validates supported devices and profile's sections.
7533  */
7534 STATIC enum i40e_status_code
7535 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7536                       u32 track_id, bool rollback)
7537 {
7538         struct i40e_profile_section_header *sec = NULL;
7539         enum i40e_status_code status = I40E_SUCCESS;
7540         struct i40e_section_table *sec_tbl;
7541         u32 vendor_dev_id;
7542         u32 dev_cnt;
7543         u32 sec_off;
7544         u32 i;
7545
7546         if (track_id == I40E_DDP_TRACKID_INVALID) {
7547                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7548                 return I40E_NOT_SUPPORTED;
7549         }
7550
7551         dev_cnt = profile->device_table_count;
7552         for (i = 0; i < dev_cnt; i++) {
7553                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7554                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7555                     hw->device_id == (vendor_dev_id & 0xFFFF))
7556                         break;
7557         }
7558         if (dev_cnt && (i == dev_cnt)) {
7559                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7560                            "Device doesn't support DDP\n");
7561                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7562         }
7563
7564         I40E_SECTION_TABLE(profile, sec_tbl);
7565
7566         /* Validate sections types */
7567         for (i = 0; i < sec_tbl->section_count; i++) {
7568                 sec_off = sec_tbl->section_offset[i];
7569                 sec = I40E_SECTION_HEADER(profile, sec_off);
7570                 if (rollback) {
7571                         if (sec->section.type == SECTION_TYPE_MMIO ||
7572                             sec->section.type == SECTION_TYPE_AQ ||
7573                             sec->section.type == SECTION_TYPE_RB_AQ) {
7574                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7575                                            "Not a roll-back package\n");
7576                                 return I40E_NOT_SUPPORTED;
7577                         }
7578                 } else {
7579                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7580                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7581                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7582                                            "Not an original package\n");
7583                                 return I40E_NOT_SUPPORTED;
7584                         }
7585                 }
7586         }
7587
7588         return status;
7589 }
7590
7591 /**
7592  * i40e_write_profile
7593  * @hw: pointer to the hardware structure
7594  * @profile: pointer to the profile segment of the package to be downloaded
7595  * @track_id: package tracking id
7596  *
7597  * Handles the download of a complete package.
7598  */
7599 enum i40e_status_code
7600 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7601                    u32 track_id)
7602 {
7603         enum i40e_status_code status = I40E_SUCCESS;
7604         struct i40e_section_table *sec_tbl;
7605         struct i40e_profile_section_header *sec = NULL;
7606         struct i40e_profile_aq_section *ddp_aq;
7607         u32 section_size = 0;
7608         u32 offset = 0, info = 0;
7609         u32 sec_off;
7610         u32 i;
7611
7612         status = i40e_validate_profile(hw, profile, track_id, false);
7613         if (status)
7614                 return status;
7615
7616         I40E_SECTION_TABLE(profile, sec_tbl);
7617
7618         for (i = 0; i < sec_tbl->section_count; i++) {
7619                 sec_off = sec_tbl->section_offset[i];
7620                 sec = I40E_SECTION_HEADER(profile, sec_off);
7621                 /* Process generic admin command */
7622                 if (sec->section.type == SECTION_TYPE_AQ) {
7623                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7624                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7625                         if (status) {
7626                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7627                                            "Failed to execute aq: section %d, opcode %u\n",
7628                                            i, ddp_aq->opcode);
7629                                 break;
7630                         }
7631                         sec->section.type = SECTION_TYPE_RB_AQ;
7632                 }
7633
7634                 /* Skip any non-mmio sections */
7635                 if (sec->section.type != SECTION_TYPE_MMIO)
7636                         continue;
7637
7638                 section_size = sec->section.size +
7639                         sizeof(struct i40e_profile_section_header);
7640
7641                 /* Write MMIO section */
7642                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7643                                            track_id, &offset, &info, NULL);
7644                 if (status) {
7645                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7646                                    "Failed to write profile: section %d, offset %d, info %d\n",
7647                                    i, offset, info);
7648                         break;
7649                 }
7650         }
7651         return status;
7652 }
7653
7654 /**
7655  * i40e_rollback_profile
7656  * @hw: pointer to the hardware structure
7657  * @profile: pointer to the profile segment of the package to be removed
7658  * @track_id: package tracking id
7659  *
7660  * Rolls back previously loaded package.
7661  */
7662 enum i40e_status_code
7663 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7664                       u32 track_id)
7665 {
7666         struct i40e_profile_section_header *sec = NULL;
7667         enum i40e_status_code status = I40E_SUCCESS;
7668         struct i40e_section_table *sec_tbl;
7669         u32 offset = 0, info = 0;
7670         u32 section_size = 0;
7671         u32 sec_off;
7672         int i;
7673
7674         status = i40e_validate_profile(hw, profile, track_id, true);
7675         if (status)
7676                 return status;
7677
7678         I40E_SECTION_TABLE(profile, sec_tbl);
7679
7680         /* For rollback write sections in reverse */
7681         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7682                 sec_off = sec_tbl->section_offset[i];
7683                 sec = I40E_SECTION_HEADER(profile, sec_off);
7684
7685                 /* Skip any non-rollback sections */
7686                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7687                         continue;
7688
7689                 section_size = sec->section.size +
7690                         sizeof(struct i40e_profile_section_header);
7691
7692                 /* Write roll-back MMIO section */
7693                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7694                                            track_id, &offset, &info, NULL);
7695                 if (status) {
7696                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7697                                    "Failed to write profile: section %d, offset %d, info %d\n",
7698                                    i, offset, info);
7699                         break;
7700                 }
7701         }
7702         return status;
7703 }
7704
7705 /**
7706  * i40e_add_pinfo_to_list
7707  * @hw: pointer to the hardware structure
7708  * @profile: pointer to the profile segment of the package
7709  * @profile_info_sec: buffer for information section
7710  * @track_id: package tracking id
7711  *
7712  * Register a profile to the list of loaded profiles.
7713  */
7714 enum i40e_status_code
7715 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7716                        struct i40e_profile_segment *profile,
7717                        u8 *profile_info_sec, u32 track_id)
7718 {
7719         enum i40e_status_code status = I40E_SUCCESS;
7720         struct i40e_profile_section_header *sec = NULL;
7721         struct i40e_profile_info *pinfo;
7722         u32 offset = 0, info = 0;
7723
7724         sec = (struct i40e_profile_section_header *)profile_info_sec;
7725         sec->tbl_size = 1;
7726         sec->data_end = sizeof(struct i40e_profile_section_header) +
7727                         sizeof(struct i40e_profile_info);
7728         sec->section.type = SECTION_TYPE_INFO;
7729         sec->section.offset = sizeof(struct i40e_profile_section_header);
7730         sec->section.size = sizeof(struct i40e_profile_info);
7731         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7732                                              sec->section.offset);
7733         pinfo->track_id = track_id;
7734         pinfo->version = profile->version;
7735         pinfo->op = I40E_DDP_ADD_TRACKID;
7736         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7737                     I40E_NONDMA_TO_NONDMA);
7738
7739         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7740                                    track_id, &offset, &info, NULL);
7741         return status;
7742 }