1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 case I40E_DEV_ID_VF_HV:
75 hw->mac.type = I40E_MAC_VF;
78 hw->mac.type = I40E_MAC_GENERIC;
82 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
86 hw->mac.type, status);
90 #ifndef I40E_NDIS_SUPPORT
92 * i40e_aq_str - convert AQ err code to a string
93 * @hw: pointer to the HW structure
94 * @aq_err: the AQ error code to convert
96 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
101 case I40E_AQ_RC_EPERM:
102 return "I40E_AQ_RC_EPERM";
103 case I40E_AQ_RC_ENOENT:
104 return "I40E_AQ_RC_ENOENT";
105 case I40E_AQ_RC_ESRCH:
106 return "I40E_AQ_RC_ESRCH";
107 case I40E_AQ_RC_EINTR:
108 return "I40E_AQ_RC_EINTR";
110 return "I40E_AQ_RC_EIO";
111 case I40E_AQ_RC_ENXIO:
112 return "I40E_AQ_RC_ENXIO";
113 case I40E_AQ_RC_E2BIG:
114 return "I40E_AQ_RC_E2BIG";
115 case I40E_AQ_RC_EAGAIN:
116 return "I40E_AQ_RC_EAGAIN";
117 case I40E_AQ_RC_ENOMEM:
118 return "I40E_AQ_RC_ENOMEM";
119 case I40E_AQ_RC_EACCES:
120 return "I40E_AQ_RC_EACCES";
121 case I40E_AQ_RC_EFAULT:
122 return "I40E_AQ_RC_EFAULT";
123 case I40E_AQ_RC_EBUSY:
124 return "I40E_AQ_RC_EBUSY";
125 case I40E_AQ_RC_EEXIST:
126 return "I40E_AQ_RC_EEXIST";
127 case I40E_AQ_RC_EINVAL:
128 return "I40E_AQ_RC_EINVAL";
129 case I40E_AQ_RC_ENOTTY:
130 return "I40E_AQ_RC_ENOTTY";
131 case I40E_AQ_RC_ENOSPC:
132 return "I40E_AQ_RC_ENOSPC";
133 case I40E_AQ_RC_ENOSYS:
134 return "I40E_AQ_RC_ENOSYS";
135 case I40E_AQ_RC_ERANGE:
136 return "I40E_AQ_RC_ERANGE";
137 case I40E_AQ_RC_EFLUSHED:
138 return "I40E_AQ_RC_EFLUSHED";
139 case I40E_AQ_RC_BAD_ADDR:
140 return "I40E_AQ_RC_BAD_ADDR";
141 case I40E_AQ_RC_EMODE:
142 return "I40E_AQ_RC_EMODE";
143 case I40E_AQ_RC_EFBIG:
144 return "I40E_AQ_RC_EFBIG";
147 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
152 * i40e_stat_str - convert status err code to a string
153 * @hw: pointer to the HW structure
154 * @stat_err: the status error code to convert
156 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
162 return "I40E_ERR_NVM";
163 case I40E_ERR_NVM_CHECKSUM:
164 return "I40E_ERR_NVM_CHECKSUM";
166 return "I40E_ERR_PHY";
167 case I40E_ERR_CONFIG:
168 return "I40E_ERR_CONFIG";
170 return "I40E_ERR_PARAM";
171 case I40E_ERR_MAC_TYPE:
172 return "I40E_ERR_MAC_TYPE";
173 case I40E_ERR_UNKNOWN_PHY:
174 return "I40E_ERR_UNKNOWN_PHY";
175 case I40E_ERR_LINK_SETUP:
176 return "I40E_ERR_LINK_SETUP";
177 case I40E_ERR_ADAPTER_STOPPED:
178 return "I40E_ERR_ADAPTER_STOPPED";
179 case I40E_ERR_INVALID_MAC_ADDR:
180 return "I40E_ERR_INVALID_MAC_ADDR";
181 case I40E_ERR_DEVICE_NOT_SUPPORTED:
182 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
183 case I40E_ERR_MASTER_REQUESTS_PENDING:
184 return "I40E_ERR_MASTER_REQUESTS_PENDING";
185 case I40E_ERR_INVALID_LINK_SETTINGS:
186 return "I40E_ERR_INVALID_LINK_SETTINGS";
187 case I40E_ERR_AUTONEG_NOT_COMPLETE:
188 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
189 case I40E_ERR_RESET_FAILED:
190 return "I40E_ERR_RESET_FAILED";
191 case I40E_ERR_SWFW_SYNC:
192 return "I40E_ERR_SWFW_SYNC";
193 case I40E_ERR_NO_AVAILABLE_VSI:
194 return "I40E_ERR_NO_AVAILABLE_VSI";
195 case I40E_ERR_NO_MEMORY:
196 return "I40E_ERR_NO_MEMORY";
197 case I40E_ERR_BAD_PTR:
198 return "I40E_ERR_BAD_PTR";
199 case I40E_ERR_RING_FULL:
200 return "I40E_ERR_RING_FULL";
201 case I40E_ERR_INVALID_PD_ID:
202 return "I40E_ERR_INVALID_PD_ID";
203 case I40E_ERR_INVALID_QP_ID:
204 return "I40E_ERR_INVALID_QP_ID";
205 case I40E_ERR_INVALID_CQ_ID:
206 return "I40E_ERR_INVALID_CQ_ID";
207 case I40E_ERR_INVALID_CEQ_ID:
208 return "I40E_ERR_INVALID_CEQ_ID";
209 case I40E_ERR_INVALID_AEQ_ID:
210 return "I40E_ERR_INVALID_AEQ_ID";
211 case I40E_ERR_INVALID_SIZE:
212 return "I40E_ERR_INVALID_SIZE";
213 case I40E_ERR_INVALID_ARP_INDEX:
214 return "I40E_ERR_INVALID_ARP_INDEX";
215 case I40E_ERR_INVALID_FPM_FUNC_ID:
216 return "I40E_ERR_INVALID_FPM_FUNC_ID";
217 case I40E_ERR_QP_INVALID_MSG_SIZE:
218 return "I40E_ERR_QP_INVALID_MSG_SIZE";
219 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
220 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
221 case I40E_ERR_INVALID_FRAG_COUNT:
222 return "I40E_ERR_INVALID_FRAG_COUNT";
223 case I40E_ERR_QUEUE_EMPTY:
224 return "I40E_ERR_QUEUE_EMPTY";
225 case I40E_ERR_INVALID_ALIGNMENT:
226 return "I40E_ERR_INVALID_ALIGNMENT";
227 case I40E_ERR_FLUSHED_QUEUE:
228 return "I40E_ERR_FLUSHED_QUEUE";
229 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
230 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
231 case I40E_ERR_INVALID_IMM_DATA_SIZE:
232 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
233 case I40E_ERR_TIMEOUT:
234 return "I40E_ERR_TIMEOUT";
235 case I40E_ERR_OPCODE_MISMATCH:
236 return "I40E_ERR_OPCODE_MISMATCH";
237 case I40E_ERR_CQP_COMPL_ERROR:
238 return "I40E_ERR_CQP_COMPL_ERROR";
239 case I40E_ERR_INVALID_VF_ID:
240 return "I40E_ERR_INVALID_VF_ID";
241 case I40E_ERR_INVALID_HMCFN_ID:
242 return "I40E_ERR_INVALID_HMCFN_ID";
243 case I40E_ERR_BACKING_PAGE_ERROR:
244 return "I40E_ERR_BACKING_PAGE_ERROR";
245 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
246 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
247 case I40E_ERR_INVALID_PBLE_INDEX:
248 return "I40E_ERR_INVALID_PBLE_INDEX";
249 case I40E_ERR_INVALID_SD_INDEX:
250 return "I40E_ERR_INVALID_SD_INDEX";
251 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
252 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
253 case I40E_ERR_INVALID_SD_TYPE:
254 return "I40E_ERR_INVALID_SD_TYPE";
255 case I40E_ERR_MEMCPY_FAILED:
256 return "I40E_ERR_MEMCPY_FAILED";
257 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
258 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
259 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
260 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
261 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
262 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
263 case I40E_ERR_SRQ_ENABLED:
264 return "I40E_ERR_SRQ_ENABLED";
265 case I40E_ERR_ADMIN_QUEUE_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_ERROR";
267 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
268 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
269 case I40E_ERR_BUF_TOO_SHORT:
270 return "I40E_ERR_BUF_TOO_SHORT";
271 case I40E_ERR_ADMIN_QUEUE_FULL:
272 return "I40E_ERR_ADMIN_QUEUE_FULL";
273 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
274 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
275 case I40E_ERR_BAD_IWARP_CQE:
276 return "I40E_ERR_BAD_IWARP_CQE";
277 case I40E_ERR_NVM_BLANK_MODE:
278 return "I40E_ERR_NVM_BLANK_MODE";
279 case I40E_ERR_NOT_IMPLEMENTED:
280 return "I40E_ERR_NOT_IMPLEMENTED";
281 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
282 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
283 case I40E_ERR_DIAG_TEST_FAILED:
284 return "I40E_ERR_DIAG_TEST_FAILED";
285 case I40E_ERR_NOT_READY:
286 return "I40E_ERR_NOT_READY";
287 case I40E_NOT_SUPPORTED:
288 return "I40E_NOT_SUPPORTED";
289 case I40E_ERR_FIRMWARE_API_VERSION:
290 return "I40E_ERR_FIRMWARE_API_VERSION";
293 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 #endif /* I40E_NDIS_SUPPORT */
300 * @hw: debug mask related to admin queue
302 * @desc: pointer to admin queue descriptor
303 * @buffer: pointer to command buffer
304 * @buf_len: max length of buffer
306 * Dumps debug log about adminq command with descriptor contents.
308 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
309 void *buffer, u16 buf_len)
311 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
312 u16 len = LE16_TO_CPU(aq_desc->datalen);
313 u8 *buf = (u8 *)buffer;
316 if ((!(mask & hw->debug_mask)) || (desc == NULL))
320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
321 LE16_TO_CPU(aq_desc->opcode),
322 LE16_TO_CPU(aq_desc->flags),
323 LE16_TO_CPU(aq_desc->datalen),
324 LE16_TO_CPU(aq_desc->retval));
325 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
326 LE32_TO_CPU(aq_desc->cookie_high),
327 LE32_TO_CPU(aq_desc->cookie_low));
328 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
329 LE32_TO_CPU(aq_desc->params.internal.param0),
330 LE32_TO_CPU(aq_desc->params.internal.param1));
331 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
336 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
339 /* write the full 16-byte chunks */
340 for (i = 0; i < (len - 16); i += 16)
342 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
343 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
344 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
345 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
346 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
347 /* the most we could have left is 16 bytes, pad with zeros */
352 memset(d_buf, 0, sizeof(d_buf));
353 for (j = 0; i < len; j++, i++)
356 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
357 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
358 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
359 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
360 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
366 * i40e_check_asq_alive
367 * @hw: pointer to the hw struct
369 * Returns true if Queue is enabled else false.
371 bool i40e_check_asq_alive(struct i40e_hw *hw)
377 return !!(rd32(hw, hw->aq.asq.len) &
378 I40E_PF_ATQLEN_ATQENABLE_MASK);
380 return !!(rd32(hw, hw->aq.asq.len) &
381 I40E_PF_ATQLEN_ATQENABLE_MASK);
382 #endif /* INTEGRATED_VF */
383 #endif /* PF_DRIVER */
387 return !!(rd32(hw, hw->aq.asq.len) &
388 I40E_VF_ATQLEN1_ATQENABLE_MASK);
390 return !!(rd32(hw, hw->aq.asq.len) &
391 I40E_VF_ATQLEN1_ATQENABLE_MASK);
392 #endif /* INTEGRATED_VF */
393 #endif /* VF_DRIVER */
398 * i40e_aq_queue_shutdown
399 * @hw: pointer to the hw struct
400 * @unloading: is the driver unloading itself
402 * Tell the Firmware that we're shutting down the AdminQ and whether
403 * or not the driver is unloading as well.
405 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
408 struct i40e_aq_desc desc;
409 struct i40e_aqc_queue_shutdown *cmd =
410 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
411 enum i40e_status_code status;
413 i40e_fill_default_direct_cmd_desc(&desc,
414 i40e_aqc_opc_queue_shutdown);
417 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
418 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
423 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
424 * hardware to a bit-field that can be used by SW to more easily determine the
427 * Macros are used to shorten the table lines and make this table human
430 * We store the PTYPE in the top byte of the bit field - this is just so that
431 * we can check that the table doesn't have a row missing, as the index into
432 * the table should be the PTYPE.
436 * IF NOT i40e_ptype_lookup[ptype].known
439 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
440 * Use the rest of the fields to look at the tunnels, inner protocols, etc
442 * Use the enum i40e_rx_l2_ptype to decode the packet type
446 /* macro to make the table lines short */
447 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
450 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
451 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
452 I40E_RX_PTYPE_##OUTER_FRAG, \
453 I40E_RX_PTYPE_TUNNEL_##T, \
454 I40E_RX_PTYPE_TUNNEL_END_##TE, \
455 I40E_RX_PTYPE_##TEF, \
456 I40E_RX_PTYPE_INNER_PROT_##I, \
457 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
459 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
460 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
462 /* shorter macros makes the table fit but are terse */
463 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
464 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
465 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
467 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
468 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
469 /* L2 Packet types */
470 I40E_PTT_UNUSED_ENTRY(0),
471 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
472 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
473 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
474 I40E_PTT_UNUSED_ENTRY(4),
475 I40E_PTT_UNUSED_ENTRY(5),
476 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
477 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
478 I40E_PTT_UNUSED_ENTRY(8),
479 I40E_PTT_UNUSED_ENTRY(9),
480 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
481 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
482 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
483 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
484 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
485 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
486 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
487 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
488 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
489 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
490 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
491 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
493 /* Non Tunneled IPv4 */
494 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
495 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
496 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
497 I40E_PTT_UNUSED_ENTRY(25),
498 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
499 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
500 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
503 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
504 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
505 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
506 I40E_PTT_UNUSED_ENTRY(32),
507 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
508 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
509 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
512 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
513 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
514 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
515 I40E_PTT_UNUSED_ENTRY(39),
516 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
517 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
518 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
520 /* IPv4 --> GRE/NAT */
521 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
523 /* IPv4 --> GRE/NAT --> IPv4 */
524 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
525 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
526 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
527 I40E_PTT_UNUSED_ENTRY(47),
528 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
529 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
530 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
532 /* IPv4 --> GRE/NAT --> IPv6 */
533 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
534 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
535 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
536 I40E_PTT_UNUSED_ENTRY(54),
537 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
538 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
539 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
541 /* IPv4 --> GRE/NAT --> MAC */
542 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
544 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
545 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
546 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
547 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
548 I40E_PTT_UNUSED_ENTRY(62),
549 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
550 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
551 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
553 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
554 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
555 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
556 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
557 I40E_PTT_UNUSED_ENTRY(69),
558 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
559 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
560 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
562 /* IPv4 --> GRE/NAT --> MAC/VLAN */
563 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
565 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
566 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
567 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
568 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
569 I40E_PTT_UNUSED_ENTRY(77),
570 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
571 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
572 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
574 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
575 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
576 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
577 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
578 I40E_PTT_UNUSED_ENTRY(84),
579 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
580 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
581 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
583 /* Non Tunneled IPv6 */
584 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
585 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
586 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
587 I40E_PTT_UNUSED_ENTRY(91),
588 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
589 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
590 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
593 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
594 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
595 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
596 I40E_PTT_UNUSED_ENTRY(98),
597 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
598 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
599 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
602 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
603 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
604 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
605 I40E_PTT_UNUSED_ENTRY(105),
606 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
607 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
608 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
610 /* IPv6 --> GRE/NAT */
611 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
613 /* IPv6 --> GRE/NAT -> IPv4 */
614 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
615 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
616 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
617 I40E_PTT_UNUSED_ENTRY(113),
618 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
619 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
620 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
622 /* IPv6 --> GRE/NAT -> IPv6 */
623 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
624 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
625 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
626 I40E_PTT_UNUSED_ENTRY(120),
627 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
628 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
629 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
631 /* IPv6 --> GRE/NAT -> MAC */
632 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
634 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
635 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(128),
639 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
643 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
644 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(135),
648 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
652 /* IPv6 --> GRE/NAT -> MAC/VLAN */
653 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
655 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
656 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(143),
660 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
664 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
665 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(150),
669 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
674 I40E_PTT_UNUSED_ENTRY(154),
675 I40E_PTT_UNUSED_ENTRY(155),
676 I40E_PTT_UNUSED_ENTRY(156),
677 I40E_PTT_UNUSED_ENTRY(157),
678 I40E_PTT_UNUSED_ENTRY(158),
679 I40E_PTT_UNUSED_ENTRY(159),
681 I40E_PTT_UNUSED_ENTRY(160),
682 I40E_PTT_UNUSED_ENTRY(161),
683 I40E_PTT_UNUSED_ENTRY(162),
684 I40E_PTT_UNUSED_ENTRY(163),
685 I40E_PTT_UNUSED_ENTRY(164),
686 I40E_PTT_UNUSED_ENTRY(165),
687 I40E_PTT_UNUSED_ENTRY(166),
688 I40E_PTT_UNUSED_ENTRY(167),
689 I40E_PTT_UNUSED_ENTRY(168),
690 I40E_PTT_UNUSED_ENTRY(169),
692 I40E_PTT_UNUSED_ENTRY(170),
693 I40E_PTT_UNUSED_ENTRY(171),
694 I40E_PTT_UNUSED_ENTRY(172),
695 I40E_PTT_UNUSED_ENTRY(173),
696 I40E_PTT_UNUSED_ENTRY(174),
697 I40E_PTT_UNUSED_ENTRY(175),
698 I40E_PTT_UNUSED_ENTRY(176),
699 I40E_PTT_UNUSED_ENTRY(177),
700 I40E_PTT_UNUSED_ENTRY(178),
701 I40E_PTT_UNUSED_ENTRY(179),
703 I40E_PTT_UNUSED_ENTRY(180),
704 I40E_PTT_UNUSED_ENTRY(181),
705 I40E_PTT_UNUSED_ENTRY(182),
706 I40E_PTT_UNUSED_ENTRY(183),
707 I40E_PTT_UNUSED_ENTRY(184),
708 I40E_PTT_UNUSED_ENTRY(185),
709 I40E_PTT_UNUSED_ENTRY(186),
710 I40E_PTT_UNUSED_ENTRY(187),
711 I40E_PTT_UNUSED_ENTRY(188),
712 I40E_PTT_UNUSED_ENTRY(189),
714 I40E_PTT_UNUSED_ENTRY(190),
715 I40E_PTT_UNUSED_ENTRY(191),
716 I40E_PTT_UNUSED_ENTRY(192),
717 I40E_PTT_UNUSED_ENTRY(193),
718 I40E_PTT_UNUSED_ENTRY(194),
719 I40E_PTT_UNUSED_ENTRY(195),
720 I40E_PTT_UNUSED_ENTRY(196),
721 I40E_PTT_UNUSED_ENTRY(197),
722 I40E_PTT_UNUSED_ENTRY(198),
723 I40E_PTT_UNUSED_ENTRY(199),
725 I40E_PTT_UNUSED_ENTRY(200),
726 I40E_PTT_UNUSED_ENTRY(201),
727 I40E_PTT_UNUSED_ENTRY(202),
728 I40E_PTT_UNUSED_ENTRY(203),
729 I40E_PTT_UNUSED_ENTRY(204),
730 I40E_PTT_UNUSED_ENTRY(205),
731 I40E_PTT_UNUSED_ENTRY(206),
732 I40E_PTT_UNUSED_ENTRY(207),
733 I40E_PTT_UNUSED_ENTRY(208),
734 I40E_PTT_UNUSED_ENTRY(209),
736 I40E_PTT_UNUSED_ENTRY(210),
737 I40E_PTT_UNUSED_ENTRY(211),
738 I40E_PTT_UNUSED_ENTRY(212),
739 I40E_PTT_UNUSED_ENTRY(213),
740 I40E_PTT_UNUSED_ENTRY(214),
741 I40E_PTT_UNUSED_ENTRY(215),
742 I40E_PTT_UNUSED_ENTRY(216),
743 I40E_PTT_UNUSED_ENTRY(217),
744 I40E_PTT_UNUSED_ENTRY(218),
745 I40E_PTT_UNUSED_ENTRY(219),
747 I40E_PTT_UNUSED_ENTRY(220),
748 I40E_PTT_UNUSED_ENTRY(221),
749 I40E_PTT_UNUSED_ENTRY(222),
750 I40E_PTT_UNUSED_ENTRY(223),
751 I40E_PTT_UNUSED_ENTRY(224),
752 I40E_PTT_UNUSED_ENTRY(225),
753 I40E_PTT_UNUSED_ENTRY(226),
754 I40E_PTT_UNUSED_ENTRY(227),
755 I40E_PTT_UNUSED_ENTRY(228),
756 I40E_PTT_UNUSED_ENTRY(229),
758 I40E_PTT_UNUSED_ENTRY(230),
759 I40E_PTT_UNUSED_ENTRY(231),
760 I40E_PTT_UNUSED_ENTRY(232),
761 I40E_PTT_UNUSED_ENTRY(233),
762 I40E_PTT_UNUSED_ENTRY(234),
763 I40E_PTT_UNUSED_ENTRY(235),
764 I40E_PTT_UNUSED_ENTRY(236),
765 I40E_PTT_UNUSED_ENTRY(237),
766 I40E_PTT_UNUSED_ENTRY(238),
767 I40E_PTT_UNUSED_ENTRY(239),
769 I40E_PTT_UNUSED_ENTRY(240),
770 I40E_PTT_UNUSED_ENTRY(241),
771 I40E_PTT_UNUSED_ENTRY(242),
772 I40E_PTT_UNUSED_ENTRY(243),
773 I40E_PTT_UNUSED_ENTRY(244),
774 I40E_PTT_UNUSED_ENTRY(245),
775 I40E_PTT_UNUSED_ENTRY(246),
776 I40E_PTT_UNUSED_ENTRY(247),
777 I40E_PTT_UNUSED_ENTRY(248),
778 I40E_PTT_UNUSED_ENTRY(249),
780 I40E_PTT_UNUSED_ENTRY(250),
781 I40E_PTT_UNUSED_ENTRY(251),
782 I40E_PTT_UNUSED_ENTRY(252),
783 I40E_PTT_UNUSED_ENTRY(253),
784 I40E_PTT_UNUSED_ENTRY(254),
785 I40E_PTT_UNUSED_ENTRY(255)
790 * i40e_validate_mac_addr - Validate unicast MAC address
791 * @mac_addr: pointer to MAC address
793 * Tests a MAC address to ensure it is a valid Individual Address
795 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
797 enum i40e_status_code status = I40E_SUCCESS;
799 DEBUGFUNC("i40e_validate_mac_addr");
801 /* Broadcast addresses ARE multicast addresses
802 * Make sure it is not a multicast address
803 * Reject the zero address
805 if (I40E_IS_MULTICAST(mac_addr) ||
806 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
807 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
808 status = I40E_ERR_INVALID_MAC_ADDR;
815 * i40e_init_shared_code - Initialize the shared code
816 * @hw: pointer to hardware structure
818 * This assigns the MAC type and PHY code and inits the NVM.
819 * Does not touch the hardware. This function must be called prior to any
820 * other function in the shared code. The i40e_hw structure should be
821 * memset to 0 prior to calling this function. The following fields in
822 * hw structure should be filled in prior to calling this function:
823 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
824 * subsystem_vendor_id, and revision_id
826 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
828 enum i40e_status_code status = I40E_SUCCESS;
829 u32 port, ari, func_rid;
831 DEBUGFUNC("i40e_init_shared_code");
833 i40e_set_mac_type(hw);
835 switch (hw->mac.type) {
839 return I40E_ERR_DEVICE_NOT_SUPPORTED;
842 hw->phy.get_link_info = true;
844 /* Determine port number and PF number*/
845 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
846 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
848 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
849 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
850 func_rid = rd32(hw, I40E_PF_FUNC_RID);
852 hw->pf_id = (u8)(func_rid & 0xff);
854 hw->pf_id = (u8)(func_rid & 0x7);
856 status = i40e_init_nvm(hw);
861 * i40e_aq_mac_address_read - Retrieve the MAC addresses
862 * @hw: pointer to the hw struct
863 * @flags: a return indicator of what addresses were added to the addr store
864 * @addrs: the requestor's mac addr store
865 * @cmd_details: pointer to command details structure or NULL
867 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
869 struct i40e_aqc_mac_address_read_data *addrs,
870 struct i40e_asq_cmd_details *cmd_details)
872 struct i40e_aq_desc desc;
873 struct i40e_aqc_mac_address_read *cmd_data =
874 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
875 enum i40e_status_code status;
877 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
878 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
880 status = i40e_asq_send_command(hw, &desc, addrs,
881 sizeof(*addrs), cmd_details);
882 *flags = LE16_TO_CPU(cmd_data->command_flags);
888 * i40e_aq_mac_address_write - Change the MAC addresses
889 * @hw: pointer to the hw struct
890 * @flags: indicates which MAC to be written
891 * @mac_addr: address to write
892 * @cmd_details: pointer to command details structure or NULL
894 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
895 u16 flags, u8 *mac_addr,
896 struct i40e_asq_cmd_details *cmd_details)
898 struct i40e_aq_desc desc;
899 struct i40e_aqc_mac_address_write *cmd_data =
900 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
901 enum i40e_status_code status;
903 i40e_fill_default_direct_cmd_desc(&desc,
904 i40e_aqc_opc_mac_address_write);
905 cmd_data->command_flags = CPU_TO_LE16(flags);
906 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
907 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
908 ((u32)mac_addr[3] << 16) |
909 ((u32)mac_addr[4] << 8) |
912 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
918 * i40e_get_mac_addr - get MAC address
919 * @hw: pointer to the HW structure
920 * @mac_addr: pointer to MAC address
922 * Reads the adapter's MAC address from register
924 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
926 struct i40e_aqc_mac_address_read_data addrs;
927 enum i40e_status_code status;
930 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
932 if (flags & I40E_AQC_LAN_ADDR_VALID)
933 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
939 * i40e_get_port_mac_addr - get Port MAC address
940 * @hw: pointer to the HW structure
941 * @mac_addr: pointer to Port MAC address
943 * Reads the adapter's Port MAC address
945 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
947 struct i40e_aqc_mac_address_read_data addrs;
948 enum i40e_status_code status;
951 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
955 if (flags & I40E_AQC_PORT_ADDR_VALID)
956 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
958 status = I40E_ERR_INVALID_MAC_ADDR;
964 * i40e_pre_tx_queue_cfg - pre tx queue configure
965 * @hw: pointer to the HW structure
966 * @queue: target pf queue index
967 * @enable: state change request
969 * Handles hw requirement to indicate intention to enable
970 * or disable target queue.
972 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
974 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
978 if (abs_queue_idx >= 128) {
979 reg_block = abs_queue_idx / 128;
980 abs_queue_idx %= 128;
983 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
984 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
985 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
988 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
990 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
992 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
996 * i40e_read_pba_string - Reads part number string from EEPROM
997 * @hw: pointer to hardware structure
998 * @pba_num: stores the part number string from the EEPROM
999 * @pba_num_size: part number string buffer length
1001 * Reads the part number string from the EEPROM.
1003 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1006 enum i40e_status_code status = I40E_SUCCESS;
1012 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1013 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1014 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1018 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1019 if (status != I40E_SUCCESS) {
1020 DEBUGOUT("Failed to read PBA Block pointer.\n");
1024 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1025 if (status != I40E_SUCCESS) {
1026 DEBUGOUT("Failed to read PBA Block size.\n");
1030 /* Subtract one to get PBA word count (PBA Size word is included in
1034 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1035 DEBUGOUT("Buffer to small for PBA data.\n");
1036 return I40E_ERR_PARAM;
1039 for (i = 0; i < pba_size; i++) {
1040 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1041 if (status != I40E_SUCCESS) {
1042 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1046 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1047 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1049 pba_num[(pba_size * 2)] = '\0';
1055 * i40e_get_media_type - Gets media type
1056 * @hw: pointer to the hardware structure
1058 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1060 enum i40e_media_type media;
1062 switch (hw->phy.link_info.phy_type) {
1063 case I40E_PHY_TYPE_10GBASE_SR:
1064 case I40E_PHY_TYPE_10GBASE_LR:
1065 case I40E_PHY_TYPE_1000BASE_SX:
1066 case I40E_PHY_TYPE_1000BASE_LX:
1067 case I40E_PHY_TYPE_40GBASE_SR4:
1068 case I40E_PHY_TYPE_40GBASE_LR4:
1069 media = I40E_MEDIA_TYPE_FIBER;
1071 case I40E_PHY_TYPE_100BASE_TX:
1072 case I40E_PHY_TYPE_1000BASE_T:
1073 case I40E_PHY_TYPE_10GBASE_T:
1074 media = I40E_MEDIA_TYPE_BASET;
1076 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1077 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1078 case I40E_PHY_TYPE_10GBASE_CR1:
1079 case I40E_PHY_TYPE_40GBASE_CR4:
1080 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1081 case I40E_PHY_TYPE_40GBASE_AOC:
1082 case I40E_PHY_TYPE_10GBASE_AOC:
1083 media = I40E_MEDIA_TYPE_DA;
1085 case I40E_PHY_TYPE_1000BASE_KX:
1086 case I40E_PHY_TYPE_10GBASE_KX4:
1087 case I40E_PHY_TYPE_10GBASE_KR:
1088 case I40E_PHY_TYPE_40GBASE_KR4:
1089 case I40E_PHY_TYPE_20GBASE_KR2:
1090 media = I40E_MEDIA_TYPE_BACKPLANE;
1092 case I40E_PHY_TYPE_SGMII:
1093 case I40E_PHY_TYPE_XAUI:
1094 case I40E_PHY_TYPE_XFI:
1095 case I40E_PHY_TYPE_XLAUI:
1096 case I40E_PHY_TYPE_XLPPI:
1098 media = I40E_MEDIA_TYPE_UNKNOWN;
1105 #define I40E_PF_RESET_WAIT_COUNT 200
1107 * i40e_pf_reset - Reset the PF
1108 * @hw: pointer to the hardware structure
1110 * Assuming someone else has triggered a global reset,
1111 * assure the global reset is complete and then reset the PF
1113 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1120 /* Poll for Global Reset steady state in case of recent GRST.
1121 * The grst delay value is in 100ms units, and we'll wait a
1122 * couple counts longer to be sure we don't just miss the end.
1124 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1125 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1126 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1127 #ifdef I40E_ESS_SUPPORT
1128 /* It can take upto 15 secs for GRST steady state */
1129 grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1131 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1132 reg = rd32(hw, I40E_GLGEN_RSTAT);
1133 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1135 i40e_msec_delay(100);
1137 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1138 DEBUGOUT("Global reset polling failed to complete.\n");
1139 return I40E_ERR_RESET_FAILED;
1142 /* Now Wait for the FW to be ready */
1143 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1144 reg = rd32(hw, I40E_GLNVM_ULD);
1145 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1146 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1147 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1148 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1149 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1152 i40e_msec_delay(10);
1154 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1155 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1156 DEBUGOUT("wait for FW Reset complete timedout\n");
1157 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1158 return I40E_ERR_RESET_FAILED;
1161 /* If there was a Global Reset in progress when we got here,
1162 * we don't need to do the PF Reset
1165 reg = rd32(hw, I40E_PFGEN_CTRL);
1166 wr32(hw, I40E_PFGEN_CTRL,
1167 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1168 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1169 reg = rd32(hw, I40E_PFGEN_CTRL);
1170 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1174 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1175 DEBUGOUT("PF reset polling failed to complete.\n");
1176 return I40E_ERR_RESET_FAILED;
1180 i40e_clear_pxe_mode(hw);
1183 return I40E_SUCCESS;
1187 * i40e_clear_hw - clear out any left over hw state
1188 * @hw: pointer to the hw struct
1190 * Clear queues and interrupts, typically called at init time,
1191 * but after the capabilities have been found so we know how many
1192 * queues and msix vectors have been allocated.
1194 void i40e_clear_hw(struct i40e_hw *hw)
1196 u32 num_queues, base_queue;
1204 /* get number of interrupts, queues, and vfs */
1205 val = rd32(hw, I40E_GLPCI_CNF2);
1206 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1207 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1208 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1209 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1211 val = rd32(hw, I40E_PFLAN_QALLOC);
1212 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1213 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1214 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1215 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1216 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1217 num_queues = (j - base_queue) + 1;
1221 val = rd32(hw, I40E_PF_VT_PFALLOC);
1222 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1223 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1224 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1225 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1226 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1227 num_vfs = (j - i) + 1;
1231 /* stop all the interrupts */
1232 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1233 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1234 for (i = 0; i < num_pf_int - 2; i++)
1235 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1237 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1238 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1239 wr32(hw, I40E_PFINT_LNKLST0, val);
1240 for (i = 0; i < num_pf_int - 2; i++)
1241 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1242 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1243 for (i = 0; i < num_vfs; i++)
1244 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1245 for (i = 0; i < num_vf_int - 2; i++)
1246 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1248 /* warn the HW of the coming Tx disables */
1249 for (i = 0; i < num_queues; i++) {
1250 u32 abs_queue_idx = base_queue + i;
1253 if (abs_queue_idx >= 128) {
1254 reg_block = abs_queue_idx / 128;
1255 abs_queue_idx %= 128;
1258 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1259 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1260 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1261 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1263 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1265 i40e_usec_delay(400);
1267 /* stop all the queues */
1268 for (i = 0; i < num_queues; i++) {
1269 wr32(hw, I40E_QINT_TQCTL(i), 0);
1270 wr32(hw, I40E_QTX_ENA(i), 0);
1271 wr32(hw, I40E_QINT_RQCTL(i), 0);
1272 wr32(hw, I40E_QRX_ENA(i), 0);
1275 /* short wait for all queue disables to settle */
1276 i40e_usec_delay(50);
1280 * i40e_clear_pxe_mode - clear pxe operations mode
1281 * @hw: pointer to the hw struct
1283 * Make sure all PXE mode settings are cleared, including things
1284 * like descriptor fetch/write-back mode.
1286 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1288 if (i40e_check_asq_alive(hw))
1289 i40e_aq_clear_pxe_mode(hw, NULL);
1293 * i40e_led_is_mine - helper to find matching led
1294 * @hw: pointer to the hw struct
1295 * @idx: index into GPIO registers
1297 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1299 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1304 if (!hw->func_caps.led[idx])
1307 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1308 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1309 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1311 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1312 * if it is not our port then ignore
1314 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1321 #define I40E_COMBINED_ACTIVITY 0xA
1322 #define I40E_FILTER_ACTIVITY 0xE
1323 #define I40E_LINK_ACTIVITY 0xC
1324 #define I40E_MAC_ACTIVITY 0xD
1325 #define I40E_LED0 22
1328 * i40e_led_get - return current on/off mode
1329 * @hw: pointer to the hw struct
1331 * The value returned is the 'mode' field as defined in the
1332 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1333 * values are variations of possible behaviors relating to
1334 * blink, link, and wire.
1336 u32 i40e_led_get(struct i40e_hw *hw)
1338 u32 current_mode = 0;
1342 /* as per the documentation GPIO 22-29 are the LED
1343 * GPIO pins named LED0..LED7
1345 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1346 u32 gpio_val = i40e_led_is_mine(hw, i);
1351 /* ignore gpio LED src mode entries related to the activity LEDs */
1352 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1353 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1354 switch (current_mode) {
1355 case I40E_COMBINED_ACTIVITY:
1356 case I40E_FILTER_ACTIVITY:
1357 case I40E_MAC_ACTIVITY:
1363 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1364 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1372 * i40e_led_set - set new on/off mode
1373 * @hw: pointer to the hw struct
1374 * @mode: 0=off, 0xf=on (else see manual for mode details)
1375 * @blink: true if the LED should blink when on, false if steady
1377 * if this function is used to turn on the blink it should
1378 * be used to disable the blink when restoring the original state.
1380 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1382 u32 current_mode = 0;
1385 if (mode & 0xfffffff0)
1386 DEBUGOUT1("invalid mode passed in %X\n", mode);
1388 /* as per the documentation GPIO 22-29 are the LED
1389 * GPIO pins named LED0..LED7
1391 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1392 u32 gpio_val = i40e_led_is_mine(hw, i);
1397 /* ignore gpio LED src mode entries related to the activity LEDs */
1398 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1399 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1400 switch (current_mode) {
1401 case I40E_COMBINED_ACTIVITY:
1402 case I40E_FILTER_ACTIVITY:
1403 case I40E_MAC_ACTIVITY:
1409 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1410 /* this & is a bit of paranoia, but serves as a range check */
1411 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1412 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1414 if (mode == I40E_LINK_ACTIVITY)
1418 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1420 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1422 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1427 /* Admin command wrappers */
1430 * i40e_aq_get_phy_capabilities
1431 * @hw: pointer to the hw struct
1432 * @abilities: structure for PHY capabilities to be filled
1433 * @qualified_modules: report Qualified Modules
1434 * @report_init: report init capabilities (active are default)
1435 * @cmd_details: pointer to command details structure or NULL
1437 * Returns the various PHY abilities supported on the Port.
1439 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1440 bool qualified_modules, bool report_init,
1441 struct i40e_aq_get_phy_abilities_resp *abilities,
1442 struct i40e_asq_cmd_details *cmd_details)
1444 struct i40e_aq_desc desc;
1445 enum i40e_status_code status;
1446 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1449 return I40E_ERR_PARAM;
1451 i40e_fill_default_direct_cmd_desc(&desc,
1452 i40e_aqc_opc_get_phy_abilities);
1454 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1455 if (abilities_size > I40E_AQ_LARGE_BUF)
1456 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1458 if (qualified_modules)
1459 desc.params.external.param0 |=
1460 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1463 desc.params.external.param0 |=
1464 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1466 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1469 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1470 status = I40E_ERR_UNKNOWN_PHY;
1473 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1479 * i40e_aq_set_phy_config
1480 * @hw: pointer to the hw struct
1481 * @config: structure with PHY configuration to be set
1482 * @cmd_details: pointer to command details structure or NULL
1484 * Set the various PHY configuration parameters
1485 * supported on the Port.One or more of the Set PHY config parameters may be
1486 * ignored in an MFP mode as the PF may not have the privilege to set some
1487 * of the PHY Config parameters. This status will be indicated by the
1490 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1491 struct i40e_aq_set_phy_config *config,
1492 struct i40e_asq_cmd_details *cmd_details)
1494 struct i40e_aq_desc desc;
1495 struct i40e_aq_set_phy_config *cmd =
1496 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1497 enum i40e_status_code status;
1500 return I40E_ERR_PARAM;
1502 i40e_fill_default_direct_cmd_desc(&desc,
1503 i40e_aqc_opc_set_phy_config);
1507 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1514 * @hw: pointer to the hw struct
1516 * Set the requested flow control mode using set_phy_config.
1518 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1519 bool atomic_restart)
1521 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1522 struct i40e_aq_get_phy_abilities_resp abilities;
1523 struct i40e_aq_set_phy_config config;
1524 enum i40e_status_code status;
1525 u8 pause_mask = 0x0;
1531 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1532 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1534 case I40E_FC_RX_PAUSE:
1535 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1537 case I40E_FC_TX_PAUSE:
1538 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1544 /* Get the current phy config */
1545 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1548 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1552 memset(&config, 0, sizeof(config));
1553 /* clear the old pause settings */
1554 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1555 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1556 /* set the new abilities */
1557 config.abilities |= pause_mask;
1558 /* If the abilities have changed, then set the new config */
1559 if (config.abilities != abilities.abilities) {
1560 /* Auto restart link so settings take effect */
1562 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1563 /* Copy over all the old settings */
1564 config.phy_type = abilities.phy_type;
1565 config.link_speed = abilities.link_speed;
1566 config.eee_capability = abilities.eee_capability;
1567 config.eeer = abilities.eeer_val;
1568 config.low_power_ctrl = abilities.d3_lpan;
1569 status = i40e_aq_set_phy_config(hw, &config, NULL);
1572 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1574 /* Update the link info */
1575 status = i40e_update_link_info(hw);
1577 /* Wait a little bit (on 40G cards it sometimes takes a really
1578 * long time for link to come back from the atomic reset)
1581 i40e_msec_delay(1000);
1582 status = i40e_update_link_info(hw);
1585 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1591 * i40e_aq_set_mac_config
1592 * @hw: pointer to the hw struct
1593 * @max_frame_size: Maximum Frame Size to be supported by the port
1594 * @crc_en: Tell HW to append a CRC to outgoing frames
1595 * @pacing: Pacing configurations
1596 * @cmd_details: pointer to command details structure or NULL
1598 * Configure MAC settings for frame size, jumbo frame support and the
1599 * addition of a CRC by the hardware.
1601 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1603 bool crc_en, u16 pacing,
1604 struct i40e_asq_cmd_details *cmd_details)
1606 struct i40e_aq_desc desc;
1607 struct i40e_aq_set_mac_config *cmd =
1608 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1609 enum i40e_status_code status;
1611 if (max_frame_size == 0)
1612 return I40E_ERR_PARAM;
1614 i40e_fill_default_direct_cmd_desc(&desc,
1615 i40e_aqc_opc_set_mac_config);
1617 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1618 cmd->params = ((u8)pacing & 0x0F) << 3;
1620 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1628 * i40e_aq_clear_pxe_mode
1629 * @hw: pointer to the hw struct
1630 * @cmd_details: pointer to command details structure or NULL
1632 * Tell the firmware that the driver is taking over from PXE
1634 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1635 struct i40e_asq_cmd_details *cmd_details)
1637 enum i40e_status_code status;
1638 struct i40e_aq_desc desc;
1639 struct i40e_aqc_clear_pxe *cmd =
1640 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1642 i40e_fill_default_direct_cmd_desc(&desc,
1643 i40e_aqc_opc_clear_pxe_mode);
1647 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1649 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1655 * i40e_aq_set_link_restart_an
1656 * @hw: pointer to the hw struct
1657 * @enable_link: if true: enable link, if false: disable link
1658 * @cmd_details: pointer to command details structure or NULL
1660 * Sets up the link and restarts the Auto-Negotiation over the link.
1662 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1663 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1665 struct i40e_aq_desc desc;
1666 struct i40e_aqc_set_link_restart_an *cmd =
1667 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1668 enum i40e_status_code status;
1670 i40e_fill_default_direct_cmd_desc(&desc,
1671 i40e_aqc_opc_set_link_restart_an);
1673 cmd->command = I40E_AQ_PHY_RESTART_AN;
1675 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1677 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1679 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1685 * i40e_aq_get_link_info
1686 * @hw: pointer to the hw struct
1687 * @enable_lse: enable/disable LinkStatusEvent reporting
1688 * @link: pointer to link status structure - optional
1689 * @cmd_details: pointer to command details structure or NULL
1691 * Returns the link status of the adapter.
1693 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1694 bool enable_lse, struct i40e_link_status *link,
1695 struct i40e_asq_cmd_details *cmd_details)
1697 struct i40e_aq_desc desc;
1698 struct i40e_aqc_get_link_status *resp =
1699 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1700 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1701 enum i40e_status_code status;
1702 bool tx_pause, rx_pause;
1705 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1708 command_flags = I40E_AQ_LSE_ENABLE;
1710 command_flags = I40E_AQ_LSE_DISABLE;
1711 resp->command_flags = CPU_TO_LE16(command_flags);
1713 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1715 if (status != I40E_SUCCESS)
1716 goto aq_get_link_info_exit;
1718 /* save off old link status information */
1719 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1720 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1722 /* update link status */
1723 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1724 hw->phy.media_type = i40e_get_media_type(hw);
1725 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1726 hw_link_info->link_info = resp->link_info;
1727 hw_link_info->an_info = resp->an_info;
1728 hw_link_info->ext_info = resp->ext_info;
1729 hw_link_info->loopback = resp->loopback;
1730 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1731 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1733 /* update fc info */
1734 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1735 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1736 if (tx_pause & rx_pause)
1737 hw->fc.current_mode = I40E_FC_FULL;
1739 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1741 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1743 hw->fc.current_mode = I40E_FC_NONE;
1745 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1746 hw_link_info->crc_enable = true;
1748 hw_link_info->crc_enable = false;
1750 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1751 hw_link_info->lse_enable = true;
1753 hw_link_info->lse_enable = false;
1755 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1756 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1757 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1759 /* save link status information */
1761 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1762 I40E_NONDMA_TO_NONDMA);
1764 /* flag cleared so helper functions don't call AQ again */
1765 hw->phy.get_link_info = false;
1767 aq_get_link_info_exit:
1772 * i40e_aq_set_phy_int_mask
1773 * @hw: pointer to the hw struct
1774 * @mask: interrupt mask to be set
1775 * @cmd_details: pointer to command details structure or NULL
1777 * Set link interrupt mask.
1779 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1781 struct i40e_asq_cmd_details *cmd_details)
1783 struct i40e_aq_desc desc;
1784 struct i40e_aqc_set_phy_int_mask *cmd =
1785 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1786 enum i40e_status_code status;
1788 i40e_fill_default_direct_cmd_desc(&desc,
1789 i40e_aqc_opc_set_phy_int_mask);
1791 cmd->event_mask = CPU_TO_LE16(mask);
1793 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1799 * i40e_aq_get_local_advt_reg
1800 * @hw: pointer to the hw struct
1801 * @advt_reg: local AN advertisement register value
1802 * @cmd_details: pointer to command details structure or NULL
1804 * Get the Local AN advertisement register value.
1806 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1808 struct i40e_asq_cmd_details *cmd_details)
1810 struct i40e_aq_desc desc;
1811 struct i40e_aqc_an_advt_reg *resp =
1812 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1813 enum i40e_status_code status;
1815 i40e_fill_default_direct_cmd_desc(&desc,
1816 i40e_aqc_opc_get_local_advt_reg);
1818 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1820 if (status != I40E_SUCCESS)
1821 goto aq_get_local_advt_reg_exit;
1823 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1824 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1826 aq_get_local_advt_reg_exit:
1831 * i40e_aq_set_local_advt_reg
1832 * @hw: pointer to the hw struct
1833 * @advt_reg: local AN advertisement register value
1834 * @cmd_details: pointer to command details structure or NULL
1836 * Get the Local AN advertisement register value.
1838 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1840 struct i40e_asq_cmd_details *cmd_details)
1842 struct i40e_aq_desc desc;
1843 struct i40e_aqc_an_advt_reg *cmd =
1844 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1845 enum i40e_status_code status;
1847 i40e_fill_default_direct_cmd_desc(&desc,
1848 i40e_aqc_opc_get_local_advt_reg);
1850 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1851 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1853 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1859 * i40e_aq_get_partner_advt
1860 * @hw: pointer to the hw struct
1861 * @advt_reg: AN partner advertisement register value
1862 * @cmd_details: pointer to command details structure or NULL
1864 * Get the link partner AN advertisement register value.
1866 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1868 struct i40e_asq_cmd_details *cmd_details)
1870 struct i40e_aq_desc desc;
1871 struct i40e_aqc_an_advt_reg *resp =
1872 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1873 enum i40e_status_code status;
1875 i40e_fill_default_direct_cmd_desc(&desc,
1876 i40e_aqc_opc_get_partner_advt);
1878 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1880 if (status != I40E_SUCCESS)
1881 goto aq_get_partner_advt_exit;
1883 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1884 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1886 aq_get_partner_advt_exit:
1891 * i40e_aq_set_lb_modes
1892 * @hw: pointer to the hw struct
1893 * @lb_modes: loopback mode to be set
1894 * @cmd_details: pointer to command details structure or NULL
1896 * Sets loopback modes.
1898 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1900 struct i40e_asq_cmd_details *cmd_details)
1902 struct i40e_aq_desc desc;
1903 struct i40e_aqc_set_lb_mode *cmd =
1904 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1905 enum i40e_status_code status;
1907 i40e_fill_default_direct_cmd_desc(&desc,
1908 i40e_aqc_opc_set_lb_modes);
1910 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1912 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1918 * i40e_aq_set_phy_debug
1919 * @hw: pointer to the hw struct
1920 * @cmd_flags: debug command flags
1921 * @cmd_details: pointer to command details structure or NULL
1923 * Reset the external PHY.
1925 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1926 struct i40e_asq_cmd_details *cmd_details)
1928 struct i40e_aq_desc desc;
1929 struct i40e_aqc_set_phy_debug *cmd =
1930 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1931 enum i40e_status_code status;
1933 i40e_fill_default_direct_cmd_desc(&desc,
1934 i40e_aqc_opc_set_phy_debug);
1936 cmd->command_flags = cmd_flags;
1938 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1945 * @hw: pointer to the hw struct
1946 * @vsi_ctx: pointer to a vsi context struct
1947 * @cmd_details: pointer to command details structure or NULL
1949 * Add a VSI context to the hardware.
1951 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1952 struct i40e_vsi_context *vsi_ctx,
1953 struct i40e_asq_cmd_details *cmd_details)
1955 struct i40e_aq_desc desc;
1956 struct i40e_aqc_add_get_update_vsi *cmd =
1957 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1958 struct i40e_aqc_add_get_update_vsi_completion *resp =
1959 (struct i40e_aqc_add_get_update_vsi_completion *)
1961 enum i40e_status_code status;
1963 i40e_fill_default_direct_cmd_desc(&desc,
1964 i40e_aqc_opc_add_vsi);
1966 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1967 cmd->connection_type = vsi_ctx->connection_type;
1968 cmd->vf_id = vsi_ctx->vf_num;
1969 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1971 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1973 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1974 sizeof(vsi_ctx->info), cmd_details);
1976 if (status != I40E_SUCCESS)
1977 goto aq_add_vsi_exit;
1979 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1980 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1981 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1982 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1989 * i40e_aq_set_default_vsi
1990 * @hw: pointer to the hw struct
1992 * @cmd_details: pointer to command details structure or NULL
1994 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1996 struct i40e_asq_cmd_details *cmd_details)
1998 struct i40e_aq_desc desc;
1999 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2000 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2002 enum i40e_status_code status;
2004 i40e_fill_default_direct_cmd_desc(&desc,
2005 i40e_aqc_opc_set_vsi_promiscuous_modes);
2007 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2008 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2009 cmd->seid = CPU_TO_LE16(seid);
2011 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2017 * i40e_aq_set_vsi_unicast_promiscuous
2018 * @hw: pointer to the hw struct
2020 * @set: set unicast promiscuous enable/disable
2021 * @cmd_details: pointer to command details structure or NULL
2023 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2025 struct i40e_asq_cmd_details *cmd_details)
2027 struct i40e_aq_desc desc;
2028 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2029 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2030 enum i40e_status_code status;
2033 i40e_fill_default_direct_cmd_desc(&desc,
2034 i40e_aqc_opc_set_vsi_promiscuous_modes);
2037 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2039 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2041 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2043 cmd->seid = CPU_TO_LE16(seid);
2044 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2050 * i40e_aq_set_vsi_multicast_promiscuous
2051 * @hw: pointer to the hw struct
2053 * @set: set multicast promiscuous enable/disable
2054 * @cmd_details: pointer to command details structure or NULL
2056 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2057 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2059 struct i40e_aq_desc desc;
2060 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2061 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2062 enum i40e_status_code status;
2065 i40e_fill_default_direct_cmd_desc(&desc,
2066 i40e_aqc_opc_set_vsi_promiscuous_modes);
2069 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2071 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2073 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2075 cmd->seid = CPU_TO_LE16(seid);
2076 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2082 * i40e_aq_set_vsi_mc_promisc_on_vlan
2083 * @hw: pointer to the hw struct
2085 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2086 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2087 * @cmd_details: pointer to command details structure or NULL
2089 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2090 u16 seid, bool enable, u16 vid,
2091 struct i40e_asq_cmd_details *cmd_details)
2093 struct i40e_aq_desc desc;
2094 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2095 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2096 enum i40e_status_code status;
2099 i40e_fill_default_direct_cmd_desc(&desc,
2100 i40e_aqc_opc_set_vsi_promiscuous_modes);
2103 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2105 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2106 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2107 cmd->seid = CPU_TO_LE16(seid);
2108 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2116 * i40e_aq_set_vsi_uc_promisc_on_vlan
2117 * @hw: pointer to the hw struct
2119 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2120 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2121 * @cmd_details: pointer to command details structure or NULL
2123 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2124 u16 seid, bool enable, u16 vid,
2125 struct i40e_asq_cmd_details *cmd_details)
2127 struct i40e_aq_desc desc;
2128 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2129 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2130 enum i40e_status_code status;
2133 i40e_fill_default_direct_cmd_desc(&desc,
2134 i40e_aqc_opc_set_vsi_promiscuous_modes);
2137 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2139 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2140 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2141 cmd->seid = CPU_TO_LE16(seid);
2142 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2150 * i40e_aq_set_vsi_broadcast
2151 * @hw: pointer to the hw struct
2153 * @set_filter: true to set filter, false to clear filter
2154 * @cmd_details: pointer to command details structure or NULL
2156 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2158 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2159 u16 seid, bool set_filter,
2160 struct i40e_asq_cmd_details *cmd_details)
2162 struct i40e_aq_desc desc;
2163 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2164 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2165 enum i40e_status_code status;
2167 i40e_fill_default_direct_cmd_desc(&desc,
2168 i40e_aqc_opc_set_vsi_promiscuous_modes);
2171 cmd->promiscuous_flags
2172 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2174 cmd->promiscuous_flags
2175 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2177 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2178 cmd->seid = CPU_TO_LE16(seid);
2179 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2185 * i40e_get_vsi_params - get VSI configuration info
2186 * @hw: pointer to the hw struct
2187 * @vsi_ctx: pointer to a vsi context struct
2188 * @cmd_details: pointer to command details structure or NULL
2190 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2191 struct i40e_vsi_context *vsi_ctx,
2192 struct i40e_asq_cmd_details *cmd_details)
2194 struct i40e_aq_desc desc;
2195 struct i40e_aqc_add_get_update_vsi *cmd =
2196 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2197 struct i40e_aqc_add_get_update_vsi_completion *resp =
2198 (struct i40e_aqc_add_get_update_vsi_completion *)
2200 enum i40e_status_code status;
2202 UNREFERENCED_1PARAMETER(cmd_details);
2203 i40e_fill_default_direct_cmd_desc(&desc,
2204 i40e_aqc_opc_get_vsi_parameters);
2206 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2208 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2210 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2211 sizeof(vsi_ctx->info), NULL);
2213 if (status != I40E_SUCCESS)
2214 goto aq_get_vsi_params_exit;
2216 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2217 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2218 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2219 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2221 aq_get_vsi_params_exit:
2226 * i40e_aq_update_vsi_params
2227 * @hw: pointer to the hw struct
2228 * @vsi_ctx: pointer to a vsi context struct
2229 * @cmd_details: pointer to command details structure or NULL
2231 * Update a VSI context.
2233 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2234 struct i40e_vsi_context *vsi_ctx,
2235 struct i40e_asq_cmd_details *cmd_details)
2237 struct i40e_aq_desc desc;
2238 struct i40e_aqc_add_get_update_vsi *cmd =
2239 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2240 enum i40e_status_code status;
2242 i40e_fill_default_direct_cmd_desc(&desc,
2243 i40e_aqc_opc_update_vsi_parameters);
2244 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2246 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2248 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2249 sizeof(vsi_ctx->info), cmd_details);
2255 * i40e_aq_get_switch_config
2256 * @hw: pointer to the hardware structure
2257 * @buf: pointer to the result buffer
2258 * @buf_size: length of input buffer
2259 * @start_seid: seid to start for the report, 0 == beginning
2260 * @cmd_details: pointer to command details structure or NULL
2262 * Fill the buf with switch configuration returned from AdminQ command
2264 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2265 struct i40e_aqc_get_switch_config_resp *buf,
2266 u16 buf_size, u16 *start_seid,
2267 struct i40e_asq_cmd_details *cmd_details)
2269 struct i40e_aq_desc desc;
2270 struct i40e_aqc_switch_seid *scfg =
2271 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2272 enum i40e_status_code status;
2274 i40e_fill_default_direct_cmd_desc(&desc,
2275 i40e_aqc_opc_get_switch_config);
2276 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2277 if (buf_size > I40E_AQ_LARGE_BUF)
2278 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2279 scfg->seid = CPU_TO_LE16(*start_seid);
2281 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2282 *start_seid = LE16_TO_CPU(scfg->seid);
2288 * i40e_aq_get_firmware_version
2289 * @hw: pointer to the hw struct
2290 * @fw_major_version: firmware major version
2291 * @fw_minor_version: firmware minor version
2292 * @fw_build: firmware build number
2293 * @api_major_version: major queue version
2294 * @api_minor_version: minor queue version
2295 * @cmd_details: pointer to command details structure or NULL
2297 * Get the firmware version from the admin queue commands
2299 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2300 u16 *fw_major_version, u16 *fw_minor_version,
2302 u16 *api_major_version, u16 *api_minor_version,
2303 struct i40e_asq_cmd_details *cmd_details)
2305 struct i40e_aq_desc desc;
2306 struct i40e_aqc_get_version *resp =
2307 (struct i40e_aqc_get_version *)&desc.params.raw;
2308 enum i40e_status_code status;
2310 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2312 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2314 if (status == I40E_SUCCESS) {
2315 if (fw_major_version != NULL)
2316 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2317 if (fw_minor_version != NULL)
2318 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2319 if (fw_build != NULL)
2320 *fw_build = LE32_TO_CPU(resp->fw_build);
2321 if (api_major_version != NULL)
2322 *api_major_version = LE16_TO_CPU(resp->api_major);
2323 if (api_minor_version != NULL)
2324 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2326 /* A workaround to fix the API version in SW */
2327 if (api_major_version && api_minor_version &&
2328 fw_major_version && fw_minor_version &&
2329 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2330 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2331 (*fw_major_version > 4)))
2332 *api_minor_version = 2;
2339 * i40e_aq_send_driver_version
2340 * @hw: pointer to the hw struct
2341 * @dv: driver's major, minor version
2342 * @cmd_details: pointer to command details structure or NULL
2344 * Send the driver version to the firmware
2346 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2347 struct i40e_driver_version *dv,
2348 struct i40e_asq_cmd_details *cmd_details)
2350 struct i40e_aq_desc desc;
2351 struct i40e_aqc_driver_version *cmd =
2352 (struct i40e_aqc_driver_version *)&desc.params.raw;
2353 enum i40e_status_code status;
2357 return I40E_ERR_PARAM;
2359 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2361 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2362 cmd->driver_major_ver = dv->major_version;
2363 cmd->driver_minor_ver = dv->minor_version;
2364 cmd->driver_build_ver = dv->build_version;
2365 cmd->driver_subbuild_ver = dv->subbuild_version;
2368 while (len < sizeof(dv->driver_string) &&
2369 (dv->driver_string[len] < 0x80) &&
2370 dv->driver_string[len])
2372 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2379 * i40e_get_link_status - get status of the HW network link
2380 * @hw: pointer to the hw struct
2381 * @link_up: pointer to bool (true/false = linkup/linkdown)
2383 * Variable link_up true if link is up, false if link is down.
2384 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2386 * Side effect: LinkStatusEvent reporting becomes enabled
2388 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2390 enum i40e_status_code status = I40E_SUCCESS;
2392 if (hw->phy.get_link_info) {
2393 status = i40e_update_link_info(hw);
2395 if (status != I40E_SUCCESS)
2396 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2400 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2406 * i40e_updatelink_status - update status of the HW network link
2407 * @hw: pointer to the hw struct
2409 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2411 struct i40e_aq_get_phy_abilities_resp abilities;
2412 enum i40e_status_code status = I40E_SUCCESS;
2414 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2418 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2423 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2424 sizeof(hw->phy.link_info.module_type));
2430 * i40e_get_link_speed
2431 * @hw: pointer to the hw struct
2433 * Returns the link speed of the adapter.
2435 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2437 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2438 enum i40e_status_code status = I40E_SUCCESS;
2440 if (hw->phy.get_link_info) {
2441 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2443 if (status != I40E_SUCCESS)
2444 goto i40e_link_speed_exit;
2447 speed = hw->phy.link_info.link_speed;
2449 i40e_link_speed_exit:
2454 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2455 * @hw: pointer to the hw struct
2456 * @uplink_seid: the MAC or other gizmo SEID
2457 * @downlink_seid: the VSI SEID
2458 * @enabled_tc: bitmap of TCs to be enabled
2459 * @default_port: true for default port VSI, false for control port
2460 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2461 * @veb_seid: pointer to where to put the resulting VEB SEID
2462 * @cmd_details: pointer to command details structure or NULL
2464 * This asks the FW to add a VEB between the uplink and downlink
2465 * elements. If the uplink SEID is 0, this will be a floating VEB.
2467 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2468 u16 downlink_seid, u8 enabled_tc,
2469 bool default_port, bool enable_l2_filtering,
2471 struct i40e_asq_cmd_details *cmd_details)
2473 struct i40e_aq_desc desc;
2474 struct i40e_aqc_add_veb *cmd =
2475 (struct i40e_aqc_add_veb *)&desc.params.raw;
2476 struct i40e_aqc_add_veb_completion *resp =
2477 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2478 enum i40e_status_code status;
2481 /* SEIDs need to either both be set or both be 0 for floating VEB */
2482 if (!!uplink_seid != !!downlink_seid)
2483 return I40E_ERR_PARAM;
2485 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2487 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2488 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2489 cmd->enable_tcs = enabled_tc;
2491 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2493 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2495 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2497 if (enable_l2_filtering)
2498 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2500 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2502 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2504 if (!status && veb_seid)
2505 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2511 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2512 * @hw: pointer to the hw struct
2513 * @veb_seid: the SEID of the VEB to query
2514 * @switch_id: the uplink switch id
2515 * @floating: set to true if the VEB is floating
2516 * @statistic_index: index of the stats counter block for this VEB
2517 * @vebs_used: number of VEB's used by function
2518 * @vebs_free: total VEB's not reserved by any function
2519 * @cmd_details: pointer to command details structure or NULL
2521 * This retrieves the parameters for a particular VEB, specified by
2522 * uplink_seid, and returns them to the caller.
2524 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2525 u16 veb_seid, u16 *switch_id,
2526 bool *floating, u16 *statistic_index,
2527 u16 *vebs_used, u16 *vebs_free,
2528 struct i40e_asq_cmd_details *cmd_details)
2530 struct i40e_aq_desc desc;
2531 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2532 (struct i40e_aqc_get_veb_parameters_completion *)
2534 enum i40e_status_code status;
2537 return I40E_ERR_PARAM;
2539 i40e_fill_default_direct_cmd_desc(&desc,
2540 i40e_aqc_opc_get_veb_parameters);
2541 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2543 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2548 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2549 if (statistic_index)
2550 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2552 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2554 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2556 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2557 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2568 * i40e_aq_add_macvlan
2569 * @hw: pointer to the hw struct
2570 * @seid: VSI for the mac address
2571 * @mv_list: list of macvlans to be added
2572 * @count: length of the list
2573 * @cmd_details: pointer to command details structure or NULL
2575 * Add MAC/VLAN addresses to the HW filtering
2577 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2578 struct i40e_aqc_add_macvlan_element_data *mv_list,
2579 u16 count, struct i40e_asq_cmd_details *cmd_details)
2581 struct i40e_aq_desc desc;
2582 struct i40e_aqc_macvlan *cmd =
2583 (struct i40e_aqc_macvlan *)&desc.params.raw;
2584 enum i40e_status_code status;
2587 if (count == 0 || !mv_list || !hw)
2588 return I40E_ERR_PARAM;
2590 buf_size = count * sizeof(*mv_list);
2592 /* prep the rest of the request */
2593 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2594 cmd->num_addresses = CPU_TO_LE16(count);
2595 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2599 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2600 if (buf_size > I40E_AQ_LARGE_BUF)
2601 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2603 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2610 * i40e_aq_remove_macvlan
2611 * @hw: pointer to the hw struct
2612 * @seid: VSI for the mac address
2613 * @mv_list: list of macvlans to be removed
2614 * @count: length of the list
2615 * @cmd_details: pointer to command details structure or NULL
2617 * Remove MAC/VLAN addresses from the HW filtering
2619 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2620 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2621 u16 count, struct i40e_asq_cmd_details *cmd_details)
2623 struct i40e_aq_desc desc;
2624 struct i40e_aqc_macvlan *cmd =
2625 (struct i40e_aqc_macvlan *)&desc.params.raw;
2626 enum i40e_status_code status;
2629 if (count == 0 || !mv_list || !hw)
2630 return I40E_ERR_PARAM;
2632 buf_size = count * sizeof(*mv_list);
2634 /* prep the rest of the request */
2635 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2636 cmd->num_addresses = CPU_TO_LE16(count);
2637 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2641 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2642 if (buf_size > I40E_AQ_LARGE_BUF)
2643 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2645 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2652 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2653 * @hw: pointer to the hw struct
2654 * @seid: VSI for the vlan filters
2655 * @v_list: list of vlan filters to be added
2656 * @count: length of the list
2657 * @cmd_details: pointer to command details structure or NULL
2659 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2660 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2661 u8 count, struct i40e_asq_cmd_details *cmd_details)
2663 struct i40e_aq_desc desc;
2664 struct i40e_aqc_macvlan *cmd =
2665 (struct i40e_aqc_macvlan *)&desc.params.raw;
2666 enum i40e_status_code status;
2669 if (count == 0 || !v_list || !hw)
2670 return I40E_ERR_PARAM;
2672 buf_size = count * sizeof(*v_list);
2674 /* prep the rest of the request */
2675 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2676 cmd->num_addresses = CPU_TO_LE16(count);
2677 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2681 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2682 if (buf_size > I40E_AQ_LARGE_BUF)
2683 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2685 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2692 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2693 * @hw: pointer to the hw struct
2694 * @seid: VSI for the vlan filters
2695 * @v_list: list of macvlans to be removed
2696 * @count: length of the list
2697 * @cmd_details: pointer to command details structure or NULL
2699 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2700 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2701 u8 count, struct i40e_asq_cmd_details *cmd_details)
2703 struct i40e_aq_desc desc;
2704 struct i40e_aqc_macvlan *cmd =
2705 (struct i40e_aqc_macvlan *)&desc.params.raw;
2706 enum i40e_status_code status;
2709 if (count == 0 || !v_list || !hw)
2710 return I40E_ERR_PARAM;
2712 buf_size = count * sizeof(*v_list);
2714 /* prep the rest of the request */
2715 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2716 cmd->num_addresses = CPU_TO_LE16(count);
2717 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2721 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2722 if (buf_size > I40E_AQ_LARGE_BUF)
2723 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2725 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2732 * i40e_aq_send_msg_to_vf
2733 * @hw: pointer to the hardware structure
2734 * @vfid: vf id to send msg
2735 * @v_opcode: opcodes for VF-PF communication
2736 * @v_retval: return error code
2737 * @msg: pointer to the msg buffer
2738 * @msglen: msg length
2739 * @cmd_details: pointer to command details
2743 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2744 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2745 struct i40e_asq_cmd_details *cmd_details)
2747 struct i40e_aq_desc desc;
2748 struct i40e_aqc_pf_vf_message *cmd =
2749 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2750 enum i40e_status_code status;
2752 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2753 cmd->id = CPU_TO_LE32(vfid);
2754 desc.cookie_high = CPU_TO_LE32(v_opcode);
2755 desc.cookie_low = CPU_TO_LE32(v_retval);
2756 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2758 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2760 if (msglen > I40E_AQ_LARGE_BUF)
2761 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2762 desc.datalen = CPU_TO_LE16(msglen);
2764 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2770 * i40e_aq_debug_read_register
2771 * @hw: pointer to the hw struct
2772 * @reg_addr: register address
2773 * @reg_val: register value
2774 * @cmd_details: pointer to command details structure or NULL
2776 * Read the register using the admin queue commands
2778 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2779 u32 reg_addr, u64 *reg_val,
2780 struct i40e_asq_cmd_details *cmd_details)
2782 struct i40e_aq_desc desc;
2783 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2784 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2785 enum i40e_status_code status;
2787 if (reg_val == NULL)
2788 return I40E_ERR_PARAM;
2790 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2792 cmd_resp->address = CPU_TO_LE32(reg_addr);
2794 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2796 if (status == I40E_SUCCESS) {
2797 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2798 (u64)LE32_TO_CPU(cmd_resp->value_low);
2805 * i40e_aq_debug_write_register
2806 * @hw: pointer to the hw struct
2807 * @reg_addr: register address
2808 * @reg_val: register value
2809 * @cmd_details: pointer to command details structure or NULL
2811 * Write to a register using the admin queue commands
2813 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2814 u32 reg_addr, u64 reg_val,
2815 struct i40e_asq_cmd_details *cmd_details)
2817 struct i40e_aq_desc desc;
2818 struct i40e_aqc_debug_reg_read_write *cmd =
2819 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2820 enum i40e_status_code status;
2822 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2824 cmd->address = CPU_TO_LE32(reg_addr);
2825 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2826 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2828 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2834 * i40e_aq_get_hmc_resource_profile
2835 * @hw: pointer to the hw struct
2836 * @profile: type of profile the HMC is to be set as
2837 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2838 * @cmd_details: pointer to command details structure or NULL
2840 * query the HMC profile of the device.
2842 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2843 enum i40e_aq_hmc_profile *profile,
2844 u8 *pe_vf_enabled_count,
2845 struct i40e_asq_cmd_details *cmd_details)
2847 struct i40e_aq_desc desc;
2848 struct i40e_aq_get_set_hmc_resource_profile *resp =
2849 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2850 enum i40e_status_code status;
2852 i40e_fill_default_direct_cmd_desc(&desc,
2853 i40e_aqc_opc_query_hmc_resource_profile);
2854 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2856 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2857 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2858 *pe_vf_enabled_count = resp->pe_vf_enabled &
2859 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2865 * i40e_aq_set_hmc_resource_profile
2866 * @hw: pointer to the hw struct
2867 * @profile: type of profile the HMC is to be set as
2868 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2869 * @cmd_details: pointer to command details structure or NULL
2871 * set the HMC profile of the device.
2873 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2874 enum i40e_aq_hmc_profile profile,
2875 u8 pe_vf_enabled_count,
2876 struct i40e_asq_cmd_details *cmd_details)
2878 struct i40e_aq_desc desc;
2879 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2880 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2881 enum i40e_status_code status;
2883 i40e_fill_default_direct_cmd_desc(&desc,
2884 i40e_aqc_opc_set_hmc_resource_profile);
2886 cmd->pm_profile = (u8)profile;
2887 cmd->pe_vf_enabled = pe_vf_enabled_count;
2889 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2895 * i40e_aq_request_resource
2896 * @hw: pointer to the hw struct
2897 * @resource: resource id
2898 * @access: access type
2899 * @sdp_number: resource number
2900 * @timeout: the maximum time in ms that the driver may hold the resource
2901 * @cmd_details: pointer to command details structure or NULL
2903 * requests common resource using the admin queue commands
2905 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2906 enum i40e_aq_resources_ids resource,
2907 enum i40e_aq_resource_access_type access,
2908 u8 sdp_number, u64 *timeout,
2909 struct i40e_asq_cmd_details *cmd_details)
2911 struct i40e_aq_desc desc;
2912 struct i40e_aqc_request_resource *cmd_resp =
2913 (struct i40e_aqc_request_resource *)&desc.params.raw;
2914 enum i40e_status_code status;
2916 DEBUGFUNC("i40e_aq_request_resource");
2918 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2920 cmd_resp->resource_id = CPU_TO_LE16(resource);
2921 cmd_resp->access_type = CPU_TO_LE16(access);
2922 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2924 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2925 /* The completion specifies the maximum time in ms that the driver
2926 * may hold the resource in the Timeout field.
2927 * If the resource is held by someone else, the command completes with
2928 * busy return value and the timeout field indicates the maximum time
2929 * the current owner of the resource has to free it.
2931 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2932 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2938 * i40e_aq_release_resource
2939 * @hw: pointer to the hw struct
2940 * @resource: resource id
2941 * @sdp_number: resource number
2942 * @cmd_details: pointer to command details structure or NULL
2944 * release common resource using the admin queue commands
2946 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2947 enum i40e_aq_resources_ids resource,
2949 struct i40e_asq_cmd_details *cmd_details)
2951 struct i40e_aq_desc desc;
2952 struct i40e_aqc_request_resource *cmd =
2953 (struct i40e_aqc_request_resource *)&desc.params.raw;
2954 enum i40e_status_code status;
2956 DEBUGFUNC("i40e_aq_release_resource");
2958 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2960 cmd->resource_id = CPU_TO_LE16(resource);
2961 cmd->resource_number = CPU_TO_LE32(sdp_number);
2963 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2970 * @hw: pointer to the hw struct
2971 * @module_pointer: module pointer location in words from the NVM beginning
2972 * @offset: byte offset from the module beginning
2973 * @length: length of the section to be read (in bytes from the offset)
2974 * @data: command buffer (size [bytes] = length)
2975 * @last_command: tells if this is the last command in a series
2976 * @cmd_details: pointer to command details structure or NULL
2978 * Read the NVM using the admin queue commands
2980 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2981 u32 offset, u16 length, void *data,
2983 struct i40e_asq_cmd_details *cmd_details)
2985 struct i40e_aq_desc desc;
2986 struct i40e_aqc_nvm_update *cmd =
2987 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2988 enum i40e_status_code status;
2990 DEBUGFUNC("i40e_aq_read_nvm");
2992 /* In offset the highest byte must be zeroed. */
2993 if (offset & 0xFF000000) {
2994 status = I40E_ERR_PARAM;
2995 goto i40e_aq_read_nvm_exit;
2998 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3000 /* If this is the last command in a series, set the proper flag. */
3002 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3003 cmd->module_pointer = module_pointer;
3004 cmd->offset = CPU_TO_LE32(offset);
3005 cmd->length = CPU_TO_LE16(length);
3007 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3008 if (length > I40E_AQ_LARGE_BUF)
3009 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3011 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3013 i40e_aq_read_nvm_exit:
3018 * i40e_aq_read_nvm_config - read an nvm config block
3019 * @hw: pointer to the hw struct
3020 * @cmd_flags: NVM access admin command bits
3021 * @field_id: field or feature id
3022 * @data: buffer for result
3023 * @buf_size: buffer size
3024 * @element_count: pointer to count of elements read by FW
3025 * @cmd_details: pointer to command details structure or NULL
3027 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3028 u8 cmd_flags, u32 field_id, void *data,
3029 u16 buf_size, u16 *element_count,
3030 struct i40e_asq_cmd_details *cmd_details)
3032 struct i40e_aq_desc desc;
3033 struct i40e_aqc_nvm_config_read *cmd =
3034 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3035 enum i40e_status_code status;
3037 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3038 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3039 if (buf_size > I40E_AQ_LARGE_BUF)
3040 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3042 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3043 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3044 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3045 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3047 cmd->element_id_msw = 0;
3049 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3051 if (!status && element_count)
3052 *element_count = LE16_TO_CPU(cmd->element_count);
3058 * i40e_aq_write_nvm_config - write an nvm config block
3059 * @hw: pointer to the hw struct
3060 * @cmd_flags: NVM access admin command bits
3061 * @data: buffer for result
3062 * @buf_size: buffer size
3063 * @element_count: count of elements to be written
3064 * @cmd_details: pointer to command details structure or NULL
3066 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3067 u8 cmd_flags, void *data, u16 buf_size,
3069 struct i40e_asq_cmd_details *cmd_details)
3071 struct i40e_aq_desc desc;
3072 struct i40e_aqc_nvm_config_write *cmd =
3073 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3074 enum i40e_status_code status;
3076 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3077 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3078 if (buf_size > I40E_AQ_LARGE_BUF)
3079 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3081 cmd->element_count = CPU_TO_LE16(element_count);
3082 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3083 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3089 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3090 * @hw: pointer to the hw struct
3091 * @cmd_details: pointer to command details structure or NULL
3093 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3094 void *buff, u16 buff_size,
3095 struct i40e_asq_cmd_details *cmd_details)
3097 struct i40e_aq_desc desc;
3098 enum i40e_status_code status;
3100 UNREFERENCED_2PARAMETER(buff, buff_size);
3102 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3103 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3104 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3105 status = I40E_ERR_NOT_IMPLEMENTED;
3112 * @hw: pointer to the hw struct
3113 * @module_pointer: module pointer location in words from the NVM beginning
3114 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3115 * @length: length of the section to be erased (expressed in 4 KB)
3116 * @last_command: tells if this is the last command in a series
3117 * @cmd_details: pointer to command details structure or NULL
3119 * Erase the NVM sector using the admin queue commands
3121 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3122 u32 offset, u16 length, bool last_command,
3123 struct i40e_asq_cmd_details *cmd_details)
3125 struct i40e_aq_desc desc;
3126 struct i40e_aqc_nvm_update *cmd =
3127 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3128 enum i40e_status_code status;
3130 DEBUGFUNC("i40e_aq_erase_nvm");
3132 /* In offset the highest byte must be zeroed. */
3133 if (offset & 0xFF000000) {
3134 status = I40E_ERR_PARAM;
3135 goto i40e_aq_erase_nvm_exit;
3138 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3140 /* If this is the last command in a series, set the proper flag. */
3142 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3143 cmd->module_pointer = module_pointer;
3144 cmd->offset = CPU_TO_LE32(offset);
3145 cmd->length = CPU_TO_LE16(length);
3147 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3149 i40e_aq_erase_nvm_exit:
3153 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3154 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3155 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3156 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3157 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3158 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3159 #define I40E_DEV_FUNC_CAP_VF 0x13
3160 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3161 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3162 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3163 #define I40E_DEV_FUNC_CAP_VSI 0x17
3164 #define I40E_DEV_FUNC_CAP_DCB 0x18
3165 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3166 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3167 #define I40E_DEV_FUNC_CAP_RSS 0x40
3168 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3169 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3170 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3171 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3172 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3173 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3174 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
3175 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3176 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3177 #define I40E_DEV_FUNC_CAP_LED 0x61
3178 #define I40E_DEV_FUNC_CAP_SDP 0x62
3179 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3182 * i40e_parse_discover_capabilities
3183 * @hw: pointer to the hw struct
3184 * @buff: pointer to a buffer containing device/function capability records
3185 * @cap_count: number of capability records in the list
3186 * @list_type_opc: type of capabilities list to parse
3188 * Parse the device/function capabilities list.
3190 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3192 enum i40e_admin_queue_opc list_type_opc)
3194 struct i40e_aqc_list_capabilities_element_resp *cap;
3195 u32 valid_functions, num_functions;
3196 u32 number, logical_id, phys_id;
3197 struct i40e_hw_capabilities *p;
3202 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3204 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3205 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3206 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3207 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3211 for (i = 0; i < cap_count; i++, cap++) {
3212 id = LE16_TO_CPU(cap->id);
3213 number = LE32_TO_CPU(cap->number);
3214 logical_id = LE32_TO_CPU(cap->logical_id);
3215 phys_id = LE32_TO_CPU(cap->phys_id);
3216 major_rev = cap->major_rev;
3219 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3220 p->switch_mode = number;
3222 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3223 p->management_mode = number;
3225 case I40E_DEV_FUNC_CAP_NPAR:
3226 p->npar_enable = number;
3228 case I40E_DEV_FUNC_CAP_OS2BMC:
3231 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3232 p->valid_functions = number;
3234 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3236 p->sr_iov_1_1 = true;
3238 case I40E_DEV_FUNC_CAP_VF:
3239 p->num_vfs = number;
3240 p->vf_base_id = logical_id;
3242 case I40E_DEV_FUNC_CAP_VMDQ:
3246 case I40E_DEV_FUNC_CAP_802_1_QBG:
3248 p->evb_802_1_qbg = true;
3250 case I40E_DEV_FUNC_CAP_802_1_QBH:
3252 p->evb_802_1_qbh = true;
3254 case I40E_DEV_FUNC_CAP_VSI:
3255 p->num_vsis = number;
3257 case I40E_DEV_FUNC_CAP_DCB:
3260 p->enabled_tcmap = logical_id;
3264 case I40E_DEV_FUNC_CAP_FCOE:
3268 case I40E_DEV_FUNC_CAP_ISCSI:
3272 case I40E_DEV_FUNC_CAP_RSS:
3274 p->rss_table_size = number;
3275 p->rss_table_entry_width = logical_id;
3277 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3278 p->num_rx_qp = number;
3279 p->base_queue = phys_id;
3281 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3282 p->num_tx_qp = number;
3283 p->base_queue = phys_id;
3285 case I40E_DEV_FUNC_CAP_MSIX:
3286 p->num_msix_vectors = number;
3288 case I40E_DEV_FUNC_CAP_MSIX_VF:
3289 p->num_msix_vectors_vf = number;
3291 case I40E_DEV_FUNC_CAP_FLEX10:
3292 if (major_rev == 1) {
3294 p->flex10_enable = true;
3295 p->flex10_capable = true;
3298 /* Capability revision >= 2 */
3300 p->flex10_enable = true;
3302 p->flex10_capable = true;
3304 p->flex10_mode = logical_id;
3305 p->flex10_status = phys_id;
3307 case I40E_DEV_FUNC_CAP_CEM:
3311 case I40E_DEV_FUNC_CAP_IWARP:
3315 case I40E_DEV_FUNC_CAP_LED:
3316 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3317 p->led[phys_id] = true;
3319 case I40E_DEV_FUNC_CAP_SDP:
3320 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3321 p->sdp[phys_id] = true;
3323 case I40E_DEV_FUNC_CAP_MDIO:
3325 p->mdio_port_num = phys_id;
3326 p->mdio_port_mode = logical_id;
3329 case I40E_DEV_FUNC_CAP_IEEE_1588:
3331 p->ieee_1588 = true;
3333 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3335 p->fd_filters_guaranteed = number;
3336 p->fd_filters_best_effort = logical_id;
3344 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3346 #ifdef I40E_FCOE_ENA
3347 /* Software override ensuring FCoE is disabled if npar or mfp
3348 * mode because it is not supported in these modes.
3350 if (p->npar_enable || p->flex10_enable)
3353 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3357 /* count the enabled ports (aka the "not disabled" ports) */
3359 for (i = 0; i < 4; i++) {
3360 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3363 /* use AQ read to get the physical register offset instead
3364 * of the port relative offset
3366 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3367 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3371 valid_functions = p->valid_functions;
3373 while (valid_functions) {
3374 if (valid_functions & 1)
3376 valid_functions >>= 1;
3379 /* partition id is 1-based, and functions are evenly spread
3380 * across the ports as partitions
3382 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3383 hw->num_partitions = num_functions / hw->num_ports;
3385 /* additional HW specific goodies that might
3386 * someday be HW version specific
3388 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3392 * i40e_aq_discover_capabilities
3393 * @hw: pointer to the hw struct
3394 * @buff: a virtual buffer to hold the capabilities
3395 * @buff_size: Size of the virtual buffer
3396 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3397 * @list_type_opc: capabilities type to discover - pass in the command opcode
3398 * @cmd_details: pointer to command details structure or NULL
3400 * Get the device capabilities descriptions from the firmware
3402 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3403 void *buff, u16 buff_size, u16 *data_size,
3404 enum i40e_admin_queue_opc list_type_opc,
3405 struct i40e_asq_cmd_details *cmd_details)
3407 struct i40e_aqc_list_capabilites *cmd;
3408 struct i40e_aq_desc desc;
3409 enum i40e_status_code status = I40E_SUCCESS;
3411 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3413 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3414 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3415 status = I40E_ERR_PARAM;
3419 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3421 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3422 if (buff_size > I40E_AQ_LARGE_BUF)
3423 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3425 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3426 *data_size = LE16_TO_CPU(desc.datalen);
3431 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3439 * i40e_aq_update_nvm
3440 * @hw: pointer to the hw struct
3441 * @module_pointer: module pointer location in words from the NVM beginning
3442 * @offset: byte offset from the module beginning
3443 * @length: length of the section to be written (in bytes from the offset)
3444 * @data: command buffer (size [bytes] = length)
3445 * @last_command: tells if this is the last command in a series
3446 * @cmd_details: pointer to command details structure or NULL
3448 * Update the NVM using the admin queue commands
3450 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3451 u32 offset, u16 length, void *data,
3453 struct i40e_asq_cmd_details *cmd_details)
3455 struct i40e_aq_desc desc;
3456 struct i40e_aqc_nvm_update *cmd =
3457 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3458 enum i40e_status_code status;
3460 DEBUGFUNC("i40e_aq_update_nvm");
3462 /* In offset the highest byte must be zeroed. */
3463 if (offset & 0xFF000000) {
3464 status = I40E_ERR_PARAM;
3465 goto i40e_aq_update_nvm_exit;
3468 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3470 /* If this is the last command in a series, set the proper flag. */
3472 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3473 cmd->module_pointer = module_pointer;
3474 cmd->offset = CPU_TO_LE32(offset);
3475 cmd->length = CPU_TO_LE16(length);
3477 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3478 if (length > I40E_AQ_LARGE_BUF)
3479 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3481 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3483 i40e_aq_update_nvm_exit:
3488 * i40e_aq_get_lldp_mib
3489 * @hw: pointer to the hw struct
3490 * @bridge_type: type of bridge requested
3491 * @mib_type: Local, Remote or both Local and Remote MIBs
3492 * @buff: pointer to a user supplied buffer to store the MIB block
3493 * @buff_size: size of the buffer (in bytes)
3494 * @local_len : length of the returned Local LLDP MIB
3495 * @remote_len: length of the returned Remote LLDP MIB
3496 * @cmd_details: pointer to command details structure or NULL
3498 * Requests the complete LLDP MIB (entire packet).
3500 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3501 u8 mib_type, void *buff, u16 buff_size,
3502 u16 *local_len, u16 *remote_len,
3503 struct i40e_asq_cmd_details *cmd_details)
3505 struct i40e_aq_desc desc;
3506 struct i40e_aqc_lldp_get_mib *cmd =
3507 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3508 struct i40e_aqc_lldp_get_mib *resp =
3509 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3510 enum i40e_status_code status;
3512 if (buff_size == 0 || !buff)
3513 return I40E_ERR_PARAM;
3515 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3516 /* Indirect Command */
3517 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3519 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3520 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3521 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3523 desc.datalen = CPU_TO_LE16(buff_size);
3525 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3526 if (buff_size > I40E_AQ_LARGE_BUF)
3527 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3529 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3531 if (local_len != NULL)
3532 *local_len = LE16_TO_CPU(resp->local_len);
3533 if (remote_len != NULL)
3534 *remote_len = LE16_TO_CPU(resp->remote_len);
3541 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3542 * @hw: pointer to the hw struct
3543 * @mib_type: Local, Remote or both Local and Remote MIBs
3544 * @buff: pointer to a user supplied buffer to store the MIB block
3545 * @buff_size: size of the buffer (in bytes)
3546 * @cmd_details: pointer to command details structure or NULL
3550 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3551 u8 mib_type, void *buff, u16 buff_size,
3552 struct i40e_asq_cmd_details *cmd_details)
3554 struct i40e_aq_desc desc;
3555 struct i40e_aqc_lldp_set_local_mib *cmd =
3556 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3557 enum i40e_status_code status;
3559 if (buff_size == 0 || !buff)
3560 return I40E_ERR_PARAM;
3562 i40e_fill_default_direct_cmd_desc(&desc,
3563 i40e_aqc_opc_lldp_set_local_mib);
3564 /* Indirect Command */
3565 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3566 if (buff_size > I40E_AQ_LARGE_BUF)
3567 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3568 desc.datalen = CPU_TO_LE16(buff_size);
3570 cmd->type = mib_type;
3571 cmd->length = CPU_TO_LE16(buff_size);
3572 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3573 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3575 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3580 * i40e_aq_cfg_lldp_mib_change_event
3581 * @hw: pointer to the hw struct
3582 * @enable_update: Enable or Disable event posting
3583 * @cmd_details: pointer to command details structure or NULL
3585 * Enable or Disable posting of an event on ARQ when LLDP MIB
3586 * associated with the interface changes
3588 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3590 struct i40e_asq_cmd_details *cmd_details)
3592 struct i40e_aq_desc desc;
3593 struct i40e_aqc_lldp_update_mib *cmd =
3594 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3595 enum i40e_status_code status;
3597 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3600 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3602 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3608 * i40e_aq_add_lldp_tlv
3609 * @hw: pointer to the hw struct
3610 * @bridge_type: type of bridge
3611 * @buff: buffer with TLV to add
3612 * @buff_size: length of the buffer
3613 * @tlv_len: length of the TLV to be added
3614 * @mib_len: length of the LLDP MIB returned in response
3615 * @cmd_details: pointer to command details structure or NULL
3617 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3618 * it is responsibility of the caller to make sure that the TLV is not
3619 * already present in the LLDPDU.
3620 * In return firmware will write the complete LLDP MIB with the newly
3621 * added TLV in the response buffer.
3623 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3624 void *buff, u16 buff_size, u16 tlv_len,
3626 struct i40e_asq_cmd_details *cmd_details)
3628 struct i40e_aq_desc desc;
3629 struct i40e_aqc_lldp_add_tlv *cmd =
3630 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3631 enum i40e_status_code status;
3633 if (buff_size == 0 || !buff || tlv_len == 0)
3634 return I40E_ERR_PARAM;
3636 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3638 /* Indirect Command */
3639 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3640 if (buff_size > I40E_AQ_LARGE_BUF)
3641 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3642 desc.datalen = CPU_TO_LE16(buff_size);
3644 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3645 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3646 cmd->len = CPU_TO_LE16(tlv_len);
3648 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3650 if (mib_len != NULL)
3651 *mib_len = LE16_TO_CPU(desc.datalen);
3658 * i40e_aq_update_lldp_tlv
3659 * @hw: pointer to the hw struct
3660 * @bridge_type: type of bridge
3661 * @buff: buffer with TLV to update
3662 * @buff_size: size of the buffer holding original and updated TLVs
3663 * @old_len: Length of the Original TLV
3664 * @new_len: Length of the Updated TLV
3665 * @offset: offset of the updated TLV in the buff
3666 * @mib_len: length of the returned LLDP MIB
3667 * @cmd_details: pointer to command details structure or NULL
3669 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3670 * Firmware will place the complete LLDP MIB in response buffer with the
3673 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3674 u8 bridge_type, void *buff, u16 buff_size,
3675 u16 old_len, u16 new_len, u16 offset,
3677 struct i40e_asq_cmd_details *cmd_details)
3679 struct i40e_aq_desc desc;
3680 struct i40e_aqc_lldp_update_tlv *cmd =
3681 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3682 enum i40e_status_code status;
3684 if (buff_size == 0 || !buff || offset == 0 ||
3685 old_len == 0 || new_len == 0)
3686 return I40E_ERR_PARAM;
3688 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3690 /* Indirect Command */
3691 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3692 if (buff_size > I40E_AQ_LARGE_BUF)
3693 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3694 desc.datalen = CPU_TO_LE16(buff_size);
3696 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3697 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3698 cmd->old_len = CPU_TO_LE16(old_len);
3699 cmd->new_offset = CPU_TO_LE16(offset);
3700 cmd->new_len = CPU_TO_LE16(new_len);
3702 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3704 if (mib_len != NULL)
3705 *mib_len = LE16_TO_CPU(desc.datalen);
3712 * i40e_aq_delete_lldp_tlv
3713 * @hw: pointer to the hw struct
3714 * @bridge_type: type of bridge
3715 * @buff: pointer to a user supplied buffer that has the TLV
3716 * @buff_size: length of the buffer
3717 * @tlv_len: length of the TLV to be deleted
3718 * @mib_len: length of the returned LLDP MIB
3719 * @cmd_details: pointer to command details structure or NULL
3721 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3722 * The firmware places the entire LLDP MIB in the response buffer.
3724 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3725 u8 bridge_type, void *buff, u16 buff_size,
3726 u16 tlv_len, u16 *mib_len,
3727 struct i40e_asq_cmd_details *cmd_details)
3729 struct i40e_aq_desc desc;
3730 struct i40e_aqc_lldp_add_tlv *cmd =
3731 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3732 enum i40e_status_code status;
3734 if (buff_size == 0 || !buff)
3735 return I40E_ERR_PARAM;
3737 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3739 /* Indirect Command */
3740 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3741 if (buff_size > I40E_AQ_LARGE_BUF)
3742 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3743 desc.datalen = CPU_TO_LE16(buff_size);
3744 cmd->len = CPU_TO_LE16(tlv_len);
3745 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3746 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3748 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3750 if (mib_len != NULL)
3751 *mib_len = LE16_TO_CPU(desc.datalen);
3759 * @hw: pointer to the hw struct
3760 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3761 * @cmd_details: pointer to command details structure or NULL
3763 * Stop or Shutdown the embedded LLDP Agent
3765 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3766 struct i40e_asq_cmd_details *cmd_details)
3768 struct i40e_aq_desc desc;
3769 struct i40e_aqc_lldp_stop *cmd =
3770 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3771 enum i40e_status_code status;
3773 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3776 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3778 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3784 * i40e_aq_start_lldp
3785 * @hw: pointer to the hw struct
3786 * @cmd_details: pointer to command details structure or NULL
3788 * Start the embedded LLDP Agent on all ports.
3790 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3791 struct i40e_asq_cmd_details *cmd_details)
3793 struct i40e_aq_desc desc;
3794 struct i40e_aqc_lldp_start *cmd =
3795 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3796 enum i40e_status_code status;
3798 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3800 cmd->command = I40E_AQ_LLDP_AGENT_START;
3802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3808 * i40e_aq_get_cee_dcb_config
3809 * @hw: pointer to the hw struct
3810 * @buff: response buffer that stores CEE operational configuration
3811 * @buff_size: size of the buffer passed
3812 * @cmd_details: pointer to command details structure or NULL
3814 * Get CEE DCBX mode operational configuration from firmware
3816 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3817 void *buff, u16 buff_size,
3818 struct i40e_asq_cmd_details *cmd_details)
3820 struct i40e_aq_desc desc;
3821 enum i40e_status_code status;
3823 if (buff_size == 0 || !buff)
3824 return I40E_ERR_PARAM;
3826 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3828 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3829 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3836 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3837 * @hw: pointer to the hw struct
3838 * @start_agent: True if DCBx Agent needs to be Started
3839 * False if DCBx Agent needs to be Stopped
3840 * @cmd_details: pointer to command details structure or NULL
3842 * Start/Stop the embedded dcbx Agent
3844 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3846 struct i40e_asq_cmd_details *cmd_details)
3848 struct i40e_aq_desc desc;
3849 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3850 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3852 enum i40e_status_code status;
3854 i40e_fill_default_direct_cmd_desc(&desc,
3855 i40e_aqc_opc_lldp_stop_start_spec_agent);
3858 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3860 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3866 * i40e_aq_add_udp_tunnel
3867 * @hw: pointer to the hw struct
3868 * @udp_port: the UDP port to add
3869 * @header_len: length of the tunneling header length in DWords
3870 * @protocol_index: protocol index type
3871 * @filter_index: pointer to filter index
3872 * @cmd_details: pointer to command details structure or NULL
3874 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3875 u16 udp_port, u8 protocol_index,
3877 struct i40e_asq_cmd_details *cmd_details)
3879 struct i40e_aq_desc desc;
3880 struct i40e_aqc_add_udp_tunnel *cmd =
3881 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3882 struct i40e_aqc_del_udp_tunnel_completion *resp =
3883 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3884 enum i40e_status_code status;
3886 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3888 cmd->udp_port = CPU_TO_LE16(udp_port);
3889 cmd->protocol_type = protocol_index;
3891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3893 if (!status && filter_index)
3894 *filter_index = resp->index;
3900 * i40e_aq_del_udp_tunnel
3901 * @hw: pointer to the hw struct
3902 * @index: filter index
3903 * @cmd_details: pointer to command details structure or NULL
3905 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3906 struct i40e_asq_cmd_details *cmd_details)
3908 struct i40e_aq_desc desc;
3909 struct i40e_aqc_remove_udp_tunnel *cmd =
3910 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3911 enum i40e_status_code status;
3913 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3923 * i40e_aq_get_switch_resource_alloc (0x0204)
3924 * @hw: pointer to the hw struct
3925 * @num_entries: pointer to u8 to store the number of resource entries returned
3926 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3927 * to store the resource information for all resource types. Each
3928 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3929 * @count: size, in bytes, of the buffer provided
3930 * @cmd_details: pointer to command details structure or NULL
3932 * Query the resources allocated to a function.
3934 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3936 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3938 struct i40e_asq_cmd_details *cmd_details)
3940 struct i40e_aq_desc desc;
3941 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3942 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3943 enum i40e_status_code status;
3944 u16 length = count * sizeof(*buf);
3946 i40e_fill_default_direct_cmd_desc(&desc,
3947 i40e_aqc_opc_get_switch_resource_alloc);
3949 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3950 if (length > I40E_AQ_LARGE_BUF)
3951 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3953 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3955 if (!status && num_entries)
3956 *num_entries = cmd_resp->num_entries;
3962 * i40e_aq_delete_element - Delete switch element
3963 * @hw: pointer to the hw struct
3964 * @seid: the SEID to delete from the switch
3965 * @cmd_details: pointer to command details structure or NULL
3967 * This deletes a switch element from the switch.
3969 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3970 struct i40e_asq_cmd_details *cmd_details)
3972 struct i40e_aq_desc desc;
3973 struct i40e_aqc_switch_seid *cmd =
3974 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3975 enum i40e_status_code status;
3978 return I40E_ERR_PARAM;
3980 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3982 cmd->seid = CPU_TO_LE16(seid);
3984 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3990 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3991 * @hw: pointer to the hw struct
3992 * @flags: component flags
3993 * @mac_seid: uplink seid (MAC SEID)
3994 * @vsi_seid: connected vsi seid
3995 * @ret_seid: seid of create pv component
3997 * This instantiates an i40e port virtualizer with specified flags.
3998 * Depending on specified flags the port virtualizer can act as a
3999 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4001 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4002 u16 mac_seid, u16 vsi_seid,
4005 struct i40e_aq_desc desc;
4006 struct i40e_aqc_add_update_pv *cmd =
4007 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4008 struct i40e_aqc_add_update_pv_completion *resp =
4009 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4010 enum i40e_status_code status;
4013 return I40E_ERR_PARAM;
4015 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4016 cmd->command_flags = CPU_TO_LE16(flags);
4017 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4018 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4020 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4021 if (!status && ret_seid)
4022 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4028 * i40e_aq_add_tag - Add an S/E-tag
4029 * @hw: pointer to the hw struct
4030 * @direct_to_queue: should s-tag direct flow to a specific queue
4031 * @vsi_seid: VSI SEID to use this tag
4032 * @tag: value of the tag
4033 * @queue_num: queue number, only valid is direct_to_queue is true
4034 * @tags_used: return value, number of tags in use by this PF
4035 * @tags_free: return value, number of unallocated tags
4036 * @cmd_details: pointer to command details structure or NULL
4038 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4039 * the number of tags allocated by the PF, and the number of unallocated
4042 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4043 u16 vsi_seid, u16 tag, u16 queue_num,
4044 u16 *tags_used, u16 *tags_free,
4045 struct i40e_asq_cmd_details *cmd_details)
4047 struct i40e_aq_desc desc;
4048 struct i40e_aqc_add_tag *cmd =
4049 (struct i40e_aqc_add_tag *)&desc.params.raw;
4050 struct i40e_aqc_add_remove_tag_completion *resp =
4051 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4052 enum i40e_status_code status;
4055 return I40E_ERR_PARAM;
4057 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4059 cmd->seid = CPU_TO_LE16(vsi_seid);
4060 cmd->tag = CPU_TO_LE16(tag);
4061 if (direct_to_queue) {
4062 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4063 cmd->queue_number = CPU_TO_LE16(queue_num);
4066 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4069 if (tags_used != NULL)
4070 *tags_used = LE16_TO_CPU(resp->tags_used);
4071 if (tags_free != NULL)
4072 *tags_free = LE16_TO_CPU(resp->tags_free);
4079 * i40e_aq_remove_tag - Remove an S- or E-tag
4080 * @hw: pointer to the hw struct
4081 * @vsi_seid: VSI SEID this tag is associated with
4082 * @tag: value of the S-tag to delete
4083 * @tags_used: return value, number of tags in use by this PF
4084 * @tags_free: return value, number of unallocated tags
4085 * @cmd_details: pointer to command details structure or NULL
4087 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4088 * the number of tags allocated by the PF, and the number of unallocated
4091 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4092 u16 tag, u16 *tags_used, u16 *tags_free,
4093 struct i40e_asq_cmd_details *cmd_details)
4095 struct i40e_aq_desc desc;
4096 struct i40e_aqc_remove_tag *cmd =
4097 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4098 struct i40e_aqc_add_remove_tag_completion *resp =
4099 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4100 enum i40e_status_code status;
4103 return I40E_ERR_PARAM;
4105 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4107 cmd->seid = CPU_TO_LE16(vsi_seid);
4108 cmd->tag = CPU_TO_LE16(tag);
4110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4113 if (tags_used != NULL)
4114 *tags_used = LE16_TO_CPU(resp->tags_used);
4115 if (tags_free != NULL)
4116 *tags_free = LE16_TO_CPU(resp->tags_free);
4123 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4124 * @hw: pointer to the hw struct
4125 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4126 * @etag: value of E-tag to add
4127 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4128 * @buf: address of indirect buffer
4129 * @tags_used: return value, number of E-tags in use by this port
4130 * @tags_free: return value, number of unallocated M-tags
4131 * @cmd_details: pointer to command details structure or NULL
4133 * This associates a multicast E-tag to a port virtualizer. It will return
4134 * the number of tags allocated by the PF, and the number of unallocated
4137 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4138 * num_tags_in_buf long.
4140 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4141 u16 etag, u8 num_tags_in_buf, void *buf,
4142 u16 *tags_used, u16 *tags_free,
4143 struct i40e_asq_cmd_details *cmd_details)
4145 struct i40e_aq_desc desc;
4146 struct i40e_aqc_add_remove_mcast_etag *cmd =
4147 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4148 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4149 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4150 enum i40e_status_code status;
4151 u16 length = sizeof(u16) * num_tags_in_buf;
4153 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4154 return I40E_ERR_PARAM;
4156 i40e_fill_default_direct_cmd_desc(&desc,
4157 i40e_aqc_opc_add_multicast_etag);
4159 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4160 cmd->etag = CPU_TO_LE16(etag);
4161 cmd->num_unicast_etags = num_tags_in_buf;
4163 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4164 if (length > I40E_AQ_LARGE_BUF)
4165 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4167 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4170 if (tags_used != NULL)
4171 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4172 if (tags_free != NULL)
4173 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4180 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4181 * @hw: pointer to the hw struct
4182 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4183 * @etag: value of the E-tag to remove
4184 * @tags_used: return value, number of tags in use by this port
4185 * @tags_free: return value, number of unallocated tags
4186 * @cmd_details: pointer to command details structure or NULL
4188 * This deletes an E-tag from the port virtualizer. It will return
4189 * the number of tags allocated by the port, and the number of unallocated
4192 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4193 u16 etag, u16 *tags_used, u16 *tags_free,
4194 struct i40e_asq_cmd_details *cmd_details)
4196 struct i40e_aq_desc desc;
4197 struct i40e_aqc_add_remove_mcast_etag *cmd =
4198 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4199 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4200 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4201 enum i40e_status_code status;
4205 return I40E_ERR_PARAM;
4207 i40e_fill_default_direct_cmd_desc(&desc,
4208 i40e_aqc_opc_remove_multicast_etag);
4210 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4211 cmd->etag = CPU_TO_LE16(etag);
4213 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4216 if (tags_used != NULL)
4217 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4218 if (tags_free != NULL)
4219 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4226 * i40e_aq_update_tag - Update an S/E-tag
4227 * @hw: pointer to the hw struct
4228 * @vsi_seid: VSI SEID using this S-tag
4229 * @old_tag: old tag value
4230 * @new_tag: new tag value
4231 * @tags_used: return value, number of tags in use by this PF
4232 * @tags_free: return value, number of unallocated tags
4233 * @cmd_details: pointer to command details structure or NULL
4235 * This updates the value of the tag currently attached to this VSI
4236 * in the switch complex. It will return the number of tags allocated
4237 * by the PF, and the number of unallocated tags available.
4239 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4240 u16 old_tag, u16 new_tag, u16 *tags_used,
4242 struct i40e_asq_cmd_details *cmd_details)
4244 struct i40e_aq_desc desc;
4245 struct i40e_aqc_update_tag *cmd =
4246 (struct i40e_aqc_update_tag *)&desc.params.raw;
4247 struct i40e_aqc_update_tag_completion *resp =
4248 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4249 enum i40e_status_code status;
4252 return I40E_ERR_PARAM;
4254 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4256 cmd->seid = CPU_TO_LE16(vsi_seid);
4257 cmd->old_tag = CPU_TO_LE16(old_tag);
4258 cmd->new_tag = CPU_TO_LE16(new_tag);
4260 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4263 if (tags_used != NULL)
4264 *tags_used = LE16_TO_CPU(resp->tags_used);
4265 if (tags_free != NULL)
4266 *tags_free = LE16_TO_CPU(resp->tags_free);
4273 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4274 * @hw: pointer to the hw struct
4275 * @tcmap: TC map for request/release any ignore PFC condition
4276 * @request: request or release ignore PFC condition
4277 * @tcmap_ret: return TCs for which PFC is currently ignored
4278 * @cmd_details: pointer to command details structure or NULL
4280 * This sends out request/release to ignore PFC condition for a TC.
4281 * It will return the TCs for which PFC is currently ignored.
4283 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4284 bool request, u8 *tcmap_ret,
4285 struct i40e_asq_cmd_details *cmd_details)
4287 struct i40e_aq_desc desc;
4288 struct i40e_aqc_pfc_ignore *cmd_resp =
4289 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4290 enum i40e_status_code status;
4292 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4295 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4297 cmd_resp->tc_bitmap = tcmap;
4299 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4302 if (tcmap_ret != NULL)
4303 *tcmap_ret = cmd_resp->tc_bitmap;
4310 * i40e_aq_dcb_updated - DCB Updated Command
4311 * @hw: pointer to the hw struct
4312 * @cmd_details: pointer to command details structure or NULL
4314 * When LLDP is handled in PF this command is used by the PF
4315 * to notify EMP that a DCB setting is modified.
4316 * When LLDP is handled in EMP this command is used by the PF
4317 * to notify EMP whenever one of the following parameters get
4319 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4320 * - PCIRTT in PRTDCB_GENC.PCIRTT
4321 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4322 * EMP will return when the shared RPB settings have been
4323 * recomputed and modified. The retval field in the descriptor
4324 * will be set to 0 when RPB is modified.
4326 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4327 struct i40e_asq_cmd_details *cmd_details)
4329 struct i40e_aq_desc desc;
4330 enum i40e_status_code status;
4332 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4334 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4340 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4341 * @hw: pointer to the hw struct
4342 * @seid: defines the SEID of the switch for which the stats are requested
4343 * @vlan_id: the VLAN ID for which the statistics are requested
4344 * @stat_index: index of the statistics counters block assigned to this VLAN
4345 * @cmd_details: pointer to command details structure or NULL
4347 * XL710 supports 128 smonVlanStats counters.This command is used to
4348 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4351 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4352 u16 vlan_id, u16 *stat_index,
4353 struct i40e_asq_cmd_details *cmd_details)
4355 struct i40e_aq_desc desc;
4356 struct i40e_aqc_add_remove_statistics *cmd_resp =
4357 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4358 enum i40e_status_code status;
4360 if ((seid == 0) || (stat_index == NULL))
4361 return I40E_ERR_PARAM;
4363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4365 cmd_resp->seid = CPU_TO_LE16(seid);
4366 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4368 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4370 if (!status && stat_index)
4371 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4377 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4378 * @hw: pointer to the hw struct
4379 * @seid: defines the SEID of the switch for which the stats are requested
4380 * @vlan_id: the VLAN ID for which the statistics are requested
4381 * @stat_index: index of the statistics counters block assigned to this VLAN
4382 * @cmd_details: pointer to command details structure or NULL
4384 * XL710 supports 128 smonVlanStats counters.This command is used to
4385 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4388 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4389 u16 vlan_id, u16 stat_index,
4390 struct i40e_asq_cmd_details *cmd_details)
4392 struct i40e_aq_desc desc;
4393 struct i40e_aqc_add_remove_statistics *cmd =
4394 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4395 enum i40e_status_code status;
4398 return I40E_ERR_PARAM;
4400 i40e_fill_default_direct_cmd_desc(&desc,
4401 i40e_aqc_opc_remove_statistics);
4403 cmd->seid = CPU_TO_LE16(seid);
4404 cmd->vlan = CPU_TO_LE16(vlan_id);
4405 cmd->stat_index = CPU_TO_LE16(stat_index);
4407 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4413 * i40e_aq_set_port_parameters - set physical port parameters.
4414 * @hw: pointer to the hw struct
4415 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4416 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4417 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4418 * @double_vlan: if set double VLAN is enabled
4419 * @cmd_details: pointer to command details structure or NULL
4421 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4422 u16 bad_frame_vsi, bool save_bad_pac,
4423 bool pad_short_pac, bool double_vlan,
4424 struct i40e_asq_cmd_details *cmd_details)
4426 struct i40e_aqc_set_port_parameters *cmd;
4427 enum i40e_status_code status;
4428 struct i40e_aq_desc desc;
4429 u16 command_flags = 0;
4431 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4433 i40e_fill_default_direct_cmd_desc(&desc,
4434 i40e_aqc_opc_set_port_parameters);
4436 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4438 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4440 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4442 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4443 cmd->command_flags = CPU_TO_LE16(command_flags);
4445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4451 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4452 * @hw: pointer to the hw struct
4453 * @seid: seid for the physical port/switching component/vsi
4454 * @buff: Indirect buffer to hold data parameters and response
4455 * @buff_size: Indirect buffer size
4456 * @opcode: Tx scheduler AQ command opcode
4457 * @cmd_details: pointer to command details structure or NULL
4459 * Generic command handler for Tx scheduler AQ commands
4461 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4462 void *buff, u16 buff_size,
4463 enum i40e_admin_queue_opc opcode,
4464 struct i40e_asq_cmd_details *cmd_details)
4466 struct i40e_aq_desc desc;
4467 struct i40e_aqc_tx_sched_ind *cmd =
4468 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4469 enum i40e_status_code status;
4470 bool cmd_param_flag = false;
4473 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4474 case i40e_aqc_opc_configure_vsi_tc_bw:
4475 case i40e_aqc_opc_enable_switching_comp_ets:
4476 case i40e_aqc_opc_modify_switching_comp_ets:
4477 case i40e_aqc_opc_disable_switching_comp_ets:
4478 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4479 case i40e_aqc_opc_configure_switching_comp_bw_config:
4480 cmd_param_flag = true;
4482 case i40e_aqc_opc_query_vsi_bw_config:
4483 case i40e_aqc_opc_query_vsi_ets_sla_config:
4484 case i40e_aqc_opc_query_switching_comp_ets_config:
4485 case i40e_aqc_opc_query_port_ets_config:
4486 case i40e_aqc_opc_query_switching_comp_bw_config:
4487 cmd_param_flag = false;
4490 return I40E_ERR_PARAM;
4493 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4495 /* Indirect command */
4496 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4498 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4499 if (buff_size > I40E_AQ_LARGE_BUF)
4500 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4502 desc.datalen = CPU_TO_LE16(buff_size);
4504 cmd->vsi_seid = CPU_TO_LE16(seid);
4506 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4512 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4513 * @hw: pointer to the hw struct
4515 * @credit: BW limit credits (0 = disabled)
4516 * @max_credit: Max BW limit credits
4517 * @cmd_details: pointer to command details structure or NULL
4519 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4520 u16 seid, u16 credit, u8 max_credit,
4521 struct i40e_asq_cmd_details *cmd_details)
4523 struct i40e_aq_desc desc;
4524 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4525 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4526 enum i40e_status_code status;
4528 i40e_fill_default_direct_cmd_desc(&desc,
4529 i40e_aqc_opc_configure_vsi_bw_limit);
4531 cmd->vsi_seid = CPU_TO_LE16(seid);
4532 cmd->credit = CPU_TO_LE16(credit);
4533 cmd->max_credit = max_credit;
4535 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4541 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4542 * @hw: pointer to the hw struct
4543 * @seid: switching component seid
4544 * @credit: BW limit credits (0 = disabled)
4545 * @max_bw: Max BW limit credits
4546 * @cmd_details: pointer to command details structure or NULL
4548 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4549 u16 seid, u16 credit, u8 max_bw,
4550 struct i40e_asq_cmd_details *cmd_details)
4552 struct i40e_aq_desc desc;
4553 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4554 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4555 enum i40e_status_code status;
4557 i40e_fill_default_direct_cmd_desc(&desc,
4558 i40e_aqc_opc_configure_switching_comp_bw_limit);
4560 cmd->seid = CPU_TO_LE16(seid);
4561 cmd->credit = CPU_TO_LE16(credit);
4562 cmd->max_bw = max_bw;
4564 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4570 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4571 * @hw: pointer to the hw struct
4573 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4574 * @cmd_details: pointer to command details structure or NULL
4576 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4578 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4579 struct i40e_asq_cmd_details *cmd_details)
4581 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4582 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4587 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4588 * @hw: pointer to the hw struct
4590 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4591 * @cmd_details: pointer to command details structure or NULL
4593 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4595 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4596 struct i40e_asq_cmd_details *cmd_details)
4598 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4599 i40e_aqc_opc_configure_vsi_tc_bw,
4604 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4605 * @hw: pointer to the hw struct
4606 * @seid: seid of the switching component connected to Physical Port
4607 * @ets_data: Buffer holding ETS parameters
4608 * @cmd_details: pointer to command details structure or NULL
4610 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4612 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4613 enum i40e_admin_queue_opc opcode,
4614 struct i40e_asq_cmd_details *cmd_details)
4616 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4617 sizeof(*ets_data), opcode, cmd_details);
4621 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4622 * @hw: pointer to the hw struct
4623 * @seid: seid of the switching component
4624 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4625 * @cmd_details: pointer to command details structure or NULL
4627 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4629 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4630 struct i40e_asq_cmd_details *cmd_details)
4632 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4633 i40e_aqc_opc_configure_switching_comp_bw_config,
4638 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4639 * @hw: pointer to the hw struct
4640 * @seid: seid of the switching component
4641 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4642 * @cmd_details: pointer to command details structure or NULL
4644 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4645 struct i40e_hw *hw, u16 seid,
4646 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4647 struct i40e_asq_cmd_details *cmd_details)
4649 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4650 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4655 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4656 * @hw: pointer to the hw struct
4657 * @seid: seid of the VSI
4658 * @bw_data: Buffer to hold VSI BW configuration
4659 * @cmd_details: pointer to command details structure or NULL
4661 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4663 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4664 struct i40e_asq_cmd_details *cmd_details)
4666 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4667 i40e_aqc_opc_query_vsi_bw_config,
4672 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4673 * @hw: pointer to the hw struct
4674 * @seid: seid of the VSI
4675 * @bw_data: Buffer to hold VSI BW configuration per TC
4676 * @cmd_details: pointer to command details structure or NULL
4678 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4680 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4681 struct i40e_asq_cmd_details *cmd_details)
4683 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4684 i40e_aqc_opc_query_vsi_ets_sla_config,
4689 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4690 * @hw: pointer to the hw struct
4691 * @seid: seid of the switching component
4692 * @bw_data: Buffer to hold switching component's per TC BW config
4693 * @cmd_details: pointer to command details structure or NULL
4695 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4697 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4698 struct i40e_asq_cmd_details *cmd_details)
4700 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4701 i40e_aqc_opc_query_switching_comp_ets_config,
4706 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4707 * @hw: pointer to the hw struct
4708 * @seid: seid of the VSI or switching component connected to Physical Port
4709 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4710 * @cmd_details: pointer to command details structure or NULL
4712 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4714 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4715 struct i40e_asq_cmd_details *cmd_details)
4717 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4718 i40e_aqc_opc_query_port_ets_config,
4723 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4724 * @hw: pointer to the hw struct
4725 * @seid: seid of the switching component
4726 * @bw_data: Buffer to hold switching component's BW configuration
4727 * @cmd_details: pointer to command details structure or NULL
4729 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4731 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4732 struct i40e_asq_cmd_details *cmd_details)
4734 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4735 i40e_aqc_opc_query_switching_comp_bw_config,
4740 * i40e_validate_filter_settings
4741 * @hw: pointer to the hardware structure
4742 * @settings: Filter control settings
4744 * Check and validate the filter control settings passed.
4745 * The function checks for the valid filter/context sizes being
4746 * passed for FCoE and PE.
4748 * Returns I40E_SUCCESS if the values passed are valid and within
4749 * range else returns an error.
4751 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4752 struct i40e_filter_control_settings *settings)
4754 u32 fcoe_cntx_size, fcoe_filt_size;
4755 u32 pe_cntx_size, pe_filt_size;
4760 /* Validate FCoE settings passed */
4761 switch (settings->fcoe_filt_num) {
4762 case I40E_HASH_FILTER_SIZE_1K:
4763 case I40E_HASH_FILTER_SIZE_2K:
4764 case I40E_HASH_FILTER_SIZE_4K:
4765 case I40E_HASH_FILTER_SIZE_8K:
4766 case I40E_HASH_FILTER_SIZE_16K:
4767 case I40E_HASH_FILTER_SIZE_32K:
4768 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4769 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4772 return I40E_ERR_PARAM;
4775 switch (settings->fcoe_cntx_num) {
4776 case I40E_DMA_CNTX_SIZE_512:
4777 case I40E_DMA_CNTX_SIZE_1K:
4778 case I40E_DMA_CNTX_SIZE_2K:
4779 case I40E_DMA_CNTX_SIZE_4K:
4780 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4781 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4784 return I40E_ERR_PARAM;
4787 /* Validate PE settings passed */
4788 switch (settings->pe_filt_num) {
4789 case I40E_HASH_FILTER_SIZE_1K:
4790 case I40E_HASH_FILTER_SIZE_2K:
4791 case I40E_HASH_FILTER_SIZE_4K:
4792 case I40E_HASH_FILTER_SIZE_8K:
4793 case I40E_HASH_FILTER_SIZE_16K:
4794 case I40E_HASH_FILTER_SIZE_32K:
4795 case I40E_HASH_FILTER_SIZE_64K:
4796 case I40E_HASH_FILTER_SIZE_128K:
4797 case I40E_HASH_FILTER_SIZE_256K:
4798 case I40E_HASH_FILTER_SIZE_512K:
4799 case I40E_HASH_FILTER_SIZE_1M:
4800 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4801 pe_filt_size <<= (u32)settings->pe_filt_num;
4804 return I40E_ERR_PARAM;
4807 switch (settings->pe_cntx_num) {
4808 case I40E_DMA_CNTX_SIZE_512:
4809 case I40E_DMA_CNTX_SIZE_1K:
4810 case I40E_DMA_CNTX_SIZE_2K:
4811 case I40E_DMA_CNTX_SIZE_4K:
4812 case I40E_DMA_CNTX_SIZE_8K:
4813 case I40E_DMA_CNTX_SIZE_16K:
4814 case I40E_DMA_CNTX_SIZE_32K:
4815 case I40E_DMA_CNTX_SIZE_64K:
4816 case I40E_DMA_CNTX_SIZE_128K:
4817 case I40E_DMA_CNTX_SIZE_256K:
4818 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4819 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4822 return I40E_ERR_PARAM;
4825 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4826 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4827 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4828 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4829 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4830 return I40E_ERR_INVALID_SIZE;
4832 return I40E_SUCCESS;
4836 * i40e_set_filter_control
4837 * @hw: pointer to the hardware structure
4838 * @settings: Filter control settings
4840 * Set the Queue Filters for PE/FCoE and enable filters required
4841 * for a single PF. It is expected that these settings are programmed
4842 * at the driver initialization time.
4844 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4845 struct i40e_filter_control_settings *settings)
4847 enum i40e_status_code ret = I40E_SUCCESS;
4848 u32 hash_lut_size = 0;
4852 return I40E_ERR_PARAM;
4854 /* Validate the input settings */
4855 ret = i40e_validate_filter_settings(hw, settings);
4859 /* Read the PF Queue Filter control register */
4860 val = rd32(hw, I40E_PFQF_CTL_0);
4862 /* Program required PE hash buckets for the PF */
4863 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4864 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4865 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4866 /* Program required PE contexts for the PF */
4867 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4868 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4869 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4871 /* Program required FCoE hash buckets for the PF */
4872 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4873 val |= ((u32)settings->fcoe_filt_num <<
4874 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4875 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4876 /* Program required FCoE DDP contexts for the PF */
4877 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4878 val |= ((u32)settings->fcoe_cntx_num <<
4879 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4880 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4882 /* Program Hash LUT size for the PF */
4883 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4884 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4886 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4887 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4889 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4890 if (settings->enable_fdir)
4891 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4892 if (settings->enable_ethtype)
4893 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4894 if (settings->enable_macvlan)
4895 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4897 wr32(hw, I40E_PFQF_CTL_0, val);
4899 return I40E_SUCCESS;
4903 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4904 * @hw: pointer to the hw struct
4905 * @mac_addr: MAC address to use in the filter
4906 * @ethtype: Ethertype to use in the filter
4907 * @flags: Flags that needs to be applied to the filter
4908 * @vsi_seid: seid of the control VSI
4909 * @queue: VSI queue number to send the packet to
4910 * @is_add: Add control packet filter if True else remove
4911 * @stats: Structure to hold information on control filter counts
4912 * @cmd_details: pointer to command details structure or NULL
4914 * This command will Add or Remove control packet filter for a control VSI.
4915 * In return it will update the total number of perfect filter count in
4918 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4919 u8 *mac_addr, u16 ethtype, u16 flags,
4920 u16 vsi_seid, u16 queue, bool is_add,
4921 struct i40e_control_filter_stats *stats,
4922 struct i40e_asq_cmd_details *cmd_details)
4924 struct i40e_aq_desc desc;
4925 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4926 (struct i40e_aqc_add_remove_control_packet_filter *)
4928 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4929 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4931 enum i40e_status_code status;
4934 return I40E_ERR_PARAM;
4937 i40e_fill_default_direct_cmd_desc(&desc,
4938 i40e_aqc_opc_add_control_packet_filter);
4939 cmd->queue = CPU_TO_LE16(queue);
4941 i40e_fill_default_direct_cmd_desc(&desc,
4942 i40e_aqc_opc_remove_control_packet_filter);
4946 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4947 I40E_NONDMA_TO_NONDMA);
4949 cmd->etype = CPU_TO_LE16(ethtype);
4950 cmd->flags = CPU_TO_LE16(flags);
4951 cmd->seid = CPU_TO_LE16(vsi_seid);
4953 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4955 if (!status && stats) {
4956 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4957 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4958 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4959 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4966 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4967 * @hw: pointer to the hw struct
4968 * @seid: VSI seid to add ethertype filter from
4970 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4971 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4974 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4975 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4976 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4977 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4978 enum i40e_status_code status;
4980 status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
4981 seid, 0, true, NULL,
4984 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4988 * i40e_aq_add_cloud_filters
4989 * @hw: pointer to the hardware structure
4990 * @seid: VSI seid to add cloud filters from
4991 * @filters: Buffer which contains the filters to be added
4992 * @filter_count: number of filters contained in the buffer
4994 * Set the cloud filters for a given VSI. The contents of the
4995 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4996 * in by the caller of the function.
4999 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5001 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5004 struct i40e_aq_desc desc;
5005 struct i40e_aqc_add_remove_cloud_filters *cmd =
5006 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5008 enum i40e_status_code status;
5010 i40e_fill_default_direct_cmd_desc(&desc,
5011 i40e_aqc_opc_add_cloud_filters);
5013 buff_len = filter_count * sizeof(*filters);
5014 desc.datalen = CPU_TO_LE16(buff_len);
5015 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5016 cmd->num_filters = filter_count;
5017 cmd->seid = CPU_TO_LE16(seid);
5019 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5025 * i40e_aq_remove_cloud_filters
5026 * @hw: pointer to the hardware structure
5027 * @seid: VSI seid to remove cloud filters from
5028 * @filters: Buffer which contains the filters to be removed
5029 * @filter_count: number of filters contained in the buffer
5031 * Remove the cloud filters for a given VSI. The contents of the
5032 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5033 * in by the caller of the function.
5036 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5038 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5041 struct i40e_aq_desc desc;
5042 struct i40e_aqc_add_remove_cloud_filters *cmd =
5043 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5044 enum i40e_status_code status;
5047 i40e_fill_default_direct_cmd_desc(&desc,
5048 i40e_aqc_opc_remove_cloud_filters);
5050 buff_len = filter_count * sizeof(*filters);
5051 desc.datalen = CPU_TO_LE16(buff_len);
5052 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5053 cmd->num_filters = filter_count;
5054 cmd->seid = CPU_TO_LE16(seid);
5056 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5062 * i40e_aq_alternate_write
5063 * @hw: pointer to the hardware structure
5064 * @reg_addr0: address of first dword to be read
5065 * @reg_val0: value to be written under 'reg_addr0'
5066 * @reg_addr1: address of second dword to be read
5067 * @reg_val1: value to be written under 'reg_addr1'
5069 * Write one or two dwords to alternate structure. Fields are indicated
5070 * by 'reg_addr0' and 'reg_addr1' register numbers.
5073 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5074 u32 reg_addr0, u32 reg_val0,
5075 u32 reg_addr1, u32 reg_val1)
5077 struct i40e_aq_desc desc;
5078 struct i40e_aqc_alternate_write *cmd_resp =
5079 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5080 enum i40e_status_code status;
5082 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5083 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5084 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5085 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5086 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5088 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5094 * i40e_aq_alternate_write_indirect
5095 * @hw: pointer to the hardware structure
5096 * @addr: address of a first register to be modified
5097 * @dw_count: number of alternate structure fields to write
5098 * @buffer: pointer to the command buffer
5100 * Write 'dw_count' dwords from 'buffer' to alternate structure
5101 * starting at 'addr'.
5104 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5105 u32 addr, u32 dw_count, void *buffer)
5107 struct i40e_aq_desc desc;
5108 struct i40e_aqc_alternate_ind_write *cmd_resp =
5109 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5110 enum i40e_status_code status;
5113 return I40E_ERR_PARAM;
5115 /* Indirect command */
5116 i40e_fill_default_direct_cmd_desc(&desc,
5117 i40e_aqc_opc_alternate_write_indirect);
5119 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5120 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5121 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5122 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5124 cmd_resp->address = CPU_TO_LE32(addr);
5125 cmd_resp->length = CPU_TO_LE32(dw_count);
5127 status = i40e_asq_send_command(hw, &desc, buffer,
5128 I40E_LO_DWORD(4*dw_count), NULL);
5134 * i40e_aq_alternate_read
5135 * @hw: pointer to the hardware structure
5136 * @reg_addr0: address of first dword to be read
5137 * @reg_val0: pointer for data read from 'reg_addr0'
5138 * @reg_addr1: address of second dword to be read
5139 * @reg_val1: pointer for data read from 'reg_addr1'
5141 * Read one or two dwords from alternate structure. Fields are indicated
5142 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5143 * is not passed then only register at 'reg_addr0' is read.
5146 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5147 u32 reg_addr0, u32 *reg_val0,
5148 u32 reg_addr1, u32 *reg_val1)
5150 struct i40e_aq_desc desc;
5151 struct i40e_aqc_alternate_write *cmd_resp =
5152 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5153 enum i40e_status_code status;
5155 if (reg_val0 == NULL)
5156 return I40E_ERR_PARAM;
5158 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5159 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5160 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5162 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5164 if (status == I40E_SUCCESS) {
5165 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5167 if (reg_val1 != NULL)
5168 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5175 * i40e_aq_alternate_read_indirect
5176 * @hw: pointer to the hardware structure
5177 * @addr: address of the alternate structure field
5178 * @dw_count: number of alternate structure fields to read
5179 * @buffer: pointer to the command buffer
5181 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5182 * place them in 'buffer'. The buffer should be allocated by caller.
5185 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5186 u32 addr, u32 dw_count, void *buffer)
5188 struct i40e_aq_desc desc;
5189 struct i40e_aqc_alternate_ind_write *cmd_resp =
5190 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5191 enum i40e_status_code status;
5194 return I40E_ERR_PARAM;
5196 /* Indirect command */
5197 i40e_fill_default_direct_cmd_desc(&desc,
5198 i40e_aqc_opc_alternate_read_indirect);
5200 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5201 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5202 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5203 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5205 cmd_resp->address = CPU_TO_LE32(addr);
5206 cmd_resp->length = CPU_TO_LE32(dw_count);
5208 status = i40e_asq_send_command(hw, &desc, buffer,
5209 I40E_LO_DWORD(4*dw_count), NULL);
5215 * i40e_aq_alternate_clear
5216 * @hw: pointer to the HW structure.
5218 * Clear the alternate structures of the port from which the function
5222 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5224 struct i40e_aq_desc desc;
5225 enum i40e_status_code status;
5227 i40e_fill_default_direct_cmd_desc(&desc,
5228 i40e_aqc_opc_alternate_clear_port);
5230 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5236 * i40e_aq_alternate_write_done
5237 * @hw: pointer to the HW structure.
5238 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5239 * @reset_needed: indicates the SW should trigger GLOBAL reset
5241 * Indicates to the FW that alternate structures have been changed.
5244 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5245 u8 bios_mode, bool *reset_needed)
5247 struct i40e_aq_desc desc;
5248 struct i40e_aqc_alternate_write_done *cmd =
5249 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5250 enum i40e_status_code status;
5252 if (reset_needed == NULL)
5253 return I40E_ERR_PARAM;
5255 i40e_fill_default_direct_cmd_desc(&desc,
5256 i40e_aqc_opc_alternate_write_done);
5258 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5260 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5261 if (!status && reset_needed)
5262 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5263 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5269 * i40e_aq_set_oem_mode
5270 * @hw: pointer to the HW structure.
5271 * @oem_mode: the OEM mode to be used
5273 * Sets the device to a specific operating mode. Currently the only supported
5274 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5277 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5280 struct i40e_aq_desc desc;
5281 struct i40e_aqc_alternate_write_done *cmd =
5282 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5283 enum i40e_status_code status;
5285 i40e_fill_default_direct_cmd_desc(&desc,
5286 i40e_aqc_opc_alternate_set_mode);
5288 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5290 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5296 * i40e_aq_resume_port_tx
5297 * @hw: pointer to the hardware structure
5298 * @cmd_details: pointer to command details structure or NULL
5300 * Resume port's Tx traffic
5302 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5303 struct i40e_asq_cmd_details *cmd_details)
5305 struct i40e_aq_desc desc;
5306 enum i40e_status_code status;
5308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5310 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5316 * i40e_set_pci_config_data - store PCI bus info
5317 * @hw: pointer to hardware structure
5318 * @link_status: the link status word from PCI config space
5320 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5322 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5324 hw->bus.type = i40e_bus_type_pci_express;
5326 switch (link_status & I40E_PCI_LINK_WIDTH) {
5327 case I40E_PCI_LINK_WIDTH_1:
5328 hw->bus.width = i40e_bus_width_pcie_x1;
5330 case I40E_PCI_LINK_WIDTH_2:
5331 hw->bus.width = i40e_bus_width_pcie_x2;
5333 case I40E_PCI_LINK_WIDTH_4:
5334 hw->bus.width = i40e_bus_width_pcie_x4;
5336 case I40E_PCI_LINK_WIDTH_8:
5337 hw->bus.width = i40e_bus_width_pcie_x8;
5340 hw->bus.width = i40e_bus_width_unknown;
5344 switch (link_status & I40E_PCI_LINK_SPEED) {
5345 case I40E_PCI_LINK_SPEED_2500:
5346 hw->bus.speed = i40e_bus_speed_2500;
5348 case I40E_PCI_LINK_SPEED_5000:
5349 hw->bus.speed = i40e_bus_speed_5000;
5351 case I40E_PCI_LINK_SPEED_8000:
5352 hw->bus.speed = i40e_bus_speed_8000;
5355 hw->bus.speed = i40e_bus_speed_unknown;
5361 * i40e_aq_debug_dump
5362 * @hw: pointer to the hardware structure
5363 * @cluster_id: specific cluster to dump
5364 * @table_id: table id within cluster
5365 * @start_index: index of line in the block to read
5366 * @buff_size: dump buffer size
5367 * @buff: dump buffer
5368 * @ret_buff_size: actual buffer size returned
5369 * @ret_next_table: next block to read
5370 * @ret_next_index: next index to read
5372 * Dump internal FW/HW data for debug purposes.
5375 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5376 u8 table_id, u32 start_index, u16 buff_size,
5377 void *buff, u16 *ret_buff_size,
5378 u8 *ret_next_table, u32 *ret_next_index,
5379 struct i40e_asq_cmd_details *cmd_details)
5381 struct i40e_aq_desc desc;
5382 struct i40e_aqc_debug_dump_internals *cmd =
5383 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5384 struct i40e_aqc_debug_dump_internals *resp =
5385 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5386 enum i40e_status_code status;
5388 if (buff_size == 0 || !buff)
5389 return I40E_ERR_PARAM;
5391 i40e_fill_default_direct_cmd_desc(&desc,
5392 i40e_aqc_opc_debug_dump_internals);
5393 /* Indirect Command */
5394 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5395 if (buff_size > I40E_AQ_LARGE_BUF)
5396 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5398 cmd->cluster_id = cluster_id;
5399 cmd->table_id = table_id;
5400 cmd->idx = CPU_TO_LE32(start_index);
5402 desc.datalen = CPU_TO_LE16(buff_size);
5404 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5406 if (ret_buff_size != NULL)
5407 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5408 if (ret_next_table != NULL)
5409 *ret_next_table = resp->table_id;
5410 if (ret_next_index != NULL)
5411 *ret_next_index = LE32_TO_CPU(resp->idx);
5418 * i40e_read_bw_from_alt_ram
5419 * @hw: pointer to the hardware structure
5420 * @max_bw: pointer for max_bw read
5421 * @min_bw: pointer for min_bw read
5422 * @min_valid: pointer for bool that is true if min_bw is a valid value
5423 * @max_valid: pointer for bool that is true if max_bw is a valid value
5425 * Read bw from the alternate ram for the given pf
5427 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5428 u32 *max_bw, u32 *min_bw,
5429 bool *min_valid, bool *max_valid)
5431 enum i40e_status_code status;
5432 u32 max_bw_addr, min_bw_addr;
5434 /* Calculate the address of the min/max bw registers */
5435 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5436 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5437 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5438 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5439 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5440 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5442 /* Read the bandwidths from alt ram */
5443 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5444 min_bw_addr, min_bw);
5446 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5451 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5460 * i40e_aq_configure_partition_bw
5461 * @hw: pointer to the hardware structure
5462 * @bw_data: Buffer holding valid pfs and bw limits
5463 * @cmd_details: pointer to command details
5465 * Configure partitions guaranteed/max bw
5467 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5468 struct i40e_aqc_configure_partition_bw_data *bw_data,
5469 struct i40e_asq_cmd_details *cmd_details)
5471 enum i40e_status_code status;
5472 struct i40e_aq_desc desc;
5473 u16 bwd_size = sizeof(*bw_data);
5475 i40e_fill_default_direct_cmd_desc(&desc,
5476 i40e_aqc_opc_configure_partition_bw);
5478 /* Indirect command */
5479 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5482 if (bwd_size > I40E_AQ_LARGE_BUF)
5483 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5485 desc.datalen = CPU_TO_LE16(bwd_size);
5487 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5491 #endif /* PF_DRIVER */
5495 * i40e_aq_send_msg_to_pf
5496 * @hw: pointer to the hardware structure
5497 * @v_opcode: opcodes for VF-PF communication
5498 * @v_retval: return error code
5499 * @msg: pointer to the msg buffer
5500 * @msglen: msg length
5501 * @cmd_details: pointer to command details
5503 * Send message to PF driver using admin queue. By default, this message
5504 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5505 * completion before returning.
5507 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5508 enum i40e_virtchnl_ops v_opcode,
5509 enum i40e_status_code v_retval,
5510 u8 *msg, u16 msglen,
5511 struct i40e_asq_cmd_details *cmd_details)
5513 struct i40e_aq_desc desc;
5514 struct i40e_asq_cmd_details details;
5515 enum i40e_status_code status;
5517 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5518 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5519 desc.cookie_high = CPU_TO_LE32(v_opcode);
5520 desc.cookie_low = CPU_TO_LE32(v_retval);
5522 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5523 | I40E_AQ_FLAG_RD));
5524 if (msglen > I40E_AQ_LARGE_BUF)
5525 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5526 desc.datalen = CPU_TO_LE16(msglen);
5529 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5530 details.async = true;
5531 cmd_details = &details;
5533 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5534 msglen, cmd_details);
5539 * i40e_vf_parse_hw_config
5540 * @hw: pointer to the hardware structure
5541 * @msg: pointer to the virtual channel VF resource structure
5543 * Given a VF resource message from the PF, populate the hw struct
5544 * with appropriate information.
5546 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5547 struct i40e_virtchnl_vf_resource *msg)
5549 struct i40e_virtchnl_vsi_resource *vsi_res;
5552 vsi_res = &msg->vsi_res[0];
5554 hw->dev_caps.num_vsis = msg->num_vsis;
5555 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5556 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5557 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5558 hw->dev_caps.dcb = msg->vf_offload_flags &
5559 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5560 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5561 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5562 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5563 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5564 for (i = 0; i < msg->num_vsis; i++) {
5565 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5566 i40e_memcpy(hw->mac.perm_addr,
5567 vsi_res->default_mac_addr,
5568 I40E_ETH_LENGTH_OF_ADDRESS,
5569 I40E_NONDMA_TO_NONDMA);
5570 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5571 I40E_ETH_LENGTH_OF_ADDRESS,
5572 I40E_NONDMA_TO_NONDMA);
5580 * @hw: pointer to the hardware structure
5582 * Send a VF_RESET message to the PF. Does not wait for response from PF
5583 * as none will be forthcoming. Immediately after calling this function,
5584 * the admin queue should be shut down and (optionally) reinitialized.
5586 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5588 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5589 I40E_SUCCESS, NULL, 0, NULL);
5591 #endif /* VF_DRIVER */