drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u8 *buf = (u8 *)buffer;
 334         u16 len;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         len = LE16_TO_CPU(aq_desc->datalen);
 341
 342         i40e_debug(hw, mask,
 343                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 344                    LE16_TO_CPU(aq_desc->opcode),
 345                    LE16_TO_CPU(aq_desc->flags),
 346                    LE16_TO_CPU(aq_desc->datalen),
 347                    LE16_TO_CPU(aq_desc->retval));
 348         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 349                    LE32_TO_CPU(aq_desc->cookie_high),
 350                    LE32_TO_CPU(aq_desc->cookie_low));
 351         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->params.internal.param0),
 353                    LE32_TO_CPU(aq_desc->params.internal.param1));
 354         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 355                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 356                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 357
 358         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 359                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 360                 if (buf_len < len)
 361                         len = buf_len;
 362                 /* write the full 16-byte chunks */
 363                 for (i = 0; i < (len - 16); i += 16)
 364                         i40e_debug(hw, mask,
 365                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 366                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 367                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 368                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 369                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 370                 /* the most we could have left is 16 bytes, pad with zeros */
 371                 if (i < len) {
 372                         char d_buf[16];
 373                         int j, i_sav;
 374
 375                         i_sav = i;
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446
 447 /**
 448  * i40e_aq_get_set_rss_lut
 449  * @hw: pointer to the hardware structure
 450  * @vsi_id: vsi fw index
 451  * @pf_lut: for PF table set true, for VSI table set false
 452  * @lut: pointer to the lut buffer provided by the caller
 453  * @lut_size: size of the lut buffer
 454  * @set: set true to set the table, false to get the table
 455  *
 456  * Internal function to get or set RSS look up table
 457  **/
 458 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 459                                                      u16 vsi_id, bool pf_lut,
 460                                                      u8 *lut, u16 lut_size,
 461                                                      bool set)
 462 {
 463         enum i40e_status_code status;
 464         struct i40e_aq_desc desc;
 465         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 466                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 467
 468         if (set)
 469                 i40e_fill_default_direct_cmd_desc(&desc,
 470                                                   i40e_aqc_opc_set_rss_lut);
 471         else
 472                 i40e_fill_default_direct_cmd_desc(&desc,
 473                                                   i40e_aqc_opc_get_rss_lut);
 474
 475         /* Indirect command */
 476         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 478
 479         cmd_resp->vsi_id =
 480                         CPU_TO_LE16((u16)((vsi_id <<
 481                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 483         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 484
 485         if (pf_lut)
 486                 cmd_resp->flags |= CPU_TO_LE16((u16)
 487                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 488                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 490         else
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495
 496         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 497
 498         return status;
 499 }
 500
 501 /**
 502  * i40e_aq_get_rss_lut
 503  * @hw: pointer to the hardware structure
 504  * @vsi_id: vsi fw index
 505  * @pf_lut: for PF table set true, for VSI table set false
 506  * @lut: pointer to the lut buffer provided by the caller
 507  * @lut_size: size of the lut buffer
 508  *
 509  * get the RSS lookup table, PF or VSI type
 510  **/
 511 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 512                                           bool pf_lut, u8 *lut, u16 lut_size)
 513 {
 514         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 515                                        false);
 516 }
 517
 518 /**
 519  * i40e_aq_set_rss_lut
 520  * @hw: pointer to the hardware structure
 521  * @vsi_id: vsi fw index
 522  * @pf_lut: for PF table set true, for VSI table set false
 523  * @lut: pointer to the lut buffer provided by the caller
 524  * @lut_size: size of the lut buffer
 525  *
 526  * set the RSS lookup table, PF or VSI type
 527  **/
 528 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 529                                           bool pf_lut, u8 *lut, u16 lut_size)
 530 {
 531         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 532 }
 533
 534 /**
 535  * i40e_aq_get_set_rss_key
 536  * @hw: pointer to the hw struct
 537  * @vsi_id: vsi fw index
 538  * @key: pointer to key info struct
 539  * @set: set true to set the key, false to get the key
 540  *
 541  * get the RSS key per VSI
 542  **/
 543 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 544                                       u16 vsi_id,
 545                                       struct i40e_aqc_get_set_rss_key_data *key,
 546                                       bool set)
 547 {
 548         enum i40e_status_code status;
 549         struct i40e_aq_desc desc;
 550         struct i40e_aqc_get_set_rss_key *cmd_resp =
 551                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 552         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 553
 554         if (set)
 555                 i40e_fill_default_direct_cmd_desc(&desc,
 556                                                   i40e_aqc_opc_set_rss_key);
 557         else
 558                 i40e_fill_default_direct_cmd_desc(&desc,
 559                                                   i40e_aqc_opc_get_rss_key);
 560
 561         /* Indirect command */
 562         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 564
 565         cmd_resp->vsi_id =
 566                         CPU_TO_LE16((u16)((vsi_id <<
 567                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 569         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 570
 571         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 572
 573         return status;
 574 }
 575
 576 /**
 577  * i40e_aq_get_rss_key
 578  * @hw: pointer to the hw struct
 579  * @vsi_id: vsi fw index
 580  * @key: pointer to key info struct
 581  *
 582  **/
 583 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 584                                       u16 vsi_id,
 585                                       struct i40e_aqc_get_set_rss_key_data *key)
 586 {
 587         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 588 }
 589
 590 /**
 591  * i40e_aq_set_rss_key
 592  * @hw: pointer to the hw struct
 593  * @vsi_id: vsi fw index
 594  * @key: pointer to key info struct
 595  *
 596  * set the RSS key per VSI
 597  **/
 598 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 599                                       u16 vsi_id,
 600                                       struct i40e_aqc_get_set_rss_key_data *key)
 601 {
 602         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 603 }
 604
 605 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 606  * hardware to a bit-field that can be used by SW to more easily determine the
 607  * packet type.
 608  *
 609  * Macros are used to shorten the table lines and make this table human
 610  * readable.
 611  *
 612  * We store the PTYPE in the top byte of the bit field - this is just so that
 613  * we can check that the table doesn't have a row missing, as the index into
 614  * the table should be the PTYPE.
 615  *
 616  * Typical work flow:
 617  *
 618  * IF NOT i40e_ptype_lookup[ptype].known
 619  * THEN
 620  *      Packet is unknown
 621  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 622  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 623  * ELSE
 624  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 625  * ENDIF
 626  */
 627
 628 /* macro to make the table lines short */
 629 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 630         {       PTYPE, \
 631                 1, \
 632                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 633                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 634                 I40E_RX_PTYPE_##OUTER_FRAG, \
 635                 I40E_RX_PTYPE_TUNNEL_##T, \
 636                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 637                 I40E_RX_PTYPE_##TEF, \
 638                 I40E_RX_PTYPE_INNER_PROT_##I, \
 639                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 640
 641 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 642                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 643
 644 /* shorter macros makes the table fit but are terse */
 645 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 646 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 647 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 648
 649 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 650 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 651         /* L2 Packet types */
 652         I40E_PTT_UNUSED_ENTRY(0),
 653         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 655         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT_UNUSED_ENTRY(4),
 657         I40E_PTT_UNUSED_ENTRY(5),
 658         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 659         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT_UNUSED_ENTRY(8),
 661         I40E_PTT_UNUSED_ENTRY(9),
 662         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 663         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 664         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674
 675         /* Non Tunneled IPv4 */
 676         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 679         I40E_PTT_UNUSED_ENTRY(25),
 680         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 681         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 682         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 683
 684         /* IPv4 --> IPv4 */
 685         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 686         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 687         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 688         I40E_PTT_UNUSED_ENTRY(32),
 689         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 690         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 691         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 692
 693         /* IPv4 --> IPv6 */
 694         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 695         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 696         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 697         I40E_PTT_UNUSED_ENTRY(39),
 698         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 699         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 700         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 701
 702         /* IPv4 --> GRE/NAT */
 703         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 704
 705         /* IPv4 --> GRE/NAT --> IPv4 */
 706         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 707         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 708         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 709         I40E_PTT_UNUSED_ENTRY(47),
 710         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 711         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 712         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 713
 714         /* IPv4 --> GRE/NAT --> IPv6 */
 715         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 716         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 717         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 718         I40E_PTT_UNUSED_ENTRY(54),
 719         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 720         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 721         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 722
 723         /* IPv4 --> GRE/NAT --> MAC */
 724         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 725
 726         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 727         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 728         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 729         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 730         I40E_PTT_UNUSED_ENTRY(62),
 731         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 732         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 733         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 734
 735         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 736         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 737         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 738         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 739         I40E_PTT_UNUSED_ENTRY(69),
 740         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 741         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 742         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 743
 744         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 745         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 746
 747         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 748         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 749         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 750         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 751         I40E_PTT_UNUSED_ENTRY(77),
 752         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 753         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 754         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 755
 756         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 757         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 758         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 759         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 760         I40E_PTT_UNUSED_ENTRY(84),
 761         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 762         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 763         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 764
 765         /* Non Tunneled IPv6 */
 766         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 767         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 768         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 769         I40E_PTT_UNUSED_ENTRY(91),
 770         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 771         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 772         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 773
 774         /* IPv6 --> IPv4 */
 775         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 776         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 777         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 778         I40E_PTT_UNUSED_ENTRY(98),
 779         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 780         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 781         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 782
 783         /* IPv6 --> IPv6 */
 784         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 785         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 786         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 787         I40E_PTT_UNUSED_ENTRY(105),
 788         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 789         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 790         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 791
 792         /* IPv6 --> GRE/NAT */
 793         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 794
 795         /* IPv6 --> GRE/NAT -> IPv4 */
 796         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 797         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 798         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 799         I40E_PTT_UNUSED_ENTRY(113),
 800         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 801         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 802         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 803
 804         /* IPv6 --> GRE/NAT -> IPv6 */
 805         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 806         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 807         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 808         I40E_PTT_UNUSED_ENTRY(120),
 809         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 810         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 811         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 812
 813         /* IPv6 --> GRE/NAT -> MAC */
 814         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 815
 816         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 817         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 818         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 819         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 820         I40E_PTT_UNUSED_ENTRY(128),
 821         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 822         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 823         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 824
 825         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 826         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 827         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 828         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 829         I40E_PTT_UNUSED_ENTRY(135),
 830         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 831         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 832         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 833
 834         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 835         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 836
 837         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 838         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 839         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 840         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 841         I40E_PTT_UNUSED_ENTRY(143),
 842         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 843         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 844         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 845
 846         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 847         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 848         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 849         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 850         I40E_PTT_UNUSED_ENTRY(150),
 851         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 852         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 853         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 854
 855         /* unused entries */
 856         I40E_PTT_UNUSED_ENTRY(154),
 857         I40E_PTT_UNUSED_ENTRY(155),
 858         I40E_PTT_UNUSED_ENTRY(156),
 859         I40E_PTT_UNUSED_ENTRY(157),
 860         I40E_PTT_UNUSED_ENTRY(158),
 861         I40E_PTT_UNUSED_ENTRY(159),
 862
 863         I40E_PTT_UNUSED_ENTRY(160),
 864         I40E_PTT_UNUSED_ENTRY(161),
 865         I40E_PTT_UNUSED_ENTRY(162),
 866         I40E_PTT_UNUSED_ENTRY(163),
 867         I40E_PTT_UNUSED_ENTRY(164),
 868         I40E_PTT_UNUSED_ENTRY(165),
 869         I40E_PTT_UNUSED_ENTRY(166),
 870         I40E_PTT_UNUSED_ENTRY(167),
 871         I40E_PTT_UNUSED_ENTRY(168),
 872         I40E_PTT_UNUSED_ENTRY(169),
 873
 874         I40E_PTT_UNUSED_ENTRY(170),
 875         I40E_PTT_UNUSED_ENTRY(171),
 876         I40E_PTT_UNUSED_ENTRY(172),
 877         I40E_PTT_UNUSED_ENTRY(173),
 878         I40E_PTT_UNUSED_ENTRY(174),
 879         I40E_PTT_UNUSED_ENTRY(175),
 880         I40E_PTT_UNUSED_ENTRY(176),
 881         I40E_PTT_UNUSED_ENTRY(177),
 882         I40E_PTT_UNUSED_ENTRY(178),
 883         I40E_PTT_UNUSED_ENTRY(179),
 884
 885         I40E_PTT_UNUSED_ENTRY(180),
 886         I40E_PTT_UNUSED_ENTRY(181),
 887         I40E_PTT_UNUSED_ENTRY(182),
 888         I40E_PTT_UNUSED_ENTRY(183),
 889         I40E_PTT_UNUSED_ENTRY(184),
 890         I40E_PTT_UNUSED_ENTRY(185),
 891         I40E_PTT_UNUSED_ENTRY(186),
 892         I40E_PTT_UNUSED_ENTRY(187),
 893         I40E_PTT_UNUSED_ENTRY(188),
 894         I40E_PTT_UNUSED_ENTRY(189),
 895
 896         I40E_PTT_UNUSED_ENTRY(190),
 897         I40E_PTT_UNUSED_ENTRY(191),
 898         I40E_PTT_UNUSED_ENTRY(192),
 899         I40E_PTT_UNUSED_ENTRY(193),
 900         I40E_PTT_UNUSED_ENTRY(194),
 901         I40E_PTT_UNUSED_ENTRY(195),
 902         I40E_PTT_UNUSED_ENTRY(196),
 903         I40E_PTT_UNUSED_ENTRY(197),
 904         I40E_PTT_UNUSED_ENTRY(198),
 905         I40E_PTT_UNUSED_ENTRY(199),
 906
 907         I40E_PTT_UNUSED_ENTRY(200),
 908         I40E_PTT_UNUSED_ENTRY(201),
 909         I40E_PTT_UNUSED_ENTRY(202),
 910         I40E_PTT_UNUSED_ENTRY(203),
 911         I40E_PTT_UNUSED_ENTRY(204),
 912         I40E_PTT_UNUSED_ENTRY(205),
 913         I40E_PTT_UNUSED_ENTRY(206),
 914         I40E_PTT_UNUSED_ENTRY(207),
 915         I40E_PTT_UNUSED_ENTRY(208),
 916         I40E_PTT_UNUSED_ENTRY(209),
 917
 918         I40E_PTT_UNUSED_ENTRY(210),
 919         I40E_PTT_UNUSED_ENTRY(211),
 920         I40E_PTT_UNUSED_ENTRY(212),
 921         I40E_PTT_UNUSED_ENTRY(213),
 922         I40E_PTT_UNUSED_ENTRY(214),
 923         I40E_PTT_UNUSED_ENTRY(215),
 924         I40E_PTT_UNUSED_ENTRY(216),
 925         I40E_PTT_UNUSED_ENTRY(217),
 926         I40E_PTT_UNUSED_ENTRY(218),
 927         I40E_PTT_UNUSED_ENTRY(219),
 928
 929         I40E_PTT_UNUSED_ENTRY(220),
 930         I40E_PTT_UNUSED_ENTRY(221),
 931         I40E_PTT_UNUSED_ENTRY(222),
 932         I40E_PTT_UNUSED_ENTRY(223),
 933         I40E_PTT_UNUSED_ENTRY(224),
 934         I40E_PTT_UNUSED_ENTRY(225),
 935         I40E_PTT_UNUSED_ENTRY(226),
 936         I40E_PTT_UNUSED_ENTRY(227),
 937         I40E_PTT_UNUSED_ENTRY(228),
 938         I40E_PTT_UNUSED_ENTRY(229),
 939
 940         I40E_PTT_UNUSED_ENTRY(230),
 941         I40E_PTT_UNUSED_ENTRY(231),
 942         I40E_PTT_UNUSED_ENTRY(232),
 943         I40E_PTT_UNUSED_ENTRY(233),
 944         I40E_PTT_UNUSED_ENTRY(234),
 945         I40E_PTT_UNUSED_ENTRY(235),
 946         I40E_PTT_UNUSED_ENTRY(236),
 947         I40E_PTT_UNUSED_ENTRY(237),
 948         I40E_PTT_UNUSED_ENTRY(238),
 949         I40E_PTT_UNUSED_ENTRY(239),
 950
 951         I40E_PTT_UNUSED_ENTRY(240),
 952         I40E_PTT_UNUSED_ENTRY(241),
 953         I40E_PTT_UNUSED_ENTRY(242),
 954         I40E_PTT_UNUSED_ENTRY(243),
 955         I40E_PTT_UNUSED_ENTRY(244),
 956         I40E_PTT_UNUSED_ENTRY(245),
 957         I40E_PTT_UNUSED_ENTRY(246),
 958         I40E_PTT_UNUSED_ENTRY(247),
 959         I40E_PTT_UNUSED_ENTRY(248),
 960         I40E_PTT_UNUSED_ENTRY(249),
 961
 962         I40E_PTT_UNUSED_ENTRY(250),
 963         I40E_PTT_UNUSED_ENTRY(251),
 964         I40E_PTT_UNUSED_ENTRY(252),
 965         I40E_PTT_UNUSED_ENTRY(253),
 966         I40E_PTT_UNUSED_ENTRY(254),
 967         I40E_PTT_UNUSED_ENTRY(255)
 968 };
 969
 970
 971 /**
 972  * i40e_validate_mac_addr - Validate unicast MAC address
 973  * @mac_addr: pointer to MAC address
 974  *
 975  * Tests a MAC address to ensure it is a valid Individual Address
 976  **/
 977 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 978 {
 979         enum i40e_status_code status = I40E_SUCCESS;
 980
 981         DEBUGFUNC("i40e_validate_mac_addr");
 982
 983         /* Broadcast addresses ARE multicast addresses
 984          * Make sure it is not a multicast address
 985          * Reject the zero address
 986          */
 987         if (I40E_IS_MULTICAST(mac_addr) ||
 988             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 989               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 990                 status = I40E_ERR_INVALID_MAC_ADDR;
 991
 992         return status;
 993 }
 994 #ifdef PF_DRIVER
 995
 996 /**
 997  * i40e_init_shared_code - Initialize the shared code
 998  * @hw: pointer to hardware structure
 999  *
1000  * This assigns the MAC type and PHY code and inits the NVM.
1001  * Does not touch the hardware. This function must be called prior to any
1002  * other function in the shared code. The i40e_hw structure should be
1003  * memset to 0 prior to calling this function.  The following fields in
1004  * hw structure should be filled in prior to calling this function:
1005  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1006  * subsystem_vendor_id, and revision_id
1007  **/
1008 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1009 {
1010         enum i40e_status_code status = I40E_SUCCESS;
1011         u32 port, ari, func_rid;
1012
1013         DEBUGFUNC("i40e_init_shared_code");
1014
1015         i40e_set_mac_type(hw);
1016
1017         switch (hw->mac.type) {
1018         case I40E_MAC_XL710:
1019         case I40E_MAC_X722:
1020                 break;
1021         default:
1022                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1023         }
1024
1025         hw->phy.get_link_info = true;
1026
1027         /* Determine port number and PF number*/
1028         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1029                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1030         hw->port = (u8)port;
1031         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1032                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1033         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1034         if (ari)
1035                 hw->pf_id = (u8)(func_rid & 0xff);
1036         else
1037                 hw->pf_id = (u8)(func_rid & 0x7);
1038
1039         if (hw->mac.type == I40E_MAC_X722)
1040                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1041                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1042
1043         status = i40e_init_nvm(hw);
1044         return status;
1045 }
1046
1047 /**
1048  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1049  * @hw: pointer to the hw struct
1050  * @flags: a return indicator of what addresses were added to the addr store
1051  * @addrs: the requestor's mac addr store
1052  * @cmd_details: pointer to command details structure or NULL
1053  **/
1054 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1055                                    u16 *flags,
1056                                    struct i40e_aqc_mac_address_read_data *addrs,
1057                                    struct i40e_asq_cmd_details *cmd_details)
1058 {
1059         struct i40e_aq_desc desc;
1060         struct i40e_aqc_mac_address_read *cmd_data =
1061                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1062         enum i40e_status_code status;
1063
1064         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1065         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1066
1067         status = i40e_asq_send_command(hw, &desc, addrs,
1068                                        sizeof(*addrs), cmd_details);
1069         *flags = LE16_TO_CPU(cmd_data->command_flags);
1070
1071         return status;
1072 }
1073
1074 /**
1075  * i40e_aq_mac_address_write - Change the MAC addresses
1076  * @hw: pointer to the hw struct
1077  * @flags: indicates which MAC to be written
1078  * @mac_addr: address to write
1079  * @cmd_details: pointer to command details structure or NULL
1080  **/
1081 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1082                                     u16 flags, u8 *mac_addr,
1083                                     struct i40e_asq_cmd_details *cmd_details)
1084 {
1085         struct i40e_aq_desc desc;
1086         struct i40e_aqc_mac_address_write *cmd_data =
1087                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1088         enum i40e_status_code status;
1089
1090         i40e_fill_default_direct_cmd_desc(&desc,
1091                                           i40e_aqc_opc_mac_address_write);
1092         cmd_data->command_flags = CPU_TO_LE16(flags);
1093         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1094         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1095                                         ((u32)mac_addr[3] << 16) |
1096                                         ((u32)mac_addr[4] << 8) |
1097                                         mac_addr[5]);
1098
1099         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1100
1101         return status;
1102 }
1103
1104 /**
1105  * i40e_get_mac_addr - get MAC address
1106  * @hw: pointer to the HW structure
1107  * @mac_addr: pointer to MAC address
1108  *
1109  * Reads the adapter's MAC address from register
1110  **/
1111 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1112 {
1113         struct i40e_aqc_mac_address_read_data addrs;
1114         enum i40e_status_code status;
1115         u16 flags = 0;
1116
1117         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1118
1119         if (flags & I40E_AQC_LAN_ADDR_VALID)
1120                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1121                         I40E_NONDMA_TO_NONDMA);
1122
1123         return status;
1124 }
1125
1126 /**
1127  * i40e_get_port_mac_addr - get Port MAC address
1128  * @hw: pointer to the HW structure
1129  * @mac_addr: pointer to Port MAC address
1130  *
1131  * Reads the adapter's Port MAC address
1132  **/
1133 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1134 {
1135         struct i40e_aqc_mac_address_read_data addrs;
1136         enum i40e_status_code status;
1137         u16 flags = 0;
1138
1139         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1140         if (status)
1141                 return status;
1142
1143         if (flags & I40E_AQC_PORT_ADDR_VALID)
1144                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1145                         I40E_NONDMA_TO_NONDMA);
1146         else
1147                 status = I40E_ERR_INVALID_MAC_ADDR;
1148
1149         return status;
1150 }
1151
1152 /**
1153  * i40e_pre_tx_queue_cfg - pre tx queue configure
1154  * @hw: pointer to the HW structure
1155  * @queue: target pf queue index
1156  * @enable: state change request
1157  *
1158  * Handles hw requirement to indicate intention to enable
1159  * or disable target queue.
1160  **/
1161 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1162 {
1163         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1164         u32 reg_block = 0;
1165         u32 reg_val;
1166
1167         if (abs_queue_idx >= 128) {
1168                 reg_block = abs_queue_idx / 128;
1169                 abs_queue_idx %= 128;
1170         }
1171
1172         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1173         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1174         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1175
1176         if (enable)
1177                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1178         else
1179                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1180
1181         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1182 }
1183
1184 /**
1185  * i40e_get_san_mac_addr - get SAN MAC address
1186  * @hw: pointer to the HW structure
1187  * @mac_addr: pointer to SAN MAC address
1188  *
1189  * Reads the adapter's SAN MAC address from NVM
1190  **/
1191 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1192                                             u8 *mac_addr)
1193 {
1194         struct i40e_aqc_mac_address_read_data addrs;
1195         enum i40e_status_code status;
1196         u16 flags = 0;
1197
1198         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1199         if (status)
1200                 return status;
1201
1202         if (flags & I40E_AQC_SAN_ADDR_VALID)
1203                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1204                         I40E_NONDMA_TO_NONDMA);
1205         else
1206                 status = I40E_ERR_INVALID_MAC_ADDR;
1207
1208         return status;
1209 }
1210
1211 /**
1212  *  i40e_read_pba_string - Reads part number string from EEPROM
1213  *  @hw: pointer to hardware structure
1214  *  @pba_num: stores the part number string from the EEPROM
1215  *  @pba_num_size: part number string buffer length
1216  *
1217  *  Reads the part number string from the EEPROM.
1218  **/
1219 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1220                                             u32 pba_num_size)
1221 {
1222         enum i40e_status_code status = I40E_SUCCESS;
1223         u16 pba_word = 0;
1224         u16 pba_size = 0;
1225         u16 pba_ptr = 0;
1226         u16 i = 0;
1227
1228         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1229         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1230                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1231                 return status;
1232         }
1233
1234         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1235         if (status != I40E_SUCCESS) {
1236                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1237                 return status;
1238         }
1239
1240         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1241         if (status != I40E_SUCCESS) {
1242                 DEBUGOUT("Failed to read PBA Block size.\n");
1243                 return status;
1244         }
1245
1246         /* Subtract one to get PBA word count (PBA Size word is included in
1247          * total size)
1248          */
1249         pba_size--;
1250         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1251                 DEBUGOUT("Buffer to small for PBA data.\n");
1252                 return I40E_ERR_PARAM;
1253         }
1254
1255         for (i = 0; i < pba_size; i++) {
1256                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1257                 if (status != I40E_SUCCESS) {
1258                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1259                         return status;
1260                 }
1261
1262                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1263                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1264         }
1265         pba_num[(pba_size * 2)] = '\0';
1266
1267         return status;
1268 }
1269
1270 /**
1271  * i40e_get_media_type - Gets media type
1272  * @hw: pointer to the hardware structure
1273  **/
1274 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1275 {
1276         enum i40e_media_type media;
1277
1278         switch (hw->phy.link_info.phy_type) {
1279         case I40E_PHY_TYPE_10GBASE_SR:
1280         case I40E_PHY_TYPE_10GBASE_LR:
1281         case I40E_PHY_TYPE_1000BASE_SX:
1282         case I40E_PHY_TYPE_1000BASE_LX:
1283         case I40E_PHY_TYPE_40GBASE_SR4:
1284         case I40E_PHY_TYPE_40GBASE_LR4:
1285         case I40E_PHY_TYPE_25GBASE_LR:
1286         case I40E_PHY_TYPE_25GBASE_SR:
1287                 media = I40E_MEDIA_TYPE_FIBER;
1288                 break;
1289         case I40E_PHY_TYPE_100BASE_TX:
1290         case I40E_PHY_TYPE_1000BASE_T:
1291         case I40E_PHY_TYPE_10GBASE_T:
1292                 media = I40E_MEDIA_TYPE_BASET;
1293                 break;
1294         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1295         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1296         case I40E_PHY_TYPE_10GBASE_CR1:
1297         case I40E_PHY_TYPE_40GBASE_CR4:
1298         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1299         case I40E_PHY_TYPE_40GBASE_AOC:
1300         case I40E_PHY_TYPE_10GBASE_AOC:
1301         case I40E_PHY_TYPE_25GBASE_CR:
1302         case I40E_PHY_TYPE_25GBASE_AOC:
1303         case I40E_PHY_TYPE_25GBASE_ACC:
1304                 media = I40E_MEDIA_TYPE_DA;
1305                 break;
1306         case I40E_PHY_TYPE_1000BASE_KX:
1307         case I40E_PHY_TYPE_10GBASE_KX4:
1308         case I40E_PHY_TYPE_10GBASE_KR:
1309         case I40E_PHY_TYPE_40GBASE_KR4:
1310         case I40E_PHY_TYPE_20GBASE_KR2:
1311         case I40E_PHY_TYPE_25GBASE_KR:
1312                 media = I40E_MEDIA_TYPE_BACKPLANE;
1313                 break;
1314         case I40E_PHY_TYPE_SGMII:
1315         case I40E_PHY_TYPE_XAUI:
1316         case I40E_PHY_TYPE_XFI:
1317         case I40E_PHY_TYPE_XLAUI:
1318         case I40E_PHY_TYPE_XLPPI:
1319         default:
1320                 media = I40E_MEDIA_TYPE_UNKNOWN;
1321                 break;
1322         }
1323
1324         return media;
1325 }
1326
1327 #define I40E_PF_RESET_WAIT_COUNT        200
1328 /**
1329  * i40e_pf_reset - Reset the PF
1330  * @hw: pointer to the hardware structure
1331  *
1332  * Assuming someone else has triggered a global reset,
1333  * assure the global reset is complete and then reset the PF
1334  **/
1335 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1336 {
1337         u32 cnt = 0;
1338         u32 cnt1 = 0;
1339         u32 reg = 0;
1340         u32 grst_del;
1341
1342         /* Poll for Global Reset steady state in case of recent GRST.
1343          * The grst delay value is in 100ms units, and we'll wait a
1344          * couple counts longer to be sure we don't just miss the end.
1345          */
1346         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1347                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1348                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1349
1350         grst_del = grst_del * 20;
1351
1352         for (cnt = 0; cnt < grst_del; cnt++) {
1353                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1354                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1355                         break;
1356                 i40e_msec_delay(100);
1357         }
1358         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1359                 DEBUGOUT("Global reset polling failed to complete.\n");
1360                 return I40E_ERR_RESET_FAILED;
1361         }
1362
1363         /* Now Wait for the FW to be ready */
1364         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1365                 reg = rd32(hw, I40E_GLNVM_ULD);
1366                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1367                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1368                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1369                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1370                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1371                         break;
1372                 }
1373                 i40e_msec_delay(10);
1374         }
1375         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1376                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1377                 DEBUGOUT("wait for FW Reset complete timedout\n");
1378                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1379                 return I40E_ERR_RESET_FAILED;
1380         }
1381
1382         /* If there was a Global Reset in progress when we got here,
1383          * we don't need to do the PF Reset
1384          */
1385         if (!cnt) {
1386                 u32 reg2 = 0;
1387
1388                 reg = rd32(hw, I40E_PFGEN_CTRL);
1389                 wr32(hw, I40E_PFGEN_CTRL,
1390                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1391                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1392                         reg = rd32(hw, I40E_PFGEN_CTRL);
1393                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1394                                 break;
1395                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1396                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1397                                 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");
1398                                 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1399                                 return I40E_ERR_NOT_READY;
1400                         }
1401                         i40e_msec_delay(1);
1402                 }
1403                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1404                         DEBUGOUT("PF reset polling failed to complete.\n");
1405                         return I40E_ERR_RESET_FAILED;
1406                 }
1407         }
1408
1409         i40e_clear_pxe_mode(hw);
1410
1411
1412         return I40E_SUCCESS;
1413 }
1414
1415 /**
1416  * i40e_clear_hw - clear out any left over hw state
1417  * @hw: pointer to the hw struct
1418  *
1419  * Clear queues and interrupts, typically called at init time,
1420  * but after the capabilities have been found so we know how many
1421  * queues and msix vectors have been allocated.
1422  **/
1423 void i40e_clear_hw(struct i40e_hw *hw)
1424 {
1425         u32 num_queues, base_queue;
1426         u32 num_pf_int;
1427         u32 num_vf_int;
1428         u32 num_vfs;
1429         u32 i, j;
1430         u32 val;
1431         u32 eol = 0x7ff;
1432
1433         /* get number of interrupts, queues, and vfs */
1434         val = rd32(hw, I40E_GLPCI_CNF2);
1435         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1436                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1437         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1438                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1439
1440         val = rd32(hw, I40E_PFLAN_QALLOC);
1441         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1442                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1443         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1444                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1445         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1446                 num_queues = (j - base_queue) + 1;
1447         else
1448                 num_queues = 0;
1449
1450         val = rd32(hw, I40E_PF_VT_PFALLOC);
1451         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1452                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1453         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1454                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1455         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1456                 num_vfs = (j - i) + 1;
1457         else
1458                 num_vfs = 0;
1459
1460         /* stop all the interrupts */
1461         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1462         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1463         for (i = 0; i < num_pf_int - 2; i++)
1464                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1465
1466         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1467         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1468         wr32(hw, I40E_PFINT_LNKLST0, val);
1469         for (i = 0; i < num_pf_int - 2; i++)
1470                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1471         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1472         for (i = 0; i < num_vfs; i++)
1473                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1474         for (i = 0; i < num_vf_int - 2; i++)
1475                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1476
1477         /* warn the HW of the coming Tx disables */
1478         for (i = 0; i < num_queues; i++) {
1479                 u32 abs_queue_idx = base_queue + i;
1480                 u32 reg_block = 0;
1481
1482                 if (abs_queue_idx >= 128) {
1483                         reg_block = abs_queue_idx / 128;
1484                         abs_queue_idx %= 128;
1485                 }
1486
1487                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1488                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1489                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1490                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1491
1492                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1493         }
1494         i40e_usec_delay(400);
1495
1496         /* stop all the queues */
1497         for (i = 0; i < num_queues; i++) {
1498                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1499                 wr32(hw, I40E_QTX_ENA(i), 0);
1500                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1501                 wr32(hw, I40E_QRX_ENA(i), 0);
1502         }
1503
1504         /* short wait for all queue disables to settle */
1505         i40e_usec_delay(50);
1506 }
1507
1508 /**
1509  * i40e_clear_pxe_mode - clear pxe operations mode
1510  * @hw: pointer to the hw struct
1511  *
1512  * Make sure all PXE mode settings are cleared, including things
1513  * like descriptor fetch/write-back mode.
1514  **/
1515 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1516 {
1517         if (i40e_check_asq_alive(hw))
1518                 i40e_aq_clear_pxe_mode(hw, NULL);
1519 }
1520
1521 /**
1522  * i40e_led_is_mine - helper to find matching led
1523  * @hw: pointer to the hw struct
1524  * @idx: index into GPIO registers
1525  *
1526  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1527  */
1528 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1529 {
1530         u32 gpio_val = 0;
1531         u32 port;
1532
1533         if (!hw->func_caps.led[idx])
1534                 return 0;
1535
1536         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1537         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1538                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1539
1540         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1541          * if it is not our port then ignore
1542          */
1543         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1544             (port != hw->port))
1545                 return 0;
1546
1547         return gpio_val;
1548 }
1549
1550 #define I40E_COMBINED_ACTIVITY 0xA
1551 #define I40E_FILTER_ACTIVITY 0xE
1552 #define I40E_LINK_ACTIVITY 0xC
1553 #define I40E_MAC_ACTIVITY 0xD
1554 #define I40E_LED0 22
1555
1556 /**
1557  * i40e_led_get - return current on/off mode
1558  * @hw: pointer to the hw struct
1559  *
1560  * The value returned is the 'mode' field as defined in the
1561  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1562  * values are variations of possible behaviors relating to
1563  * blink, link, and wire.
1564  **/
1565 u32 i40e_led_get(struct i40e_hw *hw)
1566 {
1567         u32 current_mode = 0;
1568         u32 mode = 0;
1569         int i;
1570
1571         /* as per the documentation GPIO 22-29 are the LED
1572          * GPIO pins named LED0..LED7
1573          */
1574         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1575                 u32 gpio_val = i40e_led_is_mine(hw, i);
1576
1577                 if (!gpio_val)
1578                         continue;
1579
1580                 /* ignore gpio LED src mode entries related to the activity
1581                  *  LEDs
1582                  */
1583                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1584                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1585                 switch (current_mode) {
1586                 case I40E_COMBINED_ACTIVITY:
1587                 case I40E_FILTER_ACTIVITY:
1588                 case I40E_MAC_ACTIVITY:
1589                 case I40E_LINK_ACTIVITY:
1590                         continue;
1591                 default:
1592                         break;
1593                 }
1594
1595                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1596                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1597                 break;
1598         }
1599
1600         return mode;
1601 }
1602
1603 /**
1604  * i40e_led_set - set new on/off mode
1605  * @hw: pointer to the hw struct
1606  * @mode: 0=off, 0xf=on (else see manual for mode details)
1607  * @blink: true if the LED should blink when on, false if steady
1608  *
1609  * if this function is used to turn on the blink it should
1610  * be used to disable the blink when restoring the original state.
1611  **/
1612 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1613 {
1614         u32 current_mode = 0;
1615         int i;
1616
1617         if (mode & 0xfffffff0)
1618                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1619
1620         /* as per the documentation GPIO 22-29 are the LED
1621          * GPIO pins named LED0..LED7
1622          */
1623         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1624                 u32 gpio_val = i40e_led_is_mine(hw, i);
1625
1626                 if (!gpio_val)
1627                         continue;
1628
1629                 /* ignore gpio LED src mode entries related to the activity
1630                  * LEDs
1631                  */
1632                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1633                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1634                 switch (current_mode) {
1635                 case I40E_COMBINED_ACTIVITY:
1636                 case I40E_FILTER_ACTIVITY:
1637                 case I40E_MAC_ACTIVITY:
1638                 case I40E_LINK_ACTIVITY:
1639                         continue;
1640                 default:
1641                         break;
1642                 }
1643
1644                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1645                 /* this & is a bit of paranoia, but serves as a range check */
1646                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1647                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1648
1649                 if (blink)
1650                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1651                 else
1652                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1653
1654                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1655                 break;
1656         }
1657 }
1658
1659 /* Admin command wrappers */
1660
1661 /**
1662  * i40e_aq_get_phy_capabilities
1663  * @hw: pointer to the hw struct
1664  * @abilities: structure for PHY capabilities to be filled
1665  * @qualified_modules: report Qualified Modules
1666  * @report_init: report init capabilities (active are default)
1667  * @cmd_details: pointer to command details structure or NULL
1668  *
1669  * Returns the various PHY abilities supported on the Port.
1670  **/
1671 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1672                         bool qualified_modules, bool report_init,
1673                         struct i40e_aq_get_phy_abilities_resp *abilities,
1674                         struct i40e_asq_cmd_details *cmd_details)
1675 {
1676         struct i40e_aq_desc desc;
1677         enum i40e_status_code status;
1678         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1679         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1680
1681         if (!abilities)
1682                 return I40E_ERR_PARAM;
1683
1684         do {
1685                 i40e_fill_default_direct_cmd_desc(&desc,
1686                                                i40e_aqc_opc_get_phy_abilities);
1687
1688                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1689                 if (abilities_size > I40E_AQ_LARGE_BUF)
1690                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1691
1692                 if (qualified_modules)
1693                         desc.params.external.param0 |=
1694                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1695
1696                 if (report_init)
1697                         desc.params.external.param0 |=
1698                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1699
1700                 status = i40e_asq_send_command(hw, &desc, abilities,
1701                                                abilities_size, cmd_details);
1702
1703                 if (status != I40E_SUCCESS)
1704                         break;
1705
1706                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1707                         status = I40E_ERR_UNKNOWN_PHY;
1708                         break;
1709                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1710                         i40e_msec_delay(1);
1711                         total_delay++;
1712                         status = I40E_ERR_TIMEOUT;
1713                 }
1714         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1715                  (total_delay < max_delay));
1716
1717         if (status != I40E_SUCCESS)
1718                 return status;
1719
1720         if (report_init) {
1721                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1722                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1723                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1724                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1725                 } else {
1726                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1727                         hw->phy.phy_types |=
1728                                         ((u64)abilities->phy_type_ext << 32);
1729                 }
1730         }
1731
1732         return status;
1733 }
1734
1735 /**
1736  * i40e_aq_set_phy_config
1737  * @hw: pointer to the hw struct
1738  * @config: structure with PHY configuration to be set
1739  * @cmd_details: pointer to command details structure or NULL
1740  *
1741  * Set the various PHY configuration parameters
1742  * supported on the Port.One or more of the Set PHY config parameters may be
1743  * ignored in an MFP mode as the PF may not have the privilege to set some
1744  * of the PHY Config parameters. This status will be indicated by the
1745  * command response.
1746  **/
1747 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1748                                 struct i40e_aq_set_phy_config *config,
1749                                 struct i40e_asq_cmd_details *cmd_details)
1750 {
1751         struct i40e_aq_desc desc;
1752         struct i40e_aq_set_phy_config *cmd =
1753                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1754         enum i40e_status_code status;
1755
1756         if (!config)
1757                 return I40E_ERR_PARAM;
1758
1759         i40e_fill_default_direct_cmd_desc(&desc,
1760                                           i40e_aqc_opc_set_phy_config);
1761
1762         *cmd = *config;
1763
1764         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1765
1766         return status;
1767 }
1768
1769 /**
1770  * i40e_set_fc
1771  * @hw: pointer to the hw struct
1772  * @aq_failures: buffer to return AdminQ failure information
1773  * @atomic_restart: whether to enable atomic link restart
1774  *
1775  * Set the requested flow control mode using set_phy_config.
1776  **/
1777 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1778                                   bool atomic_restart)
1779 {
1780         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1781         struct i40e_aq_get_phy_abilities_resp abilities;
1782         struct i40e_aq_set_phy_config config;
1783         enum i40e_status_code status;
1784         u8 pause_mask = 0x0;
1785
1786         *aq_failures = 0x0;
1787
1788         switch (fc_mode) {
1789         case I40E_FC_FULL:
1790                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1791                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1792                 break;
1793         case I40E_FC_RX_PAUSE:
1794                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1795                 break;
1796         case I40E_FC_TX_PAUSE:
1797                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1798                 break;
1799         default:
1800                 break;
1801         }
1802
1803         /* Get the current phy config */
1804         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1805                                               NULL);
1806         if (status) {
1807                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1808                 return status;
1809         }
1810
1811         memset(&config, 0, sizeof(config));
1812         /* clear the old pause settings */
1813         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1814                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1815         /* set the new abilities */
1816         config.abilities |= pause_mask;
1817         /* If the abilities have changed, then set the new config */
1818         if (config.abilities != abilities.abilities) {
1819                 /* Auto restart link so settings take effect */
1820                 if (atomic_restart)
1821                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1822                 /* Copy over all the old settings */
1823                 config.phy_type = abilities.phy_type;
1824                 config.phy_type_ext = abilities.phy_type_ext;
1825                 config.link_speed = abilities.link_speed;
1826                 config.eee_capability = abilities.eee_capability;
1827                 config.eeer = abilities.eeer_val;
1828                 config.low_power_ctrl = abilities.d3_lpan;
1829                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1830                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1831                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1832
1833                 if (status)
1834                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1835         }
1836         /* Update the link info */
1837         status = i40e_update_link_info(hw);
1838         if (status) {
1839                 /* Wait a little bit (on 40G cards it sometimes takes a really
1840                  * long time for link to come back from the atomic reset)
1841                  * and try once more
1842                  */
1843                 i40e_msec_delay(1000);
1844                 status = i40e_update_link_info(hw);
1845         }
1846         if (status)
1847                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1848
1849         return status;
1850 }
1851
1852 /**
1853  * i40e_aq_set_mac_config
1854  * @hw: pointer to the hw struct
1855  * @max_frame_size: Maximum Frame Size to be supported by the port
1856  * @crc_en: Tell HW to append a CRC to outgoing frames
1857  * @pacing: Pacing configurations
1858  * @cmd_details: pointer to command details structure or NULL
1859  *
1860  * Configure MAC settings for frame size, jumbo frame support and the
1861  * addition of a CRC by the hardware.
1862  **/
1863 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1864                                 u16 max_frame_size,
1865                                 bool crc_en, u16 pacing,
1866                                 struct i40e_asq_cmd_details *cmd_details)
1867 {
1868         struct i40e_aq_desc desc;
1869         struct i40e_aq_set_mac_config *cmd =
1870                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1871         enum i40e_status_code status;
1872
1873         if (max_frame_size == 0)
1874                 return I40E_ERR_PARAM;
1875
1876         i40e_fill_default_direct_cmd_desc(&desc,
1877                                           i40e_aqc_opc_set_mac_config);
1878
1879         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1880         cmd->params = ((u8)pacing & 0x0F) << 3;
1881         if (crc_en)
1882                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1883
1884         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1885
1886         return status;
1887 }
1888
1889 /**
1890  * i40e_aq_clear_pxe_mode
1891  * @hw: pointer to the hw struct
1892  * @cmd_details: pointer to command details structure or NULL
1893  *
1894  * Tell the firmware that the driver is taking over from PXE
1895  **/
1896 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1897                         struct i40e_asq_cmd_details *cmd_details)
1898 {
1899         enum i40e_status_code status;
1900         struct i40e_aq_desc desc;
1901         struct i40e_aqc_clear_pxe *cmd =
1902                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1903
1904         i40e_fill_default_direct_cmd_desc(&desc,
1905                                           i40e_aqc_opc_clear_pxe_mode);
1906
1907         cmd->rx_cnt = 0x2;
1908
1909         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1910
1911         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1912
1913         return status;
1914 }
1915
1916 /**
1917  * i40e_aq_set_link_restart_an
1918  * @hw: pointer to the hw struct
1919  * @enable_link: if true: enable link, if false: disable link
1920  * @cmd_details: pointer to command details structure or NULL
1921  *
1922  * Sets up the link and restarts the Auto-Negotiation over the link.
1923  **/
1924 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1925                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1926 {
1927         struct i40e_aq_desc desc;
1928         struct i40e_aqc_set_link_restart_an *cmd =
1929                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1930         enum i40e_status_code status;
1931
1932         i40e_fill_default_direct_cmd_desc(&desc,
1933                                           i40e_aqc_opc_set_link_restart_an);
1934
1935         cmd->command = I40E_AQ_PHY_RESTART_AN;
1936         if (enable_link)
1937                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1938         else
1939                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1940
1941         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1942
1943         return status;
1944 }
1945
1946 /**
1947  * i40e_aq_get_link_info
1948  * @hw: pointer to the hw struct
1949  * @enable_lse: enable/disable LinkStatusEvent reporting
1950  * @link: pointer to link status structure - optional
1951  * @cmd_details: pointer to command details structure or NULL
1952  *
1953  * Returns the link status of the adapter.
1954  **/
1955 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1956                                 bool enable_lse, struct i40e_link_status *link,
1957                                 struct i40e_asq_cmd_details *cmd_details)
1958 {
1959         struct i40e_aq_desc desc;
1960         struct i40e_aqc_get_link_status *resp =
1961                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1962         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1963         enum i40e_status_code status;
1964         bool tx_pause, rx_pause;
1965         u16 command_flags;
1966
1967         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1968
1969         if (enable_lse)
1970                 command_flags = I40E_AQ_LSE_ENABLE;
1971         else
1972                 command_flags = I40E_AQ_LSE_DISABLE;
1973         resp->command_flags = CPU_TO_LE16(command_flags);
1974
1975         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1976
1977         if (status != I40E_SUCCESS)
1978                 goto aq_get_link_info_exit;
1979
1980         /* save off old link status information */
1981         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1982                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1983
1984         /* update link status */
1985         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1986         hw->phy.media_type = i40e_get_media_type(hw);
1987         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1988         hw_link_info->link_info = resp->link_info;
1989         hw_link_info->an_info = resp->an_info;
1990         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1991                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1992         hw_link_info->ext_info = resp->ext_info;
1993         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1994         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1995         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1996
1997         /* update fc info */
1998         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1999         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2000         if (tx_pause & rx_pause)
2001                 hw->fc.current_mode = I40E_FC_FULL;
2002         else if (tx_pause)
2003                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2004         else if (rx_pause)
2005                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2006         else
2007                 hw->fc.current_mode = I40E_FC_NONE;
2008
2009         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2010                 hw_link_info->crc_enable = true;
2011         else
2012                 hw_link_info->crc_enable = false;
2013
2014         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2015                 hw_link_info->lse_enable = true;
2016         else
2017                 hw_link_info->lse_enable = false;
2018
2019         if ((hw->mac.type == I40E_MAC_XL710) &&
2020             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2021              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2022                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2023
2024         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2025             hw->aq.api_min_ver >= 7) {
2026                 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type);
2027                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2028         }
2029
2030         /* save link status information */
2031         if (link)
2032                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2033                             I40E_NONDMA_TO_NONDMA);
2034
2035         /* flag cleared so helper functions don't call AQ again */
2036         hw->phy.get_link_info = false;
2037
2038 aq_get_link_info_exit:
2039         return status;
2040 }
2041
2042 /**
2043  * i40e_aq_set_phy_int_mask
2044  * @hw: pointer to the hw struct
2045  * @mask: interrupt mask to be set
2046  * @cmd_details: pointer to command details structure or NULL
2047  *
2048  * Set link interrupt mask.
2049  **/
2050 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2051                                 u16 mask,
2052                                 struct i40e_asq_cmd_details *cmd_details)
2053 {
2054         struct i40e_aq_desc desc;
2055         struct i40e_aqc_set_phy_int_mask *cmd =
2056                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2057         enum i40e_status_code status;
2058
2059         i40e_fill_default_direct_cmd_desc(&desc,
2060                                           i40e_aqc_opc_set_phy_int_mask);
2061
2062         cmd->event_mask = CPU_TO_LE16(mask);
2063
2064         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2065
2066         return status;
2067 }
2068
2069 /**
2070  * i40e_aq_get_local_advt_reg
2071  * @hw: pointer to the hw struct
2072  * @advt_reg: local AN advertisement register value
2073  * @cmd_details: pointer to command details structure or NULL
2074  *
2075  * Get the Local AN advertisement register value.
2076  **/
2077 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2078                                 u64 *advt_reg,
2079                                 struct i40e_asq_cmd_details *cmd_details)
2080 {
2081         struct i40e_aq_desc desc;
2082         struct i40e_aqc_an_advt_reg *resp =
2083                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2084         enum i40e_status_code status;
2085
2086         i40e_fill_default_direct_cmd_desc(&desc,
2087                                           i40e_aqc_opc_get_local_advt_reg);
2088
2089         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2090
2091         if (status != I40E_SUCCESS)
2092                 goto aq_get_local_advt_reg_exit;
2093
2094         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2095         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2096
2097 aq_get_local_advt_reg_exit:
2098         return status;
2099 }
2100
2101 /**
2102  * i40e_aq_set_local_advt_reg
2103  * @hw: pointer to the hw struct
2104  * @advt_reg: local AN advertisement register value
2105  * @cmd_details: pointer to command details structure or NULL
2106  *
2107  * Get the Local AN advertisement register value.
2108  **/
2109 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2110                                 u64 advt_reg,
2111                                 struct i40e_asq_cmd_details *cmd_details)
2112 {
2113         struct i40e_aq_desc desc;
2114         struct i40e_aqc_an_advt_reg *cmd =
2115                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2116         enum i40e_status_code status;
2117
2118         i40e_fill_default_direct_cmd_desc(&desc,
2119                                           i40e_aqc_opc_get_local_advt_reg);
2120
2121         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2122         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2123
2124         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2125
2126         return status;
2127 }
2128
2129 /**
2130  * i40e_aq_get_partner_advt
2131  * @hw: pointer to the hw struct
2132  * @advt_reg: AN partner advertisement register value
2133  * @cmd_details: pointer to command details structure or NULL
2134  *
2135  * Get the link partner AN advertisement register value.
2136  **/
2137 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2138                                 u64 *advt_reg,
2139                                 struct i40e_asq_cmd_details *cmd_details)
2140 {
2141         struct i40e_aq_desc desc;
2142         struct i40e_aqc_an_advt_reg *resp =
2143                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2144         enum i40e_status_code status;
2145
2146         i40e_fill_default_direct_cmd_desc(&desc,
2147                                           i40e_aqc_opc_get_partner_advt);
2148
2149         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2150
2151         if (status != I40E_SUCCESS)
2152                 goto aq_get_partner_advt_exit;
2153
2154         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2155         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2156
2157 aq_get_partner_advt_exit:
2158         return status;
2159 }
2160
2161 /**
2162  * i40e_aq_set_lb_modes
2163  * @hw: pointer to the hw struct
2164  * @lb_modes: loopback mode to be set
2165  * @cmd_details: pointer to command details structure or NULL
2166  *
2167  * Sets loopback modes.
2168  **/
2169 enum i40e_status_code
2170 i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed,
2171                      struct i40e_asq_cmd_details *cmd_details)
2172 {
2173         struct i40e_aq_desc desc;
2174         struct i40e_aqc_set_lb_mode *cmd =
2175                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2176         enum i40e_status_code status;
2177
2178         i40e_fill_default_direct_cmd_desc(&desc,
2179                                           i40e_aqc_opc_set_lb_modes);
2180
2181         cmd->lb_level = lb_level;
2182         cmd->lb_type = lb_type;
2183         cmd->speed = speed;
2184         if (speed)
2185                 cmd->force_speed = 1;
2186
2187         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2188
2189         return status;
2190 }
2191
2192 /**
2193  * i40e_aq_set_phy_debug
2194  * @hw: pointer to the hw struct
2195  * @cmd_flags: debug command flags
2196  * @cmd_details: pointer to command details structure or NULL
2197  *
2198  * Reset the external PHY.
2199  **/
2200 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2201                                 struct i40e_asq_cmd_details *cmd_details)
2202 {
2203         struct i40e_aq_desc desc;
2204         struct i40e_aqc_set_phy_debug *cmd =
2205                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2206         enum i40e_status_code status;
2207
2208         i40e_fill_default_direct_cmd_desc(&desc,
2209                                           i40e_aqc_opc_set_phy_debug);
2210
2211         cmd->command_flags = cmd_flags;
2212
2213         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2214
2215         return status;
2216 }
2217
2218 /**
2219  * i40e_aq_add_vsi
2220  * @hw: pointer to the hw struct
2221  * @vsi_ctx: pointer to a vsi context struct
2222  * @cmd_details: pointer to command details structure or NULL
2223  *
2224  * Add a VSI context to the hardware.
2225 **/
2226 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2227                                 struct i40e_vsi_context *vsi_ctx,
2228                                 struct i40e_asq_cmd_details *cmd_details)
2229 {
2230         struct i40e_aq_desc desc;
2231         struct i40e_aqc_add_get_update_vsi *cmd =
2232                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2233         struct i40e_aqc_add_get_update_vsi_completion *resp =
2234                 (struct i40e_aqc_add_get_update_vsi_completion *)
2235                 &desc.params.raw;
2236         enum i40e_status_code status;
2237
2238         i40e_fill_default_direct_cmd_desc(&desc,
2239                                           i40e_aqc_opc_add_vsi);
2240
2241         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2242         cmd->connection_type = vsi_ctx->connection_type;
2243         cmd->vf_id = vsi_ctx->vf_num;
2244         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2245
2246         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2247
2248         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2249                                     sizeof(vsi_ctx->info), cmd_details);
2250
2251         if (status != I40E_SUCCESS)
2252                 goto aq_add_vsi_exit;
2253
2254         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2255         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2256         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2257         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2258
2259 aq_add_vsi_exit:
2260         return status;
2261 }
2262
2263 /**
2264  * i40e_aq_set_default_vsi
2265  * @hw: pointer to the hw struct
2266  * @seid: vsi number
2267  * @cmd_details: pointer to command details structure or NULL
2268  **/
2269 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2270                                 u16 seid,
2271                                 struct i40e_asq_cmd_details *cmd_details)
2272 {
2273         struct i40e_aq_desc desc;
2274         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2275                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2276                 &desc.params.raw;
2277         enum i40e_status_code status;
2278
2279         i40e_fill_default_direct_cmd_desc(&desc,
2280                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2281
2282         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2283         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2284         cmd->seid = CPU_TO_LE16(seid);
2285
2286         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2287
2288         return status;
2289 }
2290
2291 /**
2292  * i40e_aq_clear_default_vsi
2293  * @hw: pointer to the hw struct
2294  * @seid: vsi number
2295  * @cmd_details: pointer to command details structure or NULL
2296  **/
2297 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2298                                 u16 seid,
2299                                 struct i40e_asq_cmd_details *cmd_details)
2300 {
2301         struct i40e_aq_desc desc;
2302         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2303                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2304                 &desc.params.raw;
2305         enum i40e_status_code status;
2306
2307         i40e_fill_default_direct_cmd_desc(&desc,
2308                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2309
2310         cmd->promiscuous_flags = CPU_TO_LE16(0);
2311         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2312         cmd->seid = CPU_TO_LE16(seid);
2313
2314         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2315
2316         return status;
2317 }
2318
2319 /**
2320  * i40e_aq_set_vsi_unicast_promiscuous
2321  * @hw: pointer to the hw struct
2322  * @seid: vsi number
2323  * @set: set unicast promiscuous enable/disable
2324  * @cmd_details: pointer to command details structure or NULL
2325  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2326  **/
2327 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2328                                 u16 seid, bool set,
2329                                 struct i40e_asq_cmd_details *cmd_details,
2330                                 bool rx_only_promisc)
2331 {
2332         struct i40e_aq_desc desc;
2333         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2334                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2335         enum i40e_status_code status;
2336         u16 flags = 0;
2337
2338         i40e_fill_default_direct_cmd_desc(&desc,
2339                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2340
2341         if (set) {
2342                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2343                 if (rx_only_promisc &&
2344                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2345                      (hw->aq.api_maj_ver > 1)))
2346                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2347         }
2348
2349         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2350
2351         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2352         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2353              (hw->aq.api_maj_ver > 1))
2354                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2355
2356         cmd->seid = CPU_TO_LE16(seid);
2357         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2358
2359         return status;
2360 }
2361
2362 /**
2363  * i40e_aq_set_vsi_multicast_promiscuous
2364  * @hw: pointer to the hw struct
2365  * @seid: vsi number
2366  * @set: set multicast promiscuous enable/disable
2367  * @cmd_details: pointer to command details structure or NULL
2368  **/
2369 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2370                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2371 {
2372         struct i40e_aq_desc desc;
2373         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2374                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2375         enum i40e_status_code status;
2376         u16 flags = 0;
2377
2378         i40e_fill_default_direct_cmd_desc(&desc,
2379                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2380
2381         if (set)
2382                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2383
2384         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2385
2386         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2387
2388         cmd->seid = CPU_TO_LE16(seid);
2389         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2390
2391         return status;
2392 }
2393
2394 /**
2395 * i40e_aq_set_vsi_full_promiscuous
2396 * @hw: pointer to the hw struct
2397 * @seid: VSI number
2398 * @set: set promiscuous enable/disable
2399 * @cmd_details: pointer to command details structure or NULL
2400 **/
2401 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2402                                 u16 seid, bool set,
2403                                 struct i40e_asq_cmd_details *cmd_details)
2404 {
2405         struct i40e_aq_desc desc;
2406         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2407                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2408         enum i40e_status_code status;
2409         u16 flags = 0;
2410
2411         i40e_fill_default_direct_cmd_desc(&desc,
2412                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2413
2414         if (set)
2415                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2416                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2417                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2418
2419         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2420
2421         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2422                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2423                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2424
2425         cmd->seid = CPU_TO_LE16(seid);
2426         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2427
2428         return status;
2429 }
2430
2431 /**
2432  * i40e_aq_set_vsi_mc_promisc_on_vlan
2433  * @hw: pointer to the hw struct
2434  * @seid: vsi number
2435  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2436  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2437  * @cmd_details: pointer to command details structure or NULL
2438  **/
2439 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2440                                 u16 seid, bool enable, u16 vid,
2441                                 struct i40e_asq_cmd_details *cmd_details)
2442 {
2443         struct i40e_aq_desc desc;
2444         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2445                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2446         enum i40e_status_code status;
2447         u16 flags = 0;
2448
2449         i40e_fill_default_direct_cmd_desc(&desc,
2450                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2451
2452         if (enable)
2453                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2454
2455         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2456         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2457         cmd->seid = CPU_TO_LE16(seid);
2458         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2459
2460         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2461
2462         return status;
2463 }
2464
2465 /**
2466  * i40e_aq_set_vsi_uc_promisc_on_vlan
2467  * @hw: pointer to the hw struct
2468  * @seid: vsi number
2469  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2470  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2471  * @cmd_details: pointer to command details structure or NULL
2472  **/
2473 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2474                                 u16 seid, bool enable, u16 vid,
2475                                 struct i40e_asq_cmd_details *cmd_details)
2476 {
2477         struct i40e_aq_desc desc;
2478         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2479                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2480         enum i40e_status_code status;
2481         u16 flags = 0;
2482
2483         i40e_fill_default_direct_cmd_desc(&desc,
2484                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2485
2486         if (enable)
2487                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2488
2489         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2490         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2491         cmd->seid = CPU_TO_LE16(seid);
2492         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2493
2494         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2495
2496         return status;
2497 }
2498
2499 /**
2500  * i40e_aq_set_vsi_bc_promisc_on_vlan
2501  * @hw: pointer to the hw struct
2502  * @seid: vsi number
2503  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2504  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2505  * @cmd_details: pointer to command details structure or NULL
2506  **/
2507 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2508                                 u16 seid, bool enable, u16 vid,
2509                                 struct i40e_asq_cmd_details *cmd_details)
2510 {
2511         struct i40e_aq_desc desc;
2512         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2513                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2514         enum i40e_status_code status;
2515         u16 flags = 0;
2516
2517         i40e_fill_default_direct_cmd_desc(&desc,
2518                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2519
2520         if (enable)
2521                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2522
2523         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2524         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2525         cmd->seid = CPU_TO_LE16(seid);
2526         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2527
2528         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2529
2530         return status;
2531 }
2532
2533 /**
2534  * i40e_aq_set_vsi_broadcast
2535  * @hw: pointer to the hw struct
2536  * @seid: vsi number
2537  * @set_filter: true to set filter, false to clear filter
2538  * @cmd_details: pointer to command details structure or NULL
2539  *
2540  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2541  **/
2542 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2543                                 u16 seid, bool set_filter,
2544                                 struct i40e_asq_cmd_details *cmd_details)
2545 {
2546         struct i40e_aq_desc desc;
2547         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2548                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2549         enum i40e_status_code status;
2550
2551         i40e_fill_default_direct_cmd_desc(&desc,
2552                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2553
2554         if (set_filter)
2555                 cmd->promiscuous_flags
2556                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2557         else
2558                 cmd->promiscuous_flags
2559                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2560
2561         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2562         cmd->seid = CPU_TO_LE16(seid);
2563         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2564
2565         return status;
2566 }
2567
2568 /**
2569  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2570  * @hw: pointer to the hw struct
2571  * @seid: vsi number
2572  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2573  * @cmd_details: pointer to command details structure or NULL
2574  **/
2575 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2576                                 u16 seid, bool enable,
2577                                 struct i40e_asq_cmd_details *cmd_details)
2578 {
2579         struct i40e_aq_desc desc;
2580         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2581                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2582         enum i40e_status_code status;
2583         u16 flags = 0;
2584
2585         i40e_fill_default_direct_cmd_desc(&desc,
2586                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2587         if (enable)
2588                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2589
2590         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2591         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2592         cmd->seid = CPU_TO_LE16(seid);
2593
2594         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2595
2596         return status;
2597 }
2598
2599 /**
2600  * i40e_get_vsi_params - get VSI configuration info
2601  * @hw: pointer to the hw struct
2602  * @vsi_ctx: pointer to a vsi context struct
2603  * @cmd_details: pointer to command details structure or NULL
2604  **/
2605 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2606                                 struct i40e_vsi_context *vsi_ctx,
2607                                 struct i40e_asq_cmd_details *cmd_details)
2608 {
2609         struct i40e_aq_desc desc;
2610         struct i40e_aqc_add_get_update_vsi *cmd =
2611                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2612         struct i40e_aqc_add_get_update_vsi_completion *resp =
2613                 (struct i40e_aqc_add_get_update_vsi_completion *)
2614                 &desc.params.raw;
2615         enum i40e_status_code status;
2616
2617         UNREFERENCED_1PARAMETER(cmd_details);
2618         i40e_fill_default_direct_cmd_desc(&desc,
2619                                           i40e_aqc_opc_get_vsi_parameters);
2620
2621         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2622
2623         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2624
2625         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2626                                     sizeof(vsi_ctx->info), NULL);
2627
2628         if (status != I40E_SUCCESS)
2629                 goto aq_get_vsi_params_exit;
2630
2631         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2632         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2633         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2634         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2635
2636 aq_get_vsi_params_exit:
2637         return status;
2638 }
2639
2640 /**
2641  * i40e_aq_update_vsi_params
2642  * @hw: pointer to the hw struct
2643  * @vsi_ctx: pointer to a vsi context struct
2644  * @cmd_details: pointer to command details structure or NULL
2645  *
2646  * Update a VSI context.
2647  **/
2648 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2649                                 struct i40e_vsi_context *vsi_ctx,
2650                                 struct i40e_asq_cmd_details *cmd_details)
2651 {
2652         struct i40e_aq_desc desc;
2653         struct i40e_aqc_add_get_update_vsi *cmd =
2654                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2655         struct i40e_aqc_add_get_update_vsi_completion *resp =
2656                 (struct i40e_aqc_add_get_update_vsi_completion *)
2657                 &desc.params.raw;
2658         enum i40e_status_code status;
2659
2660         i40e_fill_default_direct_cmd_desc(&desc,
2661                                           i40e_aqc_opc_update_vsi_parameters);
2662         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2663
2664         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2665
2666         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2667                                     sizeof(vsi_ctx->info), cmd_details);
2668
2669         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2670         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2671
2672         return status;
2673 }
2674
2675 /**
2676  * i40e_aq_get_switch_config
2677  * @hw: pointer to the hardware structure
2678  * @buf: pointer to the result buffer
2679  * @buf_size: length of input buffer
2680  * @start_seid: seid to start for the report, 0 == beginning
2681  * @cmd_details: pointer to command details structure or NULL
2682  *
2683  * Fill the buf with switch configuration returned from AdminQ command
2684  **/
2685 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2686                                 struct i40e_aqc_get_switch_config_resp *buf,
2687                                 u16 buf_size, u16 *start_seid,
2688                                 struct i40e_asq_cmd_details *cmd_details)
2689 {
2690         struct i40e_aq_desc desc;
2691         struct i40e_aqc_switch_seid *scfg =
2692                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2693         enum i40e_status_code status;
2694
2695         i40e_fill_default_direct_cmd_desc(&desc,
2696                                           i40e_aqc_opc_get_switch_config);
2697         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2698         if (buf_size > I40E_AQ_LARGE_BUF)
2699                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2700         scfg->seid = CPU_TO_LE16(*start_seid);
2701
2702         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2703         *start_seid = LE16_TO_CPU(scfg->seid);
2704
2705         return status;
2706 }
2707
2708 /**
2709  * i40e_aq_set_switch_config
2710  * @hw: pointer to the hardware structure
2711  * @flags: bit flag values to set
2712  * @valid_flags: which bit flags to set
2713  * @cmd_details: pointer to command details structure or NULL
2714  *
2715  * Set switch configuration bits
2716  **/
2717 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2718                                 u16 flags, u16 valid_flags,
2719                                 struct i40e_asq_cmd_details *cmd_details)
2720 {
2721         struct i40e_aq_desc desc;
2722         struct i40e_aqc_set_switch_config *scfg =
2723                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2724         enum i40e_status_code status;
2725
2726         i40e_fill_default_direct_cmd_desc(&desc,
2727                                           i40e_aqc_opc_set_switch_config);
2728         scfg->flags = CPU_TO_LE16(flags);
2729         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2730         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2731                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2732                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2733                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2734         }
2735         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2736
2737         return status;
2738 }
2739
2740 /**
2741  * i40e_aq_get_firmware_version
2742  * @hw: pointer to the hw struct
2743  * @fw_major_version: firmware major version
2744  * @fw_minor_version: firmware minor version
2745  * @fw_build: firmware build number
2746  * @api_major_version: major queue version
2747  * @api_minor_version: minor queue version
2748  * @cmd_details: pointer to command details structure or NULL
2749  *
2750  * Get the firmware version from the admin queue commands
2751  **/
2752 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2753                                 u16 *fw_major_version, u16 *fw_minor_version,
2754                                 u32 *fw_build,
2755                                 u16 *api_major_version, u16 *api_minor_version,
2756                                 struct i40e_asq_cmd_details *cmd_details)
2757 {
2758         struct i40e_aq_desc desc;
2759         struct i40e_aqc_get_version *resp =
2760                 (struct i40e_aqc_get_version *)&desc.params.raw;
2761         enum i40e_status_code status;
2762
2763         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2764
2765         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2766
2767         if (status == I40E_SUCCESS) {
2768                 if (fw_major_version != NULL)
2769                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2770                 if (fw_minor_version != NULL)
2771                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2772                 if (fw_build != NULL)
2773                         *fw_build = LE32_TO_CPU(resp->fw_build);
2774                 if (api_major_version != NULL)
2775                         *api_major_version = LE16_TO_CPU(resp->api_major);
2776                 if (api_minor_version != NULL)
2777                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2778
2779                 /* A workaround to fix the API version in SW */
2780                 if (api_major_version && api_minor_version &&
2781                     fw_major_version && fw_minor_version &&
2782                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2783                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2784                      (*fw_major_version > 4)))
2785                         *api_minor_version = 2;
2786         }
2787
2788         return status;
2789 }
2790
2791 /**
2792  * i40e_aq_send_driver_version
2793  * @hw: pointer to the hw struct
2794  * @dv: driver's major, minor version
2795  * @cmd_details: pointer to command details structure or NULL
2796  *
2797  * Send the driver version to the firmware
2798  **/
2799 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2800                                 struct i40e_driver_version *dv,
2801                                 struct i40e_asq_cmd_details *cmd_details)
2802 {
2803         struct i40e_aq_desc desc;
2804         struct i40e_aqc_driver_version *cmd =
2805                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2806         enum i40e_status_code status;
2807         u16 len;
2808
2809         if (dv == NULL)
2810                 return I40E_ERR_PARAM;
2811
2812         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2813
2814         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2815         cmd->driver_major_ver = dv->major_version;
2816         cmd->driver_minor_ver = dv->minor_version;
2817         cmd->driver_build_ver = dv->build_version;
2818         cmd->driver_subbuild_ver = dv->subbuild_version;
2819
2820         len = 0;
2821         while (len < sizeof(dv->driver_string) &&
2822                (dv->driver_string[len] < 0x80) &&
2823                dv->driver_string[len])
2824                 len++;
2825         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2826                                        len, cmd_details);
2827
2828         return status;
2829 }
2830
2831 /**
2832  * i40e_get_link_status - get status of the HW network link
2833  * @hw: pointer to the hw struct
2834  * @link_up: pointer to bool (true/false = linkup/linkdown)
2835  *
2836  * Variable link_up true if link is up, false if link is down.
2837  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2838  *
2839  * Side effect: LinkStatusEvent reporting becomes enabled
2840  **/
2841 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2842 {
2843         enum i40e_status_code status = I40E_SUCCESS;
2844
2845         if (hw->phy.get_link_info) {
2846                 status = i40e_update_link_info(hw);
2847
2848                 if (status != I40E_SUCCESS)
2849                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2850                                    status);
2851         }
2852
2853         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2854
2855         return status;
2856 }
2857
2858 /**
2859  * i40e_updatelink_status - update status of the HW network link
2860  * @hw: pointer to the hw struct
2861  **/
2862 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2863 {
2864         struct i40e_aq_get_phy_abilities_resp abilities;
2865         enum i40e_status_code status = I40E_SUCCESS;
2866
2867         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2868         if (status)
2869                 return status;
2870
2871         /* extra checking needed to ensure link info to user is timely */
2872         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2873             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2874              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2875                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2876                                                       &abilities, NULL);
2877                 if (status)
2878                         return status;
2879
2880                 hw->phy.link_info.req_fec_info =
2881                         abilities.fec_cfg_curr_mod_ext_info &
2882                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2883
2884                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2885                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2886         }
2887         return status;
2888 }
2889
2890
2891 /**
2892  * i40e_get_link_speed
2893  * @hw: pointer to the hw struct
2894  *
2895  * Returns the link speed of the adapter.
2896  **/
2897 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2898 {
2899         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2900         enum i40e_status_code status = I40E_SUCCESS;
2901
2902         if (hw->phy.get_link_info) {
2903                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2904
2905                 if (status != I40E_SUCCESS)
2906                         goto i40e_link_speed_exit;
2907         }
2908
2909         speed = hw->phy.link_info.link_speed;
2910
2911 i40e_link_speed_exit:
2912         return speed;
2913 }
2914
2915 /**
2916  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2917  * @hw: pointer to the hw struct
2918  * @uplink_seid: the MAC or other gizmo SEID
2919  * @downlink_seid: the VSI SEID
2920  * @enabled_tc: bitmap of TCs to be enabled
2921  * @default_port: true for default port VSI, false for control port
2922  * @veb_seid: pointer to where to put the resulting VEB SEID
2923  * @enable_stats: true to turn on VEB stats
2924  * @cmd_details: pointer to command details structure or NULL
2925  *
2926  * This asks the FW to add a VEB between the uplink and downlink
2927  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2928  **/
2929 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2930                                 u16 downlink_seid, u8 enabled_tc,
2931                                 bool default_port, u16 *veb_seid,
2932                                 bool enable_stats,
2933                                 struct i40e_asq_cmd_details *cmd_details)
2934 {
2935         struct i40e_aq_desc desc;
2936         struct i40e_aqc_add_veb *cmd =
2937                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2938         struct i40e_aqc_add_veb_completion *resp =
2939                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2940         enum i40e_status_code status;
2941         u16 veb_flags = 0;
2942
2943         /* SEIDs need to either both be set or both be 0 for floating VEB */
2944         if (!!uplink_seid != !!downlink_seid)
2945                 return I40E_ERR_PARAM;
2946
2947         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2948
2949         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2950         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2951         cmd->enable_tcs = enabled_tc;
2952         if (!uplink_seid)
2953                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2954         if (default_port)
2955                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2956         else
2957                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2958
2959         /* reverse logic here: set the bitflag to disable the stats */
2960         if (!enable_stats)
2961                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2962
2963         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2964
2965         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2966
2967         if (!status && veb_seid)
2968                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2969
2970         return status;
2971 }
2972
2973 /**
2974  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2975  * @hw: pointer to the hw struct
2976  * @veb_seid: the SEID of the VEB to query
2977  * @switch_id: the uplink switch id
2978  * @floating: set to true if the VEB is floating
2979  * @statistic_index: index of the stats counter block for this VEB
2980  * @vebs_used: number of VEB's used by function
2981  * @vebs_free: total VEB's not reserved by any function
2982  * @cmd_details: pointer to command details structure or NULL
2983  *
2984  * This retrieves the parameters for a particular VEB, specified by
2985  * uplink_seid, and returns them to the caller.
2986  **/
2987 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2988                                 u16 veb_seid, u16 *switch_id,
2989                                 bool *floating, u16 *statistic_index,
2990                                 u16 *vebs_used, u16 *vebs_free,
2991                                 struct i40e_asq_cmd_details *cmd_details)
2992 {
2993         struct i40e_aq_desc desc;
2994         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2995                 (struct i40e_aqc_get_veb_parameters_completion *)
2996                 &desc.params.raw;
2997         enum i40e_status_code status;
2998
2999         if (veb_seid == 0)
3000                 return I40E_ERR_PARAM;
3001
3002         i40e_fill_default_direct_cmd_desc(&desc,
3003                                           i40e_aqc_opc_get_veb_parameters);
3004         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3005
3006         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3007         if (status)
3008                 goto get_veb_exit;
3009
3010         if (switch_id)
3011                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3012         if (statistic_index)
3013                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3014         if (vebs_used)
3015                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3016         if (vebs_free)
3017                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3018         if (floating) {
3019                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3020
3021                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3022                         *floating = true;
3023                 else
3024                         *floating = false;
3025         }
3026
3027 get_veb_exit:
3028         return status;
3029 }
3030
3031 /**
3032  * i40e_aq_add_macvlan
3033  * @hw: pointer to the hw struct
3034  * @seid: VSI for the mac address
3035  * @mv_list: list of macvlans to be added
3036  * @count: length of the list
3037  * @cmd_details: pointer to command details structure or NULL
3038  *
3039  * Add MAC/VLAN addresses to the HW filtering
3040  **/
3041 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3042                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3043                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3044 {
3045         struct i40e_aq_desc desc;
3046         struct i40e_aqc_macvlan *cmd =
3047                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3048         enum i40e_status_code status;
3049         u16 buf_size;
3050         int i;
3051
3052         if (count == 0 || !mv_list || !hw)
3053                 return I40E_ERR_PARAM;
3054
3055         buf_size = count * sizeof(*mv_list);
3056
3057         /* prep the rest of the request */
3058         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3059         cmd->num_addresses = CPU_TO_LE16(count);
3060         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3061         cmd->seid[1] = 0;
3062         cmd->seid[2] = 0;
3063
3064         for (i = 0; i < count; i++)
3065                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3066                         mv_list[i].flags |=
3067                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3068
3069         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3070         if (buf_size > I40E_AQ_LARGE_BUF)
3071                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3072
3073         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3074                                        cmd_details);
3075
3076         return status;
3077 }
3078
3079 /**
3080  * i40e_aq_remove_macvlan
3081  * @hw: pointer to the hw struct
3082  * @seid: VSI for the mac address
3083  * @mv_list: list of macvlans to be removed
3084  * @count: length of the list
3085  * @cmd_details: pointer to command details structure or NULL
3086  *
3087  * Remove MAC/VLAN addresses from the HW filtering
3088  **/
3089 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3090                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3091                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3092 {
3093         struct i40e_aq_desc desc;
3094         struct i40e_aqc_macvlan *cmd =
3095                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3096         enum i40e_status_code status;
3097         u16 buf_size;
3098
3099         if (count == 0 || !mv_list || !hw)
3100                 return I40E_ERR_PARAM;
3101
3102         buf_size = count * sizeof(*mv_list);
3103
3104         /* prep the rest of the request */
3105         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3106         cmd->num_addresses = CPU_TO_LE16(count);
3107         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3108         cmd->seid[1] = 0;
3109         cmd->seid[2] = 0;
3110
3111         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3112         if (buf_size > I40E_AQ_LARGE_BUF)
3113                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3114
3115         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3116                                        cmd_details);
3117
3118         return status;
3119 }
3120
3121 /**
3122  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3123  * @hw: pointer to the hw struct
3124  * @opcode: AQ opcode for add or delete mirror rule
3125  * @sw_seid: Switch SEID (to which rule refers)
3126  * @rule_type: Rule Type (ingress/egress/VLAN)
3127  * @id: Destination VSI SEID or Rule ID
3128  * @count: length of the list
3129  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3130  * @cmd_details: pointer to command details structure or NULL
3131  * @rule_id: Rule ID returned from FW
3132  * @rules_used: Number of rules used in internal switch
3133  * @rules_free: Number of rules free in internal switch
3134  *
3135  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3136  * VEBs/VEPA elements only
3137  **/
3138 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3139                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3140                         u16 count, __le16 *mr_list,
3141                         struct i40e_asq_cmd_details *cmd_details,
3142                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3143 {
3144         struct i40e_aq_desc desc;
3145         struct i40e_aqc_add_delete_mirror_rule *cmd =
3146                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3147         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3148         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3149         enum i40e_status_code status;
3150         u16 buf_size;
3151
3152         buf_size = count * sizeof(*mr_list);
3153
3154         /* prep the rest of the request */
3155         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3156         cmd->seid = CPU_TO_LE16(sw_seid);
3157         cmd->rule_type = CPU_TO_LE16(rule_type &
3158                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3159         cmd->num_entries = CPU_TO_LE16(count);
3160         /* Dest VSI for add, rule_id for delete */
3161         cmd->destination = CPU_TO_LE16(id);
3162         if (mr_list) {
3163                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3164                                                 I40E_AQ_FLAG_RD));
3165                 if (buf_size > I40E_AQ_LARGE_BUF)
3166                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3167         }
3168
3169         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3170                                        cmd_details);
3171         if (status == I40E_SUCCESS ||
3172             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3173                 if (rule_id)
3174                         *rule_id = LE16_TO_CPU(resp->rule_id);
3175                 if (rules_used)
3176                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3177                 if (rules_free)
3178                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3179         }
3180         return status;
3181 }
3182
3183 /**
3184  * i40e_aq_add_mirrorrule - add a mirror rule
3185  * @hw: pointer to the hw struct
3186  * @sw_seid: Switch SEID (to which rule refers)
3187  * @rule_type: Rule Type (ingress/egress/VLAN)
3188  * @dest_vsi: SEID of VSI to which packets will be mirrored
3189  * @count: length of the list
3190  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3191  * @cmd_details: pointer to command details structure or NULL
3192  * @rule_id: Rule ID returned from FW
3193  * @rules_used: Number of rules used in internal switch
3194  * @rules_free: Number of rules free in internal switch
3195  *
3196  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3197  **/
3198 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3199                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3200                         struct i40e_asq_cmd_details *cmd_details,
3201                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3202 {
3203         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3204             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3205                 if (count == 0 || !mr_list)
3206                         return I40E_ERR_PARAM;
3207         }
3208
3209         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3210                                   rule_type, dest_vsi, count, mr_list,
3211                                   cmd_details, rule_id, rules_used, rules_free);
3212 }
3213
3214 /**
3215  * i40e_aq_delete_mirrorrule - delete a mirror rule
3216  * @hw: pointer to the hw struct
3217  * @sw_seid: Switch SEID (to which rule refers)
3218  * @rule_type: Rule Type (ingress/egress/VLAN)
3219  * @count: length of the list
3220  * @rule_id: Rule ID that is returned in the receive desc as part of
3221  *              add_mirrorrule.
3222  * @mr_list: list of mirrored VLAN IDs to be removed
3223  * @cmd_details: pointer to command details structure or NULL
3224  * @rules_used: Number of rules used in internal switch
3225  * @rules_free: Number of rules free in internal switch
3226  *
3227  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3228  **/
3229 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3230                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3231                         struct i40e_asq_cmd_details *cmd_details,
3232                         u16 *rules_used, u16 *rules_free)
3233 {
3234         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3235         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3236                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3237                  * mirroring. For other rule_type, count and rule_type should
3238                  * not matter.
3239                  */
3240                 if (count == 0 || !mr_list)
3241                         return I40E_ERR_PARAM;
3242         }
3243
3244         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3245                                   rule_type, rule_id, count, mr_list,
3246                                   cmd_details, NULL, rules_used, rules_free);
3247 }
3248
3249 /**
3250  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3251  * @hw: pointer to the hw struct
3252  * @seid: VSI for the vlan filters
3253  * @v_list: list of vlan filters to be added
3254  * @count: length of the list
3255  * @cmd_details: pointer to command details structure or NULL
3256  **/
3257 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3258                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3259                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3260 {
3261         struct i40e_aq_desc desc;
3262         struct i40e_aqc_macvlan *cmd =
3263                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3264         enum i40e_status_code status;
3265         u16 buf_size;
3266
3267         if (count == 0 || !v_list || !hw)
3268                 return I40E_ERR_PARAM;
3269
3270         buf_size = count * sizeof(*v_list);
3271
3272         /* prep the rest of the request */
3273         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3274         cmd->num_addresses = CPU_TO_LE16(count);
3275         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3276         cmd->seid[1] = 0;
3277         cmd->seid[2] = 0;
3278
3279         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3280         if (buf_size > I40E_AQ_LARGE_BUF)
3281                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3282
3283         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3284                                        cmd_details);
3285
3286         return status;
3287 }
3288
3289 /**
3290  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3291  * @hw: pointer to the hw struct
3292  * @seid: VSI for the vlan filters
3293  * @v_list: list of macvlans to be removed
3294  * @count: length of the list
3295  * @cmd_details: pointer to command details structure or NULL
3296  **/
3297 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3298                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3299                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3300 {
3301         struct i40e_aq_desc desc;
3302         struct i40e_aqc_macvlan *cmd =
3303                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3304         enum i40e_status_code status;
3305         u16 buf_size;
3306
3307         if (count == 0 || !v_list || !hw)
3308                 return I40E_ERR_PARAM;
3309
3310         buf_size = count * sizeof(*v_list);
3311
3312         /* prep the rest of the request */
3313         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3314         cmd->num_addresses = CPU_TO_LE16(count);
3315         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3316         cmd->seid[1] = 0;
3317         cmd->seid[2] = 0;
3318
3319         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3320         if (buf_size > I40E_AQ_LARGE_BUF)
3321                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3322
3323         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3324                                        cmd_details);
3325
3326         return status;
3327 }
3328
3329 /**
3330  * i40e_aq_send_msg_to_vf
3331  * @hw: pointer to the hardware structure
3332  * @vfid: vf id to send msg
3333  * @v_opcode: opcodes for VF-PF communication
3334  * @v_retval: return error code
3335  * @msg: pointer to the msg buffer
3336  * @msglen: msg length
3337  * @cmd_details: pointer to command details
3338  *
3339  * send msg to vf
3340  **/
3341 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3342                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3343                                 struct i40e_asq_cmd_details *cmd_details)
3344 {
3345         struct i40e_aq_desc desc;
3346         struct i40e_aqc_pf_vf_message *cmd =
3347                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3348         enum i40e_status_code status;
3349
3350         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3351         cmd->id = CPU_TO_LE32(vfid);
3352         desc.cookie_high = CPU_TO_LE32(v_opcode);
3353         desc.cookie_low = CPU_TO_LE32(v_retval);
3354         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3355         if (msglen) {
3356                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3357                                                 I40E_AQ_FLAG_RD));
3358                 if (msglen > I40E_AQ_LARGE_BUF)
3359                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3360                 desc.datalen = CPU_TO_LE16(msglen);
3361         }
3362         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3363
3364         return status;
3365 }
3366
3367 /**
3368  * i40e_aq_debug_read_register
3369  * @hw: pointer to the hw struct
3370  * @reg_addr: register address
3371  * @reg_val: register value
3372  * @cmd_details: pointer to command details structure or NULL
3373  *
3374  * Read the register using the admin queue commands
3375  **/
3376 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3377                                 u32 reg_addr, u64 *reg_val,
3378                                 struct i40e_asq_cmd_details *cmd_details)
3379 {
3380         struct i40e_aq_desc desc;
3381         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3382                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3383         enum i40e_status_code status;
3384
3385         if (reg_val == NULL)
3386                 return I40E_ERR_PARAM;
3387
3388         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3389
3390         cmd_resp->address = CPU_TO_LE32(reg_addr);
3391
3392         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3393
3394         if (status == I40E_SUCCESS) {
3395                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3396                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3397         }
3398
3399         return status;
3400 }
3401
3402 /**
3403  * i40e_aq_debug_write_register
3404  * @hw: pointer to the hw struct
3405  * @reg_addr: register address
3406  * @reg_val: register value
3407  * @cmd_details: pointer to command details structure or NULL
3408  *
3409  * Write to a register using the admin queue commands
3410  **/
3411 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3412                                 u32 reg_addr, u64 reg_val,
3413                                 struct i40e_asq_cmd_details *cmd_details)
3414 {
3415         struct i40e_aq_desc desc;
3416         struct i40e_aqc_debug_reg_read_write *cmd =
3417                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3418         enum i40e_status_code status;
3419
3420         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3421
3422         cmd->address = CPU_TO_LE32(reg_addr);
3423         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3424         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3425
3426         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3427
3428         return status;
3429 }
3430
3431 /**
3432  * i40e_aq_request_resource
3433  * @hw: pointer to the hw struct
3434  * @resource: resource id
3435  * @access: access type
3436  * @sdp_number: resource number
3437  * @timeout: the maximum time in ms that the driver may hold the resource
3438  * @cmd_details: pointer to command details structure or NULL
3439  *
3440  * requests common resource using the admin queue commands
3441  **/
3442 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3443                                 enum i40e_aq_resources_ids resource,
3444                                 enum i40e_aq_resource_access_type access,
3445                                 u8 sdp_number, u64 *timeout,
3446                                 struct i40e_asq_cmd_details *cmd_details)
3447 {
3448         struct i40e_aq_desc desc;
3449         struct i40e_aqc_request_resource *cmd_resp =
3450                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3451         enum i40e_status_code status;
3452
3453         DEBUGFUNC("i40e_aq_request_resource");
3454
3455         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3456
3457         cmd_resp->resource_id = CPU_TO_LE16(resource);
3458         cmd_resp->access_type = CPU_TO_LE16(access);
3459         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3460
3461         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3462         /* The completion specifies the maximum time in ms that the driver
3463          * may hold the resource in the Timeout field.
3464          * If the resource is held by someone else, the command completes with
3465          * busy return value and the timeout field indicates the maximum time
3466          * the current owner of the resource has to free it.
3467          */
3468         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3469                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3470
3471         return status;
3472 }
3473
3474 /**
3475  * i40e_aq_release_resource
3476  * @hw: pointer to the hw struct
3477  * @resource: resource id
3478  * @sdp_number: resource number
3479  * @cmd_details: pointer to command details structure or NULL
3480  *
3481  * release common resource using the admin queue commands
3482  **/
3483 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3484                                 enum i40e_aq_resources_ids resource,
3485                                 u8 sdp_number,
3486                                 struct i40e_asq_cmd_details *cmd_details)
3487 {
3488         struct i40e_aq_desc desc;
3489         struct i40e_aqc_request_resource *cmd =
3490                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3491         enum i40e_status_code status;
3492
3493         DEBUGFUNC("i40e_aq_release_resource");
3494
3495         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3496
3497         cmd->resource_id = CPU_TO_LE16(resource);
3498         cmd->resource_number = CPU_TO_LE32(sdp_number);
3499
3500         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3501
3502         return status;
3503 }
3504
3505 /**
3506  * i40e_aq_read_nvm
3507  * @hw: pointer to the hw struct
3508  * @module_pointer: module pointer location in words from the NVM beginning
3509  * @offset: byte offset from the module beginning
3510  * @length: length of the section to be read (in bytes from the offset)
3511  * @data: command buffer (size [bytes] = length)
3512  * @last_command: tells if this is the last command in a series
3513  * @cmd_details: pointer to command details structure or NULL
3514  *
3515  * Read the NVM using the admin queue commands
3516  **/
3517 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3518                                 u32 offset, u16 length, void *data,
3519                                 bool last_command,
3520                                 struct i40e_asq_cmd_details *cmd_details)
3521 {
3522         struct i40e_aq_desc desc;
3523         struct i40e_aqc_nvm_update *cmd =
3524                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3525         enum i40e_status_code status;
3526
3527         DEBUGFUNC("i40e_aq_read_nvm");
3528
3529         /* In offset the highest byte must be zeroed. */
3530         if (offset & 0xFF000000) {
3531                 status = I40E_ERR_PARAM;
3532                 goto i40e_aq_read_nvm_exit;
3533         }
3534
3535         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3536
3537         /* If this is the last command in a series, set the proper flag. */
3538         if (last_command)
3539                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3540         cmd->module_pointer = module_pointer;
3541         cmd->offset = CPU_TO_LE32(offset);
3542         cmd->length = CPU_TO_LE16(length);
3543
3544         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3545         if (length > I40E_AQ_LARGE_BUF)
3546                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3547
3548         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3549
3550 i40e_aq_read_nvm_exit:
3551         return status;
3552 }
3553
3554 /**
3555  * i40e_aq_read_nvm_config - read an nvm config block
3556  * @hw: pointer to the hw struct
3557  * @cmd_flags: NVM access admin command bits
3558  * @field_id: field or feature id
3559  * @data: buffer for result
3560  * @buf_size: buffer size
3561  * @element_count: pointer to count of elements read by FW
3562  * @cmd_details: pointer to command details structure or NULL
3563  **/
3564 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3565                                 u8 cmd_flags, u32 field_id, void *data,
3566                                 u16 buf_size, u16 *element_count,
3567                                 struct i40e_asq_cmd_details *cmd_details)
3568 {
3569         struct i40e_aq_desc desc;
3570         struct i40e_aqc_nvm_config_read *cmd =
3571                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3572         enum i40e_status_code status;
3573
3574         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3575         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3576         if (buf_size > I40E_AQ_LARGE_BUF)
3577                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3578
3579         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3580         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3581         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3582                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3583         else
3584                 cmd->element_id_msw = 0;
3585
3586         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3587
3588         if (!status && element_count)
3589                 *element_count = LE16_TO_CPU(cmd->element_count);
3590
3591         return status;
3592 }
3593
3594 /**
3595  * i40e_aq_write_nvm_config - write an nvm config block
3596  * @hw: pointer to the hw struct
3597  * @cmd_flags: NVM access admin command bits
3598  * @data: buffer for result
3599  * @buf_size: buffer size
3600  * @element_count: count of elements to be written
3601  * @cmd_details: pointer to command details structure or NULL
3602  **/
3603 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3604                                 u8 cmd_flags, void *data, u16 buf_size,
3605                                 u16 element_count,
3606                                 struct i40e_asq_cmd_details *cmd_details)
3607 {
3608         struct i40e_aq_desc desc;
3609         struct i40e_aqc_nvm_config_write *cmd =
3610                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3611         enum i40e_status_code status;
3612
3613         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3614         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3615         if (buf_size > I40E_AQ_LARGE_BUF)
3616                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3617
3618         cmd->element_count = CPU_TO_LE16(element_count);
3619         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3620         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3621
3622         return status;
3623 }
3624
3625 /**
3626  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3627  * @hw: pointer to the hw struct
3628  * @buff: buffer for result
3629  * @buff_size: buffer size
3630  * @cmd_details: pointer to command details structure or NULL
3631  **/
3632 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3633                                 void *buff, u16 buff_size,
3634                                 struct i40e_asq_cmd_details *cmd_details)
3635 {
3636         struct i40e_aq_desc desc;
3637         enum i40e_status_code status;
3638
3639         UNREFERENCED_2PARAMETER(buff, buff_size);
3640
3641         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3642         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3643         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3644                 status = I40E_ERR_NOT_IMPLEMENTED;
3645
3646         return status;
3647 }
3648
3649 /**
3650  * i40e_aq_erase_nvm
3651  * @hw: pointer to the hw struct
3652  * @module_pointer: module pointer location in words from the NVM beginning
3653  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3654  * @length: length of the section to be erased (expressed in 4 KB)
3655  * @last_command: tells if this is the last command in a series
3656  * @cmd_details: pointer to command details structure or NULL
3657  *
3658  * Erase the NVM sector using the admin queue commands
3659  **/
3660 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3661                                 u32 offset, u16 length, bool last_command,
3662                                 struct i40e_asq_cmd_details *cmd_details)
3663 {
3664         struct i40e_aq_desc desc;
3665         struct i40e_aqc_nvm_update *cmd =
3666                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3667         enum i40e_status_code status;
3668
3669         DEBUGFUNC("i40e_aq_erase_nvm");
3670
3671         /* In offset the highest byte must be zeroed. */
3672         if (offset & 0xFF000000) {
3673                 status = I40E_ERR_PARAM;
3674                 goto i40e_aq_erase_nvm_exit;
3675         }
3676
3677         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3678
3679         /* If this is the last command in a series, set the proper flag. */
3680         if (last_command)
3681                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3682         cmd->module_pointer = module_pointer;
3683         cmd->offset = CPU_TO_LE32(offset);
3684         cmd->length = CPU_TO_LE16(length);
3685
3686         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3687
3688 i40e_aq_erase_nvm_exit:
3689         return status;
3690 }
3691
3692 /**
3693  * i40e_parse_discover_capabilities
3694  * @hw: pointer to the hw struct
3695  * @buff: pointer to a buffer containing device/function capability records
3696  * @cap_count: number of capability records in the list
3697  * @list_type_opc: type of capabilities list to parse
3698  *
3699  * Parse the device/function capabilities list.
3700  **/
3701 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3702                                      u32 cap_count,
3703                                      enum i40e_admin_queue_opc list_type_opc)
3704 {
3705         struct i40e_aqc_list_capabilities_element_resp *cap;
3706         u32 valid_functions, num_functions;
3707         u32 number, logical_id, phys_id;
3708         struct i40e_hw_capabilities *p;
3709         u8 major_rev;
3710         u32 i = 0;
3711         u16 id;
3712
3713         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3714
3715         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3716                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3717         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3718                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3719         else
3720                 return;
3721
3722         for (i = 0; i < cap_count; i++, cap++) {
3723                 id = LE16_TO_CPU(cap->id);
3724                 number = LE32_TO_CPU(cap->number);
3725                 logical_id = LE32_TO_CPU(cap->logical_id);
3726                 phys_id = LE32_TO_CPU(cap->phys_id);
3727                 major_rev = cap->major_rev;
3728
3729                 switch (id) {
3730                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3731                         p->switch_mode = number;
3732                         i40e_debug(hw, I40E_DEBUG_INIT,
3733                                    "HW Capability: Switch mode = %d\n",
3734                                    p->switch_mode);
3735                         break;
3736                 case I40E_AQ_CAP_ID_MNG_MODE:
3737                         p->management_mode = number;
3738                         if (major_rev > 1) {
3739                                 p->mng_protocols_over_mctp = logical_id;
3740                                 i40e_debug(hw, I40E_DEBUG_INIT,
3741                                            "HW Capability: Protocols over MCTP = %d\n",
3742                                            p->mng_protocols_over_mctp);
3743                         } else {
3744                                 p->mng_protocols_over_mctp = 0;
3745                         }
3746                         i40e_debug(hw, I40E_DEBUG_INIT,
3747                                    "HW Capability: Management Mode = %d\n",
3748                                    p->management_mode);
3749                         break;
3750                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3751                         p->npar_enable = number;
3752                         i40e_debug(hw, I40E_DEBUG_INIT,
3753                                    "HW Capability: NPAR enable = %d\n",
3754                                    p->npar_enable);
3755                         break;
3756                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3757                         p->os2bmc = number;
3758                         i40e_debug(hw, I40E_DEBUG_INIT,
3759                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3760                         break;
3761                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3762                         p->valid_functions = number;
3763                         i40e_debug(hw, I40E_DEBUG_INIT,
3764                                    "HW Capability: Valid Functions = %d\n",
3765                                    p->valid_functions);
3766                         break;
3767                 case I40E_AQ_CAP_ID_SRIOV:
3768                         if (number == 1)
3769                                 p->sr_iov_1_1 = true;
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: SR-IOV = %d\n",
3772                                    p->sr_iov_1_1);
3773                         break;
3774                 case I40E_AQ_CAP_ID_VF:
3775                         p->num_vfs = number;
3776                         p->vf_base_id = logical_id;
3777                         i40e_debug(hw, I40E_DEBUG_INIT,
3778                                    "HW Capability: VF count = %d\n",
3779                                    p->num_vfs);
3780                         i40e_debug(hw, I40E_DEBUG_INIT,
3781                                    "HW Capability: VF base_id = %d\n",
3782                                    p->vf_base_id);
3783                         break;
3784                 case I40E_AQ_CAP_ID_VMDQ:
3785                         if (number == 1)
3786                                 p->vmdq = true;
3787                         i40e_debug(hw, I40E_DEBUG_INIT,
3788                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3789                         break;
3790                 case I40E_AQ_CAP_ID_8021QBG:
3791                         if (number == 1)
3792                                 p->evb_802_1_qbg = true;
3793                         i40e_debug(hw, I40E_DEBUG_INIT,
3794                                    "HW Capability: 802.1Qbg = %d\n", number);
3795                         break;
3796                 case I40E_AQ_CAP_ID_8021QBR:
3797                         if (number == 1)
3798                                 p->evb_802_1_qbh = true;
3799                         i40e_debug(hw, I40E_DEBUG_INIT,
3800                                    "HW Capability: 802.1Qbh = %d\n", number);
3801                         break;
3802                 case I40E_AQ_CAP_ID_VSI:
3803                         p->num_vsis = number;
3804                         i40e_debug(hw, I40E_DEBUG_INIT,
3805                                    "HW Capability: VSI count = %d\n",
3806                                    p->num_vsis);
3807                         break;
3808                 case I40E_AQ_CAP_ID_DCB:
3809                         if (number == 1) {
3810                                 p->dcb = true;
3811                                 p->enabled_tcmap = logical_id;
3812                                 p->maxtc = phys_id;
3813                         }
3814                         i40e_debug(hw, I40E_DEBUG_INIT,
3815                                    "HW Capability: DCB = %d\n", p->dcb);
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: TC Mapping = %d\n",
3818                                    logical_id);
3819                         i40e_debug(hw, I40E_DEBUG_INIT,
3820                                    "HW Capability: TC Max = %d\n", p->maxtc);
3821                         break;
3822                 case I40E_AQ_CAP_ID_FCOE:
3823                         if (number == 1)
3824                                 p->fcoe = true;
3825                         i40e_debug(hw, I40E_DEBUG_INIT,
3826                                    "HW Capability: FCOE = %d\n", p->fcoe);
3827                         break;
3828                 case I40E_AQ_CAP_ID_ISCSI:
3829                         if (number == 1)
3830                                 p->iscsi = true;
3831                         i40e_debug(hw, I40E_DEBUG_INIT,
3832                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3833                         break;
3834                 case I40E_AQ_CAP_ID_RSS:
3835                         p->rss = true;
3836                         p->rss_table_size = number;
3837                         p->rss_table_entry_width = logical_id;
3838                         i40e_debug(hw, I40E_DEBUG_INIT,
3839                                    "HW Capability: RSS = %d\n", p->rss);
3840                         i40e_debug(hw, I40E_DEBUG_INIT,
3841                                    "HW Capability: RSS table size = %d\n",
3842                                    p->rss_table_size);
3843                         i40e_debug(hw, I40E_DEBUG_INIT,
3844                                    "HW Capability: RSS table width = %d\n",
3845                                    p->rss_table_entry_width);
3846                         break;
3847                 case I40E_AQ_CAP_ID_RXQ:
3848                         p->num_rx_qp = number;
3849                         p->base_queue = phys_id;
3850                         i40e_debug(hw, I40E_DEBUG_INIT,
3851                                    "HW Capability: Rx QP = %d\n", number);
3852                         i40e_debug(hw, I40E_DEBUG_INIT,
3853                                    "HW Capability: base_queue = %d\n",
3854                                    p->base_queue);
3855                         break;
3856                 case I40E_AQ_CAP_ID_TXQ:
3857                         p->num_tx_qp = number;
3858                         p->base_queue = phys_id;
3859                         i40e_debug(hw, I40E_DEBUG_INIT,
3860                                    "HW Capability: Tx QP = %d\n", number);
3861                         i40e_debug(hw, I40E_DEBUG_INIT,
3862                                    "HW Capability: base_queue = %d\n",
3863                                    p->base_queue);
3864                         break;
3865                 case I40E_AQ_CAP_ID_MSIX:
3866                         p->num_msix_vectors = number;
3867                         i40e_debug(hw, I40E_DEBUG_INIT,
3868                                    "HW Capability: MSIX vector count = %d\n",
3869                                    p->num_msix_vectors);
3870                         break;
3871                 case I40E_AQ_CAP_ID_VF_MSIX:
3872                         p->num_msix_vectors_vf = number;
3873                         i40e_debug(hw, I40E_DEBUG_INIT,
3874                                    "HW Capability: MSIX VF vector count = %d\n",
3875                                    p->num_msix_vectors_vf);
3876                         break;
3877                 case I40E_AQ_CAP_ID_FLEX10:
3878                         if (major_rev == 1) {
3879                                 if (number == 1) {
3880                                         p->flex10_enable = true;
3881                                         p->flex10_capable = true;
3882                                 }
3883                         } else {
3884                                 /* Capability revision >= 2 */
3885                                 if (number & 1)
3886                                         p->flex10_enable = true;
3887                                 if (number & 2)
3888                                         p->flex10_capable = true;
3889                         }
3890                         p->flex10_mode = logical_id;
3891                         p->flex10_status = phys_id;
3892                         i40e_debug(hw, I40E_DEBUG_INIT,
3893                                    "HW Capability: Flex10 mode = %d\n",
3894                                    p->flex10_mode);
3895                         i40e_debug(hw, I40E_DEBUG_INIT,
3896                                    "HW Capability: Flex10 status = %d\n",
3897                                    p->flex10_status);
3898                         break;
3899                 case I40E_AQ_CAP_ID_CEM:
3900                         if (number == 1)
3901                                 p->mgmt_cem = true;
3902                         i40e_debug(hw, I40E_DEBUG_INIT,
3903                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3904                         break;
3905                 case I40E_AQ_CAP_ID_IWARP:
3906                         if (number == 1)
3907                                 p->iwarp = true;
3908                         i40e_debug(hw, I40E_DEBUG_INIT,
3909                                    "HW Capability: iWARP = %d\n", p->iwarp);
3910                         break;
3911                 case I40E_AQ_CAP_ID_LED:
3912                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3913                                 p->led[phys_id] = true;
3914                         i40e_debug(hw, I40E_DEBUG_INIT,
3915                                    "HW Capability: LED - PIN %d\n", phys_id);
3916                         break;
3917                 case I40E_AQ_CAP_ID_SDP:
3918                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3919                                 p->sdp[phys_id] = true;
3920                         i40e_debug(hw, I40E_DEBUG_INIT,
3921                                    "HW Capability: SDP - PIN %d\n", phys_id);
3922                         break;
3923                 case I40E_AQ_CAP_ID_MDIO:
3924                         if (number == 1) {
3925                                 p->mdio_port_num = phys_id;
3926                                 p->mdio_port_mode = logical_id;
3927                         }
3928                         i40e_debug(hw, I40E_DEBUG_INIT,
3929                                    "HW Capability: MDIO port number = %d\n",
3930                                    p->mdio_port_num);
3931                         i40e_debug(hw, I40E_DEBUG_INIT,
3932                                    "HW Capability: MDIO port mode = %d\n",
3933                                    p->mdio_port_mode);
3934                         break;
3935                 case I40E_AQ_CAP_ID_1588:
3936                         if (number == 1)
3937                                 p->ieee_1588 = true;
3938                         i40e_debug(hw, I40E_DEBUG_INIT,
3939                                    "HW Capability: IEEE 1588 = %d\n",
3940                                    p->ieee_1588);
3941                         break;
3942                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3943                         p->fd = true;
3944                         p->fd_filters_guaranteed = number;
3945                         p->fd_filters_best_effort = logical_id;
3946                         i40e_debug(hw, I40E_DEBUG_INIT,
3947                                    "HW Capability: Flow Director = 1\n");
3948                         i40e_debug(hw, I40E_DEBUG_INIT,
3949                                    "HW Capability: Guaranteed FD filters = %d\n",
3950                                    p->fd_filters_guaranteed);
3951                         break;
3952                 case I40E_AQ_CAP_ID_WSR_PROT:
3953                         p->wr_csr_prot = (u64)number;
3954                         p->wr_csr_prot |= (u64)logical_id << 32;
3955                         i40e_debug(hw, I40E_DEBUG_INIT,
3956                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3957                                    (p->wr_csr_prot & 0xffff));
3958                         break;
3959                 case I40E_AQ_CAP_ID_NVM_MGMT:
3960                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3961                                 p->sec_rev_disabled = true;
3962                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3963                                 p->update_disabled = true;
3964                         break;
3965                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3966                         hw->num_wol_proxy_filters = (u16)number;
3967                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3968                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3969                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3970                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3971                         else
3972                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3973                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3974                         i40e_debug(hw, I40E_DEBUG_INIT,
3975                                    "HW Capability: WOL proxy filters = %d\n",
3976                                    hw->num_wol_proxy_filters);
3977                         break;
3978                 default:
3979                         break;
3980                 }
3981         }
3982
3983         if (p->fcoe)
3984                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3985
3986         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3987         p->fcoe = false;
3988
3989         /* count the enabled ports (aka the "not disabled" ports) */
3990         hw->num_ports = 0;
3991         for (i = 0; i < 4; i++) {
3992                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3993                 u64 port_cfg = 0;
3994
3995                 /* use AQ read to get the physical register offset instead
3996                  * of the port relative offset
3997                  */
3998                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3999                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4000                         hw->num_ports++;
4001         }
4002
4003         valid_functions = p->valid_functions;
4004         num_functions = 0;
4005         while (valid_functions) {
4006                 if (valid_functions & 1)
4007                         num_functions++;
4008                 valid_functions >>= 1;
4009         }
4010
4011         /* partition id is 1-based, and functions are evenly spread
4012          * across the ports as partitions
4013          */
4014         if (hw->num_ports != 0) {
4015                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4016                 hw->num_partitions = num_functions / hw->num_ports;
4017         }
4018
4019         /* additional HW specific goodies that might
4020          * someday be HW version specific
4021          */
4022         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4023 }
4024
4025 /**
4026  * i40e_aq_discover_capabilities
4027  * @hw: pointer to the hw struct
4028  * @buff: a virtual buffer to hold the capabilities
4029  * @buff_size: Size of the virtual buffer
4030  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4031  * @list_type_opc: capabilities type to discover - pass in the command opcode
4032  * @cmd_details: pointer to command details structure or NULL
4033  *
4034  * Get the device capabilities descriptions from the firmware
4035  **/
4036 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4037                                 void *buff, u16 buff_size, u16 *data_size,
4038                                 enum i40e_admin_queue_opc list_type_opc,
4039                                 struct i40e_asq_cmd_details *cmd_details)
4040 {
4041         struct i40e_aqc_list_capabilites *cmd;
4042         struct i40e_aq_desc desc;
4043         enum i40e_status_code status = I40E_SUCCESS;
4044
4045         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4046
4047         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4048                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4049                 status = I40E_ERR_PARAM;
4050                 goto exit;
4051         }
4052
4053         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4054
4055         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4056         if (buff_size > I40E_AQ_LARGE_BUF)
4057                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4058
4059         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4060         *data_size = LE16_TO_CPU(desc.datalen);
4061
4062         if (status)
4063                 goto exit;
4064
4065         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4066                                          list_type_opc);
4067
4068 exit:
4069         return status;
4070 }
4071
4072 /**
4073  * i40e_aq_update_nvm
4074  * @hw: pointer to the hw struct
4075  * @module_pointer: module pointer location in words from the NVM beginning
4076  * @offset: byte offset from the module beginning
4077  * @length: length of the section to be written (in bytes from the offset)
4078  * @data: command buffer (size [bytes] = length)
4079  * @last_command: tells if this is the last command in a series
4080  * @preservation_flags: Preservation mode flags
4081  * @cmd_details: pointer to command details structure or NULL
4082  *
4083  * Update the NVM using the admin queue commands
4084  **/
4085 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4086                                 u32 offset, u16 length, void *data,
4087                                 bool last_command, u8 preservation_flags,
4088                                 struct i40e_asq_cmd_details *cmd_details)
4089 {
4090         struct i40e_aq_desc desc;
4091         struct i40e_aqc_nvm_update *cmd =
4092                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4093         enum i40e_status_code status;
4094
4095         DEBUGFUNC("i40e_aq_update_nvm");
4096
4097         /* In offset the highest byte must be zeroed. */
4098         if (offset & 0xFF000000) {
4099                 status = I40E_ERR_PARAM;
4100                 goto i40e_aq_update_nvm_exit;
4101         }
4102
4103         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4104
4105         /* If this is the last command in a series, set the proper flag. */
4106         if (last_command)
4107                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4108         if (hw->mac.type == I40E_MAC_X722) {
4109                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4110                         cmd->command_flags |=
4111                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4112                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4113                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4114                         cmd->command_flags |=
4115                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4116                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4117         }
4118         cmd->module_pointer = module_pointer;
4119         cmd->offset = CPU_TO_LE32(offset);
4120         cmd->length = CPU_TO_LE16(length);
4121
4122         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4123         if (length > I40E_AQ_LARGE_BUF)
4124                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4125
4126         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4127
4128 i40e_aq_update_nvm_exit:
4129         return status;
4130 }
4131
4132 /**
4133  * i40e_aq_nvm_progress
4134  * @hw: pointer to the hw struct
4135  * @progress: pointer to progress returned from AQ
4136  * @cmd_details: pointer to command details structure or NULL
4137  *
4138  * Gets progress of flash rearrangement process
4139  **/
4140 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4141                                 struct i40e_asq_cmd_details *cmd_details)
4142 {
4143         enum i40e_status_code status;
4144         struct i40e_aq_desc desc;
4145
4146         DEBUGFUNC("i40e_aq_nvm_progress");
4147
4148         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4149         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4150         *progress = desc.params.raw[0];
4151         return status;
4152 }
4153
4154 /**
4155  * i40e_aq_get_lldp_mib
4156  * @hw: pointer to the hw struct
4157  * @bridge_type: type of bridge requested
4158  * @mib_type: Local, Remote or both Local and Remote MIBs
4159  * @buff: pointer to a user supplied buffer to store the MIB block
4160  * @buff_size: size of the buffer (in bytes)
4161  * @local_len : length of the returned Local LLDP MIB
4162  * @remote_len: length of the returned Remote LLDP MIB
4163  * @cmd_details: pointer to command details structure or NULL
4164  *
4165  * Requests the complete LLDP MIB (entire packet).
4166  **/
4167 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4168                                 u8 mib_type, void *buff, u16 buff_size,
4169                                 u16 *local_len, u16 *remote_len,
4170                                 struct i40e_asq_cmd_details *cmd_details)
4171 {
4172         struct i40e_aq_desc desc;
4173         struct i40e_aqc_lldp_get_mib *cmd =
4174                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4175         struct i40e_aqc_lldp_get_mib *resp =
4176                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4177         enum i40e_status_code status;
4178
4179         if (buff_size == 0 || !buff)
4180                 return I40E_ERR_PARAM;
4181
4182         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4183         /* Indirect Command */
4184         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4185
4186         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4187         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4188                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4189
4190         desc.datalen = CPU_TO_LE16(buff_size);
4191
4192         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4193         if (buff_size > I40E_AQ_LARGE_BUF)
4194                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4195
4196         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4197         if (!status) {
4198                 if (local_len != NULL)
4199                         *local_len = LE16_TO_CPU(resp->local_len);
4200                 if (remote_len != NULL)
4201                         *remote_len = LE16_TO_CPU(resp->remote_len);
4202         }
4203
4204         return status;
4205 }
4206
4207  /**
4208  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4209  * @hw: pointer to the hw struct
4210  * @mib_type: Local, Remote or both Local and Remote MIBs
4211  * @buff: pointer to a user supplied buffer to store the MIB block
4212  * @buff_size: size of the buffer (in bytes)
4213  * @cmd_details: pointer to command details structure or NULL
4214  *
4215  * Set the LLDP MIB.
4216  **/
4217 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4218                                 u8 mib_type, void *buff, u16 buff_size,
4219                                 struct i40e_asq_cmd_details *cmd_details)
4220 {
4221         struct i40e_aq_desc desc;
4222         struct i40e_aqc_lldp_set_local_mib *cmd =
4223                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4224         enum i40e_status_code status;
4225
4226         if (buff_size == 0 || !buff)
4227                 return I40E_ERR_PARAM;
4228
4229         i40e_fill_default_direct_cmd_desc(&desc,
4230                                 i40e_aqc_opc_lldp_set_local_mib);
4231         /* Indirect Command */
4232         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4233         if (buff_size > I40E_AQ_LARGE_BUF)
4234                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4235         desc.datalen = CPU_TO_LE16(buff_size);
4236
4237         cmd->type = mib_type;
4238         cmd->length = CPU_TO_LE16(buff_size);
4239         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4240         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4241
4242         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4243         return status;
4244 }
4245
4246 /**
4247  * i40e_aq_cfg_lldp_mib_change_event
4248  * @hw: pointer to the hw struct
4249  * @enable_update: Enable or Disable event posting
4250  * @cmd_details: pointer to command details structure or NULL
4251  *
4252  * Enable or Disable posting of an event on ARQ when LLDP MIB
4253  * associated with the interface changes
4254  **/
4255 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4256                                 bool enable_update,
4257                                 struct i40e_asq_cmd_details *cmd_details)
4258 {
4259         struct i40e_aq_desc desc;
4260         struct i40e_aqc_lldp_update_mib *cmd =
4261                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4262         enum i40e_status_code status;
4263
4264         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4265
4266         if (!enable_update)
4267                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4268
4269         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4270
4271         return status;
4272 }
4273
4274 /**
4275  * i40e_aq_add_lldp_tlv
4276  * @hw: pointer to the hw struct
4277  * @bridge_type: type of bridge
4278  * @buff: buffer with TLV to add
4279  * @buff_size: length of the buffer
4280  * @tlv_len: length of the TLV to be added
4281  * @mib_len: length of the LLDP MIB returned in response
4282  * @cmd_details: pointer to command details structure or NULL
4283  *
4284  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4285  * it is responsibility of the caller to make sure that the TLV is not
4286  * already present in the LLDPDU.
4287  * In return firmware will write the complete LLDP MIB with the newly
4288  * added TLV in the response buffer.
4289  **/
4290 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4291                                 void *buff, u16 buff_size, u16 tlv_len,
4292                                 u16 *mib_len,
4293                                 struct i40e_asq_cmd_details *cmd_details)
4294 {
4295         struct i40e_aq_desc desc;
4296         struct i40e_aqc_lldp_add_tlv *cmd =
4297                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4298         enum i40e_status_code status;
4299
4300         if (buff_size == 0 || !buff || tlv_len == 0)
4301                 return I40E_ERR_PARAM;
4302
4303         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4304
4305         /* Indirect Command */
4306         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4307         if (buff_size > I40E_AQ_LARGE_BUF)
4308                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4309         desc.datalen = CPU_TO_LE16(buff_size);
4310
4311         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4312                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4313         cmd->len = CPU_TO_LE16(tlv_len);
4314
4315         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4316         if (!status) {
4317                 if (mib_len != NULL)
4318                         *mib_len = LE16_TO_CPU(desc.datalen);
4319         }
4320
4321         return status;
4322 }
4323
4324 /**
4325  * i40e_aq_update_lldp_tlv
4326  * @hw: pointer to the hw struct
4327  * @bridge_type: type of bridge
4328  * @buff: buffer with TLV to update
4329  * @buff_size: size of the buffer holding original and updated TLVs
4330  * @old_len: Length of the Original TLV
4331  * @new_len: Length of the Updated TLV
4332  * @offset: offset of the updated TLV in the buff
4333  * @mib_len: length of the returned LLDP MIB
4334  * @cmd_details: pointer to command details structure or NULL
4335  *
4336  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4337  * Firmware will place the complete LLDP MIB in response buffer with the
4338  * updated TLV.
4339  **/
4340 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4341                                 u8 bridge_type, void *buff, u16 buff_size,
4342                                 u16 old_len, u16 new_len, u16 offset,
4343                                 u16 *mib_len,
4344                                 struct i40e_asq_cmd_details *cmd_details)
4345 {
4346         struct i40e_aq_desc desc;
4347         struct i40e_aqc_lldp_update_tlv *cmd =
4348                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4349         enum i40e_status_code status;
4350
4351         if (buff_size == 0 || !buff || offset == 0 ||
4352             old_len == 0 || new_len == 0)
4353                 return I40E_ERR_PARAM;
4354
4355         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4356
4357         /* Indirect Command */
4358         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4359         if (buff_size > I40E_AQ_LARGE_BUF)
4360                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4361         desc.datalen = CPU_TO_LE16(buff_size);
4362
4363         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4364                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4365         cmd->old_len = CPU_TO_LE16(old_len);
4366         cmd->new_offset = CPU_TO_LE16(offset);
4367         cmd->new_len = CPU_TO_LE16(new_len);
4368
4369         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4370         if (!status) {
4371                 if (mib_len != NULL)
4372                         *mib_len = LE16_TO_CPU(desc.datalen);
4373         }
4374
4375         return status;
4376 }
4377
4378 /**
4379  * i40e_aq_delete_lldp_tlv
4380  * @hw: pointer to the hw struct
4381  * @bridge_type: type of bridge
4382  * @buff: pointer to a user supplied buffer that has the TLV
4383  * @buff_size: length of the buffer
4384  * @tlv_len: length of the TLV to be deleted
4385  * @mib_len: length of the returned LLDP MIB
4386  * @cmd_details: pointer to command details structure or NULL
4387  *
4388  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4389  * The firmware places the entire LLDP MIB in the response buffer.
4390  **/
4391 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4392                                 u8 bridge_type, void *buff, u16 buff_size,
4393                                 u16 tlv_len, u16 *mib_len,
4394                                 struct i40e_asq_cmd_details *cmd_details)
4395 {
4396         struct i40e_aq_desc desc;
4397         struct i40e_aqc_lldp_add_tlv *cmd =
4398                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4399         enum i40e_status_code status;
4400
4401         if (buff_size == 0 || !buff)
4402                 return I40E_ERR_PARAM;
4403
4404         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4405
4406         /* Indirect Command */
4407         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4408         if (buff_size > I40E_AQ_LARGE_BUF)
4409                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4410         desc.datalen = CPU_TO_LE16(buff_size);
4411         cmd->len = CPU_TO_LE16(tlv_len);
4412         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4413                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4414
4415         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4416         if (!status) {
4417                 if (mib_len != NULL)
4418                         *mib_len = LE16_TO_CPU(desc.datalen);
4419         }
4420
4421         return status;
4422 }
4423
4424 /**
4425  * i40e_aq_stop_lldp
4426  * @hw: pointer to the hw struct
4427  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4428  * @cmd_details: pointer to command details structure or NULL
4429  *
4430  * Stop or Shutdown the embedded LLDP Agent
4431  **/
4432 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4433                                 struct i40e_asq_cmd_details *cmd_details)
4434 {
4435         struct i40e_aq_desc desc;
4436         struct i40e_aqc_lldp_stop *cmd =
4437                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4438         enum i40e_status_code status;
4439
4440         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4441
4442         if (shutdown_agent)
4443                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4444
4445         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4446
4447         return status;
4448 }
4449
4450 /**
4451  * i40e_aq_start_lldp
4452  * @hw: pointer to the hw struct
4453  * @cmd_details: pointer to command details structure or NULL
4454  *
4455  * Start the embedded LLDP Agent on all ports.
4456  **/
4457 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4458                                 struct i40e_asq_cmd_details *cmd_details)
4459 {
4460         struct i40e_aq_desc desc;
4461         struct i40e_aqc_lldp_start *cmd =
4462                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4463         enum i40e_status_code status;
4464
4465         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4466
4467         cmd->command = I40E_AQ_LLDP_AGENT_START;
4468         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4469
4470         return status;
4471 }
4472
4473 /**
4474  * i40e_aq_set_dcb_parameters
4475  * @hw: pointer to the hw struct
4476  * @cmd_details: pointer to command details structure or NULL
4477  * @dcb_enable: True if DCB configuration needs to be applied
4478  *
4479  **/
4480 enum i40e_status_code
4481 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4482                            struct i40e_asq_cmd_details *cmd_details)
4483 {
4484         struct i40e_aq_desc desc;
4485         struct i40e_aqc_set_dcb_parameters *cmd =
4486                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4487         enum i40e_status_code status;
4488
4489         i40e_fill_default_direct_cmd_desc(&desc,
4490                                           i40e_aqc_opc_set_dcb_parameters);
4491
4492         if (dcb_enable) {
4493                 cmd->valid_flags = I40E_DCB_VALID;
4494                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4495         }
4496         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4497
4498         return status;
4499 }
4500
4501 /**
4502  * i40e_aq_get_cee_dcb_config
4503  * @hw: pointer to the hw struct
4504  * @buff: response buffer that stores CEE operational configuration
4505  * @buff_size: size of the buffer passed
4506  * @cmd_details: pointer to command details structure or NULL
4507  *
4508  * Get CEE DCBX mode operational configuration from firmware
4509  **/
4510 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4511                                 void *buff, u16 buff_size,
4512                                 struct i40e_asq_cmd_details *cmd_details)
4513 {
4514         struct i40e_aq_desc desc;
4515         enum i40e_status_code status;
4516
4517         if (buff_size == 0 || !buff)
4518                 return I40E_ERR_PARAM;
4519
4520         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4521
4522         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4523         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4524                                        cmd_details);
4525
4526         return status;
4527 }
4528
4529 /**
4530  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4531  * @hw: pointer to the hw struct
4532  * @start_agent: True if DCBx Agent needs to be Started
4533  *                              False if DCBx Agent needs to be Stopped
4534  * @cmd_details: pointer to command details structure or NULL
4535  *
4536  * Start/Stop the embedded dcbx Agent
4537  **/
4538 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4539                                 bool start_agent,
4540                                 struct i40e_asq_cmd_details *cmd_details)
4541 {
4542         struct i40e_aq_desc desc;
4543         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4544                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4545                                 &desc.params.raw;
4546         enum i40e_status_code status;
4547
4548         i40e_fill_default_direct_cmd_desc(&desc,
4549                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4550
4551         if (start_agent)
4552                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4553
4554         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4555
4556         return status;
4557 }
4558
4559 /**
4560  * i40e_aq_add_udp_tunnel
4561  * @hw: pointer to the hw struct
4562  * @udp_port: the UDP port to add in Host byte order
4563  * @protocol_index: protocol index type
4564  * @filter_index: pointer to filter index
4565  * @cmd_details: pointer to command details structure or NULL
4566  *
4567  * Note: Firmware expects the udp_port value to be in Little Endian format,
4568  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4569  * Little Endian order.
4570  **/
4571 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4572                                 u16 udp_port, u8 protocol_index,
4573                                 u8 *filter_index,
4574                                 struct i40e_asq_cmd_details *cmd_details)
4575 {
4576         struct i40e_aq_desc desc;
4577         struct i40e_aqc_add_udp_tunnel *cmd =
4578                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4579         struct i40e_aqc_del_udp_tunnel_completion *resp =
4580                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4581         enum i40e_status_code status;
4582
4583         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4584
4585         cmd->udp_port = CPU_TO_LE16(udp_port);
4586         cmd->protocol_type = protocol_index;
4587
4588         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4589
4590         if (!status && filter_index)
4591                 *filter_index = resp->index;
4592
4593         return status;
4594 }
4595
4596 /**
4597  * i40e_aq_del_udp_tunnel
4598  * @hw: pointer to the hw struct
4599  * @index: filter index
4600  * @cmd_details: pointer to command details structure or NULL
4601  **/
4602 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4603                                 struct i40e_asq_cmd_details *cmd_details)
4604 {
4605         struct i40e_aq_desc desc;
4606         struct i40e_aqc_remove_udp_tunnel *cmd =
4607                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4608         enum i40e_status_code status;
4609
4610         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4611
4612         cmd->index = index;
4613
4614         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4615
4616         return status;
4617 }
4618
4619 /**
4620  * i40e_aq_get_switch_resource_alloc (0x0204)
4621  * @hw: pointer to the hw struct
4622  * @num_entries: pointer to u8 to store the number of resource entries returned
4623  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4624  *        to store the resource information for all resource types.  Each
4625  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4626  * @count: size, in bytes, of the buffer provided
4627  * @cmd_details: pointer to command details structure or NULL
4628  *
4629  * Query the resources allocated to a function.
4630  **/
4631 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4632                         u8 *num_entries,
4633                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4634                         u16 count,
4635                         struct i40e_asq_cmd_details *cmd_details)
4636 {
4637         struct i40e_aq_desc desc;
4638         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4639                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4640         enum i40e_status_code status;
4641         u16 length = count * sizeof(*buf);
4642
4643         i40e_fill_default_direct_cmd_desc(&desc,
4644                                         i40e_aqc_opc_get_switch_resource_alloc);
4645
4646         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4647         if (length > I40E_AQ_LARGE_BUF)
4648                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4649
4650         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4651
4652         if (!status && num_entries)
4653                 *num_entries = cmd_resp->num_entries;
4654
4655         return status;
4656 }
4657
4658 /**
4659  * i40e_aq_delete_element - Delete switch element
4660  * @hw: pointer to the hw struct
4661  * @seid: the SEID to delete from the switch
4662  * @cmd_details: pointer to command details structure or NULL
4663  *
4664  * This deletes a switch element from the switch.
4665  **/
4666 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4667                                 struct i40e_asq_cmd_details *cmd_details)
4668 {
4669         struct i40e_aq_desc desc;
4670         struct i40e_aqc_switch_seid *cmd =
4671                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4672         enum i40e_status_code status;
4673
4674         if (seid == 0)
4675                 return I40E_ERR_PARAM;
4676
4677         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4678
4679         cmd->seid = CPU_TO_LE16(seid);
4680
4681         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4682
4683         return status;
4684 }
4685
4686 /**
4687  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4688  * @hw: pointer to the hw struct
4689  * @flags: component flags
4690  * @mac_seid: uplink seid (MAC SEID)
4691  * @vsi_seid: connected vsi seid
4692  * @ret_seid: seid of create pv component
4693  *
4694  * This instantiates an i40e port virtualizer with specified flags.
4695  * Depending on specified flags the port virtualizer can act as a
4696  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4697  */
4698 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4699                                        u16 mac_seid, u16 vsi_seid,
4700                                        u16 *ret_seid)
4701 {
4702         struct i40e_aq_desc desc;
4703         struct i40e_aqc_add_update_pv *cmd =
4704                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4705         struct i40e_aqc_add_update_pv_completion *resp =
4706                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4707         enum i40e_status_code status;
4708
4709         if (vsi_seid == 0)
4710                 return I40E_ERR_PARAM;
4711
4712         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4713         cmd->command_flags = CPU_TO_LE16(flags);
4714         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4715         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4716
4717         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4718         if (!status && ret_seid)
4719                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4720
4721         return status;
4722 }
4723
4724 /**
4725  * i40e_aq_add_tag - Add an S/E-tag
4726  * @hw: pointer to the hw struct
4727  * @direct_to_queue: should s-tag direct flow to a specific queue
4728  * @vsi_seid: VSI SEID to use this tag
4729  * @tag: value of the tag
4730  * @queue_num: queue number, only valid is direct_to_queue is true
4731  * @tags_used: return value, number of tags in use by this PF
4732  * @tags_free: return value, number of unallocated tags
4733  * @cmd_details: pointer to command details structure or NULL
4734  *
4735  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4736  * the number of tags allocated by the PF, and the number of unallocated
4737  * tags available.
4738  **/
4739 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4740                                 u16 vsi_seid, u16 tag, u16 queue_num,
4741                                 u16 *tags_used, u16 *tags_free,
4742                                 struct i40e_asq_cmd_details *cmd_details)
4743 {
4744         struct i40e_aq_desc desc;
4745         struct i40e_aqc_add_tag *cmd =
4746                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4747         struct i40e_aqc_add_remove_tag_completion *resp =
4748                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4749         enum i40e_status_code status;
4750
4751         if (vsi_seid == 0)
4752                 return I40E_ERR_PARAM;
4753
4754         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4755
4756         cmd->seid = CPU_TO_LE16(vsi_seid);
4757         cmd->tag = CPU_TO_LE16(tag);
4758         if (direct_to_queue) {
4759                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4760                 cmd->queue_number = CPU_TO_LE16(queue_num);
4761         }
4762
4763         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4764
4765         if (!status) {
4766                 if (tags_used != NULL)
4767                         *tags_used = LE16_TO_CPU(resp->tags_used);
4768                 if (tags_free != NULL)
4769                         *tags_free = LE16_TO_CPU(resp->tags_free);
4770         }
4771
4772         return status;
4773 }
4774
4775 /**
4776  * i40e_aq_remove_tag - Remove an S- or E-tag
4777  * @hw: pointer to the hw struct
4778  * @vsi_seid: VSI SEID this tag is associated with
4779  * @tag: value of the S-tag to delete
4780  * @tags_used: return value, number of tags in use by this PF
4781  * @tags_free: return value, number of unallocated tags
4782  * @cmd_details: pointer to command details structure or NULL
4783  *
4784  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4785  * the number of tags allocated by the PF, and the number of unallocated
4786  * tags available.
4787  **/
4788 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4789                                 u16 tag, u16 *tags_used, u16 *tags_free,
4790                                 struct i40e_asq_cmd_details *cmd_details)
4791 {
4792         struct i40e_aq_desc desc;
4793         struct i40e_aqc_remove_tag *cmd =
4794                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4795         struct i40e_aqc_add_remove_tag_completion *resp =
4796                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4797         enum i40e_status_code status;
4798
4799         if (vsi_seid == 0)
4800                 return I40E_ERR_PARAM;
4801
4802         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4803
4804         cmd->seid = CPU_TO_LE16(vsi_seid);
4805         cmd->tag = CPU_TO_LE16(tag);
4806
4807         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4808
4809         if (!status) {
4810                 if (tags_used != NULL)
4811                         *tags_used = LE16_TO_CPU(resp->tags_used);
4812                 if (tags_free != NULL)
4813                         *tags_free = LE16_TO_CPU(resp->tags_free);
4814         }
4815
4816         return status;
4817 }
4818
4819 /**
4820  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4821  * @hw: pointer to the hw struct
4822  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4823  * @etag: value of E-tag to add
4824  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4825  * @buf: address of indirect buffer
4826  * @tags_used: return value, number of E-tags in use by this port
4827  * @tags_free: return value, number of unallocated M-tags
4828  * @cmd_details: pointer to command details structure or NULL
4829  *
4830  * This associates a multicast E-tag to a port virtualizer.  It will return
4831  * the number of tags allocated by the PF, and the number of unallocated
4832  * tags available.
4833  *
4834  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4835  * num_tags_in_buf long.
4836  **/
4837 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4838                                 u16 etag, u8 num_tags_in_buf, void *buf,
4839                                 u16 *tags_used, u16 *tags_free,
4840                                 struct i40e_asq_cmd_details *cmd_details)
4841 {
4842         struct i40e_aq_desc desc;
4843         struct i40e_aqc_add_remove_mcast_etag *cmd =
4844                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4845         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4846            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4847         enum i40e_status_code status;
4848         u16 length = sizeof(u16) * num_tags_in_buf;
4849
4850         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4851                 return I40E_ERR_PARAM;
4852
4853         i40e_fill_default_direct_cmd_desc(&desc,
4854                                           i40e_aqc_opc_add_multicast_etag);
4855
4856         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4857         cmd->etag = CPU_TO_LE16(etag);
4858         cmd->num_unicast_etags = num_tags_in_buf;
4859
4860         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4861         if (length > I40E_AQ_LARGE_BUF)
4862                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4863
4864         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4865
4866         if (!status) {
4867                 if (tags_used != NULL)
4868                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4869                 if (tags_free != NULL)
4870                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4871         }
4872
4873         return status;
4874 }
4875
4876 /**
4877  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4878  * @hw: pointer to the hw struct
4879  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4880  * @etag: value of the E-tag to remove
4881  * @tags_used: return value, number of tags in use by this port
4882  * @tags_free: return value, number of unallocated tags
4883  * @cmd_details: pointer to command details structure or NULL
4884  *
4885  * This deletes an E-tag from the port virtualizer.  It will return
4886  * the number of tags allocated by the port, and the number of unallocated
4887  * tags available.
4888  **/
4889 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4890                                 u16 etag, u16 *tags_used, u16 *tags_free,
4891                                 struct i40e_asq_cmd_details *cmd_details)
4892 {
4893         struct i40e_aq_desc desc;
4894         struct i40e_aqc_add_remove_mcast_etag *cmd =
4895                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4896         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4897            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4898         enum i40e_status_code status;
4899
4900
4901         if (pv_seid == 0)
4902                 return I40E_ERR_PARAM;
4903
4904         i40e_fill_default_direct_cmd_desc(&desc,
4905                                           i40e_aqc_opc_remove_multicast_etag);
4906
4907         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4908         cmd->etag = CPU_TO_LE16(etag);
4909
4910         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4911
4912         if (!status) {
4913                 if (tags_used != NULL)
4914                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4915                 if (tags_free != NULL)
4916                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4917         }
4918
4919         return status;
4920 }
4921
4922 /**
4923  * i40e_aq_update_tag - Update an S/E-tag
4924  * @hw: pointer to the hw struct
4925  * @vsi_seid: VSI SEID using this S-tag
4926  * @old_tag: old tag value
4927  * @new_tag: new tag value
4928  * @tags_used: return value, number of tags in use by this PF
4929  * @tags_free: return value, number of unallocated tags
4930  * @cmd_details: pointer to command details structure or NULL
4931  *
4932  * This updates the value of the tag currently attached to this VSI
4933  * in the switch complex.  It will return the number of tags allocated
4934  * by the PF, and the number of unallocated tags available.
4935  **/
4936 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4937                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4938                                 u16 *tags_free,
4939                                 struct i40e_asq_cmd_details *cmd_details)
4940 {
4941         struct i40e_aq_desc desc;
4942         struct i40e_aqc_update_tag *cmd =
4943                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4944         struct i40e_aqc_update_tag_completion *resp =
4945                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4946         enum i40e_status_code status;
4947
4948         if (vsi_seid == 0)
4949                 return I40E_ERR_PARAM;
4950
4951         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4952
4953         cmd->seid = CPU_TO_LE16(vsi_seid);
4954         cmd->old_tag = CPU_TO_LE16(old_tag);
4955         cmd->new_tag = CPU_TO_LE16(new_tag);
4956
4957         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4958
4959         if (!status) {
4960                 if (tags_used != NULL)
4961                         *tags_used = LE16_TO_CPU(resp->tags_used);
4962                 if (tags_free != NULL)
4963                         *tags_free = LE16_TO_CPU(resp->tags_free);
4964         }
4965
4966         return status;
4967 }
4968
4969 /**
4970  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4971  * @hw: pointer to the hw struct
4972  * @tcmap: TC map for request/release any ignore PFC condition
4973  * @request: request or release ignore PFC condition
4974  * @tcmap_ret: return TCs for which PFC is currently ignored
4975  * @cmd_details: pointer to command details structure or NULL
4976  *
4977  * This sends out request/release to ignore PFC condition for a TC.
4978  * It will return the TCs for which PFC is currently ignored.
4979  **/
4980 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4981                                 bool request, u8 *tcmap_ret,
4982                                 struct i40e_asq_cmd_details *cmd_details)
4983 {
4984         struct i40e_aq_desc desc;
4985         struct i40e_aqc_pfc_ignore *cmd_resp =
4986                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4987         enum i40e_status_code status;
4988
4989         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4990
4991         if (request)
4992                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4993
4994         cmd_resp->tc_bitmap = tcmap;
4995
4996         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4997
4998         if (!status) {
4999                 if (tcmap_ret != NULL)
5000                         *tcmap_ret = cmd_resp->tc_bitmap;
5001         }
5002
5003         return status;
5004 }
5005
5006 /**
5007  * i40e_aq_dcb_updated - DCB Updated Command
5008  * @hw: pointer to the hw struct
5009  * @cmd_details: pointer to command details structure or NULL
5010  *
5011  * When LLDP is handled in PF this command is used by the PF
5012  * to notify EMP that a DCB setting is modified.
5013  * When LLDP is handled in EMP this command is used by the PF
5014  * to notify EMP whenever one of the following parameters get
5015  * modified:
5016  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5017  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5018  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5019  * EMP will return when the shared RPB settings have been
5020  * recomputed and modified. The retval field in the descriptor
5021  * will be set to 0 when RPB is modified.
5022  **/
5023 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5024                                 struct i40e_asq_cmd_details *cmd_details)
5025 {
5026         struct i40e_aq_desc desc;
5027         enum i40e_status_code status;
5028
5029         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5030
5031         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5032
5033         return status;
5034 }
5035
5036 /**
5037  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5038  * @hw: pointer to the hw struct
5039  * @seid: defines the SEID of the switch for which the stats are requested
5040  * @vlan_id: the VLAN ID for which the statistics are requested
5041  * @stat_index: index of the statistics counters block assigned to this VLAN
5042  * @cmd_details: pointer to command details structure or NULL
5043  *
5044  * XL710 supports 128 smonVlanStats counters.This command is used to
5045  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5046  * switch.
5047  **/
5048 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5049                                 u16 vlan_id, u16 *stat_index,
5050                                 struct i40e_asq_cmd_details *cmd_details)
5051 {
5052         struct i40e_aq_desc desc;
5053         struct i40e_aqc_add_remove_statistics *cmd_resp =
5054                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5055         enum i40e_status_code status;
5056
5057         if ((seid == 0) || (stat_index == NULL))
5058                 return I40E_ERR_PARAM;
5059
5060         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5061
5062         cmd_resp->seid = CPU_TO_LE16(seid);
5063         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5064
5065         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5066
5067         if (!status && stat_index)
5068                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5069
5070         return status;
5071 }
5072
5073 /**
5074  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5075  * @hw: pointer to the hw struct
5076  * @seid: defines the SEID of the switch for which the stats are requested
5077  * @vlan_id: the VLAN ID for which the statistics are requested
5078  * @stat_index: index of the statistics counters block assigned to this VLAN
5079  * @cmd_details: pointer to command details structure or NULL
5080  *
5081  * XL710 supports 128 smonVlanStats counters.This command is used to
5082  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5083  * switch.
5084  **/
5085 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5086                                 u16 vlan_id, u16 stat_index,
5087                                 struct i40e_asq_cmd_details *cmd_details)
5088 {
5089         struct i40e_aq_desc desc;
5090         struct i40e_aqc_add_remove_statistics *cmd =
5091                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5092         enum i40e_status_code status;
5093
5094         if (seid == 0)
5095                 return I40E_ERR_PARAM;
5096
5097         i40e_fill_default_direct_cmd_desc(&desc,
5098                                           i40e_aqc_opc_remove_statistics);
5099
5100         cmd->seid = CPU_TO_LE16(seid);
5101         cmd->vlan  = CPU_TO_LE16(vlan_id);
5102         cmd->stat_index = CPU_TO_LE16(stat_index);
5103
5104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5105
5106         return status;
5107 }
5108
5109 /**
5110  * i40e_aq_set_port_parameters - set physical port parameters.
5111  * @hw: pointer to the hw struct
5112  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5113  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5114  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5115  * @double_vlan: if set double VLAN is enabled
5116  * @cmd_details: pointer to command details structure or NULL
5117  **/
5118 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5119                                 u16 bad_frame_vsi, bool save_bad_pac,
5120                                 bool pad_short_pac, bool double_vlan,
5121                                 struct i40e_asq_cmd_details *cmd_details)
5122 {
5123         struct i40e_aqc_set_port_parameters *cmd;
5124         enum i40e_status_code status;
5125         struct i40e_aq_desc desc;
5126         u16 command_flags = 0;
5127
5128         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5129
5130         i40e_fill_default_direct_cmd_desc(&desc,
5131                                           i40e_aqc_opc_set_port_parameters);
5132
5133         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5134         if (save_bad_pac)
5135                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5136         if (pad_short_pac)
5137                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5138         if (double_vlan)
5139                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5140         cmd->command_flags = CPU_TO_LE16(command_flags);
5141
5142         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5143
5144         return status;
5145 }
5146
5147 /**
5148  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5149  * @hw: pointer to the hw struct
5150  * @seid: seid for the physical port/switching component/vsi
5151  * @buff: Indirect buffer to hold data parameters and response
5152  * @buff_size: Indirect buffer size
5153  * @opcode: Tx scheduler AQ command opcode
5154  * @cmd_details: pointer to command details structure or NULL
5155  *
5156  * Generic command handler for Tx scheduler AQ commands
5157  **/
5158 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5159                                 void *buff, u16 buff_size,
5160                                  enum i40e_admin_queue_opc opcode,
5161                                 struct i40e_asq_cmd_details *cmd_details)
5162 {
5163         struct i40e_aq_desc desc;
5164         struct i40e_aqc_tx_sched_ind *cmd =
5165                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5166         enum i40e_status_code status;
5167         bool cmd_param_flag = false;
5168
5169         switch (opcode) {
5170         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5171         case i40e_aqc_opc_configure_vsi_tc_bw:
5172         case i40e_aqc_opc_enable_switching_comp_ets:
5173         case i40e_aqc_opc_modify_switching_comp_ets:
5174         case i40e_aqc_opc_disable_switching_comp_ets:
5175         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5176         case i40e_aqc_opc_configure_switching_comp_bw_config:
5177                 cmd_param_flag = true;
5178                 break;
5179         case i40e_aqc_opc_query_vsi_bw_config:
5180         case i40e_aqc_opc_query_vsi_ets_sla_config:
5181         case i40e_aqc_opc_query_switching_comp_ets_config:
5182         case i40e_aqc_opc_query_port_ets_config:
5183         case i40e_aqc_opc_query_switching_comp_bw_config:
5184                 cmd_param_flag = false;
5185                 break;
5186         default:
5187                 return I40E_ERR_PARAM;
5188         }
5189
5190         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5191
5192         /* Indirect command */
5193         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5194         if (cmd_param_flag)
5195                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5196         if (buff_size > I40E_AQ_LARGE_BUF)
5197                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5198
5199         desc.datalen = CPU_TO_LE16(buff_size);
5200
5201         cmd->vsi_seid = CPU_TO_LE16(seid);
5202
5203         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5204
5205         return status;
5206 }
5207
5208 /**
5209  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5210  * @hw: pointer to the hw struct
5211  * @seid: VSI seid
5212  * @credit: BW limit credits (0 = disabled)
5213  * @max_credit: Max BW limit credits
5214  * @cmd_details: pointer to command details structure or NULL
5215  **/
5216 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5217                                 u16 seid, u16 credit, u8 max_credit,
5218                                 struct i40e_asq_cmd_details *cmd_details)
5219 {
5220         struct i40e_aq_desc desc;
5221         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5222                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5223         enum i40e_status_code status;
5224
5225         i40e_fill_default_direct_cmd_desc(&desc,
5226                                           i40e_aqc_opc_configure_vsi_bw_limit);
5227
5228         cmd->vsi_seid = CPU_TO_LE16(seid);
5229         cmd->credit = CPU_TO_LE16(credit);
5230         cmd->max_credit = max_credit;
5231
5232         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5233
5234         return status;
5235 }
5236
5237 /**
5238  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5239  * @hw: pointer to the hw struct
5240  * @seid: switching component seid
5241  * @credit: BW limit credits (0 = disabled)
5242  * @max_bw: Max BW limit credits
5243  * @cmd_details: pointer to command details structure or NULL
5244  **/
5245 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5246                                 u16 seid, u16 credit, u8 max_bw,
5247                                 struct i40e_asq_cmd_details *cmd_details)
5248 {
5249         struct i40e_aq_desc desc;
5250         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5251           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5252         enum i40e_status_code status;
5253
5254         i40e_fill_default_direct_cmd_desc(&desc,
5255                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5256
5257         cmd->seid = CPU_TO_LE16(seid);
5258         cmd->credit = CPU_TO_LE16(credit);
5259         cmd->max_bw = max_bw;
5260
5261         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5262
5263         return status;
5264 }
5265
5266 /**
5267  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5268  * @hw: pointer to the hw struct
5269  * @seid: VSI seid
5270  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5271  * @cmd_details: pointer to command details structure or NULL
5272  **/
5273 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5274                         u16 seid,
5275                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5276                         struct i40e_asq_cmd_details *cmd_details)
5277 {
5278         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5279                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5280                                     cmd_details);
5281 }
5282
5283 /**
5284  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5285  * @hw: pointer to the hw struct
5286  * @seid: VSI seid
5287  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5288  * @cmd_details: pointer to command details structure or NULL
5289  **/
5290 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5291                         u16 seid,
5292                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5293                         struct i40e_asq_cmd_details *cmd_details)
5294 {
5295         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5296                                     i40e_aqc_opc_configure_vsi_tc_bw,
5297                                     cmd_details);
5298 }
5299
5300 /**
5301  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5302  * @hw: pointer to the hw struct
5303  * @seid: seid of the switching component connected to Physical Port
5304  * @ets_data: Buffer holding ETS parameters
5305  * @opcode: Tx scheduler AQ command opcode
5306  * @cmd_details: pointer to command details structure or NULL
5307  **/
5308 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5309                 u16 seid,
5310                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5311                 enum i40e_admin_queue_opc opcode,
5312                 struct i40e_asq_cmd_details *cmd_details)
5313 {
5314         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5315                                     sizeof(*ets_data), opcode, cmd_details);
5316 }
5317
5318 /**
5319  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5320  * @hw: pointer to the hw struct
5321  * @seid: seid of the switching component
5322  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5323  * @cmd_details: pointer to command details structure or NULL
5324  **/
5325 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5326         u16 seid,
5327         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5328         struct i40e_asq_cmd_details *cmd_details)
5329 {
5330         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5331                             i40e_aqc_opc_configure_switching_comp_bw_config,
5332                             cmd_details);
5333 }
5334
5335 /**
5336  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5337  * @hw: pointer to the hw struct
5338  * @seid: seid of the switching component
5339  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5340  * @cmd_details: pointer to command details structure or NULL
5341  **/
5342 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5343         struct i40e_hw *hw, u16 seid,
5344         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5345         struct i40e_asq_cmd_details *cmd_details)
5346 {
5347         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5348                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5349                             cmd_details);
5350 }
5351
5352 /**
5353  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5354  * @hw: pointer to the hw struct
5355  * @seid: seid of the VSI
5356  * @bw_data: Buffer to hold VSI BW configuration
5357  * @cmd_details: pointer to command details structure or NULL
5358  **/
5359 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5360                         u16 seid,
5361                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5362                         struct i40e_asq_cmd_details *cmd_details)
5363 {
5364         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5365                                     i40e_aqc_opc_query_vsi_bw_config,
5366                                     cmd_details);
5367 }
5368
5369 /**
5370  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5371  * @hw: pointer to the hw struct
5372  * @seid: seid of the VSI
5373  * @bw_data: Buffer to hold VSI BW configuration per TC
5374  * @cmd_details: pointer to command details structure or NULL
5375  **/
5376 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5377                         u16 seid,
5378                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5379                         struct i40e_asq_cmd_details *cmd_details)
5380 {
5381         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5382                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5383                                     cmd_details);
5384 }
5385
5386 /**
5387  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5388  * @hw: pointer to the hw struct
5389  * @seid: seid of the switching component
5390  * @bw_data: Buffer to hold switching component's per TC BW config
5391  * @cmd_details: pointer to command details structure or NULL
5392  **/
5393 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5394                 u16 seid,
5395                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5396                 struct i40e_asq_cmd_details *cmd_details)
5397 {
5398         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5399                                    i40e_aqc_opc_query_switching_comp_ets_config,
5400                                    cmd_details);
5401 }
5402
5403 /**
5404  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5405  * @hw: pointer to the hw struct
5406  * @seid: seid of the VSI or switching component connected to Physical Port
5407  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5408  * @cmd_details: pointer to command details structure or NULL
5409  **/
5410 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5411                         u16 seid,
5412                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5413                         struct i40e_asq_cmd_details *cmd_details)
5414 {
5415         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5416                                     i40e_aqc_opc_query_port_ets_config,
5417                                     cmd_details);
5418 }
5419
5420 /**
5421  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5422  * @hw: pointer to the hw struct
5423  * @seid: seid of the switching component
5424  * @bw_data: Buffer to hold switching component's BW configuration
5425  * @cmd_details: pointer to command details structure or NULL
5426  **/
5427 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5428                 u16 seid,
5429                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5430                 struct i40e_asq_cmd_details *cmd_details)
5431 {
5432         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5433                                     i40e_aqc_opc_query_switching_comp_bw_config,
5434                                     cmd_details);
5435 }
5436
5437 /**
5438  * i40e_validate_filter_settings
5439  * @hw: pointer to the hardware structure
5440  * @settings: Filter control settings
5441  *
5442  * Check and validate the filter control settings passed.
5443  * The function checks for the valid filter/context sizes being
5444  * passed for FCoE and PE.
5445  *
5446  * Returns I40E_SUCCESS if the values passed are valid and within
5447  * range else returns an error.
5448  **/
5449 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5450                                 struct i40e_filter_control_settings *settings)
5451 {
5452         u32 fcoe_cntx_size, fcoe_filt_size;
5453         u32 pe_cntx_size, pe_filt_size;
5454         u32 fcoe_fmax;
5455
5456         u32 val;
5457
5458         /* Validate FCoE settings passed */
5459         switch (settings->fcoe_filt_num) {
5460         case I40E_HASH_FILTER_SIZE_1K:
5461         case I40E_HASH_FILTER_SIZE_2K:
5462         case I40E_HASH_FILTER_SIZE_4K:
5463         case I40E_HASH_FILTER_SIZE_8K:
5464         case I40E_HASH_FILTER_SIZE_16K:
5465         case I40E_HASH_FILTER_SIZE_32K:
5466                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5467                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5468                 break;
5469         default:
5470                 return I40E_ERR_PARAM;
5471         }
5472
5473         switch (settings->fcoe_cntx_num) {
5474         case I40E_DMA_CNTX_SIZE_512:
5475         case I40E_DMA_CNTX_SIZE_1K:
5476         case I40E_DMA_CNTX_SIZE_2K:
5477         case I40E_DMA_CNTX_SIZE_4K:
5478                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5479                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5480                 break;
5481         default:
5482                 return I40E_ERR_PARAM;
5483         }
5484
5485         /* Validate PE settings passed */
5486         switch (settings->pe_filt_num) {
5487         case I40E_HASH_FILTER_SIZE_1K:
5488         case I40E_HASH_FILTER_SIZE_2K:
5489         case I40E_HASH_FILTER_SIZE_4K:
5490         case I40E_HASH_FILTER_SIZE_8K:
5491         case I40E_HASH_FILTER_SIZE_16K:
5492         case I40E_HASH_FILTER_SIZE_32K:
5493         case I40E_HASH_FILTER_SIZE_64K:
5494         case I40E_HASH_FILTER_SIZE_128K:
5495         case I40E_HASH_FILTER_SIZE_256K:
5496         case I40E_HASH_FILTER_SIZE_512K:
5497         case I40E_HASH_FILTER_SIZE_1M:
5498                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5499                 pe_filt_size <<= (u32)settings->pe_filt_num;
5500                 break;
5501         default:
5502                 return I40E_ERR_PARAM;
5503         }
5504
5505         switch (settings->pe_cntx_num) {
5506         case I40E_DMA_CNTX_SIZE_512:
5507         case I40E_DMA_CNTX_SIZE_1K:
5508         case I40E_DMA_CNTX_SIZE_2K:
5509         case I40E_DMA_CNTX_SIZE_4K:
5510         case I40E_DMA_CNTX_SIZE_8K:
5511         case I40E_DMA_CNTX_SIZE_16K:
5512         case I40E_DMA_CNTX_SIZE_32K:
5513         case I40E_DMA_CNTX_SIZE_64K:
5514         case I40E_DMA_CNTX_SIZE_128K:
5515         case I40E_DMA_CNTX_SIZE_256K:
5516                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5517                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5518                 break;
5519         default:
5520                 return I40E_ERR_PARAM;
5521         }
5522
5523         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5524         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5525         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5526                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5527         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5528                 return I40E_ERR_INVALID_SIZE;
5529
5530         return I40E_SUCCESS;
5531 }
5532
5533 /**
5534  * i40e_set_filter_control
5535  * @hw: pointer to the hardware structure
5536  * @settings: Filter control settings
5537  *
5538  * Set the Queue Filters for PE/FCoE and enable filters required
5539  * for a single PF. It is expected that these settings are programmed
5540  * at the driver initialization time.
5541  **/
5542 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5543                                 struct i40e_filter_control_settings *settings)
5544 {
5545         enum i40e_status_code ret = I40E_SUCCESS;
5546         u32 hash_lut_size = 0;
5547         u32 val;
5548
5549         if (!settings)
5550                 return I40E_ERR_PARAM;
5551
5552         /* Validate the input settings */
5553         ret = i40e_validate_filter_settings(hw, settings);
5554         if (ret)
5555                 return ret;
5556
5557         /* Read the PF Queue Filter control register */
5558         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5559
5560         /* Program required PE hash buckets for the PF */
5561         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5562         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5563                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5564         /* Program required PE contexts for the PF */
5565         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5566         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5567                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5568
5569         /* Program required FCoE hash buckets for the PF */
5570         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5571         val |= ((u32)settings->fcoe_filt_num <<
5572                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5573                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5574         /* Program required FCoE DDP contexts for the PF */
5575         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5576         val |= ((u32)settings->fcoe_cntx_num <<
5577                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5578                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5579
5580         /* Program Hash LUT size for the PF */
5581         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5582         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5583                 hash_lut_size = 1;
5584         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5585                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5586
5587         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5588         if (settings->enable_fdir)
5589                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5590         if (settings->enable_ethtype)
5591                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5592         if (settings->enable_macvlan)
5593                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5594
5595         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5596
5597         return I40E_SUCCESS;
5598 }
5599
5600 /**
5601  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5602  * @hw: pointer to the hw struct
5603  * @mac_addr: MAC address to use in the filter
5604  * @ethtype: Ethertype to use in the filter
5605  * @flags: Flags that needs to be applied to the filter
5606  * @vsi_seid: seid of the control VSI
5607  * @queue: VSI queue number to send the packet to
5608  * @is_add: Add control packet filter if True else remove
5609  * @stats: Structure to hold information on control filter counts
5610  * @cmd_details: pointer to command details structure or NULL
5611  *
5612  * This command will Add or Remove control packet filter for a control VSI.
5613  * In return it will update the total number of perfect filter count in
5614  * the stats member.
5615  **/
5616 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5617                                 u8 *mac_addr, u16 ethtype, u16 flags,
5618                                 u16 vsi_seid, u16 queue, bool is_add,
5619                                 struct i40e_control_filter_stats *stats,
5620                                 struct i40e_asq_cmd_details *cmd_details)
5621 {
5622         struct i40e_aq_desc desc;
5623         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5624                 (struct i40e_aqc_add_remove_control_packet_filter *)
5625                 &desc.params.raw;
5626         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5627                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5628                 &desc.params.raw;
5629         enum i40e_status_code status;
5630
5631         if (vsi_seid == 0)
5632                 return I40E_ERR_PARAM;
5633
5634         if (is_add) {
5635                 i40e_fill_default_direct_cmd_desc(&desc,
5636                                 i40e_aqc_opc_add_control_packet_filter);
5637                 cmd->queue = CPU_TO_LE16(queue);
5638         } else {
5639                 i40e_fill_default_direct_cmd_desc(&desc,
5640                                 i40e_aqc_opc_remove_control_packet_filter);
5641         }
5642
5643         if (mac_addr)
5644                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5645                             I40E_NONDMA_TO_NONDMA);
5646
5647         cmd->etype = CPU_TO_LE16(ethtype);
5648         cmd->flags = CPU_TO_LE16(flags);
5649         cmd->seid = CPU_TO_LE16(vsi_seid);
5650
5651         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5652
5653         if (!status && stats) {
5654                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5655                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5656                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5657                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5658         }
5659
5660         return status;
5661 }
5662
5663 /**
5664  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5665  * @hw: pointer to the hw struct
5666  * @seid: VSI seid to add ethertype filter from
5667  **/
5668 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5669                                                     u16 seid)
5670 {
5671 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5672         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5673                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5674                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5675         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5676         enum i40e_status_code status;
5677
5678         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5679                                                        seid, 0, true, NULL,
5680                                                        NULL);
5681         if (status)
5682                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5683 }
5684
5685 /**
5686  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5687  * @filters: list of cloud filters
5688  * @filter_count: length of list
5689  *
5690  * There's an issue in the device where the Geneve VNI layout needs
5691  * to be shifted 1 byte over from the VxLAN VNI
5692  **/
5693 STATIC void i40e_fix_up_geneve_vni(
5694         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5695         u8 filter_count)
5696 {
5697         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5698         int i;
5699
5700         for (i = 0; i < filter_count; i++) {
5701                 u16 tnl_type;
5702                 u32 ti;
5703
5704                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5705                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5706                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5707                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5708                         ti = LE32_TO_CPU(f[i].tenant_id);
5709                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5710                 }
5711         }
5712 }
5713
5714 /**
5715  * i40e_aq_add_cloud_filters
5716  * @hw: pointer to the hardware structure
5717  * @seid: VSI seid to add cloud filters from
5718  * @filters: Buffer which contains the filters to be added
5719  * @filter_count: number of filters contained in the buffer
5720  *
5721  * Set the cloud filters for a given VSI.  The contents of the
5722  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5723  * in by the caller of the function.
5724  *
5725  **/
5726 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5727         u16 seid,
5728         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5729         u8 filter_count)
5730 {
5731         struct i40e_aq_desc desc;
5732         struct i40e_aqc_add_remove_cloud_filters *cmd =
5733         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5734         enum i40e_status_code status;
5735         u16 buff_len;
5736
5737         i40e_fill_default_direct_cmd_desc(&desc,
5738                                           i40e_aqc_opc_add_cloud_filters);
5739
5740         buff_len = filter_count * sizeof(*filters);
5741         desc.datalen = CPU_TO_LE16(buff_len);
5742         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5743         cmd->num_filters = filter_count;
5744         cmd->seid = CPU_TO_LE16(seid);
5745
5746         i40e_fix_up_geneve_vni(filters, filter_count);
5747
5748         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5749
5750         return status;
5751 }
5752
5753 /**
5754  * i40e_aq_add_cloud_filters_big_buffer
5755  * @hw: pointer to the hardware structure
5756  * @seid: VSI seid to add cloud filters from
5757  * @filters: Buffer which contains the filters in big buffer to be added
5758  * @filter_count: number of filters contained in the buffer
5759  *
5760  * Set the cloud filters for a given VSI.  The contents of the
5761  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5762  * the function.
5763  *
5764  **/
5765 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5766         u16 seid,
5767         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5768         u8 filter_count)
5769 {
5770         struct i40e_aq_desc desc;
5771         struct i40e_aqc_add_remove_cloud_filters *cmd =
5772         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5773         enum i40e_status_code status;
5774         u16 buff_len;
5775         int i;
5776
5777         i40e_fill_default_direct_cmd_desc(&desc,
5778                                           i40e_aqc_opc_add_cloud_filters);
5779
5780         buff_len = filter_count * sizeof(*filters);
5781         desc.datalen = CPU_TO_LE16(buff_len);
5782         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5783         cmd->num_filters = filter_count;
5784         cmd->seid = CPU_TO_LE16(seid);
5785         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5786
5787         /* adjust Geneve VNI for HW issue */
5788         for (i = 0; i < filter_count; i++) {
5789                 u16 tnl_type;
5790                 u32 ti;
5791
5792                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5793                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5794                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5795                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5796                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5797                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5798                 }
5799         }
5800
5801         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5802
5803         return status;
5804 }
5805
5806 /**
5807  * i40e_aq_remove_cloud_filters
5808  * @hw: pointer to the hardware structure
5809  * @seid: VSI seid to remove cloud filters from
5810  * @filters: Buffer which contains the filters to be removed
5811  * @filter_count: number of filters contained in the buffer
5812  *
5813  * Remove the cloud filters for a given VSI.  The contents of the
5814  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5815  * in by the caller of the function.
5816  *
5817  **/
5818 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5819         u16 seid,
5820         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5821         u8 filter_count)
5822 {
5823         struct i40e_aq_desc desc;
5824         struct i40e_aqc_add_remove_cloud_filters *cmd =
5825         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5826         enum i40e_status_code status;
5827         u16 buff_len;
5828
5829         i40e_fill_default_direct_cmd_desc(&desc,
5830                                           i40e_aqc_opc_remove_cloud_filters);
5831
5832         buff_len = filter_count * sizeof(*filters);
5833         desc.datalen = CPU_TO_LE16(buff_len);
5834         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5835         cmd->num_filters = filter_count;
5836         cmd->seid = CPU_TO_LE16(seid);
5837
5838         i40e_fix_up_geneve_vni(filters, filter_count);
5839
5840         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5841
5842         return status;
5843 }
5844
5845 /**
5846  * i40e_aq_remove_cloud_filters_big_buffer
5847  * @hw: pointer to the hardware structure
5848  * @seid: VSI seid to remove cloud filters from
5849  * @filters: Buffer which contains the filters in big buffer to be removed
5850  * @filter_count: number of filters contained in the buffer
5851  *
5852  * Remove the cloud filters for a given VSI.  The contents of the
5853  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5854  * the function.
5855  *
5856  **/
5857 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5858         struct i40e_hw *hw,
5859         u16 seid,
5860         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5861         u8 filter_count)
5862 {
5863         struct i40e_aq_desc desc;
5864         struct i40e_aqc_add_remove_cloud_filters *cmd =
5865         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5866         enum i40e_status_code status;
5867         u16 buff_len;
5868         int i;
5869
5870         i40e_fill_default_direct_cmd_desc(&desc,
5871                                           i40e_aqc_opc_remove_cloud_filters);
5872
5873         buff_len = filter_count * sizeof(*filters);
5874         desc.datalen = CPU_TO_LE16(buff_len);
5875         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5876         cmd->num_filters = filter_count;
5877         cmd->seid = CPU_TO_LE16(seid);
5878         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5879
5880         /* adjust Geneve VNI for HW issue */
5881         for (i = 0; i < filter_count; i++) {
5882                 u16 tnl_type;
5883                 u32 ti;
5884
5885                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5886                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5887                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5888                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5889                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5890                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5891                 }
5892         }
5893
5894         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5895
5896         return status;
5897 }
5898
5899 /**
5900  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5901  * @hw: pointer to the hw struct
5902  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5903  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5904  *
5905  **/
5906 enum
5907 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5908         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5909         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5910 {
5911         struct i40e_aq_desc desc;
5912         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5913                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5914         enum i40e_status_code status = I40E_SUCCESS;
5915         int i = 0;
5916
5917         i40e_fill_default_direct_cmd_desc(&desc,
5918                                           i40e_aqc_opc_replace_cloud_filters);
5919
5920         desc.datalen = CPU_TO_LE16(32);
5921         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5922         cmd->old_filter_type = filters->old_filter_type;
5923         cmd->new_filter_type = filters->new_filter_type;
5924         cmd->valid_flags = filters->valid_flags;
5925         cmd->tr_bit = filters->tr_bit;
5926
5927         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5928                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5929
5930         /* for get cloud filters command */
5931         for (i = 0; i < 32; i += 4) {
5932                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5933                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5934                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5935                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5936         }
5937
5938         return status;
5939 }
5940
5941
5942 /**
5943  * i40e_aq_alternate_write
5944  * @hw: pointer to the hardware structure
5945  * @reg_addr0: address of first dword to be read
5946  * @reg_val0: value to be written under 'reg_addr0'
5947  * @reg_addr1: address of second dword to be read
5948  * @reg_val1: value to be written under 'reg_addr1'
5949  *
5950  * Write one or two dwords to alternate structure. Fields are indicated
5951  * by 'reg_addr0' and 'reg_addr1' register numbers.
5952  *
5953  **/
5954 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5955                                 u32 reg_addr0, u32 reg_val0,
5956                                 u32 reg_addr1, u32 reg_val1)
5957 {
5958         struct i40e_aq_desc desc;
5959         struct i40e_aqc_alternate_write *cmd_resp =
5960                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5961         enum i40e_status_code status;
5962
5963         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5964         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5965         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5966         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5967         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5968
5969         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5970
5971         return status;
5972 }
5973
5974 /**
5975  * i40e_aq_alternate_write_indirect
5976  * @hw: pointer to the hardware structure
5977  * @addr: address of a first register to be modified
5978  * @dw_count: number of alternate structure fields to write
5979  * @buffer: pointer to the command buffer
5980  *
5981  * Write 'dw_count' dwords from 'buffer' to alternate structure
5982  * starting at 'addr'.
5983  *
5984  **/
5985 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5986                                 u32 addr, u32 dw_count, void *buffer)
5987 {
5988         struct i40e_aq_desc desc;
5989         struct i40e_aqc_alternate_ind_write *cmd_resp =
5990                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5991         enum i40e_status_code status;
5992
5993         if (buffer == NULL)
5994                 return I40E_ERR_PARAM;
5995
5996         /* Indirect command */
5997         i40e_fill_default_direct_cmd_desc(&desc,
5998                                          i40e_aqc_opc_alternate_write_indirect);
5999
6000         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6001         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6002         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6003                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6004
6005         cmd_resp->address = CPU_TO_LE32(addr);
6006         cmd_resp->length = CPU_TO_LE32(dw_count);
6007
6008         status = i40e_asq_send_command(hw, &desc, buffer,
6009                                        I40E_LO_DWORD(4*dw_count), NULL);
6010
6011         return status;
6012 }
6013
6014 /**
6015  * i40e_aq_alternate_read
6016  * @hw: pointer to the hardware structure
6017  * @reg_addr0: address of first dword to be read
6018  * @reg_val0: pointer for data read from 'reg_addr0'
6019  * @reg_addr1: address of second dword to be read
6020  * @reg_val1: pointer for data read from 'reg_addr1'
6021  *
6022  * Read one or two dwords from alternate structure. Fields are indicated
6023  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6024  * is not passed then only register at 'reg_addr0' is read.
6025  *
6026  **/
6027 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6028                                 u32 reg_addr0, u32 *reg_val0,
6029                                 u32 reg_addr1, u32 *reg_val1)
6030 {
6031         struct i40e_aq_desc desc;
6032         struct i40e_aqc_alternate_write *cmd_resp =
6033                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6034         enum i40e_status_code status;
6035
6036         if (reg_val0 == NULL)
6037                 return I40E_ERR_PARAM;
6038
6039         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6040         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6041         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6042
6043         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6044
6045         if (status == I40E_SUCCESS) {
6046                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6047
6048                 if (reg_val1 != NULL)
6049                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6050         }
6051
6052         return status;
6053 }
6054
6055 /**
6056  * i40e_aq_alternate_read_indirect
6057  * @hw: pointer to the hardware structure
6058  * @addr: address of the alternate structure field
6059  * @dw_count: number of alternate structure fields to read
6060  * @buffer: pointer to the command buffer
6061  *
6062  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6063  * place them in 'buffer'. The buffer should be allocated by caller.
6064  *
6065  **/
6066 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6067                                 u32 addr, u32 dw_count, void *buffer)
6068 {
6069         struct i40e_aq_desc desc;
6070         struct i40e_aqc_alternate_ind_write *cmd_resp =
6071                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6072         enum i40e_status_code status;
6073
6074         if (buffer == NULL)
6075                 return I40E_ERR_PARAM;
6076
6077         /* Indirect command */
6078         i40e_fill_default_direct_cmd_desc(&desc,
6079                 i40e_aqc_opc_alternate_read_indirect);
6080
6081         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6082         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6083         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6084                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6085
6086         cmd_resp->address = CPU_TO_LE32(addr);
6087         cmd_resp->length = CPU_TO_LE32(dw_count);
6088
6089         status = i40e_asq_send_command(hw, &desc, buffer,
6090                                        I40E_LO_DWORD(4*dw_count), NULL);
6091
6092         return status;
6093 }
6094
6095 /**
6096  *  i40e_aq_alternate_clear
6097  *  @hw: pointer to the HW structure.
6098  *
6099  *  Clear the alternate structures of the port from which the function
6100  *  is called.
6101  *
6102  **/
6103 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6104 {
6105         struct i40e_aq_desc desc;
6106         enum i40e_status_code status;
6107
6108         i40e_fill_default_direct_cmd_desc(&desc,
6109                                           i40e_aqc_opc_alternate_clear_port);
6110
6111         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6112
6113         return status;
6114 }
6115
6116 /**
6117  *  i40e_aq_alternate_write_done
6118  *  @hw: pointer to the HW structure.
6119  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6120  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6121  *
6122  *  Indicates to the FW that alternate structures have been changed.
6123  *
6124  **/
6125 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6126                 u8 bios_mode, bool *reset_needed)
6127 {
6128         struct i40e_aq_desc desc;
6129         struct i40e_aqc_alternate_write_done *cmd =
6130                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6131         enum i40e_status_code status;
6132
6133         if (reset_needed == NULL)
6134                 return I40E_ERR_PARAM;
6135
6136         i40e_fill_default_direct_cmd_desc(&desc,
6137                                           i40e_aqc_opc_alternate_write_done);
6138
6139         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6140
6141         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6142         if (!status && reset_needed)
6143                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6144                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6145
6146         return status;
6147 }
6148
6149 /**
6150  *  i40e_aq_set_oem_mode
6151  *  @hw: pointer to the HW structure.
6152  *  @oem_mode: the OEM mode to be used
6153  *
6154  *  Sets the device to a specific operating mode. Currently the only supported
6155  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6156  *
6157  **/
6158 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6159                 u8 oem_mode)
6160 {
6161         struct i40e_aq_desc desc;
6162         struct i40e_aqc_alternate_write_done *cmd =
6163                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6164         enum i40e_status_code status;
6165
6166         i40e_fill_default_direct_cmd_desc(&desc,
6167                                           i40e_aqc_opc_alternate_set_mode);
6168
6169         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6170
6171         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6172
6173         return status;
6174 }
6175
6176 /**
6177  * i40e_aq_resume_port_tx
6178  * @hw: pointer to the hardware structure
6179  * @cmd_details: pointer to command details structure or NULL
6180  *
6181  * Resume port's Tx traffic
6182  **/
6183 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6184                                 struct i40e_asq_cmd_details *cmd_details)
6185 {
6186         struct i40e_aq_desc desc;
6187         enum i40e_status_code status;
6188
6189         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6190
6191         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6192
6193         return status;
6194 }
6195
6196 /**
6197  * i40e_set_pci_config_data - store PCI bus info
6198  * @hw: pointer to hardware structure
6199  * @link_status: the link status word from PCI config space
6200  *
6201  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6202  **/
6203 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6204 {
6205         hw->bus.type = i40e_bus_type_pci_express;
6206
6207         switch (link_status & I40E_PCI_LINK_WIDTH) {
6208         case I40E_PCI_LINK_WIDTH_1:
6209                 hw->bus.width = i40e_bus_width_pcie_x1;
6210                 break;
6211         case I40E_PCI_LINK_WIDTH_2:
6212                 hw->bus.width = i40e_bus_width_pcie_x2;
6213                 break;
6214         case I40E_PCI_LINK_WIDTH_4:
6215                 hw->bus.width = i40e_bus_width_pcie_x4;
6216                 break;
6217         case I40E_PCI_LINK_WIDTH_8:
6218                 hw->bus.width = i40e_bus_width_pcie_x8;
6219                 break;
6220         default:
6221                 hw->bus.width = i40e_bus_width_unknown;
6222                 break;
6223         }
6224
6225         switch (link_status & I40E_PCI_LINK_SPEED) {
6226         case I40E_PCI_LINK_SPEED_2500:
6227                 hw->bus.speed = i40e_bus_speed_2500;
6228                 break;
6229         case I40E_PCI_LINK_SPEED_5000:
6230                 hw->bus.speed = i40e_bus_speed_5000;
6231                 break;
6232         case I40E_PCI_LINK_SPEED_8000:
6233                 hw->bus.speed = i40e_bus_speed_8000;
6234                 break;
6235         default:
6236                 hw->bus.speed = i40e_bus_speed_unknown;
6237                 break;
6238         }
6239 }
6240
6241 /**
6242  * i40e_aq_debug_dump
6243  * @hw: pointer to the hardware structure
6244  * @cluster_id: specific cluster to dump
6245  * @table_id: table id within cluster
6246  * @start_index: index of line in the block to read
6247  * @buff_size: dump buffer size
6248  * @buff: dump buffer
6249  * @ret_buff_size: actual buffer size returned
6250  * @ret_next_table: next block to read
6251  * @ret_next_index: next index to read
6252  * @cmd_details: pointer to command details structure or NULL
6253  *
6254  * Dump internal FW/HW data for debug purposes.
6255  *
6256  **/
6257 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6258                                 u8 table_id, u32 start_index, u16 buff_size,
6259                                 void *buff, u16 *ret_buff_size,
6260                                 u8 *ret_next_table, u32 *ret_next_index,
6261                                 struct i40e_asq_cmd_details *cmd_details)
6262 {
6263         struct i40e_aq_desc desc;
6264         struct i40e_aqc_debug_dump_internals *cmd =
6265                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6266         struct i40e_aqc_debug_dump_internals *resp =
6267                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6268         enum i40e_status_code status;
6269
6270         if (buff_size == 0 || !buff)
6271                 return I40E_ERR_PARAM;
6272
6273         i40e_fill_default_direct_cmd_desc(&desc,
6274                                           i40e_aqc_opc_debug_dump_internals);
6275         /* Indirect Command */
6276         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6277         if (buff_size > I40E_AQ_LARGE_BUF)
6278                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6279
6280         cmd->cluster_id = cluster_id;
6281         cmd->table_id = table_id;
6282         cmd->idx = CPU_TO_LE32(start_index);
6283
6284         desc.datalen = CPU_TO_LE16(buff_size);
6285
6286         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6287         if (!status) {
6288                 if (ret_buff_size != NULL)
6289                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6290                 if (ret_next_table != NULL)
6291                         *ret_next_table = resp->table_id;
6292                 if (ret_next_index != NULL)
6293                         *ret_next_index = LE32_TO_CPU(resp->idx);
6294         }
6295
6296         return status;
6297 }
6298
6299 /**
6300  * i40e_read_bw_from_alt_ram
6301  * @hw: pointer to the hardware structure
6302  * @max_bw: pointer for max_bw read
6303  * @min_bw: pointer for min_bw read
6304  * @min_valid: pointer for bool that is true if min_bw is a valid value
6305  * @max_valid: pointer for bool that is true if max_bw is a valid value
6306  *
6307  * Read bw from the alternate ram for the given pf
6308  **/
6309 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6310                                         u32 *max_bw, u32 *min_bw,
6311                                         bool *min_valid, bool *max_valid)
6312 {
6313         enum i40e_status_code status;
6314         u32 max_bw_addr, min_bw_addr;
6315
6316         /* Calculate the address of the min/max bw registers */
6317         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6318                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6319                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6320         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6321                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6322                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6323
6324         /* Read the bandwidths from alt ram */
6325         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6326                                         min_bw_addr, min_bw);
6327
6328         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6329                 *min_valid = true;
6330         else
6331                 *min_valid = false;
6332
6333         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6334                 *max_valid = true;
6335         else
6336                 *max_valid = false;
6337
6338         return status;
6339 }
6340
6341 /**
6342  * i40e_aq_configure_partition_bw
6343  * @hw: pointer to the hardware structure
6344  * @bw_data: Buffer holding valid pfs and bw limits
6345  * @cmd_details: pointer to command details
6346  *
6347  * Configure partitions guaranteed/max bw
6348  **/
6349 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6350                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6351                         struct i40e_asq_cmd_details *cmd_details)
6352 {
6353         enum i40e_status_code status;
6354         struct i40e_aq_desc desc;
6355         u16 bwd_size = sizeof(*bw_data);
6356
6357         i40e_fill_default_direct_cmd_desc(&desc,
6358                                 i40e_aqc_opc_configure_partition_bw);
6359
6360         /* Indirect command */
6361         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6362         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6363
6364         desc.datalen = CPU_TO_LE16(bwd_size);
6365
6366         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6367
6368         return status;
6369 }
6370
6371 /**
6372  * i40e_read_phy_register_clause22
6373  * @hw: pointer to the HW structure
6374  * @reg: register address in the page
6375  * @phy_addr: PHY address on MDIO interface
6376  * @value: PHY register value
6377  *
6378  * Reads specified PHY register value
6379  **/
6380 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6381                                         u16 reg, u8 phy_addr, u16 *value)
6382 {
6383         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6384         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6385         u32 command = 0;
6386         u16 retry = 1000;
6387
6388         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6389                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6390                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6391                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6392                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6393         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6394         do {
6395                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6396                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6397                         status = I40E_SUCCESS;
6398                         break;
6399                 }
6400                 i40e_usec_delay(10);
6401                 retry--;
6402         } while (retry);
6403
6404         if (status) {
6405                 i40e_debug(hw, I40E_DEBUG_PHY,
6406                            "PHY: Can't write command to external PHY.\n");
6407         } else {
6408                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6409                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6410                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6411         }
6412
6413         return status;
6414 }
6415
6416 /**
6417  * i40e_write_phy_register_clause22
6418  * @hw: pointer to the HW structure
6419  * @reg: register address in the page
6420  * @phy_addr: PHY address on MDIO interface
6421  * @value: PHY register value
6422  *
6423  * Writes specified PHY register value
6424  **/
6425 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6426                                         u16 reg, u8 phy_addr, u16 value)
6427 {
6428         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6429         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6430         u32 command  = 0;
6431         u16 retry = 1000;
6432
6433         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6434         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6435
6436         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6437                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6438                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6439                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6440                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6441
6442         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6443         do {
6444                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6445                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6446                         status = I40E_SUCCESS;
6447                         break;
6448                 }
6449                 i40e_usec_delay(10);
6450                 retry--;
6451         } while (retry);
6452
6453         return status;
6454 }
6455
6456 /**
6457  * i40e_read_phy_register_clause45
6458  * @hw: pointer to the HW structure
6459  * @page: registers page number
6460  * @reg: register address in the page
6461  * @phy_addr: PHY address on MDIO interface
6462  * @value: PHY register value
6463  *
6464  * Reads specified PHY register value
6465  **/
6466 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6467                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6468 {
6469         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6470         u32 command  = 0;
6471         u16 retry = 1000;
6472         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6473
6474         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6475                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6476                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6477                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6478                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6479                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6480                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6481         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6482         do {
6483                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6484                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6485                         status = I40E_SUCCESS;
6486                         break;
6487                 }
6488                 i40e_usec_delay(10);
6489                 retry--;
6490         } while (retry);
6491
6492         if (status) {
6493                 i40e_debug(hw, I40E_DEBUG_PHY,
6494                            "PHY: Can't write command to external PHY.\n");
6495                 goto phy_read_end;
6496         }
6497
6498         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6499                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6500                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6501                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6502                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6503                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6504         status = I40E_ERR_TIMEOUT;
6505         retry = 1000;
6506         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6507         do {
6508                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6509                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6510                         status = I40E_SUCCESS;
6511                         break;
6512                 }
6513                 i40e_usec_delay(10);
6514                 retry--;
6515         } while (retry);
6516
6517         if (!status) {
6518                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6519                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6520                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6521         } else {
6522                 i40e_debug(hw, I40E_DEBUG_PHY,
6523                            "PHY: Can't read register value from external PHY.\n");
6524         }
6525
6526 phy_read_end:
6527         return status;
6528 }
6529
6530 /**
6531  * i40e_write_phy_register_clause45
6532  * @hw: pointer to the HW structure
6533  * @page: registers page number
6534  * @reg: register address in the page
6535  * @phy_addr: PHY address on MDIO interface
6536  * @value: PHY register value
6537  *
6538  * Writes value to specified PHY register
6539  **/
6540 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6541                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6542 {
6543         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6544         u32 command  = 0;
6545         u16 retry = 1000;
6546         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6547
6548         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6549                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6550                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6551                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6552                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6553                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6554                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6555         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6556         do {
6557                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6558                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6559                         status = I40E_SUCCESS;
6560                         break;
6561                 }
6562                 i40e_usec_delay(10);
6563                 retry--;
6564         } while (retry);
6565         if (status) {
6566                 i40e_debug(hw, I40E_DEBUG_PHY,
6567                            "PHY: Can't write command to external PHY.\n");
6568                 goto phy_write_end;
6569         }
6570
6571         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6572         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6573
6574         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6575                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6576                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6577                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6578                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6579                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6580         status = I40E_ERR_TIMEOUT;
6581         retry = 1000;
6582         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6583         do {
6584                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6585                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6586                         status = I40E_SUCCESS;
6587                         break;
6588                 }
6589                 i40e_usec_delay(10);
6590                 retry--;
6591         } while (retry);
6592
6593 phy_write_end:
6594         return status;
6595 }
6596
6597 /**
6598  * i40e_write_phy_register
6599  * @hw: pointer to the HW structure
6600  * @page: registers page number
6601  * @reg: register address in the page
6602  * @phy_addr: PHY address on MDIO interface
6603  * @value: PHY register value
6604  *
6605  * Writes value to specified PHY register
6606  **/
6607 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6608                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6609 {
6610         enum i40e_status_code status;
6611
6612         switch (hw->device_id) {
6613         case I40E_DEV_ID_1G_BASE_T_X722:
6614                 status = i40e_write_phy_register_clause22(hw,
6615                         reg, phy_addr, value);
6616                 break;
6617         case I40E_DEV_ID_10G_BASE_T:
6618         case I40E_DEV_ID_10G_BASE_T4:
6619         case I40E_DEV_ID_10G_BASE_T_X722:
6620         case I40E_DEV_ID_25G_B:
6621         case I40E_DEV_ID_25G_SFP28:
6622                 status = i40e_write_phy_register_clause45(hw,
6623                         page, reg, phy_addr, value);
6624                 break;
6625         default:
6626                 status = I40E_ERR_UNKNOWN_PHY;
6627                 break;
6628         }
6629
6630         return status;
6631 }
6632
6633 /**
6634  * i40e_read_phy_register
6635  * @hw: pointer to the HW structure
6636  * @page: registers page number
6637  * @reg: register address in the page
6638  * @phy_addr: PHY address on MDIO interface
6639  * @value: PHY register value
6640  *
6641  * Reads specified PHY register value
6642  **/
6643 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6644                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6645 {
6646         enum i40e_status_code status;
6647
6648         switch (hw->device_id) {
6649         case I40E_DEV_ID_1G_BASE_T_X722:
6650                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6651                                                          value);
6652                 break;
6653         case I40E_DEV_ID_10G_BASE_T:
6654         case I40E_DEV_ID_10G_BASE_T4:
6655         case I40E_DEV_ID_10G_BASE_T_X722:
6656         case I40E_DEV_ID_25G_B:
6657         case I40E_DEV_ID_25G_SFP28:
6658                 status = i40e_read_phy_register_clause45(hw, page, reg,
6659                                                          phy_addr, value);
6660                 break;
6661         default:
6662                 status = I40E_ERR_UNKNOWN_PHY;
6663                 break;
6664         }
6665
6666         return status;
6667 }
6668
6669 /**
6670  * i40e_get_phy_address
6671  * @hw: pointer to the HW structure
6672  * @dev_num: PHY port num that address we want
6673  *
6674  * Gets PHY address for current port
6675  **/
6676 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6677 {
6678         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6679         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6680
6681         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6682 }
6683
6684 /**
6685  * i40e_blink_phy_led
6686  * @hw: pointer to the HW structure
6687  * @time: time how long led will blinks in secs
6688  * @interval: gap between LED on and off in msecs
6689  *
6690  * Blinks PHY link LED
6691  **/
6692 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6693                                               u32 time, u32 interval)
6694 {
6695         enum i40e_status_code status = I40E_SUCCESS;
6696         u32 i;
6697         u16 led_ctl = 0;
6698         u16 gpio_led_port;
6699         u16 led_reg;
6700         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6701         u8 phy_addr = 0;
6702         u8 port_num;
6703
6704         i = rd32(hw, I40E_PFGEN_PORTNUM);
6705         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6706         phy_addr = i40e_get_phy_address(hw, port_num);
6707
6708         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6709              led_addr++) {
6710                 status = i40e_read_phy_register_clause45(hw,
6711                                                          I40E_PHY_COM_REG_PAGE,
6712                                                          led_addr, phy_addr,
6713                                                          &led_reg);
6714                 if (status)
6715                         goto phy_blinking_end;
6716                 led_ctl = led_reg;
6717                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6718                         led_reg = 0;
6719                         status = i40e_write_phy_register_clause45(hw,
6720                                                          I40E_PHY_COM_REG_PAGE,
6721                                                          led_addr, phy_addr,
6722                                                          led_reg);
6723                         if (status)
6724                                 goto phy_blinking_end;
6725                         break;
6726                 }
6727         }
6728
6729         if (time > 0 && interval > 0) {
6730                 for (i = 0; i < time * 1000; i += interval) {
6731                         status = i40e_read_phy_register_clause45(hw,
6732                                                 I40E_PHY_COM_REG_PAGE,
6733                                                 led_addr, phy_addr, &led_reg);
6734                         if (status)
6735                                 goto restore_config;
6736                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6737                                 led_reg = 0;
6738                         else
6739                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6740                         status = i40e_write_phy_register_clause45(hw,
6741                                                 I40E_PHY_COM_REG_PAGE,
6742                                                 led_addr, phy_addr, led_reg);
6743                         if (status)
6744                                 goto restore_config;
6745                         i40e_msec_delay(interval);
6746                 }
6747         }
6748
6749 restore_config:
6750         status = i40e_write_phy_register_clause45(hw,
6751                                                   I40E_PHY_COM_REG_PAGE,
6752                                                   led_addr, phy_addr, led_ctl);
6753
6754 phy_blinking_end:
6755         return status;
6756 }
6757
6758 /**
6759  * i40e_led_get_reg - read LED register
6760  * @hw: pointer to the HW structure
6761  * @led_addr: LED register address
6762  * @reg_val: read register value
6763  **/
6764 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6765                                               u32 *reg_val)
6766 {
6767         enum i40e_status_code status;
6768         u8 phy_addr = 0;
6769
6770         *reg_val = 0;
6771         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6772                 status = i40e_aq_get_phy_register(hw,
6773                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6774                                                 I40E_PHY_COM_REG_PAGE,
6775                                                 I40E_PHY_LED_PROV_REG_1,
6776                                                 reg_val, NULL);
6777         } else {
6778                 phy_addr = i40e_get_phy_address(hw, hw->port);
6779                 status = i40e_read_phy_register_clause45(hw,
6780                                                          I40E_PHY_COM_REG_PAGE,
6781                                                          led_addr, phy_addr,
6782                                                          (u16 *)reg_val);
6783         }
6784         return status;
6785 }
6786
6787 /**
6788  * i40e_led_set_reg - write LED register
6789  * @hw: pointer to the HW structure
6790  * @led_addr: LED register address
6791  * @reg_val: register value to write
6792  **/
6793 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6794                                               u32 reg_val)
6795 {
6796         enum i40e_status_code status;
6797         u8 phy_addr = 0;
6798
6799         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6800                 status = i40e_aq_set_phy_register(hw,
6801                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6802                                                 I40E_PHY_COM_REG_PAGE,
6803                                                 I40E_PHY_LED_PROV_REG_1,
6804                                                 reg_val, NULL);
6805         } else {
6806                 phy_addr = i40e_get_phy_address(hw, hw->port);
6807                 status = i40e_write_phy_register_clause45(hw,
6808                                                           I40E_PHY_COM_REG_PAGE,
6809                                                           led_addr, phy_addr,
6810                                                           (u16)reg_val);
6811         }
6812
6813         return status;
6814 }
6815
6816 /**
6817  * i40e_led_get_phy - return current on/off mode
6818  * @hw: pointer to the hw struct
6819  * @led_addr: address of led register to use
6820  * @val: original value of register to use
6821  *
6822  **/
6823 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6824                                        u16 *val)
6825 {
6826         enum i40e_status_code status = I40E_SUCCESS;
6827         u16 gpio_led_port;
6828         u32 reg_val_aq;
6829         u16 temp_addr;
6830         u8 phy_addr = 0;
6831         u16 reg_val;
6832
6833         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6834                 status = i40e_aq_get_phy_register(hw,
6835                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6836                                                 I40E_PHY_COM_REG_PAGE,
6837                                                 I40E_PHY_LED_PROV_REG_1,
6838                                                 &reg_val_aq, NULL);
6839                 if (status == I40E_SUCCESS)
6840                         *val = (u16)reg_val_aq;
6841                 return status;
6842         }
6843         temp_addr = I40E_PHY_LED_PROV_REG_1;
6844         phy_addr = i40e_get_phy_address(hw, hw->port);
6845         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6846              temp_addr++) {
6847                 status = i40e_read_phy_register_clause45(hw,
6848                                                          I40E_PHY_COM_REG_PAGE,
6849                                                          temp_addr, phy_addr,
6850                                                          &reg_val);
6851                 if (status)
6852                         return status;
6853                 *val = reg_val;
6854                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6855                         *led_addr = temp_addr;
6856                         break;
6857                 }
6858         }
6859         return status;
6860 }
6861
6862 /**
6863  * i40e_led_set_phy
6864  * @hw: pointer to the HW structure
6865  * @on: true or false
6866  * @led_addr: address of led register to use
6867  * @mode: original val plus bit for set or ignore
6868  *
6869  * Set led's on or off when controlled by the PHY
6870  *
6871  **/
6872 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6873                                        u16 led_addr, u32 mode)
6874 {
6875         enum i40e_status_code status = I40E_SUCCESS;
6876         u32 led_ctl = 0;
6877         u32 led_reg = 0;
6878
6879         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6880         if (status)
6881                 return status;
6882         led_ctl = led_reg;
6883         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6884                 led_reg = 0;
6885                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6886                 if (status)
6887                         return status;
6888         }
6889         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6890         if (status)
6891                 goto restore_config;
6892         if (on)
6893                 led_reg = I40E_PHY_LED_MANUAL_ON;
6894         else
6895                 led_reg = 0;
6896         status = i40e_led_set_reg(hw, led_addr, led_reg);
6897         if (status)
6898                 goto restore_config;
6899         if (mode & I40E_PHY_LED_MODE_ORIG) {
6900                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6901                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6902         }
6903         return status;
6904
6905 restore_config:
6906         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6907         return status;
6908 }
6909 #endif /* PF_DRIVER */
6910
6911 /**
6912  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6913  * @hw: pointer to the hw struct
6914  * @reg_addr: register address
6915  * @reg_val: ptr to register value
6916  * @cmd_details: pointer to command details structure or NULL
6917  *
6918  * Use the firmware to read the Rx control register,
6919  * especially useful if the Rx unit is under heavy pressure
6920  **/
6921 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6922                                 u32 reg_addr, u32 *reg_val,
6923                                 struct i40e_asq_cmd_details *cmd_details)
6924 {
6925         struct i40e_aq_desc desc;
6926         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6927                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6928         enum i40e_status_code status;
6929
6930         if (reg_val == NULL)
6931                 return I40E_ERR_PARAM;
6932
6933         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6934
6935         cmd_resp->address = CPU_TO_LE32(reg_addr);
6936
6937         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6938
6939         if (status == I40E_SUCCESS)
6940                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6941
6942         return status;
6943 }
6944
6945 /**
6946  * i40e_read_rx_ctl - read from an Rx control register
6947  * @hw: pointer to the hw struct
6948  * @reg_addr: register address
6949  **/
6950 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6951 {
6952         enum i40e_status_code status = I40E_SUCCESS;
6953         bool use_register;
6954         int retry = 5;
6955         u32 val = 0;
6956
6957         use_register = (((hw->aq.api_maj_ver == 1) &&
6958                         (hw->aq.api_min_ver < 5)) ||
6959                         (hw->mac.type == I40E_MAC_X722));
6960         if (!use_register) {
6961 do_retry:
6962                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6963                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6964                         i40e_msec_delay(1);
6965                         retry--;
6966                         goto do_retry;
6967                 }
6968         }
6969
6970         /* if the AQ access failed, try the old-fashioned way */
6971         if (status || use_register)
6972                 val = rd32(hw, reg_addr);
6973
6974         return val;
6975 }
6976
6977 /**
6978  * i40e_aq_rx_ctl_write_register
6979  * @hw: pointer to the hw struct
6980  * @reg_addr: register address
6981  * @reg_val: register value
6982  * @cmd_details: pointer to command details structure or NULL
6983  *
6984  * Use the firmware to write to an Rx control register,
6985  * especially useful if the Rx unit is under heavy pressure
6986  **/
6987 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6988                                 u32 reg_addr, u32 reg_val,
6989                                 struct i40e_asq_cmd_details *cmd_details)
6990 {
6991         struct i40e_aq_desc desc;
6992         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6993                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6994         enum i40e_status_code status;
6995
6996         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6997
6998         cmd->address = CPU_TO_LE32(reg_addr);
6999         cmd->value = CPU_TO_LE32(reg_val);
7000
7001         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7002
7003         return status;
7004 }
7005
7006 /**
7007  * i40e_write_rx_ctl - write to an Rx control register
7008  * @hw: pointer to the hw struct
7009  * @reg_addr: register address
7010  * @reg_val: register value
7011  **/
7012 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7013 {
7014         enum i40e_status_code status = I40E_SUCCESS;
7015         bool use_register;
7016         int retry = 5;
7017
7018         use_register = (((hw->aq.api_maj_ver == 1) &&
7019                         (hw->aq.api_min_ver < 5)) ||
7020                         (hw->mac.type == I40E_MAC_X722));
7021         if (!use_register) {
7022 do_retry:
7023                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7024                                                        reg_val, NULL);
7025                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7026                         i40e_msec_delay(1);
7027                         retry--;
7028                         goto do_retry;
7029                 }
7030         }
7031
7032         /* if the AQ access failed, try the old-fashioned way */
7033         if (status || use_register)
7034                 wr32(hw, reg_addr, reg_val);
7035 }
7036
7037 /**
7038  * i40e_aq_set_phy_register
7039  * @hw: pointer to the hw struct
7040  * @phy_select: select which phy should be accessed
7041  * @dev_addr: PHY device address
7042  * @reg_addr: PHY register address
7043  * @reg_val: new register value
7044  * @cmd_details: pointer to command details structure or NULL
7045  *
7046  * Write the external PHY register.
7047  **/
7048 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7049                                 u8 phy_select, u8 dev_addr,
7050                                 u32 reg_addr, u32 reg_val,
7051                                 struct i40e_asq_cmd_details *cmd_details)
7052 {
7053         struct i40e_aq_desc desc;
7054         struct i40e_aqc_phy_register_access *cmd =
7055                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7056         enum i40e_status_code status;
7057
7058         i40e_fill_default_direct_cmd_desc(&desc,
7059                                           i40e_aqc_opc_set_phy_register);
7060
7061         cmd->phy_interface = phy_select;
7062         cmd->dev_addres = dev_addr;
7063         cmd->reg_address = CPU_TO_LE32(reg_addr);
7064         cmd->reg_value = CPU_TO_LE32(reg_val);
7065
7066         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7067
7068         return status;
7069 }
7070
7071 /**
7072  * i40e_aq_get_phy_register
7073  * @hw: pointer to the hw struct
7074  * @phy_select: select which phy should be accessed
7075  * @dev_addr: PHY device address
7076  * @reg_addr: PHY register address
7077  * @reg_val: read register value
7078  * @cmd_details: pointer to command details structure or NULL
7079  *
7080  * Read the external PHY register.
7081  **/
7082 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7083                                 u8 phy_select, u8 dev_addr,
7084                                 u32 reg_addr, u32 *reg_val,
7085                                 struct i40e_asq_cmd_details *cmd_details)
7086 {
7087         struct i40e_aq_desc desc;
7088         struct i40e_aqc_phy_register_access *cmd =
7089                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7090         enum i40e_status_code status;
7091
7092         i40e_fill_default_direct_cmd_desc(&desc,
7093                                           i40e_aqc_opc_get_phy_register);
7094
7095         cmd->phy_interface = phy_select;
7096         cmd->dev_addres = dev_addr;
7097         cmd->reg_address = CPU_TO_LE32(reg_addr);
7098
7099         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7100         if (!status)
7101                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7102
7103         return status;
7104 }
7105
7106 #ifdef VF_DRIVER
7107
7108 /**
7109  * i40e_aq_send_msg_to_pf
7110  * @hw: pointer to the hardware structure
7111  * @v_opcode: opcodes for VF-PF communication
7112  * @v_retval: return error code
7113  * @msg: pointer to the msg buffer
7114  * @msglen: msg length
7115  * @cmd_details: pointer to command details
7116  *
7117  * Send message to PF driver using admin queue. By default, this message
7118  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7119  * completion before returning.
7120  **/
7121 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7122                                 enum virtchnl_ops v_opcode,
7123                                 enum i40e_status_code v_retval,
7124                                 u8 *msg, u16 msglen,
7125                                 struct i40e_asq_cmd_details *cmd_details)
7126 {
7127         struct i40e_aq_desc desc;
7128         struct i40e_asq_cmd_details details;
7129         enum i40e_status_code status;
7130
7131         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7132         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7133         desc.cookie_high = CPU_TO_LE32(v_opcode);
7134         desc.cookie_low = CPU_TO_LE32(v_retval);
7135         if (msglen) {
7136                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7137                                                 | I40E_AQ_FLAG_RD));
7138                 if (msglen > I40E_AQ_LARGE_BUF)
7139                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7140                 desc.datalen = CPU_TO_LE16(msglen);
7141         }
7142         if (!cmd_details) {
7143                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7144                 details.async = true;
7145                 cmd_details = &details;
7146         }
7147         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7148                                        msglen, cmd_details);
7149         return status;
7150 }
7151
7152 /**
7153  * i40e_vf_parse_hw_config
7154  * @hw: pointer to the hardware structure
7155  * @msg: pointer to the virtual channel VF resource structure
7156  *
7157  * Given a VF resource message from the PF, populate the hw struct
7158  * with appropriate information.
7159  **/
7160 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7161                              struct virtchnl_vf_resource *msg)
7162 {
7163         struct virtchnl_vsi_resource *vsi_res;
7164         int i;
7165
7166         vsi_res = &msg->vsi_res[0];
7167
7168         hw->dev_caps.num_vsis = msg->num_vsis;
7169         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7170         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7171         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7172         hw->dev_caps.dcb = msg->vf_offload_flags &
7173                            VIRTCHNL_VF_OFFLOAD_L2;
7174         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7175                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7176         for (i = 0; i < msg->num_vsis; i++) {
7177                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7178                         i40e_memcpy(hw->mac.perm_addr,
7179                                     vsi_res->default_mac_addr,
7180                                     ETH_ALEN,
7181                                     I40E_NONDMA_TO_NONDMA);
7182                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7183                                     ETH_ALEN,
7184                                     I40E_NONDMA_TO_NONDMA);
7185                 }
7186                 vsi_res++;
7187         }
7188 }
7189
7190 /**
7191  * i40e_vf_reset
7192  * @hw: pointer to the hardware structure
7193  *
7194  * Send a VF_RESET message to the PF. Does not wait for response from PF
7195  * as none will be forthcoming. Immediately after calling this function,
7196  * the admin queue should be shut down and (optionally) reinitialized.
7197  **/
7198 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7199 {
7200         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7201                                       I40E_SUCCESS, NULL, 0, NULL);
7202 }
7203 #endif /* VF_DRIVER */
7204
7205 /**
7206  * i40e_aq_set_arp_proxy_config
7207  * @hw: pointer to the HW structure
7208  * @proxy_config: pointer to proxy config command table struct
7209  * @cmd_details: pointer to command details
7210  *
7211  * Set ARP offload parameters from pre-populated
7212  * i40e_aqc_arp_proxy_data struct
7213  **/
7214 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7215                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7216                                 struct i40e_asq_cmd_details *cmd_details)
7217 {
7218         struct i40e_aq_desc desc;
7219         enum i40e_status_code status;
7220
7221         if (!proxy_config)
7222                 return I40E_ERR_PARAM;
7223
7224         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7225
7226         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7227         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7228         desc.params.external.addr_high =
7229                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7230         desc.params.external.addr_low =
7231                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7232         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7233
7234         status = i40e_asq_send_command(hw, &desc, proxy_config,
7235                                        sizeof(struct i40e_aqc_arp_proxy_data),
7236                                        cmd_details);
7237
7238         return status;
7239 }
7240
7241 /**
7242  * i40e_aq_opc_set_ns_proxy_table_entry
7243  * @hw: pointer to the HW structure
7244  * @ns_proxy_table_entry: pointer to NS table entry command struct
7245  * @cmd_details: pointer to command details
7246  *
7247  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7248  * from pre-populated i40e_aqc_ns_proxy_data struct
7249  **/
7250 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7251                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7252                         struct i40e_asq_cmd_details *cmd_details)
7253 {
7254         struct i40e_aq_desc desc;
7255         enum i40e_status_code status;
7256
7257         if (!ns_proxy_table_entry)
7258                 return I40E_ERR_PARAM;
7259
7260         i40e_fill_default_direct_cmd_desc(&desc,
7261                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7262
7263         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7264         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7265         desc.params.external.addr_high =
7266                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7267         desc.params.external.addr_low =
7268                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7269         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7270
7271         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7272                                        sizeof(struct i40e_aqc_ns_proxy_data),
7273                                        cmd_details);
7274
7275         return status;
7276 }
7277
7278 /**
7279  * i40e_aq_set_clear_wol_filter
7280  * @hw: pointer to the hw struct
7281  * @filter_index: index of filter to modify (0-7)
7282  * @filter: buffer containing filter to be set
7283  * @set_filter: true to set filter, false to clear filter
7284  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7285  *              if false, pass through packets may cause wake-up
7286  * @filter_valid: true if filter action is valid
7287  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7288  * @cmd_details: pointer to command details structure or NULL
7289  *
7290  * Set or clear WoL filter for port attached to the PF
7291  **/
7292 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7293                                 u8 filter_index,
7294                                 struct i40e_aqc_set_wol_filter_data *filter,
7295                                 bool set_filter, bool no_wol_tco,
7296                                 bool filter_valid, bool no_wol_tco_valid,
7297                                 struct i40e_asq_cmd_details *cmd_details)
7298 {
7299         struct i40e_aq_desc desc;
7300         struct i40e_aqc_set_wol_filter *cmd =
7301                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7302         enum i40e_status_code status;
7303         u16 cmd_flags = 0;
7304         u16 valid_flags = 0;
7305         u16 buff_len = 0;
7306
7307         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7308
7309         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7310                 return  I40E_ERR_PARAM;
7311         cmd->filter_index = CPU_TO_LE16(filter_index);
7312
7313         if (set_filter) {
7314                 if (!filter)
7315                         return  I40E_ERR_PARAM;
7316
7317                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7318                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7319         }
7320
7321         if (no_wol_tco)
7322                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7323         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7324
7325         if (filter_valid)
7326                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7327         if (no_wol_tco_valid)
7328                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7329         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7330
7331         buff_len = sizeof(*filter);
7332         desc.datalen = CPU_TO_LE16(buff_len);
7333
7334         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7335         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7336
7337         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7338         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7339
7340         status = i40e_asq_send_command(hw, &desc, filter,
7341                                        buff_len, cmd_details);
7342
7343         return status;
7344 }
7345
7346 /**
7347  * i40e_aq_get_wake_event_reason
7348  * @hw: pointer to the hw struct
7349  * @wake_reason: return value, index of matching filter
7350  * @cmd_details: pointer to command details structure or NULL
7351  *
7352  * Get information for the reason of a Wake Up event
7353  **/
7354 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7355                                 u16 *wake_reason,
7356                                 struct i40e_asq_cmd_details *cmd_details)
7357 {
7358         struct i40e_aq_desc desc;
7359         struct i40e_aqc_get_wake_reason_completion *resp =
7360                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7361         enum i40e_status_code status;
7362
7363         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7364
7365         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7366
7367         if (status == I40E_SUCCESS)
7368                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7369
7370         return status;
7371 }
7372
7373 /**
7374 * i40e_aq_clear_all_wol_filters
7375 * @hw: pointer to the hw struct
7376 * @cmd_details: pointer to command details structure or NULL
7377 *
7378 * Get information for the reason of a Wake Up event
7379 **/
7380 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7381         struct i40e_asq_cmd_details *cmd_details)
7382 {
7383         struct i40e_aq_desc desc;
7384         enum i40e_status_code status;
7385
7386         i40e_fill_default_direct_cmd_desc(&desc,
7387                                           i40e_aqc_opc_clear_all_wol_filters);
7388
7389         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7390
7391         return status;
7392 }
7393
7394 /**
7395  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7396  * @hw: pointer to the hw struct
7397  * @buff: command buffer (size in bytes = buff_size)
7398  * @buff_size: buffer size in bytes
7399  * @track_id: package tracking id
7400  * @error_offset: returns error offset
7401  * @error_info: returns error information
7402  * @cmd_details: pointer to command details structure or NULL
7403  **/
7404 enum
7405 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7406                                    u16 buff_size, u32 track_id,
7407                                    u32 *error_offset, u32 *error_info,
7408                                    struct i40e_asq_cmd_details *cmd_details)
7409 {
7410         struct i40e_aq_desc desc;
7411         struct i40e_aqc_write_personalization_profile *cmd =
7412                 (struct i40e_aqc_write_personalization_profile *)
7413                 &desc.params.raw;
7414         struct i40e_aqc_write_ddp_resp *resp;
7415         enum i40e_status_code status;
7416
7417         i40e_fill_default_direct_cmd_desc(&desc,
7418                                   i40e_aqc_opc_write_personalization_profile);
7419
7420         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7421         if (buff_size > I40E_AQ_LARGE_BUF)
7422                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7423
7424         desc.datalen = CPU_TO_LE16(buff_size);
7425
7426         cmd->profile_track_id = CPU_TO_LE32(track_id);
7427
7428         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7429         if (!status) {
7430                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7431                 if (error_offset)
7432                         *error_offset = LE32_TO_CPU(resp->error_offset);
7433                 if (error_info)
7434                         *error_info = LE32_TO_CPU(resp->error_info);
7435         }
7436
7437         return status;
7438 }
7439
7440 /**
7441  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7442  * @hw: pointer to the hw struct
7443  * @buff: command buffer (size in bytes = buff_size)
7444  * @buff_size: buffer size in bytes
7445  * @flags: AdminQ command flags
7446  * @cmd_details: pointer to command details structure or NULL
7447  **/
7448 enum
7449 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7450                                       u16 buff_size, u8 flags,
7451                                       struct i40e_asq_cmd_details *cmd_details)
7452 {
7453         struct i40e_aq_desc desc;
7454         struct i40e_aqc_get_applied_profiles *cmd =
7455                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7456         enum i40e_status_code status;
7457
7458         i40e_fill_default_direct_cmd_desc(&desc,
7459                           i40e_aqc_opc_get_personalization_profile_list);
7460
7461         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7462         if (buff_size > I40E_AQ_LARGE_BUF)
7463                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7464         desc.datalen = CPU_TO_LE16(buff_size);
7465
7466         cmd->flags = flags;
7467
7468         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7469
7470         return status;
7471 }
7472
7473 /**
7474  * i40e_find_segment_in_package
7475  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7476  * @pkg_hdr: pointer to the package header to be searched
7477  *
7478  * This function searches a package file for a particular segment type. On
7479  * success it returns a pointer to the segment header, otherwise it will
7480  * return NULL.
7481  **/
7482 struct i40e_generic_seg_header *
7483 i40e_find_segment_in_package(u32 segment_type,
7484                              struct i40e_package_header *pkg_hdr)
7485 {
7486         struct i40e_generic_seg_header *segment;
7487         u32 i;
7488
7489         /* Search all package segments for the requested segment type */
7490         for (i = 0; i < pkg_hdr->segment_count; i++) {
7491                 segment =
7492                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7493                          pkg_hdr->segment_offset[i]);
7494
7495                 if (segment->type == segment_type)
7496                         return segment;
7497         }
7498
7499         return NULL;
7500 }
7501
7502 /* Get section table in profile */
7503 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7504         do {                                                            \
7505                 struct i40e_profile_segment *p = (profile);             \
7506                 u32 count;                                              \
7507                 u32 *nvm;                                               \
7508                 count = p->device_table_count;                          \
7509                 nvm = (u32 *)&p->device_table[count];                   \
7510                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7511         } while (0)
7512
7513 /* Get section header in profile */
7514 #define I40E_SECTION_HEADER(profile, offset)                            \
7515         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7516
7517 /**
7518  * i40e_find_section_in_profile
7519  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7520  * @profile: pointer to the i40e segment header to be searched
7521  *
7522  * This function searches i40e segment for a particular section type. On
7523  * success it returns a pointer to the section header, otherwise it will
7524  * return NULL.
7525  **/
7526 struct i40e_profile_section_header *
7527 i40e_find_section_in_profile(u32 section_type,
7528                              struct i40e_profile_segment *profile)
7529 {
7530         struct i40e_profile_section_header *sec;
7531         struct i40e_section_table *sec_tbl;
7532         u32 sec_off;
7533         u32 i;
7534
7535         if (profile->header.type != SEGMENT_TYPE_I40E)
7536                 return NULL;
7537
7538         I40E_SECTION_TABLE(profile, sec_tbl);
7539
7540         for (i = 0; i < sec_tbl->section_count; i++) {
7541                 sec_off = sec_tbl->section_offset[i];
7542                 sec = I40E_SECTION_HEADER(profile, sec_off);
7543                 if (sec->section.type == section_type)
7544                         return sec;
7545         }
7546
7547         return NULL;
7548 }
7549
7550 /**
7551  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7552  * @hw: pointer to the hw struct
7553  * @aq: command buffer containing all data to execute AQ
7554  **/
7555 STATIC enum
7556 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7557                                           struct i40e_profile_aq_section *aq)
7558 {
7559         enum i40e_status_code status;
7560         struct i40e_aq_desc desc;
7561         u8 *msg = NULL;
7562         u16 msglen;
7563
7564         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7565         desc.flags |= CPU_TO_LE16(aq->flags);
7566         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7567                     I40E_NONDMA_TO_NONDMA);
7568
7569         msglen = aq->datalen;
7570         if (msglen) {
7571                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7572                                                 I40E_AQ_FLAG_RD));
7573                 if (msglen > I40E_AQ_LARGE_BUF)
7574                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7575                 desc.datalen = CPU_TO_LE16(msglen);
7576                 msg = &aq->data[0];
7577         }
7578
7579         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7580
7581         if (status != I40E_SUCCESS) {
7582                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7583                            "unable to exec DDP AQ opcode %u, error %d\n",
7584                            aq->opcode, status);
7585                 return status;
7586         }
7587
7588         /* copy returned desc to aq_buf */
7589         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7590                     I40E_NONDMA_TO_NONDMA);
7591
7592         return I40E_SUCCESS;
7593 }
7594
7595 /**
7596  * i40e_validate_profile
7597  * @hw: pointer to the hardware structure
7598  * @profile: pointer to the profile segment of the package to be validated
7599  * @track_id: package tracking id
7600  * @rollback: flag if the profile is for rollback.
7601  *
7602  * Validates supported devices and profile's sections.
7603  */
7604 STATIC enum i40e_status_code
7605 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7606                       u32 track_id, bool rollback)
7607 {
7608         struct i40e_profile_section_header *sec = NULL;
7609         enum i40e_status_code status = I40E_SUCCESS;
7610         struct i40e_section_table *sec_tbl;
7611         u32 vendor_dev_id;
7612         u32 dev_cnt;
7613         u32 sec_off;
7614         u32 i;
7615
7616         if (track_id == I40E_DDP_TRACKID_INVALID) {
7617                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7618                 return I40E_NOT_SUPPORTED;
7619         }
7620
7621         dev_cnt = profile->device_table_count;
7622         for (i = 0; i < dev_cnt; i++) {
7623                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7624                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7625                     hw->device_id == (vendor_dev_id & 0xFFFF))
7626                         break;
7627         }
7628         if (dev_cnt && (i == dev_cnt)) {
7629                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7630                            "Device doesn't support DDP\n");
7631                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7632         }
7633
7634         I40E_SECTION_TABLE(profile, sec_tbl);
7635
7636         /* Validate sections types */
7637         for (i = 0; i < sec_tbl->section_count; i++) {
7638                 sec_off = sec_tbl->section_offset[i];
7639                 sec = I40E_SECTION_HEADER(profile, sec_off);
7640                 if (rollback) {
7641                         if (sec->section.type == SECTION_TYPE_MMIO ||
7642                             sec->section.type == SECTION_TYPE_AQ ||
7643                             sec->section.type == SECTION_TYPE_RB_AQ) {
7644                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7645                                            "Not a roll-back package\n");
7646                                 return I40E_NOT_SUPPORTED;
7647                         }
7648                 } else {
7649                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7650                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7651                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7652                                            "Not an original package\n");
7653                                 return I40E_NOT_SUPPORTED;
7654                         }
7655                 }
7656         }
7657
7658         return status;
7659 }
7660
7661 /**
7662  * i40e_write_profile
7663  * @hw: pointer to the hardware structure
7664  * @profile: pointer to the profile segment of the package to be downloaded
7665  * @track_id: package tracking id
7666  *
7667  * Handles the download of a complete package.
7668  */
7669 enum i40e_status_code
7670 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7671                    u32 track_id)
7672 {
7673         enum i40e_status_code status = I40E_SUCCESS;
7674         struct i40e_section_table *sec_tbl;
7675         struct i40e_profile_section_header *sec = NULL;
7676         struct i40e_profile_aq_section *ddp_aq;
7677         u32 section_size = 0;
7678         u32 offset = 0, info = 0;
7679         u32 sec_off;
7680         u32 i;
7681
7682         status = i40e_validate_profile(hw, profile, track_id, false);
7683         if (status)
7684                 return status;
7685
7686         I40E_SECTION_TABLE(profile, sec_tbl);
7687
7688         for (i = 0; i < sec_tbl->section_count; i++) {
7689                 sec_off = sec_tbl->section_offset[i];
7690                 sec = I40E_SECTION_HEADER(profile, sec_off);
7691                 /* Process generic admin command */
7692                 if (sec->section.type == SECTION_TYPE_AQ) {
7693                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7694                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7695                         if (status) {
7696                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7697                                            "Failed to execute aq: section %d, opcode %u\n",
7698                                            i, ddp_aq->opcode);
7699                                 break;
7700                         }
7701                         sec->section.type = SECTION_TYPE_RB_AQ;
7702                 }
7703
7704                 /* Skip any non-mmio sections */
7705                 if (sec->section.type != SECTION_TYPE_MMIO)
7706                         continue;
7707
7708                 section_size = sec->section.size +
7709                         sizeof(struct i40e_profile_section_header);
7710
7711                 /* Write MMIO section */
7712                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7713                                            track_id, &offset, &info, NULL);
7714                 if (status) {
7715                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7716                                    "Failed to write profile: section %d, offset %d, info %d\n",
7717                                    i, offset, info);
7718                         break;
7719                 }
7720         }
7721         return status;
7722 }
7723
7724 /**
7725  * i40e_rollback_profile
7726  * @hw: pointer to the hardware structure
7727  * @profile: pointer to the profile segment of the package to be removed
7728  * @track_id: package tracking id
7729  *
7730  * Rolls back previously loaded package.
7731  */
7732 enum i40e_status_code
7733 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7734                       u32 track_id)
7735 {
7736         struct i40e_profile_section_header *sec = NULL;
7737         enum i40e_status_code status = I40E_SUCCESS;
7738         struct i40e_section_table *sec_tbl;
7739         u32 offset = 0, info = 0;
7740         u32 section_size = 0;
7741         u32 sec_off;
7742         int i;
7743
7744         status = i40e_validate_profile(hw, profile, track_id, true);
7745         if (status)
7746                 return status;
7747
7748         I40E_SECTION_TABLE(profile, sec_tbl);
7749
7750         /* For rollback write sections in reverse */
7751         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7752                 sec_off = sec_tbl->section_offset[i];
7753                 sec = I40E_SECTION_HEADER(profile, sec_off);
7754
7755                 /* Skip any non-rollback sections */
7756                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7757                         continue;
7758
7759                 section_size = sec->section.size +
7760                         sizeof(struct i40e_profile_section_header);
7761
7762                 /* Write roll-back MMIO section */
7763                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7764                                            track_id, &offset, &info, NULL);
7765                 if (status) {
7766                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7767                                    "Failed to write profile: section %d, offset %d, info %d\n",
7768                                    i, offset, info);
7769                         break;
7770                 }
7771         }
7772         return status;
7773 }
7774
7775 /**
7776  * i40e_add_pinfo_to_list
7777  * @hw: pointer to the hardware structure
7778  * @profile: pointer to the profile segment of the package
7779  * @profile_info_sec: buffer for information section
7780  * @track_id: package tracking id
7781  *
7782  * Register a profile to the list of loaded profiles.
7783  */
7784 enum i40e_status_code
7785 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7786                        struct i40e_profile_segment *profile,
7787                        u8 *profile_info_sec, u32 track_id)
7788 {
7789         enum i40e_status_code status = I40E_SUCCESS;
7790         struct i40e_profile_section_header *sec = NULL;
7791         struct i40e_profile_info *pinfo;
7792         u32 offset = 0, info = 0;
7793
7794         sec = (struct i40e_profile_section_header *)profile_info_sec;
7795         sec->tbl_size = 1;
7796         sec->data_end = sizeof(struct i40e_profile_section_header) +
7797                         sizeof(struct i40e_profile_info);
7798         sec->section.type = SECTION_TYPE_INFO;
7799         sec->section.offset = sizeof(struct i40e_profile_section_header);
7800         sec->section.size = sizeof(struct i40e_profile_info);
7801         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7802                                              sec->section.offset);
7803         pinfo->track_id = track_id;
7804         pinfo->version = profile->version;
7805         pinfo->op = I40E_DDP_ADD_TRACKID;
7806         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7807                     I40E_NONDMA_TO_NONDMA);
7808
7809         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7810                                    track_id, &offset, &info, NULL);
7811         return status;
7812 }