drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2020 Intel Corporation
   3  */
   4
   5 #include <inttypes.h>
   6
   7 #include "i40e_type.h"
   8 #include "i40e_adminq.h"
   9 #include "i40e_prototype.h"
  10 #include "virtchnl.h"
  11
  12 /**
  13  * i40e_set_mac_type - Sets MAC type
  14  * @hw: pointer to the HW structure
  15  *
  16  * This function sets the mac type of the adapter based on the
  17  * vendor ID and device ID stored in the hw structure.
  18  **/
  19 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  20 {
  21         enum i40e_status_code status = I40E_SUCCESS;
  22
  23         DEBUGFUNC("i40e_set_mac_type\n");
  24
  25         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  26                 switch (hw->device_id) {
  27                 case I40E_DEV_ID_SFP_XL710:
  28                 case I40E_DEV_ID_QEMU:
  29                 case I40E_DEV_ID_KX_B:
  30                 case I40E_DEV_ID_KX_C:
  31                 case I40E_DEV_ID_QSFP_A:
  32                 case I40E_DEV_ID_QSFP_B:
  33                 case I40E_DEV_ID_QSFP_C:
  34                 case I40E_DEV_ID_10G_BASE_T:
  35                 case I40E_DEV_ID_10G_BASE_T4:
  36                 case I40E_DEV_ID_10G_BASE_T_BC:
  37                 case I40E_DEV_ID_10G_B:
  38                 case I40E_DEV_ID_10G_SFP:
  39                 case I40E_DEV_ID_5G_BASE_T_BC:
  40                 case I40E_DEV_ID_20G_KR2:
  41                 case I40E_DEV_ID_20G_KR2_A:
  42                 case I40E_DEV_ID_25G_B:
  43                 case I40E_DEV_ID_25G_SFP28:
  44                 case I40E_DEV_ID_X710_N3000:
  45                 case I40E_DEV_ID_XXV710_N3000:
  46                         hw->mac.type = I40E_MAC_XL710;
  47                         break;
  48 #ifdef X722_A0_SUPPORT
  49                 case I40E_DEV_ID_X722_A0:
  50 #endif
  51                 case I40E_DEV_ID_KX_X722:
  52                 case I40E_DEV_ID_QSFP_X722:
  53                 case I40E_DEV_ID_SFP_X722:
  54                 case I40E_DEV_ID_1G_BASE_T_X722:
  55                 case I40E_DEV_ID_10G_BASE_T_X722:
  56                 case I40E_DEV_ID_SFP_I_X722:
  57                         hw->mac.type = I40E_MAC_X722;
  58                         break;
  59 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  60                 case I40E_DEV_ID_X722_VF:
  61 #ifdef X722_A0_SUPPORT
  62                 case I40E_DEV_ID_X722_A0_VF:
  63 #endif
  64                         hw->mac.type = I40E_MAC_X722_VF;
  65                         break;
  66 #endif /* INTEGRATED_VF || VF_DRIVER */
  67 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  68                 case I40E_DEV_ID_VF:
  69                 case I40E_DEV_ID_VF_HV:
  70                 case I40E_DEV_ID_ADAPTIVE_VF:
  71                         hw->mac.type = I40E_MAC_VF;
  72                         break;
  73 #endif
  74                 default:
  75                         hw->mac.type = I40E_MAC_GENERIC;
  76                         break;
  77                 }
  78         } else {
  79                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  80         }
  81
  82         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  83                   hw->mac.type, status);
  84         return status;
  85 }
  86
  87 /**
  88  * i40e_aq_str - convert AQ err code to a string
  89  * @hw: pointer to the HW structure
  90  * @aq_err: the AQ error code to convert
  91  **/
  92 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  93 {
  94         switch (aq_err) {
  95         case I40E_AQ_RC_OK:
  96                 return "OK";
  97         case I40E_AQ_RC_EPERM:
  98                 return "I40E_AQ_RC_EPERM";
  99         case I40E_AQ_RC_ENOENT:
 100                 return "I40E_AQ_RC_ENOENT";
 101         case I40E_AQ_RC_ESRCH:
 102                 return "I40E_AQ_RC_ESRCH";
 103         case I40E_AQ_RC_EINTR:
 104                 return "I40E_AQ_RC_EINTR";
 105         case I40E_AQ_RC_EIO:
 106                 return "I40E_AQ_RC_EIO";
 107         case I40E_AQ_RC_ENXIO:
 108                 return "I40E_AQ_RC_ENXIO";
 109         case I40E_AQ_RC_E2BIG:
 110                 return "I40E_AQ_RC_E2BIG";
 111         case I40E_AQ_RC_EAGAIN:
 112                 return "I40E_AQ_RC_EAGAIN";
 113         case I40E_AQ_RC_ENOMEM:
 114                 return "I40E_AQ_RC_ENOMEM";
 115         case I40E_AQ_RC_EACCES:
 116                 return "I40E_AQ_RC_EACCES";
 117         case I40E_AQ_RC_EFAULT:
 118                 return "I40E_AQ_RC_EFAULT";
 119         case I40E_AQ_RC_EBUSY:
 120                 return "I40E_AQ_RC_EBUSY";
 121         case I40E_AQ_RC_EEXIST:
 122                 return "I40E_AQ_RC_EEXIST";
 123         case I40E_AQ_RC_EINVAL:
 124                 return "I40E_AQ_RC_EINVAL";
 125         case I40E_AQ_RC_ENOTTY:
 126                 return "I40E_AQ_RC_ENOTTY";
 127         case I40E_AQ_RC_ENOSPC:
 128                 return "I40E_AQ_RC_ENOSPC";
 129         case I40E_AQ_RC_ENOSYS:
 130                 return "I40E_AQ_RC_ENOSYS";
 131         case I40E_AQ_RC_ERANGE:
 132                 return "I40E_AQ_RC_ERANGE";
 133         case I40E_AQ_RC_EFLUSHED:
 134                 return "I40E_AQ_RC_EFLUSHED";
 135         case I40E_AQ_RC_BAD_ADDR:
 136                 return "I40E_AQ_RC_BAD_ADDR";
 137         case I40E_AQ_RC_EMODE:
 138                 return "I40E_AQ_RC_EMODE";
 139         case I40E_AQ_RC_EFBIG:
 140                 return "I40E_AQ_RC_EFBIG";
 141         }
 142
 143         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 144         return hw->err_str;
 145 }
 146
 147 /**
 148  * i40e_stat_str - convert status err code to a string
 149  * @hw: pointer to the HW structure
 150  * @stat_err: the status error code to convert
 151  **/
 152 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 153 {
 154         switch (stat_err) {
 155         case I40E_SUCCESS:
 156                 return "OK";
 157         case I40E_ERR_NVM:
 158                 return "I40E_ERR_NVM";
 159         case I40E_ERR_NVM_CHECKSUM:
 160                 return "I40E_ERR_NVM_CHECKSUM";
 161         case I40E_ERR_PHY:
 162                 return "I40E_ERR_PHY";
 163         case I40E_ERR_CONFIG:
 164                 return "I40E_ERR_CONFIG";
 165         case I40E_ERR_PARAM:
 166                 return "I40E_ERR_PARAM";
 167         case I40E_ERR_MAC_TYPE:
 168                 return "I40E_ERR_MAC_TYPE";
 169         case I40E_ERR_UNKNOWN_PHY:
 170                 return "I40E_ERR_UNKNOWN_PHY";
 171         case I40E_ERR_LINK_SETUP:
 172                 return "I40E_ERR_LINK_SETUP";
 173         case I40E_ERR_ADAPTER_STOPPED:
 174                 return "I40E_ERR_ADAPTER_STOPPED";
 175         case I40E_ERR_INVALID_MAC_ADDR:
 176                 return "I40E_ERR_INVALID_MAC_ADDR";
 177         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 178                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 179         case I40E_ERR_MASTER_REQUESTS_PENDING:
 180                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 181         case I40E_ERR_INVALID_LINK_SETTINGS:
 182                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 183         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 184                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 185         case I40E_ERR_RESET_FAILED:
 186                 return "I40E_ERR_RESET_FAILED";
 187         case I40E_ERR_SWFW_SYNC:
 188                 return "I40E_ERR_SWFW_SYNC";
 189         case I40E_ERR_NO_AVAILABLE_VSI:
 190                 return "I40E_ERR_NO_AVAILABLE_VSI";
 191         case I40E_ERR_NO_MEMORY:
 192                 return "I40E_ERR_NO_MEMORY";
 193         case I40E_ERR_BAD_PTR:
 194                 return "I40E_ERR_BAD_PTR";
 195         case I40E_ERR_RING_FULL:
 196                 return "I40E_ERR_RING_FULL";
 197         case I40E_ERR_INVALID_PD_ID:
 198                 return "I40E_ERR_INVALID_PD_ID";
 199         case I40E_ERR_INVALID_QP_ID:
 200                 return "I40E_ERR_INVALID_QP_ID";
 201         case I40E_ERR_INVALID_CQ_ID:
 202                 return "I40E_ERR_INVALID_CQ_ID";
 203         case I40E_ERR_INVALID_CEQ_ID:
 204                 return "I40E_ERR_INVALID_CEQ_ID";
 205         case I40E_ERR_INVALID_AEQ_ID:
 206                 return "I40E_ERR_INVALID_AEQ_ID";
 207         case I40E_ERR_INVALID_SIZE:
 208                 return "I40E_ERR_INVALID_SIZE";
 209         case I40E_ERR_INVALID_ARP_INDEX:
 210                 return "I40E_ERR_INVALID_ARP_INDEX";
 211         case I40E_ERR_INVALID_FPM_FUNC_ID:
 212                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 213         case I40E_ERR_QP_INVALID_MSG_SIZE:
 214                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 215         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 216                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 217         case I40E_ERR_INVALID_FRAG_COUNT:
 218                 return "I40E_ERR_INVALID_FRAG_COUNT";
 219         case I40E_ERR_QUEUE_EMPTY:
 220                 return "I40E_ERR_QUEUE_EMPTY";
 221         case I40E_ERR_INVALID_ALIGNMENT:
 222                 return "I40E_ERR_INVALID_ALIGNMENT";
 223         case I40E_ERR_FLUSHED_QUEUE:
 224                 return "I40E_ERR_FLUSHED_QUEUE";
 225         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 226                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 227         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 228                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 229         case I40E_ERR_TIMEOUT:
 230                 return "I40E_ERR_TIMEOUT";
 231         case I40E_ERR_OPCODE_MISMATCH:
 232                 return "I40E_ERR_OPCODE_MISMATCH";
 233         case I40E_ERR_CQP_COMPL_ERROR:
 234                 return "I40E_ERR_CQP_COMPL_ERROR";
 235         case I40E_ERR_INVALID_VF_ID:
 236                 return "I40E_ERR_INVALID_VF_ID";
 237         case I40E_ERR_INVALID_HMCFN_ID:
 238                 return "I40E_ERR_INVALID_HMCFN_ID";
 239         case I40E_ERR_BACKING_PAGE_ERROR:
 240                 return "I40E_ERR_BACKING_PAGE_ERROR";
 241         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 242                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 243         case I40E_ERR_INVALID_PBLE_INDEX:
 244                 return "I40E_ERR_INVALID_PBLE_INDEX";
 245         case I40E_ERR_INVALID_SD_INDEX:
 246                 return "I40E_ERR_INVALID_SD_INDEX";
 247         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 248                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 249         case I40E_ERR_INVALID_SD_TYPE:
 250                 return "I40E_ERR_INVALID_SD_TYPE";
 251         case I40E_ERR_MEMCPY_FAILED:
 252                 return "I40E_ERR_MEMCPY_FAILED";
 253         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 254                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 255         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 256                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 257         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 258                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 259         case I40E_ERR_SRQ_ENABLED:
 260                 return "I40E_ERR_SRQ_ENABLED";
 261         case I40E_ERR_ADMIN_QUEUE_ERROR:
 262                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 263         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 264                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 265         case I40E_ERR_BUF_TOO_SHORT:
 266                 return "I40E_ERR_BUF_TOO_SHORT";
 267         case I40E_ERR_ADMIN_QUEUE_FULL:
 268                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 269         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 270                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 271         case I40E_ERR_BAD_IWARP_CQE:
 272                 return "I40E_ERR_BAD_IWARP_CQE";
 273         case I40E_ERR_NVM_BLANK_MODE:
 274                 return "I40E_ERR_NVM_BLANK_MODE";
 275         case I40E_ERR_NOT_IMPLEMENTED:
 276                 return "I40E_ERR_NOT_IMPLEMENTED";
 277         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 278                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 279         case I40E_ERR_DIAG_TEST_FAILED:
 280                 return "I40E_ERR_DIAG_TEST_FAILED";
 281         case I40E_ERR_NOT_READY:
 282                 return "I40E_ERR_NOT_READY";
 283         case I40E_NOT_SUPPORTED:
 284                 return "I40E_NOT_SUPPORTED";
 285         case I40E_ERR_FIRMWARE_API_VERSION:
 286                 return "I40E_ERR_FIRMWARE_API_VERSION";
 287         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 289         }
 290
 291         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 292         return hw->err_str;
 293 }
 294
 295 /**
 296  * i40e_debug_aq
 297  * @hw: debug mask related to admin queue
 298  * @mask: debug mask
 299  * @desc: pointer to admin queue descriptor
 300  * @buffer: pointer to command buffer
 301  * @buf_len: max length of buffer
 302  *
 303  * Dumps debug log about adminq command with descriptor contents.
 304  **/
 305 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 306                    void *buffer, u16 buf_len)
 307 {
 308         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 309         u32 effective_mask = hw->debug_mask & mask;
 310         u8 *buf = (u8 *)buffer;
 311         u16 len;
 312         u16 i;
 313
 314         if (!effective_mask || !desc)
 315                 return;
 316
 317         len = LE16_TO_CPU(aq_desc->datalen);
 318
 319         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 320                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 321                    LE16_TO_CPU(aq_desc->opcode),
 322                    LE16_TO_CPU(aq_desc->flags),
 323                    LE16_TO_CPU(aq_desc->datalen),
 324                    LE16_TO_CPU(aq_desc->retval));
 325         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 326                    "\tcookie (h,l) 0x%08X 0x%08X\n",
 327                    LE32_TO_CPU(aq_desc->cookie_high),
 328                    LE32_TO_CPU(aq_desc->cookie_low));
 329         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 330                    "\tparam (0,1)  0x%08X 0x%08X\n",
 331                    LE32_TO_CPU(aq_desc->params.internal.param0),
 332                    LE32_TO_CPU(aq_desc->params.internal.param1));
 333         i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
 334                    "\taddr (h,l)   0x%08X 0x%08X\n",
 335                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 336                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 337
 338         if (buffer && (buf_len != 0) && (len != 0) &&
 339             (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
 340                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 341                 if (buf_len < len)
 342                         len = buf_len;
 343                 /* write the full 16-byte chunks */
 344                 for (i = 0; i < (len - 16); i += 16)
 345                         i40e_debug(hw, mask,
 346                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 347                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 348                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 349                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 350                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 351                 /* the most we could have left is 16 bytes, pad with zeros */
 352                 if (i < len) {
 353                         char d_buf[16];
 354                         int j, i_sav;
 355
 356                         i_sav = i;
 357                         memset(d_buf, 0, sizeof(d_buf));
 358                         for (j = 0; i < len; j++, i++)
 359                                 d_buf[j] = buf[i];
 360                         i40e_debug(hw, mask,
 361                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 362                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 363                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 364                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 365                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 366                 }
 367         }
 368 }
 369
 370 /**
 371  * i40e_check_asq_alive
 372  * @hw: pointer to the hw struct
 373  *
 374  * Returns true if Queue is enabled else false.
 375  **/
 376 bool i40e_check_asq_alive(struct i40e_hw *hw)
 377 {
 378         if (hw->aq.asq.len)
 379 #ifdef PF_DRIVER
 380 #ifdef INTEGRATED_VF
 381                 if (!i40e_is_vf(hw))
 382                         return !!(rd32(hw, hw->aq.asq.len) &
 383                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 384 #else
 385                 return !!(rd32(hw, hw->aq.asq.len) &
 386                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 387 #endif /* INTEGRATED_VF */
 388 #endif /* PF_DRIVER */
 389 #ifdef VF_DRIVER
 390 #ifdef INTEGRATED_VF
 391                 if (i40e_is_vf(hw))
 392                         return !!(rd32(hw, hw->aq.asq.len) &
 393                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 394 #else
 395                 return !!(rd32(hw, hw->aq.asq.len) &
 396                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 397 #endif /* INTEGRATED_VF */
 398 #endif /* VF_DRIVER */
 399         return false;
 400 }
 401
 402 /**
 403  * i40e_aq_queue_shutdown
 404  * @hw: pointer to the hw struct
 405  * @unloading: is the driver unloading itself
 406  *
 407  * Tell the Firmware that we're shutting down the AdminQ and whether
 408  * or not the driver is unloading as well.
 409  **/
 410 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 411                                              bool unloading)
 412 {
 413         struct i40e_aq_desc desc;
 414         struct i40e_aqc_queue_shutdown *cmd =
 415                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 416         enum i40e_status_code status;
 417
 418         i40e_fill_default_direct_cmd_desc(&desc,
 419                                           i40e_aqc_opc_queue_shutdown);
 420
 421         if (unloading)
 422                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 423         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 424
 425         return status;
 426 }
 427
 428 /**
 429  * i40e_aq_get_set_rss_lut
 430  * @hw: pointer to the hardware structure
 431  * @vsi_id: vsi fw index
 432  * @pf_lut: for PF table set true, for VSI table set false
 433  * @lut: pointer to the lut buffer provided by the caller
 434  * @lut_size: size of the lut buffer
 435  * @set: set true to set the table, false to get the table
 436  *
 437  * Internal function to get or set RSS look up table
 438  **/
 439 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 440                                                      u16 vsi_id, bool pf_lut,
 441                                                      u8 *lut, u16 lut_size,
 442                                                      bool set)
 443 {
 444         enum i40e_status_code status;
 445         struct i40e_aq_desc desc;
 446         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 447                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 448
 449         if (set)
 450                 i40e_fill_default_direct_cmd_desc(&desc,
 451                                                   i40e_aqc_opc_set_rss_lut);
 452         else
 453                 i40e_fill_default_direct_cmd_desc(&desc,
 454                                                   i40e_aqc_opc_get_rss_lut);
 455
 456         /* Indirect command */
 457         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 458         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 459
 460         cmd_resp->vsi_id =
 461                         CPU_TO_LE16((u16)((vsi_id <<
 462                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 463                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 464         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 465
 466         if (pf_lut)
 467                 cmd_resp->flags |= CPU_TO_LE16((u16)
 468                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 469                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 470                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 471         else
 472                 cmd_resp->flags |= CPU_TO_LE16((u16)
 473                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 474                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 475                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 476
 477         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 478
 479         return status;
 480 }
 481
 482 /**
 483  * i40e_aq_get_rss_lut
 484  * @hw: pointer to the hardware structure
 485  * @vsi_id: vsi fw index
 486  * @pf_lut: for PF table set true, for VSI table set false
 487  * @lut: pointer to the lut buffer provided by the caller
 488  * @lut_size: size of the lut buffer
 489  *
 490  * get the RSS lookup table, PF or VSI type
 491  **/
 492 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 493                                           bool pf_lut, u8 *lut, u16 lut_size)
 494 {
 495         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 496                                        false);
 497 }
 498
 499 /**
 500  * i40e_aq_set_rss_lut
 501  * @hw: pointer to the hardware structure
 502  * @vsi_id: vsi fw index
 503  * @pf_lut: for PF table set true, for VSI table set false
 504  * @lut: pointer to the lut buffer provided by the caller
 505  * @lut_size: size of the lut buffer
 506  *
 507  * set the RSS lookup table, PF or VSI type
 508  **/
 509 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 510                                           bool pf_lut, u8 *lut, u16 lut_size)
 511 {
 512         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 513 }
 514
 515 /**
 516  * i40e_aq_get_set_rss_key
 517  * @hw: pointer to the hw struct
 518  * @vsi_id: vsi fw index
 519  * @key: pointer to key info struct
 520  * @set: set true to set the key, false to get the key
 521  *
 522  * get the RSS key per VSI
 523  **/
 524 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 525                                       u16 vsi_id,
 526                                       struct i40e_aqc_get_set_rss_key_data *key,
 527                                       bool set)
 528 {
 529         enum i40e_status_code status;
 530         struct i40e_aq_desc desc;
 531         struct i40e_aqc_get_set_rss_key *cmd_resp =
 532                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 533         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 534
 535         if (set)
 536                 i40e_fill_default_direct_cmd_desc(&desc,
 537                                                   i40e_aqc_opc_set_rss_key);
 538         else
 539                 i40e_fill_default_direct_cmd_desc(&desc,
 540                                                   i40e_aqc_opc_get_rss_key);
 541
 542         /* Indirect command */
 543         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 544         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 545
 546         cmd_resp->vsi_id =
 547                         CPU_TO_LE16((u16)((vsi_id <<
 548                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 549                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 550         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 551
 552         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 553
 554         return status;
 555 }
 556
 557 /**
 558  * i40e_aq_get_rss_key
 559  * @hw: pointer to the hw struct
 560  * @vsi_id: vsi fw index
 561  * @key: pointer to key info struct
 562  *
 563  **/
 564 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 565                                       u16 vsi_id,
 566                                       struct i40e_aqc_get_set_rss_key_data *key)
 567 {
 568         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 569 }
 570
 571 /**
 572  * i40e_aq_set_rss_key
 573  * @hw: pointer to the hw struct
 574  * @vsi_id: vsi fw index
 575  * @key: pointer to key info struct
 576  *
 577  * set the RSS key per VSI
 578  **/
 579 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 580                                       u16 vsi_id,
 581                                       struct i40e_aqc_get_set_rss_key_data *key)
 582 {
 583         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 584 }
 585
 586 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 587  * hardware to a bit-field that can be used by SW to more easily determine the
 588  * packet type.
 589  *
 590  * Macros are used to shorten the table lines and make this table human
 591  * readable.
 592  *
 593  * We store the PTYPE in the top byte of the bit field - this is just so that
 594  * we can check that the table doesn't have a row missing, as the index into
 595  * the table should be the PTYPE.
 596  *
 597  * Typical work flow:
 598  *
 599  * IF NOT i40e_ptype_lookup[ptype].known
 600  * THEN
 601  *      Packet is unknown
 602  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 603  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 604  * ELSE
 605  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 606  * ENDIF
 607  */
 608
 609 /* macro to make the table lines short */
 610 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 611         {       PTYPE, \
 612                 1, \
 613                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 614                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 615                 I40E_RX_PTYPE_##OUTER_FRAG, \
 616                 I40E_RX_PTYPE_TUNNEL_##T, \
 617                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 618                 I40E_RX_PTYPE_##TEF, \
 619                 I40E_RX_PTYPE_INNER_PROT_##I, \
 620                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 621
 622 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 623                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 624
 625 /* shorter macros makes the table fit but are terse */
 626 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 627 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 628 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 629
 630 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 631 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 632         /* L2 Packet types */
 633         I40E_PTT_UNUSED_ENTRY(0),
 634         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 635         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 636         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 637         I40E_PTT_UNUSED_ENTRY(4),
 638         I40E_PTT_UNUSED_ENTRY(5),
 639         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 640         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 641         I40E_PTT_UNUSED_ENTRY(8),
 642         I40E_PTT_UNUSED_ENTRY(9),
 643         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 644         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 645         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 651         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 652         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 653         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 654         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 655
 656         /* Non Tunneled IPv4 */
 657         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 658         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 659         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 660         I40E_PTT_UNUSED_ENTRY(25),
 661         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 662         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 663         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 664
 665         /* IPv4 --> IPv4 */
 666         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 667         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 668         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 669         I40E_PTT_UNUSED_ENTRY(32),
 670         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 671         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 672         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 673
 674         /* IPv4 --> IPv6 */
 675         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 676         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 677         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 678         I40E_PTT_UNUSED_ENTRY(39),
 679         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 680         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 681         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 682
 683         /* IPv4 --> GRE/NAT */
 684         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 685
 686         /* IPv4 --> GRE/NAT --> IPv4 */
 687         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 688         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 689         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(47),
 691         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 692         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 693         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> GRE/NAT --> IPv6 */
 696         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 697         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 698         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 699         I40E_PTT_UNUSED_ENTRY(54),
 700         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 701         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 702         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 703
 704         /* IPv4 --> GRE/NAT --> MAC */
 705         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 706
 707         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 708         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 709         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 710         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(62),
 712         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 713         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 714         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 717         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 718         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 719         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 720         I40E_PTT_UNUSED_ENTRY(69),
 721         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 722         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 723         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 724
 725         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 726         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 727
 728         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 729         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 730         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 731         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(77),
 733         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 734         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 735         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 736
 737         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 738         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 739         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 740         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(84),
 742         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 743         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 744         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 745
 746         /* Non Tunneled IPv6 */
 747         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 748         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 749         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 750         I40E_PTT_UNUSED_ENTRY(91),
 751         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 752         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 753         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 754
 755         /* IPv6 --> IPv4 */
 756         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 757         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 758         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 759         I40E_PTT_UNUSED_ENTRY(98),
 760         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 761         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 762         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 763
 764         /* IPv6 --> IPv6 */
 765         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 766         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 767         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 768         I40E_PTT_UNUSED_ENTRY(105),
 769         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 770         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 771         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 772
 773         /* IPv6 --> GRE/NAT */
 774         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 775
 776         /* IPv6 --> GRE/NAT -> IPv4 */
 777         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 778         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 779         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(113),
 781         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 782         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 783         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> GRE/NAT -> IPv6 */
 786         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 787         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 788         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 789         I40E_PTT_UNUSED_ENTRY(120),
 790         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 791         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 792         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 793
 794         /* IPv6 --> GRE/NAT -> MAC */
 795         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 796
 797         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 798         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 799         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 800         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(128),
 802         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 803         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 804         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 807         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 808         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 809         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 810         I40E_PTT_UNUSED_ENTRY(135),
 811         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 812         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 813         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 814
 815         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 816         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 817
 818         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 819         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 820         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 821         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(143),
 823         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 824         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 825         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 826
 827         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 828         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 829         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 830         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 831         I40E_PTT_UNUSED_ENTRY(150),
 832         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 833         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 834         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 835
 836         /* unused entries */
 837         I40E_PTT_UNUSED_ENTRY(154),
 838         I40E_PTT_UNUSED_ENTRY(155),
 839         I40E_PTT_UNUSED_ENTRY(156),
 840         I40E_PTT_UNUSED_ENTRY(157),
 841         I40E_PTT_UNUSED_ENTRY(158),
 842         I40E_PTT_UNUSED_ENTRY(159),
 843
 844         I40E_PTT_UNUSED_ENTRY(160),
 845         I40E_PTT_UNUSED_ENTRY(161),
 846         I40E_PTT_UNUSED_ENTRY(162),
 847         I40E_PTT_UNUSED_ENTRY(163),
 848         I40E_PTT_UNUSED_ENTRY(164),
 849         I40E_PTT_UNUSED_ENTRY(165),
 850         I40E_PTT_UNUSED_ENTRY(166),
 851         I40E_PTT_UNUSED_ENTRY(167),
 852         I40E_PTT_UNUSED_ENTRY(168),
 853         I40E_PTT_UNUSED_ENTRY(169),
 854
 855         I40E_PTT_UNUSED_ENTRY(170),
 856         I40E_PTT_UNUSED_ENTRY(171),
 857         I40E_PTT_UNUSED_ENTRY(172),
 858         I40E_PTT_UNUSED_ENTRY(173),
 859         I40E_PTT_UNUSED_ENTRY(174),
 860         I40E_PTT_UNUSED_ENTRY(175),
 861         I40E_PTT_UNUSED_ENTRY(176),
 862         I40E_PTT_UNUSED_ENTRY(177),
 863         I40E_PTT_UNUSED_ENTRY(178),
 864         I40E_PTT_UNUSED_ENTRY(179),
 865
 866         I40E_PTT_UNUSED_ENTRY(180),
 867         I40E_PTT_UNUSED_ENTRY(181),
 868         I40E_PTT_UNUSED_ENTRY(182),
 869         I40E_PTT_UNUSED_ENTRY(183),
 870         I40E_PTT_UNUSED_ENTRY(184),
 871         I40E_PTT_UNUSED_ENTRY(185),
 872         I40E_PTT_UNUSED_ENTRY(186),
 873         I40E_PTT_UNUSED_ENTRY(187),
 874         I40E_PTT_UNUSED_ENTRY(188),
 875         I40E_PTT_UNUSED_ENTRY(189),
 876
 877         I40E_PTT_UNUSED_ENTRY(190),
 878         I40E_PTT_UNUSED_ENTRY(191),
 879         I40E_PTT_UNUSED_ENTRY(192),
 880         I40E_PTT_UNUSED_ENTRY(193),
 881         I40E_PTT_UNUSED_ENTRY(194),
 882         I40E_PTT_UNUSED_ENTRY(195),
 883         I40E_PTT_UNUSED_ENTRY(196),
 884         I40E_PTT_UNUSED_ENTRY(197),
 885         I40E_PTT_UNUSED_ENTRY(198),
 886         I40E_PTT_UNUSED_ENTRY(199),
 887
 888         I40E_PTT_UNUSED_ENTRY(200),
 889         I40E_PTT_UNUSED_ENTRY(201),
 890         I40E_PTT_UNUSED_ENTRY(202),
 891         I40E_PTT_UNUSED_ENTRY(203),
 892         I40E_PTT_UNUSED_ENTRY(204),
 893         I40E_PTT_UNUSED_ENTRY(205),
 894         I40E_PTT_UNUSED_ENTRY(206),
 895         I40E_PTT_UNUSED_ENTRY(207),
 896         I40E_PTT_UNUSED_ENTRY(208),
 897         I40E_PTT_UNUSED_ENTRY(209),
 898
 899         I40E_PTT_UNUSED_ENTRY(210),
 900         I40E_PTT_UNUSED_ENTRY(211),
 901         I40E_PTT_UNUSED_ENTRY(212),
 902         I40E_PTT_UNUSED_ENTRY(213),
 903         I40E_PTT_UNUSED_ENTRY(214),
 904         I40E_PTT_UNUSED_ENTRY(215),
 905         I40E_PTT_UNUSED_ENTRY(216),
 906         I40E_PTT_UNUSED_ENTRY(217),
 907         I40E_PTT_UNUSED_ENTRY(218),
 908         I40E_PTT_UNUSED_ENTRY(219),
 909
 910         I40E_PTT_UNUSED_ENTRY(220),
 911         I40E_PTT_UNUSED_ENTRY(221),
 912         I40E_PTT_UNUSED_ENTRY(222),
 913         I40E_PTT_UNUSED_ENTRY(223),
 914         I40E_PTT_UNUSED_ENTRY(224),
 915         I40E_PTT_UNUSED_ENTRY(225),
 916         I40E_PTT_UNUSED_ENTRY(226),
 917         I40E_PTT_UNUSED_ENTRY(227),
 918         I40E_PTT_UNUSED_ENTRY(228),
 919         I40E_PTT_UNUSED_ENTRY(229),
 920
 921         I40E_PTT_UNUSED_ENTRY(230),
 922         I40E_PTT_UNUSED_ENTRY(231),
 923         I40E_PTT_UNUSED_ENTRY(232),
 924         I40E_PTT_UNUSED_ENTRY(233),
 925         I40E_PTT_UNUSED_ENTRY(234),
 926         I40E_PTT_UNUSED_ENTRY(235),
 927         I40E_PTT_UNUSED_ENTRY(236),
 928         I40E_PTT_UNUSED_ENTRY(237),
 929         I40E_PTT_UNUSED_ENTRY(238),
 930         I40E_PTT_UNUSED_ENTRY(239),
 931
 932         I40E_PTT_UNUSED_ENTRY(240),
 933         I40E_PTT_UNUSED_ENTRY(241),
 934         I40E_PTT_UNUSED_ENTRY(242),
 935         I40E_PTT_UNUSED_ENTRY(243),
 936         I40E_PTT_UNUSED_ENTRY(244),
 937         I40E_PTT_UNUSED_ENTRY(245),
 938         I40E_PTT_UNUSED_ENTRY(246),
 939         I40E_PTT_UNUSED_ENTRY(247),
 940         I40E_PTT_UNUSED_ENTRY(248),
 941         I40E_PTT_UNUSED_ENTRY(249),
 942
 943         I40E_PTT_UNUSED_ENTRY(250),
 944         I40E_PTT_UNUSED_ENTRY(251),
 945         I40E_PTT_UNUSED_ENTRY(252),
 946         I40E_PTT_UNUSED_ENTRY(253),
 947         I40E_PTT_UNUSED_ENTRY(254),
 948         I40E_PTT_UNUSED_ENTRY(255)
 949 };
 950
 951
 952 /**
 953  * i40e_validate_mac_addr - Validate unicast MAC address
 954  * @mac_addr: pointer to MAC address
 955  *
 956  * Tests a MAC address to ensure it is a valid Individual Address
 957  **/
 958 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 959 {
 960         enum i40e_status_code status = I40E_SUCCESS;
 961
 962         DEBUGFUNC("i40e_validate_mac_addr");
 963
 964         /* Broadcast addresses ARE multicast addresses
 965          * Make sure it is not a multicast address
 966          * Reject the zero address
 967          */
 968         if (I40E_IS_MULTICAST(mac_addr) ||
 969             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 970               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 971                 status = I40E_ERR_INVALID_MAC_ADDR;
 972
 973         return status;
 974 }
 975 #ifdef PF_DRIVER
 976
 977 /**
 978  * i40e_init_shared_code - Initialize the shared code
 979  * @hw: pointer to hardware structure
 980  *
 981  * This assigns the MAC type and PHY code and inits the NVM.
 982  * Does not touch the hardware. This function must be called prior to any
 983  * other function in the shared code. The i40e_hw structure should be
 984  * memset to 0 prior to calling this function.  The following fields in
 985  * hw structure should be filled in prior to calling this function:
 986  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 987  * subsystem_vendor_id, and revision_id
 988  **/
 989 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 990 {
 991         enum i40e_status_code status = I40E_SUCCESS;
 992         u32 port, ari, func_rid;
 993
 994         DEBUGFUNC("i40e_init_shared_code");
 995
 996         i40e_set_mac_type(hw);
 997
 998         switch (hw->mac.type) {
 999         case I40E_MAC_XL710:
1000         case I40E_MAC_X722:
1001                 break;
1002         default:
1003                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1004         }
1005
1006         hw->phy.get_link_info = true;
1007
1008         /* Determine port number and PF number*/
1009         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1010                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1011         hw->port = (u8)port;
1012         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1013                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1014         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1015         if (ari)
1016                 hw->pf_id = (u8)(func_rid & 0xff);
1017         else
1018                 hw->pf_id = (u8)(func_rid & 0x7);
1019
1020         if (hw->mac.type == I40E_MAC_X722)
1021                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1022                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1023         /* NVMUpdate features structure initialization */
1024         hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1025         hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1026         hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1027         i40e_memset(hw->nvmupd_features.features, 0x0,
1028                     I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1029                     sizeof(*hw->nvmupd_features.features),
1030                     I40E_NONDMA_MEM);
1031
1032         /* No features supported at the moment */
1033         hw->nvmupd_features.features[0] = 0;
1034
1035         status = i40e_init_nvm(hw);
1036         return status;
1037 }
1038
1039 /**
1040  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1041  * @hw: pointer to the hw struct
1042  * @flags: a return indicator of what addresses were added to the addr store
1043  * @addrs: the requestor's mac addr store
1044  * @cmd_details: pointer to command details structure or NULL
1045  **/
1046 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1047                                    u16 *flags,
1048                                    struct i40e_aqc_mac_address_read_data *addrs,
1049                                    struct i40e_asq_cmd_details *cmd_details)
1050 {
1051         struct i40e_aq_desc desc;
1052         struct i40e_aqc_mac_address_read *cmd_data =
1053                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1054         enum i40e_status_code status;
1055
1056         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1057         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1058
1059         status = i40e_asq_send_command(hw, &desc, addrs,
1060                                        sizeof(*addrs), cmd_details);
1061         *flags = LE16_TO_CPU(cmd_data->command_flags);
1062
1063         return status;
1064 }
1065
1066 /**
1067  * i40e_aq_mac_address_write - Change the MAC addresses
1068  * @hw: pointer to the hw struct
1069  * @flags: indicates which MAC to be written
1070  * @mac_addr: address to write
1071  * @cmd_details: pointer to command details structure or NULL
1072  **/
1073 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1074                                     u16 flags, u8 *mac_addr,
1075                                     struct i40e_asq_cmd_details *cmd_details)
1076 {
1077         struct i40e_aq_desc desc;
1078         struct i40e_aqc_mac_address_write *cmd_data =
1079                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1080         enum i40e_status_code status;
1081
1082         i40e_fill_default_direct_cmd_desc(&desc,
1083                                           i40e_aqc_opc_mac_address_write);
1084         cmd_data->command_flags = CPU_TO_LE16(flags);
1085         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1086         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1087                                         ((u32)mac_addr[3] << 16) |
1088                                         ((u32)mac_addr[4] << 8) |
1089                                         mac_addr[5]);
1090
1091         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1092
1093         return status;
1094 }
1095
1096 /**
1097  * i40e_get_mac_addr - get MAC address
1098  * @hw: pointer to the HW structure
1099  * @mac_addr: pointer to MAC address
1100  *
1101  * Reads the adapter's MAC address from register
1102  **/
1103 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1104 {
1105         struct i40e_aqc_mac_address_read_data addrs;
1106         enum i40e_status_code status;
1107         u16 flags = 0;
1108
1109         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1110
1111         if (flags & I40E_AQC_LAN_ADDR_VALID)
1112                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1113                         I40E_NONDMA_TO_NONDMA);
1114
1115         return status;
1116 }
1117
1118 /**
1119  * i40e_get_port_mac_addr - get Port MAC address
1120  * @hw: pointer to the HW structure
1121  * @mac_addr: pointer to Port MAC address
1122  *
1123  * Reads the adapter's Port MAC address
1124  **/
1125 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1126 {
1127         struct i40e_aqc_mac_address_read_data addrs;
1128         enum i40e_status_code status;
1129         u16 flags = 0;
1130
1131         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1132         if (status)
1133                 return status;
1134
1135         if (flags & I40E_AQC_PORT_ADDR_VALID)
1136                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1137                         I40E_NONDMA_TO_NONDMA);
1138         else
1139                 status = I40E_ERR_INVALID_MAC_ADDR;
1140
1141         return status;
1142 }
1143
1144 /**
1145  * i40e_pre_tx_queue_cfg - pre tx queue configure
1146  * @hw: pointer to the HW structure
1147  * @queue: target pf queue index
1148  * @enable: state change request
1149  *
1150  * Handles hw requirement to indicate intention to enable
1151  * or disable target queue.
1152  **/
1153 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1154 {
1155         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1156         u32 reg_block = 0;
1157         u32 reg_val;
1158
1159         if (abs_queue_idx >= 128) {
1160                 reg_block = abs_queue_idx / 128;
1161                 abs_queue_idx %= 128;
1162         }
1163
1164         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1165         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1166         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1167
1168         if (enable)
1169                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1170         else
1171                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1172
1173         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1174 }
1175
1176 /**
1177  * i40e_get_san_mac_addr - get SAN MAC address
1178  * @hw: pointer to the HW structure
1179  * @mac_addr: pointer to SAN MAC address
1180  *
1181  * Reads the adapter's SAN MAC address from NVM
1182  **/
1183 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1184                                             u8 *mac_addr)
1185 {
1186         struct i40e_aqc_mac_address_read_data addrs;
1187         enum i40e_status_code status;
1188         u16 flags = 0;
1189
1190         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1191         if (status)
1192                 return status;
1193
1194         if (flags & I40E_AQC_SAN_ADDR_VALID)
1195                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1196                         I40E_NONDMA_TO_NONDMA);
1197         else
1198                 status = I40E_ERR_INVALID_MAC_ADDR;
1199
1200         return status;
1201 }
1202
1203 /**
1204  *  i40e_read_pba_string - Reads part number string from EEPROM
1205  *  @hw: pointer to hardware structure
1206  *  @pba_num: stores the part number string from the EEPROM
1207  *  @pba_num_size: part number string buffer length
1208  *
1209  *  Reads the part number string from the EEPROM.
1210  **/
1211 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1212                                             u32 pba_num_size)
1213 {
1214         enum i40e_status_code status = I40E_SUCCESS;
1215         u16 pba_word = 0;
1216         u16 pba_size = 0;
1217         u16 pba_ptr = 0;
1218         u16 i = 0;
1219
1220         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1221         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1222                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1223                 return status;
1224         }
1225
1226         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1227         if (status != I40E_SUCCESS) {
1228                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1229                 return status;
1230         }
1231
1232         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1233         if (status != I40E_SUCCESS) {
1234                 DEBUGOUT("Failed to read PBA Block size.\n");
1235                 return status;
1236         }
1237
1238         /* Subtract one to get PBA word count (PBA Size word is included in
1239          * total size)
1240          */
1241         pba_size--;
1242         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1243                 DEBUGOUT("Buffer to small for PBA data.\n");
1244                 return I40E_ERR_PARAM;
1245         }
1246
1247         for (i = 0; i < pba_size; i++) {
1248                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1249                 if (status != I40E_SUCCESS) {
1250                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1251                         return status;
1252                 }
1253
1254                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1255                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1256         }
1257         pba_num[(pba_size * 2)] = '\0';
1258
1259         return status;
1260 }
1261
1262 /**
1263  * i40e_get_media_type - Gets media type
1264  * @hw: pointer to the hardware structure
1265  **/
1266 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1267 {
1268         enum i40e_media_type media;
1269
1270         switch (hw->phy.link_info.phy_type) {
1271         case I40E_PHY_TYPE_10GBASE_SR:
1272         case I40E_PHY_TYPE_10GBASE_LR:
1273         case I40E_PHY_TYPE_1000BASE_SX:
1274         case I40E_PHY_TYPE_1000BASE_LX:
1275         case I40E_PHY_TYPE_40GBASE_SR4:
1276         case I40E_PHY_TYPE_40GBASE_LR4:
1277         case I40E_PHY_TYPE_25GBASE_LR:
1278         case I40E_PHY_TYPE_25GBASE_SR:
1279                 media = I40E_MEDIA_TYPE_FIBER;
1280                 break;
1281         case I40E_PHY_TYPE_100BASE_TX:
1282         case I40E_PHY_TYPE_1000BASE_T:
1283         case I40E_PHY_TYPE_2_5GBASE_T:
1284         case I40E_PHY_TYPE_5GBASE_T:
1285         case I40E_PHY_TYPE_10GBASE_T:
1286                 media = I40E_MEDIA_TYPE_BASET;
1287                 break;
1288         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1289         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1290         case I40E_PHY_TYPE_10GBASE_CR1:
1291         case I40E_PHY_TYPE_40GBASE_CR4:
1292         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1293         case I40E_PHY_TYPE_40GBASE_AOC:
1294         case I40E_PHY_TYPE_10GBASE_AOC:
1295         case I40E_PHY_TYPE_25GBASE_CR:
1296         case I40E_PHY_TYPE_25GBASE_AOC:
1297         case I40E_PHY_TYPE_25GBASE_ACC:
1298                 media = I40E_MEDIA_TYPE_DA;
1299                 break;
1300         case I40E_PHY_TYPE_1000BASE_KX:
1301         case I40E_PHY_TYPE_10GBASE_KX4:
1302         case I40E_PHY_TYPE_10GBASE_KR:
1303         case I40E_PHY_TYPE_40GBASE_KR4:
1304         case I40E_PHY_TYPE_20GBASE_KR2:
1305         case I40E_PHY_TYPE_25GBASE_KR:
1306                 media = I40E_MEDIA_TYPE_BACKPLANE;
1307                 break;
1308         case I40E_PHY_TYPE_SGMII:
1309         case I40E_PHY_TYPE_XAUI:
1310         case I40E_PHY_TYPE_XFI:
1311         case I40E_PHY_TYPE_XLAUI:
1312         case I40E_PHY_TYPE_XLPPI:
1313         default:
1314                 media = I40E_MEDIA_TYPE_UNKNOWN;
1315                 break;
1316         }
1317
1318         return media;
1319 }
1320
1321 /**
1322  * i40e_poll_globr - Poll for Global Reset completion
1323  * @hw: pointer to the hardware structure
1324  * @retry_limit: how many times to retry before failure
1325  **/
1326 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1327                                              u32 retry_limit)
1328 {
1329         u32 cnt, reg = 0;
1330
1331         for (cnt = 0; cnt < retry_limit; cnt++) {
1332                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1333                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1334                         return I40E_SUCCESS;
1335                 i40e_msec_delay(100);
1336         }
1337
1338         DEBUGOUT("Global reset failed.\n");
1339         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1340
1341         return I40E_ERR_RESET_FAILED;
1342 }
1343
1344 #define I40E_PF_RESET_WAIT_COUNT        200
1345 /**
1346  * i40e_pf_reset - Reset the PF
1347  * @hw: pointer to the hardware structure
1348  *
1349  * Assuming someone else has triggered a global reset,
1350  * assure the global reset is complete and then reset the PF
1351  **/
1352 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1353 {
1354         u32 cnt = 0;
1355         u32 cnt1 = 0;
1356         u32 reg = 0;
1357         u32 grst_del;
1358
1359         /* Poll for Global Reset steady state in case of recent GRST.
1360          * The grst delay value is in 100ms units, and we'll wait a
1361          * couple counts longer to be sure we don't just miss the end.
1362          */
1363         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1364                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1365                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1366
1367         grst_del = min(grst_del * 20, 160U);
1368
1369         for (cnt = 0; cnt < grst_del; cnt++) {
1370                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1371                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1372                         break;
1373                 i40e_msec_delay(100);
1374         }
1375         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1376                 DEBUGOUT("Global reset polling failed to complete.\n");
1377                 return I40E_ERR_RESET_FAILED;
1378         }
1379
1380         /* Now Wait for the FW to be ready */
1381         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1382                 reg = rd32(hw, I40E_GLNVM_ULD);
1383                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1384                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1385                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1386                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1387                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1388                         break;
1389                 }
1390                 i40e_msec_delay(10);
1391         }
1392         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1393                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1394                 DEBUGOUT("wait for FW Reset complete timedout\n");
1395                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1396                 return I40E_ERR_RESET_FAILED;
1397         }
1398
1399         /* If there was a Global Reset in progress when we got here,
1400          * we don't need to do the PF Reset
1401          */
1402         if (!cnt) {
1403                 u32 reg2 = 0;
1404
1405                 reg = rd32(hw, I40E_PFGEN_CTRL);
1406                 wr32(hw, I40E_PFGEN_CTRL,
1407                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1408                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1409                         reg = rd32(hw, I40E_PFGEN_CTRL);
1410                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1411                                 break;
1412                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1413                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1414                                 break;
1415                         i40e_msec_delay(1);
1416                 }
1417                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1418                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1419                                 return I40E_ERR_RESET_FAILED;
1420                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1421                         DEBUGOUT("PF reset polling failed to complete.\n");
1422                         return I40E_ERR_RESET_FAILED;
1423                 }
1424         }
1425
1426         i40e_clear_pxe_mode(hw);
1427
1428
1429         return I40E_SUCCESS;
1430 }
1431
1432 /**
1433  * i40e_clear_hw - clear out any left over hw state
1434  * @hw: pointer to the hw struct
1435  *
1436  * Clear queues and interrupts, typically called at init time,
1437  * but after the capabilities have been found so we know how many
1438  * queues and msix vectors have been allocated.
1439  **/
1440 void i40e_clear_hw(struct i40e_hw *hw)
1441 {
1442         u32 num_queues, base_queue;
1443         u32 num_pf_int;
1444         u32 num_vf_int;
1445         u32 num_vfs;
1446         u32 i, j;
1447         u32 val;
1448         u32 eol = 0x7ff;
1449
1450         /* get number of interrupts, queues, and vfs */
1451         val = rd32(hw, I40E_GLPCI_CNF2);
1452         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1453                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1454         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1455                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1456
1457         val = rd32(hw, I40E_PFLAN_QALLOC);
1458         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1459                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1460         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1461                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1462         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1463                 num_queues = (j - base_queue) + 1;
1464         else
1465                 num_queues = 0;
1466
1467         val = rd32(hw, I40E_PF_VT_PFALLOC);
1468         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1469                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1470         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1471                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1472         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1473                 num_vfs = (j - i) + 1;
1474         else
1475                 num_vfs = 0;
1476
1477         /* stop all the interrupts */
1478         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1479         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1480         for (i = 0; i < num_pf_int - 2; i++)
1481                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1482
1483         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1484         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1485         wr32(hw, I40E_PFINT_LNKLST0, val);
1486         for (i = 0; i < num_pf_int - 2; i++)
1487                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1488         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1489         for (i = 0; i < num_vfs; i++)
1490                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1491         for (i = 0; i < num_vf_int - 2; i++)
1492                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1493
1494         /* warn the HW of the coming Tx disables */
1495         for (i = 0; i < num_queues; i++) {
1496                 u32 abs_queue_idx = base_queue + i;
1497                 u32 reg_block = 0;
1498
1499                 if (abs_queue_idx >= 128) {
1500                         reg_block = abs_queue_idx / 128;
1501                         abs_queue_idx %= 128;
1502                 }
1503
1504                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1505                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1506                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1507                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1508
1509                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1510         }
1511         i40e_usec_delay(400);
1512
1513         /* stop all the queues */
1514         for (i = 0; i < num_queues; i++) {
1515                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1516                 wr32(hw, I40E_QTX_ENA(i), 0);
1517                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1518                 wr32(hw, I40E_QRX_ENA(i), 0);
1519         }
1520
1521         /* short wait for all queue disables to settle */
1522         i40e_usec_delay(50);
1523 }
1524
1525 /**
1526  * i40e_clear_pxe_mode - clear pxe operations mode
1527  * @hw: pointer to the hw struct
1528  *
1529  * Make sure all PXE mode settings are cleared, including things
1530  * like descriptor fetch/write-back mode.
1531  **/
1532 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1533 {
1534         if (i40e_check_asq_alive(hw))
1535                 i40e_aq_clear_pxe_mode(hw, NULL);
1536 }
1537
1538 /**
1539  * i40e_led_is_mine - helper to find matching led
1540  * @hw: pointer to the hw struct
1541  * @idx: index into GPIO registers
1542  *
1543  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1544  */
1545 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1546 {
1547         u32 gpio_val = 0;
1548         u32 port;
1549
1550         if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1551             !hw->func_caps.led[idx])
1552                 return 0;
1553         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1554         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1555                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1556
1557         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1558          * if it is not our port then ignore
1559          */
1560         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1561             (port != hw->port))
1562                 return 0;
1563
1564         return gpio_val;
1565 }
1566
1567 #define I40E_COMBINED_ACTIVITY 0xA
1568 #define I40E_FILTER_ACTIVITY 0xE
1569 #define I40E_LINK_ACTIVITY 0xC
1570 #define I40E_MAC_ACTIVITY 0xD
1571 #define I40E_FW_LED BIT(4)
1572 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1573                              I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1574
1575 #define I40E_LED0 22
1576
1577 #define I40E_PIN_FUNC_SDP 0x0
1578 #define I40E_PIN_FUNC_LED 0x1
1579
1580 /**
1581  * i40e_led_get - return current on/off mode
1582  * @hw: pointer to the hw struct
1583  *
1584  * The value returned is the 'mode' field as defined in the
1585  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1586  * values are variations of possible behaviors relating to
1587  * blink, link, and wire.
1588  **/
1589 u32 i40e_led_get(struct i40e_hw *hw)
1590 {
1591         u32 current_mode = 0;
1592         u32 mode = 0;
1593         int i;
1594
1595         /* as per the documentation GPIO 22-29 are the LED
1596          * GPIO pins named LED0..LED7
1597          */
1598         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1599                 u32 gpio_val = i40e_led_is_mine(hw, i);
1600
1601                 if (!gpio_val)
1602                         continue;
1603
1604                 /* ignore gpio LED src mode entries related to the activity
1605                  *  LEDs
1606                  */
1607                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1608                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1609                 switch (current_mode) {
1610                 case I40E_COMBINED_ACTIVITY:
1611                 case I40E_FILTER_ACTIVITY:
1612                 case I40E_MAC_ACTIVITY:
1613                 case I40E_LINK_ACTIVITY:
1614                         continue;
1615                 default:
1616                         break;
1617                 }
1618
1619                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1620                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1621                 break;
1622         }
1623
1624         return mode;
1625 }
1626
1627 /**
1628  * i40e_led_set - set new on/off mode
1629  * @hw: pointer to the hw struct
1630  * @mode: 0=off, 0xf=on (else see manual for mode details)
1631  * @blink: true if the LED should blink when on, false if steady
1632  *
1633  * if this function is used to turn on the blink it should
1634  * be used to disable the blink when restoring the original state.
1635  **/
1636 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1637 {
1638         u32 current_mode = 0;
1639         int i;
1640
1641         if (mode & ~I40E_LED_MODE_VALID) {
1642                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1643                 return;
1644         }
1645
1646         /* as per the documentation GPIO 22-29 are the LED
1647          * GPIO pins named LED0..LED7
1648          */
1649         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1650                 u32 gpio_val = i40e_led_is_mine(hw, i);
1651
1652                 if (!gpio_val)
1653                         continue;
1654
1655                 /* ignore gpio LED src mode entries related to the activity
1656                  * LEDs
1657                  */
1658                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1659                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1660                 switch (current_mode) {
1661                 case I40E_COMBINED_ACTIVITY:
1662                 case I40E_FILTER_ACTIVITY:
1663                 case I40E_MAC_ACTIVITY:
1664                 case I40E_LINK_ACTIVITY:
1665                         continue;
1666                 default:
1667                         break;
1668                 }
1669
1670                 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1671                         u32 pin_func = 0;
1672
1673                         if (mode & I40E_FW_LED)
1674                                 pin_func = I40E_PIN_FUNC_SDP;
1675                         else
1676                                 pin_func = I40E_PIN_FUNC_LED;
1677
1678                         gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1679                         gpio_val |= ((pin_func <<
1680                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1681                                      I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1682                 }
1683                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1684                 /* this & is a bit of paranoia, but serves as a range check */
1685                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1686                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1687
1688                 if (blink)
1689                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1690                 else
1691                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1692
1693                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1694                 break;
1695         }
1696 }
1697
1698 /* Admin command wrappers */
1699
1700 /**
1701  * i40e_aq_get_phy_capabilities
1702  * @hw: pointer to the hw struct
1703  * @abilities: structure for PHY capabilities to be filled
1704  * @qualified_modules: report Qualified Modules
1705  * @report_init: report init capabilities (active are default)
1706  * @cmd_details: pointer to command details structure or NULL
1707  *
1708  * Returns the various PHY abilities supported on the Port.
1709  **/
1710 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1711                         bool qualified_modules, bool report_init,
1712                         struct i40e_aq_get_phy_abilities_resp *abilities,
1713                         struct i40e_asq_cmd_details *cmd_details)
1714 {
1715         struct i40e_aq_desc desc;
1716         enum i40e_status_code status;
1717         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1718         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1719
1720         if (!abilities)
1721                 return I40E_ERR_PARAM;
1722
1723         do {
1724                 i40e_fill_default_direct_cmd_desc(&desc,
1725                                                i40e_aqc_opc_get_phy_abilities);
1726
1727                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1728                 if (abilities_size > I40E_AQ_LARGE_BUF)
1729                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1730
1731                 if (qualified_modules)
1732                         desc.params.external.param0 |=
1733                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1734
1735                 if (report_init)
1736                         desc.params.external.param0 |=
1737                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1738
1739                 status = i40e_asq_send_command(hw, &desc, abilities,
1740                                                abilities_size, cmd_details);
1741
1742                 switch (hw->aq.asq_last_status) {
1743                 case I40E_AQ_RC_EIO:
1744                         status = I40E_ERR_UNKNOWN_PHY;
1745                         break;
1746                 case I40E_AQ_RC_EAGAIN:
1747                         i40e_msec_delay(1);
1748                         total_delay++;
1749                         status = I40E_ERR_TIMEOUT;
1750                         break;
1751                 /* also covers I40E_AQ_RC_OK */
1752                 default:
1753                         break;
1754                 }
1755
1756         } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1757                 (total_delay < max_delay));
1758
1759         if (status != I40E_SUCCESS)
1760                 return status;
1761
1762         if (report_init) {
1763                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1764                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1765                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1766                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1767                 } else {
1768                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1769                         hw->phy.phy_types |=
1770                                         ((u64)abilities->phy_type_ext << 32);
1771                 }
1772         }
1773
1774         return status;
1775 }
1776
1777 /**
1778  * i40e_aq_set_phy_config
1779  * @hw: pointer to the hw struct
1780  * @config: structure with PHY configuration to be set
1781  * @cmd_details: pointer to command details structure or NULL
1782  *
1783  * Set the various PHY configuration parameters
1784  * supported on the Port.One or more of the Set PHY config parameters may be
1785  * ignored in an MFP mode as the PF may not have the privilege to set some
1786  * of the PHY Config parameters. This status will be indicated by the
1787  * command response.
1788  **/
1789 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1790                                 struct i40e_aq_set_phy_config *config,
1791                                 struct i40e_asq_cmd_details *cmd_details)
1792 {
1793         struct i40e_aq_desc desc;
1794         struct i40e_aq_set_phy_config *cmd =
1795                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1796         enum i40e_status_code status;
1797
1798         if (!config)
1799                 return I40E_ERR_PARAM;
1800
1801         i40e_fill_default_direct_cmd_desc(&desc,
1802                                           i40e_aqc_opc_set_phy_config);
1803
1804         *cmd = *config;
1805
1806         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1807
1808         return status;
1809 }
1810
1811 /**
1812  * i40e_set_fc
1813  * @hw: pointer to the hw struct
1814  * @aq_failures: buffer to return AdminQ failure information
1815  * @atomic_restart: whether to enable atomic link restart
1816  *
1817  * Set the requested flow control mode using set_phy_config.
1818  **/
1819 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1820                                   bool atomic_restart)
1821 {
1822         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1823         struct i40e_aq_get_phy_abilities_resp abilities;
1824         struct i40e_aq_set_phy_config config;
1825         enum i40e_status_code status;
1826         u8 pause_mask = 0x0;
1827
1828         *aq_failures = 0x0;
1829
1830         switch (fc_mode) {
1831         case I40E_FC_FULL:
1832                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1833                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1834                 break;
1835         case I40E_FC_RX_PAUSE:
1836                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1837                 break;
1838         case I40E_FC_TX_PAUSE:
1839                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1840                 break;
1841         default:
1842                 break;
1843         }
1844
1845         /* Get the current phy config */
1846         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1847                                               NULL);
1848         if (status) {
1849                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1850                 return status;
1851         }
1852
1853         memset(&config, 0, sizeof(config));
1854         /* clear the old pause settings */
1855         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1856                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1857         /* set the new abilities */
1858         config.abilities |= pause_mask;
1859         /* If the abilities have changed, then set the new config */
1860         if (config.abilities != abilities.abilities) {
1861                 /* Auto restart link so settings take effect */
1862                 if (atomic_restart)
1863                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1864                 /* Copy over all the old settings */
1865                 config.phy_type = abilities.phy_type;
1866                 config.phy_type_ext = abilities.phy_type_ext;
1867                 config.link_speed = abilities.link_speed;
1868                 config.eee_capability = abilities.eee_capability;
1869                 config.eeer = abilities.eeer_val;
1870                 config.low_power_ctrl = abilities.d3_lpan;
1871                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1872                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1873                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1874
1875                 if (status)
1876                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1877         }
1878         /* Update the link info */
1879         status = i40e_update_link_info(hw);
1880         if (status) {
1881                 /* Wait a little bit (on 40G cards it sometimes takes a really
1882                  * long time for link to come back from the atomic reset)
1883                  * and try once more
1884                  */
1885                 i40e_msec_delay(1000);
1886                 status = i40e_update_link_info(hw);
1887         }
1888         if (status)
1889                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1890
1891         return status;
1892 }
1893
1894 /**
1895  * i40e_aq_set_mac_config
1896  * @hw: pointer to the hw struct
1897  * @max_frame_size: Maximum Frame Size to be supported by the port
1898  * @crc_en: Tell HW to append a CRC to outgoing frames
1899  * @pacing: Pacing configurations
1900  * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1901  * @cmd_details: pointer to command details structure or NULL
1902  *
1903  * Configure MAC settings for frame size, jumbo frame support and the
1904  * addition of a CRC by the hardware.
1905  **/
1906 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1907                                 u16 max_frame_size,
1908                                 bool crc_en, u16 pacing,
1909                                 bool auto_drop_blocking_packets,
1910                                 struct i40e_asq_cmd_details *cmd_details)
1911 {
1912         struct i40e_aq_desc desc;
1913         struct i40e_aq_set_mac_config *cmd =
1914                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1915         enum i40e_status_code status;
1916
1917         if (max_frame_size == 0)
1918                 return I40E_ERR_PARAM;
1919
1920         i40e_fill_default_direct_cmd_desc(&desc,
1921                                           i40e_aqc_opc_set_mac_config);
1922
1923         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1924         cmd->params = ((u8)pacing & 0x0F) << 3;
1925         if (crc_en)
1926                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1927
1928         if (auto_drop_blocking_packets) {
1929                 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1930                         cmd->params |=
1931                                 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1932                 else
1933                         i40e_debug(hw, I40E_DEBUG_ALL,
1934                                    "This FW api version does not support drop mode.\n");
1935         }
1936
1937 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1938         cmd->fc_refresh_threshold =
1939                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1940
1941         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1942
1943         return status;
1944 }
1945
1946 /**
1947  * i40e_aq_clear_pxe_mode
1948  * @hw: pointer to the hw struct
1949  * @cmd_details: pointer to command details structure or NULL
1950  *
1951  * Tell the firmware that the driver is taking over from PXE
1952  **/
1953 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1954                         struct i40e_asq_cmd_details *cmd_details)
1955 {
1956         enum i40e_status_code status;
1957         struct i40e_aq_desc desc;
1958         struct i40e_aqc_clear_pxe *cmd =
1959                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1960
1961         i40e_fill_default_direct_cmd_desc(&desc,
1962                                           i40e_aqc_opc_clear_pxe_mode);
1963
1964         cmd->rx_cnt = 0x2;
1965
1966         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1967
1968         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1969
1970         return status;
1971 }
1972
1973 /**
1974  * i40e_aq_set_link_restart_an
1975  * @hw: pointer to the hw struct
1976  * @enable_link: if true: enable link, if false: disable link
1977  * @cmd_details: pointer to command details structure or NULL
1978  *
1979  * Sets up the link and restarts the Auto-Negotiation over the link.
1980  **/
1981 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1982                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1983 {
1984         struct i40e_aq_desc desc;
1985         struct i40e_aqc_set_link_restart_an *cmd =
1986                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1987         enum i40e_status_code status;
1988
1989         i40e_fill_default_direct_cmd_desc(&desc,
1990                                           i40e_aqc_opc_set_link_restart_an);
1991
1992         cmd->command = I40E_AQ_PHY_RESTART_AN;
1993         if (enable_link)
1994                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1995         else
1996                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1997
1998         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1999
2000         return status;
2001 }
2002
2003 /**
2004  * i40e_aq_get_link_info
2005  * @hw: pointer to the hw struct
2006  * @enable_lse: enable/disable LinkStatusEvent reporting
2007  * @link: pointer to link status structure - optional
2008  * @cmd_details: pointer to command details structure or NULL
2009  *
2010  * Returns the link status of the adapter.
2011  **/
2012 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
2013                                 bool enable_lse, struct i40e_link_status *link,
2014                                 struct i40e_asq_cmd_details *cmd_details)
2015 {
2016         struct i40e_aq_desc desc;
2017         struct i40e_aqc_get_link_status *resp =
2018                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
2019         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
2020         enum i40e_status_code status;
2021         bool tx_pause, rx_pause;
2022         u16 command_flags;
2023
2024         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2025
2026         if (enable_lse)
2027                 command_flags = I40E_AQ_LSE_ENABLE;
2028         else
2029                 command_flags = I40E_AQ_LSE_DISABLE;
2030         resp->command_flags = CPU_TO_LE16(command_flags);
2031
2032         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2033
2034         if (status != I40E_SUCCESS)
2035                 goto aq_get_link_info_exit;
2036
2037         /* save off old link status information */
2038         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2039                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2040
2041         /* update link status */
2042         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2043         hw->phy.media_type = i40e_get_media_type(hw);
2044         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2045         hw_link_info->link_info = resp->link_info;
2046         hw_link_info->an_info = resp->an_info;
2047         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2048                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
2049         hw_link_info->ext_info = resp->ext_info;
2050         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2051         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2052         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2053
2054         /* update fc info */
2055         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2056         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2057         if (tx_pause & rx_pause)
2058                 hw->fc.current_mode = I40E_FC_FULL;
2059         else if (tx_pause)
2060                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2061         else if (rx_pause)
2062                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2063         else
2064                 hw->fc.current_mode = I40E_FC_NONE;
2065
2066         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2067                 hw_link_info->crc_enable = true;
2068         else
2069                 hw_link_info->crc_enable = false;
2070
2071         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2072                 hw_link_info->lse_enable = true;
2073         else
2074                 hw_link_info->lse_enable = false;
2075
2076         if ((hw->mac.type == I40E_MAC_XL710) &&
2077             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2078              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2079                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2080
2081         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2082             hw->mac.type != I40E_MAC_X722) {
2083                 __le32 tmp;
2084
2085                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2086                             I40E_NONDMA_TO_NONDMA);
2087                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2088                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2089         }
2090
2091         /* save link status information */
2092         if (link)
2093                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2094                             I40E_NONDMA_TO_NONDMA);
2095
2096         /* flag cleared so helper functions don't call AQ again */
2097         hw->phy.get_link_info = false;
2098
2099 aq_get_link_info_exit:
2100         return status;
2101 }
2102
2103 /**
2104  * i40e_aq_set_phy_int_mask
2105  * @hw: pointer to the hw struct
2106  * @mask: interrupt mask to be set
2107  * @cmd_details: pointer to command details structure or NULL
2108  *
2109  * Set link interrupt mask.
2110  **/
2111 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2112                                 u16 mask,
2113                                 struct i40e_asq_cmd_details *cmd_details)
2114 {
2115         struct i40e_aq_desc desc;
2116         struct i40e_aqc_set_phy_int_mask *cmd =
2117                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2118         enum i40e_status_code status;
2119
2120         i40e_fill_default_direct_cmd_desc(&desc,
2121                                           i40e_aqc_opc_set_phy_int_mask);
2122
2123         cmd->event_mask = CPU_TO_LE16(mask);
2124
2125         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2126
2127         return status;
2128 }
2129
2130 /**
2131  * i40e_aq_get_local_advt_reg
2132  * @hw: pointer to the hw struct
2133  * @advt_reg: local AN advertisement register value
2134  * @cmd_details: pointer to command details structure or NULL
2135  *
2136  * Get the Local AN advertisement register value.
2137  **/
2138 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2139                                 u64 *advt_reg,
2140                                 struct i40e_asq_cmd_details *cmd_details)
2141 {
2142         struct i40e_aq_desc desc;
2143         struct i40e_aqc_an_advt_reg *resp =
2144                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2145         enum i40e_status_code status;
2146
2147         i40e_fill_default_direct_cmd_desc(&desc,
2148                                           i40e_aqc_opc_get_local_advt_reg);
2149
2150         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2151
2152         if (status != I40E_SUCCESS)
2153                 goto aq_get_local_advt_reg_exit;
2154
2155         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2156         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2157
2158 aq_get_local_advt_reg_exit:
2159         return status;
2160 }
2161
2162 /**
2163  * i40e_aq_set_local_advt_reg
2164  * @hw: pointer to the hw struct
2165  * @advt_reg: local AN advertisement register value
2166  * @cmd_details: pointer to command details structure or NULL
2167  *
2168  * Get the Local AN advertisement register value.
2169  **/
2170 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2171                                 u64 advt_reg,
2172                                 struct i40e_asq_cmd_details *cmd_details)
2173 {
2174         struct i40e_aq_desc desc;
2175         struct i40e_aqc_an_advt_reg *cmd =
2176                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2177         enum i40e_status_code status;
2178
2179         i40e_fill_default_direct_cmd_desc(&desc,
2180                                           i40e_aqc_opc_get_local_advt_reg);
2181
2182         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2183         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2184
2185         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2186
2187         return status;
2188 }
2189
2190 /**
2191  * i40e_aq_get_partner_advt
2192  * @hw: pointer to the hw struct
2193  * @advt_reg: AN partner advertisement register value
2194  * @cmd_details: pointer to command details structure or NULL
2195  *
2196  * Get the link partner AN advertisement register value.
2197  **/
2198 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2199                                 u64 *advt_reg,
2200                                 struct i40e_asq_cmd_details *cmd_details)
2201 {
2202         struct i40e_aq_desc desc;
2203         struct i40e_aqc_an_advt_reg *resp =
2204                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2205         enum i40e_status_code status;
2206
2207         i40e_fill_default_direct_cmd_desc(&desc,
2208                                           i40e_aqc_opc_get_partner_advt);
2209
2210         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2211
2212         if (status != I40E_SUCCESS)
2213                 goto aq_get_partner_advt_exit;
2214
2215         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2216         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2217
2218 aq_get_partner_advt_exit:
2219         return status;
2220 }
2221
2222 /**
2223  * i40e_aq_set_lb_modes
2224  * @hw: pointer to the hw struct
2225  * @lb_modes: loopback mode to be set
2226  * @cmd_details: pointer to command details structure or NULL
2227  *
2228  * Sets loopback modes.
2229  **/
2230 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2231                                 u16 lb_modes,
2232                                 struct i40e_asq_cmd_details *cmd_details)
2233 {
2234         struct i40e_aq_desc desc;
2235         struct i40e_aqc_set_lb_mode *cmd =
2236                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2237         enum i40e_status_code status;
2238
2239         i40e_fill_default_direct_cmd_desc(&desc,
2240                                           i40e_aqc_opc_set_lb_modes);
2241
2242         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2243
2244         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2245
2246         return status;
2247 }
2248
2249 /**
2250  * i40e_aq_set_phy_debug
2251  * @hw: pointer to the hw struct
2252  * @cmd_flags: debug command flags
2253  * @cmd_details: pointer to command details structure or NULL
2254  *
2255  * Reset the external PHY.
2256  **/
2257 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2258                                 struct i40e_asq_cmd_details *cmd_details)
2259 {
2260         struct i40e_aq_desc desc;
2261         struct i40e_aqc_set_phy_debug *cmd =
2262                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2263         enum i40e_status_code status;
2264
2265         i40e_fill_default_direct_cmd_desc(&desc,
2266                                           i40e_aqc_opc_set_phy_debug);
2267
2268         cmd->command_flags = cmd_flags;
2269
2270         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2271
2272         return status;
2273 }
2274
2275 /**
2276  * i40e_hw_ver_ge
2277  * @hw: pointer to the hw struct
2278  * @maj: api major value
2279  * @min: api minor value
2280  *
2281  * Assert whether current HW api version is greater/equal than provided.
2282  **/
2283 static bool i40e_hw_ver_ge(struct i40e_hw *hw, u16 maj, u16 min)
2284 {
2285         if (hw->aq.api_maj_ver > maj ||
2286             (hw->aq.api_maj_ver == maj && hw->aq.api_min_ver >= min))
2287                 return true;
2288         return false;
2289 }
2290
2291 /**
2292  * i40e_aq_add_vsi
2293  * @hw: pointer to the hw struct
2294  * @vsi_ctx: pointer to a vsi context struct
2295  * @cmd_details: pointer to command details structure or NULL
2296  *
2297  * Add a VSI context to the hardware.
2298 **/
2299 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2300                                 struct i40e_vsi_context *vsi_ctx,
2301                                 struct i40e_asq_cmd_details *cmd_details)
2302 {
2303         struct i40e_aq_desc desc;
2304         struct i40e_aqc_add_get_update_vsi *cmd =
2305                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2306         struct i40e_aqc_add_get_update_vsi_completion *resp =
2307                 (struct i40e_aqc_add_get_update_vsi_completion *)
2308                 &desc.params.raw;
2309         enum i40e_status_code status;
2310
2311         i40e_fill_default_direct_cmd_desc(&desc,
2312                                           i40e_aqc_opc_add_vsi);
2313
2314         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2315         cmd->connection_type = vsi_ctx->connection_type;
2316         cmd->vf_id = vsi_ctx->vf_num;
2317         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2318
2319         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2320
2321         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2322                                     sizeof(vsi_ctx->info), cmd_details);
2323
2324         if (status != I40E_SUCCESS)
2325                 goto aq_add_vsi_exit;
2326
2327         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2328         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2329         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2330         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2331
2332 aq_add_vsi_exit:
2333         return status;
2334 }
2335
2336 /**
2337  * i40e_aq_set_default_vsi
2338  * @hw: pointer to the hw struct
2339  * @seid: vsi number
2340  * @cmd_details: pointer to command details structure or NULL
2341  **/
2342 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2343                                 u16 seid,
2344                                 struct i40e_asq_cmd_details *cmd_details)
2345 {
2346         struct i40e_aq_desc desc;
2347         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2348                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2349                 &desc.params.raw;
2350         enum i40e_status_code status;
2351
2352         i40e_fill_default_direct_cmd_desc(&desc,
2353                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2354
2355         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2356         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2357         cmd->seid = CPU_TO_LE16(seid);
2358
2359         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2360
2361         return status;
2362 }
2363
2364 /**
2365  * i40e_aq_clear_default_vsi
2366  * @hw: pointer to the hw struct
2367  * @seid: vsi number
2368  * @cmd_details: pointer to command details structure or NULL
2369  **/
2370 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2371                                 u16 seid,
2372                                 struct i40e_asq_cmd_details *cmd_details)
2373 {
2374         struct i40e_aq_desc desc;
2375         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2376                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2377                 &desc.params.raw;
2378         enum i40e_status_code status;
2379
2380         i40e_fill_default_direct_cmd_desc(&desc,
2381                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2382
2383         cmd->promiscuous_flags = CPU_TO_LE16(0);
2384         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2385         cmd->seid = CPU_TO_LE16(seid);
2386
2387         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2388
2389         return status;
2390 }
2391
2392 /**
2393  * i40e_aq_set_vsi_unicast_promiscuous
2394  * @hw: pointer to the hw struct
2395  * @seid: vsi number
2396  * @set: set unicast promiscuous enable/disable
2397  * @cmd_details: pointer to command details structure or NULL
2398  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2399  **/
2400 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2401                                 u16 seid, bool set,
2402                                 struct i40e_asq_cmd_details *cmd_details,
2403                                 bool rx_only_promisc)
2404 {
2405         struct i40e_aq_desc desc;
2406         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2407                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2408         enum i40e_status_code status;
2409         u16 flags = 0;
2410
2411         i40e_fill_default_direct_cmd_desc(&desc,
2412                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2413
2414         if (set) {
2415                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2416                 if (rx_only_promisc && i40e_hw_ver_ge(hw, 1, 5))
2417                         flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2418         }
2419
2420         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2421
2422         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2423         if (i40e_hw_ver_ge(hw, 1, 5))
2424                 cmd->valid_flags |=
2425                         CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2426
2427         cmd->seid = CPU_TO_LE16(seid);
2428         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2429
2430         return status;
2431 }
2432
2433 /**
2434  * i40e_aq_set_vsi_multicast_promiscuous
2435  * @hw: pointer to the hw struct
2436  * @seid: vsi number
2437  * @set: set multicast promiscuous enable/disable
2438  * @cmd_details: pointer to command details structure or NULL
2439  **/
2440 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2441                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2442 {
2443         struct i40e_aq_desc desc;
2444         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2445                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2446         enum i40e_status_code status;
2447         u16 flags = 0;
2448
2449         i40e_fill_default_direct_cmd_desc(&desc,
2450                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2451
2452         if (set)
2453                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2454
2455         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2456
2457         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2458
2459         cmd->seid = CPU_TO_LE16(seid);
2460         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2461
2462         return status;
2463 }
2464
2465 /**
2466 * i40e_aq_set_vsi_full_promiscuous
2467 * @hw: pointer to the hw struct
2468 * @seid: VSI number
2469 * @set: set promiscuous enable/disable
2470 * @cmd_details: pointer to command details structure or NULL
2471 **/
2472 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2473                                 u16 seid, bool set,
2474                                 struct i40e_asq_cmd_details *cmd_details)
2475 {
2476         struct i40e_aq_desc desc;
2477         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2478                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2479         enum i40e_status_code status;
2480         u16 flags = 0;
2481
2482         i40e_fill_default_direct_cmd_desc(&desc,
2483                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2484
2485         if (set)
2486                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2487                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2488                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2489
2490         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2491
2492         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2493                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2494                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2495
2496         cmd->seid = CPU_TO_LE16(seid);
2497         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2498
2499         return status;
2500 }
2501
2502 /**
2503  * i40e_aq_set_vsi_mc_promisc_on_vlan
2504  * @hw: pointer to the hw struct
2505  * @seid: vsi number
2506  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2507  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2508  * @cmd_details: pointer to command details structure or NULL
2509  **/
2510 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2511                                 u16 seid, bool enable, u16 vid,
2512                                 struct i40e_asq_cmd_details *cmd_details)
2513 {
2514         struct i40e_aq_desc desc;
2515         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2516                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2517         enum i40e_status_code status;
2518         u16 flags = 0;
2519
2520         i40e_fill_default_direct_cmd_desc(&desc,
2521                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2522
2523         if (enable)
2524                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2525
2526         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2527         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2528         cmd->seid = CPU_TO_LE16(seid);
2529         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2530
2531         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2532
2533         return status;
2534 }
2535
2536 /**
2537  * i40e_aq_set_vsi_uc_promisc_on_vlan
2538  * @hw: pointer to the hw struct
2539  * @seid: vsi number
2540  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2541  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2542  * @cmd_details: pointer to command details structure or NULL
2543  **/
2544 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2545                                 u16 seid, bool enable, u16 vid,
2546                                 struct i40e_asq_cmd_details *cmd_details)
2547 {
2548         struct i40e_aq_desc desc;
2549         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2550                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2551         enum i40e_status_code status;
2552         u16 flags = 0;
2553
2554         i40e_fill_default_direct_cmd_desc(&desc,
2555                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2556
2557         if (enable) {
2558                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2559                 if (i40e_hw_ver_ge(hw, 1, 5))
2560                         flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2561         }
2562
2563         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2564         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2565         if (i40e_hw_ver_ge(hw, 1, 5))
2566                 cmd->valid_flags |=
2567                         CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2568         cmd->seid = CPU_TO_LE16(seid);
2569         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2570
2571         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2572
2573         return status;
2574 }
2575
2576 /**
2577  * i40e_aq_set_vsi_bc_promisc_on_vlan
2578  * @hw: pointer to the hw struct
2579  * @seid: vsi number
2580  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2581  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2582  * @cmd_details: pointer to command details structure or NULL
2583  **/
2584 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2585                                 u16 seid, bool enable, u16 vid,
2586                                 struct i40e_asq_cmd_details *cmd_details)
2587 {
2588         struct i40e_aq_desc desc;
2589         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2590                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2591         enum i40e_status_code status;
2592         u16 flags = 0;
2593
2594         i40e_fill_default_direct_cmd_desc(&desc,
2595                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2596
2597         if (enable)
2598                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2599
2600         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2601         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2602         cmd->seid = CPU_TO_LE16(seid);
2603         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2604
2605         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2606
2607         return status;
2608 }
2609
2610 /**
2611  * i40e_aq_set_vsi_broadcast
2612  * @hw: pointer to the hw struct
2613  * @seid: vsi number
2614  * @set_filter: true to set filter, false to clear filter
2615  * @cmd_details: pointer to command details structure or NULL
2616  *
2617  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2618  **/
2619 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2620                                 u16 seid, bool set_filter,
2621                                 struct i40e_asq_cmd_details *cmd_details)
2622 {
2623         struct i40e_aq_desc desc;
2624         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2625                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2626         enum i40e_status_code status;
2627
2628         i40e_fill_default_direct_cmd_desc(&desc,
2629                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2630
2631         if (set_filter)
2632                 cmd->promiscuous_flags
2633                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2634         else
2635                 cmd->promiscuous_flags
2636                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2637
2638         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2639         cmd->seid = CPU_TO_LE16(seid);
2640         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2641
2642         return status;
2643 }
2644
2645 /**
2646  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2647  * @hw: pointer to the hw struct
2648  * @seid: vsi number
2649  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2650  * @cmd_details: pointer to command details structure or NULL
2651  **/
2652 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2653                                 u16 seid, bool enable,
2654                                 struct i40e_asq_cmd_details *cmd_details)
2655 {
2656         struct i40e_aq_desc desc;
2657         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2658                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2659         enum i40e_status_code status;
2660         u16 flags = 0;
2661
2662         i40e_fill_default_direct_cmd_desc(&desc,
2663                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2664         if (enable)
2665                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2666
2667         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2668         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2669         cmd->seid = CPU_TO_LE16(seid);
2670
2671         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2672
2673         return status;
2674 }
2675
2676 /**
2677  * i40e_get_vsi_params - get VSI configuration info
2678  * @hw: pointer to the hw struct
2679  * @vsi_ctx: pointer to a vsi context struct
2680  * @cmd_details: pointer to command details structure or NULL
2681  **/
2682 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2683                                 struct i40e_vsi_context *vsi_ctx,
2684                                 struct i40e_asq_cmd_details *cmd_details)
2685 {
2686         struct i40e_aq_desc desc;
2687         struct i40e_aqc_add_get_update_vsi *cmd =
2688                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2689         struct i40e_aqc_add_get_update_vsi_completion *resp =
2690                 (struct i40e_aqc_add_get_update_vsi_completion *)
2691                 &desc.params.raw;
2692         enum i40e_status_code status;
2693
2694         UNREFERENCED_1PARAMETER(cmd_details);
2695         i40e_fill_default_direct_cmd_desc(&desc,
2696                                           i40e_aqc_opc_get_vsi_parameters);
2697
2698         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2699
2700         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2701
2702         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2703                                     sizeof(vsi_ctx->info), NULL);
2704
2705         if (status != I40E_SUCCESS)
2706                 goto aq_get_vsi_params_exit;
2707
2708         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2709         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2710         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2711         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2712
2713 aq_get_vsi_params_exit:
2714         return status;
2715 }
2716
2717 /**
2718  * i40e_aq_update_vsi_params
2719  * @hw: pointer to the hw struct
2720  * @vsi_ctx: pointer to a vsi context struct
2721  * @cmd_details: pointer to command details structure or NULL
2722  *
2723  * Update a VSI context.
2724  **/
2725 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2726                                 struct i40e_vsi_context *vsi_ctx,
2727                                 struct i40e_asq_cmd_details *cmd_details)
2728 {
2729         struct i40e_aq_desc desc;
2730         struct i40e_aqc_add_get_update_vsi *cmd =
2731                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2732         struct i40e_aqc_add_get_update_vsi_completion *resp =
2733                 (struct i40e_aqc_add_get_update_vsi_completion *)
2734                 &desc.params.raw;
2735         enum i40e_status_code status;
2736
2737         i40e_fill_default_direct_cmd_desc(&desc,
2738                                           i40e_aqc_opc_update_vsi_parameters);
2739         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2740
2741         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2742
2743         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2744                                     sizeof(vsi_ctx->info), cmd_details);
2745
2746         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2747         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2748
2749         return status;
2750 }
2751
2752 /**
2753  * i40e_aq_get_switch_config
2754  * @hw: pointer to the hardware structure
2755  * @buf: pointer to the result buffer
2756  * @buf_size: length of input buffer
2757  * @start_seid: seid to start for the report, 0 == beginning
2758  * @cmd_details: pointer to command details structure or NULL
2759  *
2760  * Fill the buf with switch configuration returned from AdminQ command
2761  **/
2762 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2763                                 struct i40e_aqc_get_switch_config_resp *buf,
2764                                 u16 buf_size, u16 *start_seid,
2765                                 struct i40e_asq_cmd_details *cmd_details)
2766 {
2767         struct i40e_aq_desc desc;
2768         struct i40e_aqc_switch_seid *scfg =
2769                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2770         enum i40e_status_code status;
2771
2772         i40e_fill_default_direct_cmd_desc(&desc,
2773                                           i40e_aqc_opc_get_switch_config);
2774         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2775         if (buf_size > I40E_AQ_LARGE_BUF)
2776                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2777         scfg->seid = CPU_TO_LE16(*start_seid);
2778
2779         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2780         *start_seid = LE16_TO_CPU(scfg->seid);
2781
2782         return status;
2783 }
2784
2785 /**
2786  * i40e_aq_set_switch_config
2787  * @hw: pointer to the hardware structure
2788  * @flags: bit flag values to set
2789  * @mode: cloud filter mode
2790  * @valid_flags: which bit flags to set
2791  * @cmd_details: pointer to command details structure or NULL
2792  *
2793  * Set switch configuration bits
2794  **/
2795 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2796                                 u16 flags, u16 valid_flags, u8 mode,
2797                                 struct i40e_asq_cmd_details *cmd_details)
2798 {
2799         struct i40e_aq_desc desc;
2800         struct i40e_aqc_set_switch_config *scfg =
2801                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2802         enum i40e_status_code status;
2803
2804         i40e_fill_default_direct_cmd_desc(&desc,
2805                                           i40e_aqc_opc_set_switch_config);
2806         scfg->flags = CPU_TO_LE16(flags);
2807         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2808         scfg->mode = mode;
2809         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2810                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2811                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2812                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2813         }
2814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2815
2816         return status;
2817 }
2818
2819 /**
2820  * i40e_aq_get_firmware_version
2821  * @hw: pointer to the hw struct
2822  * @fw_major_version: firmware major version
2823  * @fw_minor_version: firmware minor version
2824  * @fw_build: firmware build number
2825  * @api_major_version: major queue version
2826  * @api_minor_version: minor queue version
2827  * @cmd_details: pointer to command details structure or NULL
2828  *
2829  * Get the firmware version from the admin queue commands
2830  **/
2831 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2832                                 u16 *fw_major_version, u16 *fw_minor_version,
2833                                 u32 *fw_build,
2834                                 u16 *api_major_version, u16 *api_minor_version,
2835                                 struct i40e_asq_cmd_details *cmd_details)
2836 {
2837         struct i40e_aq_desc desc;
2838         struct i40e_aqc_get_version *resp =
2839                 (struct i40e_aqc_get_version *)&desc.params.raw;
2840         enum i40e_status_code status;
2841
2842         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2843
2844         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2845
2846         if (status == I40E_SUCCESS) {
2847                 if (fw_major_version != NULL)
2848                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2849                 if (fw_minor_version != NULL)
2850                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2851                 if (fw_build != NULL)
2852                         *fw_build = LE32_TO_CPU(resp->fw_build);
2853                 if (api_major_version != NULL)
2854                         *api_major_version = LE16_TO_CPU(resp->api_major);
2855                 if (api_minor_version != NULL)
2856                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2857
2858                 /* A workaround to fix the API version in SW */
2859                 if (api_major_version && api_minor_version &&
2860                     fw_major_version && fw_minor_version &&
2861                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2862                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2863                      (*fw_major_version > 4)))
2864                         *api_minor_version = 2;
2865         }
2866
2867         return status;
2868 }
2869
2870 /**
2871  * i40e_aq_send_driver_version
2872  * @hw: pointer to the hw struct
2873  * @dv: driver's major, minor version
2874  * @cmd_details: pointer to command details structure or NULL
2875  *
2876  * Send the driver version to the firmware
2877  **/
2878 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2879                                 struct i40e_driver_version *dv,
2880                                 struct i40e_asq_cmd_details *cmd_details)
2881 {
2882         struct i40e_aq_desc desc;
2883         struct i40e_aqc_driver_version *cmd =
2884                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2885         enum i40e_status_code status;
2886         u16 len;
2887
2888         if (dv == NULL)
2889                 return I40E_ERR_PARAM;
2890
2891         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2892
2893         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2894         cmd->driver_major_ver = dv->major_version;
2895         cmd->driver_minor_ver = dv->minor_version;
2896         cmd->driver_build_ver = dv->build_version;
2897         cmd->driver_subbuild_ver = dv->subbuild_version;
2898
2899         len = 0;
2900         while (len < sizeof(dv->driver_string) &&
2901                (dv->driver_string[len] < 0x80) &&
2902                dv->driver_string[len])
2903                 len++;
2904         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2905                                        len, cmd_details);
2906
2907         return status;
2908 }
2909
2910 /**
2911  * i40e_get_link_status - get status of the HW network link
2912  * @hw: pointer to the hw struct
2913  * @link_up: pointer to bool (true/false = linkup/linkdown)
2914  *
2915  * Variable link_up true if link is up, false if link is down.
2916  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2917  *
2918  * Side effect: LinkStatusEvent reporting becomes enabled
2919  **/
2920 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2921 {
2922         enum i40e_status_code status = I40E_SUCCESS;
2923
2924         if (hw->phy.get_link_info) {
2925                 status = i40e_update_link_info(hw);
2926
2927                 if (status != I40E_SUCCESS)
2928                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2929                                    status);
2930         }
2931
2932         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2933
2934         return status;
2935 }
2936
2937 /**
2938  * i40e_updatelink_status - update status of the HW network link
2939  * @hw: pointer to the hw struct
2940  **/
2941 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2942 {
2943         struct i40e_aq_get_phy_abilities_resp abilities;
2944         enum i40e_status_code status = I40E_SUCCESS;
2945
2946         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2947         if (status)
2948                 return status;
2949
2950         /* extra checking needed to ensure link info to user is timely */
2951         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2952             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2953              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2954                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2955                                                       &abilities, NULL);
2956                 if (status)
2957                         return status;
2958
2959                 if (abilities.fec_cfg_curr_mod_ext_info &
2960                     I40E_AQ_ENABLE_FEC_AUTO)
2961                         hw->phy.link_info.req_fec_info =
2962                                 (I40E_AQ_REQUEST_FEC_KR |
2963                                  I40E_AQ_REQUEST_FEC_RS);
2964                 else
2965                         hw->phy.link_info.req_fec_info =
2966                                 abilities.fec_cfg_curr_mod_ext_info &
2967                                 (I40E_AQ_REQUEST_FEC_KR |
2968                                  I40E_AQ_REQUEST_FEC_RS);
2969
2970                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2971                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2972         }
2973         return status;
2974 }
2975
2976
2977 /**
2978  * i40e_get_link_speed
2979  * @hw: pointer to the hw struct
2980  *
2981  * Returns the link speed of the adapter.
2982  **/
2983 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2984 {
2985         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2986         enum i40e_status_code status = I40E_SUCCESS;
2987
2988         if (hw->phy.get_link_info) {
2989                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2990
2991                 if (status != I40E_SUCCESS)
2992                         goto i40e_link_speed_exit;
2993         }
2994
2995         speed = hw->phy.link_info.link_speed;
2996
2997 i40e_link_speed_exit:
2998         return speed;
2999 }
3000
3001 /**
3002  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
3003  * @hw: pointer to the hw struct
3004  * @uplink_seid: the MAC or other gizmo SEID
3005  * @downlink_seid: the VSI SEID
3006  * @enabled_tc: bitmap of TCs to be enabled
3007  * @default_port: true for default port VSI, false for control port
3008  * @veb_seid: pointer to where to put the resulting VEB SEID
3009  * @enable_stats: true to turn on VEB stats
3010  * @cmd_details: pointer to command details structure or NULL
3011  *
3012  * This asks the FW to add a VEB between the uplink and downlink
3013  * elements.  If the uplink SEID is 0, this will be a floating VEB.
3014  **/
3015 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
3016                                 u16 downlink_seid, u8 enabled_tc,
3017                                 bool default_port, u16 *veb_seid,
3018                                 bool enable_stats,
3019                                 struct i40e_asq_cmd_details *cmd_details)
3020 {
3021         struct i40e_aq_desc desc;
3022         struct i40e_aqc_add_veb *cmd =
3023                 (struct i40e_aqc_add_veb *)&desc.params.raw;
3024         struct i40e_aqc_add_veb_completion *resp =
3025                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
3026         enum i40e_status_code status;
3027         u16 veb_flags = 0;
3028
3029         /* SEIDs need to either both be set or both be 0 for floating VEB */
3030         if (!!uplink_seid != !!downlink_seid)
3031                 return I40E_ERR_PARAM;
3032
3033         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
3034
3035         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
3036         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
3037         cmd->enable_tcs = enabled_tc;
3038         if (!uplink_seid)
3039                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
3040         if (default_port)
3041                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
3042         else
3043                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
3044
3045         /* reverse logic here: set the bitflag to disable the stats */
3046         if (!enable_stats)
3047                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
3048
3049         cmd->veb_flags = CPU_TO_LE16(veb_flags);
3050
3051         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3052
3053         if (!status && veb_seid)
3054                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
3055
3056         return status;
3057 }
3058
3059 /**
3060  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
3061  * @hw: pointer to the hw struct
3062  * @veb_seid: the SEID of the VEB to query
3063  * @switch_id: the uplink switch id
3064  * @floating: set to true if the VEB is floating
3065  * @statistic_index: index of the stats counter block for this VEB
3066  * @vebs_used: number of VEB's used by function
3067  * @vebs_free: total VEB's not reserved by any function
3068  * @cmd_details: pointer to command details structure or NULL
3069  *
3070  * This retrieves the parameters for a particular VEB, specified by
3071  * uplink_seid, and returns them to the caller.
3072  **/
3073 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3074                                 u16 veb_seid, u16 *switch_id,
3075                                 bool *floating, u16 *statistic_index,
3076                                 u16 *vebs_used, u16 *vebs_free,
3077                                 struct i40e_asq_cmd_details *cmd_details)
3078 {
3079         struct i40e_aq_desc desc;
3080         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3081                 (struct i40e_aqc_get_veb_parameters_completion *)
3082                 &desc.params.raw;
3083         enum i40e_status_code status;
3084
3085         if (veb_seid == 0)
3086                 return I40E_ERR_PARAM;
3087
3088         i40e_fill_default_direct_cmd_desc(&desc,
3089                                           i40e_aqc_opc_get_veb_parameters);
3090         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3091
3092         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3093         if (status)
3094                 goto get_veb_exit;
3095
3096         if (switch_id)
3097                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3098         if (statistic_index)
3099                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3100         if (vebs_used)
3101                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3102         if (vebs_free)
3103                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3104         if (floating) {
3105                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3106
3107                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3108                         *floating = true;
3109                 else
3110                         *floating = false;
3111         }
3112
3113 get_veb_exit:
3114         return status;
3115 }
3116
3117 /**
3118  * i40e_aq_add_macvlan
3119  * @hw: pointer to the hw struct
3120  * @seid: VSI for the mac address
3121  * @mv_list: list of macvlans to be added
3122  * @count: length of the list
3123  * @cmd_details: pointer to command details structure or NULL
3124  *
3125  * Add MAC/VLAN addresses to the HW filtering
3126  **/
3127 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3128                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3129                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3130 {
3131         struct i40e_aq_desc desc;
3132         struct i40e_aqc_macvlan *cmd =
3133                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3134         enum i40e_status_code status;
3135         u16 buf_size;
3136         int i;
3137
3138         if (count == 0 || !mv_list || !hw)
3139                 return I40E_ERR_PARAM;
3140
3141         buf_size = count * sizeof(*mv_list);
3142
3143         /* prep the rest of the request */
3144         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3145         cmd->num_addresses = CPU_TO_LE16(count);
3146         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3147         cmd->seid[1] = 0;
3148         cmd->seid[2] = 0;
3149
3150         for (i = 0; i < count; i++)
3151                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3152                         mv_list[i].flags |=
3153                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3154
3155         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3156         if (buf_size > I40E_AQ_LARGE_BUF)
3157                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3158
3159         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3160                                        cmd_details);
3161
3162         return status;
3163 }
3164
3165 /**
3166  * i40e_aq_remove_macvlan
3167  * @hw: pointer to the hw struct
3168  * @seid: VSI for the mac address
3169  * @mv_list: list of macvlans to be removed
3170  * @count: length of the list
3171  * @cmd_details: pointer to command details structure or NULL
3172  *
3173  * Remove MAC/VLAN addresses from the HW filtering
3174  **/
3175 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3176                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3177                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3178 {
3179         struct i40e_aq_desc desc;
3180         struct i40e_aqc_macvlan *cmd =
3181                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3182         enum i40e_status_code status;
3183         u16 buf_size;
3184
3185         if (count == 0 || !mv_list || !hw)
3186                 return I40E_ERR_PARAM;
3187
3188         buf_size = count * sizeof(*mv_list);
3189
3190         /* prep the rest of the request */
3191         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3192         cmd->num_addresses = CPU_TO_LE16(count);
3193         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3194         cmd->seid[1] = 0;
3195         cmd->seid[2] = 0;
3196
3197         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3198         if (buf_size > I40E_AQ_LARGE_BUF)
3199                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3200
3201         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3202                                        cmd_details);
3203
3204         return status;
3205 }
3206
3207 /**
3208  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3209  * @hw: pointer to the hw struct
3210  * @opcode: AQ opcode for add or delete mirror rule
3211  * @sw_seid: Switch SEID (to which rule refers)
3212  * @rule_type: Rule Type (ingress/egress/VLAN)
3213  * @id: Destination VSI SEID or Rule ID
3214  * @count: length of the list
3215  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3216  * @cmd_details: pointer to command details structure or NULL
3217  * @rule_id: Rule ID returned from FW
3218  * @rules_used: Number of rules used in internal switch
3219  * @rules_free: Number of rules free in internal switch
3220  *
3221  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3222  * VEBs/VEPA elements only
3223  **/
3224 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3225                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3226                         u16 count, __le16 *mr_list,
3227                         struct i40e_asq_cmd_details *cmd_details,
3228                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3229 {
3230         struct i40e_aq_desc desc;
3231         struct i40e_aqc_add_delete_mirror_rule *cmd =
3232                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3233         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3234         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3235         enum i40e_status_code status;
3236         u16 buf_size;
3237
3238         buf_size = count * sizeof(*mr_list);
3239
3240         /* prep the rest of the request */
3241         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3242         cmd->seid = CPU_TO_LE16(sw_seid);
3243         cmd->rule_type = CPU_TO_LE16(rule_type &
3244                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3245         cmd->num_entries = CPU_TO_LE16(count);
3246         /* Dest VSI for add, rule_id for delete */
3247         cmd->destination = CPU_TO_LE16(id);
3248         if (mr_list) {
3249                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3250                                                 I40E_AQ_FLAG_RD));
3251                 if (buf_size > I40E_AQ_LARGE_BUF)
3252                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3253         }
3254
3255         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3256                                        cmd_details);
3257         if (status == I40E_SUCCESS ||
3258             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3259                 if (rule_id)
3260                         *rule_id = LE16_TO_CPU(resp->rule_id);
3261                 if (rules_used)
3262                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3263                 if (rules_free)
3264                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3265         }
3266         return status;
3267 }
3268
3269 /**
3270  * i40e_aq_add_mirrorrule - add a mirror rule
3271  * @hw: pointer to the hw struct
3272  * @sw_seid: Switch SEID (to which rule refers)
3273  * @rule_type: Rule Type (ingress/egress/VLAN)
3274  * @dest_vsi: SEID of VSI to which packets will be mirrored
3275  * @count: length of the list
3276  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3277  * @cmd_details: pointer to command details structure or NULL
3278  * @rule_id: Rule ID returned from FW
3279  * @rules_used: Number of rules used in internal switch
3280  * @rules_free: Number of rules free in internal switch
3281  *
3282  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3283  **/
3284 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3285                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3286                         struct i40e_asq_cmd_details *cmd_details,
3287                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3288 {
3289         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3290             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3291                 if (count == 0 || !mr_list)
3292                         return I40E_ERR_PARAM;
3293         }
3294
3295         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3296                                   rule_type, dest_vsi, count, mr_list,
3297                                   cmd_details, rule_id, rules_used, rules_free);
3298 }
3299
3300 /**
3301  * i40e_aq_delete_mirrorrule - delete a mirror rule
3302  * @hw: pointer to the hw struct
3303  * @sw_seid: Switch SEID (to which rule refers)
3304  * @rule_type: Rule Type (ingress/egress/VLAN)
3305  * @count: length of the list
3306  * @rule_id: Rule ID that is returned in the receive desc as part of
3307  *              add_mirrorrule.
3308  * @mr_list: list of mirrored VLAN IDs to be removed
3309  * @cmd_details: pointer to command details structure or NULL
3310  * @rules_used: Number of rules used in internal switch
3311  * @rules_free: Number of rules free in internal switch
3312  *
3313  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3314  **/
3315 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3316                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3317                         struct i40e_asq_cmd_details *cmd_details,
3318                         u16 *rules_used, u16 *rules_free)
3319 {
3320         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3321         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3322                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3323                  * mirroring. For other rule_type, count and rule_type should
3324                  * not matter.
3325                  */
3326                 if (count == 0 || !mr_list)
3327                         return I40E_ERR_PARAM;
3328         }
3329
3330         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3331                                   rule_type, rule_id, count, mr_list,
3332                                   cmd_details, NULL, rules_used, rules_free);
3333 }
3334
3335 /**
3336  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3337  * @hw: pointer to the hw struct
3338  * @seid: VSI for the vlan filters
3339  * @v_list: list of vlan filters to be added
3340  * @count: length of the list
3341  * @cmd_details: pointer to command details structure or NULL
3342  **/
3343 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3344                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3345                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3346 {
3347         struct i40e_aq_desc desc;
3348         struct i40e_aqc_macvlan *cmd =
3349                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3350         enum i40e_status_code status;
3351         u16 buf_size;
3352
3353         if (count == 0 || !v_list || !hw)
3354                 return I40E_ERR_PARAM;
3355
3356         buf_size = count * sizeof(*v_list);
3357
3358         /* prep the rest of the request */
3359         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3360         cmd->num_addresses = CPU_TO_LE16(count);
3361         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3362         cmd->seid[1] = 0;
3363         cmd->seid[2] = 0;
3364
3365         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3366         if (buf_size > I40E_AQ_LARGE_BUF)
3367                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3368
3369         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3370                                        cmd_details);
3371
3372         return status;
3373 }
3374
3375 /**
3376  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3377  * @hw: pointer to the hw struct
3378  * @seid: VSI for the vlan filters
3379  * @v_list: list of macvlans to be removed
3380  * @count: length of the list
3381  * @cmd_details: pointer to command details structure or NULL
3382  **/
3383 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3384                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3385                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3386 {
3387         struct i40e_aq_desc desc;
3388         struct i40e_aqc_macvlan *cmd =
3389                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3390         enum i40e_status_code status;
3391         u16 buf_size;
3392
3393         if (count == 0 || !v_list || !hw)
3394                 return I40E_ERR_PARAM;
3395
3396         buf_size = count * sizeof(*v_list);
3397
3398         /* prep the rest of the request */
3399         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3400         cmd->num_addresses = CPU_TO_LE16(count);
3401         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3402         cmd->seid[1] = 0;
3403         cmd->seid[2] = 0;
3404
3405         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3406         if (buf_size > I40E_AQ_LARGE_BUF)
3407                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3408
3409         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3410                                        cmd_details);
3411
3412         return status;
3413 }
3414
3415 /**
3416  * i40e_aq_send_msg_to_vf
3417  * @hw: pointer to the hardware structure
3418  * @vfid: vf id to send msg
3419  * @v_opcode: opcodes for VF-PF communication
3420  * @v_retval: return error code
3421  * @msg: pointer to the msg buffer
3422  * @msglen: msg length
3423  * @cmd_details: pointer to command details
3424  *
3425  * send msg to vf
3426  **/
3427 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3428                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3429                                 struct i40e_asq_cmd_details *cmd_details)
3430 {
3431         struct i40e_aq_desc desc;
3432         struct i40e_aqc_pf_vf_message *cmd =
3433                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3434         enum i40e_status_code status;
3435
3436         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3437         cmd->id = CPU_TO_LE32(vfid);
3438         desc.cookie_high = CPU_TO_LE32(v_opcode);
3439         desc.cookie_low = CPU_TO_LE32(v_retval);
3440         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3441         if (msglen) {
3442                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3443                                                 I40E_AQ_FLAG_RD));
3444                 if (msglen > I40E_AQ_LARGE_BUF)
3445                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3446                 desc.datalen = CPU_TO_LE16(msglen);
3447         }
3448         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3449
3450         return status;
3451 }
3452
3453 /**
3454  * i40e_aq_debug_read_register
3455  * @hw: pointer to the hw struct
3456  * @reg_addr: register address
3457  * @reg_val: register value
3458  * @cmd_details: pointer to command details structure or NULL
3459  *
3460  * Read the register using the admin queue commands
3461  **/
3462 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3463                                 u32 reg_addr, u64 *reg_val,
3464                                 struct i40e_asq_cmd_details *cmd_details)
3465 {
3466         struct i40e_aq_desc desc;
3467         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3468                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3469         enum i40e_status_code status;
3470
3471         if (reg_val == NULL)
3472                 return I40E_ERR_PARAM;
3473
3474         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3475
3476         cmd_resp->address = CPU_TO_LE32(reg_addr);
3477
3478         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3479
3480         if (status == I40E_SUCCESS) {
3481                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3482                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3483         }
3484
3485         return status;
3486 }
3487
3488 /**
3489  * i40e_aq_debug_write_register
3490  * @hw: pointer to the hw struct
3491  * @reg_addr: register address
3492  * @reg_val: register value
3493  * @cmd_details: pointer to command details structure or NULL
3494  *
3495  * Write to a register using the admin queue commands
3496  **/
3497 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3498                                 u32 reg_addr, u64 reg_val,
3499                                 struct i40e_asq_cmd_details *cmd_details)
3500 {
3501         struct i40e_aq_desc desc;
3502         struct i40e_aqc_debug_reg_read_write *cmd =
3503                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3504         enum i40e_status_code status;
3505
3506         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3507
3508         cmd->address = CPU_TO_LE32(reg_addr);
3509         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3510         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3511
3512         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3513
3514         return status;
3515 }
3516
3517 /**
3518  * i40e_aq_request_resource
3519  * @hw: pointer to the hw struct
3520  * @resource: resource id
3521  * @access: access type
3522  * @sdp_number: resource number
3523  * @timeout: the maximum time in ms that the driver may hold the resource
3524  * @cmd_details: pointer to command details structure or NULL
3525  *
3526  * requests common resource using the admin queue commands
3527  **/
3528 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3529                                 enum i40e_aq_resources_ids resource,
3530                                 enum i40e_aq_resource_access_type access,
3531                                 u8 sdp_number, u64 *timeout,
3532                                 struct i40e_asq_cmd_details *cmd_details)
3533 {
3534         struct i40e_aq_desc desc;
3535         struct i40e_aqc_request_resource *cmd_resp =
3536                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3537         enum i40e_status_code status;
3538
3539         DEBUGFUNC("i40e_aq_request_resource");
3540
3541         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3542
3543         cmd_resp->resource_id = CPU_TO_LE16(resource);
3544         cmd_resp->access_type = CPU_TO_LE16(access);
3545         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3546
3547         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3548         /* The completion specifies the maximum time in ms that the driver
3549          * may hold the resource in the Timeout field.
3550          * If the resource is held by someone else, the command completes with
3551          * busy return value and the timeout field indicates the maximum time
3552          * the current owner of the resource has to free it.
3553          */
3554         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3555                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3556
3557         return status;
3558 }
3559
3560 /**
3561  * i40e_aq_release_resource
3562  * @hw: pointer to the hw struct
3563  * @resource: resource id
3564  * @sdp_number: resource number
3565  * @cmd_details: pointer to command details structure or NULL
3566  *
3567  * release common resource using the admin queue commands
3568  **/
3569 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3570                                 enum i40e_aq_resources_ids resource,
3571                                 u8 sdp_number,
3572                                 struct i40e_asq_cmd_details *cmd_details)
3573 {
3574         struct i40e_aq_desc desc;
3575         struct i40e_aqc_request_resource *cmd =
3576                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3577         enum i40e_status_code status;
3578
3579         DEBUGFUNC("i40e_aq_release_resource");
3580
3581         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3582
3583         cmd->resource_id = CPU_TO_LE16(resource);
3584         cmd->resource_number = CPU_TO_LE32(sdp_number);
3585
3586         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3587
3588         return status;
3589 }
3590
3591 /**
3592  * i40e_aq_read_nvm
3593  * @hw: pointer to the hw struct
3594  * @module_pointer: module pointer location in words from the NVM beginning
3595  * @offset: byte offset from the module beginning
3596  * @length: length of the section to be read (in bytes from the offset)
3597  * @data: command buffer (size [bytes] = length)
3598  * @last_command: tells if this is the last command in a series
3599  * @cmd_details: pointer to command details structure or NULL
3600  *
3601  * Read the NVM using the admin queue commands
3602  **/
3603 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3604                                 u32 offset, u16 length, void *data,
3605                                 bool last_command,
3606                                 struct i40e_asq_cmd_details *cmd_details)
3607 {
3608         struct i40e_aq_desc desc;
3609         struct i40e_aqc_nvm_update *cmd =
3610                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3611         enum i40e_status_code status;
3612
3613         DEBUGFUNC("i40e_aq_read_nvm");
3614
3615         /* In offset the highest byte must be zeroed. */
3616         if (offset & 0xFF000000) {
3617                 status = I40E_ERR_PARAM;
3618                 goto i40e_aq_read_nvm_exit;
3619         }
3620
3621         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3622
3623         /* If this is the last command in a series, set the proper flag. */
3624         if (last_command)
3625                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3626         cmd->module_pointer = module_pointer;
3627         cmd->offset = CPU_TO_LE32(offset);
3628         cmd->length = CPU_TO_LE16(length);
3629
3630         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3631         if (length > I40E_AQ_LARGE_BUF)
3632                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3633
3634         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3635
3636 i40e_aq_read_nvm_exit:
3637         return status;
3638 }
3639
3640 /**
3641  * i40e_aq_read_nvm_config - read an nvm config block
3642  * @hw: pointer to the hw struct
3643  * @cmd_flags: NVM access admin command bits
3644  * @field_id: field or feature id
3645  * @data: buffer for result
3646  * @buf_size: buffer size
3647  * @element_count: pointer to count of elements read by FW
3648  * @cmd_details: pointer to command details structure or NULL
3649  **/
3650 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3651                                 u8 cmd_flags, u32 field_id, void *data,
3652                                 u16 buf_size, u16 *element_count,
3653                                 struct i40e_asq_cmd_details *cmd_details)
3654 {
3655         struct i40e_aq_desc desc;
3656         struct i40e_aqc_nvm_config_read *cmd =
3657                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3658         enum i40e_status_code status;
3659
3660         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3661         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3662         if (buf_size > I40E_AQ_LARGE_BUF)
3663                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3664
3665         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3666         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3667         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3668                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3669         else
3670                 cmd->element_id_msw = 0;
3671
3672         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3673
3674         if (!status && element_count)
3675                 *element_count = LE16_TO_CPU(cmd->element_count);
3676
3677         return status;
3678 }
3679
3680 /**
3681  * i40e_aq_write_nvm_config - write an nvm config block
3682  * @hw: pointer to the hw struct
3683  * @cmd_flags: NVM access admin command bits
3684  * @data: buffer for result
3685  * @buf_size: buffer size
3686  * @element_count: count of elements to be written
3687  * @cmd_details: pointer to command details structure or NULL
3688  **/
3689 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3690                                 u8 cmd_flags, void *data, u16 buf_size,
3691                                 u16 element_count,
3692                                 struct i40e_asq_cmd_details *cmd_details)
3693 {
3694         struct i40e_aq_desc desc;
3695         struct i40e_aqc_nvm_config_write *cmd =
3696                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3697         enum i40e_status_code status;
3698
3699         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3700         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3701         if (buf_size > I40E_AQ_LARGE_BUF)
3702                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3703
3704         cmd->element_count = CPU_TO_LE16(element_count);
3705         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3706         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3707
3708         return status;
3709 }
3710
3711 /**
3712  * i40e_aq_nvm_update_in_process
3713  * @hw: pointer to the hw struct
3714  * @update_flow_state: True indicates that update flow starts, false that ends
3715  * @cmd_details: pointer to command details structure or NULL
3716  *
3717  * Indicate NVM update in process.
3718  **/
3719 enum i40e_status_code
3720 i40e_aq_nvm_update_in_process(struct i40e_hw *hw,
3721                               bool update_flow_state,
3722                               struct i40e_asq_cmd_details *cmd_details)
3723 {
3724         struct i40e_aq_desc desc;
3725         struct i40e_aqc_nvm_update_in_process *cmd =
3726                 (struct i40e_aqc_nvm_update_in_process *)&desc.params.raw;
3727         enum i40e_status_code status;
3728
3729         i40e_fill_default_direct_cmd_desc(&desc,
3730                                           i40e_aqc_opc_nvm_update_in_process);
3731
3732         cmd->command = I40E_AQ_UPDATE_FLOW_END;
3733
3734         if (update_flow_state)
3735                 cmd->command |= I40E_AQ_UPDATE_FLOW_START;
3736
3737         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3738
3739         return status;
3740 }
3741
3742 /**
3743  * i40e_aq_min_rollback_rev_update - triggers an ow after update
3744  * @hw: pointer to the hw struct
3745  * @mode: opt-in mode, 1b for single module update, 0b for bulk update
3746  * @module: module to be updated. Ignored if mode is 0b
3747  * @min_rrev: value of the new minimal version. Ignored if mode is 0b
3748  * @cmd_details: pointer to command details structure or NULL
3749  **/
3750 enum i40e_status_code
3751 i40e_aq_min_rollback_rev_update(struct i40e_hw *hw, u8 mode, u8 module,
3752                                 u32 min_rrev,
3753                                 struct i40e_asq_cmd_details *cmd_details)
3754 {
3755         struct i40e_aq_desc desc;
3756         struct i40e_aqc_rollback_revision_update *cmd =
3757                 (struct i40e_aqc_rollback_revision_update *)&desc.params.raw;
3758         enum i40e_status_code status;
3759
3760         i40e_fill_default_direct_cmd_desc(&desc,
3761                 i40e_aqc_opc_rollback_revision_update);
3762         cmd->optin_mode = mode;
3763         cmd->module_selected = module;
3764         cmd->min_rrev = min_rrev;
3765
3766         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3767
3768         return status;
3769 }
3770
3771 /**
3772  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3773  * @hw: pointer to the hw struct
3774  * @buff: buffer for result
3775  * @buff_size: buffer size
3776  * @cmd_details: pointer to command details structure or NULL
3777  **/
3778 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3779                                 void *buff, u16 buff_size,
3780                                 struct i40e_asq_cmd_details *cmd_details)
3781 {
3782         struct i40e_aq_desc desc;
3783         enum i40e_status_code status;
3784
3785         UNREFERENCED_2PARAMETER(buff, buff_size);
3786
3787         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3788         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3789         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3790                 status = I40E_ERR_NOT_IMPLEMENTED;
3791
3792         return status;
3793 }
3794
3795 /**
3796  * i40e_aq_erase_nvm
3797  * @hw: pointer to the hw struct
3798  * @module_pointer: module pointer location in words from the NVM beginning
3799  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3800  * @length: length of the section to be erased (expressed in 4 KB)
3801  * @last_command: tells if this is the last command in a series
3802  * @cmd_details: pointer to command details structure or NULL
3803  *
3804  * Erase the NVM sector using the admin queue commands
3805  **/
3806 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3807                                 u32 offset, u16 length, bool last_command,
3808                                 struct i40e_asq_cmd_details *cmd_details)
3809 {
3810         struct i40e_aq_desc desc;
3811         struct i40e_aqc_nvm_update *cmd =
3812                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3813         enum i40e_status_code status;
3814
3815         DEBUGFUNC("i40e_aq_erase_nvm");
3816
3817         /* In offset the highest byte must be zeroed. */
3818         if (offset & 0xFF000000) {
3819                 status = I40E_ERR_PARAM;
3820                 goto i40e_aq_erase_nvm_exit;
3821         }
3822
3823         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3824
3825         /* If this is the last command in a series, set the proper flag. */
3826         if (last_command)
3827                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3828         cmd->module_pointer = module_pointer;
3829         cmd->offset = CPU_TO_LE32(offset);
3830         cmd->length = CPU_TO_LE16(length);
3831
3832         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3833
3834 i40e_aq_erase_nvm_exit:
3835         return status;
3836 }
3837
3838 /**
3839  * i40e_parse_discover_capabilities
3840  * @hw: pointer to the hw struct
3841  * @buff: pointer to a buffer containing device/function capability records
3842  * @cap_count: number of capability records in the list
3843  * @list_type_opc: type of capabilities list to parse
3844  *
3845  * Parse the device/function capabilities list.
3846  **/
3847 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3848                                      u32 cap_count,
3849                                      enum i40e_admin_queue_opc list_type_opc)
3850 {
3851         struct i40e_aqc_list_capabilities_element_resp *cap;
3852         u32 valid_functions, num_functions;
3853         u32 number, logical_id, phys_id;
3854         struct i40e_hw_capabilities *p;
3855         enum i40e_status_code status;
3856         u16 id, ocp_cfg_word0;
3857         u8 major_rev;
3858         u32 i = 0;
3859
3860         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3861
3862         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3863                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3864         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3865                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3866         else
3867                 return;
3868
3869         for (i = 0; i < cap_count; i++, cap++) {
3870                 id = LE16_TO_CPU(cap->id);
3871                 number = LE32_TO_CPU(cap->number);
3872                 logical_id = LE32_TO_CPU(cap->logical_id);
3873                 phys_id = LE32_TO_CPU(cap->phys_id);
3874                 major_rev = cap->major_rev;
3875
3876                 switch (id) {
3877                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3878                         p->switch_mode = number;
3879                         i40e_debug(hw, I40E_DEBUG_INIT,
3880                                    "HW Capability: Switch mode = %d\n",
3881                                    p->switch_mode);
3882                         break;
3883                 case I40E_AQ_CAP_ID_MNG_MODE:
3884                         p->management_mode = number;
3885                         if (major_rev > 1) {
3886                                 p->mng_protocols_over_mctp = logical_id;
3887                                 i40e_debug(hw, I40E_DEBUG_INIT,
3888                                            "HW Capability: Protocols over MCTP = %d\n",
3889                                            p->mng_protocols_over_mctp);
3890                         } else {
3891                                 p->mng_protocols_over_mctp = 0;
3892                         }
3893                         i40e_debug(hw, I40E_DEBUG_INIT,
3894                                    "HW Capability: Management Mode = %d\n",
3895                                    p->management_mode);
3896                         break;
3897                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3898                         p->npar_enable = number;
3899                         i40e_debug(hw, I40E_DEBUG_INIT,
3900                                    "HW Capability: NPAR enable = %d\n",
3901                                    p->npar_enable);
3902                         break;
3903                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3904                         p->os2bmc = number;
3905                         i40e_debug(hw, I40E_DEBUG_INIT,
3906                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3907                         break;
3908                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3909                         p->valid_functions = number;
3910                         i40e_debug(hw, I40E_DEBUG_INIT,
3911                                    "HW Capability: Valid Functions = %d\n",
3912                                    p->valid_functions);
3913                         break;
3914                 case I40E_AQ_CAP_ID_SRIOV:
3915                         if (number == 1)
3916                                 p->sr_iov_1_1 = true;
3917                         i40e_debug(hw, I40E_DEBUG_INIT,
3918                                    "HW Capability: SR-IOV = %d\n",
3919                                    p->sr_iov_1_1);
3920                         break;
3921                 case I40E_AQ_CAP_ID_VF:
3922                         p->num_vfs = number;
3923                         p->vf_base_id = logical_id;
3924                         i40e_debug(hw, I40E_DEBUG_INIT,
3925                                    "HW Capability: VF count = %d\n",
3926                                    p->num_vfs);
3927                         i40e_debug(hw, I40E_DEBUG_INIT,
3928                                    "HW Capability: VF base_id = %d\n",
3929                                    p->vf_base_id);
3930                         break;
3931                 case I40E_AQ_CAP_ID_VMDQ:
3932                         if (number == 1)
3933                                 p->vmdq = true;
3934                         i40e_debug(hw, I40E_DEBUG_INIT,
3935                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3936                         break;
3937                 case I40E_AQ_CAP_ID_8021QBG:
3938                         if (number == 1)
3939                                 p->evb_802_1_qbg = true;
3940                         i40e_debug(hw, I40E_DEBUG_INIT,
3941                                    "HW Capability: 802.1Qbg = %d\n", number);
3942                         break;
3943                 case I40E_AQ_CAP_ID_8021QBR:
3944                         if (number == 1)
3945                                 p->evb_802_1_qbh = true;
3946                         i40e_debug(hw, I40E_DEBUG_INIT,
3947                                    "HW Capability: 802.1Qbh = %d\n", number);
3948                         break;
3949                 case I40E_AQ_CAP_ID_VSI:
3950                         p->num_vsis = number;
3951                         i40e_debug(hw, I40E_DEBUG_INIT,
3952                                    "HW Capability: VSI count = %d\n",
3953                                    p->num_vsis);
3954                         break;
3955                 case I40E_AQ_CAP_ID_DCB:
3956                         if (number == 1) {
3957                                 p->dcb = true;
3958                                 p->enabled_tcmap = logical_id;
3959                                 p->maxtc = phys_id;
3960                         }
3961                         i40e_debug(hw, I40E_DEBUG_INIT,
3962                                    "HW Capability: DCB = %d\n", p->dcb);
3963                         i40e_debug(hw, I40E_DEBUG_INIT,
3964                                    "HW Capability: TC Mapping = %d\n",
3965                                    logical_id);
3966                         i40e_debug(hw, I40E_DEBUG_INIT,
3967                                    "HW Capability: TC Max = %d\n", p->maxtc);
3968                         break;
3969                 case I40E_AQ_CAP_ID_FCOE:
3970                         if (number == 1)
3971                                 p->fcoe = true;
3972                         i40e_debug(hw, I40E_DEBUG_INIT,
3973                                    "HW Capability: FCOE = %d\n", p->fcoe);
3974                         break;
3975                 case I40E_AQ_CAP_ID_ISCSI:
3976                         if (number == 1)
3977                                 p->iscsi = true;
3978                         i40e_debug(hw, I40E_DEBUG_INIT,
3979                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3980                         break;
3981                 case I40E_AQ_CAP_ID_RSS:
3982                         p->rss = true;
3983                         p->rss_table_size = number;
3984                         p->rss_table_entry_width = logical_id;
3985                         i40e_debug(hw, I40E_DEBUG_INIT,
3986                                    "HW Capability: RSS = %d\n", p->rss);
3987                         i40e_debug(hw, I40E_DEBUG_INIT,
3988                                    "HW Capability: RSS table size = %d\n",
3989                                    p->rss_table_size);
3990                         i40e_debug(hw, I40E_DEBUG_INIT,
3991                                    "HW Capability: RSS table width = %d\n",
3992                                    p->rss_table_entry_width);
3993                         break;
3994                 case I40E_AQ_CAP_ID_RXQ:
3995                         p->num_rx_qp = number;
3996                         p->base_queue = phys_id;
3997                         i40e_debug(hw, I40E_DEBUG_INIT,
3998                                    "HW Capability: Rx QP = %d\n", number);
3999                         i40e_debug(hw, I40E_DEBUG_INIT,
4000                                    "HW Capability: base_queue = %d\n",
4001                                    p->base_queue);
4002                         break;
4003                 case I40E_AQ_CAP_ID_TXQ:
4004                         p->num_tx_qp = number;
4005                         p->base_queue = phys_id;
4006                         i40e_debug(hw, I40E_DEBUG_INIT,
4007                                    "HW Capability: Tx QP = %d\n", number);
4008                         i40e_debug(hw, I40E_DEBUG_INIT,
4009                                    "HW Capability: base_queue = %d\n",
4010                                    p->base_queue);
4011                         break;
4012                 case I40E_AQ_CAP_ID_MSIX:
4013                         p->num_msix_vectors = number;
4014                         i40e_debug(hw, I40E_DEBUG_INIT,
4015                                    "HW Capability: MSIX vector count = %d\n",
4016                                    p->num_msix_vectors);
4017                         break;
4018                 case I40E_AQ_CAP_ID_VF_MSIX:
4019                         p->num_msix_vectors_vf = number;
4020                         i40e_debug(hw, I40E_DEBUG_INIT,
4021                                    "HW Capability: MSIX VF vector count = %d\n",
4022                                    p->num_msix_vectors_vf);
4023                         break;
4024                 case I40E_AQ_CAP_ID_FLEX10:
4025                         if (major_rev == 1) {
4026                                 if (number == 1) {
4027                                         p->flex10_enable = true;
4028                                         p->flex10_capable = true;
4029                                 }
4030                         } else {
4031                                 /* Capability revision >= 2 */
4032                                 if (number & 1)
4033                                         p->flex10_enable = true;
4034                                 if (number & 2)
4035                                         p->flex10_capable = true;
4036                         }
4037                         p->flex10_mode = logical_id;
4038                         p->flex10_status = phys_id;
4039                         i40e_debug(hw, I40E_DEBUG_INIT,
4040                                    "HW Capability: Flex10 mode = %d\n",
4041                                    p->flex10_mode);
4042                         i40e_debug(hw, I40E_DEBUG_INIT,
4043                                    "HW Capability: Flex10 status = %d\n",
4044                                    p->flex10_status);
4045                         break;
4046                 case I40E_AQ_CAP_ID_CEM:
4047                         if (number == 1)
4048                                 p->mgmt_cem = true;
4049                         i40e_debug(hw, I40E_DEBUG_INIT,
4050                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
4051                         break;
4052                 case I40E_AQ_CAP_ID_IWARP:
4053                         if (number == 1)
4054                                 p->iwarp = true;
4055                         i40e_debug(hw, I40E_DEBUG_INIT,
4056                                    "HW Capability: iWARP = %d\n", p->iwarp);
4057                         break;
4058                 case I40E_AQ_CAP_ID_LED:
4059                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
4060                                 p->led[phys_id] = true;
4061                         i40e_debug(hw, I40E_DEBUG_INIT,
4062                                    "HW Capability: LED - PIN %d\n", phys_id);
4063                         break;
4064                 case I40E_AQ_CAP_ID_SDP:
4065                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
4066                                 p->sdp[phys_id] = true;
4067                         i40e_debug(hw, I40E_DEBUG_INIT,
4068                                    "HW Capability: SDP - PIN %d\n", phys_id);
4069                         break;
4070                 case I40E_AQ_CAP_ID_MDIO:
4071                         if (number == 1) {
4072                                 p->mdio_port_num = phys_id;
4073                                 p->mdio_port_mode = logical_id;
4074                         }
4075                         i40e_debug(hw, I40E_DEBUG_INIT,
4076                                    "HW Capability: MDIO port number = %d\n",
4077                                    p->mdio_port_num);
4078                         i40e_debug(hw, I40E_DEBUG_INIT,
4079                                    "HW Capability: MDIO port mode = %d\n",
4080                                    p->mdio_port_mode);
4081                         break;
4082                 case I40E_AQ_CAP_ID_1588:
4083                         if (number == 1)
4084                                 p->ieee_1588 = true;
4085                         i40e_debug(hw, I40E_DEBUG_INIT,
4086                                    "HW Capability: IEEE 1588 = %d\n",
4087                                    p->ieee_1588);
4088                         break;
4089                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
4090                         p->fd = true;
4091                         p->fd_filters_guaranteed = number;
4092                         p->fd_filters_best_effort = logical_id;
4093                         i40e_debug(hw, I40E_DEBUG_INIT,
4094                                    "HW Capability: Flow Director = 1\n");
4095                         i40e_debug(hw, I40E_DEBUG_INIT,
4096                                    "HW Capability: Guaranteed FD filters = %d\n",
4097                                    p->fd_filters_guaranteed);
4098                         break;
4099                 case I40E_AQ_CAP_ID_WSR_PROT:
4100                         p->wr_csr_prot = (u64)number;
4101                         p->wr_csr_prot |= (u64)logical_id << 32;
4102                         i40e_debug(hw, I40E_DEBUG_INIT,
4103                                    "HW Capability: wr_csr_prot = 0x%" PRIX64 "\n\n",
4104                                    (p->wr_csr_prot & 0xffff));
4105                         break;
4106                 case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS:
4107                         p->dis_unused_ports = (bool)number;
4108                         i40e_debug(hw, I40E_DEBUG_INIT,
4109                                    "HW Capability: dis_unused_ports = %d\n\n",
4110                                    p->dis_unused_ports);
4111                         break;
4112                 case I40E_AQ_CAP_ID_NVM_MGMT:
4113                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
4114                                 p->sec_rev_disabled = true;
4115                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
4116                                 p->update_disabled = true;
4117                         break;
4118                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
4119                         hw->num_wol_proxy_filters = (u16)number;
4120                         hw->wol_proxy_vsi_seid = (u16)logical_id;
4121                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
4122                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
4123                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
4124                         else
4125                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
4126                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
4127                         i40e_debug(hw, I40E_DEBUG_INIT,
4128                                    "HW Capability: WOL proxy filters = %d\n",
4129                                    hw->num_wol_proxy_filters);
4130                         break;
4131                 default:
4132                         break;
4133                 }
4134         }
4135
4136         if (p->fcoe)
4137                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4138
4139         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4140         p->fcoe = false;
4141
4142         /* count the enabled ports (aka the "not disabled" ports) */
4143         hw->num_ports = 0;
4144         for (i = 0; i < 4; i++) {
4145                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4146                 u64 port_cfg = 0;
4147
4148                 /* use AQ read to get the physical register offset instead
4149                  * of the port relative offset
4150                  */
4151                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4152                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4153                         hw->num_ports++;
4154         }
4155
4156         /* OCP cards case: if a mezz is removed the ethernet port is at
4157          * disabled state in PRTGEN_CNF register. Additional NVM read is
4158          * needed in order to check if we are dealing with OCP card.
4159          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4160          * physical ports results in wrong partition id calculation and thus
4161          * not supporting WoL.
4162          */
4163         if (hw->mac.type == I40E_MAC_X722) {
4164                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4165                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4166                                                   2 * I40E_SR_OCP_CFG_WORD0,
4167                                                   sizeof(ocp_cfg_word0),
4168                                                   &ocp_cfg_word0, true, NULL);
4169                         if (status == I40E_SUCCESS &&
4170                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4171                                 hw->num_ports = 4;
4172                         i40e_release_nvm(hw);
4173                 }
4174         }
4175
4176         valid_functions = p->valid_functions;
4177         num_functions = 0;
4178         while (valid_functions) {
4179                 if (valid_functions & 1)
4180                         num_functions++;
4181                 valid_functions >>= 1;
4182         }
4183
4184         /* partition id is 1-based, and functions are evenly spread
4185          * across the ports as partitions
4186          */
4187         if (hw->num_ports != 0) {
4188                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4189                 hw->num_partitions = num_functions / hw->num_ports;
4190         }
4191
4192         /* additional HW specific goodies that might
4193          * someday be HW version specific
4194          */
4195         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4196 }
4197
4198 /**
4199  * i40e_aq_discover_capabilities
4200  * @hw: pointer to the hw struct
4201  * @buff: a virtual buffer to hold the capabilities
4202  * @buff_size: Size of the virtual buffer
4203  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4204  * @list_type_opc: capabilities type to discover - pass in the command opcode
4205  * @cmd_details: pointer to command details structure or NULL
4206  *
4207  * Get the device capabilities descriptions from the firmware
4208  **/
4209 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4210                                 void *buff, u16 buff_size, u16 *data_size,
4211                                 enum i40e_admin_queue_opc list_type_opc,
4212                                 struct i40e_asq_cmd_details *cmd_details)
4213 {
4214         struct i40e_aqc_list_capabilites *cmd;
4215         struct i40e_aq_desc desc;
4216         enum i40e_status_code status = I40E_SUCCESS;
4217
4218         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4219
4220         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4221                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4222                 status = I40E_ERR_PARAM;
4223                 goto exit;
4224         }
4225
4226         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4227
4228         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4229         if (buff_size > I40E_AQ_LARGE_BUF)
4230                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4231
4232         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4233         *data_size = LE16_TO_CPU(desc.datalen);
4234
4235         if (status)
4236                 goto exit;
4237
4238         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4239                                          list_type_opc);
4240
4241 exit:
4242         return status;
4243 }
4244
4245 /**
4246  * i40e_aq_update_nvm
4247  * @hw: pointer to the hw struct
4248  * @module_pointer: module pointer location in words from the NVM beginning
4249  * @offset: byte offset from the module beginning
4250  * @length: length of the section to be written (in bytes from the offset)
4251  * @data: command buffer (size [bytes] = length)
4252  * @last_command: tells if this is the last command in a series
4253  * @preservation_flags: Preservation mode flags
4254  * @cmd_details: pointer to command details structure or NULL
4255  *
4256  * Update the NVM using the admin queue commands
4257  **/
4258 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4259                                 u32 offset, u16 length, void *data,
4260                                 bool last_command, u8 preservation_flags,
4261                                 struct i40e_asq_cmd_details *cmd_details)
4262 {
4263         struct i40e_aq_desc desc;
4264         struct i40e_aqc_nvm_update *cmd =
4265                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4266         enum i40e_status_code status;
4267
4268         DEBUGFUNC("i40e_aq_update_nvm");
4269
4270         /* In offset the highest byte must be zeroed. */
4271         if (offset & 0xFF000000) {
4272                 status = I40E_ERR_PARAM;
4273                 goto i40e_aq_update_nvm_exit;
4274         }
4275
4276         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4277
4278         /* If this is the last command in a series, set the proper flag. */
4279         if (last_command)
4280                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4281         if (hw->mac.type == I40E_MAC_X722) {
4282                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4283                         cmd->command_flags |=
4284                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4285                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4286                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4287                         cmd->command_flags |=
4288                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4289                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4290         }
4291         cmd->module_pointer = module_pointer;
4292         cmd->offset = CPU_TO_LE32(offset);
4293         cmd->length = CPU_TO_LE16(length);
4294
4295         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4296         if (length > I40E_AQ_LARGE_BUF)
4297                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4298
4299         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4300
4301 i40e_aq_update_nvm_exit:
4302         return status;
4303 }
4304
4305 /**
4306  * i40e_aq_rearrange_nvm
4307  * @hw: pointer to the hw struct
4308  * @rearrange_nvm: defines direction of rearrangement
4309  * @cmd_details: pointer to command details structure or NULL
4310  *
4311  * Rearrange NVM structure, available only for transition FW
4312  **/
4313 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4314                                 u8 rearrange_nvm,
4315                                 struct i40e_asq_cmd_details *cmd_details)
4316 {
4317         struct i40e_aqc_nvm_update *cmd;
4318         enum i40e_status_code status;
4319         struct i40e_aq_desc desc;
4320
4321         DEBUGFUNC("i40e_aq_rearrange_nvm");
4322
4323         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4324
4325         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4326
4327         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4328                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4329
4330         if (!rearrange_nvm) {
4331                 status = I40E_ERR_PARAM;
4332                 goto i40e_aq_rearrange_nvm_exit;
4333         }
4334
4335         cmd->command_flags |= rearrange_nvm;
4336         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4337
4338 i40e_aq_rearrange_nvm_exit:
4339         return status;
4340 }
4341
4342 /**
4343  * i40e_aq_get_lldp_mib
4344  * @hw: pointer to the hw struct
4345  * @bridge_type: type of bridge requested
4346  * @mib_type: Local, Remote or both Local and Remote MIBs
4347  * @buff: pointer to a user supplied buffer to store the MIB block
4348  * @buff_size: size of the buffer (in bytes)
4349  * @local_len : length of the returned Local LLDP MIB
4350  * @remote_len: length of the returned Remote LLDP MIB
4351  * @cmd_details: pointer to command details structure or NULL
4352  *
4353  * Requests the complete LLDP MIB (entire packet).
4354  **/
4355 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4356                                 u8 mib_type, void *buff, u16 buff_size,
4357                                 u16 *local_len, u16 *remote_len,
4358                                 struct i40e_asq_cmd_details *cmd_details)
4359 {
4360         struct i40e_aq_desc desc;
4361         struct i40e_aqc_lldp_get_mib *cmd =
4362                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4363         struct i40e_aqc_lldp_get_mib *resp =
4364                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4365         enum i40e_status_code status;
4366
4367         if (buff_size == 0 || !buff)
4368                 return I40E_ERR_PARAM;
4369
4370         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4371         /* Indirect Command */
4372         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4373
4374         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4375         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4376                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4377
4378         desc.datalen = CPU_TO_LE16(buff_size);
4379
4380         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4381         if (buff_size > I40E_AQ_LARGE_BUF)
4382                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4383
4384         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4385         if (!status) {
4386                 if (local_len != NULL)
4387                         *local_len = LE16_TO_CPU(resp->local_len);
4388                 if (remote_len != NULL)
4389                         *remote_len = LE16_TO_CPU(resp->remote_len);
4390         }
4391
4392         return status;
4393 }
4394
4395  /**
4396  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4397  * @hw: pointer to the hw struct
4398  * @mib_type: Local, Remote or both Local and Remote MIBs
4399  * @buff: pointer to a user supplied buffer to store the MIB block
4400  * @buff_size: size of the buffer (in bytes)
4401  * @cmd_details: pointer to command details structure or NULL
4402  *
4403  * Set the LLDP MIB.
4404  **/
4405 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4406                                 u8 mib_type, void *buff, u16 buff_size,
4407                                 struct i40e_asq_cmd_details *cmd_details)
4408 {
4409         struct i40e_aq_desc desc;
4410         struct i40e_aqc_lldp_set_local_mib *cmd =
4411                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4412         enum i40e_status_code status;
4413
4414         if (buff_size == 0 || !buff)
4415                 return I40E_ERR_PARAM;
4416
4417         i40e_fill_default_direct_cmd_desc(&desc,
4418                                 i40e_aqc_opc_lldp_set_local_mib);
4419         /* Indirect Command */
4420         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4421         if (buff_size > I40E_AQ_LARGE_BUF)
4422                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4423         desc.datalen = CPU_TO_LE16(buff_size);
4424
4425         cmd->type = mib_type;
4426         cmd->length = CPU_TO_LE16(buff_size);
4427         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4428         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4429
4430         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4431         return status;
4432 }
4433
4434 /**
4435  * i40e_aq_cfg_lldp_mib_change_event
4436  * @hw: pointer to the hw struct
4437  * @enable_update: Enable or Disable event posting
4438  * @cmd_details: pointer to command details structure or NULL
4439  *
4440  * Enable or Disable posting of an event on ARQ when LLDP MIB
4441  * associated with the interface changes
4442  **/
4443 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4444                                 bool enable_update,
4445                                 struct i40e_asq_cmd_details *cmd_details)
4446 {
4447         struct i40e_aq_desc desc;
4448         struct i40e_aqc_lldp_update_mib *cmd =
4449                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4450         enum i40e_status_code status;
4451
4452         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4453
4454         if (!enable_update)
4455                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4456
4457         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4458
4459         return status;
4460 }
4461
4462 /**
4463  * i40e_aq_restore_lldp
4464  * @hw: pointer to the hw struct
4465  * @setting: pointer to factory setting variable or NULL
4466  * @restore: True if factory settings should be restored
4467  * @cmd_details: pointer to command details structure or NULL
4468  *
4469  * Restore LLDP Agent factory settings if @restore set to True. In other case
4470  * only returns factory setting in AQ response.
4471  **/
4472 enum i40e_status_code
4473 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4474                      struct i40e_asq_cmd_details *cmd_details)
4475 {
4476         struct i40e_aq_desc desc;
4477         struct i40e_aqc_lldp_restore *cmd =
4478                 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4479         enum i40e_status_code status;
4480
4481         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4482                 i40e_debug(hw, I40E_DEBUG_ALL,
4483                            "Restore LLDP not supported by current FW version.\n");
4484                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4485         }
4486
4487         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4488
4489         if (restore)
4490                 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4491
4492         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4493
4494         if (setting)
4495                 *setting = cmd->command & 1;
4496
4497         return status;
4498 }
4499
4500 /**
4501  * i40e_aq_stop_lldp
4502  * @hw: pointer to the hw struct
4503  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4504  * @persist: True if stop of LLDP should be persistent across power cycles
4505  * @cmd_details: pointer to command details structure or NULL
4506  *
4507  * Stop or Shutdown the embedded LLDP Agent
4508  **/
4509 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4510                                 bool persist,
4511                                 struct i40e_asq_cmd_details *cmd_details)
4512 {
4513         struct i40e_aq_desc desc;
4514         struct i40e_aqc_lldp_stop *cmd =
4515                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4516         enum i40e_status_code status;
4517
4518         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4519
4520         if (shutdown_agent)
4521                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4522
4523         if (persist) {
4524                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4525                         cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4526                 else
4527                         i40e_debug(hw, I40E_DEBUG_ALL,
4528                                    "Persistent Stop LLDP not supported by current FW version.\n");
4529         }
4530
4531         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4532
4533         return status;
4534 }
4535
4536 /**
4537  * i40e_aq_start_lldp
4538  * @hw: pointer to the hw struct
4539  * @persist: True if start of LLDP should be persistent across power cycles
4540  * @cmd_details: pointer to command details structure or NULL
4541  *
4542  * Start the embedded LLDP Agent on all ports.
4543  **/
4544 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4545                                 bool persist,
4546                                 struct i40e_asq_cmd_details *cmd_details)
4547 {
4548         struct i40e_aq_desc desc;
4549         struct i40e_aqc_lldp_start *cmd =
4550                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4551         enum i40e_status_code status;
4552
4553         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4554
4555         cmd->command = I40E_AQ_LLDP_AGENT_START;
4556
4557         if (persist) {
4558                 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4559                         cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4560                 else
4561                         i40e_debug(hw, I40E_DEBUG_ALL,
4562                                    "Persistent Start LLDP not supported by current FW version.\n");
4563         }
4564
4565         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4566
4567         return status;
4568 }
4569
4570 /**
4571  * i40e_aq_set_dcb_parameters
4572  * @hw: pointer to the hw struct
4573  * @cmd_details: pointer to command details structure or NULL
4574  * @dcb_enable: True if DCB configuration needs to be applied
4575  *
4576  **/
4577 enum i40e_status_code
4578 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4579                            struct i40e_asq_cmd_details *cmd_details)
4580 {
4581         struct i40e_aq_desc desc;
4582         struct i40e_aqc_set_dcb_parameters *cmd =
4583                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4584         enum i40e_status_code status;
4585
4586         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4587                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4588
4589         i40e_fill_default_direct_cmd_desc(&desc,
4590                                           i40e_aqc_opc_set_dcb_parameters);
4591
4592         if (dcb_enable) {
4593                 cmd->valid_flags = I40E_DCB_VALID;
4594                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4595         }
4596         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4597
4598         return status;
4599 }
4600
4601 /**
4602  * i40e_aq_get_cee_dcb_config
4603  * @hw: pointer to the hw struct
4604  * @buff: response buffer that stores CEE operational configuration
4605  * @buff_size: size of the buffer passed
4606  * @cmd_details: pointer to command details structure or NULL
4607  *
4608  * Get CEE DCBX mode operational configuration from firmware
4609  **/
4610 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4611                                 void *buff, u16 buff_size,
4612                                 struct i40e_asq_cmd_details *cmd_details)
4613 {
4614         struct i40e_aq_desc desc;
4615         enum i40e_status_code status;
4616
4617         if (buff_size == 0 || !buff)
4618                 return I40E_ERR_PARAM;
4619
4620         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4621
4622         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4623         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4624                                        cmd_details);
4625
4626         return status;
4627 }
4628
4629 /**
4630  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4631  * @hw: pointer to the hw struct
4632  * @start_agent: True if DCBx Agent needs to be Started
4633  *                              False if DCBx Agent needs to be Stopped
4634  * @cmd_details: pointer to command details structure or NULL
4635  *
4636  * Start/Stop the embedded dcbx Agent
4637  **/
4638 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4639                                 bool start_agent,
4640                                 struct i40e_asq_cmd_details *cmd_details)
4641 {
4642         struct i40e_aq_desc desc;
4643         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4644                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4645                                 &desc.params.raw;
4646         enum i40e_status_code status;
4647
4648         i40e_fill_default_direct_cmd_desc(&desc,
4649                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4650
4651         if (start_agent)
4652                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4653
4654         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4655
4656         return status;
4657 }
4658
4659 /**
4660  * i40e_aq_add_udp_tunnel
4661  * @hw: pointer to the hw struct
4662  * @udp_port: the UDP port to add in Host byte order
4663  * @protocol_index: protocol index type
4664  * @filter_index: pointer to filter index
4665  * @cmd_details: pointer to command details structure or NULL
4666  *
4667  * Note: Firmware expects the udp_port value to be in Little Endian format,
4668  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4669  * Little Endian order.
4670  **/
4671 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4672                                 u16 udp_port, u8 protocol_index,
4673                                 u8 *filter_index,
4674                                 struct i40e_asq_cmd_details *cmd_details)
4675 {
4676         struct i40e_aq_desc desc;
4677         struct i40e_aqc_add_udp_tunnel *cmd =
4678                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4679         struct i40e_aqc_del_udp_tunnel_completion *resp =
4680                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4681         enum i40e_status_code status;
4682
4683         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4684
4685         cmd->udp_port = CPU_TO_LE16(udp_port);
4686         cmd->protocol_type = protocol_index;
4687
4688         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4689
4690         if (!status && filter_index)
4691                 *filter_index = resp->index;
4692
4693         return status;
4694 }
4695
4696 /**
4697  * i40e_aq_del_udp_tunnel
4698  * @hw: pointer to the hw struct
4699  * @index: filter index
4700  * @cmd_details: pointer to command details structure or NULL
4701  **/
4702 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4703                                 struct i40e_asq_cmd_details *cmd_details)
4704 {
4705         struct i40e_aq_desc desc;
4706         struct i40e_aqc_remove_udp_tunnel *cmd =
4707                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4708         enum i40e_status_code status;
4709
4710         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4711
4712         cmd->index = index;
4713
4714         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4715
4716         return status;
4717 }
4718
4719 /**
4720  * i40e_aq_get_switch_resource_alloc (0x0204)
4721  * @hw: pointer to the hw struct
4722  * @num_entries: pointer to u8 to store the number of resource entries returned
4723  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4724  *        to store the resource information for all resource types.  Each
4725  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4726  * @count: size, in bytes, of the buffer provided
4727  * @cmd_details: pointer to command details structure or NULL
4728  *
4729  * Query the resources allocated to a function.
4730  **/
4731 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4732                         u8 *num_entries,
4733                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4734                         u16 count,
4735                         struct i40e_asq_cmd_details *cmd_details)
4736 {
4737         struct i40e_aq_desc desc;
4738         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4739                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4740         enum i40e_status_code status;
4741         u16 length = count * sizeof(*buf);
4742
4743         i40e_fill_default_direct_cmd_desc(&desc,
4744                                         i40e_aqc_opc_get_switch_resource_alloc);
4745
4746         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4747         if (length > I40E_AQ_LARGE_BUF)
4748                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4749
4750         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4751
4752         if (!status && num_entries)
4753                 *num_entries = cmd_resp->num_entries;
4754
4755         return status;
4756 }
4757
4758 /**
4759  * i40e_aq_delete_element - Delete switch element
4760  * @hw: pointer to the hw struct
4761  * @seid: the SEID to delete from the switch
4762  * @cmd_details: pointer to command details structure or NULL
4763  *
4764  * This deletes a switch element from the switch.
4765  **/
4766 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4767                                 struct i40e_asq_cmd_details *cmd_details)
4768 {
4769         struct i40e_aq_desc desc;
4770         struct i40e_aqc_switch_seid *cmd =
4771                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4772         enum i40e_status_code status;
4773
4774         if (seid == 0)
4775                 return I40E_ERR_PARAM;
4776
4777         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4778
4779         cmd->seid = CPU_TO_LE16(seid);
4780
4781         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4782
4783         return status;
4784 }
4785
4786 /**
4787  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4788  * @hw: pointer to the hw struct
4789  * @flags: component flags
4790  * @mac_seid: uplink seid (MAC SEID)
4791  * @vsi_seid: connected vsi seid
4792  * @ret_seid: seid of create pv component
4793  *
4794  * This instantiates an i40e port virtualizer with specified flags.
4795  * Depending on specified flags the port virtualizer can act as a
4796  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4797  */
4798 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4799                                        u16 mac_seid, u16 vsi_seid,
4800                                        u16 *ret_seid)
4801 {
4802         struct i40e_aq_desc desc;
4803         struct i40e_aqc_add_update_pv *cmd =
4804                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4805         struct i40e_aqc_add_update_pv_completion *resp =
4806                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4807         enum i40e_status_code status;
4808
4809         if (vsi_seid == 0)
4810                 return I40E_ERR_PARAM;
4811
4812         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4813         cmd->command_flags = CPU_TO_LE16(flags);
4814         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4815         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4816
4817         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4818         if (!status && ret_seid)
4819                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4820
4821         return status;
4822 }
4823
4824 /**
4825  * i40e_aq_add_tag - Add an S/E-tag
4826  * @hw: pointer to the hw struct
4827  * @direct_to_queue: should s-tag direct flow to a specific queue
4828  * @vsi_seid: VSI SEID to use this tag
4829  * @tag: value of the tag
4830  * @queue_num: queue number, only valid is direct_to_queue is true
4831  * @tags_used: return value, number of tags in use by this PF
4832  * @tags_free: return value, number of unallocated tags
4833  * @cmd_details: pointer to command details structure or NULL
4834  *
4835  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4836  * the number of tags allocated by the PF, and the number of unallocated
4837  * tags available.
4838  **/
4839 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4840                                 u16 vsi_seid, u16 tag, u16 queue_num,
4841                                 u16 *tags_used, u16 *tags_free,
4842                                 struct i40e_asq_cmd_details *cmd_details)
4843 {
4844         struct i40e_aq_desc desc;
4845         struct i40e_aqc_add_tag *cmd =
4846                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4847         struct i40e_aqc_add_remove_tag_completion *resp =
4848                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4849         enum i40e_status_code status;
4850
4851         if (vsi_seid == 0)
4852                 return I40E_ERR_PARAM;
4853
4854         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4855
4856         cmd->seid = CPU_TO_LE16(vsi_seid);
4857         cmd->tag = CPU_TO_LE16(tag);
4858         if (direct_to_queue) {
4859                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4860                 cmd->queue_number = CPU_TO_LE16(queue_num);
4861         }
4862
4863         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4864
4865         if (!status) {
4866                 if (tags_used != NULL)
4867                         *tags_used = LE16_TO_CPU(resp->tags_used);
4868                 if (tags_free != NULL)
4869                         *tags_free = LE16_TO_CPU(resp->tags_free);
4870         }
4871
4872         return status;
4873 }
4874
4875 /**
4876  * i40e_aq_remove_tag - Remove an S- or E-tag
4877  * @hw: pointer to the hw struct
4878  * @vsi_seid: VSI SEID this tag is associated with
4879  * @tag: value of the S-tag to delete
4880  * @tags_used: return value, number of tags in use by this PF
4881  * @tags_free: return value, number of unallocated tags
4882  * @cmd_details: pointer to command details structure or NULL
4883  *
4884  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4885  * the number of tags allocated by the PF, and the number of unallocated
4886  * tags available.
4887  **/
4888 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4889                                 u16 tag, u16 *tags_used, u16 *tags_free,
4890                                 struct i40e_asq_cmd_details *cmd_details)
4891 {
4892         struct i40e_aq_desc desc;
4893         struct i40e_aqc_remove_tag *cmd =
4894                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4895         struct i40e_aqc_add_remove_tag_completion *resp =
4896                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4897         enum i40e_status_code status;
4898
4899         if (vsi_seid == 0)
4900                 return I40E_ERR_PARAM;
4901
4902         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4903
4904         cmd->seid = CPU_TO_LE16(vsi_seid);
4905         cmd->tag = CPU_TO_LE16(tag);
4906
4907         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4908
4909         if (!status) {
4910                 if (tags_used != NULL)
4911                         *tags_used = LE16_TO_CPU(resp->tags_used);
4912                 if (tags_free != NULL)
4913                         *tags_free = LE16_TO_CPU(resp->tags_free);
4914         }
4915
4916         return status;
4917 }
4918
4919 /**
4920  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4921  * @hw: pointer to the hw struct
4922  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4923  * @etag: value of E-tag to add
4924  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4925  * @buf: address of indirect buffer
4926  * @tags_used: return value, number of E-tags in use by this port
4927  * @tags_free: return value, number of unallocated M-tags
4928  * @cmd_details: pointer to command details structure or NULL
4929  *
4930  * This associates a multicast E-tag to a port virtualizer.  It will return
4931  * the number of tags allocated by the PF, and the number of unallocated
4932  * tags available.
4933  *
4934  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4935  * num_tags_in_buf long.
4936  **/
4937 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4938                                 u16 etag, u8 num_tags_in_buf, void *buf,
4939                                 u16 *tags_used, u16 *tags_free,
4940                                 struct i40e_asq_cmd_details *cmd_details)
4941 {
4942         struct i40e_aq_desc desc;
4943         struct i40e_aqc_add_remove_mcast_etag *cmd =
4944                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4945         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4946            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4947         enum i40e_status_code status;
4948         u16 length = sizeof(u16) * num_tags_in_buf;
4949
4950         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4951                 return I40E_ERR_PARAM;
4952
4953         i40e_fill_default_direct_cmd_desc(&desc,
4954                                           i40e_aqc_opc_add_multicast_etag);
4955
4956         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4957         cmd->etag = CPU_TO_LE16(etag);
4958         cmd->num_unicast_etags = num_tags_in_buf;
4959
4960         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4961
4962         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4963
4964         if (!status) {
4965                 if (tags_used != NULL)
4966                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4967                 if (tags_free != NULL)
4968                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4969         }
4970
4971         return status;
4972 }
4973
4974 /**
4975  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4976  * @hw: pointer to the hw struct
4977  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4978  * @etag: value of the E-tag to remove
4979  * @tags_used: return value, number of tags in use by this port
4980  * @tags_free: return value, number of unallocated tags
4981  * @cmd_details: pointer to command details structure or NULL
4982  *
4983  * This deletes an E-tag from the port virtualizer.  It will return
4984  * the number of tags allocated by the port, and the number of unallocated
4985  * tags available.
4986  **/
4987 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4988                                 u16 etag, u16 *tags_used, u16 *tags_free,
4989                                 struct i40e_asq_cmd_details *cmd_details)
4990 {
4991         struct i40e_aq_desc desc;
4992         struct i40e_aqc_add_remove_mcast_etag *cmd =
4993                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4994         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4995            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4996         enum i40e_status_code status;
4997
4998
4999         if (pv_seid == 0)
5000                 return I40E_ERR_PARAM;
5001
5002         i40e_fill_default_direct_cmd_desc(&desc,
5003                                           i40e_aqc_opc_remove_multicast_etag);
5004
5005         cmd->pv_seid = CPU_TO_LE16(pv_seid);
5006         cmd->etag = CPU_TO_LE16(etag);
5007
5008         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5009
5010         if (!status) {
5011                 if (tags_used != NULL)
5012                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
5013                 if (tags_free != NULL)
5014                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
5015         }
5016
5017         return status;
5018 }
5019
5020 /**
5021  * i40e_aq_update_tag - Update an S/E-tag
5022  * @hw: pointer to the hw struct
5023  * @vsi_seid: VSI SEID using this S-tag
5024  * @old_tag: old tag value
5025  * @new_tag: new tag value
5026  * @tags_used: return value, number of tags in use by this PF
5027  * @tags_free: return value, number of unallocated tags
5028  * @cmd_details: pointer to command details structure or NULL
5029  *
5030  * This updates the value of the tag currently attached to this VSI
5031  * in the switch complex.  It will return the number of tags allocated
5032  * by the PF, and the number of unallocated tags available.
5033  **/
5034 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
5035                                 u16 old_tag, u16 new_tag, u16 *tags_used,
5036                                 u16 *tags_free,
5037                                 struct i40e_asq_cmd_details *cmd_details)
5038 {
5039         struct i40e_aq_desc desc;
5040         struct i40e_aqc_update_tag *cmd =
5041                 (struct i40e_aqc_update_tag *)&desc.params.raw;
5042         struct i40e_aqc_update_tag_completion *resp =
5043                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
5044         enum i40e_status_code status;
5045
5046         if (vsi_seid == 0)
5047                 return I40E_ERR_PARAM;
5048
5049         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
5050
5051         cmd->seid = CPU_TO_LE16(vsi_seid);
5052         cmd->old_tag = CPU_TO_LE16(old_tag);
5053         cmd->new_tag = CPU_TO_LE16(new_tag);
5054
5055         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5056
5057         if (!status) {
5058                 if (tags_used != NULL)
5059                         *tags_used = LE16_TO_CPU(resp->tags_used);
5060                 if (tags_free != NULL)
5061                         *tags_free = LE16_TO_CPU(resp->tags_free);
5062         }
5063
5064         return status;
5065 }
5066
5067 /**
5068  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5069  * @hw: pointer to the hw struct
5070  * @tcmap: TC map for request/release any ignore PFC condition
5071  * @request: request or release ignore PFC condition
5072  * @tcmap_ret: return TCs for which PFC is currently ignored
5073  * @cmd_details: pointer to command details structure or NULL
5074  *
5075  * This sends out request/release to ignore PFC condition for a TC.
5076  * It will return the TCs for which PFC is currently ignored.
5077  **/
5078 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5079                                 bool request, u8 *tcmap_ret,
5080                                 struct i40e_asq_cmd_details *cmd_details)
5081 {
5082         struct i40e_aq_desc desc;
5083         struct i40e_aqc_pfc_ignore *cmd_resp =
5084                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5085         enum i40e_status_code status;
5086
5087         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5088
5089         if (request)
5090                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5091
5092         cmd_resp->tc_bitmap = tcmap;
5093
5094         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5095
5096         if (!status) {
5097                 if (tcmap_ret != NULL)
5098                         *tcmap_ret = cmd_resp->tc_bitmap;
5099         }
5100
5101         return status;
5102 }
5103
5104 /**
5105  * i40e_aq_dcb_updated - DCB Updated Command
5106  * @hw: pointer to the hw struct
5107  * @cmd_details: pointer to command details structure or NULL
5108  *
5109  * When LLDP is handled in PF this command is used by the PF
5110  * to notify EMP that a DCB setting is modified.
5111  * When LLDP is handled in EMP this command is used by the PF
5112  * to notify EMP whenever one of the following parameters get
5113  * modified:
5114  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5115  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5116  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5117  * EMP will return when the shared RPB settings have been
5118  * recomputed and modified. The retval field in the descriptor
5119  * will be set to 0 when RPB is modified.
5120  **/
5121 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5122                                 struct i40e_asq_cmd_details *cmd_details)
5123 {
5124         struct i40e_aq_desc desc;
5125         enum i40e_status_code status;
5126
5127         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5128
5129         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5130
5131         return status;
5132 }
5133
5134 /**
5135  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5136  * @hw: pointer to the hw struct
5137  * @seid: defines the SEID of the switch for which the stats are requested
5138  * @vlan_id: the VLAN ID for which the statistics are requested
5139  * @stat_index: index of the statistics counters block assigned to this VLAN
5140  * @cmd_details: pointer to command details structure or NULL
5141  *
5142  * XL710 supports 128 smonVlanStats counters.This command is used to
5143  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5144  * switch.
5145  **/
5146 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5147                                 u16 vlan_id, u16 *stat_index,
5148                                 struct i40e_asq_cmd_details *cmd_details)
5149 {
5150         struct i40e_aq_desc desc;
5151         struct i40e_aqc_add_remove_statistics *cmd_resp =
5152                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5153         enum i40e_status_code status;
5154
5155         if ((seid == 0) || (stat_index == NULL))
5156                 return I40E_ERR_PARAM;
5157
5158         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5159
5160         cmd_resp->seid = CPU_TO_LE16(seid);
5161         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5162
5163         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5164
5165         if (!status && stat_index)
5166                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5167
5168         return status;
5169 }
5170
5171 /**
5172  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5173  * @hw: pointer to the hw struct
5174  * @seid: defines the SEID of the switch for which the stats are requested
5175  * @vlan_id: the VLAN ID for which the statistics are requested
5176  * @stat_index: index of the statistics counters block assigned to this VLAN
5177  * @cmd_details: pointer to command details structure or NULL
5178  *
5179  * XL710 supports 128 smonVlanStats counters.This command is used to
5180  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5181  * switch.
5182  **/
5183 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5184                                 u16 vlan_id, u16 stat_index,
5185                                 struct i40e_asq_cmd_details *cmd_details)
5186 {
5187         struct i40e_aq_desc desc;
5188         struct i40e_aqc_add_remove_statistics *cmd =
5189                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5190         enum i40e_status_code status;
5191
5192         if (seid == 0)
5193                 return I40E_ERR_PARAM;
5194
5195         i40e_fill_default_direct_cmd_desc(&desc,
5196                                           i40e_aqc_opc_remove_statistics);
5197
5198         cmd->seid = CPU_TO_LE16(seid);
5199         cmd->vlan  = CPU_TO_LE16(vlan_id);
5200         cmd->stat_index = CPU_TO_LE16(stat_index);
5201
5202         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5203
5204         return status;
5205 }
5206
5207 /**
5208  * i40e_aq_set_port_parameters - set physical port parameters.
5209  * @hw: pointer to the hw struct
5210  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5211  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5212  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5213  * @double_vlan: if set double VLAN is enabled
5214  * @cmd_details: pointer to command details structure or NULL
5215  **/
5216 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5217                                 u16 bad_frame_vsi, bool save_bad_pac,
5218                                 bool pad_short_pac, bool double_vlan,
5219                                 struct i40e_asq_cmd_details *cmd_details)
5220 {
5221         struct i40e_aqc_set_port_parameters *cmd;
5222         enum i40e_status_code status;
5223         struct i40e_aq_desc desc;
5224         u16 command_flags = 0;
5225
5226         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5227
5228         i40e_fill_default_direct_cmd_desc(&desc,
5229                                           i40e_aqc_opc_set_port_parameters);
5230
5231         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5232         if (save_bad_pac)
5233                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5234         if (pad_short_pac)
5235                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5236         if (double_vlan)
5237                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5238         cmd->command_flags = CPU_TO_LE16(command_flags);
5239
5240         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5241
5242         return status;
5243 }
5244
5245 /**
5246  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5247  * @hw: pointer to the hw struct
5248  * @seid: seid for the physical port/switching component/vsi
5249  * @buff: Indirect buffer to hold data parameters and response
5250  * @buff_size: Indirect buffer size
5251  * @opcode: Tx scheduler AQ command opcode
5252  * @cmd_details: pointer to command details structure or NULL
5253  *
5254  * Generic command handler for Tx scheduler AQ commands
5255  **/
5256 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5257                                 void *buff, u16 buff_size,
5258                                  enum i40e_admin_queue_opc opcode,
5259                                 struct i40e_asq_cmd_details *cmd_details)
5260 {
5261         struct i40e_aq_desc desc;
5262         struct i40e_aqc_tx_sched_ind *cmd =
5263                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5264         enum i40e_status_code status;
5265         bool cmd_param_flag = false;
5266
5267         switch (opcode) {
5268         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5269         case i40e_aqc_opc_configure_vsi_tc_bw:
5270         case i40e_aqc_opc_enable_switching_comp_ets:
5271         case i40e_aqc_opc_modify_switching_comp_ets:
5272         case i40e_aqc_opc_disable_switching_comp_ets:
5273         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5274         case i40e_aqc_opc_configure_switching_comp_bw_config:
5275                 cmd_param_flag = true;
5276                 break;
5277         case i40e_aqc_opc_query_vsi_bw_config:
5278         case i40e_aqc_opc_query_vsi_ets_sla_config:
5279         case i40e_aqc_opc_query_switching_comp_ets_config:
5280         case i40e_aqc_opc_query_port_ets_config:
5281         case i40e_aqc_opc_query_switching_comp_bw_config:
5282                 cmd_param_flag = false;
5283                 break;
5284         default:
5285                 return I40E_ERR_PARAM;
5286         }
5287
5288         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5289
5290         /* Indirect command */
5291         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5292         if (cmd_param_flag)
5293                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5294         if (buff_size > I40E_AQ_LARGE_BUF)
5295                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5296
5297         desc.datalen = CPU_TO_LE16(buff_size);
5298
5299         cmd->vsi_seid = CPU_TO_LE16(seid);
5300
5301         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5302
5303         return status;
5304 }
5305
5306 /**
5307  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5308  * @hw: pointer to the hw struct
5309  * @seid: VSI seid
5310  * @credit: BW limit credits (0 = disabled)
5311  * @max_credit: Max BW limit credits
5312  * @cmd_details: pointer to command details structure or NULL
5313  **/
5314 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5315                                 u16 seid, u16 credit, u8 max_credit,
5316                                 struct i40e_asq_cmd_details *cmd_details)
5317 {
5318         struct i40e_aq_desc desc;
5319         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5320                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5321         enum i40e_status_code status;
5322
5323         i40e_fill_default_direct_cmd_desc(&desc,
5324                                           i40e_aqc_opc_configure_vsi_bw_limit);
5325
5326         cmd->vsi_seid = CPU_TO_LE16(seid);
5327         cmd->credit = CPU_TO_LE16(credit);
5328         cmd->max_credit = max_credit;
5329
5330         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5331
5332         return status;
5333 }
5334
5335 /**
5336  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5337  * @hw: pointer to the hw struct
5338  * @seid: switching component seid
5339  * @credit: BW limit credits (0 = disabled)
5340  * @max_bw: Max BW limit credits
5341  * @cmd_details: pointer to command details structure or NULL
5342  **/
5343 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5344                                 u16 seid, u16 credit, u8 max_bw,
5345                                 struct i40e_asq_cmd_details *cmd_details)
5346 {
5347         struct i40e_aq_desc desc;
5348         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5349           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5350         enum i40e_status_code status;
5351
5352         i40e_fill_default_direct_cmd_desc(&desc,
5353                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5354
5355         cmd->seid = CPU_TO_LE16(seid);
5356         cmd->credit = CPU_TO_LE16(credit);
5357         cmd->max_bw = max_bw;
5358
5359         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5360
5361         return status;
5362 }
5363
5364 /**
5365  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5366  * @hw: pointer to the hw struct
5367  * @seid: VSI seid
5368  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5369  * @cmd_details: pointer to command details structure or NULL
5370  **/
5371 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5372                         u16 seid,
5373                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5374                         struct i40e_asq_cmd_details *cmd_details)
5375 {
5376         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5377                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5378                                     cmd_details);
5379 }
5380
5381 /**
5382  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5383  * @hw: pointer to the hw struct
5384  * @seid: VSI seid
5385  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5386  * @cmd_details: pointer to command details structure or NULL
5387  **/
5388 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5389                         u16 seid,
5390                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5391                         struct i40e_asq_cmd_details *cmd_details)
5392 {
5393         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5394                                     i40e_aqc_opc_configure_vsi_tc_bw,
5395                                     cmd_details);
5396 }
5397
5398 /**
5399  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5400  * @hw: pointer to the hw struct
5401  * @seid: seid of the switching component connected to Physical Port
5402  * @ets_data: Buffer holding ETS parameters
5403  * @opcode: Tx scheduler AQ command opcode
5404  * @cmd_details: pointer to command details structure or NULL
5405  **/
5406 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5407                 u16 seid,
5408                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5409                 enum i40e_admin_queue_opc opcode,
5410                 struct i40e_asq_cmd_details *cmd_details)
5411 {
5412         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5413                                     sizeof(*ets_data), opcode, cmd_details);
5414 }
5415
5416 /**
5417  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5418  * @hw: pointer to the hw struct
5419  * @seid: seid of the switching component
5420  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5421  * @cmd_details: pointer to command details structure or NULL
5422  **/
5423 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5424         u16 seid,
5425         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5426         struct i40e_asq_cmd_details *cmd_details)
5427 {
5428         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5429                             i40e_aqc_opc_configure_switching_comp_bw_config,
5430                             cmd_details);
5431 }
5432
5433 /**
5434  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5435  * @hw: pointer to the hw struct
5436  * @seid: seid of the switching component
5437  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5438  * @cmd_details: pointer to command details structure or NULL
5439  **/
5440 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5441         struct i40e_hw *hw, u16 seid,
5442         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5443         struct i40e_asq_cmd_details *cmd_details)
5444 {
5445         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5446                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5447                             cmd_details);
5448 }
5449
5450 /**
5451  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5452  * @hw: pointer to the hw struct
5453  * @seid: seid of the VSI
5454  * @bw_data: Buffer to hold VSI BW configuration
5455  * @cmd_details: pointer to command details structure or NULL
5456  **/
5457 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5458                         u16 seid,
5459                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5460                         struct i40e_asq_cmd_details *cmd_details)
5461 {
5462         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5463                                     i40e_aqc_opc_query_vsi_bw_config,
5464                                     cmd_details);
5465 }
5466
5467 /**
5468  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5469  * @hw: pointer to the hw struct
5470  * @seid: seid of the VSI
5471  * @bw_data: Buffer to hold VSI BW configuration per TC
5472  * @cmd_details: pointer to command details structure or NULL
5473  **/
5474 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5475                         u16 seid,
5476                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5477                         struct i40e_asq_cmd_details *cmd_details)
5478 {
5479         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5480                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5481                                     cmd_details);
5482 }
5483
5484 /**
5485  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5486  * @hw: pointer to the hw struct
5487  * @seid: seid of the switching component
5488  * @bw_data: Buffer to hold switching component's per TC BW config
5489  * @cmd_details: pointer to command details structure or NULL
5490  **/
5491 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5492                 u16 seid,
5493                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5494                 struct i40e_asq_cmd_details *cmd_details)
5495 {
5496         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5497                                    i40e_aqc_opc_query_switching_comp_ets_config,
5498                                    cmd_details);
5499 }
5500
5501 /**
5502  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5503  * @hw: pointer to the hw struct
5504  * @seid: seid of the VSI or switching component connected to Physical Port
5505  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5506  * @cmd_details: pointer to command details structure or NULL
5507  **/
5508 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5509                         u16 seid,
5510                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5511                         struct i40e_asq_cmd_details *cmd_details)
5512 {
5513         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5514                                     i40e_aqc_opc_query_port_ets_config,
5515                                     cmd_details);
5516 }
5517
5518 /**
5519  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5520  * @hw: pointer to the hw struct
5521  * @seid: seid of the switching component
5522  * @bw_data: Buffer to hold switching component's BW configuration
5523  * @cmd_details: pointer to command details structure or NULL
5524  **/
5525 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5526                 u16 seid,
5527                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5528                 struct i40e_asq_cmd_details *cmd_details)
5529 {
5530         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5531                                     i40e_aqc_opc_query_switching_comp_bw_config,
5532                                     cmd_details);
5533 }
5534
5535 /**
5536  * i40e_validate_filter_settings
5537  * @hw: pointer to the hardware structure
5538  * @settings: Filter control settings
5539  *
5540  * Check and validate the filter control settings passed.
5541  * The function checks for the valid filter/context sizes being
5542  * passed for FCoE and PE.
5543  *
5544  * Returns I40E_SUCCESS if the values passed are valid and within
5545  * range else returns an error.
5546  **/
5547 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5548                                 struct i40e_filter_control_settings *settings)
5549 {
5550         u32 fcoe_cntx_size, fcoe_filt_size;
5551         u32 pe_cntx_size, pe_filt_size;
5552         u32 fcoe_fmax;
5553
5554         u32 val;
5555
5556         /* Validate FCoE settings passed */
5557         switch (settings->fcoe_filt_num) {
5558         case I40E_HASH_FILTER_SIZE_1K:
5559         case I40E_HASH_FILTER_SIZE_2K:
5560         case I40E_HASH_FILTER_SIZE_4K:
5561         case I40E_HASH_FILTER_SIZE_8K:
5562         case I40E_HASH_FILTER_SIZE_16K:
5563         case I40E_HASH_FILTER_SIZE_32K:
5564                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5565                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5566                 break;
5567         default:
5568                 return I40E_ERR_PARAM;
5569         }
5570
5571         switch (settings->fcoe_cntx_num) {
5572         case I40E_DMA_CNTX_SIZE_512:
5573         case I40E_DMA_CNTX_SIZE_1K:
5574         case I40E_DMA_CNTX_SIZE_2K:
5575         case I40E_DMA_CNTX_SIZE_4K:
5576                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5577                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5578                 break;
5579         default:
5580                 return I40E_ERR_PARAM;
5581         }
5582
5583         /* Validate PE settings passed */
5584         switch (settings->pe_filt_num) {
5585         case I40E_HASH_FILTER_SIZE_1K:
5586         case I40E_HASH_FILTER_SIZE_2K:
5587         case I40E_HASH_FILTER_SIZE_4K:
5588         case I40E_HASH_FILTER_SIZE_8K:
5589         case I40E_HASH_FILTER_SIZE_16K:
5590         case I40E_HASH_FILTER_SIZE_32K:
5591         case I40E_HASH_FILTER_SIZE_64K:
5592         case I40E_HASH_FILTER_SIZE_128K:
5593         case I40E_HASH_FILTER_SIZE_256K:
5594         case I40E_HASH_FILTER_SIZE_512K:
5595         case I40E_HASH_FILTER_SIZE_1M:
5596                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5597                 pe_filt_size <<= (u32)settings->pe_filt_num;
5598                 break;
5599         default:
5600                 return I40E_ERR_PARAM;
5601         }
5602
5603         switch (settings->pe_cntx_num) {
5604         case I40E_DMA_CNTX_SIZE_512:
5605         case I40E_DMA_CNTX_SIZE_1K:
5606         case I40E_DMA_CNTX_SIZE_2K:
5607         case I40E_DMA_CNTX_SIZE_4K:
5608         case I40E_DMA_CNTX_SIZE_8K:
5609         case I40E_DMA_CNTX_SIZE_16K:
5610         case I40E_DMA_CNTX_SIZE_32K:
5611         case I40E_DMA_CNTX_SIZE_64K:
5612         case I40E_DMA_CNTX_SIZE_128K:
5613         case I40E_DMA_CNTX_SIZE_256K:
5614                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5615                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5616                 break;
5617         default:
5618                 return I40E_ERR_PARAM;
5619         }
5620
5621         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5622         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5623         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5624                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5625         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5626                 return I40E_ERR_INVALID_SIZE;
5627
5628         return I40E_SUCCESS;
5629 }
5630
5631 /**
5632  * i40e_set_filter_control
5633  * @hw: pointer to the hardware structure
5634  * @settings: Filter control settings
5635  *
5636  * Set the Queue Filters for PE/FCoE and enable filters required
5637  * for a single PF. It is expected that these settings are programmed
5638  * at the driver initialization time.
5639  **/
5640 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5641                                 struct i40e_filter_control_settings *settings)
5642 {
5643         enum i40e_status_code ret = I40E_SUCCESS;
5644         u32 hash_lut_size = 0;
5645         u32 val;
5646
5647         if (!settings)
5648                 return I40E_ERR_PARAM;
5649
5650         /* Validate the input settings */
5651         ret = i40e_validate_filter_settings(hw, settings);
5652         if (ret)
5653                 return ret;
5654
5655         /* Read the PF Queue Filter control register */
5656         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5657
5658         /* Program required PE hash buckets for the PF */
5659         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5660         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5661                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5662         /* Program required PE contexts for the PF */
5663         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5664         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5665                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5666
5667         /* Program required FCoE hash buckets for the PF */
5668         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5669         val |= ((u32)settings->fcoe_filt_num <<
5670                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5671                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5672         /* Program required FCoE DDP contexts for the PF */
5673         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5674         val |= ((u32)settings->fcoe_cntx_num <<
5675                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5676                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5677
5678         /* Program Hash LUT size for the PF */
5679         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5680         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5681                 hash_lut_size = 1;
5682         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5683                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5684
5685         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5686         if (settings->enable_fdir)
5687                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5688         if (settings->enable_ethtype)
5689                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5690         if (settings->enable_macvlan)
5691                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5692
5693         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5694
5695         return I40E_SUCCESS;
5696 }
5697
5698 /**
5699  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5700  * @hw: pointer to the hw struct
5701  * @mac_addr: MAC address to use in the filter
5702  * @ethtype: Ethertype to use in the filter
5703  * @flags: Flags that needs to be applied to the filter
5704  * @vsi_seid: seid of the control VSI
5705  * @queue: VSI queue number to send the packet to
5706  * @is_add: Add control packet filter if True else remove
5707  * @stats: Structure to hold information on control filter counts
5708  * @cmd_details: pointer to command details structure or NULL
5709  *
5710  * This command will Add or Remove control packet filter for a control VSI.
5711  * In return it will update the total number of perfect filter count in
5712  * the stats member.
5713  **/
5714 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5715                                 u8 *mac_addr, u16 ethtype, u16 flags,
5716                                 u16 vsi_seid, u16 queue, bool is_add,
5717                                 struct i40e_control_filter_stats *stats,
5718                                 struct i40e_asq_cmd_details *cmd_details)
5719 {
5720         struct i40e_aq_desc desc;
5721         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5722                 (struct i40e_aqc_add_remove_control_packet_filter *)
5723                 &desc.params.raw;
5724         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5725                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5726                 &desc.params.raw;
5727         enum i40e_status_code status;
5728
5729         if (vsi_seid == 0)
5730                 return I40E_ERR_PARAM;
5731
5732         if (is_add) {
5733                 i40e_fill_default_direct_cmd_desc(&desc,
5734                                 i40e_aqc_opc_add_control_packet_filter);
5735                 cmd->queue = CPU_TO_LE16(queue);
5736         } else {
5737                 i40e_fill_default_direct_cmd_desc(&desc,
5738                                 i40e_aqc_opc_remove_control_packet_filter);
5739         }
5740
5741         if (mac_addr)
5742                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5743                             I40E_NONDMA_TO_NONDMA);
5744
5745         cmd->etype = CPU_TO_LE16(ethtype);
5746         cmd->flags = CPU_TO_LE16(flags);
5747         cmd->seid = CPU_TO_LE16(vsi_seid);
5748
5749         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5750
5751         if (!status && stats) {
5752                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5753                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5754                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5755                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5756         }
5757
5758         return status;
5759 }
5760
5761 /**
5762  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5763  * @hw: pointer to the hw struct
5764  * @seid: VSI seid to add ethertype filter from
5765  **/
5766 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5767                                                     u16 seid)
5768 {
5769 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5770         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5771                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5772                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5773         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5774         enum i40e_status_code status;
5775
5776         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5777                                                        seid, 0, true, NULL,
5778                                                        NULL);
5779         if (status)
5780                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5781 }
5782
5783 /**
5784  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5785  * @filters: list of cloud filters
5786  * @filter_count: length of list
5787  *
5788  * There's an issue in the device where the Geneve VNI layout needs
5789  * to be shifted 1 byte over from the VxLAN VNI
5790  **/
5791 STATIC void i40e_fix_up_geneve_vni(
5792         struct i40e_aqc_cloud_filters_element_data *filters,
5793         u8 filter_count)
5794 {
5795         struct i40e_aqc_cloud_filters_element_data *f = filters;
5796         int i;
5797
5798         for (i = 0; i < filter_count; i++) {
5799                 u16 tnl_type;
5800                 u32 ti;
5801
5802                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5803                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5804                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5805                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5806                         ti = LE32_TO_CPU(f[i].tenant_id);
5807                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5808                 }
5809         }
5810 }
5811
5812 /**
5813  * i40e_aq_add_cloud_filters
5814  * @hw: pointer to the hardware structure
5815  * @seid: VSI seid to add cloud filters from
5816  * @filters: Buffer which contains the filters to be added
5817  * @filter_count: number of filters contained in the buffer
5818  *
5819  * Set the cloud filters for a given VSI.  The contents of the
5820  * i40e_aqc_cloud_filters_element_data are filled
5821  * in by the caller of the function.
5822  *
5823  **/
5824 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5825         u16 seid,
5826         struct i40e_aqc_cloud_filters_element_data *filters,
5827         u8 filter_count)
5828 {
5829         struct i40e_aq_desc desc;
5830         struct i40e_aqc_add_remove_cloud_filters *cmd =
5831         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5832         enum i40e_status_code status;
5833         u16 buff_len;
5834
5835         i40e_fill_default_direct_cmd_desc(&desc,
5836                                           i40e_aqc_opc_add_cloud_filters);
5837
5838         buff_len = filter_count * sizeof(*filters);
5839         desc.datalen = CPU_TO_LE16(buff_len);
5840         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5841         cmd->num_filters = filter_count;
5842         cmd->seid = CPU_TO_LE16(seid);
5843
5844         i40e_fix_up_geneve_vni(filters, filter_count);
5845
5846         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5847
5848         return status;
5849 }
5850
5851 /**
5852  * i40e_aq_add_cloud_filters_bb
5853  * @hw: pointer to the hardware structure
5854  * @seid: VSI seid to add cloud filters from
5855  * @filters: Buffer which contains the filters in big buffer to be added
5856  * @filter_count: number of filters contained in the buffer
5857  *
5858  * Set the cloud filters for a given VSI.  The contents of the
5859  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5860  * the function.
5861  *
5862  **/
5863 enum i40e_status_code
5864 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5865                              struct i40e_aqc_cloud_filters_element_bb *filters,
5866                              u8 filter_count)
5867 {
5868         struct i40e_aq_desc desc;
5869         struct i40e_aqc_add_remove_cloud_filters *cmd =
5870         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5871         enum i40e_status_code status;
5872         u16 buff_len;
5873         int i;
5874
5875         i40e_fill_default_direct_cmd_desc(&desc,
5876                                           i40e_aqc_opc_add_cloud_filters);
5877
5878         buff_len = filter_count * sizeof(*filters);
5879         desc.datalen = CPU_TO_LE16(buff_len);
5880         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5881         cmd->num_filters = filter_count;
5882         cmd->seid = CPU_TO_LE16(seid);
5883         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5884
5885         for (i = 0; i < filter_count; i++) {
5886                 u16 tnl_type;
5887                 u32 ti;
5888
5889                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5890                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5891                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5892
5893                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5894                  * one more byte further than normally used for Tenant ID in
5895                  * other tunnel types.
5896                  */
5897                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5898                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5899                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5900                 }
5901         }
5902
5903         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5904
5905         return status;
5906 }
5907
5908 /**
5909  * i40e_aq_rem_cloud_filters
5910  * @hw: pointer to the hardware structure
5911  * @seid: VSI seid to remove cloud filters from
5912  * @filters: Buffer which contains the filters to be removed
5913  * @filter_count: number of filters contained in the buffer
5914  *
5915  * Remove the cloud filters for a given VSI.  The contents of the
5916  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5917  * of the function.
5918  *
5919  **/
5920 enum i40e_status_code
5921 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5922                           struct i40e_aqc_cloud_filters_element_data *filters,
5923                           u8 filter_count)
5924 {
5925         struct i40e_aq_desc desc;
5926         struct i40e_aqc_add_remove_cloud_filters *cmd =
5927         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5928         enum i40e_status_code status;
5929         u16 buff_len;
5930
5931         i40e_fill_default_direct_cmd_desc(&desc,
5932                                           i40e_aqc_opc_remove_cloud_filters);
5933
5934         buff_len = filter_count * sizeof(*filters);
5935         desc.datalen = CPU_TO_LE16(buff_len);
5936         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5937         cmd->num_filters = filter_count;
5938         cmd->seid = CPU_TO_LE16(seid);
5939
5940         i40e_fix_up_geneve_vni(filters, filter_count);
5941
5942         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5943
5944         return status;
5945 }
5946
5947 /**
5948  * i40e_aq_rem_cloud_filters_bb
5949  * @hw: pointer to the hardware structure
5950  * @seid: VSI seid to remove cloud filters from
5951  * @filters: Buffer which contains the filters in big buffer to be removed
5952  * @filter_count: number of filters contained in the buffer
5953  *
5954  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5955  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5956  * function.
5957  *
5958  **/
5959 enum i40e_status_code
5960 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5961                              struct i40e_aqc_cloud_filters_element_bb *filters,
5962                              u8 filter_count)
5963 {
5964         struct i40e_aq_desc desc;
5965         struct i40e_aqc_add_remove_cloud_filters *cmd =
5966         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5967         enum i40e_status_code status;
5968         u16 buff_len;
5969         int i;
5970
5971         i40e_fill_default_direct_cmd_desc(&desc,
5972                                           i40e_aqc_opc_remove_cloud_filters);
5973
5974         buff_len = filter_count * sizeof(*filters);
5975         desc.datalen = CPU_TO_LE16(buff_len);
5976         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5977         cmd->num_filters = filter_count;
5978         cmd->seid = CPU_TO_LE16(seid);
5979         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5980
5981         for (i = 0; i < filter_count; i++) {
5982                 u16 tnl_type;
5983                 u32 ti;
5984
5985                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5986                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5987                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5988
5989                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5990                  * one more byte further than normally used for Tenant ID in
5991                  * other tunnel types.
5992                  */
5993                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5994                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5995                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5996                 }
5997         }
5998
5999         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6000
6001         return status;
6002 }
6003
6004 /**
6005  * i40e_aq_replace_cloud_filters - Replace cloud filter command
6006  * @hw: pointer to the hw struct
6007  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
6008  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
6009  *
6010  **/
6011 enum
6012 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
6013         struct i40e_aqc_replace_cloud_filters_cmd *filters,
6014         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
6015 {
6016         struct i40e_aq_desc desc;
6017         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
6018                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
6019         enum i40e_status_code status = I40E_SUCCESS;
6020         int i = 0;
6021
6022         /* X722 doesn't support this command */
6023         if (hw->mac.type == I40E_MAC_X722)
6024                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
6025
6026         /* need FW version greater than 6.00 */
6027         if (hw->aq.fw_maj_ver < 6)
6028                 return I40E_NOT_SUPPORTED;
6029
6030         i40e_fill_default_direct_cmd_desc(&desc,
6031                                           i40e_aqc_opc_replace_cloud_filters);
6032
6033         desc.datalen = CPU_TO_LE16(32);
6034         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6035         cmd->old_filter_type = filters->old_filter_type;
6036         cmd->new_filter_type = filters->new_filter_type;
6037         cmd->valid_flags = filters->valid_flags;
6038         cmd->tr_bit = filters->tr_bit;
6039         cmd->tr_bit2 = filters->tr_bit2;
6040
6041         status = i40e_asq_send_command(hw, &desc, cmd_buf,
6042                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
6043
6044         /* for get cloud filters command */
6045         for (i = 0; i < 32; i += 4) {
6046                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
6047                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
6048                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
6049                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
6050         }
6051
6052         return status;
6053 }
6054
6055
6056 /**
6057  * i40e_aq_alternate_write
6058  * @hw: pointer to the hardware structure
6059  * @reg_addr0: address of first dword to be read
6060  * @reg_val0: value to be written under 'reg_addr0'
6061  * @reg_addr1: address of second dword to be read
6062  * @reg_val1: value to be written under 'reg_addr1'
6063  *
6064  * Write one or two dwords to alternate structure. Fields are indicated
6065  * by 'reg_addr0' and 'reg_addr1' register numbers.
6066  *
6067  **/
6068 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6069                                 u32 reg_addr0, u32 reg_val0,
6070                                 u32 reg_addr1, u32 reg_val1)
6071 {
6072         struct i40e_aq_desc desc;
6073         struct i40e_aqc_alternate_write *cmd_resp =
6074                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6075         enum i40e_status_code status;
6076
6077         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6078         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6079         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6080         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6081         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6082
6083         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6084
6085         return status;
6086 }
6087
6088 /**
6089  * i40e_aq_alternate_write_indirect
6090  * @hw: pointer to the hardware structure
6091  * @addr: address of a first register to be modified
6092  * @dw_count: number of alternate structure fields to write
6093  * @buffer: pointer to the command buffer
6094  *
6095  * Write 'dw_count' dwords from 'buffer' to alternate structure
6096  * starting at 'addr'.
6097  *
6098  **/
6099 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6100                                 u32 addr, u32 dw_count, void *buffer)
6101 {
6102         struct i40e_aq_desc desc;
6103         struct i40e_aqc_alternate_ind_write *cmd_resp =
6104                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6105         enum i40e_status_code status;
6106
6107         if (buffer == NULL)
6108                 return I40E_ERR_PARAM;
6109
6110         /* Indirect command */
6111         i40e_fill_default_direct_cmd_desc(&desc,
6112                                          i40e_aqc_opc_alternate_write_indirect);
6113
6114         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6115         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6116         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6117                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6118
6119         cmd_resp->address = CPU_TO_LE32(addr);
6120         cmd_resp->length = CPU_TO_LE32(dw_count);
6121
6122         status = i40e_asq_send_command(hw, &desc, buffer,
6123                                        I40E_LO_DWORD(4*dw_count), NULL);
6124
6125         return status;
6126 }
6127
6128 /**
6129  * i40e_aq_alternate_read
6130  * @hw: pointer to the hardware structure
6131  * @reg_addr0: address of first dword to be read
6132  * @reg_val0: pointer for data read from 'reg_addr0'
6133  * @reg_addr1: address of second dword to be read
6134  * @reg_val1: pointer for data read from 'reg_addr1'
6135  *
6136  * Read one or two dwords from alternate structure. Fields are indicated
6137  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6138  * is not passed then only register at 'reg_addr0' is read.
6139  *
6140  **/
6141 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6142                                 u32 reg_addr0, u32 *reg_val0,
6143                                 u32 reg_addr1, u32 *reg_val1)
6144 {
6145         struct i40e_aq_desc desc;
6146         struct i40e_aqc_alternate_write *cmd_resp =
6147                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6148         enum i40e_status_code status;
6149
6150         if (reg_val0 == NULL)
6151                 return I40E_ERR_PARAM;
6152
6153         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6154         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6155         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6156
6157         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6158
6159         if (status == I40E_SUCCESS) {
6160                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6161
6162                 if (reg_val1 != NULL)
6163                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6164         }
6165
6166         return status;
6167 }
6168
6169 /**
6170  * i40e_aq_alternate_read_indirect
6171  * @hw: pointer to the hardware structure
6172  * @addr: address of the alternate structure field
6173  * @dw_count: number of alternate structure fields to read
6174  * @buffer: pointer to the command buffer
6175  *
6176  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6177  * place them in 'buffer'. The buffer should be allocated by caller.
6178  *
6179  **/
6180 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6181                                 u32 addr, u32 dw_count, void *buffer)
6182 {
6183         struct i40e_aq_desc desc;
6184         struct i40e_aqc_alternate_ind_write *cmd_resp =
6185                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6186         enum i40e_status_code status;
6187
6188         if (buffer == NULL)
6189                 return I40E_ERR_PARAM;
6190
6191         /* Indirect command */
6192         i40e_fill_default_direct_cmd_desc(&desc,
6193                 i40e_aqc_opc_alternate_read_indirect);
6194
6195         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6196         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6197         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6198                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6199
6200         cmd_resp->address = CPU_TO_LE32(addr);
6201         cmd_resp->length = CPU_TO_LE32(dw_count);
6202
6203         status = i40e_asq_send_command(hw, &desc, buffer,
6204                                        I40E_LO_DWORD(4*dw_count), NULL);
6205
6206         return status;
6207 }
6208
6209 /**
6210  *  i40e_aq_alternate_clear
6211  *  @hw: pointer to the HW structure.
6212  *
6213  *  Clear the alternate structures of the port from which the function
6214  *  is called.
6215  *
6216  **/
6217 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6218 {
6219         struct i40e_aq_desc desc;
6220         enum i40e_status_code status;
6221
6222         i40e_fill_default_direct_cmd_desc(&desc,
6223                                           i40e_aqc_opc_alternate_clear_port);
6224
6225         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6226
6227         return status;
6228 }
6229
6230 /**
6231  *  i40e_aq_alternate_write_done
6232  *  @hw: pointer to the HW structure.
6233  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6234  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6235  *
6236  *  Indicates to the FW that alternate structures have been changed.
6237  *
6238  **/
6239 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6240                 u8 bios_mode, bool *reset_needed)
6241 {
6242         struct i40e_aq_desc desc;
6243         struct i40e_aqc_alternate_write_done *cmd =
6244                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6245         enum i40e_status_code status;
6246
6247         if (reset_needed == NULL)
6248                 return I40E_ERR_PARAM;
6249
6250         i40e_fill_default_direct_cmd_desc(&desc,
6251                                           i40e_aqc_opc_alternate_write_done);
6252
6253         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6254
6255         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6256         if (!status && reset_needed)
6257                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6258                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6259
6260         return status;
6261 }
6262
6263 /**
6264  *  i40e_aq_set_oem_mode
6265  *  @hw: pointer to the HW structure.
6266  *  @oem_mode: the OEM mode to be used
6267  *
6268  *  Sets the device to a specific operating mode. Currently the only supported
6269  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6270  *
6271  **/
6272 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6273                 u8 oem_mode)
6274 {
6275         struct i40e_aq_desc desc;
6276         struct i40e_aqc_alternate_write_done *cmd =
6277                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6278         enum i40e_status_code status;
6279
6280         i40e_fill_default_direct_cmd_desc(&desc,
6281                                           i40e_aqc_opc_alternate_set_mode);
6282
6283         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6284
6285         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6286
6287         return status;
6288 }
6289
6290 /**
6291  * i40e_aq_resume_port_tx
6292  * @hw: pointer to the hardware structure
6293  * @cmd_details: pointer to command details structure or NULL
6294  *
6295  * Resume port's Tx traffic
6296  **/
6297 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6298                                 struct i40e_asq_cmd_details *cmd_details)
6299 {
6300         struct i40e_aq_desc desc;
6301         enum i40e_status_code status;
6302
6303         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6304
6305         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6306
6307         return status;
6308 }
6309
6310 /**
6311  * i40e_set_pci_config_data - store PCI bus info
6312  * @hw: pointer to hardware structure
6313  * @link_status: the link status word from PCI config space
6314  *
6315  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6316  **/
6317 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6318 {
6319         hw->bus.type = i40e_bus_type_pci_express;
6320
6321         switch (link_status & I40E_PCI_LINK_WIDTH) {
6322         case I40E_PCI_LINK_WIDTH_1:
6323                 hw->bus.width = i40e_bus_width_pcie_x1;
6324                 break;
6325         case I40E_PCI_LINK_WIDTH_2:
6326                 hw->bus.width = i40e_bus_width_pcie_x2;
6327                 break;
6328         case I40E_PCI_LINK_WIDTH_4:
6329                 hw->bus.width = i40e_bus_width_pcie_x4;
6330                 break;
6331         case I40E_PCI_LINK_WIDTH_8:
6332                 hw->bus.width = i40e_bus_width_pcie_x8;
6333                 break;
6334         default:
6335                 hw->bus.width = i40e_bus_width_unknown;
6336                 break;
6337         }
6338
6339         switch (link_status & I40E_PCI_LINK_SPEED) {
6340         case I40E_PCI_LINK_SPEED_2500:
6341                 hw->bus.speed = i40e_bus_speed_2500;
6342                 break;
6343         case I40E_PCI_LINK_SPEED_5000:
6344                 hw->bus.speed = i40e_bus_speed_5000;
6345                 break;
6346         case I40E_PCI_LINK_SPEED_8000:
6347                 hw->bus.speed = i40e_bus_speed_8000;
6348                 break;
6349         default:
6350                 hw->bus.speed = i40e_bus_speed_unknown;
6351                 break;
6352         }
6353 }
6354
6355 /**
6356  * i40e_aq_debug_dump
6357  * @hw: pointer to the hardware structure
6358  * @cluster_id: specific cluster to dump
6359  * @table_id: table id within cluster
6360  * @start_index: index of line in the block to read
6361  * @buff_size: dump buffer size
6362  * @buff: dump buffer
6363  * @ret_buff_size: actual buffer size returned
6364  * @ret_next_table: next block to read
6365  * @ret_next_index: next index to read
6366  * @cmd_details: pointer to command details structure or NULL
6367  *
6368  * Dump internal FW/HW data for debug purposes.
6369  *
6370  **/
6371 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6372                                 u8 table_id, u32 start_index, u16 buff_size,
6373                                 void *buff, u16 *ret_buff_size,
6374                                 u8 *ret_next_table, u32 *ret_next_index,
6375                                 struct i40e_asq_cmd_details *cmd_details)
6376 {
6377         struct i40e_aq_desc desc;
6378         struct i40e_aqc_debug_dump_internals *cmd =
6379                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6380         struct i40e_aqc_debug_dump_internals *resp =
6381                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6382         enum i40e_status_code status;
6383
6384         if (buff_size == 0 || !buff)
6385                 return I40E_ERR_PARAM;
6386
6387         i40e_fill_default_direct_cmd_desc(&desc,
6388                                           i40e_aqc_opc_debug_dump_internals);
6389         /* Indirect Command */
6390         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6391         if (buff_size > I40E_AQ_LARGE_BUF)
6392                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6393
6394         cmd->cluster_id = cluster_id;
6395         cmd->table_id = table_id;
6396         cmd->idx = CPU_TO_LE32(start_index);
6397
6398         desc.datalen = CPU_TO_LE16(buff_size);
6399
6400         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6401         if (!status) {
6402                 if (ret_buff_size != NULL)
6403                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6404                 if (ret_next_table != NULL)
6405                         *ret_next_table = resp->table_id;
6406                 if (ret_next_index != NULL)
6407                         *ret_next_index = LE32_TO_CPU(resp->idx);
6408         }
6409
6410         return status;
6411 }
6412
6413
6414 /**
6415  * i40e_enable_eee
6416  * @hw: pointer to the hardware structure
6417  * @enable: state of Energy Efficient Ethernet mode to be set
6418  *
6419  * Enables or disables Energy Efficient Ethernet (EEE) mode
6420  * accordingly to @enable parameter.
6421  **/
6422 enum i40e_status_code i40e_enable_eee(struct i40e_hw *hw, bool enable)
6423 {
6424         struct i40e_aq_get_phy_abilities_resp abilities;
6425         struct i40e_aq_set_phy_config config;
6426         enum i40e_status_code status;
6427         __le16 eee_capability;
6428
6429         /* Get initial PHY capabilities */
6430         status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
6431                                               NULL);
6432         if (status)
6433                 goto err;
6434
6435         /* Check whether NIC configuration is compatible with Energy Efficient
6436          * Ethernet (EEE) mode.
6437          */
6438         if (abilities.eee_capability == 0) {
6439                 status = I40E_ERR_CONFIG;
6440                 goto err;
6441         }
6442
6443         /* Cache initial EEE capability */
6444         eee_capability = abilities.eee_capability;
6445
6446         /* Get current configuration */
6447         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6448                                               NULL);
6449         if (status)
6450                 goto err;
6451
6452         /* Cache current configuration */
6453         config.phy_type = abilities.phy_type;
6454         config.phy_type_ext = abilities.phy_type_ext;
6455         config.link_speed = abilities.link_speed;
6456         config.abilities = abilities.abilities |
6457                            I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
6458         config.eeer = abilities.eeer_val;
6459         config.low_power_ctrl = abilities.d3_lpan;
6460         config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
6461                             I40E_AQ_PHY_FEC_CONFIG_MASK;
6462
6463         /* Set desired EEE state */
6464         if (enable) {
6465                 config.eee_capability = eee_capability;
6466                 config.eeer |= I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6467         } else {
6468                 config.eee_capability = 0;
6469                 config.eeer &= ~I40E_PRTPM_EEER_TX_LPI_EN_MASK;
6470         }
6471
6472         /* Save modified config */
6473         status = i40e_aq_set_phy_config(hw, &config, NULL);
6474 err:
6475         return status;
6476 }
6477
6478 /**
6479  * i40e_read_bw_from_alt_ram
6480  * @hw: pointer to the hardware structure
6481  * @max_bw: pointer for max_bw read
6482  * @min_bw: pointer for min_bw read
6483  * @min_valid: pointer for bool that is true if min_bw is a valid value
6484  * @max_valid: pointer for bool that is true if max_bw is a valid value
6485  *
6486  * Read bw from the alternate ram for the given pf
6487  **/
6488 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6489                                         u32 *max_bw, u32 *min_bw,
6490                                         bool *min_valid, bool *max_valid)
6491 {
6492         enum i40e_status_code status;
6493         u32 max_bw_addr, min_bw_addr;
6494
6495         /* Calculate the address of the min/max bw registers */
6496         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6497                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6498                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6499         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6500                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6501                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6502
6503         /* Read the bandwidths from alt ram */
6504         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6505                                         min_bw_addr, min_bw);
6506
6507         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6508                 *min_valid = true;
6509         else
6510                 *min_valid = false;
6511
6512         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6513                 *max_valid = true;
6514         else
6515                 *max_valid = false;
6516
6517         return status;
6518 }
6519
6520 /**
6521  * i40e_aq_configure_partition_bw
6522  * @hw: pointer to the hardware structure
6523  * @bw_data: Buffer holding valid pfs and bw limits
6524  * @cmd_details: pointer to command details
6525  *
6526  * Configure partitions guaranteed/max bw
6527  **/
6528 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6529                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6530                         struct i40e_asq_cmd_details *cmd_details)
6531 {
6532         enum i40e_status_code status;
6533         struct i40e_aq_desc desc;
6534         u16 bwd_size = sizeof(*bw_data);
6535
6536         i40e_fill_default_direct_cmd_desc(&desc,
6537                                 i40e_aqc_opc_configure_partition_bw);
6538
6539         /* Indirect command */
6540         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6541         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6542
6543         desc.datalen = CPU_TO_LE16(bwd_size);
6544
6545         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6546
6547         return status;
6548 }
6549
6550 /**
6551  * i40e_read_phy_register_clause22
6552  * @hw: pointer to the HW structure
6553  * @reg: register address in the page
6554  * @phy_addr: PHY address on MDIO interface
6555  * @value: PHY register value
6556  *
6557  * Reads specified PHY register value
6558  **/
6559 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6560                                         u16 reg, u8 phy_addr, u16 *value)
6561 {
6562         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6563         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6564         u32 command = 0;
6565         u16 retry = 1000;
6566
6567         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6568                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6569                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6570                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6571                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6572         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6573         do {
6574                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6575                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6576                         status = I40E_SUCCESS;
6577                         break;
6578                 }
6579                 i40e_usec_delay(10);
6580                 retry--;
6581         } while (retry);
6582
6583         if (status) {
6584                 i40e_debug(hw, I40E_DEBUG_PHY,
6585                            "PHY: Can't write command to external PHY.\n");
6586         } else {
6587                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6588                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6589                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6590         }
6591
6592         return status;
6593 }
6594
6595 /**
6596  * i40e_write_phy_register_clause22
6597  * @hw: pointer to the HW structure
6598  * @reg: register address in the page
6599  * @phy_addr: PHY address on MDIO interface
6600  * @value: PHY register value
6601  *
6602  * Writes specified PHY register value
6603  **/
6604 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6605                                         u16 reg, u8 phy_addr, u16 value)
6606 {
6607         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6608         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6609         u32 command  = 0;
6610         u16 retry = 1000;
6611
6612         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6613         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6614
6615         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6616                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6617                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6618                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6619                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6620
6621         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6622         do {
6623                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6624                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6625                         status = I40E_SUCCESS;
6626                         break;
6627                 }
6628                 i40e_usec_delay(10);
6629                 retry--;
6630         } while (retry);
6631
6632         return status;
6633 }
6634
6635 /**
6636  * i40e_read_phy_register_clause45
6637  * @hw: pointer to the HW structure
6638  * @page: registers page number
6639  * @reg: register address in the page
6640  * @phy_addr: PHY address on MDIO interface
6641  * @value: PHY register value
6642  *
6643  * Reads specified PHY register value
6644  **/
6645 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6646                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6647 {
6648         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6649         u32 command  = 0;
6650         u16 retry = 1000;
6651         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6652
6653         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6654                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6655                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6656                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6657                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6658                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6659                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6660         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6661         do {
6662                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6663                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6664                         status = I40E_SUCCESS;
6665                         break;
6666                 }
6667                 i40e_usec_delay(10);
6668                 retry--;
6669         } while (retry);
6670
6671         if (status) {
6672                 i40e_debug(hw, I40E_DEBUG_PHY,
6673                            "PHY: Can't write command to external PHY.\n");
6674                 goto phy_read_end;
6675         }
6676
6677         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6678                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6679                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6680                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6681                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6682                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6683         status = I40E_ERR_TIMEOUT;
6684         retry = 1000;
6685         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6686         do {
6687                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6688                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6689                         status = I40E_SUCCESS;
6690                         break;
6691                 }
6692                 i40e_usec_delay(10);
6693                 retry--;
6694         } while (retry);
6695
6696         if (!status) {
6697                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6698                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6699                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6700         } else {
6701                 i40e_debug(hw, I40E_DEBUG_PHY,
6702                            "PHY: Can't read register value from external PHY.\n");
6703         }
6704
6705 phy_read_end:
6706         return status;
6707 }
6708
6709 /**
6710  * i40e_write_phy_register_clause45
6711  * @hw: pointer to the HW structure
6712  * @page: registers page number
6713  * @reg: register address in the page
6714  * @phy_addr: PHY address on MDIO interface
6715  * @value: PHY register value
6716  *
6717  * Writes value to specified PHY register
6718  **/
6719 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6720                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6721 {
6722         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6723         u32 command  = 0;
6724         u16 retry = 1000;
6725         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6726
6727         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6728                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6729                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6730                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6731                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6732                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6733                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6734         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6735         do {
6736                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6737                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6738                         status = I40E_SUCCESS;
6739                         break;
6740                 }
6741                 i40e_usec_delay(10);
6742                 retry--;
6743         } while (retry);
6744         if (status) {
6745                 i40e_debug(hw, I40E_DEBUG_PHY,
6746                            "PHY: Can't write command to external PHY.\n");
6747                 goto phy_write_end;
6748         }
6749
6750         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6751         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6752
6753         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6754                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6755                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6756                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6757                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6758                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6759         status = I40E_ERR_TIMEOUT;
6760         retry = 1000;
6761         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6762         do {
6763                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6764                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6765                         status = I40E_SUCCESS;
6766                         break;
6767                 }
6768                 i40e_usec_delay(10);
6769                 retry--;
6770         } while (retry);
6771
6772 phy_write_end:
6773         return status;
6774 }
6775
6776 /**
6777  * i40e_write_phy_register
6778  * @hw: pointer to the HW structure
6779  * @page: registers page number
6780  * @reg: register address in the page
6781  * @phy_addr: PHY address on MDIO interface
6782  * @value: PHY register value
6783  *
6784  * Writes value to specified PHY register
6785  **/
6786 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6787                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6788 {
6789         enum i40e_status_code status;
6790
6791         switch (hw->device_id) {
6792         case I40E_DEV_ID_1G_BASE_T_X722:
6793                 status = i40e_write_phy_register_clause22(hw,
6794                         reg, phy_addr, value);
6795                 break;
6796         case I40E_DEV_ID_10G_BASE_T:
6797         case I40E_DEV_ID_10G_BASE_T4:
6798         case I40E_DEV_ID_10G_BASE_T_BC:
6799         case I40E_DEV_ID_5G_BASE_T_BC:
6800         case I40E_DEV_ID_10G_BASE_T_X722:
6801         case I40E_DEV_ID_25G_B:
6802         case I40E_DEV_ID_25G_SFP28:
6803                 status = i40e_write_phy_register_clause45(hw,
6804                         page, reg, phy_addr, value);
6805                 break;
6806         default:
6807                 status = I40E_ERR_UNKNOWN_PHY;
6808                 break;
6809         }
6810
6811         return status;
6812 }
6813
6814 /**
6815  * i40e_read_phy_register
6816  * @hw: pointer to the HW structure
6817  * @page: registers page number
6818  * @reg: register address in the page
6819  * @phy_addr: PHY address on MDIO interface
6820  * @value: PHY register value
6821  *
6822  * Reads specified PHY register value
6823  **/
6824 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6825                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6826 {
6827         enum i40e_status_code status;
6828
6829         switch (hw->device_id) {
6830         case I40E_DEV_ID_1G_BASE_T_X722:
6831                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6832                                                          value);
6833                 break;
6834         case I40E_DEV_ID_10G_BASE_T:
6835         case I40E_DEV_ID_10G_BASE_T4:
6836         case I40E_DEV_ID_5G_BASE_T_BC:
6837         case I40E_DEV_ID_10G_BASE_T_X722:
6838         case I40E_DEV_ID_25G_B:
6839         case I40E_DEV_ID_25G_SFP28:
6840                 status = i40e_read_phy_register_clause45(hw, page, reg,
6841                                                          phy_addr, value);
6842                 break;
6843         default:
6844                 status = I40E_ERR_UNKNOWN_PHY;
6845                 break;
6846         }
6847
6848         return status;
6849 }
6850
6851 /**
6852  * i40e_get_phy_address
6853  * @hw: pointer to the HW structure
6854  * @dev_num: PHY port num that address we want
6855  *
6856  * Gets PHY address for current port
6857  **/
6858 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6859 {
6860         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6861         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6862
6863         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6864 }
6865
6866 /**
6867  * i40e_blink_phy_led
6868  * @hw: pointer to the HW structure
6869  * @time: time how long led will blinks in secs
6870  * @interval: gap between LED on and off in msecs
6871  *
6872  * Blinks PHY link LED
6873  **/
6874 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6875                                               u32 time, u32 interval)
6876 {
6877         enum i40e_status_code status = I40E_SUCCESS;
6878         u32 i;
6879         u16 led_ctl = 0;
6880         u16 gpio_led_port;
6881         u16 led_reg;
6882         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6883         u8 phy_addr = 0;
6884         u8 port_num;
6885
6886         i = rd32(hw, I40E_PFGEN_PORTNUM);
6887         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6888         phy_addr = i40e_get_phy_address(hw, port_num);
6889
6890         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6891              led_addr++) {
6892                 status = i40e_read_phy_register_clause45(hw,
6893                                                          I40E_PHY_COM_REG_PAGE,
6894                                                          led_addr, phy_addr,
6895                                                          &led_reg);
6896                 if (status)
6897                         goto phy_blinking_end;
6898                 led_ctl = led_reg;
6899                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6900                         led_reg = 0;
6901                         status = i40e_write_phy_register_clause45(hw,
6902                                                          I40E_PHY_COM_REG_PAGE,
6903                                                          led_addr, phy_addr,
6904                                                          led_reg);
6905                         if (status)
6906                                 goto phy_blinking_end;
6907                         break;
6908                 }
6909         }
6910
6911         if (time > 0 && interval > 0) {
6912                 for (i = 0; i < time * 1000; i += interval) {
6913                         status = i40e_read_phy_register_clause45(hw,
6914                                                 I40E_PHY_COM_REG_PAGE,
6915                                                 led_addr, phy_addr, &led_reg);
6916                         if (status)
6917                                 goto restore_config;
6918                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6919                                 led_reg = 0;
6920                         else
6921                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6922                         status = i40e_write_phy_register_clause45(hw,
6923                                                 I40E_PHY_COM_REG_PAGE,
6924                                                 led_addr, phy_addr, led_reg);
6925                         if (status)
6926                                 goto restore_config;
6927                         i40e_msec_delay(interval);
6928                 }
6929         }
6930
6931 restore_config:
6932         status = i40e_write_phy_register_clause45(hw,
6933                                                   I40E_PHY_COM_REG_PAGE,
6934                                                   led_addr, phy_addr, led_ctl);
6935
6936 phy_blinking_end:
6937         return status;
6938 }
6939
6940 /**
6941  * i40e_led_get_reg - read LED register
6942  * @hw: pointer to the HW structure
6943  * @led_addr: LED register address
6944  * @reg_val: read register value
6945  **/
6946 enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6947                                        u32 *reg_val)
6948 {
6949         enum i40e_status_code status;
6950         u8 phy_addr = 0;
6951
6952         *reg_val = 0;
6953         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6954                 status = i40e_aq_get_phy_register(hw,
6955                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6956                                                 I40E_PHY_COM_REG_PAGE, true,
6957                                                 I40E_PHY_LED_PROV_REG_1,
6958                                                 reg_val, NULL);
6959         } else {
6960                 phy_addr = i40e_get_phy_address(hw, hw->port);
6961                 status = i40e_read_phy_register_clause45(hw,
6962                                                          I40E_PHY_COM_REG_PAGE,
6963                                                          led_addr, phy_addr,
6964                                                          (u16 *)reg_val);
6965         }
6966         return status;
6967 }
6968
6969 /**
6970  * i40e_led_set_reg - write LED register
6971  * @hw: pointer to the HW structure
6972  * @led_addr: LED register address
6973  * @reg_val: register value to write
6974  **/
6975 enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6976                                        u32 reg_val)
6977 {
6978         enum i40e_status_code status;
6979         u8 phy_addr = 0;
6980
6981         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6982                 status = i40e_aq_set_phy_register(hw,
6983                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6984                                                 I40E_PHY_COM_REG_PAGE, true,
6985                                                 I40E_PHY_LED_PROV_REG_1,
6986                                                 reg_val, NULL);
6987         } else {
6988                 phy_addr = i40e_get_phy_address(hw, hw->port);
6989                 status = i40e_write_phy_register_clause45(hw,
6990                                                           I40E_PHY_COM_REG_PAGE,
6991                                                           led_addr, phy_addr,
6992                                                           (u16)reg_val);
6993         }
6994
6995         return status;
6996 }
6997
6998 /**
6999  * i40e_led_get_phy - return current on/off mode
7000  * @hw: pointer to the hw struct
7001  * @led_addr: address of led register to use
7002  * @val: original value of register to use
7003  *
7004  **/
7005 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
7006                                        u16 *val)
7007 {
7008         enum i40e_status_code status = I40E_SUCCESS;
7009         u16 gpio_led_port;
7010         u32 reg_val_aq;
7011         u16 temp_addr;
7012         u8 phy_addr = 0;
7013         u16 reg_val;
7014
7015         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
7016                 status = i40e_aq_get_phy_register(hw,
7017                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7018                                                 I40E_PHY_COM_REG_PAGE, true,
7019                                                 I40E_PHY_LED_PROV_REG_1,
7020                                                 &reg_val_aq, NULL);
7021                 if (status == I40E_SUCCESS)
7022                         *val = (u16)reg_val_aq;
7023                 return status;
7024         }
7025         temp_addr = I40E_PHY_LED_PROV_REG_1;
7026         phy_addr = i40e_get_phy_address(hw, hw->port);
7027         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
7028              temp_addr++) {
7029                 status = i40e_read_phy_register_clause45(hw,
7030                                                          I40E_PHY_COM_REG_PAGE,
7031                                                          temp_addr, phy_addr,
7032                                                          &reg_val);
7033                 if (status)
7034                         return status;
7035                 *val = reg_val;
7036                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
7037                         *led_addr = temp_addr;
7038                         break;
7039                 }
7040         }
7041         return status;
7042 }
7043
7044 /**
7045  * i40e_led_set_phy
7046  * @hw: pointer to the HW structure
7047  * @on: true or false
7048  * @led_addr: address of led register to use
7049  * @mode: original val plus bit for set or ignore
7050  *
7051  * Set led's on or off when controlled by the PHY
7052  *
7053  **/
7054 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
7055                                        u16 led_addr, u32 mode)
7056 {
7057         enum i40e_status_code status = I40E_SUCCESS;
7058         u32 led_ctl = 0;
7059         u32 led_reg = 0;
7060
7061         status = i40e_led_get_reg(hw, led_addr, &led_reg);
7062         if (status)
7063                 return status;
7064         led_ctl = led_reg;
7065         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
7066                 led_reg = 0;
7067                 status = i40e_led_set_reg(hw, led_addr, led_reg);
7068                 if (status)
7069                         return status;
7070         }
7071         status = i40e_led_get_reg(hw, led_addr, &led_reg);
7072         if (status)
7073                 goto restore_config;
7074         if (on)
7075                 led_reg = I40E_PHY_LED_MANUAL_ON;
7076         else
7077                 led_reg = 0;
7078         status = i40e_led_set_reg(hw, led_addr, led_reg);
7079         if (status)
7080                 goto restore_config;
7081         if (mode & I40E_PHY_LED_MODE_ORIG) {
7082                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
7083                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
7084         }
7085         return status;
7086
7087 restore_config:
7088         status = i40e_led_set_reg(hw, led_addr, led_ctl);
7089         return status;
7090 }
7091 #endif /* PF_DRIVER */
7092 /**
7093  * i40e_get_phy_lpi_status - read LPI status from PHY or MAC register
7094  * @hw: pointer to the hw struct
7095  * @stat: pointer to structure with status of rx and tx lpi
7096  *
7097  * Read LPI state directly from external PHY register or from MAC
7098  * register, depending on device ID and current link speed.
7099  */
7100 enum i40e_status_code i40e_get_phy_lpi_status(struct i40e_hw *hw,
7101                                               struct i40e_hw_port_stats *stat)
7102 {
7103         enum i40e_status_code ret = I40E_SUCCESS;
7104         bool eee_mrvl_phy;
7105         bool eee_bcm_phy;
7106         u32 val;
7107
7108         stat->rx_lpi_status = 0;
7109         stat->tx_lpi_status = 0;
7110
7111         eee_bcm_phy =
7112                 (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7113                  hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7114                 (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
7115                  hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB);
7116         eee_mrvl_phy =
7117                 hw->device_id == I40E_DEV_ID_1G_BASE_T_X722;
7118
7119         if (eee_bcm_phy || eee_mrvl_phy) {
7120                 /* read Clause 45 PCS Status 1 register */
7121                 ret = i40e_aq_get_phy_register(hw,
7122                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
7123                                                I40E_BCM_PHY_PCS_STATUS1_PAGE,
7124                                                true,
7125                                                I40E_BCM_PHY_PCS_STATUS1_REG,
7126                                                &val, NULL);
7127
7128                 if (ret != I40E_SUCCESS)
7129                         return ret;
7130
7131                 stat->rx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_RX_LPI);
7132                 stat->tx_lpi_status = !!(val & I40E_BCM_PHY_PCS_STATUS1_TX_LPI);
7133
7134                 return ret;
7135         }
7136
7137         val = rd32(hw, I40E_PRTPM_EEE_STAT);
7138         stat->rx_lpi_status = (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
7139                                I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
7140         stat->tx_lpi_status = (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
7141                                I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
7142
7143         return ret;
7144 }
7145
7146 /**
7147  * i40e_get_lpi_counters - read LPI counters from EEE statistics
7148  * @hw: pointer to the hw struct
7149  * @tx_counter: pointer to memory for TX LPI counter
7150  * @rx_counter: pointer to memory for RX LPI counter
7151  * @is_clear:   returns true if counters are clear after read
7152  *
7153  * Read Low Power Idle (LPI) mode counters from Energy Efficient
7154  * Ethernet (EEE) statistics.
7155  **/
7156 enum i40e_status_code i40e_get_lpi_counters(struct i40e_hw *hw,
7157                                             u32 *tx_counter, u32 *rx_counter,
7158                                             bool *is_clear)
7159 {
7160         /* only X710-T*L requires special handling of counters
7161          * for other devices we just read the MAC registers
7162          */
7163         if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
7164              hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
7165             hw->phy.link_info.link_speed != I40E_LINK_SPEED_1GB) {
7166                 enum i40e_status_code retval;
7167                 u32 cmd_status = 0;
7168
7169                 *is_clear = false;
7170                 retval = i40e_aq_run_phy_activity(hw,
7171                                 I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7172                                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT,
7173                                 &cmd_status, tx_counter, rx_counter, NULL);
7174
7175                 if (!retval && cmd_status != I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7176                         retval = I40E_ERR_ADMIN_QUEUE_ERROR;
7177
7178                 return retval;
7179         }
7180
7181         *is_clear = true;
7182         *tx_counter = rd32(hw, I40E_PRTPM_TLPIC);
7183         *rx_counter = rd32(hw, I40E_PRTPM_RLPIC);
7184
7185         return I40E_SUCCESS;
7186 }
7187
7188 /**
7189  * i40e_get_lpi_duration - read LPI time duration from EEE statistics
7190  * @hw: pointer to the hw struct
7191  * @stat: pointer to structure with status of rx and tx lpi
7192  * @tx_duration: pointer to memory for TX LPI time duration
7193  * @rx_duration: pointer to memory for RX LPI time duration
7194  *
7195  * Read Low Power Idle (LPI) mode time duration from Energy Efficient
7196  * Ethernet (EEE) statistics.
7197  */
7198 enum i40e_status_code i40e_get_lpi_duration(struct i40e_hw *hw,
7199                                             struct i40e_hw_port_stats *stat,
7200                                             u64 *tx_duration, u64 *rx_duration)
7201 {
7202         u32 tx_time_dur, rx_time_dur;
7203         enum i40e_status_code retval;
7204         u32 cmd_status;
7205
7206         if (hw->device_id != I40E_DEV_ID_10G_BASE_T_BC &&
7207             hw->device_id != I40E_DEV_ID_5G_BASE_T_BC)
7208                 return I40E_ERR_NOT_IMPLEMENTED;
7209
7210         retval = i40e_aq_run_phy_activity
7211                 (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7212                 I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR,
7213                 &cmd_status, &tx_time_dur, &rx_time_dur, NULL);
7214
7215         if (retval)
7216                 return retval;
7217         if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7218             I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7219                 return I40E_ERR_ADMIN_QUEUE_ERROR;
7220
7221         if (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB &&
7222             !tx_time_dur && !rx_time_dur &&
7223             stat->tx_lpi_status && stat->rx_lpi_status) {
7224                 retval = i40e_aq_run_phy_activity
7225                         (hw, I40E_AQ_RUN_PHY_ACT_ID_USR_DFND,
7226                         I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR,
7227                         &cmd_status,
7228                         &tx_time_dur, &rx_time_dur, NULL);
7229
7230                 if (retval)
7231                         return retval;
7232                 if ((cmd_status & I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK) !=
7233                     I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC)
7234                         return I40E_ERR_ADMIN_QUEUE_ERROR;
7235                 tx_time_dur = 0;
7236                 rx_time_dur = 0;
7237         }
7238
7239         *tx_duration = tx_time_dur;
7240         *rx_duration = rx_time_dur;
7241
7242         return retval;
7243 }
7244
7245 /**
7246  * i40e_lpi_stat_update - update LPI counters with values relative to offset
7247  * @hw: pointer to the hw struct
7248  * @offset_loaded: flag indicating need of writing current value to offset
7249  * @tx_offset: pointer to offset of TX LPI counter
7250  * @tx_stat: pointer to value of TX LPI counter
7251  * @rx_offset: pointer to offset of RX LPI counter
7252  * @rx_stat: pointer to value of RX LPI counter
7253  *
7254  * Update Low Power Idle (LPI) mode counters while having regard to passed
7255  * offsets.
7256  **/
7257 enum i40e_status_code i40e_lpi_stat_update(struct i40e_hw *hw,
7258                                            bool offset_loaded, u64 *tx_offset,
7259                                            u64 *tx_stat, u64 *rx_offset,
7260                                            u64 *rx_stat)
7261 {
7262         enum i40e_status_code retval;
7263         u32 tx_counter, rx_counter;
7264         bool is_clear;
7265
7266         retval = i40e_get_lpi_counters(hw, &tx_counter, &rx_counter, &is_clear);
7267         if (retval)
7268                 goto err;
7269
7270         if (is_clear) {
7271                 *tx_stat += tx_counter;
7272                 *rx_stat += rx_counter;
7273         } else {
7274                 if (!offset_loaded) {
7275                         *tx_offset = tx_counter;
7276                         *rx_offset = rx_counter;
7277                 }
7278
7279                 *tx_stat = (tx_counter >= *tx_offset) ?
7280                         (u32)(tx_counter - *tx_offset) :
7281                         (u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
7282                 *rx_stat = (rx_counter >= *rx_offset) ?
7283                         (u32)(rx_counter - *rx_offset) :
7284                         (u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
7285         }
7286 err:
7287         return retval;
7288 }
7289
7290 /**
7291  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7292  * @hw: pointer to the hw struct
7293  * @reg_addr: register address
7294  * @reg_val: ptr to register value
7295  * @cmd_details: pointer to command details structure or NULL
7296  *
7297  * Use the firmware to read the Rx control register,
7298  * especially useful if the Rx unit is under heavy pressure
7299  **/
7300 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7301                                 u32 reg_addr, u32 *reg_val,
7302                                 struct i40e_asq_cmd_details *cmd_details)
7303 {
7304         struct i40e_aq_desc desc;
7305         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7306                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7307         enum i40e_status_code status;
7308
7309         if (reg_val == NULL)
7310                 return I40E_ERR_PARAM;
7311
7312         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7313
7314         cmd_resp->address = CPU_TO_LE32(reg_addr);
7315
7316         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7317
7318         if (status == I40E_SUCCESS)
7319                 *reg_val = LE32_TO_CPU(cmd_resp->value);
7320
7321         return status;
7322 }
7323
7324 /**
7325  * i40e_read_rx_ctl - read from an Rx control register
7326  * @hw: pointer to the hw struct
7327  * @reg_addr: register address
7328  **/
7329 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7330 {
7331         enum i40e_status_code status = I40E_SUCCESS;
7332         bool use_register;
7333         int retry = 5;
7334         u32 val = 0;
7335
7336         use_register = (((hw->aq.api_maj_ver == 1) &&
7337                         (hw->aq.api_min_ver < 5)) ||
7338                         (hw->mac.type == I40E_MAC_X722));
7339         if (!use_register) {
7340 do_retry:
7341                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7342                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7343                         i40e_msec_delay(1);
7344                         retry--;
7345                         goto do_retry;
7346                 }
7347         }
7348
7349         /* if the AQ access failed, try the old-fashioned way */
7350         if (status || use_register)
7351                 val = rd32(hw, reg_addr);
7352
7353         return val;
7354 }
7355
7356 /**
7357  * i40e_aq_rx_ctl_write_register
7358  * @hw: pointer to the hw struct
7359  * @reg_addr: register address
7360  * @reg_val: register value
7361  * @cmd_details: pointer to command details structure or NULL
7362  *
7363  * Use the firmware to write to an Rx control register,
7364  * especially useful if the Rx unit is under heavy pressure
7365  **/
7366 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7367                                 u32 reg_addr, u32 reg_val,
7368                                 struct i40e_asq_cmd_details *cmd_details)
7369 {
7370         struct i40e_aq_desc desc;
7371         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7372                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7373         enum i40e_status_code status;
7374
7375         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7376
7377         cmd->address = CPU_TO_LE32(reg_addr);
7378         cmd->value = CPU_TO_LE32(reg_val);
7379
7380         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7381
7382         return status;
7383 }
7384
7385 /**
7386  * i40e_write_rx_ctl - write to an Rx control register
7387  * @hw: pointer to the hw struct
7388  * @reg_addr: register address
7389  * @reg_val: register value
7390  **/
7391 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7392 {
7393         enum i40e_status_code status = I40E_SUCCESS;
7394         bool use_register;
7395         int retry = 5;
7396
7397         use_register = (((hw->aq.api_maj_ver == 1) &&
7398                         (hw->aq.api_min_ver < 5)) ||
7399                         (hw->mac.type == I40E_MAC_X722));
7400         if (!use_register) {
7401 do_retry:
7402                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7403                                                        reg_val, NULL);
7404                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7405                         i40e_msec_delay(1);
7406                         retry--;
7407                         goto do_retry;
7408                 }
7409         }
7410
7411         /* if the AQ access failed, try the old-fashioned way */
7412         if (status || use_register)
7413                 wr32(hw, reg_addr, reg_val);
7414 }
7415
7416 /**
7417  * i40e_mdio_if_number_selection - MDIO I/F number selection
7418  * @hw: pointer to the hw struct
7419  * @set_mdio: use MDIO I/F number specified by mdio_num
7420  * @mdio_num: MDIO I/F number
7421  * @cmd: pointer to PHY Register command structure
7422  **/
7423 static void
7424 i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
7425                               struct i40e_aqc_phy_register_access *cmd)
7426 {
7427         if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
7428                 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
7429                         cmd->cmd_flags |=
7430                                 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
7431                                 ((mdio_num <<
7432                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
7433                                 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
7434                 else
7435                         i40e_debug(hw, I40E_DEBUG_PHY,
7436                                    "MDIO I/F number selection not supported by current FW version.\n");
7437         }
7438 }
7439
7440 /**
7441  * i40e_aq_set_phy_register_ext
7442  * @hw: pointer to the hw struct
7443  * @phy_select: select which phy should be accessed
7444  * @dev_addr: PHY device address
7445  * @page_change: enable auto page change
7446  * @set_mdio: use MDIO I/F number specified by mdio_num
7447  * @mdio_num: MDIO I/F number
7448  * @reg_addr: PHY register address
7449  * @reg_val: new register value
7450  * @cmd_details: pointer to command details structure or NULL
7451  *
7452  * Write the external PHY register.
7453  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7454  * may use simple wrapper i40e_aq_set_phy_register.
7455  **/
7456 enum i40e_status_code
7457 i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
7458                              u8 phy_select, u8 dev_addr, bool page_change,
7459                              bool set_mdio, u8 mdio_num,
7460                              u32 reg_addr, u32 reg_val,
7461                              struct i40e_asq_cmd_details *cmd_details)
7462 {
7463         struct i40e_aq_desc desc;
7464         struct i40e_aqc_phy_register_access *cmd =
7465                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7466         enum i40e_status_code status;
7467
7468         i40e_fill_default_direct_cmd_desc(&desc,
7469                                           i40e_aqc_opc_set_phy_register);
7470
7471         cmd->phy_interface = phy_select;
7472         cmd->dev_addres = dev_addr;
7473         cmd->reg_address = CPU_TO_LE32(reg_addr);
7474         cmd->reg_value = CPU_TO_LE32(reg_val);
7475
7476         if (!page_change)
7477                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7478
7479         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7480
7481         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7482
7483         return status;
7484 }
7485
7486 /**
7487  * i40e_aq_get_phy_register_ext
7488  * @hw: pointer to the hw struct
7489  * @phy_select: select which phy should be accessed
7490  * @dev_addr: PHY device address
7491  * @page_change: enable auto page change
7492  * @set_mdio: use MDIO I/F number specified by mdio_num
7493  * @mdio_num: MDIO I/F number
7494  * @reg_addr: PHY register address
7495  * @reg_val: read register value
7496  * @cmd_details: pointer to command details structure or NULL
7497  *
7498  * Read the external PHY register.
7499  * NOTE: In common cases MDIO I/F number should not be changed, thats why you
7500  * may use simple wrapper i40e_aq_get_phy_register.
7501  **/
7502 enum i40e_status_code
7503 i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
7504                              u8 phy_select, u8 dev_addr, bool page_change,
7505                              bool set_mdio, u8 mdio_num,
7506                              u32 reg_addr, u32 *reg_val,
7507                              struct i40e_asq_cmd_details *cmd_details)
7508 {
7509         struct i40e_aq_desc desc;
7510         struct i40e_aqc_phy_register_access *cmd =
7511                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7512         enum i40e_status_code status;
7513
7514         i40e_fill_default_direct_cmd_desc(&desc,
7515                                           i40e_aqc_opc_get_phy_register);
7516
7517         cmd->phy_interface = phy_select;
7518         cmd->dev_addres = dev_addr;
7519         cmd->reg_address = CPU_TO_LE32(reg_addr);
7520
7521         if (!page_change)
7522                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7523
7524         i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
7525
7526         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7527         if (!status)
7528                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7529
7530         return status;
7531 }
7532
7533 /**
7534  * i40e_aq_run_phy_activity
7535  * @hw: pointer to the hw struct
7536  * @activity_id: ID of DNL activity to run
7537  * @dnl_opcode: opcode passed to DNL script
7538  * @cmd_status: pointer to memory to write return value of DNL script
7539  * @data0: pointer to memory for first 4 bytes of data returned by DNL script
7540  * @data1: pointer to memory for last 4 bytes of data returned by DNL script
7541  * @cmd_details: pointer to command details structure or NULL
7542  *
7543  * Run DNL admin command.
7544  **/
7545 enum i40e_status_code
7546 i40e_aq_run_phy_activity(struct i40e_hw *hw, u16 activity_id, u32 dnl_opcode,
7547                          u32 *cmd_status, u32 *data0, u32 *data1,
7548                          struct i40e_asq_cmd_details *cmd_details)
7549 {
7550         struct i40e_aqc_run_phy_activity *cmd;
7551         enum i40e_status_code retval;
7552         struct i40e_aq_desc desc;
7553
7554         cmd = (struct i40e_aqc_run_phy_activity *)&desc.params.raw;
7555
7556         if (!cmd_status || !data0 || !data1) {
7557                 retval = I40E_ERR_PARAM;
7558                 goto err;
7559         }
7560
7561         i40e_fill_default_direct_cmd_desc(&desc,
7562                                           i40e_aqc_opc_run_phy_activity);
7563
7564         cmd->activity_id = CPU_TO_LE16(activity_id);
7565         cmd->params.cmd.dnl_opcode = CPU_TO_LE32(dnl_opcode);
7566
7567         retval = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7568         if (retval)
7569                 goto err;
7570
7571         *cmd_status = LE32_TO_CPU(cmd->params.resp.cmd_status);
7572         *data0 = LE32_TO_CPU(cmd->params.resp.data0);
7573         *data1 = LE32_TO_CPU(cmd->params.resp.data1);
7574 err:
7575         return retval;
7576 }
7577
7578 #ifdef VF_DRIVER
7579
7580 /**
7581  * i40e_aq_send_msg_to_pf
7582  * @hw: pointer to the hardware structure
7583  * @v_opcode: opcodes for VF-PF communication
7584  * @v_retval: return error code
7585  * @msg: pointer to the msg buffer
7586  * @msglen: msg length
7587  * @cmd_details: pointer to command details
7588  *
7589  * Send message to PF driver using admin queue. By default, this message
7590  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7591  * completion before returning.
7592  **/
7593 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7594                                 enum virtchnl_ops v_opcode,
7595                                 enum i40e_status_code v_retval,
7596                                 u8 *msg, u16 msglen,
7597                                 struct i40e_asq_cmd_details *cmd_details)
7598 {
7599         struct i40e_aq_desc desc;
7600         struct i40e_asq_cmd_details details;
7601         enum i40e_status_code status;
7602
7603         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7604         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7605         desc.cookie_high = CPU_TO_LE32(v_opcode);
7606         desc.cookie_low = CPU_TO_LE32(v_retval);
7607         if (msglen) {
7608                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7609                                                 | I40E_AQ_FLAG_RD));
7610                 if (msglen > I40E_AQ_LARGE_BUF)
7611                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7612                 desc.datalen = CPU_TO_LE16(msglen);
7613         }
7614         if (!cmd_details) {
7615                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7616                 details.async = true;
7617                 cmd_details = &details;
7618         }
7619         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7620                                        msglen, cmd_details);
7621         return status;
7622 }
7623
7624 /**
7625  * i40e_vf_parse_hw_config
7626  * @hw: pointer to the hardware structure
7627  * @msg: pointer to the virtual channel VF resource structure
7628  *
7629  * Given a VF resource message from the PF, populate the hw struct
7630  * with appropriate information.
7631  **/
7632 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7633                              struct virtchnl_vf_resource *msg)
7634 {
7635         struct virtchnl_vsi_resource *vsi_res;
7636         int i;
7637
7638         vsi_res = &msg->vsi_res[0];
7639
7640         hw->dev_caps.num_vsis = msg->num_vsis;
7641         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7642         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7643         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7644         hw->dev_caps.dcb = msg->vf_cap_flags &
7645                            VIRTCHNL_VF_OFFLOAD_L2;
7646         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7647                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7648         for (i = 0; i < msg->num_vsis; i++) {
7649                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7650                         i40e_memcpy(hw->mac.perm_addr,
7651                                     vsi_res->default_mac_addr,
7652                                     ETH_ALEN,
7653                                     I40E_NONDMA_TO_NONDMA);
7654                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7655                                     ETH_ALEN,
7656                                     I40E_NONDMA_TO_NONDMA);
7657                 }
7658                 vsi_res++;
7659         }
7660 }
7661
7662 /**
7663  * i40e_vf_reset
7664  * @hw: pointer to the hardware structure
7665  *
7666  * Send a VF_RESET message to the PF. Does not wait for response from PF
7667  * as none will be forthcoming. Immediately after calling this function,
7668  * the admin queue should be shut down and (optionally) reinitialized.
7669  **/
7670 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7671 {
7672         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7673                                       I40E_SUCCESS, NULL, 0, NULL);
7674 }
7675 #endif /* VF_DRIVER */
7676
7677 /**
7678  * i40e_aq_set_arp_proxy_config
7679  * @hw: pointer to the HW structure
7680  * @proxy_config: pointer to proxy config command table struct
7681  * @cmd_details: pointer to command details
7682  *
7683  * Set ARP offload parameters from pre-populated
7684  * i40e_aqc_arp_proxy_data struct
7685  **/
7686 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7687                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7688                                 struct i40e_asq_cmd_details *cmd_details)
7689 {
7690         struct i40e_aq_desc desc;
7691         enum i40e_status_code status;
7692
7693         if (!proxy_config)
7694                 return I40E_ERR_PARAM;
7695
7696         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7697
7698         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7699         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7700         desc.params.external.addr_high =
7701                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7702         desc.params.external.addr_low =
7703                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7704         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7705
7706         status = i40e_asq_send_command(hw, &desc, proxy_config,
7707                                        sizeof(struct i40e_aqc_arp_proxy_data),
7708                                        cmd_details);
7709
7710         return status;
7711 }
7712
7713 /**
7714  * i40e_aq_opc_set_ns_proxy_table_entry
7715  * @hw: pointer to the HW structure
7716  * @ns_proxy_table_entry: pointer to NS table entry command struct
7717  * @cmd_details: pointer to command details
7718  *
7719  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7720  * from pre-populated i40e_aqc_ns_proxy_data struct
7721  **/
7722 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7723                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7724                         struct i40e_asq_cmd_details *cmd_details)
7725 {
7726         struct i40e_aq_desc desc;
7727         enum i40e_status_code status;
7728
7729         if (!ns_proxy_table_entry)
7730                 return I40E_ERR_PARAM;
7731
7732         i40e_fill_default_direct_cmd_desc(&desc,
7733                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7734
7735         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7736         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7737         desc.params.external.addr_high =
7738                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7739         desc.params.external.addr_low =
7740                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7741         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7742
7743         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7744                                        sizeof(struct i40e_aqc_ns_proxy_data),
7745                                        cmd_details);
7746
7747         return status;
7748 }
7749
7750 /**
7751  * i40e_aq_set_clear_wol_filter
7752  * @hw: pointer to the hw struct
7753  * @filter_index: index of filter to modify (0-7)
7754  * @filter: buffer containing filter to be set
7755  * @set_filter: true to set filter, false to clear filter
7756  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7757  *              if false, pass through packets may cause wake-up
7758  * @filter_valid: true if filter action is valid
7759  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7760  * @cmd_details: pointer to command details structure or NULL
7761  *
7762  * Set or clear WoL filter for port attached to the PF
7763  **/
7764 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7765                                 u8 filter_index,
7766                                 struct i40e_aqc_set_wol_filter_data *filter,
7767                                 bool set_filter, bool no_wol_tco,
7768                                 bool filter_valid, bool no_wol_tco_valid,
7769                                 struct i40e_asq_cmd_details *cmd_details)
7770 {
7771         struct i40e_aq_desc desc;
7772         struct i40e_aqc_set_wol_filter *cmd =
7773                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7774         enum i40e_status_code status;
7775         u16 cmd_flags = 0;
7776         u16 valid_flags = 0;
7777         u16 buff_len = 0;
7778
7779         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7780
7781         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7782                 return  I40E_ERR_PARAM;
7783         cmd->filter_index = CPU_TO_LE16(filter_index);
7784
7785         if (set_filter) {
7786                 if (!filter)
7787                         return  I40E_ERR_PARAM;
7788
7789                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7790                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7791         }
7792
7793         if (no_wol_tco)
7794                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7795         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7796
7797         if (filter_valid)
7798                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7799         if (no_wol_tco_valid)
7800                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7801         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7802
7803         buff_len = sizeof(*filter);
7804         desc.datalen = CPU_TO_LE16(buff_len);
7805
7806         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7807         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7808
7809         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7810         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7811
7812         status = i40e_asq_send_command(hw, &desc, filter,
7813                                        buff_len, cmd_details);
7814
7815         return status;
7816 }
7817
7818 /**
7819  * i40e_aq_get_wake_event_reason
7820  * @hw: pointer to the hw struct
7821  * @wake_reason: return value, index of matching filter
7822  * @cmd_details: pointer to command details structure or NULL
7823  *
7824  * Get information for the reason of a Wake Up event
7825  **/
7826 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7827                                 u16 *wake_reason,
7828                                 struct i40e_asq_cmd_details *cmd_details)
7829 {
7830         struct i40e_aq_desc desc;
7831         struct i40e_aqc_get_wake_reason_completion *resp =
7832                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7833         enum i40e_status_code status;
7834
7835         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7836
7837         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7838
7839         if (status == I40E_SUCCESS)
7840                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7841
7842         return status;
7843 }
7844
7845 /**
7846 * i40e_aq_clear_all_wol_filters
7847 * @hw: pointer to the hw struct
7848 * @cmd_details: pointer to command details structure or NULL
7849 *
7850 * Get information for the reason of a Wake Up event
7851 **/
7852 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7853         struct i40e_asq_cmd_details *cmd_details)
7854 {
7855         struct i40e_aq_desc desc;
7856         enum i40e_status_code status;
7857
7858         i40e_fill_default_direct_cmd_desc(&desc,
7859                                           i40e_aqc_opc_clear_all_wol_filters);
7860
7861         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7862
7863         return status;
7864 }
7865
7866 /**
7867  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7868  * @hw: pointer to the hw struct
7869  * @buff: command buffer (size in bytes = buff_size)
7870  * @buff_size: buffer size in bytes
7871  * @track_id: package tracking id
7872  * @error_offset: returns error offset
7873  * @error_info: returns error information
7874  * @cmd_details: pointer to command details structure or NULL
7875  **/
7876 enum
7877 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7878                                    u16 buff_size, u32 track_id,
7879                                    u32 *error_offset, u32 *error_info,
7880                                    struct i40e_asq_cmd_details *cmd_details)
7881 {
7882         struct i40e_aq_desc desc;
7883         struct i40e_aqc_write_personalization_profile *cmd =
7884                 (struct i40e_aqc_write_personalization_profile *)
7885                 &desc.params.raw;
7886         struct i40e_aqc_write_ddp_resp *resp;
7887         enum i40e_status_code status;
7888
7889         i40e_fill_default_direct_cmd_desc(&desc,
7890                                   i40e_aqc_opc_write_personalization_profile);
7891
7892         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7893         if (buff_size > I40E_AQ_LARGE_BUF)
7894                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7895
7896         desc.datalen = CPU_TO_LE16(buff_size);
7897
7898         cmd->profile_track_id = CPU_TO_LE32(track_id);
7899
7900         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7901         if (!status) {
7902                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7903                 if (error_offset)
7904                         *error_offset = LE32_TO_CPU(resp->error_offset);
7905                 if (error_info)
7906                         *error_info = LE32_TO_CPU(resp->error_info);
7907         }
7908
7909         return status;
7910 }
7911
7912 /**
7913  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7914  * @hw: pointer to the hw struct
7915  * @buff: command buffer (size in bytes = buff_size)
7916  * @buff_size: buffer size in bytes
7917  * @flags: AdminQ command flags
7918  * @cmd_details: pointer to command details structure or NULL
7919  **/
7920 enum
7921 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7922                                       u16 buff_size, u8 flags,
7923                                       struct i40e_asq_cmd_details *cmd_details)
7924 {
7925         struct i40e_aq_desc desc;
7926         struct i40e_aqc_get_applied_profiles *cmd =
7927                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7928         enum i40e_status_code status;
7929
7930         i40e_fill_default_direct_cmd_desc(&desc,
7931                           i40e_aqc_opc_get_personalization_profile_list);
7932
7933         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7934         if (buff_size > I40E_AQ_LARGE_BUF)
7935                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7936         desc.datalen = CPU_TO_LE16(buff_size);
7937
7938         cmd->flags = flags;
7939
7940         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7941
7942         return status;
7943 }
7944
7945 /**
7946  * i40e_find_segment_in_package
7947  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7948  * @pkg_hdr: pointer to the package header to be searched
7949  *
7950  * This function searches a package file for a particular segment type. On
7951  * success it returns a pointer to the segment header, otherwise it will
7952  * return NULL.
7953  **/
7954 struct i40e_generic_seg_header *
7955 i40e_find_segment_in_package(u32 segment_type,
7956                              struct i40e_package_header *pkg_hdr)
7957 {
7958         struct i40e_generic_seg_header *segment;
7959         u32 i;
7960
7961         /* Search all package segments for the requested segment type */
7962         for (i = 0; i < pkg_hdr->segment_count; i++) {
7963                 segment =
7964                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7965                          pkg_hdr->segment_offset[i]);
7966
7967                 if (segment->type == segment_type)
7968                         return segment;
7969         }
7970
7971         return NULL;
7972 }
7973
7974 /* Get section table in profile */
7975 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7976         do {                                                            \
7977                 struct i40e_profile_segment *p = (profile);             \
7978                 u32 count;                                              \
7979                 u32 *nvm;                                               \
7980                 count = p->device_table_count;                          \
7981                 nvm = (u32 *)&p->device_table[count];                   \
7982                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7983         } while (0)
7984
7985 /* Get section header in profile */
7986 #define I40E_SECTION_HEADER(profile, offset)                            \
7987         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7988
7989 /**
7990  * i40e_find_section_in_profile
7991  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7992  * @profile: pointer to the i40e segment header to be searched
7993  *
7994  * This function searches i40e segment for a particular section type. On
7995  * success it returns a pointer to the section header, otherwise it will
7996  * return NULL.
7997  **/
7998 struct i40e_profile_section_header *
7999 i40e_find_section_in_profile(u32 section_type,
8000                              struct i40e_profile_segment *profile)
8001 {
8002         struct i40e_profile_section_header *sec;
8003         struct i40e_section_table *sec_tbl;
8004         u32 sec_off;
8005         u32 i;
8006
8007         if (profile->header.type != SEGMENT_TYPE_I40E)
8008                 return NULL;
8009
8010         I40E_SECTION_TABLE(profile, sec_tbl);
8011
8012         for (i = 0; i < sec_tbl->section_count; i++) {
8013                 sec_off = sec_tbl->section_offset[i];
8014                 sec = I40E_SECTION_HEADER(profile, sec_off);
8015                 if (sec->section.type == section_type)
8016                         return sec;
8017         }
8018
8019         return NULL;
8020 }
8021
8022 /**
8023  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
8024  * @hw: pointer to the hw struct
8025  * @aq: command buffer containing all data to execute AQ
8026  **/
8027 STATIC enum
8028 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
8029                                           struct i40e_profile_aq_section *aq)
8030 {
8031         enum i40e_status_code status;
8032         struct i40e_aq_desc desc;
8033         u8 *msg = NULL;
8034         u16 msglen;
8035
8036         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
8037         desc.flags |= CPU_TO_LE16(aq->flags);
8038         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
8039                     I40E_NONDMA_TO_NONDMA);
8040
8041         msglen = aq->datalen;
8042         if (msglen) {
8043                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
8044                                                 I40E_AQ_FLAG_RD));
8045                 if (msglen > I40E_AQ_LARGE_BUF)
8046                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
8047                 desc.datalen = CPU_TO_LE16(msglen);
8048                 msg = &aq->data[0];
8049         }
8050
8051         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
8052
8053         if (status != I40E_SUCCESS) {
8054                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8055                            "unable to exec DDP AQ opcode %u, error %d\n",
8056                            aq->opcode, status);
8057                 return status;
8058         }
8059
8060         /* copy returned desc to aq_buf */
8061         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
8062                     I40E_NONDMA_TO_NONDMA);
8063
8064         return I40E_SUCCESS;
8065 }
8066
8067 /**
8068  * i40e_validate_profile
8069  * @hw: pointer to the hardware structure
8070  * @profile: pointer to the profile segment of the package to be validated
8071  * @track_id: package tracking id
8072  * @rollback: flag if the profile is for rollback.
8073  *
8074  * Validates supported devices and profile's sections.
8075  */
8076 STATIC enum i40e_status_code
8077 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8078                       u32 track_id, bool rollback)
8079 {
8080         struct i40e_profile_section_header *sec = NULL;
8081         enum i40e_status_code status = I40E_SUCCESS;
8082         struct i40e_section_table *sec_tbl;
8083         u32 vendor_dev_id;
8084         u32 dev_cnt;
8085         u32 sec_off;
8086         u32 i;
8087
8088         if (track_id == I40E_DDP_TRACKID_INVALID) {
8089                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
8090                 return I40E_NOT_SUPPORTED;
8091         }
8092
8093         dev_cnt = profile->device_table_count;
8094         for (i = 0; i < dev_cnt; i++) {
8095                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
8096                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
8097                     hw->device_id == (vendor_dev_id & 0xFFFF))
8098                         break;
8099         }
8100         if (dev_cnt && (i == dev_cnt)) {
8101                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8102                            "Device doesn't support DDP\n");
8103                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
8104         }
8105
8106         I40E_SECTION_TABLE(profile, sec_tbl);
8107
8108         /* Validate sections types */
8109         for (i = 0; i < sec_tbl->section_count; i++) {
8110                 sec_off = sec_tbl->section_offset[i];
8111                 sec = I40E_SECTION_HEADER(profile, sec_off);
8112                 if (rollback) {
8113                         if (sec->section.type == SECTION_TYPE_MMIO ||
8114                             sec->section.type == SECTION_TYPE_AQ ||
8115                             sec->section.type == SECTION_TYPE_RB_AQ) {
8116                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8117                                            "Not a roll-back package\n");
8118                                 return I40E_NOT_SUPPORTED;
8119                         }
8120                 } else {
8121                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
8122                             sec->section.type == SECTION_TYPE_RB_MMIO) {
8123                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8124                                            "Not an original package\n");
8125                                 return I40E_NOT_SUPPORTED;
8126                         }
8127                 }
8128         }
8129
8130         return status;
8131 }
8132
8133 /**
8134  * i40e_write_profile
8135  * @hw: pointer to the hardware structure
8136  * @profile: pointer to the profile segment of the package to be downloaded
8137  * @track_id: package tracking id
8138  *
8139  * Handles the download of a complete package.
8140  */
8141 enum i40e_status_code
8142 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8143                    u32 track_id)
8144 {
8145         enum i40e_status_code status = I40E_SUCCESS;
8146         struct i40e_section_table *sec_tbl;
8147         struct i40e_profile_section_header *sec = NULL;
8148         struct i40e_profile_aq_section *ddp_aq;
8149         u32 section_size = 0;
8150         u32 offset = 0, info = 0;
8151         u32 sec_off;
8152         u32 i;
8153
8154         status = i40e_validate_profile(hw, profile, track_id, false);
8155         if (status)
8156                 return status;
8157
8158         I40E_SECTION_TABLE(profile, sec_tbl);
8159
8160         for (i = 0; i < sec_tbl->section_count; i++) {
8161                 sec_off = sec_tbl->section_offset[i];
8162                 sec = I40E_SECTION_HEADER(profile, sec_off);
8163                 /* Process generic admin command */
8164                 if (sec->section.type == SECTION_TYPE_AQ) {
8165                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
8166                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
8167                         if (status) {
8168                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
8169                                            "Failed to execute aq: section %d, opcode %u\n",
8170                                            i, ddp_aq->opcode);
8171                                 break;
8172                         }
8173                         sec->section.type = SECTION_TYPE_RB_AQ;
8174                 }
8175
8176                 /* Skip any non-mmio sections */
8177                 if (sec->section.type != SECTION_TYPE_MMIO)
8178                         continue;
8179
8180                 section_size = sec->section.size +
8181                         sizeof(struct i40e_profile_section_header);
8182
8183                 /* Write MMIO section */
8184                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8185                                            track_id, &offset, &info, NULL);
8186                 if (status) {
8187                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8188                                    "Failed to write profile: section %d, offset %d, info %d\n",
8189                                    i, offset, info);
8190                         break;
8191                 }
8192         }
8193         return status;
8194 }
8195
8196 /**
8197  * i40e_rollback_profile
8198  * @hw: pointer to the hardware structure
8199  * @profile: pointer to the profile segment of the package to be removed
8200  * @track_id: package tracking id
8201  *
8202  * Rolls back previously loaded package.
8203  */
8204 enum i40e_status_code
8205 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
8206                       u32 track_id)
8207 {
8208         struct i40e_profile_section_header *sec = NULL;
8209         enum i40e_status_code status = I40E_SUCCESS;
8210         struct i40e_section_table *sec_tbl;
8211         u32 offset = 0, info = 0;
8212         u32 section_size = 0;
8213         u32 sec_off;
8214         int i;
8215
8216         status = i40e_validate_profile(hw, profile, track_id, true);
8217         if (status)
8218                 return status;
8219
8220         I40E_SECTION_TABLE(profile, sec_tbl);
8221
8222         /* For rollback write sections in reverse */
8223         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
8224                 sec_off = sec_tbl->section_offset[i];
8225                 sec = I40E_SECTION_HEADER(profile, sec_off);
8226
8227                 /* Skip any non-rollback sections */
8228                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
8229                         continue;
8230
8231                 section_size = sec->section.size +
8232                         sizeof(struct i40e_profile_section_header);
8233
8234                 /* Write roll-back MMIO section */
8235                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
8236                                            track_id, &offset, &info, NULL);
8237                 if (status) {
8238                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
8239                                    "Failed to write profile: section %d, offset %d, info %d\n",
8240                                    i, offset, info);
8241                         break;
8242                 }
8243         }
8244         return status;
8245 }
8246
8247 /**
8248  * i40e_add_pinfo_to_list
8249  * @hw: pointer to the hardware structure
8250  * @profile: pointer to the profile segment of the package
8251  * @profile_info_sec: buffer for information section
8252  * @track_id: package tracking id
8253  *
8254  * Register a profile to the list of loaded profiles.
8255  */
8256 enum i40e_status_code
8257 i40e_add_pinfo_to_list(struct i40e_hw *hw,
8258                        struct i40e_profile_segment *profile,
8259                        u8 *profile_info_sec, u32 track_id)
8260 {
8261         enum i40e_status_code status = I40E_SUCCESS;
8262         struct i40e_profile_section_header *sec = NULL;
8263         struct i40e_profile_info *pinfo;
8264         u32 offset = 0, info = 0;
8265
8266         sec = (struct i40e_profile_section_header *)profile_info_sec;
8267         sec->tbl_size = 1;
8268         sec->data_end = sizeof(struct i40e_profile_section_header) +
8269                         sizeof(struct i40e_profile_info);
8270         sec->section.type = SECTION_TYPE_INFO;
8271         sec->section.offset = sizeof(struct i40e_profile_section_header);
8272         sec->section.size = sizeof(struct i40e_profile_info);
8273         pinfo = (struct i40e_profile_info *)(profile_info_sec +
8274                                              sec->section.offset);
8275         pinfo->track_id = track_id;
8276         pinfo->version = profile->version;
8277         pinfo->op = I40E_DDP_ADD_TRACKID;
8278         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
8279                     I40E_NONDMA_TO_NONDMA);
8280
8281         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
8282                                    track_id, &offset, &info, NULL);
8283         return status;
8284 }