drivers/net/i40e/base/i40e_nvm.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_prototype.h"
  35
  36 /**
  37  * i40e_init_nvm_ops - Initialize NVM function pointers
  38  * @hw: pointer to the HW structure
  39  *
  40  * Setup the function pointers and the NVM info structure. Should be called
  41  * once per NVM initialization, e.g. inside the i40e_init_shared_code().
  42  * Please notice that the NVM term is used here (& in all methods covered
  43  * in this file) as an equivalent of the FLASH part mapped into the SR.
  44  * We are accessing FLASH always through the Shadow RAM.
  45  **/
  46 enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
  47 {
  48         struct i40e_nvm_info *nvm = &hw->nvm;
  49         enum i40e_status_code ret_code = I40E_SUCCESS;
  50         u32 fla, gens;
  51         u8 sr_size;
  52
  53         DEBUGFUNC("i40e_init_nvm");
  54
  55         /* The SR size is stored regardless of the nvm programming mode
  56          * as the blank mode may be used in the factory line.
  57          */
  58         gens = rd32(hw, I40E_GLNVM_GENS);
  59         sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
  60                            I40E_GLNVM_GENS_SR_SIZE_SHIFT);
  61         /* Switching to words (sr_size contains power of 2KB) */
  62         nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
  63
  64         /* Check if we are in the normal or blank NVM programming mode */
  65         fla = rd32(hw, I40E_GLNVM_FLA);
  66         if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
  67                 /* Max NVM timeout */
  68                 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
  69                 nvm->blank_nvm_mode = false;
  70         } else { /* Blank programming mode */
  71                 nvm->blank_nvm_mode = true;
  72                 ret_code = I40E_ERR_NVM_BLANK_MODE;
  73                 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
  74         }
  75
  76         return ret_code;
  77 }
  78
  79 /**
  80  * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
  81  * @hw: pointer to the HW structure
  82  * @access: NVM access type (read or write)
  83  *
  84  * This function will request NVM ownership for reading
  85  * via the proper Admin Command.
  86  **/
  87 enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
  88                                        enum i40e_aq_resource_access_type access)
  89 {
  90         enum i40e_status_code ret_code = I40E_SUCCESS;
  91         u64 gtime, timeout;
  92         u64 time_left = 0;
  93
  94         DEBUGFUNC("i40e_acquire_nvm");
  95
  96         if (hw->nvm.blank_nvm_mode)
  97                 goto i40e_i40e_acquire_nvm_exit;
  98
  99         ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
 100                                             0, &time_left, NULL);
 101         /* Reading the Global Device Timer */
 102         gtime = rd32(hw, I40E_GLVFGEN_TIMER);
 103
 104         /* Store the timeout */
 105         hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
 106
 107         if (ret_code)
 108                 i40e_debug(hw, I40E_DEBUG_NVM,
 109                            "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
 110                            access, time_left, ret_code, hw->aq.asq_last_status);
 111
 112         if (ret_code && time_left) {
 113                 /* Poll until the current NVM owner timeouts */
 114                 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
 115                 while ((gtime < timeout) && time_left) {
 116                         i40e_msec_delay(10);
 117                         gtime = rd32(hw, I40E_GLVFGEN_TIMER);
 118                         ret_code = i40e_aq_request_resource(hw,
 119                                                         I40E_NVM_RESOURCE_ID,
 120                                                         access, 0, &time_left,
 121                                                         NULL);
 122                         if (ret_code == I40E_SUCCESS) {
 123                                 hw->nvm.hw_semaphore_timeout =
 124                                             I40E_MS_TO_GTIME(time_left) + gtime;
 125                                 break;
 126                         }
 127                 }
 128                 if (ret_code != I40E_SUCCESS) {
 129                         hw->nvm.hw_semaphore_timeout = 0;
 130                         i40e_debug(hw, I40E_DEBUG_NVM,
 131                                    "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
 132                                    time_left, ret_code, hw->aq.asq_last_status);
 133                 }
 134         }
 135
 136 i40e_i40e_acquire_nvm_exit:
 137         return ret_code;
 138 }
 139
 140 /**
 141  * i40e_release_nvm - Generic request for releasing the NVM ownership
 142  * @hw: pointer to the HW structure
 143  *
 144  * This function will release NVM resource via the proper Admin Command.
 145  **/
 146 void i40e_release_nvm(struct i40e_hw *hw)
 147 {
 148         enum i40e_status_code ret_code = I40E_SUCCESS;
 149         u32 total_delay = 0;
 150
 151         DEBUGFUNC("i40e_release_nvm");
 152
 153         if (hw->nvm.blank_nvm_mode)
 154                 return;
 155
 156         ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
 157
 158         /* there are some rare cases when trying to release the resource
 159          * results in an admin Q timeout, so handle them correctly
 160          */
 161         while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) &&
 162                (total_delay < hw->aq.asq_cmd_timeout)) {
 163                         i40e_msec_delay(1);
 164                         ret_code = i40e_aq_release_resource(hw,
 165                                                 I40E_NVM_RESOURCE_ID, 0, NULL);
 166                         total_delay++;
 167         }
 168 }
 169
 170 /**
 171  * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
 172  * @hw: pointer to the HW structure
 173  *
 174  * Polls the SRCTL Shadow RAM register done bit.
 175  **/
 176 static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
 177 {
 178         enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
 179         u32 srctl, wait_cnt;
 180
 181         DEBUGFUNC("i40e_poll_sr_srctl_done_bit");
 182
 183         /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
 184         for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
 185                 srctl = rd32(hw, I40E_GLNVM_SRCTL);
 186                 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
 187                         ret_code = I40E_SUCCESS;
 188                         break;
 189                 }
 190                 i40e_usec_delay(5);
 191         }
 192         if (ret_code == I40E_ERR_TIMEOUT)
 193                 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
 194         return ret_code;
 195 }
 196
 197 /**
 198  * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
 199  * @hw: pointer to the HW structure
 200  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 201  * @data: word read from the Shadow RAM
 202  *
 203  * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
 204  **/
 205 STATIC enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw,
 206                                                       u16 offset,
 207                                                       u16 *data)
 208 {
 209         enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
 210         u32 sr_reg;
 211
 212         DEBUGFUNC("i40e_read_nvm_word_srctl");
 213
 214         if (offset >= hw->nvm.sr_size) {
 215                 i40e_debug(hw, I40E_DEBUG_NVM,
 216                            "NVM read error: Offset %d beyond Shadow RAM limit %d\n",
 217                            offset, hw->nvm.sr_size);
 218                 ret_code = I40E_ERR_PARAM;
 219                 goto read_nvm_exit;
 220         }
 221
 222         /* Poll the done bit first */
 223         ret_code = i40e_poll_sr_srctl_done_bit(hw);
 224         if (ret_code == I40E_SUCCESS) {
 225                 /* Write the address and start reading */
 226                 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
 227                          BIT(I40E_GLNVM_SRCTL_START_SHIFT);
 228                 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
 229
 230                 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
 231                 ret_code = i40e_poll_sr_srctl_done_bit(hw);
 232                 if (ret_code == I40E_SUCCESS) {
 233                         sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
 234                         *data = (u16)((sr_reg &
 235                                        I40E_GLNVM_SRDATA_RDDATA_MASK)
 236                                     >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
 237                 }
 238         }
 239         if (ret_code != I40E_SUCCESS)
 240                 i40e_debug(hw, I40E_DEBUG_NVM,
 241                            "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
 242                            offset);
 243
 244 read_nvm_exit:
 245         return ret_code;
 246 }
 247
 248 /**
 249  * i40e_read_nvm_aq - Read Shadow RAM.
 250  * @hw: pointer to the HW structure.
 251  * @module_pointer: module pointer location in words from the NVM beginning
 252  * @offset: offset in words from module start
 253  * @words: number of words to write
 254  * @data: buffer with words to write to the Shadow RAM
 255  * @last_command: tells the AdminQ that this is the last command
 256  *
 257  * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 258  **/
 259 STATIC enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw,
 260                                               u8 module_pointer, u32 offset,
 261                                               u16 words, void *data,
 262                                               bool last_command)
 263 {
 264         enum i40e_status_code ret_code = I40E_ERR_NVM;
 265         struct i40e_asq_cmd_details cmd_details;
 266
 267         DEBUGFUNC("i40e_read_nvm_aq");
 268
 269         memset(&cmd_details, 0, sizeof(cmd_details));
 270         cmd_details.wb_desc = &hw->nvm_wb_desc;
 271
 272         /* Here we are checking the SR limit only for the flat memory model.
 273          * We cannot do it for the module-based model, as we did not acquire
 274          * the NVM resource yet (we cannot get the module pointer value).
 275          * Firmware will check the module-based model.
 276          */
 277         if ((offset + words) > hw->nvm.sr_size)
 278                 i40e_debug(hw, I40E_DEBUG_NVM,
 279                            "NVM write error: offset %d beyond Shadow RAM limit %d\n",
 280                            (offset + words), hw->nvm.sr_size);
 281         else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
 282                 /* We can write only up to 4KB (one sector), in one AQ write */
 283                 i40e_debug(hw, I40E_DEBUG_NVM,
 284                            "NVM write fail error: tried to write %d words, limit is %d.\n",
 285                            words, I40E_SR_SECTOR_SIZE_IN_WORDS);
 286         else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
 287                  != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
 288                 /* A single write cannot spread over two sectors */
 289                 i40e_debug(hw, I40E_DEBUG_NVM,
 290                            "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
 291                            offset, words);
 292         else
 293                 ret_code = i40e_aq_read_nvm(hw, module_pointer,
 294                                             2 * offset,  /*bytes*/
 295                                             2 * words,   /*bytes*/
 296                                             data, last_command, &cmd_details);
 297
 298         return ret_code;
 299 }
 300
 301 /**
 302  * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
 303  * @hw: pointer to the HW structure
 304  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 305  * @data: word read from the Shadow RAM
 306  *
 307  * Reads one 16 bit word from the Shadow RAM using the AdminQ
 308  **/
 309 STATIC enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
 310                                                    u16 *data)
 311 {
 312         enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
 313
 314         DEBUGFUNC("i40e_read_nvm_word_aq");
 315
 316         ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
 317         *data = LE16_TO_CPU(*(__le16 *)data);
 318
 319         return ret_code;
 320 }
 321
 322 /**
 323  * __i40e_read_nvm_word - Reads NVM word, assumes caller does the locking
 324  * @hw: pointer to the HW structure
 325  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 326  * @data: word read from the Shadow RAM
 327  *
 328  * Reads one 16 bit word from the Shadow RAM.
 329  *
 330  * Do not use this function except in cases where the nvm lock is already
 331  * taken via i40e_acquire_nvm().
 332  **/
 333 enum i40e_status_code __i40e_read_nvm_word(struct i40e_hw *hw,
 334                                            u16 offset,
 335                                            u16 *data)
 336 {
 337
 338         if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
 339                 return i40e_read_nvm_word_aq(hw, offset, data);
 340
 341         return i40e_read_nvm_word_srctl(hw, offset, data);
 342 }
 343
 344 /**
 345  * i40e_read_nvm_word - Reads NVM word, acquires lock if necessary
 346  * @hw: pointer to the HW structure
 347  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 348  * @data: word read from the Shadow RAM
 349  *
 350  * Reads one 16 bit word from the Shadow RAM.
 351  **/
 352 enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
 353                                          u16 *data)
 354 {
 355         enum i40e_status_code ret_code = I40E_SUCCESS;
 356
 357         if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
 358                 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 359
 360         if (ret_code)
 361                 return ret_code;
 362         ret_code = __i40e_read_nvm_word(hw, offset, data);
 363
 364         if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
 365                 i40e_release_nvm(hw);
 366         return ret_code;
 367 }
 368
 369 /**
 370  * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
 371  * @hw: pointer to the HW structure
 372  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 373  * @words: (in) number of words to read; (out) number of words actually read
 374  * @data: words read from the Shadow RAM
 375  *
 376  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
 377  * method. The buffer read is preceded by the NVM ownership take
 378  * and followed by the release.
 379  **/
 380 STATIC enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
 381                                                         u16 *words, u16 *data)
 382 {
 383         enum i40e_status_code ret_code = I40E_SUCCESS;
 384         u16 index, word;
 385
 386         DEBUGFUNC("i40e_read_nvm_buffer_srctl");
 387
 388         /* Loop through the selected region */
 389         for (word = 0; word < *words; word++) {
 390                 index = offset + word;
 391                 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
 392                 if (ret_code != I40E_SUCCESS)
 393                         break;
 394         }
 395
 396         /* Update the number of words read from the Shadow RAM */
 397         *words = word;
 398
 399         return ret_code;
 400 }
 401
 402 /**
 403  * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
 404  * @hw: pointer to the HW structure
 405  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 406  * @words: (in) number of words to read; (out) number of words actually read
 407  * @data: words read from the Shadow RAM
 408  *
 409  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
 410  * method. The buffer read is preceded by the NVM ownership take
 411  * and followed by the release.
 412  **/
 413 STATIC enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
 414                                                      u16 *words, u16 *data)
 415 {
 416         enum i40e_status_code ret_code;
 417         u16 read_size = *words;
 418         bool last_cmd = false;
 419         u16 words_read = 0;
 420         u16 i = 0;
 421
 422         DEBUGFUNC("i40e_read_nvm_buffer_aq");
 423
 424         do {
 425                 /* Calculate number of bytes we should read in this step.
 426                  * FVL AQ do not allow to read more than one page at a time or
 427                  * to cross page boundaries.
 428                  */
 429                 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
 430                         read_size = min(*words,
 431                                         (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
 432                                       (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
 433                 else
 434                         read_size = min((*words - words_read),
 435                                         I40E_SR_SECTOR_SIZE_IN_WORDS);
 436
 437                 /* Check if this is last command, if so set proper flag */
 438                 if ((words_read + read_size) >= *words)
 439                         last_cmd = true;
 440
 441                 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
 442                                             data + words_read, last_cmd);
 443                 if (ret_code != I40E_SUCCESS)
 444                         goto read_nvm_buffer_aq_exit;
 445
 446                 /* Increment counter for words already read and move offset to
 447                  * new read location
 448                  */
 449                 words_read += read_size;
 450                 offset += read_size;
 451         } while (words_read < *words);
 452
 453         for (i = 0; i < *words; i++)
 454                 data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
 455
 456 read_nvm_buffer_aq_exit:
 457         *words = words_read;
 458         return ret_code;
 459 }
 460
 461 /**
 462  * __i40e_read_nvm_buffer - Reads NVM buffer, caller must acquire lock
 463  * @hw: pointer to the HW structure
 464  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 465  * @words: (in) number of words to read; (out) number of words actually read
 466  * @data: words read from the Shadow RAM
 467  *
 468  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
 469  * method.
 470  **/
 471 enum i40e_status_code __i40e_read_nvm_buffer(struct i40e_hw *hw,
 472                                              u16 offset,
 473                                              u16 *words, u16 *data)
 474 {
 475         if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
 476                 return i40e_read_nvm_buffer_aq(hw, offset, words, data);
 477
 478         return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
 479 }
 480
 481 /**
 482  * i40e_read_nvm_buffer - Reads Shadow RAM buffer and acquire lock if necessary
 483  * @hw: pointer to the HW structure
 484  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 485  * @words: (in) number of words to read; (out) number of words actually read
 486  * @data: words read from the Shadow RAM
 487  *
 488  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
 489  * method. The buffer read is preceded by the NVM ownership take
 490  * and followed by the release.
 491  **/
 492 enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
 493                                            u16 *words, u16 *data)
 494 {
 495         enum i40e_status_code ret_code = I40E_SUCCESS;
 496
 497         if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
 498                 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 499                 if (!ret_code) {
 500                         ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
 501                                                          data);
 502                         i40e_release_nvm(hw);
 503                 }
 504         } else {
 505                 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
 506         }
 507
 508         return ret_code;
 509 }
 510
 511 /**
 512  * i40e_write_nvm_aq - Writes Shadow RAM.
 513  * @hw: pointer to the HW structure.
 514  * @module_pointer: module pointer location in words from the NVM beginning
 515  * @offset: offset in words from module start
 516  * @words: number of words to write
 517  * @data: buffer with words to write to the Shadow RAM
 518  * @last_command: tells the AdminQ that this is the last command
 519  *
 520  * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 521  **/
 522 enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
 523                                         u32 offset, u16 words, void *data,
 524                                         bool last_command)
 525 {
 526         enum i40e_status_code ret_code = I40E_ERR_NVM;
 527         struct i40e_asq_cmd_details cmd_details;
 528
 529         DEBUGFUNC("i40e_write_nvm_aq");
 530
 531         memset(&cmd_details, 0, sizeof(cmd_details));
 532         cmd_details.wb_desc = &hw->nvm_wb_desc;
 533
 534         /* Here we are checking the SR limit only for the flat memory model.
 535          * We cannot do it for the module-based model, as we did not acquire
 536          * the NVM resource yet (we cannot get the module pointer value).
 537          * Firmware will check the module-based model.
 538          */
 539         if ((offset + words) > hw->nvm.sr_size)
 540                 DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
 541         else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
 542                 /* We can write only up to 4KB (one sector), in one AQ write */
 543                 DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
 544         else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
 545                  != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
 546                 /* A single write cannot spread over two sectors */
 547                 DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
 548         else
 549                 ret_code = i40e_aq_update_nvm(hw, module_pointer,
 550                                               2 * offset,  /*bytes*/
 551                                               2 * words,   /*bytes*/
 552                                               data, last_command, 0,
 553                                               &cmd_details);
 554
 555         return ret_code;
 556 }
 557
 558 /**
 559  * __i40e_write_nvm_word - Writes Shadow RAM word
 560  * @hw: pointer to the HW structure
 561  * @offset: offset of the Shadow RAM word to write
 562  * @data: word to write to the Shadow RAM
 563  *
 564  * Writes a 16 bit word to the SR using the i40e_write_nvm_aq() method.
 565  * NVM ownership have to be acquired and released (on ARQ completion event
 566  * reception) by caller. To commit SR to NVM update checksum function
 567  * should be called.
 568  **/
 569 enum i40e_status_code __i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
 570                                             void *data)
 571 {
 572         DEBUGFUNC("i40e_write_nvm_word");
 573
 574         *((__le16 *)data) = CPU_TO_LE16(*((u16 *)data));
 575
 576         /* Value 0x00 below means that we treat SR as a flat mem */
 577         return i40e_write_nvm_aq(hw, 0x00, offset, 1, data, false);
 578 }
 579
 580 /**
 581  * __i40e_write_nvm_buffer - Writes Shadow RAM buffer
 582  * @hw: pointer to the HW structure
 583  * @module_pointer: module pointer location in words from the NVM beginning
 584  * @offset: offset of the Shadow RAM buffer to write
 585  * @words: number of words to write
 586  * @data: words to write to the Shadow RAM
 587  *
 588  * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 589  * NVM ownership must be acquired before calling this function and released
 590  * on ARQ completion event reception by caller. To commit SR to NVM update
 591  * checksum function should be called.
 592  **/
 593 enum i40e_status_code __i40e_write_nvm_buffer(struct i40e_hw *hw,
 594                                               u8 module_pointer, u32 offset,
 595                                               u16 words, void *data)
 596 {
 597         __le16 *le_word_ptr = (__le16 *)data;
 598         u16 *word_ptr = (u16 *)data;
 599         u32 i = 0;
 600
 601         DEBUGFUNC("i40e_write_nvm_buffer");
 602
 603         for (i = 0; i < words; i++)
 604                 le_word_ptr[i] = CPU_TO_LE16(word_ptr[i]);
 605
 606         /* Here we will only write one buffer as the size of the modules
 607          * mirrored in the Shadow RAM is always less than 4K.
 608          */
 609         return i40e_write_nvm_aq(hw, module_pointer, offset, words,
 610                                  data, false);
 611 }
 612
 613 /**
 614  * i40e_calc_nvm_checksum - Calculates and returns the checksum
 615  * @hw: pointer to hardware structure
 616  * @checksum: pointer to the checksum
 617  *
 618  * This function calculates SW Checksum that covers the whole 64kB shadow RAM
 619  * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
 620  * is customer specific and unknown. Therefore, this function skips all maximum
 621  * possible size of VPD (1kB).
 622  **/
 623 enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)
 624 {
 625         enum i40e_status_code ret_code = I40E_SUCCESS;
 626         struct i40e_virt_mem vmem;
 627         u16 pcie_alt_module = 0;
 628         u16 checksum_local = 0;
 629         u16 vpd_module = 0;
 630         u16 *data;
 631         u16 i = 0;
 632
 633         DEBUGFUNC("i40e_calc_nvm_checksum");
 634
 635         ret_code = i40e_allocate_virt_mem(hw, &vmem,
 636                                     I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
 637         if (ret_code)
 638                 goto i40e_calc_nvm_checksum_exit;
 639         data = (u16 *)vmem.va;
 640
 641         /* read pointer to VPD area */
 642         ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
 643         if (ret_code != I40E_SUCCESS) {
 644                 ret_code = I40E_ERR_NVM_CHECKSUM;
 645                 goto i40e_calc_nvm_checksum_exit;
 646         }
 647
 648         /* read pointer to PCIe Alt Auto-load module */
 649         ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
 650                                         &pcie_alt_module);
 651         if (ret_code != I40E_SUCCESS) {
 652                 ret_code = I40E_ERR_NVM_CHECKSUM;
 653                 goto i40e_calc_nvm_checksum_exit;
 654         }
 655
 656         /* Calculate SW checksum that covers the whole 64kB shadow RAM
 657          * except the VPD and PCIe ALT Auto-load modules
 658          */
 659         for (i = 0; i < hw->nvm.sr_size; i++) {
 660                 /* Read SR page */
 661                 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
 662                         u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
 663
 664                         ret_code = __i40e_read_nvm_buffer(hw, i, &words, data);
 665                         if (ret_code != I40E_SUCCESS) {
 666                                 ret_code = I40E_ERR_NVM_CHECKSUM;
 667                                 goto i40e_calc_nvm_checksum_exit;
 668                         }
 669                 }
 670
 671                 /* Skip Checksum word */
 672                 if (i == I40E_SR_SW_CHECKSUM_WORD)
 673                         continue;
 674                 /* Skip VPD module (convert byte size to word count) */
 675                 if ((i >= (u32)vpd_module) &&
 676                     (i < ((u32)vpd_module +
 677                      (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
 678                         continue;
 679                 }
 680                 /* Skip PCIe ALT module (convert byte size to word count) */
 681                 if ((i >= (u32)pcie_alt_module) &&
 682                     (i < ((u32)pcie_alt_module +
 683                      (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
 684                         continue;
 685                 }
 686
 687                 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
 688         }
 689
 690         *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
 691
 692 i40e_calc_nvm_checksum_exit:
 693         i40e_free_virt_mem(hw, &vmem);
 694         return ret_code;
 695 }
 696
 697 /**
 698  * i40e_update_nvm_checksum - Updates the NVM checksum
 699  * @hw: pointer to hardware structure
 700  *
 701  * NVM ownership must be acquired before calling this function and released
 702  * on ARQ completion event reception by caller.
 703  * This function will commit SR to NVM.
 704  **/
 705 enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
 706 {
 707         enum i40e_status_code ret_code = I40E_SUCCESS;
 708         u16 checksum;
 709         __le16 le_sum;
 710
 711         DEBUGFUNC("i40e_update_nvm_checksum");
 712
 713         ret_code = i40e_calc_nvm_checksum(hw, &checksum);
 714         le_sum = CPU_TO_LE16(checksum);
 715         if (ret_code == I40E_SUCCESS)
 716                 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
 717                                              1, &le_sum, true);
 718
 719         return ret_code;
 720 }
 721
 722 /**
 723  * i40e_validate_nvm_checksum - Validate EEPROM checksum
 724  * @hw: pointer to hardware structure
 725  * @checksum: calculated checksum
 726  *
 727  * Performs checksum calculation and validates the NVM SW checksum. If the
 728  * caller does not need checksum, the value can be NULL.
 729  **/
 730 enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
 731                                                  u16 *checksum)
 732 {
 733         enum i40e_status_code ret_code = I40E_SUCCESS;
 734         u16 checksum_sr = 0;
 735         u16 checksum_local = 0;
 736
 737         DEBUGFUNC("i40e_validate_nvm_checksum");
 738
 739         /* We must acquire the NVM lock in order to correctly synchronize the
 740          * NVM accesses across multiple PFs. Without doing so it is possible
 741          * for one of the PFs to read invalid data potentially indicating that
 742          * the checksum is invalid.
 743          */
 744         ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 745         if (ret_code)
 746                 return ret_code;
 747         ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
 748         __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
 749         i40e_release_nvm(hw);
 750         if (ret_code)
 751                 return ret_code;
 752
 753         /* Verify read checksum from EEPROM is the same as
 754          * calculated checksum
 755          */
 756         if (checksum_local != checksum_sr)
 757                 ret_code = I40E_ERR_NVM_CHECKSUM;
 758
 759         /* If the user cares, return the calculated checksum */
 760         if (checksum)
 761                 *checksum = checksum_local;
 762
 763         return ret_code;
 764 }
 765
 766 STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
 767                                                     struct i40e_nvm_access *cmd,
 768                                                     u8 *bytes, int *perrno);
 769 STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
 770                                                     struct i40e_nvm_access *cmd,
 771                                                     u8 *bytes, int *perrno);
 772 STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
 773                                                     struct i40e_nvm_access *cmd,
 774                                                     u8 *bytes, int *perrno);
 775 STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
 776                                                     struct i40e_nvm_access *cmd,
 777                                                     int *perrno);
 778 STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
 779                                                    struct i40e_nvm_access *cmd,
 780                                                    int *perrno);
 781 STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
 782                                                    struct i40e_nvm_access *cmd,
 783                                                    u8 *bytes, int *perrno);
 784 STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
 785                                                   struct i40e_nvm_access *cmd,
 786                                                   u8 *bytes, int *perrno);
 787 STATIC enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw,
 788                                                  struct i40e_nvm_access *cmd,
 789                                                  u8 *bytes, int *perrno);
 790 STATIC enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
 791                                                     struct i40e_nvm_access *cmd,
 792                                                     u8 *bytes, int *perrno);
 793 STATIC INLINE u8 i40e_nvmupd_get_module(u32 val)
 794 {
 795         return (u8)(val & I40E_NVM_MOD_PNT_MASK);
 796 }
 797 STATIC INLINE u8 i40e_nvmupd_get_transaction(u32 val)
 798 {
 799         return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
 800 }
 801
 802 STATIC INLINE u8 i40e_nvmupd_get_preservation_flags(u32 val)
 803 {
 804         return (u8)((val & I40E_NVM_PRESERVATION_FLAGS_MASK) >>
 805                     I40E_NVM_PRESERVATION_FLAGS_SHIFT);
 806 }
 807
 808 STATIC const char *i40e_nvm_update_state_str[] = {
 809         "I40E_NVMUPD_INVALID",
 810         "I40E_NVMUPD_READ_CON",
 811         "I40E_NVMUPD_READ_SNT",
 812         "I40E_NVMUPD_READ_LCB",
 813         "I40E_NVMUPD_READ_SA",
 814         "I40E_NVMUPD_WRITE_ERA",
 815         "I40E_NVMUPD_WRITE_CON",
 816         "I40E_NVMUPD_WRITE_SNT",
 817         "I40E_NVMUPD_WRITE_LCB",
 818         "I40E_NVMUPD_WRITE_SA",
 819         "I40E_NVMUPD_CSUM_CON",
 820         "I40E_NVMUPD_CSUM_SA",
 821         "I40E_NVMUPD_CSUM_LCB",
 822         "I40E_NVMUPD_STATUS",
 823         "I40E_NVMUPD_EXEC_AQ",
 824         "I40E_NVMUPD_GET_AQ_RESULT",
 825 };
 826
 827 /**
 828  * i40e_nvmupd_command - Process an NVM update command
 829  * @hw: pointer to hardware structure
 830  * @cmd: pointer to nvm update command
 831  * @bytes: pointer to the data buffer
 832  * @perrno: pointer to return error code
 833  *
 834  * Dispatches command depending on what update state is current
 835  **/
 836 enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,
 837                                           struct i40e_nvm_access *cmd,
 838                                           u8 *bytes, int *perrno)
 839 {
 840         enum i40e_status_code status;
 841         enum i40e_nvmupd_cmd upd_cmd;
 842
 843         DEBUGFUNC("i40e_nvmupd_command");
 844
 845         /* assume success */
 846         *perrno = 0;
 847
 848         /* early check for status command and debug msgs */
 849         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 850
 851         i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n",
 852                    i40e_nvm_update_state_str[upd_cmd],
 853                    hw->nvmupd_state,
 854                    hw->nvm_release_on_done, hw->nvm_wait_opcode,
 855                    cmd->command, cmd->config, cmd->offset, cmd->data_size);
 856
 857         if (upd_cmd == I40E_NVMUPD_INVALID) {
 858                 *perrno = -EFAULT;
 859                 i40e_debug(hw, I40E_DEBUG_NVM,
 860                            "i40e_nvmupd_validate_command returns %d errno %d\n",
 861                            upd_cmd, *perrno);
 862         }
 863
 864         /* a status request returns immediately rather than
 865          * going into the state machine
 866          */
 867         if (upd_cmd == I40E_NVMUPD_STATUS) {
 868                 if (!cmd->data_size) {
 869                         *perrno = -EFAULT;
 870                         return I40E_ERR_BUF_TOO_SHORT;
 871                 }
 872
 873                 bytes[0] = hw->nvmupd_state;
 874
 875                 if (cmd->data_size >= 4) {
 876                         bytes[1] = 0;
 877                         *((u16 *)&bytes[2]) = hw->nvm_wait_opcode;
 878                 }
 879
 880                 /* Clear error status on read */
 881                 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR)
 882                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 883
 884                 return I40E_SUCCESS;
 885         }
 886
 887         /* Clear status even it is not read and log */
 888         if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
 889                 i40e_debug(hw, I40E_DEBUG_NVM,
 890                            "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
 891                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 892         }
 893
 894         /* Acquire lock to prevent race condition where adminq_task
 895          * can execute after i40e_nvmupd_nvm_read/write but before state
 896          * variables (nvm_wait_opcode, nvm_release_on_done) are updated.
 897          *
 898          * During NVMUpdate, it is observed that lock could be held for
 899          * ~5ms for most commands. However lock is held for ~60ms for
 900          * NVMUPD_CSUM_LCB command.
 901          */
 902         i40e_acquire_spinlock(&hw->aq.arq_spinlock);
 903         switch (hw->nvmupd_state) {
 904         case I40E_NVMUPD_STATE_INIT:
 905                 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
 906                 break;
 907
 908         case I40E_NVMUPD_STATE_READING:
 909                 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
 910                 break;
 911
 912         case I40E_NVMUPD_STATE_WRITING:
 913                 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
 914                 break;
 915
 916         case I40E_NVMUPD_STATE_INIT_WAIT:
 917         case I40E_NVMUPD_STATE_WRITE_WAIT:
 918                 /* if we need to stop waiting for an event, clear
 919                  * the wait info and return before doing anything else
 920                  */
 921                 if (cmd->offset == 0xffff) {
 922                         i40e_nvmupd_check_wait_event(hw, hw->nvm_wait_opcode);
 923                         status = I40E_SUCCESS;
 924                         goto exit;
 925                 }
 926
 927                 status = I40E_ERR_NOT_READY;
 928                 *perrno = -EBUSY;
 929                 break;
 930
 931         default:
 932                 /* invalid state, should never happen */
 933                 i40e_debug(hw, I40E_DEBUG_NVM,
 934                            "NVMUPD: no such state %d\n", hw->nvmupd_state);
 935                 status = I40E_NOT_SUPPORTED;
 936                 *perrno = -ESRCH;
 937                 break;
 938         }
 939 exit:
 940         i40e_release_spinlock(&hw->aq.arq_spinlock);
 941         return status;
 942 }
 943
 944 /**
 945  * i40e_nvmupd_state_init - Handle NVM update state Init
 946  * @hw: pointer to hardware structure
 947  * @cmd: pointer to nvm update command buffer
 948  * @bytes: pointer to the data buffer
 949  * @perrno: pointer to return error code
 950  *
 951  * Process legitimate commands of the Init state and conditionally set next
 952  * state. Reject all other commands.
 953  **/
 954 STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
 955                                                     struct i40e_nvm_access *cmd,
 956                                                     u8 *bytes, int *perrno)
 957 {
 958         enum i40e_status_code status = I40E_SUCCESS;
 959         enum i40e_nvmupd_cmd upd_cmd;
 960
 961         DEBUGFUNC("i40e_nvmupd_state_init");
 962
 963         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 964
 965         switch (upd_cmd) {
 966         case I40E_NVMUPD_READ_SA:
 967                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 968                 if (status) {
 969                         *perrno = i40e_aq_rc_to_posix(status,
 970                                                      hw->aq.asq_last_status);
 971                 } else {
 972                         status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 973                         i40e_release_nvm(hw);
 974                 }
 975                 break;
 976
 977         case I40E_NVMUPD_READ_SNT:
 978                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 979                 if (status) {
 980                         *perrno = i40e_aq_rc_to_posix(status,
 981                                                      hw->aq.asq_last_status);
 982                 } else {
 983                         status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 984                         if (status)
 985                                 i40e_release_nvm(hw);
 986                         else
 987                                 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
 988                 }
 989                 break;
 990
 991         case I40E_NVMUPD_WRITE_ERA:
 992                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 993                 if (status) {
 994                         *perrno = i40e_aq_rc_to_posix(status,
 995                                                      hw->aq.asq_last_status);
 996                 } else {
 997                         status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
 998                         if (status) {
 999                                 i40e_release_nvm(hw);
1000                         } else {
1001                                 hw->nvm_release_on_done = true;
1002                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase;
1003                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1004                         }
1005                 }
1006                 break;
1007
1008         case I40E_NVMUPD_WRITE_SA:
1009                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1010                 if (status) {
1011                         *perrno = i40e_aq_rc_to_posix(status,
1012                                                      hw->aq.asq_last_status);
1013                 } else {
1014                         status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1015                         if (status) {
1016                                 i40e_release_nvm(hw);
1017                         } else {
1018                                 hw->nvm_release_on_done = true;
1019                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1020                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1021                         }
1022                 }
1023                 break;
1024
1025         case I40E_NVMUPD_WRITE_SNT:
1026                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1027                 if (status) {
1028                         *perrno = i40e_aq_rc_to_posix(status,
1029                                                      hw->aq.asq_last_status);
1030                 } else {
1031                         status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1032                         if (status) {
1033                                 i40e_release_nvm(hw);
1034                         } else {
1035                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1036                                 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1037                         }
1038                 }
1039                 break;
1040
1041         case I40E_NVMUPD_CSUM_SA:
1042                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1043                 if (status) {
1044                         *perrno = i40e_aq_rc_to_posix(status,
1045                                                      hw->aq.asq_last_status);
1046                 } else {
1047                         status = i40e_update_nvm_checksum(hw);
1048                         if (status) {
1049                                 *perrno = hw->aq.asq_last_status ?
1050                                    i40e_aq_rc_to_posix(status,
1051                                                        hw->aq.asq_last_status) :
1052                                    -EIO;
1053                                 i40e_release_nvm(hw);
1054                         } else {
1055                                 hw->nvm_release_on_done = true;
1056                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1057                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1058                         }
1059                 }
1060                 break;
1061
1062         case I40E_NVMUPD_EXEC_AQ:
1063                 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
1064                 break;
1065
1066         case I40E_NVMUPD_GET_AQ_RESULT:
1067                 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
1068                 break;
1069
1070         default:
1071                 i40e_debug(hw, I40E_DEBUG_NVM,
1072                            "NVMUPD: bad cmd %s in init state\n",
1073                            i40e_nvm_update_state_str[upd_cmd]);
1074                 status = I40E_ERR_NVM;
1075                 *perrno = -ESRCH;
1076                 break;
1077         }
1078         return status;
1079 }
1080
1081 /**
1082  * i40e_nvmupd_state_reading - Handle NVM update state Reading
1083  * @hw: pointer to hardware structure
1084  * @cmd: pointer to nvm update command buffer
1085  * @bytes: pointer to the data buffer
1086  * @perrno: pointer to return error code
1087  *
1088  * NVM ownership is already held.  Process legitimate commands and set any
1089  * change in state; reject all other commands.
1090  **/
1091 STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
1092                                                     struct i40e_nvm_access *cmd,
1093                                                     u8 *bytes, int *perrno)
1094 {
1095         enum i40e_status_code status = I40E_SUCCESS;
1096         enum i40e_nvmupd_cmd upd_cmd;
1097
1098         DEBUGFUNC("i40e_nvmupd_state_reading");
1099
1100         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
1101
1102         switch (upd_cmd) {
1103         case I40E_NVMUPD_READ_SA:
1104         case I40E_NVMUPD_READ_CON:
1105                 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
1106                 break;
1107
1108         case I40E_NVMUPD_READ_LCB:
1109                 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
1110                 i40e_release_nvm(hw);
1111                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1112                 break;
1113
1114         default:
1115                 i40e_debug(hw, I40E_DEBUG_NVM,
1116                            "NVMUPD: bad cmd %s in reading state.\n",
1117                            i40e_nvm_update_state_str[upd_cmd]);
1118                 status = I40E_NOT_SUPPORTED;
1119                 *perrno = -ESRCH;
1120                 break;
1121         }
1122         return status;
1123 }
1124
1125 /**
1126  * i40e_nvmupd_state_writing - Handle NVM update state Writing
1127  * @hw: pointer to hardware structure
1128  * @cmd: pointer to nvm update command buffer
1129  * @bytes: pointer to the data buffer
1130  * @perrno: pointer to return error code
1131  *
1132  * NVM ownership is already held.  Process legitimate commands and set any
1133  * change in state; reject all other commands
1134  **/
1135 STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
1136                                                     struct i40e_nvm_access *cmd,
1137                                                     u8 *bytes, int *perrno)
1138 {
1139         enum i40e_status_code status = I40E_SUCCESS;
1140         enum i40e_nvmupd_cmd upd_cmd;
1141         bool retry_attempt = false;
1142
1143         DEBUGFUNC("i40e_nvmupd_state_writing");
1144
1145         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
1146
1147 retry:
1148         switch (upd_cmd) {
1149         case I40E_NVMUPD_WRITE_CON:
1150                 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1151                 if (!status) {
1152                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1153                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1154                 }
1155                 break;
1156
1157         case I40E_NVMUPD_WRITE_LCB:
1158                 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1159                 if (status) {
1160                         *perrno = hw->aq.asq_last_status ?
1161                                    i40e_aq_rc_to_posix(status,
1162                                                        hw->aq.asq_last_status) :
1163                                    -EIO;
1164                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1165                 } else {
1166                         hw->nvm_release_on_done = true;
1167                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1168                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1169                 }
1170                 break;
1171
1172         case I40E_NVMUPD_CSUM_CON:
1173                 /* Assumes the caller has acquired the nvm */
1174                 status = i40e_update_nvm_checksum(hw);
1175                 if (status) {
1176                         *perrno = hw->aq.asq_last_status ?
1177                                    i40e_aq_rc_to_posix(status,
1178                                                        hw->aq.asq_last_status) :
1179                                    -EIO;
1180                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1181                 } else {
1182                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1183                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1184                 }
1185                 break;
1186
1187         case I40E_NVMUPD_CSUM_LCB:
1188                 /* Assumes the caller has acquired the nvm */
1189                 status = i40e_update_nvm_checksum(hw);
1190                 if (status) {
1191                         *perrno = hw->aq.asq_last_status ?
1192                                    i40e_aq_rc_to_posix(status,
1193                                                        hw->aq.asq_last_status) :
1194                                    -EIO;
1195                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1196                 } else {
1197                         hw->nvm_release_on_done = true;
1198                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1199                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1200                 }
1201                 break;
1202
1203         default:
1204                 i40e_debug(hw, I40E_DEBUG_NVM,
1205                            "NVMUPD: bad cmd %s in writing state.\n",
1206                            i40e_nvm_update_state_str[upd_cmd]);
1207                 status = I40E_NOT_SUPPORTED;
1208                 *perrno = -ESRCH;
1209                 break;
1210         }
1211
1212         /* In some circumstances, a multi-write transaction takes longer
1213          * than the default 3 minute timeout on the write semaphore.  If
1214          * the write failed with an EBUSY status, this is likely the problem,
1215          * so here we try to reacquire the semaphore then retry the write.
1216          * We only do one retry, then give up.
1217          */
1218         if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1219             !retry_attempt) {
1220                 enum i40e_status_code old_status = status;
1221                 u32 old_asq_status = hw->aq.asq_last_status;
1222                 u32 gtime;
1223
1224                 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1225                 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1226                         i40e_debug(hw, I40E_DEBUG_ALL,
1227                                    "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1228                                    gtime, hw->nvm.hw_semaphore_timeout);
1229                         i40e_release_nvm(hw);
1230                         status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1231                         if (status) {
1232                                 i40e_debug(hw, I40E_DEBUG_ALL,
1233                                            "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1234                                            hw->aq.asq_last_status);
1235                                 status = old_status;
1236                                 hw->aq.asq_last_status = old_asq_status;
1237                         } else {
1238                                 retry_attempt = true;
1239                                 goto retry;
1240                         }
1241                 }
1242         }
1243
1244         return status;
1245 }
1246
1247 /**
1248  * i40e_nvmupd_check_wait_event - handle NVM update operation events
1249  * @hw: pointer to the hardware structure
1250  * @opcode: the event that just happened
1251  **/
1252 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode)
1253 {
1254         if (opcode == hw->nvm_wait_opcode) {
1255
1256                 i40e_debug(hw, I40E_DEBUG_NVM,
1257                            "NVMUPD: clearing wait on opcode 0x%04x\n", opcode);
1258                 if (hw->nvm_release_on_done) {
1259                         i40e_release_nvm(hw);
1260                         hw->nvm_release_on_done = false;
1261                 }
1262                 hw->nvm_wait_opcode = 0;
1263
1264                 if (hw->aq.arq_last_status) {
1265                         hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR;
1266                         return;
1267                 }
1268
1269                 switch (hw->nvmupd_state) {
1270                 case I40E_NVMUPD_STATE_INIT_WAIT:
1271                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1272                         break;
1273
1274                 case I40E_NVMUPD_STATE_WRITE_WAIT:
1275                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1276                         break;
1277
1278                 default:
1279                         break;
1280                 }
1281         }
1282 }
1283
1284 /**
1285  * i40e_nvmupd_validate_command - Validate given command
1286  * @hw: pointer to hardware structure
1287  * @cmd: pointer to nvm update command buffer
1288  * @perrno: pointer to return error code
1289  *
1290  * Return one of the valid command types or I40E_NVMUPD_INVALID
1291  **/
1292 STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1293                                                     struct i40e_nvm_access *cmd,
1294                                                     int *perrno)
1295 {
1296         enum i40e_nvmupd_cmd upd_cmd;
1297         u8 module, transaction;
1298
1299         DEBUGFUNC("i40e_nvmupd_validate_command\n");
1300
1301         /* anything that doesn't match a recognized case is an error */
1302         upd_cmd = I40E_NVMUPD_INVALID;
1303
1304         transaction = i40e_nvmupd_get_transaction(cmd->config);
1305         module = i40e_nvmupd_get_module(cmd->config);
1306
1307         /* limits on data size */
1308         if ((cmd->data_size < 1) ||
1309             (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1310                 i40e_debug(hw, I40E_DEBUG_NVM,
1311                            "i40e_nvmupd_validate_command data_size %d\n",
1312                            cmd->data_size);
1313                 *perrno = -EFAULT;
1314                 return I40E_NVMUPD_INVALID;
1315         }
1316
1317         switch (cmd->command) {
1318         case I40E_NVM_READ:
1319                 switch (transaction) {
1320                 case I40E_NVM_CON:
1321                         upd_cmd = I40E_NVMUPD_READ_CON;
1322                         break;
1323                 case I40E_NVM_SNT:
1324                         upd_cmd = I40E_NVMUPD_READ_SNT;
1325                         break;
1326                 case I40E_NVM_LCB:
1327                         upd_cmd = I40E_NVMUPD_READ_LCB;
1328                         break;
1329                 case I40E_NVM_SA:
1330                         upd_cmd = I40E_NVMUPD_READ_SA;
1331                         break;
1332                 case I40E_NVM_EXEC:
1333                         if (module == 0xf)
1334                                 upd_cmd = I40E_NVMUPD_STATUS;
1335                         else if (module == 0)
1336                                 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1337                         break;
1338                 }
1339                 break;
1340
1341         case I40E_NVM_WRITE:
1342                 switch (transaction) {
1343                 case I40E_NVM_CON:
1344                         upd_cmd = I40E_NVMUPD_WRITE_CON;
1345                         break;
1346                 case I40E_NVM_SNT:
1347                         upd_cmd = I40E_NVMUPD_WRITE_SNT;
1348                         break;
1349                 case I40E_NVM_LCB:
1350                         upd_cmd = I40E_NVMUPD_WRITE_LCB;
1351                         break;
1352                 case I40E_NVM_SA:
1353                         upd_cmd = I40E_NVMUPD_WRITE_SA;
1354                         break;
1355                 case I40E_NVM_ERA:
1356                         upd_cmd = I40E_NVMUPD_WRITE_ERA;
1357                         break;
1358                 case I40E_NVM_CSUM:
1359                         upd_cmd = I40E_NVMUPD_CSUM_CON;
1360                         break;
1361                 case (I40E_NVM_CSUM|I40E_NVM_SA):
1362                         upd_cmd = I40E_NVMUPD_CSUM_SA;
1363                         break;
1364                 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1365                         upd_cmd = I40E_NVMUPD_CSUM_LCB;
1366                         break;
1367                 case I40E_NVM_EXEC:
1368                         if (module == 0)
1369                                 upd_cmd = I40E_NVMUPD_EXEC_AQ;
1370                         break;
1371                 }
1372                 break;
1373         }
1374
1375         return upd_cmd;
1376 }
1377
1378 /**
1379  * i40e_nvmupd_exec_aq - Run an AQ command
1380  * @hw: pointer to hardware structure
1381  * @cmd: pointer to nvm update command buffer
1382  * @bytes: pointer to the data buffer
1383  * @perrno: pointer to return error code
1384  *
1385  * cmd structure contains identifiers and data buffer
1386  **/
1387 STATIC enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1388                                                  struct i40e_nvm_access *cmd,
1389                                                  u8 *bytes, int *perrno)
1390 {
1391         struct i40e_asq_cmd_details cmd_details;
1392         enum i40e_status_code status;
1393         struct i40e_aq_desc *aq_desc;
1394         u32 buff_size = 0;
1395         u8 *buff = NULL;
1396         u32 aq_desc_len;
1397         u32 aq_data_len;
1398
1399         i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1400         memset(&cmd_details, 0, sizeof(cmd_details));
1401         cmd_details.wb_desc = &hw->nvm_wb_desc;
1402
1403         aq_desc_len = sizeof(struct i40e_aq_desc);
1404         memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1405
1406         /* get the aq descriptor */
1407         if (cmd->data_size < aq_desc_len) {
1408                 i40e_debug(hw, I40E_DEBUG_NVM,
1409                            "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1410                            cmd->data_size, aq_desc_len);
1411                 *perrno = -EINVAL;
1412                 return I40E_ERR_PARAM;
1413         }
1414         aq_desc = (struct i40e_aq_desc *)bytes;
1415
1416         /* if data buffer needed, make sure it's ready */
1417         aq_data_len = cmd->data_size - aq_desc_len;
1418         buff_size = max(aq_data_len, (u32)LE16_TO_CPU(aq_desc->datalen));
1419         if (buff_size) {
1420                 if (!hw->nvm_buff.va) {
1421                         status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1422                                                         hw->aq.asq_buf_size);
1423                         if (status)
1424                                 i40e_debug(hw, I40E_DEBUG_NVM,
1425                                            "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1426                                            status);
1427                 }
1428
1429                 if (hw->nvm_buff.va) {
1430                         buff = hw->nvm_buff.va;
1431                         i40e_memcpy(buff, &bytes[aq_desc_len], aq_data_len,
1432                                 I40E_NONDMA_TO_NONDMA);
1433                 }
1434         }
1435
1436         /* and away we go! */
1437         status = i40e_asq_send_command(hw, aq_desc, buff,
1438                                        buff_size, &cmd_details);
1439         if (status) {
1440                 i40e_debug(hw, I40E_DEBUG_NVM,
1441                            "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1442                            i40e_stat_str(hw, status),
1443                            i40e_aq_str(hw, hw->aq.asq_last_status));
1444                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1445         }
1446
1447         /* should we wait for a followup event? */
1448         if (cmd->offset) {
1449                 hw->nvm_wait_opcode = cmd->offset;
1450                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1451         }
1452
1453         return status;
1454 }
1455
1456 /**
1457  * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1458  * @hw: pointer to hardware structure
1459  * @cmd: pointer to nvm update command buffer
1460  * @bytes: pointer to the data buffer
1461  * @perrno: pointer to return error code
1462  *
1463  * cmd structure contains identifiers and data buffer
1464  **/
1465 STATIC enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1466                                                     struct i40e_nvm_access *cmd,
1467                                                     u8 *bytes, int *perrno)
1468 {
1469         u32 aq_total_len;
1470         u32 aq_desc_len;
1471         int remainder;
1472         u8 *buff;
1473
1474         i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1475
1476         aq_desc_len = sizeof(struct i40e_aq_desc);
1477         aq_total_len = aq_desc_len + LE16_TO_CPU(hw->nvm_wb_desc.datalen);
1478
1479         /* check offset range */
1480         if (cmd->offset > aq_total_len) {
1481                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1482                            __func__, cmd->offset, aq_total_len);
1483                 *perrno = -EINVAL;
1484                 return I40E_ERR_PARAM;
1485         }
1486
1487         /* check copylength range */
1488         if (cmd->data_size > (aq_total_len - cmd->offset)) {
1489                 int new_len = aq_total_len - cmd->offset;
1490
1491                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1492                            __func__, cmd->data_size, new_len);
1493                 cmd->data_size = new_len;
1494         }
1495
1496         remainder = cmd->data_size;
1497         if (cmd->offset < aq_desc_len) {
1498                 u32 len = aq_desc_len - cmd->offset;
1499
1500                 len = min(len, cmd->data_size);
1501                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1502                            __func__, cmd->offset, cmd->offset + len);
1503
1504                 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1505                 i40e_memcpy(bytes, buff, len, I40E_NONDMA_TO_NONDMA);
1506
1507                 bytes += len;
1508                 remainder -= len;
1509                 buff = hw->nvm_buff.va;
1510         } else {
1511                 buff = (u8 *)hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1512         }
1513
1514         if (remainder > 0) {
1515                 int start_byte = buff - (u8 *)hw->nvm_buff.va;
1516
1517                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1518                            __func__, start_byte, start_byte + remainder);
1519                 i40e_memcpy(bytes, buff, remainder, I40E_NONDMA_TO_NONDMA);
1520         }
1521
1522         return I40E_SUCCESS;
1523 }
1524
1525 /**
1526  * i40e_nvmupd_nvm_read - Read NVM
1527  * @hw: pointer to hardware structure
1528  * @cmd: pointer to nvm update command buffer
1529  * @bytes: pointer to the data buffer
1530  * @perrno: pointer to return error code
1531  *
1532  * cmd structure contains identifiers and data buffer
1533  **/
1534 STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1535                                                   struct i40e_nvm_access *cmd,
1536                                                   u8 *bytes, int *perrno)
1537 {
1538         struct i40e_asq_cmd_details cmd_details;
1539         enum i40e_status_code status;
1540         u8 module, transaction;
1541         bool last;
1542
1543         transaction = i40e_nvmupd_get_transaction(cmd->config);
1544         module = i40e_nvmupd_get_module(cmd->config);
1545         last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1546
1547         memset(&cmd_details, 0, sizeof(cmd_details));
1548         cmd_details.wb_desc = &hw->nvm_wb_desc;
1549
1550         status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1551                                   bytes, last, &cmd_details);
1552         if (status) {
1553                 i40e_debug(hw, I40E_DEBUG_NVM,
1554                            "i40e_nvmupd_nvm_read mod 0x%x  off 0x%x  len 0x%x\n",
1555                            module, cmd->offset, cmd->data_size);
1556                 i40e_debug(hw, I40E_DEBUG_NVM,
1557                            "i40e_nvmupd_nvm_read status %d aq %d\n",
1558                            status, hw->aq.asq_last_status);
1559                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1560         }
1561
1562         return status;
1563 }
1564
1565 /**
1566  * i40e_nvmupd_nvm_erase - Erase an NVM module
1567  * @hw: pointer to hardware structure
1568  * @cmd: pointer to nvm update command buffer
1569  * @perrno: pointer to return error code
1570  *
1571  * module, offset, data_size and data are in cmd structure
1572  **/
1573 STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1574                                                    struct i40e_nvm_access *cmd,
1575                                                    int *perrno)
1576 {
1577         enum i40e_status_code status = I40E_SUCCESS;
1578         struct i40e_asq_cmd_details cmd_details;
1579         u8 module, transaction;
1580         bool last;
1581
1582         transaction = i40e_nvmupd_get_transaction(cmd->config);
1583         module = i40e_nvmupd_get_module(cmd->config);
1584         last = (transaction & I40E_NVM_LCB);
1585
1586         memset(&cmd_details, 0, sizeof(cmd_details));
1587         cmd_details.wb_desc = &hw->nvm_wb_desc;
1588
1589         status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1590                                    last, &cmd_details);
1591         if (status) {
1592                 i40e_debug(hw, I40E_DEBUG_NVM,
1593                            "i40e_nvmupd_nvm_erase mod 0x%x  off 0x%x len 0x%x\n",
1594                            module, cmd->offset, cmd->data_size);
1595                 i40e_debug(hw, I40E_DEBUG_NVM,
1596                            "i40e_nvmupd_nvm_erase status %d aq %d\n",
1597                            status, hw->aq.asq_last_status);
1598                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1599         }
1600
1601         return status;
1602 }
1603
1604 /**
1605  * i40e_nvmupd_nvm_write - Write NVM
1606  * @hw: pointer to hardware structure
1607  * @cmd: pointer to nvm update command buffer
1608  * @bytes: pointer to the data buffer
1609  * @perrno: pointer to return error code
1610  *
1611  * module, offset, data_size and data are in cmd structure
1612  **/
1613 STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1614                                                    struct i40e_nvm_access *cmd,
1615                                                    u8 *bytes, int *perrno)
1616 {
1617         enum i40e_status_code status = I40E_SUCCESS;
1618         struct i40e_asq_cmd_details cmd_details;
1619         u8 module, transaction;
1620         u8 preservation_flags;
1621         bool last;
1622
1623         transaction = i40e_nvmupd_get_transaction(cmd->config);
1624         module = i40e_nvmupd_get_module(cmd->config);
1625         last = (transaction & I40E_NVM_LCB);
1626         preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config);
1627
1628         memset(&cmd_details, 0, sizeof(cmd_details));
1629         cmd_details.wb_desc = &hw->nvm_wb_desc;
1630
1631         status = i40e_aq_update_nvm(hw, module, cmd->offset,
1632                                     (u16)cmd->data_size, bytes, last,
1633                                     preservation_flags, &cmd_details);
1634         if (status) {
1635                 i40e_debug(hw, I40E_DEBUG_NVM,
1636                            "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1637                            module, cmd->offset, cmd->data_size);
1638                 i40e_debug(hw, I40E_DEBUG_NVM,
1639                            "i40e_nvmupd_nvm_write status %d aq %d\n",
1640                            status, hw->aq.asq_last_status);
1641                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1642         }
1643
1644         return status;
1645 }