drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef I40E_MASK
  53 /* I40E_MASK is a macro used on 32 bit registers */
  54 #define I40E_MASK(mask, shift) (mask << shift)
  55 #endif
  56
  57 #define I40E_MAX_PF                     16
  58 #define I40E_MAX_PF_VSI                 64
  59 #define I40E_MAX_PF_QP                  128
  60 #define I40E_MAX_VSI_QP                 16
  61 #define I40E_MAX_VF_VSI                 3
  62 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  63 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  64
  65 /* something less than 1 minute */
  66 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  67
  68 /* Max default timeout in ms, */
  69 #define I40E_MAX_NVM_TIMEOUT            18000
  70
  71 /* Check whether address is multicast. */
  72 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  73
  74 /* Check whether an address is broadcast. */
  75 #define I40E_IS_BROADCAST(address)      \
  76         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  77         (((u8 *)(address))[1] == ((u8)0xff)))
  78
  79 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  80 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  81
  82 /* forward declaration */
  83 struct i40e_hw;
  84 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  85
  86 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  87 /* Data type manipulation macros. */
  88 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  89 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  90
  91 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  92 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  93
  94 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  95 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
  96
  97 /* Number of Transmit Descriptors must be a multiple of 8. */
  98 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
  99 /* Number of Receive Descriptors must be a multiple of 32 if
 100  * the number of descriptors is greater than 32.
 101  */
 102 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 103
 104 #define I40E_DESC_UNUSED(R)     \
 105         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 106         (R)->next_to_clean - (R)->next_to_use - 1)
 107
 108 /* bitfields for Tx queue mapping in QTX_CTL */
 109 #define I40E_QTX_CTL_VF_QUEUE   0x0
 110 #define I40E_QTX_CTL_VM_QUEUE   0x1
 111 #define I40E_QTX_CTL_PF_QUEUE   0x2
 112
 113 /* debug masks - set these bits in hw->debug_mask to control output */
 114 enum i40e_debug_mask {
 115         I40E_DEBUG_INIT                 = 0x00000001,
 116         I40E_DEBUG_RELEASE              = 0x00000002,
 117
 118         I40E_DEBUG_LINK                 = 0x00000010,
 119         I40E_DEBUG_PHY                  = 0x00000020,
 120         I40E_DEBUG_HMC                  = 0x00000040,
 121         I40E_DEBUG_NVM                  = 0x00000080,
 122         I40E_DEBUG_LAN                  = 0x00000100,
 123         I40E_DEBUG_FLOW                 = 0x00000200,
 124         I40E_DEBUG_DCB                  = 0x00000400,
 125         I40E_DEBUG_DIAG                 = 0x00000800,
 126         I40E_DEBUG_FD                   = 0x00001000,
 127
 128         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 129         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 130         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 131         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 132         I40E_DEBUG_AQ                   = 0x0F000000,
 133
 134         I40E_DEBUG_USER                 = 0xF0000000,
 135
 136         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 137 };
 138
 139 /* PCI Bus Info */
 140 #define I40E_PCI_LINK_STATUS            0xB2
 141 #define I40E_PCI_LINK_WIDTH             0x3F0
 142 #define I40E_PCI_LINK_WIDTH_1           0x10
 143 #define I40E_PCI_LINK_WIDTH_2           0x20
 144 #define I40E_PCI_LINK_WIDTH_4           0x40
 145 #define I40E_PCI_LINK_WIDTH_8           0x80
 146 #define I40E_PCI_LINK_SPEED             0xF
 147 #define I40E_PCI_LINK_SPEED_2500        0x1
 148 #define I40E_PCI_LINK_SPEED_5000        0x2
 149 #define I40E_PCI_LINK_SPEED_8000        0x3
 150
 151 /* Memory types */
 152 enum i40e_memset_type {
 153         I40E_NONDMA_MEM = 0,
 154         I40E_DMA_MEM
 155 };
 156
 157 /* Memcpy types */
 158 enum i40e_memcpy_type {
 159         I40E_NONDMA_TO_NONDMA = 0,
 160         I40E_NONDMA_TO_DMA,
 161         I40E_DMA_TO_DMA,
 162         I40E_DMA_TO_NONDMA
 163 };
 164
 165 /* These are structs for managing the hardware information and the operations.
 166  * The structures of function pointers are filled out at init time when we
 167  * know for sure exactly which hardware we're working with.  This gives us the
 168  * flexibility of using the same main driver code but adapting to slightly
 169  * different hardware needs as new parts are developed.  For this architecture,
 170  * the Firmware and AdminQ are intended to insulate the driver from most of the
 171  * future changes, but these structures will also do part of the job.
 172  */
 173 enum i40e_mac_type {
 174         I40E_MAC_UNKNOWN = 0,
 175         I40E_MAC_X710,
 176         I40E_MAC_XL710,
 177         I40E_MAC_VF,
 178         I40E_MAC_GENERIC,
 179 };
 180
 181 enum i40e_media_type {
 182         I40E_MEDIA_TYPE_UNKNOWN = 0,
 183         I40E_MEDIA_TYPE_FIBER,
 184         I40E_MEDIA_TYPE_BASET,
 185         I40E_MEDIA_TYPE_BACKPLANE,
 186         I40E_MEDIA_TYPE_CX4,
 187         I40E_MEDIA_TYPE_DA,
 188         I40E_MEDIA_TYPE_VIRTUAL
 189 };
 190
 191 enum i40e_fc_mode {
 192         I40E_FC_NONE = 0,
 193         I40E_FC_RX_PAUSE,
 194         I40E_FC_TX_PAUSE,
 195         I40E_FC_FULL,
 196         I40E_FC_PFC,
 197         I40E_FC_DEFAULT
 198 };
 199
 200 enum i40e_set_fc_aq_failures {
 201         I40E_SET_FC_AQ_FAIL_NONE = 0,
 202         I40E_SET_FC_AQ_FAIL_GET = 1,
 203         I40E_SET_FC_AQ_FAIL_SET = 2,
 204         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 205         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 206 };
 207
 208 enum i40e_vsi_type {
 209         I40E_VSI_MAIN = 0,
 210         I40E_VSI_VMDQ1,
 211         I40E_VSI_VMDQ2,
 212         I40E_VSI_CTRL,
 213         I40E_VSI_FCOE,
 214         I40E_VSI_MIRROR,
 215         I40E_VSI_SRIOV,
 216         I40E_VSI_FDIR,
 217         I40E_VSI_TYPE_UNKNOWN
 218 };
 219
 220 enum i40e_queue_type {
 221         I40E_QUEUE_TYPE_RX = 0,
 222         I40E_QUEUE_TYPE_TX,
 223         I40E_QUEUE_TYPE_PE_CEQ,
 224         I40E_QUEUE_TYPE_UNKNOWN
 225 };
 226
 227 struct i40e_link_status {
 228         enum i40e_aq_phy_type phy_type;
 229         enum i40e_aq_link_speed link_speed;
 230         u8 link_info;
 231         u8 an_info;
 232         u8 ext_info;
 233         u8 loopback;
 234         /* is Link Status Event notification to SW enabled */
 235         bool lse_enable;
 236         u16 max_frame_size;
 237         bool crc_enable;
 238         u8 pacing;
 239         u8 requested_speeds;
 240         u8 module_type[3];
 241         /* 1st byte: module identifier */
 242 #define I40E_MODULE_TYPE_SFP            0x03
 243 #define I40E_MODULE_TYPE_QSFP           0x0D
 244         /* 2nd byte: ethernet compliance codes for 10/40G */
 245 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 246 #define I40E_MODULE_TYPE_40G_LR4        0x02
 247 #define I40E_MODULE_TYPE_40G_SR4        0x04
 248 #define I40E_MODULE_TYPE_40G_CR4        0x08
 249 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 250 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 251 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 252 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 253         /* 3rd byte: ethernet compliance codes for 1G */
 254 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 255 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 256 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 257 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 258 };
 259
 260 struct i40e_phy_info {
 261         struct i40e_link_status link_info;
 262         struct i40e_link_status link_info_old;
 263         u32 autoneg_advertised;
 264         u32 phy_id;
 265         u32 module_type;
 266         bool get_link_info;
 267         enum i40e_media_type media_type;
 268 };
 269
 270 #define I40E_HW_CAP_MAX_GPIO                    30
 271 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 272 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 273
 274 /* Capabilities of a PF or a VF or the whole device */
 275 struct i40e_hw_capabilities {
 276         u32  switch_mode;
 277 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 278 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 279 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 280
 281         u32  management_mode;
 282         u32  npar_enable;
 283         u32  os2bmc;
 284         u32  valid_functions;
 285         bool sr_iov_1_1;
 286         bool vmdq;
 287         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 288         bool evb_802_1_qbh; /* Bridge Port Extension */
 289         bool dcb;
 290         bool fcoe;
 291         bool iscsi; /* Indicates iSCSI enabled */
 292         bool mfp_mode_1;
 293         bool mgmt_cem;
 294         bool ieee_1588;
 295         bool iwarp;
 296         bool fd;
 297         u32 fd_filters_guaranteed;
 298         u32 fd_filters_best_effort;
 299         bool rss;
 300         u32 rss_table_size;
 301         u32 rss_table_entry_width;
 302         bool led[I40E_HW_CAP_MAX_GPIO];
 303         bool sdp[I40E_HW_CAP_MAX_GPIO];
 304         u32 nvm_image_type;
 305         u32 num_flow_director_filters;
 306         u32 num_vfs;
 307         u32 vf_base_id;
 308         u32 num_vsis;
 309         u32 num_rx_qp;
 310         u32 num_tx_qp;
 311         u32 base_queue;
 312         u32 num_msix_vectors;
 313         u32 num_msix_vectors_vf;
 314         u32 led_pin_num;
 315         u32 sdp_pin_num;
 316         u32 mdio_port_num;
 317         u32 mdio_port_mode;
 318         u8 rx_buf_chain_len;
 319         u32 enabled_tcmap;
 320         u32 maxtc;
 321 };
 322
 323 struct i40e_mac_info {
 324         enum i40e_mac_type type;
 325         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 326         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 327         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 328         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 329         u16 max_fcoeq;
 330 };
 331
 332 enum i40e_aq_resources_ids {
 333         I40E_NVM_RESOURCE_ID = 1
 334 };
 335
 336 enum i40e_aq_resource_access_type {
 337         I40E_RESOURCE_READ = 1,
 338         I40E_RESOURCE_WRITE
 339 };
 340
 341 struct i40e_nvm_info {
 342         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 343         u32 timeout;              /* [ms] */
 344         u16 sr_size;              /* Shadow RAM size in words */
 345         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 346         u16 version;              /* NVM package version */
 347         u32 eetrack;              /* NVM data version */
 348 };
 349
 350 /* definitions used in NVM update support */
 351
 352 enum i40e_nvmupd_cmd {
 353         I40E_NVMUPD_INVALID,
 354         I40E_NVMUPD_READ_CON,
 355         I40E_NVMUPD_READ_SNT,
 356         I40E_NVMUPD_READ_LCB,
 357         I40E_NVMUPD_READ_SA,
 358         I40E_NVMUPD_WRITE_ERA,
 359         I40E_NVMUPD_WRITE_CON,
 360         I40E_NVMUPD_WRITE_SNT,
 361         I40E_NVMUPD_WRITE_LCB,
 362         I40E_NVMUPD_WRITE_SA,
 363         I40E_NVMUPD_CSUM_CON,
 364         I40E_NVMUPD_CSUM_SA,
 365         I40E_NVMUPD_CSUM_LCB,
 366         I40E_NVMUPD_STATUS,
 367         I40E_NVMUPD_EXEC_AQ,
 368         I40E_NVMUPD_GET_AQ_RESULT,
 369 };
 370
 371 enum i40e_nvmupd_state {
 372         I40E_NVMUPD_STATE_INIT,
 373         I40E_NVMUPD_STATE_READING,
 374         I40E_NVMUPD_STATE_WRITING,
 375         I40E_NVMUPD_STATE_INIT_WAIT,
 376         I40E_NVMUPD_STATE_WRITE_WAIT,
 377 };
 378
 379 /* nvm_access definition and its masks/shifts need to be accessible to
 380  * application, core driver, and shared code.  Where is the right file?
 381  */
 382 #define I40E_NVM_READ   0xB
 383 #define I40E_NVM_WRITE  0xC
 384
 385 #define I40E_NVM_MOD_PNT_MASK 0xFF
 386
 387 #define I40E_NVM_TRANS_SHIFT    8
 388 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 389 #define I40E_NVM_CON            0x0
 390 #define I40E_NVM_SNT            0x1
 391 #define I40E_NVM_LCB            0x2
 392 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 393 #define I40E_NVM_ERA            0x4
 394 #define I40E_NVM_CSUM           0x8
 395 #define I40E_NVM_EXEC           0xf
 396
 397 #define I40E_NVM_ADAPT_SHIFT    16
 398 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 399
 400 #define I40E_NVMUPD_MAX_DATA    4096
 401 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 402
 403 struct i40e_nvm_access {
 404         u32 command;
 405         u32 config;
 406         u32 offset;     /* in bytes */
 407         u32 data_size;  /* in bytes */
 408         u8 data[1];
 409 };
 410
 411 /* PCI bus types */
 412 enum i40e_bus_type {
 413         i40e_bus_type_unknown = 0,
 414         i40e_bus_type_pci,
 415         i40e_bus_type_pcix,
 416         i40e_bus_type_pci_express,
 417         i40e_bus_type_reserved
 418 };
 419
 420 /* PCI bus speeds */
 421 enum i40e_bus_speed {
 422         i40e_bus_speed_unknown  = 0,
 423         i40e_bus_speed_33       = 33,
 424         i40e_bus_speed_66       = 66,
 425         i40e_bus_speed_100      = 100,
 426         i40e_bus_speed_120      = 120,
 427         i40e_bus_speed_133      = 133,
 428         i40e_bus_speed_2500     = 2500,
 429         i40e_bus_speed_5000     = 5000,
 430         i40e_bus_speed_8000     = 8000,
 431         i40e_bus_speed_reserved
 432 };
 433
 434 /* PCI bus widths */
 435 enum i40e_bus_width {
 436         i40e_bus_width_unknown  = 0,
 437         i40e_bus_width_pcie_x1  = 1,
 438         i40e_bus_width_pcie_x2  = 2,
 439         i40e_bus_width_pcie_x4  = 4,
 440         i40e_bus_width_pcie_x8  = 8,
 441         i40e_bus_width_32       = 32,
 442         i40e_bus_width_64       = 64,
 443         i40e_bus_width_reserved
 444 };
 445
 446 /* Bus parameters */
 447 struct i40e_bus_info {
 448         enum i40e_bus_speed speed;
 449         enum i40e_bus_width width;
 450         enum i40e_bus_type type;
 451
 452         u16 func;
 453         u16 device;
 454         u16 lan_id;
 455 };
 456
 457 /* Flow control (FC) parameters */
 458 struct i40e_fc_info {
 459         enum i40e_fc_mode current_mode; /* FC mode in effect */
 460         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 461 };
 462
 463 #define I40E_MAX_TRAFFIC_CLASS          8
 464 #define I40E_MAX_USER_PRIORITY          8
 465 #define I40E_DCBX_MAX_APPS              32
 466 #define I40E_LLDPDU_SIZE                1500
 467 #define I40E_TLV_STATUS_OPER            0x1
 468 #define I40E_TLV_STATUS_SYNC            0x2
 469 #define I40E_TLV_STATUS_ERR             0x4
 470 #define I40E_CEE_OPER_MAX_APPS          3
 471 #define I40E_APP_PROTOID_FCOE           0x8906
 472 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 473 #define I40E_APP_PROTOID_FIP            0x8914
 474 #define I40E_APP_SEL_ETHTYPE            0x1
 475 #define I40E_APP_SEL_TCPIP              0x2
 476
 477 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 478 struct i40e_dcb_ets_config {
 479         u8 willing;
 480         u8 cbs;
 481         u8 maxtcs;
 482         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 483         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 484         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 485 };
 486
 487 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 488 struct i40e_dcb_pfc_config {
 489         u8 willing;
 490         u8 mbc;
 491         u8 pfccap;
 492         u8 pfcenable;
 493 };
 494
 495 /* CEE or IEEE 802.1Qaz Application Priority data */
 496 struct i40e_dcb_app_priority_table {
 497         u8  priority;
 498         u8  selector;
 499         u16 protocolid;
 500 };
 501
 502 struct i40e_dcbx_config {
 503         u8  dcbx_mode;
 504 #define I40E_DCBX_MODE_CEE      0x1
 505 #define I40E_DCBX_MODE_IEEE     0x2
 506         u32 numapps;
 507         struct i40e_dcb_ets_config etscfg;
 508         struct i40e_dcb_ets_config etsrec;
 509         struct i40e_dcb_pfc_config pfc;
 510         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 511 };
 512
 513 /* Port hardware description */
 514 struct i40e_hw {
 515         u8 *hw_addr;
 516         void *back;
 517
 518         /* subsystem structs */
 519         struct i40e_phy_info phy;
 520         struct i40e_mac_info mac;
 521         struct i40e_bus_info bus;
 522         struct i40e_nvm_info nvm;
 523         struct i40e_fc_info fc;
 524
 525         /* pci info */
 526         u16 device_id;
 527         u16 vendor_id;
 528         u16 subsystem_device_id;
 529         u16 subsystem_vendor_id;
 530         u8 revision_id;
 531         u8 port;
 532         bool adapter_stopped;
 533
 534         /* capabilities for entire device and PCI func */
 535         struct i40e_hw_capabilities dev_caps;
 536         struct i40e_hw_capabilities func_caps;
 537
 538         /* Flow Director shared filter space */
 539         u16 fdir_shared_filter_count;
 540
 541         /* device profile info */
 542         u8  pf_id;
 543         u16 main_vsi_seid;
 544
 545         /* for multi-function MACs */
 546         u16 partition_id;
 547         u16 num_partitions;
 548         u16 num_ports;
 549
 550         /* Closest numa node to the device */
 551         u16 numa_node;
 552
 553         /* Admin Queue info */
 554         struct i40e_adminq_info aq;
 555
 556         /* state of nvm update process */
 557         enum i40e_nvmupd_state nvmupd_state;
 558         struct i40e_aq_desc nvm_wb_desc;
 559         struct i40e_virt_mem nvm_buff;
 560
 561         /* HMC info */
 562         struct i40e_hmc_info hmc; /* HMC info struct */
 563
 564         /* LLDP/DCBX Status */
 565         u16 dcbx_status;
 566
 567         /* DCBX info */
 568         struct i40e_dcbx_config local_dcbx_config;
 569         struct i40e_dcbx_config remote_dcbx_config;
 570
 571         /* debug mask */
 572         u32 debug_mask;
 573 #ifndef I40E_NDIS_SUPPORT
 574         char err_str[16];
 575 #endif /* I40E_NDIS_SUPPORT */
 576 };
 577
 578 static inline bool i40e_is_vf(struct i40e_hw *hw)
 579 {
 580         return hw->mac.type == I40E_MAC_VF;
 581 }
 582
 583 struct i40e_driver_version {
 584         u8 major_version;
 585         u8 minor_version;
 586         u8 build_version;
 587         u8 subbuild_version;
 588         u8 driver_string[32];
 589 };
 590
 591 /* RX Descriptors */
 592 union i40e_16byte_rx_desc {
 593         struct {
 594                 __le64 pkt_addr; /* Packet buffer address */
 595                 __le64 hdr_addr; /* Header buffer address */
 596         } read;
 597         struct {
 598                 struct {
 599                         struct {
 600                                 union {
 601                                         __le16 mirroring_status;
 602                                         __le16 fcoe_ctx_id;
 603                                 } mirr_fcoe;
 604                                 __le16 l2tag1;
 605                         } lo_dword;
 606                         union {
 607                                 __le32 rss; /* RSS Hash */
 608                                 __le32 fd_id; /* Flow director filter id */
 609                                 __le32 fcoe_param; /* FCoE DDP Context id */
 610                         } hi_dword;
 611                 } qword0;
 612                 struct {
 613                         /* ext status/error/pktype/length */
 614                         __le64 status_error_len;
 615                 } qword1;
 616         } wb;  /* writeback */
 617 };
 618
 619 union i40e_32byte_rx_desc {
 620         struct {
 621                 __le64  pkt_addr; /* Packet buffer address */
 622                 __le64  hdr_addr; /* Header buffer address */
 623                         /* bit 0 of hdr_buffer_addr is DD bit */
 624                 __le64  rsvd1;
 625                 __le64  rsvd2;
 626         } read;
 627         struct {
 628                 struct {
 629                         struct {
 630                                 union {
 631                                         __le16 mirroring_status;
 632                                         __le16 fcoe_ctx_id;
 633                                 } mirr_fcoe;
 634                                 __le16 l2tag1;
 635                         } lo_dword;
 636                         union {
 637                                 __le32 rss; /* RSS Hash */
 638                                 __le32 fcoe_param; /* FCoE DDP Context id */
 639                                 /* Flow director filter id in case of
 640                                  * Programming status desc WB
 641                                  */
 642                                 __le32 fd_id;
 643                         } hi_dword;
 644                 } qword0;
 645                 struct {
 646                         /* status/error/pktype/length */
 647                         __le64 status_error_len;
 648                 } qword1;
 649                 struct {
 650                         __le16 ext_status; /* extended status */
 651                         __le16 rsvd;
 652                         __le16 l2tag2_1;
 653                         __le16 l2tag2_2;
 654                 } qword2;
 655                 struct {
 656                         union {
 657                                 __le32 flex_bytes_lo;
 658                                 __le32 pe_status;
 659                         } lo_dword;
 660                         union {
 661                                 __le32 flex_bytes_hi;
 662                                 __le32 fd_id;
 663                         } hi_dword;
 664                 } qword3;
 665         } wb;  /* writeback */
 666 };
 667
 668 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 669 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 670                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 671 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 672 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 673                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 674
 675 enum i40e_rx_desc_status_bits {
 676         /* Note: These are predefined bit offsets */
 677         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 678         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 679         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 680         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 681         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 682         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 683         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 684         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 685
 686         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 687         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 688         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 689         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 690         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 691         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 692         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 693         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 694 };
 695
 696 #define I40E_RXD_QW1_STATUS_SHIFT       0
 697 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
 698                                          I40E_RXD_QW1_STATUS_SHIFT)
 699
 700 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 701 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 702                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 703
 704 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 705 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 706                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 707
 708 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 709 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 710                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 711
 712 enum i40e_rx_desc_fltstat_values {
 713         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 714         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 715         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 716         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 717 };
 718
 719 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 720 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 721 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 722 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 723
 724 #define I40E_RXD_QW1_ERROR_SHIFT        19
 725 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 726
 727 enum i40e_rx_desc_error_bits {
 728         /* Note: These are predefined bit offsets */
 729         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 730         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 731         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 732         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 733         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 734         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 735         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 736         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 737         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 738 };
 739
 740 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 741         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 742         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 743         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 744         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 745         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 746 };
 747
 748 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 749 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 750
 751 /* Packet type non-ip values */
 752 enum i40e_rx_l2_ptype {
 753         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 754         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 755         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 756         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 757         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 758         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 759         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 760         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 761         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 762         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 763         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 764         I40E_RX_PTYPE_L2_ARP                            = 11,
 765         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 766         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 767         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 768         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 769         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 770         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 771         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 772         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 773         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 774         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 775         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 776         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 777         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 778         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 779 };
 780
 781 struct i40e_rx_ptype_decoded {
 782         u32 ptype:8;
 783         u32 known:1;
 784         u32 outer_ip:1;
 785         u32 outer_ip_ver:1;
 786         u32 outer_frag:1;
 787         u32 tunnel_type:3;
 788         u32 tunnel_end_prot:2;
 789         u32 tunnel_end_frag:1;
 790         u32 inner_prot:4;
 791         u32 payload_layer:3;
 792 };
 793
 794 enum i40e_rx_ptype_outer_ip {
 795         I40E_RX_PTYPE_OUTER_L2  = 0,
 796         I40E_RX_PTYPE_OUTER_IP  = 1
 797 };
 798
 799 enum i40e_rx_ptype_outer_ip_ver {
 800         I40E_RX_PTYPE_OUTER_NONE        = 0,
 801         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 802         I40E_RX_PTYPE_OUTER_IPV6        = 1
 803 };
 804
 805 enum i40e_rx_ptype_outer_fragmented {
 806         I40E_RX_PTYPE_NOT_FRAG  = 0,
 807         I40E_RX_PTYPE_FRAG      = 1
 808 };
 809
 810 enum i40e_rx_ptype_tunnel_type {
 811         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 812         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 813         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 814         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 815         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 816 };
 817
 818 enum i40e_rx_ptype_tunnel_end_prot {
 819         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 820         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 821         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 822 };
 823
 824 enum i40e_rx_ptype_inner_prot {
 825         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 826         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 827         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 828         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 829         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 830         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 831 };
 832
 833 enum i40e_rx_ptype_payload_layer {
 834         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 835         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 836         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 837         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 838 };
 839
 840 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 841 #define I40E_RX_PTYPE_SHIFT             56
 842
 843 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 844 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 845                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 846
 847 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 848 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 849                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 850
 851 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 852 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 853                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 854
 855 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 856 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 857
 858 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 859 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 860                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 861
 862 enum i40e_rx_desc_ext_status_bits {
 863         /* Note: These are predefined bit offsets */
 864         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 865         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 866         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 867         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 868         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 869         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 870         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 871 };
 872
 873 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 874 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 875
 876 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 877 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 878
 879 enum i40e_rx_desc_pe_status_bits {
 880         /* Note: These are predefined bit offsets */
 881         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 882         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 883         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 884         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 885         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 886         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 887         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 888         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 889         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 890 };
 891
 892 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 893 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 894
 895 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 896 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 897                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 898
 899 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 900 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 901                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 902
 903 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 904 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 905                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 906
 907 enum i40e_rx_prog_status_desc_status_bits {
 908         /* Note: These are predefined bit offsets */
 909         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 910         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 911 };
 912
 913 enum i40e_rx_prog_status_desc_prog_id_masks {
 914         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 915         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 916         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 917 };
 918
 919 enum i40e_rx_prog_status_desc_error_bits {
 920         /* Note: These are predefined bit offsets */
 921         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 922         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 923         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 924         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 925 };
 926
 927 #define I40E_TWO_BIT_MASK       0x3
 928 #define I40E_THREE_BIT_MASK     0x7
 929 #define I40E_FOUR_BIT_MASK      0xF
 930 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
 931
 932 /* TX Descriptor */
 933 struct i40e_tx_desc {
 934         __le64 buffer_addr; /* Address of descriptor's data buf */
 935         __le64 cmd_type_offset_bsz;
 936 };
 937
 938 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 939 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 940
 941 enum i40e_tx_desc_dtype_value {
 942         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 943         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 944         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 945         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 946         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 947         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 948         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 949         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 950         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 951         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 952 };
 953
 954 #define I40E_TXD_QW1_CMD_SHIFT  4
 955 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 956
 957 enum i40e_tx_desc_cmd_bits {
 958         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 959         I40E_TX_DESC_CMD_RS                     = 0x0002,
 960         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 961         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 962         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 963         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 964         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 965         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 966         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 967         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 968         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 969         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 970         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 971         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 972         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 973         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 974         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 975         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 976 };
 977
 978 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 979 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 980                                          I40E_TXD_QW1_OFFSET_SHIFT)
 981
 982 enum i40e_tx_desc_length_fields {
 983         /* Note: These are predefined bit offsets */
 984         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 985         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 986         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 987 };
 988
 989 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
 990 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
 991 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 992 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 993
 994 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 995 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 996                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 997
 998 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 999 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1000
1001 /* Context descriptors */
1002 struct i40e_tx_context_desc {
1003         __le32 tunneling_params;
1004         __le16 l2tag2;
1005         __le16 rsvd;
1006         __le64 type_cmd_tso_mss;
1007 };
1008
1009 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1010 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1011
1012 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1013 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1014
1015 enum i40e_tx_ctx_desc_cmd_bits {
1016         I40E_TX_CTX_DESC_TSO            = 0x01,
1017         I40E_TX_CTX_DESC_TSYN           = 0x02,
1018         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1019         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1020         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1021         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1022         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1023         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1024         I40E_TX_CTX_DESC_SWPE           = 0x40
1025 };
1026
1027 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1028 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1029                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1030
1031 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1032 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1033                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1034
1035 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1036 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1037
1038 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1039 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1040                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1041
1042 enum i40e_tx_ctx_desc_eipt_offload {
1043         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1044         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1045         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1046         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1047 };
1048
1049 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1050 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1051                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1052
1053 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1054 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1055
1056 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1057 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1058
1059 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1060 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
1061                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1062
1063 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1064
1065 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1066 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1067                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1068
1069 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1070 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1071                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1072
1073 struct i40e_nop_desc {
1074         __le64 rsvd;
1075         __le64 dtype_cmd;
1076 };
1077
1078 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1079 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1080
1081 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1082 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1083
1084 enum i40e_tx_nop_desc_cmd_bits {
1085         /* Note: These are predefined bit offsets */
1086         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1087         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1088         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1089 };
1090
1091 struct i40e_filter_program_desc {
1092         __le32 qindex_flex_ptype_vsi;
1093         __le32 rsvd;
1094         __le32 dtype_cmd_cntindex;
1095         __le32 fd_id;
1096 };
1097 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1098 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1099                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1100 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1101 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1102                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1103 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1104 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1105                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1106
1107 /* Packet Classifier Types for filters */
1108 enum i40e_filter_pctype {
1109         /* Note: Values 0-30 are reserved for future use */
1110         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1111         /* Note: Value 32 is reserved for future use */
1112         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1113         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1114         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1115         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1116         /* Note: Values 37-40 are reserved for future use */
1117         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1118         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1119         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1120         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1121         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1122         /* Note: Value 47 is reserved for future use */
1123         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1124         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1125         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1126         /* Note: Values 51-62 are reserved for future use */
1127         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1128 };
1129
1130 enum i40e_filter_program_desc_dest {
1131         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1132         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1133         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1134 };
1135
1136 enum i40e_filter_program_desc_fd_status {
1137         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1138         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1139         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1140         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1141 };
1142
1143 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1144 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1145                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1146
1147 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1148 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1149
1150 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1151 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1152                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1153
1154 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1155 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1156
1157 enum i40e_filter_program_desc_pcmd {
1158         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1159         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1160 };
1161
1162 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1163 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1164
1165 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1166 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
1167                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1168
1169 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1170                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1171 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1172                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1173
1174 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1175 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1176                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1177
1178 enum i40e_filter_type {
1179         I40E_FLOW_DIRECTOR_FLTR = 0,
1180         I40E_PE_QUAD_HASH_FLTR = 1,
1181         I40E_ETHERTYPE_FLTR,
1182         I40E_FCOE_CTX_FLTR,
1183         I40E_MAC_VLAN_FLTR,
1184         I40E_HASH_FLTR
1185 };
1186
1187 struct i40e_vsi_context {
1188         u16 seid;
1189         u16 uplink_seid;
1190         u16 vsi_number;
1191         u16 vsis_allocated;
1192         u16 vsis_unallocated;
1193         u16 flags;
1194         u8 pf_num;
1195         u8 vf_num;
1196         u8 connection_type;
1197         struct i40e_aqc_vsi_properties_data info;
1198 };
1199
1200 struct i40e_veb_context {
1201         u16 seid;
1202         u16 uplink_seid;
1203         u16 veb_number;
1204         u16 vebs_allocated;
1205         u16 vebs_unallocated;
1206         u16 flags;
1207         struct i40e_aqc_get_veb_parameters_completion info;
1208 };
1209
1210 /* Statistics collected by each port, VSI, VEB, and S-channel */
1211 struct i40e_eth_stats {
1212         u64 rx_bytes;                   /* gorc */
1213         u64 rx_unicast;                 /* uprc */
1214         u64 rx_multicast;               /* mprc */
1215         u64 rx_broadcast;               /* bprc */
1216         u64 rx_discards;                /* rdpc */
1217         u64 rx_unknown_protocol;        /* rupp */
1218         u64 tx_bytes;                   /* gotc */
1219         u64 tx_unicast;                 /* uptc */
1220         u64 tx_multicast;               /* mptc */
1221         u64 tx_broadcast;               /* bptc */
1222         u64 tx_discards;                /* tdpc */
1223         u64 tx_errors;                  /* tepc */
1224 };
1225
1226 /* Statistics collected per VEB per TC */
1227 struct i40e_veb_tc_stats {
1228         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1229         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1230         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1231         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1232 };
1233
1234 /* Statistics collected by the MAC */
1235 struct i40e_hw_port_stats {
1236         /* eth stats collected by the port */
1237         struct i40e_eth_stats eth;
1238
1239         /* additional port specific stats */
1240         u64 tx_dropped_link_down;       /* tdold */
1241         u64 crc_errors;                 /* crcerrs */
1242         u64 illegal_bytes;              /* illerrc */
1243         u64 error_bytes;                /* errbc */
1244         u64 mac_local_faults;           /* mlfc */
1245         u64 mac_remote_faults;          /* mrfc */
1246         u64 rx_length_errors;           /* rlec */
1247         u64 link_xon_rx;                /* lxonrxc */
1248         u64 link_xoff_rx;               /* lxoffrxc */
1249         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1250         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1251         u64 link_xon_tx;                /* lxontxc */
1252         u64 link_xoff_tx;               /* lxofftxc */
1253         u64 priority_xon_tx[8];         /* pxontxc[8] */
1254         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1255         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1256         u64 rx_size_64;                 /* prc64 */
1257         u64 rx_size_127;                /* prc127 */
1258         u64 rx_size_255;                /* prc255 */
1259         u64 rx_size_511;                /* prc511 */
1260         u64 rx_size_1023;               /* prc1023 */
1261         u64 rx_size_1522;               /* prc1522 */
1262         u64 rx_size_big;                /* prc9522 */
1263         u64 rx_undersize;               /* ruc */
1264         u64 rx_fragments;               /* rfc */
1265         u64 rx_oversize;                /* roc */
1266         u64 rx_jabber;                  /* rjc */
1267         u64 tx_size_64;                 /* ptc64 */
1268         u64 tx_size_127;                /* ptc127 */
1269         u64 tx_size_255;                /* ptc255 */
1270         u64 tx_size_511;                /* ptc511 */
1271         u64 tx_size_1023;               /* ptc1023 */
1272         u64 tx_size_1522;               /* ptc1522 */
1273         u64 tx_size_big;                /* ptc9522 */
1274         u64 mac_short_packet_dropped;   /* mspdc */
1275         u64 checksum_error;             /* xec */
1276         /* flow director stats */
1277         u64 fd_atr_match;
1278         u64 fd_sb_match;
1279         /* EEE LPI */
1280         u32 tx_lpi_status;
1281         u32 rx_lpi_status;
1282         u64 tx_lpi_count;               /* etlpic */
1283         u64 rx_lpi_count;               /* erlpic */
1284 };
1285
1286 /* Checksum and Shadow RAM pointers */
1287 #define I40E_SR_NVM_CONTROL_WORD                0x00
1288 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1289 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1290 #define I40E_SR_OPTION_ROM_PTR                  0x05
1291 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1292 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1293 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1294 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1295 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1296 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1297 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1298 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1299 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1300 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1301 #define I40E_SR_PBA_FLAGS                       0x15
1302 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1303 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1304 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1305 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1306 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1307 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1308 #define I40E_SR_NVM_MAP_VERSION                 0x29
1309 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1310 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1311 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1312 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1313 #define I40E_SR_VPD_PTR                         0x2F
1314 #define I40E_SR_PXE_SETUP_PTR                   0x30
1315 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1316 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1317 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1318 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1319 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1320 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1321 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1322 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1323 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1324 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1325 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1326 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1327 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1328 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1329 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1330 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1331 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1332 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1333
1334 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1335 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1336 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1337 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1338 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1339
1340 /* Shadow RAM related */
1341 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1342 #define I40E_SR_BUF_ALIGNMENT           4096
1343 #define I40E_SR_WORDS_IN_1KB            512
1344 /* Checksum should be calculated such that after adding all the words,
1345  * including the checksum word itself, the sum should be 0xBABA.
1346  */
1347 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1348
1349 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1350
1351 enum i40e_switch_element_types {
1352         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1353         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1354         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1355         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1356         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1357         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1358         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1359         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1360         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1361 };
1362
1363 /* Supported EtherType filters */
1364 enum i40e_ether_type_index {
1365         I40E_ETHER_TYPE_1588            = 0,
1366         I40E_ETHER_TYPE_FIP             = 1,
1367         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1368         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1369         I40E_ETHER_TYPE_LLDP            = 4,
1370         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1371         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1372         I40E_ETHER_TYPE_QCN_CNM         = 7,
1373         I40E_ETHER_TYPE_8021X           = 8,
1374         I40E_ETHER_TYPE_ARP             = 9,
1375         I40E_ETHER_TYPE_RSV1            = 10,
1376         I40E_ETHER_TYPE_RSV2            = 11,
1377 };
1378
1379 /* Filter context base size is 1K */
1380 #define I40E_HASH_FILTER_BASE_SIZE      1024
1381 /* Supported Hash filter values */
1382 enum i40e_hash_filter_size {
1383         I40E_HASH_FILTER_SIZE_1K        = 0,
1384         I40E_HASH_FILTER_SIZE_2K        = 1,
1385         I40E_HASH_FILTER_SIZE_4K        = 2,
1386         I40E_HASH_FILTER_SIZE_8K        = 3,
1387         I40E_HASH_FILTER_SIZE_16K       = 4,
1388         I40E_HASH_FILTER_SIZE_32K       = 5,
1389         I40E_HASH_FILTER_SIZE_64K       = 6,
1390         I40E_HASH_FILTER_SIZE_128K      = 7,
1391         I40E_HASH_FILTER_SIZE_256K      = 8,
1392         I40E_HASH_FILTER_SIZE_512K      = 9,
1393         I40E_HASH_FILTER_SIZE_1M        = 10,
1394 };
1395
1396 /* DMA context base size is 0.5K */
1397 #define I40E_DMA_CNTX_BASE_SIZE         512
1398 /* Supported DMA context values */
1399 enum i40e_dma_cntx_size {
1400         I40E_DMA_CNTX_SIZE_512          = 0,
1401         I40E_DMA_CNTX_SIZE_1K           = 1,
1402         I40E_DMA_CNTX_SIZE_2K           = 2,
1403         I40E_DMA_CNTX_SIZE_4K           = 3,
1404         I40E_DMA_CNTX_SIZE_8K           = 4,
1405         I40E_DMA_CNTX_SIZE_16K          = 5,
1406         I40E_DMA_CNTX_SIZE_32K          = 6,
1407         I40E_DMA_CNTX_SIZE_64K          = 7,
1408         I40E_DMA_CNTX_SIZE_128K         = 8,
1409         I40E_DMA_CNTX_SIZE_256K         = 9,
1410 };
1411
1412 /* Supported Hash look up table (LUT) sizes */
1413 enum i40e_hash_lut_size {
1414         I40E_HASH_LUT_SIZE_128          = 0,
1415         I40E_HASH_LUT_SIZE_512          = 1,
1416 };
1417
1418 /* Structure to hold a per PF filter control settings */
1419 struct i40e_filter_control_settings {
1420         /* number of PE Quad Hash filter buckets */
1421         enum i40e_hash_filter_size pe_filt_num;
1422         /* number of PE Quad Hash contexts */
1423         enum i40e_dma_cntx_size pe_cntx_num;
1424         /* number of FCoE filter buckets */
1425         enum i40e_hash_filter_size fcoe_filt_num;
1426         /* number of FCoE DDP contexts */
1427         enum i40e_dma_cntx_size fcoe_cntx_num;
1428         /* size of the Hash LUT */
1429         enum i40e_hash_lut_size hash_lut_size;
1430         /* enable FDIR filters for PF and its VFs */
1431         bool enable_fdir;
1432         /* enable Ethertype filters for PF and its VFs */
1433         bool enable_ethtype;
1434         /* enable MAC/VLAN filters for PF and its VFs */
1435         bool enable_macvlan;
1436 };
1437
1438 /* Structure to hold device level control filter counts */
1439 struct i40e_control_filter_stats {
1440         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1441         u16 etype_used;       /* Used perfect EtherType filters */
1442         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1443         u16 etype_free;       /* Un-used perfect EtherType filters */
1444 };
1445
1446 enum i40e_reset_type {
1447         I40E_RESET_POR          = 0,
1448         I40E_RESET_CORER        = 1,
1449         I40E_RESET_GLOBR        = 2,
1450         I40E_RESET_EMPR         = 3,
1451 };
1452
1453 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1454 #define I40E_NVM_LLDP_CFG_PTR           0xD
1455 struct i40e_lldp_variables {
1456         u16 length;
1457         u16 adminstatus;
1458         u16 msgfasttx;
1459         u16 msgtxinterval;
1460         u16 txparams;
1461         u16 timers;
1462         u16 crc8;
1463 };
1464
1465 /* Offsets into Alternate Ram */
1466 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1467 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1468 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1469 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1470 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1471 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1472
1473 /* Alternate Ram Bandwidth Masks */
1474 #define I40E_ALT_BW_VALUE_MASK          0xFF
1475 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1476 #define I40E_ALT_BW_VALID_MASK          0x80000000
1477
1478 /* RSS Hash Table Size */
1479 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1480 #endif /* _I40E_TYPE_H_ */