drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 161                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 162 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 163                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 164 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 165                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 166
 167 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 168                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 169 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 170                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 171 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 172                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 173 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 174                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 175 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 176                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 177
 178 #define I40E_PHY_COM_REG_PAGE                   0x1E
 179 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 180 #define I40E_PHY_LED_MANUAL_ON                  0x100
 181 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 182 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 183 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 184
 185 /* Memory types */
 186 enum i40e_memset_type {
 187         I40E_NONDMA_MEM = 0,
 188         I40E_DMA_MEM
 189 };
 190
 191 /* Memcpy types */
 192 enum i40e_memcpy_type {
 193         I40E_NONDMA_TO_NONDMA = 0,
 194         I40E_NONDMA_TO_DMA,
 195         I40E_DMA_TO_DMA,
 196         I40E_DMA_TO_NONDMA
 197 };
 198
 199 #ifdef X722_SUPPORT
 200 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 201 #endif
 202 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 203
 204
 205 /* These are structs for managing the hardware information and the operations.
 206  * The structures of function pointers are filled out at init time when we
 207  * know for sure exactly which hardware we're working with.  This gives us the
 208  * flexibility of using the same main driver code but adapting to slightly
 209  * different hardware needs as new parts are developed.  For this architecture,
 210  * the Firmware and AdminQ are intended to insulate the driver from most of the
 211  * future changes, but these structures will also do part of the job.
 212  */
 213 enum i40e_mac_type {
 214         I40E_MAC_UNKNOWN = 0,
 215         I40E_MAC_X710,
 216         I40E_MAC_XL710,
 217         I40E_MAC_VF,
 218 #ifdef X722_SUPPORT
 219         I40E_MAC_X722,
 220         I40E_MAC_X722_VF,
 221 #endif
 222         I40E_MAC_GENERIC,
 223 };
 224
 225 enum i40e_media_type {
 226         I40E_MEDIA_TYPE_UNKNOWN = 0,
 227         I40E_MEDIA_TYPE_FIBER,
 228         I40E_MEDIA_TYPE_BASET,
 229         I40E_MEDIA_TYPE_BACKPLANE,
 230         I40E_MEDIA_TYPE_CX4,
 231         I40E_MEDIA_TYPE_DA,
 232         I40E_MEDIA_TYPE_VIRTUAL
 233 };
 234
 235 enum i40e_fc_mode {
 236         I40E_FC_NONE = 0,
 237         I40E_FC_RX_PAUSE,
 238         I40E_FC_TX_PAUSE,
 239         I40E_FC_FULL,
 240         I40E_FC_PFC,
 241         I40E_FC_DEFAULT
 242 };
 243
 244 enum i40e_set_fc_aq_failures {
 245         I40E_SET_FC_AQ_FAIL_NONE = 0,
 246         I40E_SET_FC_AQ_FAIL_GET = 1,
 247         I40E_SET_FC_AQ_FAIL_SET = 2,
 248         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 249         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 250 };
 251
 252 enum i40e_vsi_type {
 253         I40E_VSI_MAIN   = 0,
 254         I40E_VSI_VMDQ1  = 1,
 255         I40E_VSI_VMDQ2  = 2,
 256         I40E_VSI_CTRL   = 3,
 257         I40E_VSI_FCOE   = 4,
 258         I40E_VSI_MIRROR = 5,
 259         I40E_VSI_SRIOV  = 6,
 260         I40E_VSI_FDIR   = 7,
 261         I40E_VSI_TYPE_UNKNOWN
 262 };
 263
 264 enum i40e_queue_type {
 265         I40E_QUEUE_TYPE_RX = 0,
 266         I40E_QUEUE_TYPE_TX,
 267         I40E_QUEUE_TYPE_PE_CEQ,
 268         I40E_QUEUE_TYPE_UNKNOWN
 269 };
 270
 271 struct i40e_link_status {
 272         enum i40e_aq_phy_type phy_type;
 273         enum i40e_aq_link_speed link_speed;
 274         u8 link_info;
 275         u8 an_info;
 276         u8 ext_info;
 277         u8 loopback;
 278         /* is Link Status Event notification to SW enabled */
 279         bool lse_enable;
 280         u16 max_frame_size;
 281         bool crc_enable;
 282         u8 pacing;
 283         u8 requested_speeds;
 284         u8 module_type[3];
 285         /* 1st byte: module identifier */
 286 #define I40E_MODULE_TYPE_SFP            0x03
 287 #define I40E_MODULE_TYPE_QSFP           0x0D
 288         /* 2nd byte: ethernet compliance codes for 10/40G */
 289 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 290 #define I40E_MODULE_TYPE_40G_LR4        0x02
 291 #define I40E_MODULE_TYPE_40G_SR4        0x04
 292 #define I40E_MODULE_TYPE_40G_CR4        0x08
 293 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 294 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 295 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 296 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 297         /* 3rd byte: ethernet compliance codes for 1G */
 298 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 299 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 300 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 301 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 302 };
 303
 304 struct i40e_phy_info {
 305         struct i40e_link_status link_info;
 306         struct i40e_link_status link_info_old;
 307         bool get_link_info;
 308         enum i40e_media_type media_type;
 309         /* all the phy types the NVM is capable of */
 310         u64 phy_types;
 311 };
 312
 313 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 314 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 315 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 316 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 317 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 318 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 319 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 320 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 321 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 322 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 323 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 324 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 325 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 326 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 327 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 328 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 329 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 330 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 331 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 332 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 333 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 334 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 335 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 336 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 337 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 338 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 339 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 340                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 341 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 342 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_KR + 32)
 343 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_CR + 32)
 344 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_SR + 32)
 345 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_LR + 32)
 346 #define I40E_HW_CAP_MAX_GPIO                    30
 347 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 348 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 349
 350 #ifdef X722_SUPPORT
 351 enum i40e_acpi_programming_method {
 352         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 353         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 354 };
 355
 356 #define I40E_WOL_SUPPORT_MASK                   1
 357 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       (1 << 1)
 358 #define I40E_PROXY_SUPPORT_MASK                 (1 << 2)
 359
 360 #endif
 361 /* Capabilities of a PF or a VF or the whole device */
 362 struct i40e_hw_capabilities {
 363         u32  switch_mode;
 364 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 365 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 366 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 367
 368         u32  management_mode;
 369         u32  npar_enable;
 370         u32  os2bmc;
 371         u32  valid_functions;
 372         bool sr_iov_1_1;
 373         bool vmdq;
 374         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 375         bool evb_802_1_qbh; /* Bridge Port Extension */
 376         bool dcb;
 377         bool fcoe;
 378         bool iscsi; /* Indicates iSCSI enabled */
 379         bool flex10_enable;
 380         bool flex10_capable;
 381         u32  flex10_mode;
 382 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 383 #define I40E_FLEX10_MODE_DCC            0x1
 384 #define I40E_FLEX10_MODE_DCI            0x2
 385
 386         u32 flex10_status;
 387 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 388 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 389
 390         bool sec_rev_disabled;
 391         bool update_disabled;
 392 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 393 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 394
 395         bool mgmt_cem;
 396         bool ieee_1588;
 397         bool iwarp;
 398         bool fd;
 399         u32 fd_filters_guaranteed;
 400         u32 fd_filters_best_effort;
 401         bool rss;
 402         u32 rss_table_size;
 403         u32 rss_table_entry_width;
 404         bool led[I40E_HW_CAP_MAX_GPIO];
 405         bool sdp[I40E_HW_CAP_MAX_GPIO];
 406         u32 nvm_image_type;
 407         u32 num_flow_director_filters;
 408         u32 num_vfs;
 409         u32 vf_base_id;
 410         u32 num_vsis;
 411         u32 num_rx_qp;
 412         u32 num_tx_qp;
 413         u32 base_queue;
 414         u32 num_msix_vectors;
 415         u32 num_msix_vectors_vf;
 416         u32 led_pin_num;
 417         u32 sdp_pin_num;
 418         u32 mdio_port_num;
 419         u32 mdio_port_mode;
 420         u8 rx_buf_chain_len;
 421         u32 enabled_tcmap;
 422         u32 maxtc;
 423         u64 wr_csr_prot;
 424 #ifdef X722_SUPPORT
 425         bool apm_wol_support;
 426         enum i40e_acpi_programming_method acpi_prog_method;
 427         bool proxy_support;
 428 #endif
 429 };
 430
 431 struct i40e_mac_info {
 432         enum i40e_mac_type type;
 433         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 434         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 435         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 436         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 437         u16 max_fcoeq;
 438 };
 439
 440 enum i40e_aq_resources_ids {
 441         I40E_NVM_RESOURCE_ID = 1
 442 };
 443
 444 enum i40e_aq_resource_access_type {
 445         I40E_RESOURCE_READ = 1,
 446         I40E_RESOURCE_WRITE
 447 };
 448
 449 struct i40e_nvm_info {
 450         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 451         u32 timeout;              /* [ms] */
 452         u16 sr_size;              /* Shadow RAM size in words */
 453         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 454         u16 version;              /* NVM package version */
 455         u32 eetrack;              /* NVM data version */
 456         u32 oem_ver;              /* OEM version info */
 457 };
 458
 459 /* definitions used in NVM update support */
 460
 461 enum i40e_nvmupd_cmd {
 462         I40E_NVMUPD_INVALID,
 463         I40E_NVMUPD_READ_CON,
 464         I40E_NVMUPD_READ_SNT,
 465         I40E_NVMUPD_READ_LCB,
 466         I40E_NVMUPD_READ_SA,
 467         I40E_NVMUPD_WRITE_ERA,
 468         I40E_NVMUPD_WRITE_CON,
 469         I40E_NVMUPD_WRITE_SNT,
 470         I40E_NVMUPD_WRITE_LCB,
 471         I40E_NVMUPD_WRITE_SA,
 472         I40E_NVMUPD_CSUM_CON,
 473         I40E_NVMUPD_CSUM_SA,
 474         I40E_NVMUPD_CSUM_LCB,
 475         I40E_NVMUPD_STATUS,
 476         I40E_NVMUPD_EXEC_AQ,
 477         I40E_NVMUPD_GET_AQ_RESULT,
 478 };
 479
 480 enum i40e_nvmupd_state {
 481         I40E_NVMUPD_STATE_INIT,
 482         I40E_NVMUPD_STATE_READING,
 483         I40E_NVMUPD_STATE_WRITING,
 484         I40E_NVMUPD_STATE_INIT_WAIT,
 485         I40E_NVMUPD_STATE_WRITE_WAIT,
 486 };
 487
 488 /* nvm_access definition and its masks/shifts need to be accessible to
 489  * application, core driver, and shared code.  Where is the right file?
 490  */
 491 #define I40E_NVM_READ   0xB
 492 #define I40E_NVM_WRITE  0xC
 493
 494 #define I40E_NVM_MOD_PNT_MASK 0xFF
 495
 496 #define I40E_NVM_TRANS_SHIFT    8
 497 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 498 #define I40E_NVM_CON            0x0
 499 #define I40E_NVM_SNT            0x1
 500 #define I40E_NVM_LCB            0x2
 501 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 502 #define I40E_NVM_ERA            0x4
 503 #define I40E_NVM_CSUM           0x8
 504 #define I40E_NVM_EXEC           0xf
 505
 506 #define I40E_NVM_ADAPT_SHIFT    16
 507 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 508
 509 #define I40E_NVMUPD_MAX_DATA    4096
 510 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 511
 512 struct i40e_nvm_access {
 513         u32 command;
 514         u32 config;
 515         u32 offset;     /* in bytes */
 516         u32 data_size;  /* in bytes */
 517         u8 data[1];
 518 };
 519
 520 /* PCI bus types */
 521 enum i40e_bus_type {
 522         i40e_bus_type_unknown = 0,
 523         i40e_bus_type_pci,
 524         i40e_bus_type_pcix,
 525         i40e_bus_type_pci_express,
 526         i40e_bus_type_reserved
 527 };
 528
 529 /* PCI bus speeds */
 530 enum i40e_bus_speed {
 531         i40e_bus_speed_unknown  = 0,
 532         i40e_bus_speed_33       = 33,
 533         i40e_bus_speed_66       = 66,
 534         i40e_bus_speed_100      = 100,
 535         i40e_bus_speed_120      = 120,
 536         i40e_bus_speed_133      = 133,
 537         i40e_bus_speed_2500     = 2500,
 538         i40e_bus_speed_5000     = 5000,
 539         i40e_bus_speed_8000     = 8000,
 540         i40e_bus_speed_reserved
 541 };
 542
 543 /* PCI bus widths */
 544 enum i40e_bus_width {
 545         i40e_bus_width_unknown  = 0,
 546         i40e_bus_width_pcie_x1  = 1,
 547         i40e_bus_width_pcie_x2  = 2,
 548         i40e_bus_width_pcie_x4  = 4,
 549         i40e_bus_width_pcie_x8  = 8,
 550         i40e_bus_width_32       = 32,
 551         i40e_bus_width_64       = 64,
 552         i40e_bus_width_reserved
 553 };
 554
 555 /* Bus parameters */
 556 struct i40e_bus_info {
 557         enum i40e_bus_speed speed;
 558         enum i40e_bus_width width;
 559         enum i40e_bus_type type;
 560
 561         u16 func;
 562         u16 device;
 563         u16 lan_id;
 564 };
 565
 566 /* Flow control (FC) parameters */
 567 struct i40e_fc_info {
 568         enum i40e_fc_mode current_mode; /* FC mode in effect */
 569         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 570 };
 571
 572 #define I40E_MAX_TRAFFIC_CLASS          8
 573 #define I40E_MAX_USER_PRIORITY          8
 574 #define I40E_DCBX_MAX_APPS              32
 575 #define I40E_LLDPDU_SIZE                1500
 576 #define I40E_TLV_STATUS_OPER            0x1
 577 #define I40E_TLV_STATUS_SYNC            0x2
 578 #define I40E_TLV_STATUS_ERR             0x4
 579 #define I40E_CEE_OPER_MAX_APPS          3
 580 #define I40E_APP_PROTOID_FCOE           0x8906
 581 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 582 #define I40E_APP_PROTOID_FIP            0x8914
 583 #define I40E_APP_SEL_ETHTYPE            0x1
 584 #define I40E_APP_SEL_TCPIP              0x2
 585 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 586 #define I40E_CEE_APP_SEL_TCPIP          0x1
 587
 588 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 589 struct i40e_dcb_ets_config {
 590         u8 willing;
 591         u8 cbs;
 592         u8 maxtcs;
 593         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 594         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 595         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 596 };
 597
 598 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 599 struct i40e_dcb_pfc_config {
 600         u8 willing;
 601         u8 mbc;
 602         u8 pfccap;
 603         u8 pfcenable;
 604 };
 605
 606 /* CEE or IEEE 802.1Qaz Application Priority data */
 607 struct i40e_dcb_app_priority_table {
 608         u8  priority;
 609         u8  selector;
 610         u16 protocolid;
 611 };
 612
 613 struct i40e_dcbx_config {
 614         u8  dcbx_mode;
 615 #define I40E_DCBX_MODE_CEE      0x1
 616 #define I40E_DCBX_MODE_IEEE     0x2
 617         u8  app_mode;
 618 #define I40E_DCBX_APPS_NON_WILLING      0x1
 619         u32 numapps;
 620         u32 tlv_status; /* CEE mode TLV status */
 621         struct i40e_dcb_ets_config etscfg;
 622         struct i40e_dcb_ets_config etsrec;
 623         struct i40e_dcb_pfc_config pfc;
 624         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 625 };
 626
 627 /* Port hardware description */
 628 struct i40e_hw {
 629         u8 *hw_addr;
 630         void *back;
 631
 632         /* subsystem structs */
 633         struct i40e_phy_info phy;
 634         struct i40e_mac_info mac;
 635         struct i40e_bus_info bus;
 636         struct i40e_nvm_info nvm;
 637         struct i40e_fc_info fc;
 638
 639         /* pci info */
 640         u16 device_id;
 641         u16 vendor_id;
 642         u16 subsystem_device_id;
 643         u16 subsystem_vendor_id;
 644         u8 revision_id;
 645         u8 port;
 646         bool adapter_stopped;
 647
 648         /* capabilities for entire device and PCI func */
 649         struct i40e_hw_capabilities dev_caps;
 650         struct i40e_hw_capabilities func_caps;
 651
 652         /* Flow Director shared filter space */
 653         u16 fdir_shared_filter_count;
 654
 655         /* device profile info */
 656         u8  pf_id;
 657         u16 main_vsi_seid;
 658
 659         /* for multi-function MACs */
 660         u16 partition_id;
 661         u16 num_partitions;
 662         u16 num_ports;
 663
 664         /* Closest numa node to the device */
 665         u16 numa_node;
 666
 667         /* Admin Queue info */
 668         struct i40e_adminq_info aq;
 669
 670         /* state of nvm update process */
 671         enum i40e_nvmupd_state nvmupd_state;
 672         struct i40e_aq_desc nvm_wb_desc;
 673         struct i40e_virt_mem nvm_buff;
 674         bool nvm_release_on_done;
 675         u16 nvm_wait_opcode;
 676
 677         /* HMC info */
 678         struct i40e_hmc_info hmc; /* HMC info struct */
 679
 680         /* LLDP/DCBX Status */
 681         u16 dcbx_status;
 682
 683         /* DCBX info */
 684         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 685         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 686         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 687
 688 #ifdef X722_SUPPORT
 689         /* WoL and proxy support */
 690         u16 num_wol_proxy_filters;
 691         u16 wol_proxy_vsi_seid;
 692
 693 #endif
 694 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 695         u64 flags;
 696
 697         /* debug mask */
 698         u32 debug_mask;
 699 #ifndef I40E_NDIS_SUPPORT
 700         char err_str[16];
 701 #endif /* I40E_NDIS_SUPPORT */
 702 };
 703
 704 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 705 {
 706 #ifdef X722_SUPPORT
 707         return (hw->mac.type == I40E_MAC_VF ||
 708                 hw->mac.type == I40E_MAC_X722_VF);
 709 #else
 710         return hw->mac.type == I40E_MAC_VF;
 711 #endif
 712 }
 713
 714 struct i40e_driver_version {
 715         u8 major_version;
 716         u8 minor_version;
 717         u8 build_version;
 718         u8 subbuild_version;
 719         u8 driver_string[32];
 720 };
 721
 722 /* RX Descriptors */
 723 union i40e_16byte_rx_desc {
 724         struct {
 725                 __le64 pkt_addr; /* Packet buffer address */
 726                 __le64 hdr_addr; /* Header buffer address */
 727         } read;
 728         struct {
 729                 struct {
 730                         struct {
 731                                 union {
 732                                         __le16 mirroring_status;
 733                                         __le16 fcoe_ctx_id;
 734                                 } mirr_fcoe;
 735                                 __le16 l2tag1;
 736                         } lo_dword;
 737                         union {
 738                                 __le32 rss; /* RSS Hash */
 739                                 __le32 fd_id; /* Flow director filter id */
 740                                 __le32 fcoe_param; /* FCoE DDP Context id */
 741                         } hi_dword;
 742                 } qword0;
 743                 struct {
 744                         /* ext status/error/pktype/length */
 745                         __le64 status_error_len;
 746                 } qword1;
 747         } wb;  /* writeback */
 748 };
 749
 750 union i40e_32byte_rx_desc {
 751         struct {
 752                 __le64  pkt_addr; /* Packet buffer address */
 753                 __le64  hdr_addr; /* Header buffer address */
 754                         /* bit 0 of hdr_buffer_addr is DD bit */
 755                 __le64  rsvd1;
 756                 __le64  rsvd2;
 757         } read;
 758         struct {
 759                 struct {
 760                         struct {
 761                                 union {
 762                                         __le16 mirroring_status;
 763                                         __le16 fcoe_ctx_id;
 764                                 } mirr_fcoe;
 765                                 __le16 l2tag1;
 766                         } lo_dword;
 767                         union {
 768                                 __le32 rss; /* RSS Hash */
 769                                 __le32 fcoe_param; /* FCoE DDP Context id */
 770                                 /* Flow director filter id in case of
 771                                  * Programming status desc WB
 772                                  */
 773                                 __le32 fd_id;
 774                         } hi_dword;
 775                 } qword0;
 776                 struct {
 777                         /* status/error/pktype/length */
 778                         __le64 status_error_len;
 779                 } qword1;
 780                 struct {
 781                         __le16 ext_status; /* extended status */
 782                         __le16 rsvd;
 783                         __le16 l2tag2_1;
 784                         __le16 l2tag2_2;
 785                 } qword2;
 786                 struct {
 787                         union {
 788                                 __le32 flex_bytes_lo;
 789                                 __le32 pe_status;
 790                         } lo_dword;
 791                         union {
 792                                 __le32 flex_bytes_hi;
 793                                 __le32 fd_id;
 794                         } hi_dword;
 795                 } qword3;
 796         } wb;  /* writeback */
 797 };
 798
 799 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 800 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 801                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 802 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 803 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 804                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 805
 806 enum i40e_rx_desc_status_bits {
 807         /* Note: These are predefined bit offsets */
 808         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 809         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 810         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 811         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 812         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 813         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 814         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 815 #ifdef X722_SUPPORT
 816         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 817 #else
 818         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 819 #endif
 820
 821         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 822         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 823         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 824         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 825         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 826         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 827 #ifdef X722_SUPPORT
 828         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 829 #else
 830         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 831 #endif
 832         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 833 };
 834
 835 #define I40E_RXD_QW1_STATUS_SHIFT       0
 836 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 837                                          I40E_RXD_QW1_STATUS_SHIFT)
 838
 839 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 840 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 841                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 842
 843 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 844 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 845
 846 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 847 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 848                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 849
 850 enum i40e_rx_desc_fltstat_values {
 851         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 852         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 853         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 854         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 855 };
 856
 857 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 858 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 859 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 860 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 861
 862 #define I40E_RXD_QW1_ERROR_SHIFT        19
 863 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 864
 865 enum i40e_rx_desc_error_bits {
 866         /* Note: These are predefined bit offsets */
 867         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 868         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 869         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 870         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 871         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 872         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 873         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 874         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 875         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 876 };
 877
 878 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 879         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 880         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 881         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 882         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 883         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 884 };
 885
 886 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 887 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 888
 889 /* Packet type non-ip values */
 890 enum i40e_rx_l2_ptype {
 891         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 892         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 893         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 894         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 895         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 896         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 897         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 898         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 899         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 900         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 901         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 902         I40E_RX_PTYPE_L2_ARP                            = 11,
 903         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 904         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 905         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 906         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 907         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 908         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 909         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 910         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 911         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 912         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 913         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 914         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 915         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 916         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 917 };
 918
 919 struct i40e_rx_ptype_decoded {
 920         u32 ptype:8;
 921         u32 known:1;
 922         u32 outer_ip:1;
 923         u32 outer_ip_ver:1;
 924         u32 outer_frag:1;
 925         u32 tunnel_type:3;
 926         u32 tunnel_end_prot:2;
 927         u32 tunnel_end_frag:1;
 928         u32 inner_prot:4;
 929         u32 payload_layer:3;
 930 };
 931
 932 enum i40e_rx_ptype_outer_ip {
 933         I40E_RX_PTYPE_OUTER_L2  = 0,
 934         I40E_RX_PTYPE_OUTER_IP  = 1
 935 };
 936
 937 enum i40e_rx_ptype_outer_ip_ver {
 938         I40E_RX_PTYPE_OUTER_NONE        = 0,
 939         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 940         I40E_RX_PTYPE_OUTER_IPV6        = 1
 941 };
 942
 943 enum i40e_rx_ptype_outer_fragmented {
 944         I40E_RX_PTYPE_NOT_FRAG  = 0,
 945         I40E_RX_PTYPE_FRAG      = 1
 946 };
 947
 948 enum i40e_rx_ptype_tunnel_type {
 949         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 950         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 951         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 952         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 953         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 954 };
 955
 956 enum i40e_rx_ptype_tunnel_end_prot {
 957         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 958         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 959         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 960 };
 961
 962 enum i40e_rx_ptype_inner_prot {
 963         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 964         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 965         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 966         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 967         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 968         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 969 };
 970
 971 enum i40e_rx_ptype_payload_layer {
 972         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 973         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 974         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 975         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 976 };
 977
 978 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 979 #define I40E_RX_PTYPE_SHIFT             56
 980
 981 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 982 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 983                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 984
 985 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 986 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 987                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 988
 989 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 990 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 991
 992 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 993 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 994
 995 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 996 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 997                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 998
 999 enum i40e_rx_desc_ext_status_bits {
1000         /* Note: These are predefined bit offsets */
1001         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1002         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1003         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1004         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1005         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1006         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1007         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1008 };
1009
1010 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1011 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1012
1013 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1014 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1015
1016 enum i40e_rx_desc_pe_status_bits {
1017         /* Note: These are predefined bit offsets */
1018         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1019         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1020         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1021         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1022         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1023         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1024         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1025         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1026         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1027 };
1028
1029 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1030 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1031
1032 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1033 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1034                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1035
1036 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1037 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1038                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1039
1040 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1041 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1042                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1043
1044 enum i40e_rx_prog_status_desc_status_bits {
1045         /* Note: These are predefined bit offsets */
1046         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1047         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1048 };
1049
1050 enum i40e_rx_prog_status_desc_prog_id_masks {
1051         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1052         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1053         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1054 };
1055
1056 enum i40e_rx_prog_status_desc_error_bits {
1057         /* Note: These are predefined bit offsets */
1058         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1059         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1060         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1061         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1062 };
1063
1064 #define I40E_TWO_BIT_MASK       0x3
1065 #define I40E_THREE_BIT_MASK     0x7
1066 #define I40E_FOUR_BIT_MASK      0xF
1067 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1068
1069 /* TX Descriptor */
1070 struct i40e_tx_desc {
1071         __le64 buffer_addr; /* Address of descriptor's data buf */
1072         __le64 cmd_type_offset_bsz;
1073 };
1074
1075 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1076 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1077
1078 enum i40e_tx_desc_dtype_value {
1079         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1080         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1081         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1082         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1083         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1084         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1085         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1086         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1087         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1088         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1089 };
1090
1091 #define I40E_TXD_QW1_CMD_SHIFT  4
1092 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1093
1094 enum i40e_tx_desc_cmd_bits {
1095         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1096         I40E_TX_DESC_CMD_RS                     = 0x0002,
1097         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1098         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1099         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1100         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1101         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1102         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1103         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1104         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1105         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1106         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1107         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1108         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1109         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1110         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1111         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1112         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1113 };
1114
1115 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1116 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1117                                          I40E_TXD_QW1_OFFSET_SHIFT)
1118
1119 enum i40e_tx_desc_length_fields {
1120         /* Note: These are predefined bit offsets */
1121         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1122         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1123         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1124 };
1125
1126 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1127 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1128 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1129 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1130
1131 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1132 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1133                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1134
1135 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1136 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1137
1138 /* Context descriptors */
1139 struct i40e_tx_context_desc {
1140         __le32 tunneling_params;
1141         __le16 l2tag2;
1142         __le16 rsvd;
1143         __le64 type_cmd_tso_mss;
1144 };
1145
1146 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1147 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1148
1149 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1150 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1151
1152 enum i40e_tx_ctx_desc_cmd_bits {
1153         I40E_TX_CTX_DESC_TSO            = 0x01,
1154         I40E_TX_CTX_DESC_TSYN           = 0x02,
1155         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1156         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1157         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1158         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1159         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1160         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1161         I40E_TX_CTX_DESC_SWPE           = 0x40
1162 };
1163
1164 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1165 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1166                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1167
1168 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1169 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1170                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1171
1172 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1173 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1174
1175 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1176 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1177                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1178
1179 enum i40e_tx_ctx_desc_eipt_offload {
1180         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1181         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1182         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1183         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1184 };
1185
1186 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1187 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1188                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1189
1190 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1191 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1192
1193 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1194 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1195
1196 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1197 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1198
1199 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1200
1201 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1202 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1203                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1204
1205 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1206 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1207                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1208
1209 #ifdef X722_SUPPORT
1210 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1211 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1212 #endif
1213 struct i40e_nop_desc {
1214         __le64 rsvd;
1215         __le64 dtype_cmd;
1216 };
1217
1218 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1219 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1220
1221 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1222 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1223
1224 enum i40e_tx_nop_desc_cmd_bits {
1225         /* Note: These are predefined bit offsets */
1226         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1227         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1228         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1229 };
1230
1231 struct i40e_filter_program_desc {
1232         __le32 qindex_flex_ptype_vsi;
1233         __le32 rsvd;
1234         __le32 dtype_cmd_cntindex;
1235         __le32 fd_id;
1236 };
1237 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1238 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1239                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1240 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1241 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1242                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1243 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1244 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1245                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1246
1247 /* Packet Classifier Types for filters */
1248 enum i40e_filter_pctype {
1249 #ifdef X722_SUPPORT
1250         /* Note: Values 0-28 are reserved for future use.
1251          * Value 29, 30, 32 are not supported on XL710 and X710.
1252          */
1253         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1254         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1255 #else
1256         /* Note: Values 0-30 are reserved for future use */
1257 #endif
1258         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1259 #ifdef X722_SUPPORT
1260         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1261 #else
1262         /* Note: Value 32 is reserved for future use */
1263 #endif
1264         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1265         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1266         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1267         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1268 #ifdef X722_SUPPORT
1269         /* Note: Values 37-38 are reserved for future use.
1270          * Value 39, 40, 42 are not supported on XL710 and X710.
1271          */
1272         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1273         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1274 #else
1275         /* Note: Values 37-40 are reserved for future use */
1276 #endif
1277         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1278 #ifdef X722_SUPPORT
1279         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1280 #endif
1281         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1282         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1283         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1284         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1285         /* Note: Value 47 is reserved for future use */
1286         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1287         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1288         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1289         /* Note: Values 51-62 are reserved for future use */
1290         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1291 };
1292
1293 enum i40e_filter_program_desc_dest {
1294         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1295         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1296         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1297 };
1298
1299 enum i40e_filter_program_desc_fd_status {
1300         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1301         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1302         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1303         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1304 };
1305
1306 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1307 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1308                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1309
1310 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1311 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1312
1313 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1314 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1315                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1316
1317 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1318 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1319
1320 enum i40e_filter_program_desc_pcmd {
1321         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1322         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1323 };
1324
1325 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1326 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1327
1328 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1329 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1330
1331 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1332                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1333 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1334                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1335 #ifdef X722_SUPPORT
1336
1337 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1338                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1339 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1340 #endif
1341
1342 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1343 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1344                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1345
1346 enum i40e_filter_type {
1347         I40E_FLOW_DIRECTOR_FLTR = 0,
1348         I40E_PE_QUAD_HASH_FLTR = 1,
1349         I40E_ETHERTYPE_FLTR,
1350         I40E_FCOE_CTX_FLTR,
1351         I40E_MAC_VLAN_FLTR,
1352         I40E_HASH_FLTR
1353 };
1354
1355 struct i40e_vsi_context {
1356         u16 seid;
1357         u16 uplink_seid;
1358         u16 vsi_number;
1359         u16 vsis_allocated;
1360         u16 vsis_unallocated;
1361         u16 flags;
1362         u8 pf_num;
1363         u8 vf_num;
1364         u8 connection_type;
1365         struct i40e_aqc_vsi_properties_data info;
1366 };
1367
1368 struct i40e_veb_context {
1369         u16 seid;
1370         u16 uplink_seid;
1371         u16 veb_number;
1372         u16 vebs_allocated;
1373         u16 vebs_unallocated;
1374         u16 flags;
1375         struct i40e_aqc_get_veb_parameters_completion info;
1376 };
1377
1378 /* Statistics collected by each port, VSI, VEB, and S-channel */
1379 struct i40e_eth_stats {
1380         u64 rx_bytes;                   /* gorc */
1381         u64 rx_unicast;                 /* uprc */
1382         u64 rx_multicast;               /* mprc */
1383         u64 rx_broadcast;               /* bprc */
1384         u64 rx_discards;                /* rdpc */
1385         u64 rx_unknown_protocol;        /* rupp */
1386         u64 tx_bytes;                   /* gotc */
1387         u64 tx_unicast;                 /* uptc */
1388         u64 tx_multicast;               /* mptc */
1389         u64 tx_broadcast;               /* bptc */
1390         u64 tx_discards;                /* tdpc */
1391         u64 tx_errors;                  /* tepc */
1392 };
1393
1394 /* Statistics collected per VEB per TC */
1395 struct i40e_veb_tc_stats {
1396         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1397         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1398         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1399         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1400 };
1401
1402 /* Statistics collected per function for FCoE */
1403 struct i40e_fcoe_stats {
1404         u64 rx_fcoe_packets;            /* fcoeprc */
1405         u64 rx_fcoe_dwords;             /* focedwrc */
1406         u64 rx_fcoe_dropped;            /* fcoerpdc */
1407         u64 tx_fcoe_packets;            /* fcoeptc */
1408         u64 tx_fcoe_dwords;             /* focedwtc */
1409         u64 fcoe_bad_fccrc;             /* fcoecrc */
1410         u64 fcoe_last_error;            /* fcoelast */
1411         u64 fcoe_ddp_count;             /* fcoeddpc */
1412 };
1413
1414 /* offset to per function FCoE statistics block */
1415 #define I40E_FCOE_VF_STAT_OFFSET        0
1416 #define I40E_FCOE_PF_STAT_OFFSET        128
1417 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1418
1419 /* Statistics collected by the MAC */
1420 struct i40e_hw_port_stats {
1421         /* eth stats collected by the port */
1422         struct i40e_eth_stats eth;
1423
1424         /* additional port specific stats */
1425         u64 tx_dropped_link_down;       /* tdold */
1426         u64 crc_errors;                 /* crcerrs */
1427         u64 illegal_bytes;              /* illerrc */
1428         u64 error_bytes;                /* errbc */
1429         u64 mac_local_faults;           /* mlfc */
1430         u64 mac_remote_faults;          /* mrfc */
1431         u64 rx_length_errors;           /* rlec */
1432         u64 link_xon_rx;                /* lxonrxc */
1433         u64 link_xoff_rx;               /* lxoffrxc */
1434         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1435         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1436         u64 link_xon_tx;                /* lxontxc */
1437         u64 link_xoff_tx;               /* lxofftxc */
1438         u64 priority_xon_tx[8];         /* pxontxc[8] */
1439         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1440         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1441         u64 rx_size_64;                 /* prc64 */
1442         u64 rx_size_127;                /* prc127 */
1443         u64 rx_size_255;                /* prc255 */
1444         u64 rx_size_511;                /* prc511 */
1445         u64 rx_size_1023;               /* prc1023 */
1446         u64 rx_size_1522;               /* prc1522 */
1447         u64 rx_size_big;                /* prc9522 */
1448         u64 rx_undersize;               /* ruc */
1449         u64 rx_fragments;               /* rfc */
1450         u64 rx_oversize;                /* roc */
1451         u64 rx_jabber;                  /* rjc */
1452         u64 tx_size_64;                 /* ptc64 */
1453         u64 tx_size_127;                /* ptc127 */
1454         u64 tx_size_255;                /* ptc255 */
1455         u64 tx_size_511;                /* ptc511 */
1456         u64 tx_size_1023;               /* ptc1023 */
1457         u64 tx_size_1522;               /* ptc1522 */
1458         u64 tx_size_big;                /* ptc9522 */
1459         u64 mac_short_packet_dropped;   /* mspdc */
1460         u64 checksum_error;             /* xec */
1461         /* flow director stats */
1462         u64 fd_atr_match;
1463         u64 fd_sb_match;
1464         u64 fd_atr_tunnel_match;
1465         u32 fd_atr_status;
1466         u32 fd_sb_status;
1467         /* EEE LPI */
1468         u32 tx_lpi_status;
1469         u32 rx_lpi_status;
1470         u64 tx_lpi_count;               /* etlpic */
1471         u64 rx_lpi_count;               /* erlpic */
1472 };
1473
1474 /* Checksum and Shadow RAM pointers */
1475 #define I40E_SR_NVM_CONTROL_WORD                0x00
1476 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1477 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1478 #define I40E_SR_OPTION_ROM_PTR                  0x05
1479 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1480 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1481 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1482 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1483 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1484 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1485 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1486 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1487 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1488 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1489 #define I40E_SR_PBA_FLAGS                       0x15
1490 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1491 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1492 #define I40E_NVM_OEM_VER_OFF                    0x83
1493 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1494 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1495 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1496 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1497 #define I40E_SR_NVM_MAP_VERSION                 0x29
1498 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1499 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1500 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1501 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1502 #define I40E_SR_VPD_PTR                         0x2F
1503 #define I40E_SR_PXE_SETUP_PTR                   0x30
1504 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1505 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1506 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1507 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1508 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1509 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1510 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1511 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1512 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1513 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1514 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1515 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1516 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1517 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1518 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1519 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1520 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1521 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1522
1523 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1524 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1525 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1526 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1527 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1528
1529 /* Shadow RAM related */
1530 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1531 #define I40E_SR_BUF_ALIGNMENT           4096
1532 #define I40E_SR_WORDS_IN_1KB            512
1533 /* Checksum should be calculated such that after adding all the words,
1534  * including the checksum word itself, the sum should be 0xBABA.
1535  */
1536 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1537
1538 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1539
1540 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1541
1542 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1543         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1544         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1545         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1546         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1547         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1548         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1549         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1550         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1551         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1552         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1553         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1554         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1555         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1556 };
1557
1558 /* FCoE DIF/DIX Context descriptor */
1559 struct i40e_fcoe_difdix_context_desc {
1560         __le64 flags_buff0_buff1_ref;
1561         __le64 difapp_msk_bias;
1562 };
1563
1564 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1565 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1566                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1567
1568 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1569         /* 2 BITS */
1570         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1571         /* 1 BIT  */
1572         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1573         /* 1 BIT  */
1574         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1575         /* 2 BITS */
1576         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1577         /* 2 BITS */
1578         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1579         /* 2 BITS */
1580         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1581         /* 2 BITS */
1582         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1583         /* 2 BITS */
1584         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1585         /* 2 BITS */
1586         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1587         /* 2 BITS */
1588         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1589         /* 2 BITS */
1590         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1591         /* 1 BIT  */
1592         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1593         /* 1 BIT  */
1594         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1595         /* 2 BITS */
1596         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1597         /* 2 BITS */
1598         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1599         /* 2 BITS */
1600         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1601         /* 2 BITS */
1602         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1603         /* 1 BIT  */
1604         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1605         /* 1 BIT  */
1606         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1607         /* 1 BIT */
1608         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1609         /* 1 BIT */
1610         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1611 };
1612
1613 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1614 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1615                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1616
1617 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1618 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1619                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1620
1621 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1622 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1623                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1624
1625 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1626 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1627                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1628
1629 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1630 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1631                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1632
1633 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1634 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1635                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1636
1637 /* FCoE DIF/DIX Buffers descriptor */
1638 struct i40e_fcoe_difdix_buffers_desc {
1639         __le64 buff_addr0;
1640         __le64 buff_addr1;
1641 };
1642
1643 /* FCoE DDP Context descriptor */
1644 struct i40e_fcoe_ddp_context_desc {
1645         __le64 rsvd;
1646         __le64 type_cmd_foff_lsize;
1647 };
1648
1649 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1650 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1651                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1652
1653 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1654 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1655                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1656
1657 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1658         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1659         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1660         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1661         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1662         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1663         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1664 };
1665
1666 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1667 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1668                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1669
1670 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1671 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1672                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1673
1674 /* FCoE DDP/DWO Queue Context descriptor */
1675 struct i40e_fcoe_queue_context_desc {
1676         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1677         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1678 };
1679
1680 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1681 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1682                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1683
1684 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1685 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1686                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1687
1688 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1689 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1690                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1691
1692 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1693 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1694                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1695
1696 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1697         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1698         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1699 };
1700
1701 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1702 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1703                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1704
1705 /* FCoE DDP/DWO Filter Context descriptor */
1706 struct i40e_fcoe_filter_context_desc {
1707         __le32 param;
1708         __le16 seqn;
1709
1710         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1711         __le16 rsvd_dmaindx;
1712
1713         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1714         __le64 flags_rsvd_lanq;
1715 };
1716
1717 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1718 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1719                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1720
1721 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1722         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1723         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1724         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1725         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1726         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1727         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1728 };
1729
1730 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1731 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1732                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1733
1734 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1735 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1736                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1737
1738 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1739 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1740                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1741
1742 enum i40e_switch_element_types {
1743         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1744         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1745         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1746         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1747         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1748         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1749         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1750         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1751         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1752 };
1753
1754 /* Supported EtherType filters */
1755 enum i40e_ether_type_index {
1756         I40E_ETHER_TYPE_1588            = 0,
1757         I40E_ETHER_TYPE_FIP             = 1,
1758         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1759         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1760         I40E_ETHER_TYPE_LLDP            = 4,
1761         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1762         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1763         I40E_ETHER_TYPE_QCN_CNM         = 7,
1764         I40E_ETHER_TYPE_8021X           = 8,
1765         I40E_ETHER_TYPE_ARP             = 9,
1766         I40E_ETHER_TYPE_RSV1            = 10,
1767         I40E_ETHER_TYPE_RSV2            = 11,
1768 };
1769
1770 /* Filter context base size is 1K */
1771 #define I40E_HASH_FILTER_BASE_SIZE      1024
1772 /* Supported Hash filter values */
1773 enum i40e_hash_filter_size {
1774         I40E_HASH_FILTER_SIZE_1K        = 0,
1775         I40E_HASH_FILTER_SIZE_2K        = 1,
1776         I40E_HASH_FILTER_SIZE_4K        = 2,
1777         I40E_HASH_FILTER_SIZE_8K        = 3,
1778         I40E_HASH_FILTER_SIZE_16K       = 4,
1779         I40E_HASH_FILTER_SIZE_32K       = 5,
1780         I40E_HASH_FILTER_SIZE_64K       = 6,
1781         I40E_HASH_FILTER_SIZE_128K      = 7,
1782         I40E_HASH_FILTER_SIZE_256K      = 8,
1783         I40E_HASH_FILTER_SIZE_512K      = 9,
1784         I40E_HASH_FILTER_SIZE_1M        = 10,
1785 };
1786
1787 /* DMA context base size is 0.5K */
1788 #define I40E_DMA_CNTX_BASE_SIZE         512
1789 /* Supported DMA context values */
1790 enum i40e_dma_cntx_size {
1791         I40E_DMA_CNTX_SIZE_512          = 0,
1792         I40E_DMA_CNTX_SIZE_1K           = 1,
1793         I40E_DMA_CNTX_SIZE_2K           = 2,
1794         I40E_DMA_CNTX_SIZE_4K           = 3,
1795         I40E_DMA_CNTX_SIZE_8K           = 4,
1796         I40E_DMA_CNTX_SIZE_16K          = 5,
1797         I40E_DMA_CNTX_SIZE_32K          = 6,
1798         I40E_DMA_CNTX_SIZE_64K          = 7,
1799         I40E_DMA_CNTX_SIZE_128K         = 8,
1800         I40E_DMA_CNTX_SIZE_256K         = 9,
1801 };
1802
1803 /* Supported Hash look up table (LUT) sizes */
1804 enum i40e_hash_lut_size {
1805         I40E_HASH_LUT_SIZE_128          = 0,
1806         I40E_HASH_LUT_SIZE_512          = 1,
1807 };
1808
1809 /* Structure to hold a per PF filter control settings */
1810 struct i40e_filter_control_settings {
1811         /* number of PE Quad Hash filter buckets */
1812         enum i40e_hash_filter_size pe_filt_num;
1813         /* number of PE Quad Hash contexts */
1814         enum i40e_dma_cntx_size pe_cntx_num;
1815         /* number of FCoE filter buckets */
1816         enum i40e_hash_filter_size fcoe_filt_num;
1817         /* number of FCoE DDP contexts */
1818         enum i40e_dma_cntx_size fcoe_cntx_num;
1819         /* size of the Hash LUT */
1820         enum i40e_hash_lut_size hash_lut_size;
1821         /* enable FDIR filters for PF and its VFs */
1822         bool enable_fdir;
1823         /* enable Ethertype filters for PF and its VFs */
1824         bool enable_ethtype;
1825         /* enable MAC/VLAN filters for PF and its VFs */
1826         bool enable_macvlan;
1827 };
1828
1829 /* Structure to hold device level control filter counts */
1830 struct i40e_control_filter_stats {
1831         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1832         u16 etype_used;       /* Used perfect EtherType filters */
1833         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1834         u16 etype_free;       /* Un-used perfect EtherType filters */
1835 };
1836
1837 enum i40e_reset_type {
1838         I40E_RESET_POR          = 0,
1839         I40E_RESET_CORER        = 1,
1840         I40E_RESET_GLOBR        = 2,
1841         I40E_RESET_EMPR         = 3,
1842 };
1843
1844 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1845 #define I40E_NVM_LLDP_CFG_PTR           0xD
1846 struct i40e_lldp_variables {
1847         u16 length;
1848         u16 adminstatus;
1849         u16 msgfasttx;
1850         u16 msgtxinterval;
1851         u16 txparams;
1852         u16 timers;
1853         u16 crc8;
1854 };
1855
1856 /* Offsets into Alternate Ram */
1857 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1858 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1859 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1860 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1861 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1862 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1863
1864 /* Alternate Ram Bandwidth Masks */
1865 #define I40E_ALT_BW_VALUE_MASK          0xFF
1866 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1867 #define I40E_ALT_BW_VALID_MASK          0x80000000
1868
1869 /* RSS Hash Table Size */
1870 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1871
1872 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1873 #define I40E_L3_SRC_SHIFT               47
1874 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1875 #define I40E_L3_V6_SRC_SHIFT            43
1876 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1877 #define I40E_L3_DST_SHIFT               35
1878 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1879 #define I40E_L3_V6_DST_SHIFT            35
1880 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1881 #define I40E_L4_SRC_SHIFT               34
1882 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1883 #define I40E_L4_DST_SHIFT               33
1884 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1885 #define I40E_VERIFY_TAG_SHIFT           31
1886 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1887
1888 #define I40E_FLEX_50_SHIFT              13
1889 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1890 #define I40E_FLEX_51_SHIFT              12
1891 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1892 #define I40E_FLEX_52_SHIFT              11
1893 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1894 #define I40E_FLEX_53_SHIFT              10
1895 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1896 #define I40E_FLEX_54_SHIFT              9
1897 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1898 #define I40E_FLEX_55_SHIFT              8
1899 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1900 #define I40E_FLEX_56_SHIFT              7
1901 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1902 #define I40E_FLEX_57_SHIFT              6
1903 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1904 #endif /* _I40E_TYPE_H_ */