drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef I40E_MASK
  53 /* I40E_MASK is a macro used on 32 bit registers */
  54 #define I40E_MASK(mask, shift) (mask << shift)
  55 #endif
  56
  57 #define I40E_MAX_PF                     16
  58 #define I40E_MAX_PF_VSI                 64
  59 #define I40E_MAX_PF_QP                  128
  60 #define I40E_MAX_VSI_QP                 16
  61 #define I40E_MAX_VF_VSI                 3
  62 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  63 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  64
  65 /* something less than 1 minute */
  66 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  67
  68 /* Max default timeout in ms, */
  69 #define I40E_MAX_NVM_TIMEOUT            18000
  70
  71 /* Check whether address is multicast. */
  72 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  73
  74 /* Check whether an address is broadcast. */
  75 #define I40E_IS_BROADCAST(address)      \
  76         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  77         (((u8 *)(address))[1] == ((u8)0xff)))
  78
  79 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  80 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  81
  82 /* forward declaration */
  83 struct i40e_hw;
  84 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  85
  86 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  87 /* Data type manipulation macros. */
  88 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  89 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  90
  91 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  92 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  93
  94 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  95 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
  96
  97 /* Number of Transmit Descriptors must be a multiple of 8. */
  98 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
  99 /* Number of Receive Descriptors must be a multiple of 32 if
 100  * the number of descriptors is greater than 32.
 101  */
 102 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 103
 104 #define I40E_DESC_UNUSED(R)     \
 105         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 106         (R)->next_to_clean - (R)->next_to_use - 1)
 107
 108 /* bitfields for Tx queue mapping in QTX_CTL */
 109 #define I40E_QTX_CTL_VF_QUEUE   0x0
 110 #define I40E_QTX_CTL_VM_QUEUE   0x1
 111 #define I40E_QTX_CTL_PF_QUEUE   0x2
 112
 113 /* debug masks - set these bits in hw->debug_mask to control output */
 114 enum i40e_debug_mask {
 115         I40E_DEBUG_INIT                 = 0x00000001,
 116         I40E_DEBUG_RELEASE              = 0x00000002,
 117
 118         I40E_DEBUG_LINK                 = 0x00000010,
 119         I40E_DEBUG_PHY                  = 0x00000020,
 120         I40E_DEBUG_HMC                  = 0x00000040,
 121         I40E_DEBUG_NVM                  = 0x00000080,
 122         I40E_DEBUG_LAN                  = 0x00000100,
 123         I40E_DEBUG_FLOW                 = 0x00000200,
 124         I40E_DEBUG_DCB                  = 0x00000400,
 125         I40E_DEBUG_DIAG                 = 0x00000800,
 126         I40E_DEBUG_FD                   = 0x00001000,
 127
 128         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 129         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 130         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 131         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 132         I40E_DEBUG_AQ                   = 0x0F000000,
 133
 134         I40E_DEBUG_USER                 = 0xF0000000,
 135
 136         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 137 };
 138
 139 /* PCI Bus Info */
 140 #define I40E_PCI_LINK_STATUS            0xB2
 141 #define I40E_PCI_LINK_WIDTH             0x3F0
 142 #define I40E_PCI_LINK_WIDTH_1           0x10
 143 #define I40E_PCI_LINK_WIDTH_2           0x20
 144 #define I40E_PCI_LINK_WIDTH_4           0x40
 145 #define I40E_PCI_LINK_WIDTH_8           0x80
 146 #define I40E_PCI_LINK_SPEED             0xF
 147 #define I40E_PCI_LINK_SPEED_2500        0x1
 148 #define I40E_PCI_LINK_SPEED_5000        0x2
 149 #define I40E_PCI_LINK_SPEED_8000        0x3
 150
 151 /* Memory types */
 152 enum i40e_memset_type {
 153         I40E_NONDMA_MEM = 0,
 154         I40E_DMA_MEM
 155 };
 156
 157 /* Memcpy types */
 158 enum i40e_memcpy_type {
 159         I40E_NONDMA_TO_NONDMA = 0,
 160         I40E_NONDMA_TO_DMA,
 161         I40E_DMA_TO_DMA,
 162         I40E_DMA_TO_NONDMA
 163 };
 164
 165 /* These are structs for managing the hardware information and the operations.
 166  * The structures of function pointers are filled out at init time when we
 167  * know for sure exactly which hardware we're working with.  This gives us the
 168  * flexibility of using the same main driver code but adapting to slightly
 169  * different hardware needs as new parts are developed.  For this architecture,
 170  * the Firmware and AdminQ are intended to insulate the driver from most of the
 171  * future changes, but these structures will also do part of the job.
 172  */
 173 enum i40e_mac_type {
 174         I40E_MAC_UNKNOWN = 0,
 175         I40E_MAC_X710,
 176         I40E_MAC_XL710,
 177         I40E_MAC_VF,
 178         I40E_MAC_GENERIC,
 179 };
 180
 181 enum i40e_media_type {
 182         I40E_MEDIA_TYPE_UNKNOWN = 0,
 183         I40E_MEDIA_TYPE_FIBER,
 184         I40E_MEDIA_TYPE_BASET,
 185         I40E_MEDIA_TYPE_BACKPLANE,
 186         I40E_MEDIA_TYPE_CX4,
 187         I40E_MEDIA_TYPE_DA,
 188         I40E_MEDIA_TYPE_VIRTUAL
 189 };
 190
 191 enum i40e_fc_mode {
 192         I40E_FC_NONE = 0,
 193         I40E_FC_RX_PAUSE,
 194         I40E_FC_TX_PAUSE,
 195         I40E_FC_FULL,
 196         I40E_FC_PFC,
 197         I40E_FC_DEFAULT
 198 };
 199
 200 enum i40e_set_fc_aq_failures {
 201         I40E_SET_FC_AQ_FAIL_NONE = 0,
 202         I40E_SET_FC_AQ_FAIL_GET = 1,
 203         I40E_SET_FC_AQ_FAIL_SET = 2,
 204         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 205         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 206 };
 207
 208 enum i40e_vsi_type {
 209         I40E_VSI_MAIN = 0,
 210         I40E_VSI_VMDQ1,
 211         I40E_VSI_VMDQ2,
 212         I40E_VSI_CTRL,
 213         I40E_VSI_FCOE,
 214         I40E_VSI_MIRROR,
 215         I40E_VSI_SRIOV,
 216         I40E_VSI_FDIR,
 217         I40E_VSI_TYPE_UNKNOWN
 218 };
 219
 220 enum i40e_queue_type {
 221         I40E_QUEUE_TYPE_RX = 0,
 222         I40E_QUEUE_TYPE_TX,
 223         I40E_QUEUE_TYPE_PE_CEQ,
 224         I40E_QUEUE_TYPE_UNKNOWN
 225 };
 226
 227 struct i40e_link_status {
 228         enum i40e_aq_phy_type phy_type;
 229         enum i40e_aq_link_speed link_speed;
 230         u8 link_info;
 231         u8 an_info;
 232         u8 ext_info;
 233         u8 loopback;
 234         /* is Link Status Event notification to SW enabled */
 235         bool lse_enable;
 236         u16 max_frame_size;
 237         bool crc_enable;
 238         u8 pacing;
 239         u8 requested_speeds;
 240         u8 module_type[3];
 241         /* 1st byte: module identifier */
 242 #define I40E_MODULE_TYPE_SFP            0x03
 243 #define I40E_MODULE_TYPE_QSFP           0x0D
 244         /* 2nd byte: ethernet compliance codes for 10/40G */
 245 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 246 #define I40E_MODULE_TYPE_40G_LR4        0x02
 247 #define I40E_MODULE_TYPE_40G_SR4        0x04
 248 #define I40E_MODULE_TYPE_40G_CR4        0x08
 249 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 250 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 251 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 252 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 253         /* 3rd byte: ethernet compliance codes for 1G */
 254 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 255 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 256 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 257 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 258 };
 259
 260 struct i40e_phy_info {
 261         struct i40e_link_status link_info;
 262         struct i40e_link_status link_info_old;
 263         u32 autoneg_advertised;
 264         u32 phy_id;
 265         u32 module_type;
 266         bool get_link_info;
 267         enum i40e_media_type media_type;
 268 };
 269
 270 #define I40E_HW_CAP_MAX_GPIO                    30
 271 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 272 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 273
 274 /* Capabilities of a PF or a VF or the whole device */
 275 struct i40e_hw_capabilities {
 276         u32  switch_mode;
 277 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 278 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 279 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 280
 281         u32  management_mode;
 282         u32  npar_enable;
 283         u32  os2bmc;
 284         u32  valid_functions;
 285         bool sr_iov_1_1;
 286         bool vmdq;
 287         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 288         bool evb_802_1_qbh; /* Bridge Port Extension */
 289         bool dcb;
 290         bool fcoe;
 291         bool iscsi; /* Indicates iSCSI enabled */
 292         bool mfp_mode_1;
 293         bool mgmt_cem;
 294         bool ieee_1588;
 295         bool iwarp;
 296         bool fd;
 297         u32 fd_filters_guaranteed;
 298         u32 fd_filters_best_effort;
 299         bool rss;
 300         u32 rss_table_size;
 301         u32 rss_table_entry_width;
 302         bool led[I40E_HW_CAP_MAX_GPIO];
 303         bool sdp[I40E_HW_CAP_MAX_GPIO];
 304         u32 nvm_image_type;
 305         u32 num_flow_director_filters;
 306         u32 num_vfs;
 307         u32 vf_base_id;
 308         u32 num_vsis;
 309         u32 num_rx_qp;
 310         u32 num_tx_qp;
 311         u32 base_queue;
 312         u32 num_msix_vectors;
 313         u32 num_msix_vectors_vf;
 314         u32 led_pin_num;
 315         u32 sdp_pin_num;
 316         u32 mdio_port_num;
 317         u32 mdio_port_mode;
 318         u8 rx_buf_chain_len;
 319         u32 enabled_tcmap;
 320         u32 maxtc;
 321 };
 322
 323 struct i40e_mac_info {
 324         enum i40e_mac_type type;
 325         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 326         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 327         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 328         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 329         u16 max_fcoeq;
 330 };
 331
 332 enum i40e_aq_resources_ids {
 333         I40E_NVM_RESOURCE_ID = 1
 334 };
 335
 336 enum i40e_aq_resource_access_type {
 337         I40E_RESOURCE_READ = 1,
 338         I40E_RESOURCE_WRITE
 339 };
 340
 341 struct i40e_nvm_info {
 342         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 343         u32 timeout;              /* [ms] */
 344         u16 sr_size;              /* Shadow RAM size in words */
 345         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 346         u16 version;              /* NVM package version */
 347         u32 eetrack;              /* NVM data version */
 348 };
 349
 350 /* definitions used in NVM update support */
 351
 352 enum i40e_nvmupd_cmd {
 353         I40E_NVMUPD_INVALID,
 354         I40E_NVMUPD_READ_CON,
 355         I40E_NVMUPD_READ_SNT,
 356         I40E_NVMUPD_READ_LCB,
 357         I40E_NVMUPD_READ_SA,
 358         I40E_NVMUPD_WRITE_ERA,
 359         I40E_NVMUPD_WRITE_CON,
 360         I40E_NVMUPD_WRITE_SNT,
 361         I40E_NVMUPD_WRITE_LCB,
 362         I40E_NVMUPD_WRITE_SA,
 363         I40E_NVMUPD_CSUM_CON,
 364         I40E_NVMUPD_CSUM_SA,
 365         I40E_NVMUPD_CSUM_LCB,
 366 };
 367
 368 enum i40e_nvmupd_state {
 369         I40E_NVMUPD_STATE_INIT,
 370         I40E_NVMUPD_STATE_READING,
 371         I40E_NVMUPD_STATE_WRITING,
 372         I40E_NVMUPD_STATE_INIT_WAIT,
 373         I40E_NVMUPD_STATE_WRITE_WAIT,
 374 };
 375
 376 /* nvm_access definition and its masks/shifts need to be accessible to
 377  * application, core driver, and shared code.  Where is the right file?
 378  */
 379 #define I40E_NVM_READ   0xB
 380 #define I40E_NVM_WRITE  0xC
 381
 382 #define I40E_NVM_MOD_PNT_MASK 0xFF
 383
 384 #define I40E_NVM_TRANS_SHIFT    8
 385 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 386 #define I40E_NVM_CON            0x0
 387 #define I40E_NVM_SNT            0x1
 388 #define I40E_NVM_LCB            0x2
 389 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 390 #define I40E_NVM_ERA            0x4
 391 #define I40E_NVM_CSUM           0x8
 392
 393 #define I40E_NVM_ADAPT_SHIFT    16
 394 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 395
 396 #define I40E_NVMUPD_MAX_DATA    4096
 397 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 398
 399 struct i40e_nvm_access {
 400         u32 command;
 401         u32 config;
 402         u32 offset;     /* in bytes */
 403         u32 data_size;  /* in bytes */
 404         u8 data[1];
 405 };
 406
 407 /* PCI bus types */
 408 enum i40e_bus_type {
 409         i40e_bus_type_unknown = 0,
 410         i40e_bus_type_pci,
 411         i40e_bus_type_pcix,
 412         i40e_bus_type_pci_express,
 413         i40e_bus_type_reserved
 414 };
 415
 416 /* PCI bus speeds */
 417 enum i40e_bus_speed {
 418         i40e_bus_speed_unknown  = 0,
 419         i40e_bus_speed_33       = 33,
 420         i40e_bus_speed_66       = 66,
 421         i40e_bus_speed_100      = 100,
 422         i40e_bus_speed_120      = 120,
 423         i40e_bus_speed_133      = 133,
 424         i40e_bus_speed_2500     = 2500,
 425         i40e_bus_speed_5000     = 5000,
 426         i40e_bus_speed_8000     = 8000,
 427         i40e_bus_speed_reserved
 428 };
 429
 430 /* PCI bus widths */
 431 enum i40e_bus_width {
 432         i40e_bus_width_unknown  = 0,
 433         i40e_bus_width_pcie_x1  = 1,
 434         i40e_bus_width_pcie_x2  = 2,
 435         i40e_bus_width_pcie_x4  = 4,
 436         i40e_bus_width_pcie_x8  = 8,
 437         i40e_bus_width_32       = 32,
 438         i40e_bus_width_64       = 64,
 439         i40e_bus_width_reserved
 440 };
 441
 442 /* Bus parameters */
 443 struct i40e_bus_info {
 444         enum i40e_bus_speed speed;
 445         enum i40e_bus_width width;
 446         enum i40e_bus_type type;
 447
 448         u16 func;
 449         u16 device;
 450         u16 lan_id;
 451 };
 452
 453 /* Flow control (FC) parameters */
 454 struct i40e_fc_info {
 455         enum i40e_fc_mode current_mode; /* FC mode in effect */
 456         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 457 };
 458
 459 #define I40E_MAX_TRAFFIC_CLASS          8
 460 #define I40E_MAX_USER_PRIORITY          8
 461 #define I40E_DCBX_MAX_APPS              32
 462 #define I40E_LLDPDU_SIZE                1500
 463 #define I40E_TLV_STATUS_OPER            0x1
 464 #define I40E_TLV_STATUS_SYNC            0x2
 465 #define I40E_TLV_STATUS_ERR             0x4
 466 #define I40E_CEE_OPER_MAX_APPS          3
 467 #define I40E_APP_PROTOID_FCOE           0x8906
 468 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 469 #define I40E_APP_PROTOID_FIP            0x8914
 470 #define I40E_APP_SEL_ETHTYPE            0x1
 471 #define I40E_APP_SEL_TCPIP              0x2
 472
 473 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 474 struct i40e_dcb_ets_config {
 475         u8 willing;
 476         u8 cbs;
 477         u8 maxtcs;
 478         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 479         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 480         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 481 };
 482
 483 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 484 struct i40e_dcb_pfc_config {
 485         u8 willing;
 486         u8 mbc;
 487         u8 pfccap;
 488         u8 pfcenable;
 489 };
 490
 491 /* CEE or IEEE 802.1Qaz Application Priority data */
 492 struct i40e_dcb_app_priority_table {
 493         u8  priority;
 494         u8  selector;
 495         u16 protocolid;
 496 };
 497
 498 struct i40e_dcbx_config {
 499         u8  dcbx_mode;
 500 #define I40E_DCBX_MODE_CEE      0x1
 501 #define I40E_DCBX_MODE_IEEE     0x2
 502         u32 numapps;
 503         struct i40e_dcb_ets_config etscfg;
 504         struct i40e_dcb_ets_config etsrec;
 505         struct i40e_dcb_pfc_config pfc;
 506         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 507 };
 508
 509 /* Port hardware description */
 510 struct i40e_hw {
 511         u8 *hw_addr;
 512         void *back;
 513
 514         /* subsystem structs */
 515         struct i40e_phy_info phy;
 516         struct i40e_mac_info mac;
 517         struct i40e_bus_info bus;
 518         struct i40e_nvm_info nvm;
 519         struct i40e_fc_info fc;
 520
 521         /* pci info */
 522         u16 device_id;
 523         u16 vendor_id;
 524         u16 subsystem_device_id;
 525         u16 subsystem_vendor_id;
 526         u8 revision_id;
 527         u8 port;
 528         bool adapter_stopped;
 529
 530         /* capabilities for entire device and PCI func */
 531         struct i40e_hw_capabilities dev_caps;
 532         struct i40e_hw_capabilities func_caps;
 533
 534         /* Flow Director shared filter space */
 535         u16 fdir_shared_filter_count;
 536
 537         /* device profile info */
 538         u8  pf_id;
 539         u16 main_vsi_seid;
 540
 541         /* for multi-function MACs */
 542         u16 partition_id;
 543         u16 num_partitions;
 544         u16 num_ports;
 545
 546         /* Closest numa node to the device */
 547         u16 numa_node;
 548
 549         /* Admin Queue info */
 550         struct i40e_adminq_info aq;
 551
 552         /* state of nvm update process */
 553         enum i40e_nvmupd_state nvmupd_state;
 554         struct i40e_aq_desc nvm_wb_desc;
 555
 556         /* HMC info */
 557         struct i40e_hmc_info hmc; /* HMC info struct */
 558
 559         /* LLDP/DCBX Status */
 560         u16 dcbx_status;
 561
 562         /* DCBX info */
 563         struct i40e_dcbx_config local_dcbx_config;
 564         struct i40e_dcbx_config remote_dcbx_config;
 565
 566         /* debug mask */
 567         u32 debug_mask;
 568 #ifndef I40E_NDIS_SUPPORT
 569         char err_str[16];
 570 #endif /* I40E_NDIS_SUPPORT */
 571 };
 572
 573 static inline bool i40e_is_vf(struct i40e_hw *hw)
 574 {
 575         return hw->mac.type == I40E_MAC_VF;
 576 }
 577
 578 struct i40e_driver_version {
 579         u8 major_version;
 580         u8 minor_version;
 581         u8 build_version;
 582         u8 subbuild_version;
 583         u8 driver_string[32];
 584 };
 585
 586 /* RX Descriptors */
 587 union i40e_16byte_rx_desc {
 588         struct {
 589                 __le64 pkt_addr; /* Packet buffer address */
 590                 __le64 hdr_addr; /* Header buffer address */
 591         } read;
 592         struct {
 593                 struct {
 594                         struct {
 595                                 union {
 596                                         __le16 mirroring_status;
 597                                         __le16 fcoe_ctx_id;
 598                                 } mirr_fcoe;
 599                                 __le16 l2tag1;
 600                         } lo_dword;
 601                         union {
 602                                 __le32 rss; /* RSS Hash */
 603                                 __le32 fd_id; /* Flow director filter id */
 604                                 __le32 fcoe_param; /* FCoE DDP Context id */
 605                         } hi_dword;
 606                 } qword0;
 607                 struct {
 608                         /* ext status/error/pktype/length */
 609                         __le64 status_error_len;
 610                 } qword1;
 611         } wb;  /* writeback */
 612 };
 613
 614 union i40e_32byte_rx_desc {
 615         struct {
 616                 __le64  pkt_addr; /* Packet buffer address */
 617                 __le64  hdr_addr; /* Header buffer address */
 618                         /* bit 0 of hdr_buffer_addr is DD bit */
 619                 __le64  rsvd1;
 620                 __le64  rsvd2;
 621         } read;
 622         struct {
 623                 struct {
 624                         struct {
 625                                 union {
 626                                         __le16 mirroring_status;
 627                                         __le16 fcoe_ctx_id;
 628                                 } mirr_fcoe;
 629                                 __le16 l2tag1;
 630                         } lo_dword;
 631                         union {
 632                                 __le32 rss; /* RSS Hash */
 633                                 __le32 fcoe_param; /* FCoE DDP Context id */
 634                                 /* Flow director filter id in case of
 635                                  * Programming status desc WB
 636                                  */
 637                                 __le32 fd_id;
 638                         } hi_dword;
 639                 } qword0;
 640                 struct {
 641                         /* status/error/pktype/length */
 642                         __le64 status_error_len;
 643                 } qword1;
 644                 struct {
 645                         __le16 ext_status; /* extended status */
 646                         __le16 rsvd;
 647                         __le16 l2tag2_1;
 648                         __le16 l2tag2_2;
 649                 } qword2;
 650                 struct {
 651                         union {
 652                                 __le32 flex_bytes_lo;
 653                                 __le32 pe_status;
 654                         } lo_dword;
 655                         union {
 656                                 __le32 flex_bytes_hi;
 657                                 __le32 fd_id;
 658                         } hi_dword;
 659                 } qword3;
 660         } wb;  /* writeback */
 661 };
 662
 663 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 664 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 665                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 666 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 667 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 668                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 669
 670 enum i40e_rx_desc_status_bits {
 671         /* Note: These are predefined bit offsets */
 672         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 673         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 674         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 675         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 676         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 677         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 678         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 679         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 680
 681         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 682         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 683         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 684         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 685         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 686         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 687         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 688         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 689 };
 690
 691 #define I40E_RXD_QW1_STATUS_SHIFT       0
 692 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
 693                                          I40E_RXD_QW1_STATUS_SHIFT)
 694
 695 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 696 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 697                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 698
 699 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 700 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 701                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 702
 703 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 704 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 705                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 706
 707 enum i40e_rx_desc_fltstat_values {
 708         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 709         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 710         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 711         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 712 };
 713
 714 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 715 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 716 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 717 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 718
 719 #define I40E_RXD_QW1_ERROR_SHIFT        19
 720 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 721
 722 enum i40e_rx_desc_error_bits {
 723         /* Note: These are predefined bit offsets */
 724         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 725         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 726         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 727         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 728         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 729         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 730         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 731         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 732         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 733 };
 734
 735 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 736         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 737         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 738         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 739         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 740         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 741 };
 742
 743 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 744 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 745
 746 /* Packet type non-ip values */
 747 enum i40e_rx_l2_ptype {
 748         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 749         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 750         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 751         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 752         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 753         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 754         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 755         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 756         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 757         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 758         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 759         I40E_RX_PTYPE_L2_ARP                            = 11,
 760         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 761         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 762         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 763         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 764         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 765         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 766         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 767         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 768         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 769         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 770         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 771         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 772         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 773         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 774 };
 775
 776 struct i40e_rx_ptype_decoded {
 777         u32 ptype:8;
 778         u32 known:1;
 779         u32 outer_ip:1;
 780         u32 outer_ip_ver:1;
 781         u32 outer_frag:1;
 782         u32 tunnel_type:3;
 783         u32 tunnel_end_prot:2;
 784         u32 tunnel_end_frag:1;
 785         u32 inner_prot:4;
 786         u32 payload_layer:3;
 787 };
 788
 789 enum i40e_rx_ptype_outer_ip {
 790         I40E_RX_PTYPE_OUTER_L2  = 0,
 791         I40E_RX_PTYPE_OUTER_IP  = 1
 792 };
 793
 794 enum i40e_rx_ptype_outer_ip_ver {
 795         I40E_RX_PTYPE_OUTER_NONE        = 0,
 796         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 797         I40E_RX_PTYPE_OUTER_IPV6        = 1
 798 };
 799
 800 enum i40e_rx_ptype_outer_fragmented {
 801         I40E_RX_PTYPE_NOT_FRAG  = 0,
 802         I40E_RX_PTYPE_FRAG      = 1
 803 };
 804
 805 enum i40e_rx_ptype_tunnel_type {
 806         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 807         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 808         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 809         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 810         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 811 };
 812
 813 enum i40e_rx_ptype_tunnel_end_prot {
 814         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 815         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 816         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 817 };
 818
 819 enum i40e_rx_ptype_inner_prot {
 820         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 821         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 822         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 823         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 824         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 825         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 826 };
 827
 828 enum i40e_rx_ptype_payload_layer {
 829         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 830         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 831         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 832         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 833 };
 834
 835 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 836 #define I40E_RX_PTYPE_SHIFT             56
 837
 838 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 839 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 840                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 841
 842 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 843 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 844                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 845
 846 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 847 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 848                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 849
 850 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 851 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 852
 853 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 854 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 855                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 856
 857 enum i40e_rx_desc_ext_status_bits {
 858         /* Note: These are predefined bit offsets */
 859         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 860         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 861         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 862         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 863         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 864         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 865         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 866 };
 867
 868 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 869 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 870
 871 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 872 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 873
 874 enum i40e_rx_desc_pe_status_bits {
 875         /* Note: These are predefined bit offsets */
 876         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 877         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 878         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 879         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 880         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 881         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 882         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 883         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 884         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 885 };
 886
 887 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 888 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 889
 890 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 891 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 892                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 893
 894 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 895 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 896                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 897
 898 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 899 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 900                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 901
 902 enum i40e_rx_prog_status_desc_status_bits {
 903         /* Note: These are predefined bit offsets */
 904         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 905         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 906 };
 907
 908 enum i40e_rx_prog_status_desc_prog_id_masks {
 909         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 910         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 911         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 912 };
 913
 914 enum i40e_rx_prog_status_desc_error_bits {
 915         /* Note: These are predefined bit offsets */
 916         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 917         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 918         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 919         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 920 };
 921
 922 #define I40E_TWO_BIT_MASK       0x3
 923 #define I40E_THREE_BIT_MASK     0x7
 924 #define I40E_FOUR_BIT_MASK      0xF
 925 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
 926
 927 /* TX Descriptor */
 928 struct i40e_tx_desc {
 929         __le64 buffer_addr; /* Address of descriptor's data buf */
 930         __le64 cmd_type_offset_bsz;
 931 };
 932
 933 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 934 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 935
 936 enum i40e_tx_desc_dtype_value {
 937         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 938         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 939         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 940         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 941         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 942         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 943         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 944         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 945         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 946         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 947 };
 948
 949 #define I40E_TXD_QW1_CMD_SHIFT  4
 950 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 951
 952 enum i40e_tx_desc_cmd_bits {
 953         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 954         I40E_TX_DESC_CMD_RS                     = 0x0002,
 955         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 956         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 957         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 958         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 959         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 960         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 961         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 962         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 963         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 964         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 965         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 966         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 967         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 968         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 969         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 970         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 971 };
 972
 973 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 974 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 975                                          I40E_TXD_QW1_OFFSET_SHIFT)
 976
 977 enum i40e_tx_desc_length_fields {
 978         /* Note: These are predefined bit offsets */
 979         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 980         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 981         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 982 };
 983
 984 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
 985 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
 986 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 987 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 988
 989 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 990 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 991                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 992
 993 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 994 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 995
 996 /* Context descriptors */
 997 struct i40e_tx_context_desc {
 998         __le32 tunneling_params;
 999         __le16 l2tag2;
1000         __le16 rsvd;
1001         __le64 type_cmd_tso_mss;
1002 };
1003
1004 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1005 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1006
1007 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1008 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1009
1010 enum i40e_tx_ctx_desc_cmd_bits {
1011         I40E_TX_CTX_DESC_TSO            = 0x01,
1012         I40E_TX_CTX_DESC_TSYN           = 0x02,
1013         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1014         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1015         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1016         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1017         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1018         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1019         I40E_TX_CTX_DESC_SWPE           = 0x40
1020 };
1021
1022 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1023 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1024                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1025
1026 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1027 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1028                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1029
1030 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1031 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1032
1033 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1034 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1035                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1036
1037 enum i40e_tx_ctx_desc_eipt_offload {
1038         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1039         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1040         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1041         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1042 };
1043
1044 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1045 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1046                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1047
1048 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1049 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1050
1051 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1052 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1053
1054 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1055 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
1056                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1057
1058 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1059
1060 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1061 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1062                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1063
1064 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1065 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1066                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1067
1068 struct i40e_nop_desc {
1069         __le64 rsvd;
1070         __le64 dtype_cmd;
1071 };
1072
1073 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1074 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1075
1076 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1077 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1078
1079 enum i40e_tx_nop_desc_cmd_bits {
1080         /* Note: These are predefined bit offsets */
1081         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1082         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1083         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1084 };
1085
1086 struct i40e_filter_program_desc {
1087         __le32 qindex_flex_ptype_vsi;
1088         __le32 rsvd;
1089         __le32 dtype_cmd_cntindex;
1090         __le32 fd_id;
1091 };
1092 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1093 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1094                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1095 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1096 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1097                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1098 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1099 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1100                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1101
1102 /* Packet Classifier Types for filters */
1103 enum i40e_filter_pctype {
1104         /* Note: Values 0-30 are reserved for future use */
1105         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1106         /* Note: Value 32 is reserved for future use */
1107         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1108         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1109         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1110         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1111         /* Note: Values 37-40 are reserved for future use */
1112         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1113         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1114         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1115         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1116         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1117         /* Note: Value 47 is reserved for future use */
1118         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1119         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1120         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1121         /* Note: Values 51-62 are reserved for future use */
1122         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1123 };
1124
1125 enum i40e_filter_program_desc_dest {
1126         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1127         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1128         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1129 };
1130
1131 enum i40e_filter_program_desc_fd_status {
1132         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1133         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1134         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1135         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1136 };
1137
1138 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1139 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1140                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1141
1142 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1143 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1144
1145 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1146 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1147                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1148
1149 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1150 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1151
1152 enum i40e_filter_program_desc_pcmd {
1153         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1154         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1155 };
1156
1157 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1158 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1159
1160 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1161 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
1162                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1163
1164 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1165                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1166 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1167                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1168
1169 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1170 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1171                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1172
1173 enum i40e_filter_type {
1174         I40E_FLOW_DIRECTOR_FLTR = 0,
1175         I40E_PE_QUAD_HASH_FLTR = 1,
1176         I40E_ETHERTYPE_FLTR,
1177         I40E_FCOE_CTX_FLTR,
1178         I40E_MAC_VLAN_FLTR,
1179         I40E_HASH_FLTR
1180 };
1181
1182 struct i40e_vsi_context {
1183         u16 seid;
1184         u16 uplink_seid;
1185         u16 vsi_number;
1186         u16 vsis_allocated;
1187         u16 vsis_unallocated;
1188         u16 flags;
1189         u8 pf_num;
1190         u8 vf_num;
1191         u8 connection_type;
1192         struct i40e_aqc_vsi_properties_data info;
1193 };
1194
1195 struct i40e_veb_context {
1196         u16 seid;
1197         u16 uplink_seid;
1198         u16 veb_number;
1199         u16 vebs_allocated;
1200         u16 vebs_unallocated;
1201         u16 flags;
1202         struct i40e_aqc_get_veb_parameters_completion info;
1203 };
1204
1205 /* Statistics collected by each port, VSI, VEB, and S-channel */
1206 struct i40e_eth_stats {
1207         u64 rx_bytes;                   /* gorc */
1208         u64 rx_unicast;                 /* uprc */
1209         u64 rx_multicast;               /* mprc */
1210         u64 rx_broadcast;               /* bprc */
1211         u64 rx_discards;                /* rdpc */
1212         u64 rx_unknown_protocol;        /* rupp */
1213         u64 tx_bytes;                   /* gotc */
1214         u64 tx_unicast;                 /* uptc */
1215         u64 tx_multicast;               /* mptc */
1216         u64 tx_broadcast;               /* bptc */
1217         u64 tx_discards;                /* tdpc */
1218         u64 tx_errors;                  /* tepc */
1219 };
1220
1221 /* Statistics collected per VEB per TC */
1222 struct i40e_veb_tc_stats {
1223         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1224         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1225         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1226         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1227 };
1228
1229 /* Statistics collected by the MAC */
1230 struct i40e_hw_port_stats {
1231         /* eth stats collected by the port */
1232         struct i40e_eth_stats eth;
1233
1234         /* additional port specific stats */
1235         u64 tx_dropped_link_down;       /* tdold */
1236         u64 crc_errors;                 /* crcerrs */
1237         u64 illegal_bytes;              /* illerrc */
1238         u64 error_bytes;                /* errbc */
1239         u64 mac_local_faults;           /* mlfc */
1240         u64 mac_remote_faults;          /* mrfc */
1241         u64 rx_length_errors;           /* rlec */
1242         u64 link_xon_rx;                /* lxonrxc */
1243         u64 link_xoff_rx;               /* lxoffrxc */
1244         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1245         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1246         u64 link_xon_tx;                /* lxontxc */
1247         u64 link_xoff_tx;               /* lxofftxc */
1248         u64 priority_xon_tx[8];         /* pxontxc[8] */
1249         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1250         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1251         u64 rx_size_64;                 /* prc64 */
1252         u64 rx_size_127;                /* prc127 */
1253         u64 rx_size_255;                /* prc255 */
1254         u64 rx_size_511;                /* prc511 */
1255         u64 rx_size_1023;               /* prc1023 */
1256         u64 rx_size_1522;               /* prc1522 */
1257         u64 rx_size_big;                /* prc9522 */
1258         u64 rx_undersize;               /* ruc */
1259         u64 rx_fragments;               /* rfc */
1260         u64 rx_oversize;                /* roc */
1261         u64 rx_jabber;                  /* rjc */
1262         u64 tx_size_64;                 /* ptc64 */
1263         u64 tx_size_127;                /* ptc127 */
1264         u64 tx_size_255;                /* ptc255 */
1265         u64 tx_size_511;                /* ptc511 */
1266         u64 tx_size_1023;               /* ptc1023 */
1267         u64 tx_size_1522;               /* ptc1522 */
1268         u64 tx_size_big;                /* ptc9522 */
1269         u64 mac_short_packet_dropped;   /* mspdc */
1270         u64 checksum_error;             /* xec */
1271         /* flow director stats */
1272         u64 fd_atr_match;
1273         u64 fd_sb_match;
1274         /* EEE LPI */
1275         u32 tx_lpi_status;
1276         u32 rx_lpi_status;
1277         u64 tx_lpi_count;               /* etlpic */
1278         u64 rx_lpi_count;               /* erlpic */
1279 };
1280
1281 /* Checksum and Shadow RAM pointers */
1282 #define I40E_SR_NVM_CONTROL_WORD                0x00
1283 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1284 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1285 #define I40E_SR_OPTION_ROM_PTR                  0x05
1286 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1287 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1288 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1289 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1290 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1291 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1292 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1293 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1294 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1295 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1296 #define I40E_SR_PBA_FLAGS                       0x15
1297 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1298 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1299 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1300 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1301 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1302 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1303 #define I40E_SR_NVM_MAP_VERSION                 0x29
1304 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1305 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1306 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1307 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1308 #define I40E_SR_VPD_PTR                         0x2F
1309 #define I40E_SR_PXE_SETUP_PTR                   0x30
1310 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1311 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1312 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1313 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1314 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1315 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1316 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1317 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1318 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1319 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1320 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1321 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1322 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1323 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1324 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1325 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1326 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1327 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1328
1329 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1330 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1331 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1332 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1333 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1334
1335 /* Shadow RAM related */
1336 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1337 #define I40E_SR_BUF_ALIGNMENT           4096
1338 #define I40E_SR_WORDS_IN_1KB            512
1339 /* Checksum should be calculated such that after adding all the words,
1340  * including the checksum word itself, the sum should be 0xBABA.
1341  */
1342 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1343
1344 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1345
1346 enum i40e_switch_element_types {
1347         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1348         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1349         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1350         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1351         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1352         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1353         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1354         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1355         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1356 };
1357
1358 /* Supported EtherType filters */
1359 enum i40e_ether_type_index {
1360         I40E_ETHER_TYPE_1588            = 0,
1361         I40E_ETHER_TYPE_FIP             = 1,
1362         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1363         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1364         I40E_ETHER_TYPE_LLDP            = 4,
1365         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1366         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1367         I40E_ETHER_TYPE_QCN_CNM         = 7,
1368         I40E_ETHER_TYPE_8021X           = 8,
1369         I40E_ETHER_TYPE_ARP             = 9,
1370         I40E_ETHER_TYPE_RSV1            = 10,
1371         I40E_ETHER_TYPE_RSV2            = 11,
1372 };
1373
1374 /* Filter context base size is 1K */
1375 #define I40E_HASH_FILTER_BASE_SIZE      1024
1376 /* Supported Hash filter values */
1377 enum i40e_hash_filter_size {
1378         I40E_HASH_FILTER_SIZE_1K        = 0,
1379         I40E_HASH_FILTER_SIZE_2K        = 1,
1380         I40E_HASH_FILTER_SIZE_4K        = 2,
1381         I40E_HASH_FILTER_SIZE_8K        = 3,
1382         I40E_HASH_FILTER_SIZE_16K       = 4,
1383         I40E_HASH_FILTER_SIZE_32K       = 5,
1384         I40E_HASH_FILTER_SIZE_64K       = 6,
1385         I40E_HASH_FILTER_SIZE_128K      = 7,
1386         I40E_HASH_FILTER_SIZE_256K      = 8,
1387         I40E_HASH_FILTER_SIZE_512K      = 9,
1388         I40E_HASH_FILTER_SIZE_1M        = 10,
1389 };
1390
1391 /* DMA context base size is 0.5K */
1392 #define I40E_DMA_CNTX_BASE_SIZE         512
1393 /* Supported DMA context values */
1394 enum i40e_dma_cntx_size {
1395         I40E_DMA_CNTX_SIZE_512          = 0,
1396         I40E_DMA_CNTX_SIZE_1K           = 1,
1397         I40E_DMA_CNTX_SIZE_2K           = 2,
1398         I40E_DMA_CNTX_SIZE_4K           = 3,
1399         I40E_DMA_CNTX_SIZE_8K           = 4,
1400         I40E_DMA_CNTX_SIZE_16K          = 5,
1401         I40E_DMA_CNTX_SIZE_32K          = 6,
1402         I40E_DMA_CNTX_SIZE_64K          = 7,
1403         I40E_DMA_CNTX_SIZE_128K         = 8,
1404         I40E_DMA_CNTX_SIZE_256K         = 9,
1405 };
1406
1407 /* Supported Hash look up table (LUT) sizes */
1408 enum i40e_hash_lut_size {
1409         I40E_HASH_LUT_SIZE_128          = 0,
1410         I40E_HASH_LUT_SIZE_512          = 1,
1411 };
1412
1413 /* Structure to hold a per PF filter control settings */
1414 struct i40e_filter_control_settings {
1415         /* number of PE Quad Hash filter buckets */
1416         enum i40e_hash_filter_size pe_filt_num;
1417         /* number of PE Quad Hash contexts */
1418         enum i40e_dma_cntx_size pe_cntx_num;
1419         /* number of FCoE filter buckets */
1420         enum i40e_hash_filter_size fcoe_filt_num;
1421         /* number of FCoE DDP contexts */
1422         enum i40e_dma_cntx_size fcoe_cntx_num;
1423         /* size of the Hash LUT */
1424         enum i40e_hash_lut_size hash_lut_size;
1425         /* enable FDIR filters for PF and its VFs */
1426         bool enable_fdir;
1427         /* enable Ethertype filters for PF and its VFs */
1428         bool enable_ethtype;
1429         /* enable MAC/VLAN filters for PF and its VFs */
1430         bool enable_macvlan;
1431 };
1432
1433 /* Structure to hold device level control filter counts */
1434 struct i40e_control_filter_stats {
1435         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1436         u16 etype_used;       /* Used perfect EtherType filters */
1437         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1438         u16 etype_free;       /* Un-used perfect EtherType filters */
1439 };
1440
1441 enum i40e_reset_type {
1442         I40E_RESET_POR          = 0,
1443         I40E_RESET_CORER        = 1,
1444         I40E_RESET_GLOBR        = 2,
1445         I40E_RESET_EMPR         = 3,
1446 };
1447
1448 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1449 #define I40E_NVM_LLDP_CFG_PTR           0xD
1450 struct i40e_lldp_variables {
1451         u16 length;
1452         u16 adminstatus;
1453         u16 msgfasttx;
1454         u16 msgtxinterval;
1455         u16 txparams;
1456         u16 timers;
1457         u16 crc8;
1458 };
1459
1460 /* Offsets into Alternate Ram */
1461 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1462 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1463 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1464 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1465 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1466 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1467
1468 /* Alternate Ram Bandwidth Masks */
1469 #define I40E_ALT_BW_VALUE_MASK          0xFF
1470 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1471 #define I40E_ALT_BW_VALID_MASK          0x80000000
1472
1473 /* RSS Hash Table Size */
1474 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1475 #endif /* _I40E_TYPE_H_ */