drivers/net/i40e/base/i40e_type.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #ifndef _I40E_TYPE_H_
   6 #define _I40E_TYPE_H_
   7
   8 #include "i40e_status.h"
   9 #include "i40e_osdep.h"
  10 #include "i40e_register.h"
  11 #include "i40e_adminq.h"
  12 #include "i40e_hmc.h"
  13 #include "i40e_lan_hmc.h"
  14 #include "i40e_devids.h"
  15
  16 #define UNREFERENCED_XPARAMETER
  17 #define UNREFERENCED_1PARAMETER(_p) (_p);
  18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  22
  23 #ifndef LINUX_MACROS
  24 #ifndef BIT
  25 #define BIT(a) (1UL << (a))
  26 #endif /* BIT */
  27 #ifndef BIT_ULL
  28 #define BIT_ULL(a) (1ULL << (a))
  29 #endif /* BIT_ULL */
  30 #endif /* LINUX_MACROS */
  31
  32 #ifndef I40E_MASK
  33 /* I40E_MASK is a macro used on 32 bit registers */
  34 #define I40E_MASK(mask, shift) (mask << shift)
  35 #endif
  36
  37 #define I40E_MAX_PF                     16
  38 #define I40E_MAX_PF_VSI                 64
  39 #define I40E_MAX_PF_QP                  128
  40 #define I40E_MAX_VSI_QP                 16
  41 #define I40E_MAX_VF_VSI                 4
  42 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  43 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  44
  45 /* something less than 1 minute */
  46 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  47
  48 /* Max default timeout in ms, */
  49 #define I40E_MAX_NVM_TIMEOUT            18000
  50
  51 /* Max timeout in ms for the phy to respond */
  52 #define I40E_MAX_PHY_TIMEOUT            500
  53
  54 /* Check whether address is multicast. */
  55 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  56
  57 /* Check whether an address is broadcast. */
  58 #define I40E_IS_BROADCAST(address)      \
  59         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  60         (((u8 *)(address))[1] == ((u8)0xff)))
  61
  62 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  63 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  64
  65 /* forward declaration */
  66 struct i40e_hw;
  67 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  68
  69 #ifndef ETH_ALEN
  70 #define ETH_ALEN        6
  71 #endif
  72 /* Data type manipulation macros. */
  73 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  74 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  75
  76 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  77 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  78
  79 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  80 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
  81
  82 /* Number of Transmit Descriptors must be a multiple of 32. */
  83 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 32
  84 /* Number of Receive Descriptors must be a multiple of 32 if
  85  * the number of descriptors is greater than 32.
  86  */
  87 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
  88
  89 #define I40E_DESC_UNUSED(R)     \
  90         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  91         (R)->next_to_clean - (R)->next_to_use - 1)
  92
  93 /* bitfields for Tx queue mapping in QTX_CTL */
  94 #define I40E_QTX_CTL_VF_QUEUE   0x0
  95 #define I40E_QTX_CTL_VM_QUEUE   0x1
  96 #define I40E_QTX_CTL_PF_QUEUE   0x2
  97
  98 /* debug masks - set these bits in hw->debug_mask to control output */
  99 enum i40e_debug_mask {
 100         I40E_DEBUG_INIT                 = 0x00000001,
 101         I40E_DEBUG_RELEASE              = 0x00000002,
 102
 103         I40E_DEBUG_LINK                 = 0x00000010,
 104         I40E_DEBUG_PHY                  = 0x00000020,
 105         I40E_DEBUG_HMC                  = 0x00000040,
 106         I40E_DEBUG_NVM                  = 0x00000080,
 107         I40E_DEBUG_LAN                  = 0x00000100,
 108         I40E_DEBUG_FLOW                 = 0x00000200,
 109         I40E_DEBUG_DCB                  = 0x00000400,
 110         I40E_DEBUG_DIAG                 = 0x00000800,
 111         I40E_DEBUG_FD                   = 0x00001000,
 112         I40E_DEBUG_PACKAGE              = 0x00002000,
 113
 114         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 115         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 116         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 117         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 118         I40E_DEBUG_AQ                   = 0x0F000000,
 119
 120         I40E_DEBUG_USER                 = 0xF0000000,
 121
 122         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 123 };
 124
 125 /* PCI Bus Info */
 126 #define I40E_PCI_LINK_STATUS            0xB2
 127 #define I40E_PCI_LINK_WIDTH             0x3F0
 128 #define I40E_PCI_LINK_WIDTH_1           0x10
 129 #define I40E_PCI_LINK_WIDTH_2           0x20
 130 #define I40E_PCI_LINK_WIDTH_4           0x40
 131 #define I40E_PCI_LINK_WIDTH_8           0x80
 132 #define I40E_PCI_LINK_SPEED             0xF
 133 #define I40E_PCI_LINK_SPEED_2500        0x1
 134 #define I40E_PCI_LINK_SPEED_5000        0x2
 135 #define I40E_PCI_LINK_SPEED_8000        0x3
 136
 137 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 138                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 139 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 140                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 141 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 142                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 143
 144 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 145                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 146 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 147                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 148 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 149                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 150 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 151                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 152 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 153                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 154
 155 #define I40E_PHY_COM_REG_PAGE                   0x1E
 156 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 157 #define I40E_PHY_LED_MANUAL_ON                  0x100
 158 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 159 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 160 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 161
 162 /* Memory types */
 163 enum i40e_memset_type {
 164         I40E_NONDMA_MEM = 0,
 165         I40E_DMA_MEM
 166 };
 167
 168 /* Memcpy types */
 169 enum i40e_memcpy_type {
 170         I40E_NONDMA_TO_NONDMA = 0,
 171         I40E_NONDMA_TO_DMA,
 172         I40E_DMA_TO_DMA,
 173         I40E_DMA_TO_NONDMA
 174 };
 175
 176 /* These are structs for managing the hardware information and the operations.
 177  * The structures of function pointers are filled out at init time when we
 178  * know for sure exactly which hardware we're working with.  This gives us the
 179  * flexibility of using the same main driver code but adapting to slightly
 180  * different hardware needs as new parts are developed.  For this architecture,
 181  * the Firmware and AdminQ are intended to insulate the driver from most of the
 182  * future changes, but these structures will also do part of the job.
 183  */
 184 enum i40e_mac_type {
 185         I40E_MAC_UNKNOWN = 0,
 186         I40E_MAC_XL710,
 187         I40E_MAC_VF,
 188         I40E_MAC_X722,
 189         I40E_MAC_X722_VF,
 190         I40E_MAC_GENERIC,
 191 };
 192
 193 enum i40e_media_type {
 194         I40E_MEDIA_TYPE_UNKNOWN = 0,
 195         I40E_MEDIA_TYPE_FIBER,
 196         I40E_MEDIA_TYPE_BASET,
 197         I40E_MEDIA_TYPE_BACKPLANE,
 198         I40E_MEDIA_TYPE_CX4,
 199         I40E_MEDIA_TYPE_DA,
 200         I40E_MEDIA_TYPE_VIRTUAL
 201 };
 202
 203 enum i40e_fc_mode {
 204         I40E_FC_NONE = 0,
 205         I40E_FC_RX_PAUSE,
 206         I40E_FC_TX_PAUSE,
 207         I40E_FC_FULL,
 208         I40E_FC_PFC,
 209         I40E_FC_DEFAULT
 210 };
 211
 212 enum i40e_set_fc_aq_failures {
 213         I40E_SET_FC_AQ_FAIL_NONE = 0,
 214         I40E_SET_FC_AQ_FAIL_GET = 1,
 215         I40E_SET_FC_AQ_FAIL_SET = 2,
 216         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 217         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 218 };
 219
 220 enum i40e_vsi_type {
 221         I40E_VSI_MAIN   = 0,
 222         I40E_VSI_VMDQ1  = 1,
 223         I40E_VSI_VMDQ2  = 2,
 224         I40E_VSI_CTRL   = 3,
 225         I40E_VSI_FCOE   = 4,
 226         I40E_VSI_MIRROR = 5,
 227         I40E_VSI_SRIOV  = 6,
 228         I40E_VSI_FDIR   = 7,
 229         I40E_VSI_TYPE_UNKNOWN
 230 };
 231
 232 enum i40e_queue_type {
 233         I40E_QUEUE_TYPE_RX = 0,
 234         I40E_QUEUE_TYPE_TX,
 235         I40E_QUEUE_TYPE_PE_CEQ,
 236         I40E_QUEUE_TYPE_UNKNOWN
 237 };
 238
 239 struct i40e_link_status {
 240         enum i40e_aq_phy_type phy_type;
 241         enum i40e_aq_link_speed link_speed;
 242         u8 link_info;
 243         u8 an_info;
 244         u8 req_fec_info;
 245         u8 fec_info;
 246         u8 ext_info;
 247         u8 loopback;
 248         /* is Link Status Event notification to SW enabled */
 249         bool lse_enable;
 250         u16 max_frame_size;
 251         bool crc_enable;
 252         u8 pacing;
 253         u8 requested_speeds;
 254         u8 module_type[3];
 255         /* 1st byte: module identifier */
 256 #define I40E_MODULE_TYPE_SFP            0x03
 257 #define I40E_MODULE_TYPE_QSFP           0x0D
 258         /* 2nd byte: ethernet compliance codes for 10/40G */
 259 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 260 #define I40E_MODULE_TYPE_40G_LR4        0x02
 261 #define I40E_MODULE_TYPE_40G_SR4        0x04
 262 #define I40E_MODULE_TYPE_40G_CR4        0x08
 263 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 264 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 265 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 266 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 267         /* 3rd byte: ethernet compliance codes for 1G */
 268 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 269 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 270 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 271 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 272 };
 273
 274 struct i40e_phy_info {
 275         struct i40e_link_status link_info;
 276         struct i40e_link_status link_info_old;
 277         bool get_link_info;
 278         enum i40e_media_type media_type;
 279         /* all the phy types the NVM is capable of */
 280         u64 phy_types;
 281 };
 282
 283 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 284 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 285 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 286 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 287 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 288 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 289 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 290 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 291 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 292 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 293 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 294 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 295 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 296 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 297 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 298 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 299 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 300 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 301 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 302 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 303 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 304 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 305 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 306 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 307 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 308 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 309 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 310                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 311 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 312 /*
 313  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 314  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 315  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 316  * a shift is needed to adjust for this with values larger than 31. The
 317  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 318  */
 319 #define I40E_PHY_TYPE_OFFSET 1
 320 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 321                                              I40E_PHY_TYPE_OFFSET)
 322 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 323                                              I40E_PHY_TYPE_OFFSET)
 324 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 325                                              I40E_PHY_TYPE_OFFSET)
 326 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 327                                              I40E_PHY_TYPE_OFFSET)
 328 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 329                                              I40E_PHY_TYPE_OFFSET)
 330 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 331                                              I40E_PHY_TYPE_OFFSET)
 332 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
 333 #define I40E_PHY_TYPE_OFFSET2 (-10)
 334 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
 335                                              I40E_PHY_TYPE_OFFSET2)
 336 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
 337                                              I40E_PHY_TYPE_OFFSET2)
 338 #define I40E_HW_CAP_MAX_GPIO                    30
 339 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 340 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 341
 342 enum i40e_acpi_programming_method {
 343         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 344         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 345 };
 346
 347 #define I40E_WOL_SUPPORT_MASK                   0x1
 348 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 349 #define I40E_PROXY_SUPPORT_MASK                 0x4
 350
 351 /* Capabilities of a PF or a VF or the whole device */
 352 struct i40e_hw_capabilities {
 353         u32  switch_mode;
 354 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 355 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 356 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 357
 358         /* Cloud filter modes:
 359          * Mode1: Filter on L4 port only
 360          * Mode2: Filter for non-tunneled traffic
 361          * Mode3: Filter for tunnel traffic
 362          */
 363 #define I40E_CLOUD_FILTER_MODE1 0x6
 364 #define I40E_CLOUD_FILTER_MODE2 0x7
 365 #define I40E_CLOUD_FILTER_MODE3 0x8
 366 #define I40E_SWITCH_MODE_MASK   0xF
 367
 368         u32  management_mode;
 369         u32  mng_protocols_over_mctp;
 370 #define I40E_MNG_PROTOCOL_PLDM          0x2
 371 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 372 #define I40E_MNG_PROTOCOL_NCSI          0x8
 373         u32  npar_enable;
 374         u32  os2bmc;
 375         u32  valid_functions;
 376         bool sr_iov_1_1;
 377         bool vmdq;
 378         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 379         bool evb_802_1_qbh; /* Bridge Port Extension */
 380         bool dcb;
 381         bool fcoe;
 382         bool iscsi; /* Indicates iSCSI enabled */
 383         bool flex10_enable;
 384         bool flex10_capable;
 385         u32  flex10_mode;
 386 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 387 #define I40E_FLEX10_MODE_DCC            0x1
 388 #define I40E_FLEX10_MODE_DCI            0x2
 389
 390         u32 flex10_status;
 391 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 392 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 393
 394         bool sec_rev_disabled;
 395         bool update_disabled;
 396 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 397 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 398
 399         bool mgmt_cem;
 400         bool ieee_1588;
 401         bool iwarp;
 402         bool fd;
 403         u32 fd_filters_guaranteed;
 404         u32 fd_filters_best_effort;
 405         bool rss;
 406         u32 rss_table_size;
 407         u32 rss_table_entry_width;
 408         bool led[I40E_HW_CAP_MAX_GPIO];
 409         bool sdp[I40E_HW_CAP_MAX_GPIO];
 410         u32 nvm_image_type;
 411         u32 num_flow_director_filters;
 412         u32 num_vfs;
 413         u32 vf_base_id;
 414         u32 num_vsis;
 415         u32 num_rx_qp;
 416         u32 num_tx_qp;
 417         u32 base_queue;
 418         u32 num_msix_vectors;
 419         u32 num_msix_vectors_vf;
 420         u32 led_pin_num;
 421         u32 sdp_pin_num;
 422         u32 mdio_port_num;
 423         u32 mdio_port_mode;
 424         u8 rx_buf_chain_len;
 425         u32 enabled_tcmap;
 426         u32 maxtc;
 427         u64 wr_csr_prot;
 428         bool apm_wol_support;
 429         enum i40e_acpi_programming_method acpi_prog_method;
 430         bool proxy_support;
 431 };
 432
 433 struct i40e_mac_info {
 434         enum i40e_mac_type type;
 435         u8 addr[ETH_ALEN];
 436         u8 perm_addr[ETH_ALEN];
 437         u8 san_addr[ETH_ALEN];
 438         u8 port_addr[ETH_ALEN];
 439         u16 max_fcoeq;
 440 };
 441
 442 enum i40e_aq_resources_ids {
 443         I40E_NVM_RESOURCE_ID = 1
 444 };
 445
 446 enum i40e_aq_resource_access_type {
 447         I40E_RESOURCE_READ = 1,
 448         I40E_RESOURCE_WRITE
 449 };
 450
 451 struct i40e_nvm_info {
 452         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 453         u32 timeout;              /* [ms] */
 454         u16 sr_size;              /* Shadow RAM size in words */
 455         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 456         u16 version;              /* NVM package version */
 457         u32 eetrack;              /* NVM data version */
 458         u32 oem_ver;              /* OEM version info */
 459 };
 460
 461 /* definitions used in NVM update support */
 462
 463 enum i40e_nvmupd_cmd {
 464         I40E_NVMUPD_INVALID,
 465         I40E_NVMUPD_READ_CON,
 466         I40E_NVMUPD_READ_SNT,
 467         I40E_NVMUPD_READ_LCB,
 468         I40E_NVMUPD_READ_SA,
 469         I40E_NVMUPD_WRITE_ERA,
 470         I40E_NVMUPD_WRITE_CON,
 471         I40E_NVMUPD_WRITE_SNT,
 472         I40E_NVMUPD_WRITE_LCB,
 473         I40E_NVMUPD_WRITE_SA,
 474         I40E_NVMUPD_CSUM_CON,
 475         I40E_NVMUPD_CSUM_SA,
 476         I40E_NVMUPD_CSUM_LCB,
 477         I40E_NVMUPD_STATUS,
 478         I40E_NVMUPD_EXEC_AQ,
 479         I40E_NVMUPD_GET_AQ_RESULT,
 480         I40E_NVMUPD_GET_AQ_EVENT,
 481         I40E_NVMUPD_FEATURES,
 482 };
 483
 484 enum i40e_nvmupd_state {
 485         I40E_NVMUPD_STATE_INIT,
 486         I40E_NVMUPD_STATE_READING,
 487         I40E_NVMUPD_STATE_WRITING,
 488         I40E_NVMUPD_STATE_INIT_WAIT,
 489         I40E_NVMUPD_STATE_WRITE_WAIT,
 490         I40E_NVMUPD_STATE_ERROR
 491 };
 492
 493 /* nvm_access definition and its masks/shifts need to be accessible to
 494  * application, core driver, and shared code.  Where is the right file?
 495  */
 496 #define I40E_NVM_READ   0xB
 497 #define I40E_NVM_WRITE  0xC
 498
 499 #define I40E_NVM_MOD_PNT_MASK 0xFF
 500
 501 #define I40E_NVM_TRANS_SHIFT                    8
 502 #define I40E_NVM_TRANS_MASK                     (0xf << I40E_NVM_TRANS_SHIFT)
 503 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT       12
 504 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
 505                                 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
 506 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 507 #define I40E_NVM_PRESERVATION_FLAGS_ALL         0x02
 508 #define I40E_NVM_CON                            0x0
 509 #define I40E_NVM_SNT                            0x1
 510 #define I40E_NVM_LCB                            0x2
 511 #define I40E_NVM_SA                             (I40E_NVM_SNT | I40E_NVM_LCB)
 512 #define I40E_NVM_ERA                            0x4
 513 #define I40E_NVM_CSUM                           0x8
 514 #define I40E_NVM_AQE                            0xe
 515 #define I40E_NVM_EXEC                           0xf
 516
 517 #define I40E_NVM_EXEC_GET_AQ_RESULT             0x0
 518 #define I40E_NVM_EXEC_FEATURES                  0xe
 519 #define I40E_NVM_EXEC_STATUS                    0xf
 520
 521 #define I40E_NVM_ADAPT_SHIFT    16
 522 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 523
 524 #define I40E_NVMUPD_MAX_DATA    4096
 525 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 526
 527 struct i40e_nvm_access {
 528         u32 command;
 529         u32 config;
 530         u32 offset;     /* in bytes */
 531         u32 data_size;  /* in bytes */
 532         u8 data[1];
 533 };
 534
 535 /* NVMUpdate features API */
 536 #define I40E_NVMUPD_FEATURES_API_VER_MAJOR              0
 537 #define I40E_NVMUPD_FEATURES_API_VER_MINOR              14
 538 #define I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN     12
 539
 540 #define I40E_NVMUPD_FEATURE_FLAT_NVM_SUPPORT            BIT(0)
 541
 542 struct i40e_nvmupd_features {
 543         u8 major;
 544         u8 minor;
 545         u16 size;
 546         u8 features[I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];
 547 };
 548
 549 /* (Q)SFP module access definitions */
 550 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 551 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 552 #define I40E_MODULE_TYPE_ADDR           0x00
 553 #define I40E_MODULE_REVISION_ADDR       0x01
 554 #define I40E_MODULE_SFF_8472_COMP       0x5E
 555 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 556 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 557 #define I40E_MODULE_SFF_DIAG_CAPAB      0x40
 558 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 559 #define I40E_MODULE_TYPE_QSFP28         0x11
 560 #define I40E_MODULE_QSFP_MAX_LEN        640
 561
 562 /* PCI bus types */
 563 enum i40e_bus_type {
 564         i40e_bus_type_unknown = 0,
 565         i40e_bus_type_pci,
 566         i40e_bus_type_pcix,
 567         i40e_bus_type_pci_express,
 568         i40e_bus_type_reserved
 569 };
 570
 571 /* PCI bus speeds */
 572 enum i40e_bus_speed {
 573         i40e_bus_speed_unknown  = 0,
 574         i40e_bus_speed_33       = 33,
 575         i40e_bus_speed_66       = 66,
 576         i40e_bus_speed_100      = 100,
 577         i40e_bus_speed_120      = 120,
 578         i40e_bus_speed_133      = 133,
 579         i40e_bus_speed_2500     = 2500,
 580         i40e_bus_speed_5000     = 5000,
 581         i40e_bus_speed_8000     = 8000,
 582         i40e_bus_speed_reserved
 583 };
 584
 585 /* PCI bus widths */
 586 enum i40e_bus_width {
 587         i40e_bus_width_unknown  = 0,
 588         i40e_bus_width_pcie_x1  = 1,
 589         i40e_bus_width_pcie_x2  = 2,
 590         i40e_bus_width_pcie_x4  = 4,
 591         i40e_bus_width_pcie_x8  = 8,
 592         i40e_bus_width_32       = 32,
 593         i40e_bus_width_64       = 64,
 594         i40e_bus_width_reserved
 595 };
 596
 597 /* Bus parameters */
 598 struct i40e_bus_info {
 599         enum i40e_bus_speed speed;
 600         enum i40e_bus_width width;
 601         enum i40e_bus_type type;
 602
 603         u16 func;
 604         u16 device;
 605         u16 lan_id;
 606         u16 bus_id;
 607 };
 608
 609 /* Flow control (FC) parameters */
 610 struct i40e_fc_info {
 611         enum i40e_fc_mode current_mode; /* FC mode in effect */
 612         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 613 };
 614
 615 #define I40E_MAX_TRAFFIC_CLASS          8
 616 #define I40E_MAX_USER_PRIORITY          8
 617 #define I40E_DCBX_MAX_APPS              32
 618 #define I40E_LLDPDU_SIZE                1500
 619 #define I40E_TLV_STATUS_OPER            0x1
 620 #define I40E_TLV_STATUS_SYNC            0x2
 621 #define I40E_TLV_STATUS_ERR             0x4
 622 #define I40E_CEE_OPER_MAX_APPS          3
 623 #define I40E_APP_PROTOID_FCOE           0x8906
 624 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 625 #define I40E_APP_PROTOID_FIP            0x8914
 626 #define I40E_APP_SEL_ETHTYPE            0x1
 627 #define I40E_APP_SEL_TCPIP              0x2
 628 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 629 #define I40E_CEE_APP_SEL_TCPIP          0x1
 630
 631 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 632 struct i40e_dcb_ets_config {
 633         u8 willing;
 634         u8 cbs;
 635         u8 maxtcs;
 636         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 637         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 638         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 639 };
 640
 641 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 642 struct i40e_dcb_pfc_config {
 643         u8 willing;
 644         u8 mbc;
 645         u8 pfccap;
 646         u8 pfcenable;
 647 };
 648
 649 /* CEE or IEEE 802.1Qaz Application Priority data */
 650 struct i40e_dcb_app_priority_table {
 651         u8  priority;
 652         u8  selector;
 653         u16 protocolid;
 654 };
 655
 656 struct i40e_dcbx_config {
 657         u8  dcbx_mode;
 658 #define I40E_DCBX_MODE_CEE      0x1
 659 #define I40E_DCBX_MODE_IEEE     0x2
 660         u8  app_mode;
 661 #define I40E_DCBX_APPS_NON_WILLING      0x1
 662         u32 numapps;
 663         u32 tlv_status; /* CEE mode TLV status */
 664         struct i40e_dcb_ets_config etscfg;
 665         struct i40e_dcb_ets_config etsrec;
 666         struct i40e_dcb_pfc_config pfc;
 667         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 668 };
 669
 670 /* Port hardware description */
 671 struct i40e_hw {
 672         u8 *hw_addr;
 673         void *back;
 674
 675         /* subsystem structs */
 676         struct i40e_phy_info phy;
 677         struct i40e_mac_info mac;
 678         struct i40e_bus_info bus;
 679         struct i40e_nvm_info nvm;
 680         struct i40e_fc_info fc;
 681
 682         /* switch device is used to get link status when i40e is in ipn3ke */
 683         struct rte_eth_dev *switch_dev;
 684
 685         /* pci info */
 686         u16 device_id;
 687         u16 vendor_id;
 688         u16 subsystem_device_id;
 689         u16 subsystem_vendor_id;
 690         u8 revision_id;
 691         u8 port;
 692         bool adapter_stopped;
 693         bool adapter_closed;
 694
 695         /* capabilities for entire device and PCI func */
 696         struct i40e_hw_capabilities dev_caps;
 697         struct i40e_hw_capabilities func_caps;
 698
 699         /* Flow Director shared filter space */
 700         u16 fdir_shared_filter_count;
 701
 702         /* device profile info */
 703         u8  pf_id;
 704         u16 main_vsi_seid;
 705
 706         /* for multi-function MACs */
 707         u16 partition_id;
 708         u16 num_partitions;
 709         u16 num_ports;
 710
 711         /* Closest numa node to the device */
 712         u16 numa_node;
 713
 714         /* Admin Queue info */
 715         struct i40e_adminq_info aq;
 716
 717         /* state of nvm update process */
 718         enum i40e_nvmupd_state nvmupd_state;
 719         struct i40e_aq_desc nvm_wb_desc;
 720         struct i40e_aq_desc nvm_aq_event_desc;
 721         struct i40e_virt_mem nvm_buff;
 722         bool nvm_release_on_done;
 723         u16 nvm_wait_opcode;
 724
 725         /* HMC info */
 726         struct i40e_hmc_info hmc; /* HMC info struct */
 727
 728         /* LLDP/DCBX Status */
 729         u16 dcbx_status;
 730
 731         /* DCBX info */
 732         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 733         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 734         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 735
 736         /* WoL and proxy support */
 737         u16 num_wol_proxy_filters;
 738         u16 wol_proxy_vsi_seid;
 739
 740 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 741 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 742 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 743 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 744 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE      BIT_ULL(4)
 745 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT     BIT_ULL(5)
 746 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
 747 #define I40E_HW_FLAG_DROP_MODE              BIT_ULL(7)
 748         u64 flags;
 749
 750         /* Used in set switch config AQ command */
 751         u16 switch_tag;
 752         u16 first_tag;
 753         u16 second_tag;
 754
 755         /* NVMUpdate features */
 756         struct i40e_nvmupd_features nvmupd_features;
 757
 758         /* debug mask */
 759         u32 debug_mask;
 760         char err_str[16];
 761 };
 762
 763 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 764 {
 765         return (hw->mac.type == I40E_MAC_VF ||
 766                 hw->mac.type == I40E_MAC_X722_VF);
 767 }
 768
 769 struct i40e_driver_version {
 770         u8 major_version;
 771         u8 minor_version;
 772         u8 build_version;
 773         u8 subbuild_version;
 774         u8 driver_string[32];
 775 };
 776
 777 /* RX Descriptors */
 778 union i40e_16byte_rx_desc {
 779         struct {
 780                 __le64 pkt_addr; /* Packet buffer address */
 781                 __le64 hdr_addr; /* Header buffer address */
 782         } read;
 783         struct {
 784                 struct {
 785                         struct {
 786                                 union {
 787                                         __le16 mirroring_status;
 788                                         __le16 fcoe_ctx_id;
 789                                 } mirr_fcoe;
 790                                 __le16 l2tag1;
 791                         } lo_dword;
 792                         union {
 793                                 __le32 rss; /* RSS Hash */
 794                                 __le32 fd_id; /* Flow director filter id */
 795                                 __le32 fcoe_param; /* FCoE DDP Context id */
 796                         } hi_dword;
 797                 } qword0;
 798                 struct {
 799                         /* ext status/error/pktype/length */
 800                         __le64 status_error_len;
 801                 } qword1;
 802         } wb;  /* writeback */
 803 };
 804
 805 union i40e_32byte_rx_desc {
 806         struct {
 807                 __le64  pkt_addr; /* Packet buffer address */
 808                 __le64  hdr_addr; /* Header buffer address */
 809                         /* bit 0 of hdr_buffer_addr is DD bit */
 810                 __le64  rsvd1;
 811                 __le64  rsvd2;
 812         } read;
 813         struct {
 814                 struct {
 815                         struct {
 816                                 union {
 817                                         __le16 mirroring_status;
 818                                         __le16 fcoe_ctx_id;
 819                                 } mirr_fcoe;
 820                                 __le16 l2tag1;
 821                         } lo_dword;
 822                         union {
 823                                 __le32 rss; /* RSS Hash */
 824                                 __le32 fcoe_param; /* FCoE DDP Context id */
 825                                 /* Flow director filter id in case of
 826                                  * Programming status desc WB
 827                                  */
 828                                 __le32 fd_id;
 829                         } hi_dword;
 830                 } qword0;
 831                 struct {
 832                         /* status/error/pktype/length */
 833                         __le64 status_error_len;
 834                 } qword1;
 835                 struct {
 836                         __le16 ext_status; /* extended status */
 837                         __le16 rsvd;
 838                         __le16 l2tag2_1;
 839                         __le16 l2tag2_2;
 840                 } qword2;
 841                 struct {
 842                         union {
 843                                 __le32 flex_bytes_lo;
 844                                 __le32 pe_status;
 845                         } lo_dword;
 846                         union {
 847                                 __le32 flex_bytes_hi;
 848                                 __le32 fd_id;
 849                         } hi_dword;
 850                 } qword3;
 851         } wb;  /* writeback */
 852 };
 853
 854 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 855 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 856                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 857 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 858 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 859                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 860
 861 enum i40e_rx_desc_status_bits {
 862         /* Note: These are predefined bit offsets */
 863         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 864         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 865         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 866         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 867         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 868         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 869         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 870         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 871
 872         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 873         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 874         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 875         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 876         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 877         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 878         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 879         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 880 };
 881
 882 #define I40E_RXD_QW1_STATUS_SHIFT       0
 883 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 884                                          I40E_RXD_QW1_STATUS_SHIFT)
 885
 886 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 887 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 888                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 889
 890 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 891 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 892
 893 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 894 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 895                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 896
 897 enum i40e_rx_desc_fltstat_values {
 898         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 899         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 900         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 901         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 902 };
 903
 904 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 905 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 906 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 907 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 908
 909 #define I40E_RXD_QW1_ERROR_SHIFT        19
 910 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 911
 912 enum i40e_rx_desc_error_bits {
 913         /* Note: These are predefined bit offsets */
 914         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 915         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 916         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 917         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 918         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 919         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 920         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 921         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 922         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 923 };
 924
 925 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 926         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 927         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 928         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 929         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 930         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 931 };
 932
 933 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 934 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 935
 936 /* Packet type non-ip values */
 937 enum i40e_rx_l2_ptype {
 938         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 939         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 940         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 941         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 942         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 943         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 944         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 945         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 946         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 947         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 948         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 949         I40E_RX_PTYPE_L2_ARP                            = 11,
 950         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 951         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 952         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 953         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 954         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 955         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 956         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 957         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 958         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 959         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 960         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 961         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 962         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 963         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 964 };
 965
 966 struct i40e_rx_ptype_decoded {
 967         u32 ptype:8;
 968         u32 known:1;
 969         u32 outer_ip:1;
 970         u32 outer_ip_ver:1;
 971         u32 outer_frag:1;
 972         u32 tunnel_type:3;
 973         u32 tunnel_end_prot:2;
 974         u32 tunnel_end_frag:1;
 975         u32 inner_prot:4;
 976         u32 payload_layer:3;
 977 };
 978
 979 enum i40e_rx_ptype_outer_ip {
 980         I40E_RX_PTYPE_OUTER_L2  = 0,
 981         I40E_RX_PTYPE_OUTER_IP  = 1
 982 };
 983
 984 enum i40e_rx_ptype_outer_ip_ver {
 985         I40E_RX_PTYPE_OUTER_NONE        = 0,
 986         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 987         I40E_RX_PTYPE_OUTER_IPV6        = 1
 988 };
 989
 990 enum i40e_rx_ptype_outer_fragmented {
 991         I40E_RX_PTYPE_NOT_FRAG  = 0,
 992         I40E_RX_PTYPE_FRAG      = 1
 993 };
 994
 995 enum i40e_rx_ptype_tunnel_type {
 996         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 997         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 998         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 999         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
1000         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
1001 };
1002
1003 enum i40e_rx_ptype_tunnel_end_prot {
1004         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
1005         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
1006         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
1007 };
1008
1009 enum i40e_rx_ptype_inner_prot {
1010         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
1011         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
1012         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
1013         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
1014         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
1015         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
1016 };
1017
1018 enum i40e_rx_ptype_payload_layer {
1019         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
1020         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
1021         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
1022         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
1023 };
1024
1025 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
1026 #define I40E_RX_PTYPE_SHIFT             56
1027
1028 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
1029 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
1030                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1031
1032 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
1033 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
1034                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1035
1036 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
1037 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1038
1039 #define I40E_RXD_QW1_NEXTP_SHIFT        38
1040 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1041
1042 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
1043 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1044                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
1045
1046 enum i40e_rx_desc_ext_status_bits {
1047         /* Note: These are predefined bit offsets */
1048         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1049         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1050         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1051         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1052         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1053         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1054         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1055 };
1056
1057 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1058 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1059
1060 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1061 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1062
1063 enum i40e_rx_desc_pe_status_bits {
1064         /* Note: These are predefined bit offsets */
1065         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1066         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1067         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1068         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1069         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1070         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1071         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1072         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1073         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1074 };
1075
1076 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1077 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1078
1079 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1080 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1081                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1082
1083 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1084 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1085                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1086
1087 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1088 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1089                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1090
1091 enum i40e_rx_prog_status_desc_status_bits {
1092         /* Note: These are predefined bit offsets */
1093         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1094         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1095 };
1096
1097 enum i40e_rx_prog_status_desc_prog_id_masks {
1098         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1099         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1100         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1101 };
1102
1103 enum i40e_rx_prog_status_desc_error_bits {
1104         /* Note: These are predefined bit offsets */
1105         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1106         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1107         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1108         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1109 };
1110
1111 #define I40E_TWO_BIT_MASK       0x3
1112 #define I40E_THREE_BIT_MASK     0x7
1113 #define I40E_FOUR_BIT_MASK      0xF
1114 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1115
1116 /* TX Descriptor */
1117 struct i40e_tx_desc {
1118         __le64 buffer_addr; /* Address of descriptor's data buf */
1119         __le64 cmd_type_offset_bsz;
1120 };
1121
1122 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1123 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1124
1125 enum i40e_tx_desc_dtype_value {
1126         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1127         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1128         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1129         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1130         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1131         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1132         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1133         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1134         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1135         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1136 };
1137
1138 #define I40E_TXD_QW1_CMD_SHIFT  4
1139 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1140
1141 enum i40e_tx_desc_cmd_bits {
1142         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1143         I40E_TX_DESC_CMD_RS                     = 0x0002,
1144         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1145         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1146         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1147         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1148         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1149         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1150         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1151         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1152         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1153         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1154         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1155         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1156         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1157         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1158         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1159         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1160 };
1161
1162 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1163 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1164                                          I40E_TXD_QW1_OFFSET_SHIFT)
1165
1166 enum i40e_tx_desc_length_fields {
1167         /* Note: These are predefined bit offsets */
1168         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1169         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1170         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1171 };
1172
1173 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1174 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1175 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1176 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1177
1178 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1179 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1180                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1181
1182 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1183 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1184
1185 /* Context descriptors */
1186 struct i40e_tx_context_desc {
1187         __le32 tunneling_params;
1188         __le16 l2tag2;
1189         __le16 rsvd;
1190         __le64 type_cmd_tso_mss;
1191 };
1192
1193 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1194 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1195
1196 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1197 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1198
1199 enum i40e_tx_ctx_desc_cmd_bits {
1200         I40E_TX_CTX_DESC_TSO            = 0x01,
1201         I40E_TX_CTX_DESC_TSYN           = 0x02,
1202         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1203         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1204         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1205         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1206         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1207         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1208         I40E_TX_CTX_DESC_SWPE           = 0x40
1209 };
1210
1211 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1212 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1213                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1214
1215 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1216 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1217                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1218
1219 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1220 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1221
1222 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1223 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1224                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1225
1226 enum i40e_tx_ctx_desc_eipt_offload {
1227         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1228         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1229         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1230         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1231 };
1232
1233 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1234 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1235                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1236
1237 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1238 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1239
1240 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1241 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1242
1243 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1244 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1245
1246 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1247
1248 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1249 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1250                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1251
1252 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1253 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1254                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1255
1256 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1257 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1258 struct i40e_nop_desc {
1259         __le64 rsvd;
1260         __le64 dtype_cmd;
1261 };
1262
1263 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1264 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1265
1266 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1267 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1268
1269 enum i40e_tx_nop_desc_cmd_bits {
1270         /* Note: These are predefined bit offsets */
1271         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1272         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1273         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1274 };
1275
1276 struct i40e_filter_program_desc {
1277         __le32 qindex_flex_ptype_vsi;
1278         __le32 rsvd;
1279         __le32 dtype_cmd_cntindex;
1280         __le32 fd_id;
1281 };
1282 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1283 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1284                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1285 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1286 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1287                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1288 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1289 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1290                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1291
1292 /* Packet Classifier Types for filters */
1293 enum i40e_filter_pctype {
1294         /* Note: Values 0-28 are reserved for future use.
1295          * Value 29, 30, 32 are not supported on XL710 and X710.
1296          */
1297         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1298         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1299         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1300         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1301         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1302         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1303         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1304         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1305         /* Note: Values 37-38 are reserved for future use.
1306          * Value 39, 40, 42 are not supported on XL710 and X710.
1307          */
1308         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1309         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1310         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1311         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1312         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1313         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1314         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1315         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1316         /* Note: Value 47 is reserved for future use */
1317         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1318         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1319         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1320         /* Note: Values 51-62 are reserved for future use */
1321         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1322 };
1323
1324 enum i40e_filter_program_desc_dest {
1325         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1326         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1327         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1328 };
1329
1330 enum i40e_filter_program_desc_fd_status {
1331         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1332         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1333         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1334         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1335 };
1336
1337 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1338 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1339                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1340
1341 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1342 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1343
1344 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1345 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1346                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1347
1348 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1349 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1350
1351 enum i40e_filter_program_desc_pcmd {
1352         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1353         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1354 };
1355
1356 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1357 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1358
1359 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1360 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1361
1362 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1363                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1364 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1365                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1366
1367 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1368                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1369 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1370
1371 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1372 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1373                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1374
1375 enum i40e_filter_type {
1376         I40E_FLOW_DIRECTOR_FLTR = 0,
1377         I40E_PE_QUAD_HASH_FLTR = 1,
1378         I40E_ETHERTYPE_FLTR,
1379         I40E_FCOE_CTX_FLTR,
1380         I40E_MAC_VLAN_FLTR,
1381         I40E_HASH_FLTR
1382 };
1383
1384 struct i40e_vsi_context {
1385         u16 seid;
1386         u16 uplink_seid;
1387         u16 vsi_number;
1388         u16 vsis_allocated;
1389         u16 vsis_unallocated;
1390         u16 flags;
1391         u8 pf_num;
1392         u8 vf_num;
1393         u8 connection_type;
1394         struct i40e_aqc_vsi_properties_data info;
1395 };
1396
1397 struct i40e_veb_context {
1398         u16 seid;
1399         u16 uplink_seid;
1400         u16 veb_number;
1401         u16 vebs_allocated;
1402         u16 vebs_unallocated;
1403         u16 flags;
1404         struct i40e_aqc_get_veb_parameters_completion info;
1405 };
1406
1407 /* Statistics collected by each port, VSI, VEB, and S-channel */
1408 struct i40e_eth_stats {
1409         u64 rx_bytes;                   /* gorc */
1410         u64 rx_unicast;                 /* uprc */
1411         u64 rx_multicast;               /* mprc */
1412         u64 rx_broadcast;               /* bprc */
1413         u64 rx_discards;                /* rdpc */
1414         u64 rx_unknown_protocol;        /* rupp */
1415         u64 tx_bytes;                   /* gotc */
1416         u64 tx_unicast;                 /* uptc */
1417         u64 tx_multicast;               /* mptc */
1418         u64 tx_broadcast;               /* bptc */
1419         u64 tx_discards;                /* tdpc */
1420         u64 tx_errors;                  /* tepc */
1421 };
1422
1423 /* Statistics collected per VEB per TC */
1424 struct i40e_veb_tc_stats {
1425         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1426         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1427         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1428         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1429 };
1430
1431 /* Statistics collected per function for FCoE */
1432 struct i40e_fcoe_stats {
1433         u64 rx_fcoe_packets;            /* fcoeprc */
1434         u64 rx_fcoe_dwords;             /* focedwrc */
1435         u64 rx_fcoe_dropped;            /* fcoerpdc */
1436         u64 tx_fcoe_packets;            /* fcoeptc */
1437         u64 tx_fcoe_dwords;             /* focedwtc */
1438         u64 fcoe_bad_fccrc;             /* fcoecrc */
1439         u64 fcoe_last_error;            /* fcoelast */
1440         u64 fcoe_ddp_count;             /* fcoeddpc */
1441 };
1442
1443 /* offset to per function FCoE statistics block */
1444 #define I40E_FCOE_VF_STAT_OFFSET        0
1445 #define I40E_FCOE_PF_STAT_OFFSET        128
1446 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1447
1448 /* Statistics collected by the MAC */
1449 struct i40e_hw_port_stats {
1450         /* eth stats collected by the port */
1451         struct i40e_eth_stats eth;
1452
1453         /* additional port specific stats */
1454         u64 tx_dropped_link_down;       /* tdold */
1455         u64 crc_errors;                 /* crcerrs */
1456         u64 illegal_bytes;              /* illerrc */
1457         u64 error_bytes;                /* errbc */
1458         u64 mac_local_faults;           /* mlfc */
1459         u64 mac_remote_faults;          /* mrfc */
1460         u64 rx_length_errors;           /* rlec */
1461         u64 link_xon_rx;                /* lxonrxc */
1462         u64 link_xoff_rx;               /* lxoffrxc */
1463         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1464         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1465         u64 link_xon_tx;                /* lxontxc */
1466         u64 link_xoff_tx;               /* lxofftxc */
1467         u64 priority_xon_tx[8];         /* pxontxc[8] */
1468         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1469         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1470         u64 rx_size_64;                 /* prc64 */
1471         u64 rx_size_127;                /* prc127 */
1472         u64 rx_size_255;                /* prc255 */
1473         u64 rx_size_511;                /* prc511 */
1474         u64 rx_size_1023;               /* prc1023 */
1475         u64 rx_size_1522;               /* prc1522 */
1476         u64 rx_size_big;                /* prc9522 */
1477         u64 rx_undersize;               /* ruc */
1478         u64 rx_fragments;               /* rfc */
1479         u64 rx_oversize;                /* roc */
1480         u64 rx_jabber;                  /* rjc */
1481         u64 tx_size_64;                 /* ptc64 */
1482         u64 tx_size_127;                /* ptc127 */
1483         u64 tx_size_255;                /* ptc255 */
1484         u64 tx_size_511;                /* ptc511 */
1485         u64 tx_size_1023;               /* ptc1023 */
1486         u64 tx_size_1522;               /* ptc1522 */
1487         u64 tx_size_big;                /* ptc9522 */
1488         u64 mac_short_packet_dropped;   /* mspdc */
1489         u64 checksum_error;             /* xec */
1490         /* flow director stats */
1491         u64 fd_atr_match;
1492         u64 fd_sb_match;
1493         u64 fd_atr_tunnel_match;
1494         u32 fd_atr_status;
1495         u32 fd_sb_status;
1496         /* EEE LPI */
1497         u32 tx_lpi_status;
1498         u32 rx_lpi_status;
1499         u64 tx_lpi_count;               /* etlpic */
1500         u64 rx_lpi_count;               /* erlpic */
1501 };
1502
1503 /* Checksum and Shadow RAM pointers */
1504 #define I40E_SR_NVM_CONTROL_WORD                0x00
1505 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1506 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1507 #define I40E_SR_OPTION_ROM_PTR                  0x05
1508 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1509 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1510 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1511 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1512 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1513 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1514 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1515 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1516 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1517 #define I40E_EMP_MODULE_PTR                     0x0F
1518 #define I40E_SR_EMP_MODULE_PTR                  0x48
1519 #define I40E_SR_PBA_FLAGS                       0x15
1520 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1521 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1522 #define I40E_NVM_OEM_VER_OFF                    0x83
1523 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1524 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1525 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1526 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1527 #define I40E_SR_NVM_MAP_VERSION                 0x29
1528 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1529 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1530 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1531 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1532 #define I40E_SR_VPD_PTR                         0x2F
1533 #define I40E_SR_PXE_SETUP_PTR                   0x30
1534 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1535 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1536 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1537 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1538 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1539 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1540 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1541 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1542 #define I40E_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1543 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1544 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1545 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1546 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1547 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1548 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1549 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1550 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1551 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1552 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1553
1554 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1555 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1556 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1557 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1558 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1559 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID   BIT(5)
1560 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1561 #define I40E_PTR_TYPE                           BIT(15)
1562 #define I40E_SR_OCP_CFG_WORD0                   0x2B
1563 #define I40E_SR_OCP_ENABLED                     BIT(15)
1564
1565 /* Shadow RAM related */
1566 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1567 #define I40E_SR_BUF_ALIGNMENT           4096
1568 #define I40E_SR_WORDS_IN_1KB            512
1569 /* Checksum should be calculated such that after adding all the words,
1570  * including the checksum word itself, the sum should be 0xBABA.
1571  */
1572 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1573
1574 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1575
1576 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1577
1578 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1579         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1580         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1581         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1582         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1583         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1584         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1585         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1586         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1587         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1588         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1589         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1590         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1591         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1592 };
1593
1594 /* FCoE DIF/DIX Context descriptor */
1595 struct i40e_fcoe_difdix_context_desc {
1596         __le64 flags_buff0_buff1_ref;
1597         __le64 difapp_msk_bias;
1598 };
1599
1600 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1601 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1602                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1603
1604 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1605         /* 2 BITS */
1606         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1607         /* 1 BIT  */
1608         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1609         /* 1 BIT  */
1610         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1611         /* 2 BITS */
1612         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1613         /* 2 BITS */
1614         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1615         /* 2 BITS */
1616         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1617         /* 2 BITS */
1618         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1619         /* 2 BITS */
1620         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1621         /* 2 BITS */
1622         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1623         /* 2 BITS */
1624         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1625         /* 2 BITS */
1626         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1627         /* 1 BIT  */
1628         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1629         /* 1 BIT  */
1630         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1631         /* 2 BITS */
1632         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1633         /* 2 BITS */
1634         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1635         /* 2 BITS */
1636         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1637         /* 2 BITS */
1638         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1639         /* 1 BIT  */
1640         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1641         /* 1 BIT  */
1642         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1643         /* 1 BIT */
1644         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1645         /* 1 BIT */
1646         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1647 };
1648
1649 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1650 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1651                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1652
1653 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1654 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1655                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1656
1657 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1658 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1659                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1660
1661 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1662 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1663                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1664
1665 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1666 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1667                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1668
1669 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1670 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1671                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1672
1673 /* FCoE DIF/DIX Buffers descriptor */
1674 struct i40e_fcoe_difdix_buffers_desc {
1675         __le64 buff_addr0;
1676         __le64 buff_addr1;
1677 };
1678
1679 /* FCoE DDP Context descriptor */
1680 struct i40e_fcoe_ddp_context_desc {
1681         __le64 rsvd;
1682         __le64 type_cmd_foff_lsize;
1683 };
1684
1685 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1686 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1687                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1688
1689 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1690 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1691                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1692
1693 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1694         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1695         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1696         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1697         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1698         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1699         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1700 };
1701
1702 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1703 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1704                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1705
1706 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1707 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1708                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1709
1710 /* FCoE DDP/DWO Queue Context descriptor */
1711 struct i40e_fcoe_queue_context_desc {
1712         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1713         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1714 };
1715
1716 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1717 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1718                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1719
1720 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1721 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1722                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1723
1724 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1725 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1726                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1727
1728 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1729 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1730                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1731
1732 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1733         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1734         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1735 };
1736
1737 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1738 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1739                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1740
1741 /* FCoE DDP/DWO Filter Context descriptor */
1742 struct i40e_fcoe_filter_context_desc {
1743         __le32 param;
1744         __le16 seqn;
1745
1746         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1747         __le16 rsvd_dmaindx;
1748
1749         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1750         __le64 flags_rsvd_lanq;
1751 };
1752
1753 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1754 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1755                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1756
1757 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1758         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1759         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1760         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1761         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1762         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1763         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1764 };
1765
1766 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1767 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1768                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1769
1770 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1771 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1772                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1773
1774 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1775 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1776                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1777
1778 enum i40e_switch_element_types {
1779         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1780         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1781         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1782         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1783         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1784         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1785         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1786         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1787         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1788 };
1789
1790 /* Supported EtherType filters */
1791 enum i40e_ether_type_index {
1792         I40E_ETHER_TYPE_1588            = 0,
1793         I40E_ETHER_TYPE_FIP             = 1,
1794         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1795         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1796         I40E_ETHER_TYPE_LLDP            = 4,
1797         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1798         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1799         I40E_ETHER_TYPE_QCN_CNM         = 7,
1800         I40E_ETHER_TYPE_8021X           = 8,
1801         I40E_ETHER_TYPE_ARP             = 9,
1802         I40E_ETHER_TYPE_RSV1            = 10,
1803         I40E_ETHER_TYPE_RSV2            = 11,
1804 };
1805
1806 /* Filter context base size is 1K */
1807 #define I40E_HASH_FILTER_BASE_SIZE      1024
1808 /* Supported Hash filter values */
1809 enum i40e_hash_filter_size {
1810         I40E_HASH_FILTER_SIZE_1K        = 0,
1811         I40E_HASH_FILTER_SIZE_2K        = 1,
1812         I40E_HASH_FILTER_SIZE_4K        = 2,
1813         I40E_HASH_FILTER_SIZE_8K        = 3,
1814         I40E_HASH_FILTER_SIZE_16K       = 4,
1815         I40E_HASH_FILTER_SIZE_32K       = 5,
1816         I40E_HASH_FILTER_SIZE_64K       = 6,
1817         I40E_HASH_FILTER_SIZE_128K      = 7,
1818         I40E_HASH_FILTER_SIZE_256K      = 8,
1819         I40E_HASH_FILTER_SIZE_512K      = 9,
1820         I40E_HASH_FILTER_SIZE_1M        = 10,
1821 };
1822
1823 /* DMA context base size is 0.5K */
1824 #define I40E_DMA_CNTX_BASE_SIZE         512
1825 /* Supported DMA context values */
1826 enum i40e_dma_cntx_size {
1827         I40E_DMA_CNTX_SIZE_512          = 0,
1828         I40E_DMA_CNTX_SIZE_1K           = 1,
1829         I40E_DMA_CNTX_SIZE_2K           = 2,
1830         I40E_DMA_CNTX_SIZE_4K           = 3,
1831         I40E_DMA_CNTX_SIZE_8K           = 4,
1832         I40E_DMA_CNTX_SIZE_16K          = 5,
1833         I40E_DMA_CNTX_SIZE_32K          = 6,
1834         I40E_DMA_CNTX_SIZE_64K          = 7,
1835         I40E_DMA_CNTX_SIZE_128K         = 8,
1836         I40E_DMA_CNTX_SIZE_256K         = 9,
1837 };
1838
1839 /* Supported Hash look up table (LUT) sizes */
1840 enum i40e_hash_lut_size {
1841         I40E_HASH_LUT_SIZE_128          = 0,
1842         I40E_HASH_LUT_SIZE_512          = 1,
1843 };
1844
1845 /* Structure to hold a per PF filter control settings */
1846 struct i40e_filter_control_settings {
1847         /* number of PE Quad Hash filter buckets */
1848         enum i40e_hash_filter_size pe_filt_num;
1849         /* number of PE Quad Hash contexts */
1850         enum i40e_dma_cntx_size pe_cntx_num;
1851         /* number of FCoE filter buckets */
1852         enum i40e_hash_filter_size fcoe_filt_num;
1853         /* number of FCoE DDP contexts */
1854         enum i40e_dma_cntx_size fcoe_cntx_num;
1855         /* size of the Hash LUT */
1856         enum i40e_hash_lut_size hash_lut_size;
1857         /* enable FDIR filters for PF and its VFs */
1858         bool enable_fdir;
1859         /* enable Ethertype filters for PF and its VFs */
1860         bool enable_ethtype;
1861         /* enable MAC/VLAN filters for PF and its VFs */
1862         bool enable_macvlan;
1863 };
1864
1865 /* Structure to hold device level control filter counts */
1866 struct i40e_control_filter_stats {
1867         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1868         u16 etype_used;       /* Used perfect EtherType filters */
1869         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1870         u16 etype_free;       /* Un-used perfect EtherType filters */
1871 };
1872
1873 enum i40e_reset_type {
1874         I40E_RESET_POR          = 0,
1875         I40E_RESET_CORER        = 1,
1876         I40E_RESET_GLOBR        = 2,
1877         I40E_RESET_EMPR         = 3,
1878 };
1879
1880 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1881 #define I40E_NVM_LLDP_CFG_PTR   0x06
1882 #define I40E_SR_LLDP_CFG_PTR    0x31
1883 struct i40e_lldp_variables {
1884         u16 length;
1885         u16 adminstatus;
1886         u16 msgfasttx;
1887         u16 msgtxinterval;
1888         u16 txparams;
1889         u16 timers;
1890         u16 crc8;
1891 };
1892
1893 /* Offsets into Alternate Ram */
1894 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1895 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1896 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1897 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1898 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1899 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1900
1901 /* Alternate Ram Bandwidth Masks */
1902 #define I40E_ALT_BW_VALUE_MASK          0xFF
1903 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1904 #define I40E_ALT_BW_VALID_MASK          0x80000000
1905
1906 /* RSS Hash Table Size */
1907 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1908
1909 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1910 #define I40E_L3_SRC_SHIFT               47
1911 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1912 #define I40E_L3_V6_SRC_SHIFT            43
1913 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1914 #define I40E_L3_DST_SHIFT               35
1915 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1916 #define I40E_L3_V6_DST_SHIFT            35
1917 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1918 #define I40E_L4_SRC_SHIFT               34
1919 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1920 #define I40E_L4_DST_SHIFT               33
1921 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1922 #define I40E_VERIFY_TAG_SHIFT           31
1923 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1924
1925 #define I40E_FLEX_50_SHIFT              13
1926 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1927 #define I40E_FLEX_51_SHIFT              12
1928 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1929 #define I40E_FLEX_52_SHIFT              11
1930 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1931 #define I40E_FLEX_53_SHIFT              10
1932 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1933 #define I40E_FLEX_54_SHIFT              9
1934 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1935 #define I40E_FLEX_55_SHIFT              8
1936 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1937 #define I40E_FLEX_56_SHIFT              7
1938 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1939 #define I40E_FLEX_57_SHIFT              6
1940 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1941
1942 /* Version format for Dynamic Device Personalization(DDP) */
1943 struct i40e_ddp_version {
1944         u8 major;
1945         u8 minor;
1946         u8 update;
1947         u8 draft;
1948 };
1949
1950 #define I40E_DDP_NAME_SIZE      32
1951
1952 /* Package header */
1953 struct i40e_package_header {
1954         struct i40e_ddp_version version;
1955         u32 segment_count;
1956         u32 segment_offset[1];
1957 };
1958
1959 /* Generic segment header */
1960 struct i40e_generic_seg_header {
1961 #define SEGMENT_TYPE_METADATA   0x00000001
1962 #define SEGMENT_TYPE_NOTES      0x00000002
1963 #define SEGMENT_TYPE_I40E       0x00000011
1964 #define SEGMENT_TYPE_X722       0x00000012
1965         u32 type;
1966         struct i40e_ddp_version version;
1967         u32 size;
1968         char name[I40E_DDP_NAME_SIZE];
1969 };
1970
1971 struct i40e_metadata_segment {
1972         struct i40e_generic_seg_header header;
1973         struct i40e_ddp_version version;
1974 #define I40E_DDP_TRACKID_RDONLY         0
1975 #define I40E_DDP_TRACKID_INVALID        0xFFFFFFFF
1976         u32 track_id;
1977         char name[I40E_DDP_NAME_SIZE];
1978 };
1979
1980 struct i40e_device_id_entry {
1981         u32 vendor_dev_id;
1982         u32 sub_vendor_dev_id;
1983 };
1984
1985 struct i40e_profile_segment {
1986         struct i40e_generic_seg_header header;
1987         struct i40e_ddp_version version;
1988         char name[I40E_DDP_NAME_SIZE];
1989         u32 device_table_count;
1990         struct i40e_device_id_entry device_table[1];
1991 };
1992
1993 struct i40e_section_table {
1994         u32 section_count;
1995         u32 section_offset[1];
1996 };
1997
1998 struct i40e_profile_section_header {
1999         u16 tbl_size;
2000         u16 data_end;
2001         struct {
2002 #define SECTION_TYPE_INFO       0x00000010
2003 #define SECTION_TYPE_MMIO       0x00000800
2004 #define SECTION_TYPE_RB_MMIO    0x00001800
2005 #define SECTION_TYPE_AQ         0x00000801
2006 #define SECTION_TYPE_RB_AQ      0x00001801
2007 #define SECTION_TYPE_NOTE       0x80000000
2008 #define SECTION_TYPE_NAME       0x80000001
2009 #define SECTION_TYPE_PROTO      0x80000002
2010 #define SECTION_TYPE_PCTYPE     0x80000003
2011 #define SECTION_TYPE_PTYPE      0x80000004
2012                 u32 type;
2013                 u32 offset;
2014                 u32 size;
2015         } section;
2016 };
2017
2018 struct i40e_profile_tlv_section_record {
2019         u8 rtype;
2020         u8 type;
2021         u16 len;
2022         u8 data[12];
2023 };
2024
2025 /* Generic AQ section in proflie */
2026 struct i40e_profile_aq_section {
2027         u16 opcode;
2028         u16 flags;
2029         u8  param[16];
2030         u16 datalen;
2031         u8  data[1];
2032 };
2033
2034 struct i40e_profile_info {
2035         u32 track_id;
2036         struct i40e_ddp_version version;
2037         u8 op;
2038 #define I40E_DDP_ADD_TRACKID            0x01
2039 #define I40E_DDP_REMOVE_TRACKID 0x02
2040         u8 reserved[7];
2041         u8 name[I40E_DDP_NAME_SIZE];
2042 };
2043
2044 #define I40E_BCM_PHY_PCS_STATUS1_PAGE   0x3
2045 #define I40E_BCM_PHY_PCS_STATUS1_REG    0x0001
2046 #define I40E_BCM_PHY_PCS_STATUS1_RX_LPI BIT(8)
2047 #define I40E_BCM_PHY_PCS_STATUS1_TX_LPI BIT(9)
2048
2049 #endif /* _I40E_TYPE_H_ */