4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and interval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control default high water */
90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
92 /* Flow control default low water */
93 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
95 /* Flow control enable fwd bit */
96 #define I40E_PRTMAC_FWD_CTRL 0x00000001
98 /* Receive Packet Buffer size */
99 #define I40E_RXPBSIZE (968 * 1024)
101 /* Kilobytes shift */
102 #define I40E_KILOSHIFT 10
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
260 struct rte_eth_stats *stats);
261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
262 struct rte_eth_xstat *xstats, unsigned n);
263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
264 struct rte_eth_xstat_name *xstats_names,
266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
272 char *fw_version, size_t fw_size);
273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
274 struct rte_eth_dev_info *dev_info);
275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
279 enum rte_vlan_type vlan_type,
281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
289 struct rte_eth_fc_conf *fc_conf);
290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
291 struct rte_eth_fc_conf *fc_conf);
292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
293 struct rte_eth_pfc_conf *pfc_conf);
294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
295 struct ether_addr *mac_addr,
298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
300 struct rte_eth_rss_reta_entry64 *reta_conf,
302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
303 struct rte_eth_rss_reta_entry64 *reta_conf,
306 static int i40e_get_cap(struct i40e_hw *hw);
307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
308 static int i40e_pf_setup(struct i40e_pf *pf);
309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
314 bool offset_loaded, uint64_t *offset, uint64_t *stat);
315 static void i40e_stat_update_48(struct i40e_hw *hw,
321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
322 static void i40e_dev_interrupt_handler(void *param);
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
342 struct rte_eth_rss_conf *rss_conf);
343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
344 struct rte_eth_rss_conf *rss_conf);
345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
346 struct rte_eth_udp_tunnel *udp_tunnel);
347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
348 struct rte_eth_udp_tunnel *udp_tunnel);
349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
351 enum rte_filter_op filter_op,
353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
354 enum rte_filter_type filter_type,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
358 struct rte_eth_dcb_info *dcb_info);
359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
360 static void i40e_configure_registers(struct i40e_hw *hw);
361 static void i40e_hw_init(struct rte_eth_dev *dev);
362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
364 struct rte_eth_mirror_conf *mirror_conf,
365 uint8_t sw_id, uint8_t on);
366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
371 struct timespec *timestamp,
373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
374 struct timespec *timestamp);
375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
380 struct timespec *timestamp);
381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
382 const struct timespec *timestamp);
384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
389 static int i40e_get_regs(struct rte_eth_dev *dev,
390 struct rte_dev_reg_info *regs);
392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
395 struct rte_dev_eeprom_info *eeprom);
397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
398 struct ether_addr *mac_addr);
400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
402 static int i40e_ethertype_filter_convert(
403 const struct rte_eth_ethertype_filter *input,
404 struct i40e_ethertype_filter *filter);
405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
406 struct i40e_ethertype_filter *filter);
408 static int i40e_tunnel_filter_convert(
409 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
410 struct i40e_tunnel_filter *tunnel_filter);
411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
412 struct i40e_tunnel_filter *tunnel_filter);
413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
417 static void i40e_filter_restore(struct i40e_pf *pf);
418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
420 int i40e_logtype_init;
421 int i40e_logtype_driver;
423 static const struct rte_pci_id pci_id_i40e_map[] = {
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
444 { .vendor_id = 0, /* sentinel */ },
447 static const struct eth_dev_ops i40e_eth_dev_ops = {
448 .dev_configure = i40e_dev_configure,
449 .dev_start = i40e_dev_start,
450 .dev_stop = i40e_dev_stop,
451 .dev_close = i40e_dev_close,
452 .promiscuous_enable = i40e_dev_promiscuous_enable,
453 .promiscuous_disable = i40e_dev_promiscuous_disable,
454 .allmulticast_enable = i40e_dev_allmulticast_enable,
455 .allmulticast_disable = i40e_dev_allmulticast_disable,
456 .dev_set_link_up = i40e_dev_set_link_up,
457 .dev_set_link_down = i40e_dev_set_link_down,
458 .link_update = i40e_dev_link_update,
459 .stats_get = i40e_dev_stats_get,
460 .xstats_get = i40e_dev_xstats_get,
461 .xstats_get_names = i40e_dev_xstats_get_names,
462 .stats_reset = i40e_dev_stats_reset,
463 .xstats_reset = i40e_dev_stats_reset,
464 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
465 .fw_version_get = i40e_fw_version_get,
466 .dev_infos_get = i40e_dev_info_get,
467 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
468 .vlan_filter_set = i40e_vlan_filter_set,
469 .vlan_tpid_set = i40e_vlan_tpid_set,
470 .vlan_offload_set = i40e_vlan_offload_set,
471 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
472 .vlan_pvid_set = i40e_vlan_pvid_set,
473 .rx_queue_start = i40e_dev_rx_queue_start,
474 .rx_queue_stop = i40e_dev_rx_queue_stop,
475 .tx_queue_start = i40e_dev_tx_queue_start,
476 .tx_queue_stop = i40e_dev_tx_queue_stop,
477 .rx_queue_setup = i40e_dev_rx_queue_setup,
478 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
479 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
480 .rx_queue_release = i40e_dev_rx_queue_release,
481 .rx_queue_count = i40e_dev_rx_queue_count,
482 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
483 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
484 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
485 .tx_queue_setup = i40e_dev_tx_queue_setup,
486 .tx_queue_release = i40e_dev_tx_queue_release,
487 .dev_led_on = i40e_dev_led_on,
488 .dev_led_off = i40e_dev_led_off,
489 .flow_ctrl_get = i40e_flow_ctrl_get,
490 .flow_ctrl_set = i40e_flow_ctrl_set,
491 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
492 .mac_addr_add = i40e_macaddr_add,
493 .mac_addr_remove = i40e_macaddr_remove,
494 .reta_update = i40e_dev_rss_reta_update,
495 .reta_query = i40e_dev_rss_reta_query,
496 .rss_hash_update = i40e_dev_rss_hash_update,
497 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
498 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
499 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
500 .filter_ctrl = i40e_dev_filter_ctrl,
501 .rxq_info_get = i40e_rxq_info_get,
502 .txq_info_get = i40e_txq_info_get,
503 .mirror_rule_set = i40e_mirror_rule_set,
504 .mirror_rule_reset = i40e_mirror_rule_reset,
505 .timesync_enable = i40e_timesync_enable,
506 .timesync_disable = i40e_timesync_disable,
507 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
508 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
509 .get_dcb_info = i40e_dev_get_dcb_info,
510 .timesync_adjust_time = i40e_timesync_adjust_time,
511 .timesync_read_time = i40e_timesync_read_time,
512 .timesync_write_time = i40e_timesync_write_time,
513 .get_reg = i40e_get_regs,
514 .get_eeprom_length = i40e_get_eeprom_length,
515 .get_eeprom = i40e_get_eeprom,
516 .mac_addr_set = i40e_set_default_mac_addr,
517 .mtu_set = i40e_dev_mtu_set,
520 /* store statistics names and its offset in stats structure */
521 struct rte_i40e_xstats_name_off {
522 char name[RTE_ETH_XSTATS_NAME_SIZE];
526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
527 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
528 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
529 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
530 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
531 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
532 rx_unknown_protocol)},
533 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
534 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
535 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
536 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
540 sizeof(rte_i40e_stats_strings[0]))
542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
543 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
544 tx_dropped_link_down)},
545 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
546 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
548 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
549 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
551 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
555 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
556 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
557 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
558 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
559 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
560 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
577 mac_short_packet_dropped)},
578 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
580 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
581 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
582 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
594 {"rx_flow_director_atr_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
596 {"rx_flow_director_sb_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
598 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
604 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
609 sizeof(rte_i40e_hw_port_strings[0]))
611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
612 {"xon_packets", offsetof(struct i40e_hw_port_stats,
614 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
619 sizeof(rte_i40e_rxq_prio_strings[0]))
621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
622 {"xon_packets", offsetof(struct i40e_hw_port_stats,
624 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
626 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
627 priority_xon_2_xoff)},
630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
631 sizeof(rte_i40e_txq_prio_strings[0]))
633 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
634 struct rte_pci_device *pci_dev)
636 return rte_eth_dev_pci_generic_probe(pci_dev,
637 sizeof(struct i40e_adapter), eth_i40e_dev_init);
640 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
642 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
645 static struct rte_pci_driver rte_i40e_pmd = {
646 .id_table = pci_id_i40e_map,
647 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
648 .probe = eth_i40e_pci_probe,
649 .remove = eth_i40e_pci_remove,
653 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
654 struct rte_eth_link *link)
656 struct rte_eth_link *dst = link;
657 struct rte_eth_link *src = &(dev->data->dev_link);
659 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
660 *(uint64_t *)src) == 0)
667 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
668 struct rte_eth_link *link)
670 struct rte_eth_link *dst = &(dev->data->dev_link);
671 struct rte_eth_link *src = link;
673 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
674 *(uint64_t *)src) == 0)
680 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
681 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
682 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
684 #ifndef I40E_GLQF_ORT
685 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
687 #ifndef I40E_GLQF_PIT
688 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
690 #ifndef I40E_GLQF_L3_MAP
691 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
694 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
697 * Initialize registers for flexible payload, which should be set by NVM.
698 * This should be removed from code once it is fixed in NVM.
700 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
710 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
711 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
713 /* Initialize registers for parsing packet type of QinQ */
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
715 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
718 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
721 * Add a ethertype filter to drop all flow control frames transmitted
725 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
727 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
728 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
729 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
730 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
733 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
734 I40E_FLOW_CONTROL_ETHERTYPE, flags,
735 pf->main_vsi_seid, 0,
739 "Failed to add filter to drop flow control frames from VSIs.");
743 floating_veb_list_handler(__rte_unused const char *key,
744 const char *floating_veb_value,
748 unsigned int count = 0;
751 bool *vf_floating_veb = opaque;
753 while (isblank(*floating_veb_value))
754 floating_veb_value++;
756 /* Reset floating VEB configuration for VFs */
757 for (idx = 0; idx < I40E_MAX_VF; idx++)
758 vf_floating_veb[idx] = false;
762 while (isblank(*floating_veb_value))
763 floating_veb_value++;
764 if (*floating_veb_value == '\0')
767 idx = strtoul(floating_veb_value, &end, 10);
768 if (errno || end == NULL)
770 while (isblank(*end))
774 } else if ((*end == ';') || (*end == '\0')) {
776 if (min == I40E_MAX_VF)
778 if (max >= I40E_MAX_VF)
779 max = I40E_MAX_VF - 1;
780 for (idx = min; idx <= max; idx++) {
781 vf_floating_veb[idx] = true;
788 floating_veb_value = end + 1;
789 } while (*end != '\0');
798 config_vf_floating_veb(struct rte_devargs *devargs,
799 uint16_t floating_veb,
800 bool *vf_floating_veb)
802 struct rte_kvargs *kvlist;
804 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
808 /* All the VFs attach to the floating VEB by default
809 * when the floating VEB is enabled.
811 for (i = 0; i < I40E_MAX_VF; i++)
812 vf_floating_veb[i] = true;
817 kvlist = rte_kvargs_parse(devargs->args, NULL);
821 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
822 rte_kvargs_free(kvlist);
825 /* When the floating_veb_list parameter exists, all the VFs
826 * will attach to the legacy VEB firstly, then configure VFs
827 * to the floating VEB according to the floating_veb_list.
829 if (rte_kvargs_process(kvlist, floating_veb_list,
830 floating_veb_list_handler,
831 vf_floating_veb) < 0) {
832 rte_kvargs_free(kvlist);
835 rte_kvargs_free(kvlist);
839 i40e_check_floating_handler(__rte_unused const char *key,
841 __rte_unused void *opaque)
843 if (strcmp(value, "1"))
850 is_floating_veb_supported(struct rte_devargs *devargs)
852 struct rte_kvargs *kvlist;
853 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
858 kvlist = rte_kvargs_parse(devargs->args, NULL);
862 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
863 rte_kvargs_free(kvlist);
866 /* Floating VEB is enabled when there's key-value:
867 * enable_floating_veb=1
869 if (rte_kvargs_process(kvlist, floating_veb_key,
870 i40e_check_floating_handler, NULL) < 0) {
871 rte_kvargs_free(kvlist);
874 rte_kvargs_free(kvlist);
880 config_floating_veb(struct rte_eth_dev *dev)
882 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
883 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
884 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
886 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
888 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
890 is_floating_veb_supported(pci_dev->device.devargs);
891 config_vf_floating_veb(pci_dev->device.devargs,
893 pf->floating_veb_list);
895 pf->floating_veb = false;
899 #define I40E_L2_TAGS_S_TAG_SHIFT 1
900 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
903 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
905 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
906 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
907 char ethertype_hash_name[RTE_HASH_NAMESIZE];
910 struct rte_hash_parameters ethertype_hash_params = {
911 .name = ethertype_hash_name,
912 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
913 .key_len = sizeof(struct i40e_ethertype_filter_input),
914 .hash_func = rte_hash_crc,
915 .hash_func_init_val = 0,
916 .socket_id = rte_socket_id(),
919 /* Initialize ethertype filter rule list and hash */
920 TAILQ_INIT(ðertype_rule->ethertype_list);
921 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
922 "ethertype_%s", dev->device->name);
923 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
924 if (!ethertype_rule->hash_table) {
925 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
928 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
929 sizeof(struct i40e_ethertype_filter *) *
930 I40E_MAX_ETHERTYPE_FILTER_NUM,
932 if (!ethertype_rule->hash_map) {
934 "Failed to allocate memory for ethertype hash map!");
936 goto err_ethertype_hash_map_alloc;
941 err_ethertype_hash_map_alloc:
942 rte_hash_free(ethertype_rule->hash_table);
948 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
950 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
951 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
952 char tunnel_hash_name[RTE_HASH_NAMESIZE];
955 struct rte_hash_parameters tunnel_hash_params = {
956 .name = tunnel_hash_name,
957 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
958 .key_len = sizeof(struct i40e_tunnel_filter_input),
959 .hash_func = rte_hash_crc,
960 .hash_func_init_val = 0,
961 .socket_id = rte_socket_id(),
964 /* Initialize tunnel filter rule list and hash */
965 TAILQ_INIT(&tunnel_rule->tunnel_list);
966 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
967 "tunnel_%s", dev->device->name);
968 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
969 if (!tunnel_rule->hash_table) {
970 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
973 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
974 sizeof(struct i40e_tunnel_filter *) *
975 I40E_MAX_TUNNEL_FILTER_NUM,
977 if (!tunnel_rule->hash_map) {
979 "Failed to allocate memory for tunnel hash map!");
981 goto err_tunnel_hash_map_alloc;
986 err_tunnel_hash_map_alloc:
987 rte_hash_free(tunnel_rule->hash_table);
993 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
996 struct i40e_fdir_info *fdir_info = &pf->fdir;
997 char fdir_hash_name[RTE_HASH_NAMESIZE];
1000 struct rte_hash_parameters fdir_hash_params = {
1001 .name = fdir_hash_name,
1002 .entries = I40E_MAX_FDIR_FILTER_NUM,
1003 .key_len = sizeof(struct rte_eth_fdir_input),
1004 .hash_func = rte_hash_crc,
1005 .hash_func_init_val = 0,
1006 .socket_id = rte_socket_id(),
1009 /* Initialize flow director filter rule list and hash */
1010 TAILQ_INIT(&fdir_info->fdir_list);
1011 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1012 "fdir_%s", dev->device->name);
1013 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1014 if (!fdir_info->hash_table) {
1015 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1018 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1019 sizeof(struct i40e_fdir_filter *) *
1020 I40E_MAX_FDIR_FILTER_NUM,
1022 if (!fdir_info->hash_map) {
1024 "Failed to allocate memory for fdir hash map!");
1026 goto err_fdir_hash_map_alloc;
1030 err_fdir_hash_map_alloc:
1031 rte_hash_free(fdir_info->hash_table);
1037 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 struct rte_pci_device *pci_dev;
1040 struct rte_intr_handle *intr_handle;
1041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 struct i40e_vsi *vsi;
1046 uint8_t aq_fail = 0;
1048 PMD_INIT_FUNC_TRACE();
1050 dev->dev_ops = &i40e_eth_dev_ops;
1051 dev->rx_pkt_burst = i40e_recv_pkts;
1052 dev->tx_pkt_burst = i40e_xmit_pkts;
1053 dev->tx_pkt_prepare = i40e_prep_pkts;
1055 /* for secondary processes, we don't initialise any further as primary
1056 * has already done this work. Only check we don't need a different
1058 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1059 i40e_set_rx_function(dev);
1060 i40e_set_tx_function(dev);
1063 i40e_set_default_ptype_table(dev);
1064 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1065 intr_handle = &pci_dev->intr_handle;
1067 rte_eth_copy_pci_info(dev, pci_dev);
1068 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1071 pf->adapter->eth_dev = dev;
1072 pf->dev_data = dev->data;
1074 hw->back = I40E_PF_TO_ADAPTER(pf);
1075 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1078 "Hardware is not available, as address is NULL");
1082 hw->vendor_id = pci_dev->id.vendor_id;
1083 hw->device_id = pci_dev->id.device_id;
1084 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1085 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1086 hw->bus.device = pci_dev->addr.devid;
1087 hw->bus.func = pci_dev->addr.function;
1088 hw->adapter_stopped = 0;
1090 /* Make sure all is clean before doing PF reset */
1093 /* Initialize the hardware */
1096 /* Reset here to make sure all is clean for each PF */
1097 ret = i40e_pf_reset(hw);
1099 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1103 /* Initialize the shared code (base driver) */
1104 ret = i40e_init_shared_code(hw);
1106 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1111 * To work around the NVM issue, initialize registers
1112 * for flexible payload and packet type of QinQ by
1113 * software. It should be removed once issues are fixed
1116 i40e_GLQF_reg_init(hw);
1118 /* Initialize the input set for filters (hash and fd) to default value */
1119 i40e_filter_input_set_init(pf);
1121 /* Initialize the parameters for adminq */
1122 i40e_init_adminq_parameter(hw);
1123 ret = i40e_init_adminq(hw);
1124 if (ret != I40E_SUCCESS) {
1125 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1128 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1129 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1130 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1131 ((hw->nvm.version >> 12) & 0xf),
1132 ((hw->nvm.version >> 4) & 0xff),
1133 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135 /* initialise the L3_MAP register */
1136 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1139 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141 /* Need the special FW version to support floating VEB */
1142 config_floating_veb(dev);
1143 /* Clear PXE mode */
1144 i40e_clear_pxe_mode(hw);
1145 i40e_dev_sync_phy_type(hw);
1148 * On X710, performance number is far from the expectation on recent
1149 * firmware versions. The fix for this issue may not be integrated in
1150 * the following firmware version. So the workaround in software driver
1151 * is needed. It needs to modify the initial values of 3 internal only
1152 * registers. Note that the workaround can be removed when it is fixed
1153 * in firmware in the future.
1155 i40e_configure_registers(hw);
1157 /* Get hw capabilities */
1158 ret = i40e_get_cap(hw);
1159 if (ret != I40E_SUCCESS) {
1160 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1161 goto err_get_capabilities;
1164 /* Initialize parameters for PF */
1165 ret = i40e_pf_parameter_init(dev);
1167 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1168 goto err_parameter_init;
1171 /* Initialize the queue management */
1172 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1174 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1175 goto err_qp_pool_init;
1177 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1178 hw->func_caps.num_msix_vectors - 1);
1180 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1181 goto err_msix_pool_init;
1184 /* Initialize lan hmc */
1185 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1186 hw->func_caps.num_rx_qp, 0, 0);
1187 if (ret != I40E_SUCCESS) {
1188 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1189 goto err_init_lan_hmc;
1192 /* Configure lan hmc */
1193 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1194 if (ret != I40E_SUCCESS) {
1195 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1196 goto err_configure_lan_hmc;
1199 /* Get and check the mac address */
1200 i40e_get_mac_addr(hw, hw->mac.addr);
1201 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1202 PMD_INIT_LOG(ERR, "mac address is not valid");
1204 goto err_get_mac_addr;
1206 /* Copy the permanent MAC address */
1207 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1208 (struct ether_addr *) hw->mac.perm_addr);
1210 /* Disable flow control */
1211 hw->fc.requested_mode = I40E_FC_NONE;
1212 i40e_set_fc(hw, &aq_fail, TRUE);
1214 /* Set the global registers with default ether type value */
1215 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1216 if (ret != I40E_SUCCESS) {
1218 "Failed to set the default outer VLAN ether type");
1219 goto err_setup_pf_switch;
1222 /* PF setup, which includes VSI setup */
1223 ret = i40e_pf_setup(pf);
1225 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1226 goto err_setup_pf_switch;
1229 /* reset all stats of the device, including pf and main vsi */
1230 i40e_dev_stats_reset(dev);
1234 /* Disable double vlan by default */
1235 i40e_vsi_config_double_vlan(vsi, FALSE);
1237 /* Disable S-TAG identification when floating_veb is disabled */
1238 if (!pf->floating_veb) {
1239 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1240 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1241 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1242 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1246 if (!vsi->max_macaddrs)
1247 len = ETHER_ADDR_LEN;
1249 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1251 /* Should be after VSI initialized */
1252 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1253 if (!dev->data->mac_addrs) {
1255 "Failed to allocated memory for storing mac address");
1258 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1259 &dev->data->mac_addrs[0]);
1261 /* Init dcb to sw mode by default */
1262 ret = i40e_dcb_init_configure(dev, TRUE);
1263 if (ret != I40E_SUCCESS) {
1264 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1265 pf->flags &= ~I40E_FLAG_DCB;
1267 /* Update HW struct after DCB configuration */
1270 /* initialize pf host driver to setup SRIOV resource if applicable */
1271 i40e_pf_host_init(dev);
1273 /* register callback func to eal lib */
1274 rte_intr_callback_register(intr_handle,
1275 i40e_dev_interrupt_handler, dev);
1277 /* configure and enable device interrupt */
1278 i40e_pf_config_irq0(hw, TRUE);
1279 i40e_pf_enable_irq0(hw);
1281 /* enable uio intr after callback register */
1282 rte_intr_enable(intr_handle);
1284 * Add an ethertype filter to drop all flow control frames transmitted
1285 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1288 i40e_add_tx_flow_control_drop_filter(pf);
1290 /* Set the max frame size to 0x2600 by default,
1291 * in case other drivers changed the default value.
1293 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295 /* initialize mirror rule list */
1296 TAILQ_INIT(&pf->mirror_list);
1298 ret = i40e_init_ethtype_filter_list(dev);
1300 goto err_init_ethtype_filter_list;
1301 ret = i40e_init_tunnel_filter_list(dev);
1303 goto err_init_tunnel_filter_list;
1304 ret = i40e_init_fdir_filter_list(dev);
1306 goto err_init_fdir_filter_list;
1310 err_init_fdir_filter_list:
1311 rte_free(pf->tunnel.hash_table);
1312 rte_free(pf->tunnel.hash_map);
1313 err_init_tunnel_filter_list:
1314 rte_free(pf->ethertype.hash_table);
1315 rte_free(pf->ethertype.hash_map);
1316 err_init_ethtype_filter_list:
1317 rte_free(dev->data->mac_addrs);
1319 i40e_vsi_release(pf->main_vsi);
1320 err_setup_pf_switch:
1322 err_configure_lan_hmc:
1323 (void)i40e_shutdown_lan_hmc(hw);
1325 i40e_res_pool_destroy(&pf->msix_pool);
1327 i40e_res_pool_destroy(&pf->qp_pool);
1330 err_get_capabilities:
1331 (void)i40e_shutdown_adminq(hw);
1337 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1339 struct i40e_ethertype_filter *p_ethertype;
1340 struct i40e_ethertype_rule *ethertype_rule;
1342 ethertype_rule = &pf->ethertype;
1343 /* Remove all ethertype filter rules and hash */
1344 if (ethertype_rule->hash_map)
1345 rte_free(ethertype_rule->hash_map);
1346 if (ethertype_rule->hash_table)
1347 rte_hash_free(ethertype_rule->hash_table);
1349 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1350 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1351 p_ethertype, rules);
1352 rte_free(p_ethertype);
1357 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1359 struct i40e_tunnel_filter *p_tunnel;
1360 struct i40e_tunnel_rule *tunnel_rule;
1362 tunnel_rule = &pf->tunnel;
1363 /* Remove all tunnel director rules and hash */
1364 if (tunnel_rule->hash_map)
1365 rte_free(tunnel_rule->hash_map);
1366 if (tunnel_rule->hash_table)
1367 rte_hash_free(tunnel_rule->hash_table);
1369 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1370 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1376 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1378 struct i40e_fdir_filter *p_fdir;
1379 struct i40e_fdir_info *fdir_info;
1381 fdir_info = &pf->fdir;
1382 /* Remove all flow director rules and hash */
1383 if (fdir_info->hash_map)
1384 rte_free(fdir_info->hash_map);
1385 if (fdir_info->hash_table)
1386 rte_hash_free(fdir_info->hash_table);
1388 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1389 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1395 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1398 struct rte_pci_device *pci_dev;
1399 struct rte_intr_handle *intr_handle;
1401 struct i40e_filter_control_settings settings;
1402 struct rte_flow *p_flow;
1404 uint8_t aq_fail = 0;
1406 PMD_INIT_FUNC_TRACE();
1408 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1411 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1412 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1414 intr_handle = &pci_dev->intr_handle;
1416 if (hw->adapter_stopped == 0)
1417 i40e_dev_close(dev);
1419 dev->dev_ops = NULL;
1420 dev->rx_pkt_burst = NULL;
1421 dev->tx_pkt_burst = NULL;
1423 /* Clear PXE mode */
1424 i40e_clear_pxe_mode(hw);
1426 /* Unconfigure filter control */
1427 memset(&settings, 0, sizeof(settings));
1428 ret = i40e_set_filter_control(hw, &settings);
1430 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1433 /* Disable flow control */
1434 hw->fc.requested_mode = I40E_FC_NONE;
1435 i40e_set_fc(hw, &aq_fail, TRUE);
1437 /* uninitialize pf host driver */
1438 i40e_pf_host_uninit(dev);
1440 rte_free(dev->data->mac_addrs);
1441 dev->data->mac_addrs = NULL;
1443 /* disable uio intr before callback unregister */
1444 rte_intr_disable(intr_handle);
1446 /* register callback func to eal lib */
1447 rte_intr_callback_unregister(intr_handle,
1448 i40e_dev_interrupt_handler, dev);
1450 i40e_rm_ethtype_filter_list(pf);
1451 i40e_rm_tunnel_filter_list(pf);
1452 i40e_rm_fdir_filter_list(pf);
1454 /* Remove all flows */
1455 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1456 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1464 i40e_dev_configure(struct rte_eth_dev *dev)
1466 struct i40e_adapter *ad =
1467 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1468 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1469 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1470 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1473 ret = i40e_dev_sync_phy_type(hw);
1477 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1478 * bulk allocation or vector Rx preconditions we will reset it.
1480 ad->rx_bulk_alloc_allowed = true;
1481 ad->rx_vec_allowed = true;
1482 ad->tx_simple_allowed = true;
1483 ad->tx_vec_allowed = true;
1485 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1486 ret = i40e_fdir_setup(pf);
1487 if (ret != I40E_SUCCESS) {
1488 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1491 ret = i40e_fdir_configure(dev);
1493 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1497 i40e_fdir_teardown(pf);
1499 ret = i40e_dev_init_vlan(dev);
1504 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1505 * RSS setting have different requirements.
1506 * General PMD driver call sequence are NIC init, configure,
1507 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1508 * will try to lookup the VSI that specific queue belongs to if VMDQ
1509 * applicable. So, VMDQ setting has to be done before
1510 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1511 * For RSS setting, it will try to calculate actual configured RX queue
1512 * number, which will be available after rx_queue_setup(). dev_start()
1513 * function is good to place RSS setup.
1515 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1516 ret = i40e_vmdq_setup(dev);
1521 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1522 ret = i40e_dcb_setup(dev);
1524 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1529 TAILQ_INIT(&pf->flow_list);
1534 /* need to release vmdq resource if exists */
1535 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1536 i40e_vsi_release(pf->vmdq[i].vsi);
1537 pf->vmdq[i].vsi = NULL;
1542 /* need to release fdir resource if exists */
1543 i40e_fdir_teardown(pf);
1548 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1550 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1551 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1552 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1553 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1554 uint16_t msix_vect = vsi->msix_intr;
1557 for (i = 0; i < vsi->nb_qps; i++) {
1558 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1559 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1563 if (vsi->type != I40E_VSI_SRIOV) {
1564 if (!rte_intr_allow_others(intr_handle)) {
1565 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1566 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1568 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1571 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1572 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1574 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1579 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1580 vsi->user_param + (msix_vect - 1);
1582 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1583 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1585 I40E_WRITE_FLUSH(hw);
1589 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1590 int base_queue, int nb_queue)
1594 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1596 /* Bind all RX queues to allocated MSIX interrupt */
1597 for (i = 0; i < nb_queue; i++) {
1598 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1599 I40E_QINT_RQCTL_ITR_INDX_MASK |
1600 ((base_queue + i + 1) <<
1601 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1602 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1603 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1605 if (i == nb_queue - 1)
1606 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1607 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1610 /* Write first RX queue to Link list register as the head element */
1611 if (vsi->type != I40E_VSI_SRIOV) {
1613 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1615 if (msix_vect == I40E_MISC_VEC_ID) {
1616 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1618 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1620 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1622 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1625 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1627 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1629 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1631 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1638 if (msix_vect == I40E_MISC_VEC_ID) {
1640 I40E_VPINT_LNKLST0(vsi->user_param),
1642 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1644 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1646 /* num_msix_vectors_vf needs to minus irq0 */
1647 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1648 vsi->user_param + (msix_vect - 1);
1650 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1652 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1654 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1658 I40E_WRITE_FLUSH(hw);
1662 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1664 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1665 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1666 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1667 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1668 uint16_t msix_vect = vsi->msix_intr;
1669 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1670 uint16_t queue_idx = 0;
1675 for (i = 0; i < vsi->nb_qps; i++) {
1676 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1677 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1680 /* INTENA flag is not auto-cleared for interrupt */
1681 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1682 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1683 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1684 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1685 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1687 /* VF bind interrupt */
1688 if (vsi->type == I40E_VSI_SRIOV) {
1689 __vsi_queues_bind_intr(vsi, msix_vect,
1690 vsi->base_queue, vsi->nb_qps);
1694 /* PF & VMDq bind interrupt */
1695 if (rte_intr_dp_is_en(intr_handle)) {
1696 if (vsi->type == I40E_VSI_MAIN) {
1699 } else if (vsi->type == I40E_VSI_VMDQ2) {
1700 struct i40e_vsi *main_vsi =
1701 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1702 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1707 for (i = 0; i < vsi->nb_used_qps; i++) {
1709 if (!rte_intr_allow_others(intr_handle))
1710 /* allow to share MISC_VEC_ID */
1711 msix_vect = I40E_MISC_VEC_ID;
1713 /* no enough msix_vect, map all to one */
1714 __vsi_queues_bind_intr(vsi, msix_vect,
1715 vsi->base_queue + i,
1716 vsi->nb_used_qps - i);
1717 for (; !!record && i < vsi->nb_used_qps; i++)
1718 intr_handle->intr_vec[queue_idx + i] =
1722 /* 1:1 queue/msix_vect mapping */
1723 __vsi_queues_bind_intr(vsi, msix_vect,
1724 vsi->base_queue + i, 1);
1726 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1734 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1736 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1737 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1738 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1739 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1740 uint16_t interval = i40e_calc_itr_interval(\
1741 RTE_LIBRTE_I40E_ITR_INTERVAL);
1742 uint16_t msix_intr, i;
1744 if (rte_intr_allow_others(intr_handle))
1745 for (i = 0; i < vsi->nb_msix; i++) {
1746 msix_intr = vsi->msix_intr + i;
1747 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1748 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1749 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1750 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1752 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1755 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1756 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1757 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1758 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1760 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1762 I40E_WRITE_FLUSH(hw);
1766 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1768 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1769 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1770 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1771 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1772 uint16_t msix_intr, i;
1774 if (rte_intr_allow_others(intr_handle))
1775 for (i = 0; i < vsi->nb_msix; i++) {
1776 msix_intr = vsi->msix_intr + i;
1777 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1781 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1783 I40E_WRITE_FLUSH(hw);
1786 static inline uint8_t
1787 i40e_parse_link_speeds(uint16_t link_speeds)
1789 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1791 if (link_speeds & ETH_LINK_SPEED_40G)
1792 link_speed |= I40E_LINK_SPEED_40GB;
1793 if (link_speeds & ETH_LINK_SPEED_25G)
1794 link_speed |= I40E_LINK_SPEED_25GB;
1795 if (link_speeds & ETH_LINK_SPEED_20G)
1796 link_speed |= I40E_LINK_SPEED_20GB;
1797 if (link_speeds & ETH_LINK_SPEED_10G)
1798 link_speed |= I40E_LINK_SPEED_10GB;
1799 if (link_speeds & ETH_LINK_SPEED_1G)
1800 link_speed |= I40E_LINK_SPEED_1GB;
1801 if (link_speeds & ETH_LINK_SPEED_100M)
1802 link_speed |= I40E_LINK_SPEED_100MB;
1808 i40e_phy_conf_link(struct i40e_hw *hw,
1810 uint8_t force_speed)
1812 enum i40e_status_code status;
1813 struct i40e_aq_get_phy_abilities_resp phy_ab;
1814 struct i40e_aq_set_phy_config phy_conf;
1815 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1816 I40E_AQ_PHY_FLAG_PAUSE_RX |
1817 I40E_AQ_PHY_FLAG_PAUSE_RX |
1818 I40E_AQ_PHY_FLAG_LOW_POWER;
1819 const uint8_t advt = I40E_LINK_SPEED_40GB |
1820 I40E_LINK_SPEED_25GB |
1821 I40E_LINK_SPEED_10GB |
1822 I40E_LINK_SPEED_1GB |
1823 I40E_LINK_SPEED_100MB;
1827 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1832 memset(&phy_conf, 0, sizeof(phy_conf));
1834 /* bits 0-2 use the values from get_phy_abilities_resp */
1836 abilities |= phy_ab.abilities & mask;
1838 /* update ablities and speed */
1839 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1840 phy_conf.link_speed = advt;
1842 phy_conf.link_speed = force_speed;
1844 phy_conf.abilities = abilities;
1846 /* use get_phy_abilities_resp value for the rest */
1847 phy_conf.phy_type = phy_ab.phy_type;
1848 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1849 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1850 phy_conf.eee_capability = phy_ab.eee_capability;
1851 phy_conf.eeer = phy_ab.eeer_val;
1852 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1854 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1855 phy_ab.abilities, phy_ab.link_speed);
1856 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1857 phy_conf.abilities, phy_conf.link_speed);
1859 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1863 return I40E_SUCCESS;
1867 i40e_apply_link_speed(struct rte_eth_dev *dev)
1870 uint8_t abilities = 0;
1871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 struct rte_eth_conf *conf = &dev->data->dev_conf;
1874 speed = i40e_parse_link_speeds(conf->link_speeds);
1875 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1876 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1877 abilities |= I40E_AQ_PHY_AN_ENABLED;
1878 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1880 /* Skip changing speed on 40G interfaces, FW does not support */
1881 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1882 speed = I40E_LINK_SPEED_UNKNOWN;
1883 abilities |= I40E_AQ_PHY_AN_ENABLED;
1886 return i40e_phy_conf_link(hw, abilities, speed);
1890 i40e_dev_start(struct rte_eth_dev *dev)
1892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1894 struct i40e_vsi *main_vsi = pf->main_vsi;
1896 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1897 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1898 uint32_t intr_vector = 0;
1899 struct i40e_vsi *vsi;
1901 hw->adapter_stopped = 0;
1903 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1904 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1905 dev->data->port_id);
1909 rte_intr_disable(intr_handle);
1911 if ((rte_intr_cap_multiple(intr_handle) ||
1912 !RTE_ETH_DEV_SRIOV(dev).active) &&
1913 dev->data->dev_conf.intr_conf.rxq != 0) {
1914 intr_vector = dev->data->nb_rx_queues;
1915 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1920 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1921 intr_handle->intr_vec =
1922 rte_zmalloc("intr_vec",
1923 dev->data->nb_rx_queues * sizeof(int),
1925 if (!intr_handle->intr_vec) {
1927 "Failed to allocate %d rx_queues intr_vec",
1928 dev->data->nb_rx_queues);
1933 /* Initialize VSI */
1934 ret = i40e_dev_rxtx_init(pf);
1935 if (ret != I40E_SUCCESS) {
1936 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1940 /* Map queues with MSIX interrupt */
1941 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1942 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1943 i40e_vsi_queues_bind_intr(main_vsi);
1944 i40e_vsi_enable_queues_intr(main_vsi);
1946 /* Map VMDQ VSI queues with MSIX interrupt */
1947 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1948 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1949 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1950 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1953 /* enable FDIR MSIX interrupt */
1954 if (pf->fdir.fdir_vsi) {
1955 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1956 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1959 /* Enable all queues which have been configured */
1960 ret = i40e_dev_switch_queues(pf, TRUE);
1961 if (ret != I40E_SUCCESS) {
1962 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1966 /* Enable receiving broadcast packets */
1967 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1968 if (ret != I40E_SUCCESS)
1969 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1971 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1972 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1974 if (ret != I40E_SUCCESS)
1975 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1978 /* Enable the VLAN promiscuous mode. */
1980 for (i = 0; i < pf->vf_num; i++) {
1981 vsi = pf->vfs[i].vsi;
1982 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1987 /* Apply link configure */
1988 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1989 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1990 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1991 ETH_LINK_SPEED_40G)) {
1992 PMD_DRV_LOG(ERR, "Invalid link setting");
1995 ret = i40e_apply_link_speed(dev);
1996 if (I40E_SUCCESS != ret) {
1997 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2001 if (!rte_intr_allow_others(intr_handle)) {
2002 rte_intr_callback_unregister(intr_handle,
2003 i40e_dev_interrupt_handler,
2005 /* configure and enable device interrupt */
2006 i40e_pf_config_irq0(hw, FALSE);
2007 i40e_pf_enable_irq0(hw);
2009 if (dev->data->dev_conf.intr_conf.lsc != 0)
2011 "lsc won't enable because of no intr multiplex");
2012 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2013 ret = i40e_aq_set_phy_int_mask(hw,
2014 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2015 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2016 I40E_AQ_EVENT_MEDIA_NA), NULL);
2017 if (ret != I40E_SUCCESS)
2018 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2020 /* Call get_link_info aq commond to enable LSE */
2021 i40e_dev_link_update(dev, 0);
2024 /* enable uio intr after callback register */
2025 rte_intr_enable(intr_handle);
2027 i40e_filter_restore(pf);
2029 return I40E_SUCCESS;
2032 i40e_dev_switch_queues(pf, FALSE);
2033 i40e_dev_clear_queues(dev);
2039 i40e_dev_stop(struct rte_eth_dev *dev)
2041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2042 struct i40e_vsi *main_vsi = pf->main_vsi;
2043 struct i40e_mirror_rule *p_mirror;
2044 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2045 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2048 /* Disable all queues */
2049 i40e_dev_switch_queues(pf, FALSE);
2051 /* un-map queues with interrupt registers */
2052 i40e_vsi_disable_queues_intr(main_vsi);
2053 i40e_vsi_queues_unbind_intr(main_vsi);
2055 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2056 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2057 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2060 if (pf->fdir.fdir_vsi) {
2061 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2062 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2064 /* Clear all queues and release memory */
2065 i40e_dev_clear_queues(dev);
2068 i40e_dev_set_link_down(dev);
2070 /* Remove all mirror rules */
2071 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2072 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2075 pf->nb_mirror_rule = 0;
2077 if (!rte_intr_allow_others(intr_handle))
2078 /* resume to the default handler */
2079 rte_intr_callback_register(intr_handle,
2080 i40e_dev_interrupt_handler,
2083 /* Clean datapath event and queue/vec mapping */
2084 rte_intr_efd_disable(intr_handle);
2085 if (intr_handle->intr_vec) {
2086 rte_free(intr_handle->intr_vec);
2087 intr_handle->intr_vec = NULL;
2092 i40e_dev_close(struct rte_eth_dev *dev)
2094 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2095 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2097 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2101 PMD_INIT_FUNC_TRACE();
2104 hw->adapter_stopped = 1;
2105 i40e_dev_free_queues(dev);
2107 /* Disable interrupt */
2108 i40e_pf_disable_irq0(hw);
2109 rte_intr_disable(intr_handle);
2111 /* shutdown and destroy the HMC */
2112 i40e_shutdown_lan_hmc(hw);
2114 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2115 i40e_vsi_release(pf->vmdq[i].vsi);
2116 pf->vmdq[i].vsi = NULL;
2121 /* release all the existing VSIs and VEBs */
2122 i40e_fdir_teardown(pf);
2123 i40e_vsi_release(pf->main_vsi);
2125 /* shutdown the adminq */
2126 i40e_aq_queue_shutdown(hw, true);
2127 i40e_shutdown_adminq(hw);
2129 i40e_res_pool_destroy(&pf->qp_pool);
2130 i40e_res_pool_destroy(&pf->msix_pool);
2132 /* force a PF reset to clean anything leftover */
2133 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2134 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2135 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2136 I40E_WRITE_FLUSH(hw);
2140 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2142 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2143 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144 struct i40e_vsi *vsi = pf->main_vsi;
2147 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2149 if (status != I40E_SUCCESS)
2150 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2152 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2154 if (status != I40E_SUCCESS)
2155 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2160 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2162 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2163 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 struct i40e_vsi *vsi = pf->main_vsi;
2167 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2169 if (status != I40E_SUCCESS)
2170 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2172 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2174 if (status != I40E_SUCCESS)
2175 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2179 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 struct i40e_vsi *vsi = pf->main_vsi;
2186 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2187 if (ret != I40E_SUCCESS)
2188 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2192 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2194 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2195 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196 struct i40e_vsi *vsi = pf->main_vsi;
2199 if (dev->data->promiscuous == 1)
2200 return; /* must remain in all_multicast mode */
2202 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2203 vsi->seid, FALSE, NULL);
2204 if (ret != I40E_SUCCESS)
2205 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2209 * Set device link up.
2212 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2214 /* re-apply link speed setting */
2215 return i40e_apply_link_speed(dev);
2219 * Set device link down.
2222 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2224 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2225 uint8_t abilities = 0;
2226 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2229 return i40e_phy_conf_link(hw, abilities, speed);
2233 i40e_dev_link_update(struct rte_eth_dev *dev,
2234 int wait_to_complete)
2236 #define CHECK_INTERVAL 100 /* 100ms */
2237 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct i40e_link_status link_status;
2240 struct rte_eth_link link, old;
2242 unsigned rep_cnt = MAX_REPEAT_TIME;
2243 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2245 memset(&link, 0, sizeof(link));
2246 memset(&old, 0, sizeof(old));
2247 memset(&link_status, 0, sizeof(link_status));
2248 rte_i40e_dev_atomic_read_link_status(dev, &old);
2251 /* Get link status information from hardware */
2252 status = i40e_aq_get_link_info(hw, enable_lse,
2253 &link_status, NULL);
2254 if (status != I40E_SUCCESS) {
2255 link.link_speed = ETH_SPEED_NUM_100M;
2256 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2257 PMD_DRV_LOG(ERR, "Failed to get link info");
2261 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2262 if (!wait_to_complete || link.link_status)
2265 rte_delay_ms(CHECK_INTERVAL);
2266 } while (--rep_cnt);
2268 if (!link.link_status)
2271 /* i40e uses full duplex only */
2272 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2274 /* Parse the link status */
2275 switch (link_status.link_speed) {
2276 case I40E_LINK_SPEED_100MB:
2277 link.link_speed = ETH_SPEED_NUM_100M;
2279 case I40E_LINK_SPEED_1GB:
2280 link.link_speed = ETH_SPEED_NUM_1G;
2282 case I40E_LINK_SPEED_10GB:
2283 link.link_speed = ETH_SPEED_NUM_10G;
2285 case I40E_LINK_SPEED_20GB:
2286 link.link_speed = ETH_SPEED_NUM_20G;
2288 case I40E_LINK_SPEED_25GB:
2289 link.link_speed = ETH_SPEED_NUM_25G;
2291 case I40E_LINK_SPEED_40GB:
2292 link.link_speed = ETH_SPEED_NUM_40G;
2295 link.link_speed = ETH_SPEED_NUM_100M;
2299 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2300 ETH_LINK_SPEED_FIXED);
2303 rte_i40e_dev_atomic_write_link_status(dev, &link);
2304 if (link.link_status == old.link_status)
2307 i40e_notify_all_vfs_link_status(dev);
2312 /* Get all the statistics of a VSI */
2314 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2316 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2317 struct i40e_eth_stats *nes = &vsi->eth_stats;
2318 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2319 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2321 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2322 vsi->offset_loaded, &oes->rx_bytes,
2324 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2325 vsi->offset_loaded, &oes->rx_unicast,
2327 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2328 vsi->offset_loaded, &oes->rx_multicast,
2329 &nes->rx_multicast);
2330 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2331 vsi->offset_loaded, &oes->rx_broadcast,
2332 &nes->rx_broadcast);
2333 /* exclude CRC bytes */
2334 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2335 nes->rx_broadcast) * ETHER_CRC_LEN;
2337 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2338 &oes->rx_discards, &nes->rx_discards);
2339 /* GLV_REPC not supported */
2340 /* GLV_RMPC not supported */
2341 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2342 &oes->rx_unknown_protocol,
2343 &nes->rx_unknown_protocol);
2344 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2345 vsi->offset_loaded, &oes->tx_bytes,
2347 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2348 vsi->offset_loaded, &oes->tx_unicast,
2350 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2351 vsi->offset_loaded, &oes->tx_multicast,
2352 &nes->tx_multicast);
2353 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2354 vsi->offset_loaded, &oes->tx_broadcast,
2355 &nes->tx_broadcast);
2356 /* exclude CRC bytes */
2357 nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2358 nes->tx_broadcast) * ETHER_CRC_LEN;
2359 /* GLV_TDPC not supported */
2360 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2361 &oes->tx_errors, &nes->tx_errors);
2362 vsi->offset_loaded = true;
2364 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2366 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2367 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2368 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2369 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2370 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2371 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2372 nes->rx_unknown_protocol);
2373 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2374 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2375 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2376 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2377 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2378 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2379 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2384 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2387 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2388 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2390 /* Get rx/tx bytes of internal transfer packets */
2391 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2392 I40E_GLV_GORCL(hw->port),
2394 &pf->internal_rx_bytes_offset,
2395 &pf->internal_rx_bytes);
2397 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2398 I40E_GLV_GOTCL(hw->port),
2400 &pf->internal_tx_bytes_offset,
2401 &pf->internal_tx_bytes);
2403 /* Get statistics of struct i40e_eth_stats */
2404 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2405 I40E_GLPRT_GORCL(hw->port),
2406 pf->offset_loaded, &os->eth.rx_bytes,
2408 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2409 I40E_GLPRT_UPRCL(hw->port),
2410 pf->offset_loaded, &os->eth.rx_unicast,
2411 &ns->eth.rx_unicast);
2412 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2413 I40E_GLPRT_MPRCL(hw->port),
2414 pf->offset_loaded, &os->eth.rx_multicast,
2415 &ns->eth.rx_multicast);
2416 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2417 I40E_GLPRT_BPRCL(hw->port),
2418 pf->offset_loaded, &os->eth.rx_broadcast,
2419 &ns->eth.rx_broadcast);
2420 /* Workaround: CRC size should not be included in byte statistics,
2421 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2423 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2424 ns->eth.rx_broadcast) * ETHER_CRC_LEN + pf->internal_rx_bytes;
2426 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2427 pf->offset_loaded, &os->eth.rx_discards,
2428 &ns->eth.rx_discards);
2429 /* GLPRT_REPC not supported */
2430 /* GLPRT_RMPC not supported */
2431 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2433 &os->eth.rx_unknown_protocol,
2434 &ns->eth.rx_unknown_protocol);
2435 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2436 I40E_GLPRT_GOTCL(hw->port),
2437 pf->offset_loaded, &os->eth.tx_bytes,
2439 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2440 I40E_GLPRT_UPTCL(hw->port),
2441 pf->offset_loaded, &os->eth.tx_unicast,
2442 &ns->eth.tx_unicast);
2443 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2444 I40E_GLPRT_MPTCL(hw->port),
2445 pf->offset_loaded, &os->eth.tx_multicast,
2446 &ns->eth.tx_multicast);
2447 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2448 I40E_GLPRT_BPTCL(hw->port),
2449 pf->offset_loaded, &os->eth.tx_broadcast,
2450 &ns->eth.tx_broadcast);
2451 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2452 ns->eth.tx_broadcast) * ETHER_CRC_LEN + pf->internal_tx_bytes;
2453 /* GLPRT_TEPC not supported */
2455 /* additional port specific stats */
2456 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2457 pf->offset_loaded, &os->tx_dropped_link_down,
2458 &ns->tx_dropped_link_down);
2459 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2460 pf->offset_loaded, &os->crc_errors,
2462 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2463 pf->offset_loaded, &os->illegal_bytes,
2464 &ns->illegal_bytes);
2465 /* GLPRT_ERRBC not supported */
2466 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2467 pf->offset_loaded, &os->mac_local_faults,
2468 &ns->mac_local_faults);
2469 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2470 pf->offset_loaded, &os->mac_remote_faults,
2471 &ns->mac_remote_faults);
2472 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2473 pf->offset_loaded, &os->rx_length_errors,
2474 &ns->rx_length_errors);
2475 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2476 pf->offset_loaded, &os->link_xon_rx,
2478 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2479 pf->offset_loaded, &os->link_xoff_rx,
2481 for (i = 0; i < 8; i++) {
2482 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2484 &os->priority_xon_rx[i],
2485 &ns->priority_xon_rx[i]);
2486 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2488 &os->priority_xoff_rx[i],
2489 &ns->priority_xoff_rx[i]);
2491 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2492 pf->offset_loaded, &os->link_xon_tx,
2494 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2495 pf->offset_loaded, &os->link_xoff_tx,
2497 for (i = 0; i < 8; i++) {
2498 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2500 &os->priority_xon_tx[i],
2501 &ns->priority_xon_tx[i]);
2502 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2504 &os->priority_xoff_tx[i],
2505 &ns->priority_xoff_tx[i]);
2506 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2508 &os->priority_xon_2_xoff[i],
2509 &ns->priority_xon_2_xoff[i]);
2511 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2512 I40E_GLPRT_PRC64L(hw->port),
2513 pf->offset_loaded, &os->rx_size_64,
2515 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2516 I40E_GLPRT_PRC127L(hw->port),
2517 pf->offset_loaded, &os->rx_size_127,
2519 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2520 I40E_GLPRT_PRC255L(hw->port),
2521 pf->offset_loaded, &os->rx_size_255,
2523 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2524 I40E_GLPRT_PRC511L(hw->port),
2525 pf->offset_loaded, &os->rx_size_511,
2527 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2528 I40E_GLPRT_PRC1023L(hw->port),
2529 pf->offset_loaded, &os->rx_size_1023,
2531 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2532 I40E_GLPRT_PRC1522L(hw->port),
2533 pf->offset_loaded, &os->rx_size_1522,
2535 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2536 I40E_GLPRT_PRC9522L(hw->port),
2537 pf->offset_loaded, &os->rx_size_big,
2539 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2540 pf->offset_loaded, &os->rx_undersize,
2542 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2543 pf->offset_loaded, &os->rx_fragments,
2545 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2546 pf->offset_loaded, &os->rx_oversize,
2548 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2549 pf->offset_loaded, &os->rx_jabber,
2551 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2552 I40E_GLPRT_PTC64L(hw->port),
2553 pf->offset_loaded, &os->tx_size_64,
2555 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2556 I40E_GLPRT_PTC127L(hw->port),
2557 pf->offset_loaded, &os->tx_size_127,
2559 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2560 I40E_GLPRT_PTC255L(hw->port),
2561 pf->offset_loaded, &os->tx_size_255,
2563 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2564 I40E_GLPRT_PTC511L(hw->port),
2565 pf->offset_loaded, &os->tx_size_511,
2567 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2568 I40E_GLPRT_PTC1023L(hw->port),
2569 pf->offset_loaded, &os->tx_size_1023,
2571 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2572 I40E_GLPRT_PTC1522L(hw->port),
2573 pf->offset_loaded, &os->tx_size_1522,
2575 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2576 I40E_GLPRT_PTC9522L(hw->port),
2577 pf->offset_loaded, &os->tx_size_big,
2579 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2581 &os->fd_sb_match, &ns->fd_sb_match);
2582 /* GLPRT_MSPDC not supported */
2583 /* GLPRT_XEC not supported */
2585 pf->offset_loaded = true;
2588 i40e_update_vsi_stats(pf->main_vsi);
2591 /* Get all statistics of a port */
2593 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2595 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2596 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2597 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2600 /* call read registers - updates values, now write them to struct */
2601 i40e_read_stats_registers(pf, hw);
2603 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2604 pf->main_vsi->eth_stats.rx_multicast +
2605 pf->main_vsi->eth_stats.rx_broadcast -
2606 pf->main_vsi->eth_stats.rx_discards;
2607 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2608 pf->main_vsi->eth_stats.tx_multicast +
2609 pf->main_vsi->eth_stats.tx_broadcast;
2610 stats->ibytes = ns->eth.rx_bytes;
2611 stats->obytes = ns->eth.tx_bytes;
2612 stats->oerrors = ns->eth.tx_errors +
2613 pf->main_vsi->eth_stats.tx_errors;
2616 stats->imissed = ns->eth.rx_discards +
2617 pf->main_vsi->eth_stats.rx_discards;
2618 stats->ierrors = ns->crc_errors +
2619 ns->rx_length_errors + ns->rx_undersize +
2620 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2622 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2623 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2624 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2625 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2626 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2627 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2628 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2629 ns->eth.rx_unknown_protocol);
2630 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2631 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2632 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2633 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2634 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2635 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2637 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2638 ns->tx_dropped_link_down);
2639 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2640 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2642 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2643 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2644 ns->mac_local_faults);
2645 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2646 ns->mac_remote_faults);
2647 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2648 ns->rx_length_errors);
2649 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2650 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2651 for (i = 0; i < 8; i++) {
2652 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2653 i, ns->priority_xon_rx[i]);
2654 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2655 i, ns->priority_xoff_rx[i]);
2657 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2658 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2659 for (i = 0; i < 8; i++) {
2660 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2661 i, ns->priority_xon_tx[i]);
2662 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2663 i, ns->priority_xoff_tx[i]);
2664 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2665 i, ns->priority_xon_2_xoff[i]);
2667 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2668 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2669 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2670 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2671 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2672 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2673 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2674 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2675 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2676 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2677 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2678 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2679 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2680 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2681 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2682 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2683 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2684 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2685 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2686 ns->mac_short_packet_dropped);
2687 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2688 ns->checksum_error);
2689 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2690 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2693 /* Reset the statistics */
2695 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2697 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2698 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2700 /* Mark PF and VSI stats to update the offset, aka "reset" */
2701 pf->offset_loaded = false;
2703 pf->main_vsi->offset_loaded = false;
2705 /* read the stats, reading current register values into offset */
2706 i40e_read_stats_registers(pf, hw);
2710 i40e_xstats_calc_num(void)
2712 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2713 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2714 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2717 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2718 struct rte_eth_xstat_name *xstats_names,
2719 __rte_unused unsigned limit)
2724 if (xstats_names == NULL)
2725 return i40e_xstats_calc_num();
2727 /* Note: limit checked in rte_eth_xstats_names() */
2729 /* Get stats from i40e_eth_stats struct */
2730 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2731 snprintf(xstats_names[count].name,
2732 sizeof(xstats_names[count].name),
2733 "%s", rte_i40e_stats_strings[i].name);
2737 /* Get individiual stats from i40e_hw_port struct */
2738 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2739 snprintf(xstats_names[count].name,
2740 sizeof(xstats_names[count].name),
2741 "%s", rte_i40e_hw_port_strings[i].name);
2745 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2746 for (prio = 0; prio < 8; prio++) {
2747 snprintf(xstats_names[count].name,
2748 sizeof(xstats_names[count].name),
2749 "rx_priority%u_%s", prio,
2750 rte_i40e_rxq_prio_strings[i].name);
2755 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2756 for (prio = 0; prio < 8; prio++) {
2757 snprintf(xstats_names[count].name,
2758 sizeof(xstats_names[count].name),
2759 "tx_priority%u_%s", prio,
2760 rte_i40e_txq_prio_strings[i].name);
2768 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2771 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2773 unsigned i, count, prio;
2774 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2776 count = i40e_xstats_calc_num();
2780 i40e_read_stats_registers(pf, hw);
2787 /* Get stats from i40e_eth_stats struct */
2788 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2789 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2790 rte_i40e_stats_strings[i].offset);
2791 xstats[count].id = count;
2795 /* Get individiual stats from i40e_hw_port struct */
2796 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2797 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2798 rte_i40e_hw_port_strings[i].offset);
2799 xstats[count].id = count;
2803 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2804 for (prio = 0; prio < 8; prio++) {
2805 xstats[count].value =
2806 *(uint64_t *)(((char *)hw_stats) +
2807 rte_i40e_rxq_prio_strings[i].offset +
2808 (sizeof(uint64_t) * prio));
2809 xstats[count].id = count;
2814 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2815 for (prio = 0; prio < 8; prio++) {
2816 xstats[count].value =
2817 *(uint64_t *)(((char *)hw_stats) +
2818 rte_i40e_txq_prio_strings[i].offset +
2819 (sizeof(uint64_t) * prio));
2820 xstats[count].id = count;
2829 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2830 __rte_unused uint16_t queue_id,
2831 __rte_unused uint8_t stat_idx,
2832 __rte_unused uint8_t is_rx)
2834 PMD_INIT_FUNC_TRACE();
2840 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848 full_ver = hw->nvm.oem_ver;
2849 ver = (u8)(full_ver >> 24);
2850 build = (u16)((full_ver >> 8) & 0xffff);
2851 patch = (u8)(full_ver & 0xff);
2853 ret = snprintf(fw_version, fw_size,
2854 "%d.%d%d 0x%08x %d.%d.%d",
2855 ((hw->nvm.version >> 12) & 0xf),
2856 ((hw->nvm.version >> 4) & 0xff),
2857 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2860 ret += 1; /* add the size of '\0' */
2861 if (fw_size < (u32)ret)
2868 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2870 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872 struct i40e_vsi *vsi = pf->main_vsi;
2873 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2875 dev_info->pci_dev = pci_dev;
2876 dev_info->max_rx_queues = vsi->nb_qps;
2877 dev_info->max_tx_queues = vsi->nb_qps;
2878 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2879 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2880 dev_info->max_mac_addrs = vsi->max_macaddrs;
2881 dev_info->max_vfs = pci_dev->max_vfs;
2882 dev_info->rx_offload_capa =
2883 DEV_RX_OFFLOAD_VLAN_STRIP |
2884 DEV_RX_OFFLOAD_QINQ_STRIP |
2885 DEV_RX_OFFLOAD_IPV4_CKSUM |
2886 DEV_RX_OFFLOAD_UDP_CKSUM |
2887 DEV_RX_OFFLOAD_TCP_CKSUM;
2888 dev_info->tx_offload_capa =
2889 DEV_TX_OFFLOAD_VLAN_INSERT |
2890 DEV_TX_OFFLOAD_QINQ_INSERT |
2891 DEV_TX_OFFLOAD_IPV4_CKSUM |
2892 DEV_TX_OFFLOAD_UDP_CKSUM |
2893 DEV_TX_OFFLOAD_TCP_CKSUM |
2894 DEV_TX_OFFLOAD_SCTP_CKSUM |
2895 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2896 DEV_TX_OFFLOAD_TCP_TSO |
2897 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2898 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2899 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2900 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2901 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2903 dev_info->reta_size = pf->hash_lut_size;
2904 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2906 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2908 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2909 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2910 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2912 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2916 dev_info->default_txconf = (struct rte_eth_txconf) {
2918 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2919 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2920 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2922 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2923 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2924 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2925 ETH_TXQ_FLAGS_NOOFFLOADS,
2928 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2929 .nb_max = I40E_MAX_RING_DESC,
2930 .nb_min = I40E_MIN_RING_DESC,
2931 .nb_align = I40E_ALIGN_RING_DESC,
2934 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2935 .nb_max = I40E_MAX_RING_DESC,
2936 .nb_min = I40E_MIN_RING_DESC,
2937 .nb_align = I40E_ALIGN_RING_DESC,
2938 .nb_seg_max = I40E_TX_MAX_SEG,
2939 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2942 if (pf->flags & I40E_FLAG_VMDQ) {
2943 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2944 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2945 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2946 pf->max_nb_vmdq_vsi;
2947 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2948 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2949 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2952 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2954 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2955 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2957 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2960 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2964 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2967 struct i40e_vsi *vsi = pf->main_vsi;
2968 PMD_INIT_FUNC_TRACE();
2971 return i40e_vsi_add_vlan(vsi, vlan_id);
2973 return i40e_vsi_delete_vlan(vsi, vlan_id);
2977 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
2978 enum rte_vlan_type vlan_type,
2979 uint16_t tpid, int qinq)
2981 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984 uint16_t reg_id = 3;
2988 if (vlan_type == ETH_VLAN_TYPE_OUTER)
2992 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2994 if (ret != I40E_SUCCESS) {
2996 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3001 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3004 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3005 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3006 if (reg_r == reg_w) {
3007 PMD_DRV_LOG(DEBUG, "No need to write");
3011 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3013 if (ret != I40E_SUCCESS) {
3015 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3020 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3027 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3028 enum rte_vlan_type vlan_type,
3031 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3032 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3035 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3036 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3037 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3039 "Unsupported vlan type.");
3042 /* 802.1ad frames ability is added in NVM API 1.7*/
3043 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3045 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3046 hw->first_tag = rte_cpu_to_le_16(tpid);
3047 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3048 hw->second_tag = rte_cpu_to_le_16(tpid);
3050 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3051 hw->second_tag = rte_cpu_to_le_16(tpid);
3053 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3054 if (ret != I40E_SUCCESS) {
3056 "Set switch config failed aq_err: %d",
3057 hw->aq.asq_last_status);
3061 /* If NVM API < 1.7, keep the register setting */
3062 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3069 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3071 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3072 struct i40e_vsi *vsi = pf->main_vsi;
3074 if (mask & ETH_VLAN_FILTER_MASK) {
3075 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3076 i40e_vsi_config_vlan_filter(vsi, TRUE);
3078 i40e_vsi_config_vlan_filter(vsi, FALSE);
3081 if (mask & ETH_VLAN_STRIP_MASK) {
3082 /* Enable or disable VLAN stripping */
3083 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3084 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3086 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3089 if (mask & ETH_VLAN_EXTEND_MASK) {
3090 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3091 i40e_vsi_config_double_vlan(vsi, TRUE);
3092 /* Set global registers with default ethertype. */
3093 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3095 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3099 i40e_vsi_config_double_vlan(vsi, FALSE);
3104 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3105 __rte_unused uint16_t queue,
3106 __rte_unused int on)
3108 PMD_INIT_FUNC_TRACE();
3112 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3114 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3115 struct i40e_vsi *vsi = pf->main_vsi;
3116 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3117 struct i40e_vsi_vlan_pvid_info info;
3119 memset(&info, 0, sizeof(info));
3122 info.config.pvid = pvid;
3124 info.config.reject.tagged =
3125 data->dev_conf.txmode.hw_vlan_reject_tagged;
3126 info.config.reject.untagged =
3127 data->dev_conf.txmode.hw_vlan_reject_untagged;
3130 return i40e_vsi_vlan_pvid_set(vsi, &info);
3134 i40e_dev_led_on(struct rte_eth_dev *dev)
3136 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137 uint32_t mode = i40e_led_get(hw);
3140 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3146 i40e_dev_led_off(struct rte_eth_dev *dev)
3148 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149 uint32_t mode = i40e_led_get(hw);
3152 i40e_led_set(hw, 0, false);
3158 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3160 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3163 fc_conf->pause_time = pf->fc_conf.pause_time;
3164 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3165 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3167 /* Return current mode according to actual setting*/
3168 switch (hw->fc.current_mode) {
3170 fc_conf->mode = RTE_FC_FULL;
3172 case I40E_FC_TX_PAUSE:
3173 fc_conf->mode = RTE_FC_TX_PAUSE;
3175 case I40E_FC_RX_PAUSE:
3176 fc_conf->mode = RTE_FC_RX_PAUSE;
3180 fc_conf->mode = RTE_FC_NONE;
3187 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3189 uint32_t mflcn_reg, fctrl_reg, reg;
3190 uint32_t max_high_water;
3191 uint8_t i, aq_failure;
3195 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3196 [RTE_FC_NONE] = I40E_FC_NONE,
3197 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3198 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3199 [RTE_FC_FULL] = I40E_FC_FULL
3202 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3204 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3205 if ((fc_conf->high_water > max_high_water) ||
3206 (fc_conf->high_water < fc_conf->low_water)) {
3208 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3213 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3215 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3217 pf->fc_conf.pause_time = fc_conf->pause_time;
3218 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3219 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3221 PMD_INIT_FUNC_TRACE();
3223 /* All the link flow control related enable/disable register
3224 * configuration is handle by the F/W
3226 err = i40e_set_fc(hw, &aq_failure, true);
3230 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3231 /* Configure flow control refresh threshold,
3232 * the value for stat_tx_pause_refresh_timer[8]
3233 * is used for global pause operation.
3237 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3238 pf->fc_conf.pause_time);
3240 /* configure the timer value included in transmitted pause
3242 * the value for stat_tx_pause_quanta[8] is used for global
3245 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3246 pf->fc_conf.pause_time);
3248 fctrl_reg = I40E_READ_REG(hw,
3249 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3251 if (fc_conf->mac_ctrl_frame_fwd != 0)
3252 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3254 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3256 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3259 /* Configure pause time (2 TCs per register) */
3260 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3261 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3262 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3264 /* Configure flow control refresh threshold value */
3265 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3266 pf->fc_conf.pause_time / 2);
3268 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3270 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3271 *depending on configuration
3273 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3274 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3275 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3277 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3278 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3281 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3284 /* config the water marker both based on the packets and bytes */
3285 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3286 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3287 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3288 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3289 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3290 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3291 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3292 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3294 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3295 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3298 I40E_WRITE_FLUSH(hw);
3304 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3305 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3307 PMD_INIT_FUNC_TRACE();
3312 /* Add a MAC address, and update filters */
3314 i40e_macaddr_add(struct rte_eth_dev *dev,
3315 struct ether_addr *mac_addr,
3316 __rte_unused uint32_t index,
3319 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3320 struct i40e_mac_filter_info mac_filter;
3321 struct i40e_vsi *vsi;
3324 /* If VMDQ not enabled or configured, return */
3325 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3326 !pf->nb_cfg_vmdq_vsi)) {
3327 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3328 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3333 if (pool > pf->nb_cfg_vmdq_vsi) {
3334 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3335 pool, pf->nb_cfg_vmdq_vsi);
3339 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3340 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3341 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3343 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3348 vsi = pf->vmdq[pool - 1].vsi;
3350 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3351 if (ret != I40E_SUCCESS) {
3352 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3358 /* Remove a MAC address, and update filters */
3360 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3362 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3363 struct i40e_vsi *vsi;
3364 struct rte_eth_dev_data *data = dev->data;
3365 struct ether_addr *macaddr;
3370 macaddr = &(data->mac_addrs[index]);
3372 pool_sel = dev->data->mac_pool_sel[index];
3374 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3375 if (pool_sel & (1ULL << i)) {
3379 /* No VMDQ pool enabled or configured */
3380 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3381 (i > pf->nb_cfg_vmdq_vsi)) {
3383 "No VMDQ pool enabled/configured");
3386 vsi = pf->vmdq[i - 1].vsi;
3388 ret = i40e_vsi_delete_mac(vsi, macaddr);
3391 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3398 /* Set perfect match or hash match of MAC and VLAN for a VF */
3400 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3401 struct rte_eth_mac_filter *filter,
3405 struct i40e_mac_filter_info mac_filter;
3406 struct ether_addr old_mac;
3407 struct ether_addr *new_mac;
3408 struct i40e_pf_vf *vf = NULL;
3413 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3416 hw = I40E_PF_TO_HW(pf);
3418 if (filter == NULL) {
3419 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3423 new_mac = &filter->mac_addr;
3425 if (is_zero_ether_addr(new_mac)) {
3426 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3430 vf_id = filter->dst_id;
3432 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3433 PMD_DRV_LOG(ERR, "Invalid argument.");
3436 vf = &pf->vfs[vf_id];
3438 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3439 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3444 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3445 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3447 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3450 mac_filter.filter_type = filter->filter_type;
3451 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3452 if (ret != I40E_SUCCESS) {
3453 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3456 ether_addr_copy(new_mac, &pf->dev_addr);
3458 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3460 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3461 if (ret != I40E_SUCCESS) {
3462 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3466 /* Clear device address as it has been removed */
3467 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3468 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3474 /* MAC filter handle */
3476 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3479 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3480 struct rte_eth_mac_filter *filter;
3481 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3482 int ret = I40E_NOT_SUPPORTED;
3484 filter = (struct rte_eth_mac_filter *)(arg);
3486 switch (filter_op) {
3487 case RTE_ETH_FILTER_NOP:
3490 case RTE_ETH_FILTER_ADD:
3491 i40e_pf_disable_irq0(hw);
3493 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3494 i40e_pf_enable_irq0(hw);
3496 case RTE_ETH_FILTER_DELETE:
3497 i40e_pf_disable_irq0(hw);
3499 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3500 i40e_pf_enable_irq0(hw);
3503 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3504 ret = I40E_ERR_PARAM;
3512 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3514 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3515 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3521 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3522 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3525 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3529 uint32_t *lut_dw = (uint32_t *)lut;
3530 uint16_t i, lut_size_dw = lut_size / 4;
3532 for (i = 0; i < lut_size_dw; i++)
3533 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3540 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3549 pf = I40E_VSI_TO_PF(vsi);
3550 hw = I40E_VSI_TO_HW(vsi);
3552 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3553 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3556 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3560 uint32_t *lut_dw = (uint32_t *)lut;
3561 uint16_t i, lut_size_dw = lut_size / 4;
3563 for (i = 0; i < lut_size_dw; i++)
3564 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3565 I40E_WRITE_FLUSH(hw);
3572 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3573 struct rte_eth_rss_reta_entry64 *reta_conf,
3576 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3577 uint16_t i, lut_size = pf->hash_lut_size;
3578 uint16_t idx, shift;
3582 if (reta_size != lut_size ||
3583 reta_size > ETH_RSS_RETA_SIZE_512) {
3585 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3586 reta_size, lut_size);
3590 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3592 PMD_DRV_LOG(ERR, "No memory can be allocated");
3595 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3598 for (i = 0; i < reta_size; i++) {
3599 idx = i / RTE_RETA_GROUP_SIZE;
3600 shift = i % RTE_RETA_GROUP_SIZE;
3601 if (reta_conf[idx].mask & (1ULL << shift))
3602 lut[i] = reta_conf[idx].reta[shift];
3604 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3613 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3614 struct rte_eth_rss_reta_entry64 *reta_conf,
3617 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3618 uint16_t i, lut_size = pf->hash_lut_size;
3619 uint16_t idx, shift;
3623 if (reta_size != lut_size ||
3624 reta_size > ETH_RSS_RETA_SIZE_512) {
3626 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3627 reta_size, lut_size);
3631 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3633 PMD_DRV_LOG(ERR, "No memory can be allocated");
3637 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3640 for (i = 0; i < reta_size; i++) {
3641 idx = i / RTE_RETA_GROUP_SIZE;
3642 shift = i % RTE_RETA_GROUP_SIZE;
3643 if (reta_conf[idx].mask & (1ULL << shift))
3644 reta_conf[idx].reta[shift] = lut[i];
3654 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3655 * @hw: pointer to the HW structure
3656 * @mem: pointer to mem struct to fill out
3657 * @size: size of memory requested
3658 * @alignment: what to align the allocation to
3660 enum i40e_status_code
3661 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3662 struct i40e_dma_mem *mem,
3666 const struct rte_memzone *mz = NULL;
3667 char z_name[RTE_MEMZONE_NAMESIZE];
3670 return I40E_ERR_PARAM;
3672 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3673 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3674 alignment, RTE_PGSIZE_2M);
3676 return I40E_ERR_NO_MEMORY;
3680 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3681 mem->zone = (const void *)mz;
3683 "memzone %s allocated with physical address: %"PRIu64,
3686 return I40E_SUCCESS;
3690 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3691 * @hw: pointer to the HW structure
3692 * @mem: ptr to mem struct to free
3694 enum i40e_status_code
3695 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3696 struct i40e_dma_mem *mem)
3699 return I40E_ERR_PARAM;
3702 "memzone %s to be freed with physical address: %"PRIu64,
3703 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3704 rte_memzone_free((const struct rte_memzone *)mem->zone);
3709 return I40E_SUCCESS;
3713 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3714 * @hw: pointer to the HW structure
3715 * @mem: pointer to mem struct to fill out
3716 * @size: size of memory requested
3718 enum i40e_status_code
3719 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3720 struct i40e_virt_mem *mem,
3724 return I40E_ERR_PARAM;
3727 mem->va = rte_zmalloc("i40e", size, 0);
3730 return I40E_SUCCESS;
3732 return I40E_ERR_NO_MEMORY;
3736 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3737 * @hw: pointer to the HW structure
3738 * @mem: pointer to mem struct to free
3740 enum i40e_status_code
3741 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3742 struct i40e_virt_mem *mem)
3745 return I40E_ERR_PARAM;
3750 return I40E_SUCCESS;
3754 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3756 rte_spinlock_init(&sp->spinlock);
3760 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3762 rte_spinlock_lock(&sp->spinlock);
3766 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3768 rte_spinlock_unlock(&sp->spinlock);
3772 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3778 * Get the hardware capabilities, which will be parsed
3779 * and saved into struct i40e_hw.
3782 i40e_get_cap(struct i40e_hw *hw)
3784 struct i40e_aqc_list_capabilities_element_resp *buf;
3785 uint16_t len, size = 0;
3788 /* Calculate a huge enough buff for saving response data temporarily */
3789 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3790 I40E_MAX_CAP_ELE_NUM;
3791 buf = rte_zmalloc("i40e", len, 0);
3793 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3794 return I40E_ERR_NO_MEMORY;
3797 /* Get, parse the capabilities and save it to hw */
3798 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3799 i40e_aqc_opc_list_func_capabilities, NULL);
3800 if (ret != I40E_SUCCESS)
3801 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3803 /* Free the temporary buffer after being used */
3810 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3812 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3813 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3814 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3815 uint16_t qp_count = 0, vsi_count = 0;
3817 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3818 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3821 /* Add the parameter init for LFC */
3822 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3823 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3824 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3826 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3827 pf->max_num_vsi = hw->func_caps.num_vsis;
3828 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3829 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3830 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3832 /* FDir queue/VSI allocation */
3833 pf->fdir_qp_offset = 0;
3834 if (hw->func_caps.fd) {
3835 pf->flags |= I40E_FLAG_FDIR;
3836 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3838 pf->fdir_nb_qps = 0;
3840 qp_count += pf->fdir_nb_qps;
3843 /* LAN queue/VSI allocation */
3844 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3845 if (!hw->func_caps.rss) {
3848 pf->flags |= I40E_FLAG_RSS;
3849 if (hw->mac.type == I40E_MAC_X722)
3850 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3851 pf->lan_nb_qps = pf->lan_nb_qp_max;
3853 qp_count += pf->lan_nb_qps;
3856 /* VF queue/VSI allocation */
3857 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3858 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3859 pf->flags |= I40E_FLAG_SRIOV;
3860 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3861 pf->vf_num = pci_dev->max_vfs;
3863 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3864 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3869 qp_count += pf->vf_nb_qps * pf->vf_num;
3870 vsi_count += pf->vf_num;
3872 /* VMDq queue/VSI allocation */
3873 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3874 pf->vmdq_nb_qps = 0;
3875 pf->max_nb_vmdq_vsi = 0;
3876 if (hw->func_caps.vmdq) {
3877 if (qp_count < hw->func_caps.num_tx_qp &&
3878 vsi_count < hw->func_caps.num_vsis) {
3879 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3880 qp_count) / pf->vmdq_nb_qp_max;
3882 /* Limit the maximum number of VMDq vsi to the maximum
3883 * ethdev can support
3885 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3886 hw->func_caps.num_vsis - vsi_count);
3887 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3889 if (pf->max_nb_vmdq_vsi) {
3890 pf->flags |= I40E_FLAG_VMDQ;
3891 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3893 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3894 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3895 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3898 "No enough queues left for VMDq");
3901 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3904 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3905 vsi_count += pf->max_nb_vmdq_vsi;
3907 if (hw->func_caps.dcb)
3908 pf->flags |= I40E_FLAG_DCB;
3910 if (qp_count > hw->func_caps.num_tx_qp) {
3912 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3913 qp_count, hw->func_caps.num_tx_qp);
3916 if (vsi_count > hw->func_caps.num_vsis) {
3918 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3919 vsi_count, hw->func_caps.num_vsis);
3927 i40e_pf_get_switch_config(struct i40e_pf *pf)
3929 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3930 struct i40e_aqc_get_switch_config_resp *switch_config;
3931 struct i40e_aqc_switch_config_element_resp *element;
3932 uint16_t start_seid = 0, num_reported;
3935 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3936 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3937 if (!switch_config) {
3938 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3942 /* Get the switch configurations */
3943 ret = i40e_aq_get_switch_config(hw, switch_config,
3944 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3945 if (ret != I40E_SUCCESS) {
3946 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3949 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3950 if (num_reported != 1) { /* The number should be 1 */
3951 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3955 /* Parse the switch configuration elements */
3956 element = &(switch_config->element[0]);
3957 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3958 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3959 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3961 PMD_DRV_LOG(INFO, "Unknown element type");
3964 rte_free(switch_config);
3970 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3973 struct pool_entry *entry;
3975 if (pool == NULL || num == 0)
3978 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3979 if (entry == NULL) {
3980 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3984 /* queue heap initialize */
3985 pool->num_free = num;
3986 pool->num_alloc = 0;
3988 LIST_INIT(&pool->alloc_list);
3989 LIST_INIT(&pool->free_list);
3991 /* Initialize element */
3995 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4000 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4002 struct pool_entry *entry, *next_entry;
4007 for (entry = LIST_FIRST(&pool->alloc_list);
4008 entry && (next_entry = LIST_NEXT(entry, next), 1);
4009 entry = next_entry) {
4010 LIST_REMOVE(entry, next);
4014 for (entry = LIST_FIRST(&pool->free_list);
4015 entry && (next_entry = LIST_NEXT(entry, next), 1);
4016 entry = next_entry) {
4017 LIST_REMOVE(entry, next);
4022 pool->num_alloc = 0;
4024 LIST_INIT(&pool->alloc_list);
4025 LIST_INIT(&pool->free_list);
4029 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4032 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4033 uint32_t pool_offset;
4037 PMD_DRV_LOG(ERR, "Invalid parameter");
4041 pool_offset = base - pool->base;
4042 /* Lookup in alloc list */
4043 LIST_FOREACH(entry, &pool->alloc_list, next) {
4044 if (entry->base == pool_offset) {
4045 valid_entry = entry;
4046 LIST_REMOVE(entry, next);
4051 /* Not find, return */
4052 if (valid_entry == NULL) {
4053 PMD_DRV_LOG(ERR, "Failed to find entry");
4058 * Found it, move it to free list and try to merge.
4059 * In order to make merge easier, always sort it by qbase.
4060 * Find adjacent prev and last entries.
4063 LIST_FOREACH(entry, &pool->free_list, next) {
4064 if (entry->base > valid_entry->base) {
4072 /* Try to merge with next one*/
4074 /* Merge with next one */
4075 if (valid_entry->base + valid_entry->len == next->base) {
4076 next->base = valid_entry->base;
4077 next->len += valid_entry->len;
4078 rte_free(valid_entry);
4085 /* Merge with previous one */
4086 if (prev->base + prev->len == valid_entry->base) {
4087 prev->len += valid_entry->len;
4088 /* If it merge with next one, remove next node */
4090 LIST_REMOVE(valid_entry, next);
4091 rte_free(valid_entry);
4093 rte_free(valid_entry);
4099 /* Not find any entry to merge, insert */
4102 LIST_INSERT_AFTER(prev, valid_entry, next);
4103 else if (next != NULL)
4104 LIST_INSERT_BEFORE(next, valid_entry, next);
4105 else /* It's empty list, insert to head */
4106 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4109 pool->num_free += valid_entry->len;
4110 pool->num_alloc -= valid_entry->len;
4116 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4119 struct pool_entry *entry, *valid_entry;
4121 if (pool == NULL || num == 0) {
4122 PMD_DRV_LOG(ERR, "Invalid parameter");
4126 if (pool->num_free < num) {
4127 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4128 num, pool->num_free);
4133 /* Lookup in free list and find most fit one */
4134 LIST_FOREACH(entry, &pool->free_list, next) {
4135 if (entry->len >= num) {
4137 if (entry->len == num) {
4138 valid_entry = entry;
4141 if (valid_entry == NULL || valid_entry->len > entry->len)
4142 valid_entry = entry;
4146 /* Not find one to satisfy the request, return */
4147 if (valid_entry == NULL) {
4148 PMD_DRV_LOG(ERR, "No valid entry found");
4152 * The entry have equal queue number as requested,
4153 * remove it from alloc_list.
4155 if (valid_entry->len == num) {
4156 LIST_REMOVE(valid_entry, next);
4159 * The entry have more numbers than requested,
4160 * create a new entry for alloc_list and minus its
4161 * queue base and number in free_list.
4163 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4164 if (entry == NULL) {
4166 "Failed to allocate memory for resource pool");
4169 entry->base = valid_entry->base;
4171 valid_entry->base += num;
4172 valid_entry->len -= num;
4173 valid_entry = entry;
4176 /* Insert it into alloc list, not sorted */
4177 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4179 pool->num_free -= valid_entry->len;
4180 pool->num_alloc += valid_entry->len;
4182 return valid_entry->base + pool->base;
4186 * bitmap_is_subset - Check whether src2 is subset of src1
4189 bitmap_is_subset(uint8_t src1, uint8_t src2)
4191 return !((src1 ^ src2) & src2);
4194 static enum i40e_status_code
4195 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4197 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4199 /* If DCB is not supported, only default TC is supported */
4200 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4201 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4202 return I40E_NOT_SUPPORTED;
4205 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4207 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4208 hw->func_caps.enabled_tcmap, enabled_tcmap);
4209 return I40E_NOT_SUPPORTED;
4211 return I40E_SUCCESS;
4215 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4216 struct i40e_vsi_vlan_pvid_info *info)
4219 struct i40e_vsi_context ctxt;
4220 uint8_t vlan_flags = 0;
4223 if (vsi == NULL || info == NULL) {
4224 PMD_DRV_LOG(ERR, "invalid parameters");
4225 return I40E_ERR_PARAM;
4229 vsi->info.pvid = info->config.pvid;
4231 * If insert pvid is enabled, only tagged pkts are
4232 * allowed to be sent out.
4234 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4235 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4238 if (info->config.reject.tagged == 0)
4239 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4241 if (info->config.reject.untagged == 0)
4242 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4244 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4245 I40E_AQ_VSI_PVLAN_MODE_MASK);
4246 vsi->info.port_vlan_flags |= vlan_flags;
4247 vsi->info.valid_sections =
4248 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4249 memset(&ctxt, 0, sizeof(ctxt));
4250 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4251 ctxt.seid = vsi->seid;
4253 hw = I40E_VSI_TO_HW(vsi);
4254 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4255 if (ret != I40E_SUCCESS)
4256 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4262 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4264 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4266 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4268 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4269 if (ret != I40E_SUCCESS)
4273 PMD_DRV_LOG(ERR, "seid not valid");
4277 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4278 tc_bw_data.tc_valid_bits = enabled_tcmap;
4279 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4280 tc_bw_data.tc_bw_credits[i] =
4281 (enabled_tcmap & (1 << i)) ? 1 : 0;
4283 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4284 if (ret != I40E_SUCCESS) {
4285 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4289 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4290 sizeof(vsi->info.qs_handle));
4291 return I40E_SUCCESS;
4294 static enum i40e_status_code
4295 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4296 struct i40e_aqc_vsi_properties_data *info,
4297 uint8_t enabled_tcmap)
4299 enum i40e_status_code ret;
4300 int i, total_tc = 0;
4301 uint16_t qpnum_per_tc, bsf, qp_idx;
4303 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4304 if (ret != I40E_SUCCESS)
4307 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4308 if (enabled_tcmap & (1 << i))
4310 vsi->enabled_tc = enabled_tcmap;
4312 /* Number of queues per enabled TC */
4313 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4314 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4315 bsf = rte_bsf32(qpnum_per_tc);
4317 /* Adjust the queue number to actual queues that can be applied */
4318 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4319 vsi->nb_qps = qpnum_per_tc * total_tc;
4322 * Configure TC and queue mapping parameters, for enabled TC,
4323 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4324 * default queue will serve it.
4327 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4328 if (vsi->enabled_tc & (1 << i)) {
4329 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4330 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4331 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4332 qp_idx += qpnum_per_tc;
4334 info->tc_mapping[i] = 0;
4337 /* Associate queue number with VSI */
4338 if (vsi->type == I40E_VSI_SRIOV) {
4339 info->mapping_flags |=
4340 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4341 for (i = 0; i < vsi->nb_qps; i++)
4342 info->queue_mapping[i] =
4343 rte_cpu_to_le_16(vsi->base_queue + i);
4345 info->mapping_flags |=
4346 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4347 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4349 info->valid_sections |=
4350 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4352 return I40E_SUCCESS;
4356 i40e_veb_release(struct i40e_veb *veb)
4358 struct i40e_vsi *vsi;
4364 if (!TAILQ_EMPTY(&veb->head)) {
4365 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4368 /* associate_vsi field is NULL for floating VEB */
4369 if (veb->associate_vsi != NULL) {
4370 vsi = veb->associate_vsi;
4371 hw = I40E_VSI_TO_HW(vsi);
4373 vsi->uplink_seid = veb->uplink_seid;
4376 veb->associate_pf->main_vsi->floating_veb = NULL;
4377 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4380 i40e_aq_delete_element(hw, veb->seid, NULL);
4382 return I40E_SUCCESS;
4386 static struct i40e_veb *
4387 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4389 struct i40e_veb *veb;
4395 "veb setup failed, associated PF shouldn't null");
4398 hw = I40E_PF_TO_HW(pf);
4400 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4402 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4406 veb->associate_vsi = vsi;
4407 veb->associate_pf = pf;
4408 TAILQ_INIT(&veb->head);
4409 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4411 /* create floating veb if vsi is NULL */
4413 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4414 I40E_DEFAULT_TCMAP, false,
4415 &veb->seid, false, NULL);
4417 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4418 true, &veb->seid, false, NULL);
4421 if (ret != I40E_SUCCESS) {
4422 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4423 hw->aq.asq_last_status);
4426 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4428 /* get statistics index */
4429 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4430 &veb->stats_idx, NULL, NULL, NULL);
4431 if (ret != I40E_SUCCESS) {
4432 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4433 hw->aq.asq_last_status);
4436 /* Get VEB bandwidth, to be implemented */
4437 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4439 vsi->uplink_seid = veb->seid;
4448 i40e_vsi_release(struct i40e_vsi *vsi)
4452 struct i40e_vsi_list *vsi_list;
4455 struct i40e_mac_filter *f;
4456 uint16_t user_param;
4459 return I40E_SUCCESS;
4464 user_param = vsi->user_param;
4466 pf = I40E_VSI_TO_PF(vsi);
4467 hw = I40E_VSI_TO_HW(vsi);
4469 /* VSI has child to attach, release child first */
4471 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4472 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4475 i40e_veb_release(vsi->veb);
4478 if (vsi->floating_veb) {
4479 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4480 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4485 /* Remove all macvlan filters of the VSI */
4486 i40e_vsi_remove_all_macvlan_filter(vsi);
4487 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4490 if (vsi->type != I40E_VSI_MAIN &&
4491 ((vsi->type != I40E_VSI_SRIOV) ||
4492 !pf->floating_veb_list[user_param])) {
4493 /* Remove vsi from parent's sibling list */
4494 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4495 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4496 return I40E_ERR_PARAM;
4498 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4499 &vsi->sib_vsi_list, list);
4501 /* Remove all switch element of the VSI */
4502 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4503 if (ret != I40E_SUCCESS)
4504 PMD_DRV_LOG(ERR, "Failed to delete element");
4507 if ((vsi->type == I40E_VSI_SRIOV) &&
4508 pf->floating_veb_list[user_param]) {
4509 /* Remove vsi from parent's sibling list */
4510 if (vsi->parent_vsi == NULL ||
4511 vsi->parent_vsi->floating_veb == NULL) {
4512 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4513 return I40E_ERR_PARAM;
4515 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4516 &vsi->sib_vsi_list, list);
4518 /* Remove all switch element of the VSI */
4519 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4520 if (ret != I40E_SUCCESS)
4521 PMD_DRV_LOG(ERR, "Failed to delete element");
4524 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4526 if (vsi->type != I40E_VSI_SRIOV)
4527 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4530 return I40E_SUCCESS;
4534 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4536 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4537 struct i40e_aqc_remove_macvlan_element_data def_filter;
4538 struct i40e_mac_filter_info filter;
4541 if (vsi->type != I40E_VSI_MAIN)
4542 return I40E_ERR_CONFIG;
4543 memset(&def_filter, 0, sizeof(def_filter));
4544 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4546 def_filter.vlan_tag = 0;
4547 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4548 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4549 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4550 if (ret != I40E_SUCCESS) {
4551 struct i40e_mac_filter *f;
4552 struct ether_addr *mac;
4555 "Cannot remove the default macvlan filter");
4556 /* It needs to add the permanent mac into mac list */
4557 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4559 PMD_DRV_LOG(ERR, "failed to allocate memory");
4560 return I40E_ERR_NO_MEMORY;
4562 mac = &f->mac_info.mac_addr;
4563 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4565 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4566 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4571 (void)rte_memcpy(&filter.mac_addr,
4572 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4573 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4574 return i40e_vsi_add_mac(vsi, &filter);
4578 * i40e_vsi_get_bw_config - Query VSI BW Information
4579 * @vsi: the VSI to be queried
4581 * Returns 0 on success, negative value on failure
4583 static enum i40e_status_code
4584 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4586 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4587 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4588 struct i40e_hw *hw = &vsi->adapter->hw;
4593 memset(&bw_config, 0, sizeof(bw_config));
4594 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4595 if (ret != I40E_SUCCESS) {
4596 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4597 hw->aq.asq_last_status);
4601 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4602 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4603 &ets_sla_config, NULL);
4604 if (ret != I40E_SUCCESS) {
4606 "VSI failed to get TC bandwdith configuration %u",
4607 hw->aq.asq_last_status);
4611 /* store and print out BW info */
4612 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4613 vsi->bw_info.bw_max = bw_config.max_bw;
4614 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4615 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4616 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4617 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4619 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4620 vsi->bw_info.bw_ets_share_credits[i] =
4621 ets_sla_config.share_credits[i];
4622 vsi->bw_info.bw_ets_credits[i] =
4623 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4624 /* 4 bits per TC, 4th bit is reserved */
4625 vsi->bw_info.bw_ets_max[i] =
4626 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4627 RTE_LEN2MASK(3, uint8_t));
4628 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4629 vsi->bw_info.bw_ets_share_credits[i]);
4630 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4631 vsi->bw_info.bw_ets_credits[i]);
4632 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4633 vsi->bw_info.bw_ets_max[i]);
4636 return I40E_SUCCESS;
4639 /* i40e_enable_pf_lb
4640 * @pf: pointer to the pf structure
4642 * allow loopback on pf
4645 i40e_enable_pf_lb(struct i40e_pf *pf)
4647 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4648 struct i40e_vsi_context ctxt;
4651 /* Use the FW API if FW >= v5.0 */
4652 if (hw->aq.fw_maj_ver < 5) {
4653 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4657 memset(&ctxt, 0, sizeof(ctxt));
4658 ctxt.seid = pf->main_vsi_seid;
4659 ctxt.pf_num = hw->pf_id;
4660 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4662 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4663 ret, hw->aq.asq_last_status);
4666 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4667 ctxt.info.valid_sections =
4668 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4669 ctxt.info.switch_id |=
4670 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4672 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4674 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4675 hw->aq.asq_last_status);
4680 i40e_vsi_setup(struct i40e_pf *pf,
4681 enum i40e_vsi_type type,
4682 struct i40e_vsi *uplink_vsi,
4683 uint16_t user_param)
4685 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4686 struct i40e_vsi *vsi;
4687 struct i40e_mac_filter_info filter;
4689 struct i40e_vsi_context ctxt;
4690 struct ether_addr broadcast =
4691 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4693 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4694 uplink_vsi == NULL) {
4696 "VSI setup failed, VSI link shouldn't be NULL");
4700 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4702 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4707 * 1.type is not MAIN and uplink vsi is not NULL
4708 * If uplink vsi didn't setup VEB, create one first under veb field
4709 * 2.type is SRIOV and the uplink is NULL
4710 * If floating VEB is NULL, create one veb under floating veb field
4713 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4714 uplink_vsi->veb == NULL) {
4715 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4717 if (uplink_vsi->veb == NULL) {
4718 PMD_DRV_LOG(ERR, "VEB setup failed");
4721 /* set ALLOWLOOPBACk on pf, when veb is created */
4722 i40e_enable_pf_lb(pf);
4725 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4726 pf->main_vsi->floating_veb == NULL) {
4727 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4729 if (pf->main_vsi->floating_veb == NULL) {
4730 PMD_DRV_LOG(ERR, "VEB setup failed");
4735 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4737 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4740 TAILQ_INIT(&vsi->mac_list);
4742 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4743 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4744 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4745 vsi->user_param = user_param;
4746 vsi->vlan_anti_spoof_on = 0;
4747 vsi->vlan_filter_on = 0;
4748 /* Allocate queues */
4749 switch (vsi->type) {
4750 case I40E_VSI_MAIN :
4751 vsi->nb_qps = pf->lan_nb_qps;
4753 case I40E_VSI_SRIOV :
4754 vsi->nb_qps = pf->vf_nb_qps;
4756 case I40E_VSI_VMDQ2:
4757 vsi->nb_qps = pf->vmdq_nb_qps;
4760 vsi->nb_qps = pf->fdir_nb_qps;
4766 * The filter status descriptor is reported in rx queue 0,
4767 * while the tx queue for fdir filter programming has no
4768 * such constraints, can be non-zero queues.
4769 * To simplify it, choose FDIR vsi use queue 0 pair.
4770 * To make sure it will use queue 0 pair, queue allocation
4771 * need be done before this function is called
4773 if (type != I40E_VSI_FDIR) {
4774 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4776 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4780 vsi->base_queue = ret;
4782 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4784 /* VF has MSIX interrupt in VF range, don't allocate here */
4785 if (type == I40E_VSI_MAIN) {
4786 ret = i40e_res_pool_alloc(&pf->msix_pool,
4787 RTE_MIN(vsi->nb_qps,
4788 RTE_MAX_RXTX_INTR_VEC_ID));
4790 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4792 goto fail_queue_alloc;
4794 vsi->msix_intr = ret;
4795 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4796 } else if (type != I40E_VSI_SRIOV) {
4797 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4799 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4800 goto fail_queue_alloc;
4802 vsi->msix_intr = ret;
4810 if (type == I40E_VSI_MAIN) {
4811 /* For main VSI, no need to add since it's default one */
4812 vsi->uplink_seid = pf->mac_seid;
4813 vsi->seid = pf->main_vsi_seid;
4814 /* Bind queues with specific MSIX interrupt */
4816 * Needs 2 interrupt at least, one for misc cause which will
4817 * enabled from OS side, Another for queues binding the
4818 * interrupt from device side only.
4821 /* Get default VSI parameters from hardware */
4822 memset(&ctxt, 0, sizeof(ctxt));
4823 ctxt.seid = vsi->seid;
4824 ctxt.pf_num = hw->pf_id;
4825 ctxt.uplink_seid = vsi->uplink_seid;
4827 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4828 if (ret != I40E_SUCCESS) {
4829 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4830 goto fail_msix_alloc;
4832 (void)rte_memcpy(&vsi->info, &ctxt.info,
4833 sizeof(struct i40e_aqc_vsi_properties_data));
4834 vsi->vsi_id = ctxt.vsi_number;
4835 vsi->info.valid_sections = 0;
4837 /* Configure tc, enabled TC0 only */
4838 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4840 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4841 goto fail_msix_alloc;
4844 /* TC, queue mapping */
4845 memset(&ctxt, 0, sizeof(ctxt));
4846 vsi->info.valid_sections |=
4847 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4848 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4849 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4850 (void)rte_memcpy(&ctxt.info, &vsi->info,
4851 sizeof(struct i40e_aqc_vsi_properties_data));
4852 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4853 I40E_DEFAULT_TCMAP);
4854 if (ret != I40E_SUCCESS) {
4856 "Failed to configure TC queue mapping");
4857 goto fail_msix_alloc;
4859 ctxt.seid = vsi->seid;
4860 ctxt.pf_num = hw->pf_id;
4861 ctxt.uplink_seid = vsi->uplink_seid;
4864 /* Update VSI parameters */
4865 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4866 if (ret != I40E_SUCCESS) {
4867 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4868 goto fail_msix_alloc;
4871 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4872 sizeof(vsi->info.tc_mapping));
4873 (void)rte_memcpy(&vsi->info.queue_mapping,
4874 &ctxt.info.queue_mapping,
4875 sizeof(vsi->info.queue_mapping));
4876 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4877 vsi->info.valid_sections = 0;
4879 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4883 * Updating default filter settings are necessary to prevent
4884 * reception of tagged packets.
4885 * Some old firmware configurations load a default macvlan
4886 * filter which accepts both tagged and untagged packets.
4887 * The updating is to use a normal filter instead if needed.
4888 * For NVM 4.2.2 or after, the updating is not needed anymore.
4889 * The firmware with correct configurations load the default
4890 * macvlan filter which is expected and cannot be removed.
4892 i40e_update_default_filter_setting(vsi);
4893 i40e_config_qinq(hw, vsi);
4894 } else if (type == I40E_VSI_SRIOV) {
4895 memset(&ctxt, 0, sizeof(ctxt));
4897 * For other VSI, the uplink_seid equals to uplink VSI's
4898 * uplink_seid since they share same VEB
4900 if (uplink_vsi == NULL)
4901 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4903 vsi->uplink_seid = uplink_vsi->uplink_seid;
4904 ctxt.pf_num = hw->pf_id;
4905 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4906 ctxt.uplink_seid = vsi->uplink_seid;
4907 ctxt.connection_type = 0x1;
4908 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4910 /* Use the VEB configuration if FW >= v5.0 */
4911 if (hw->aq.fw_maj_ver >= 5) {
4912 /* Configure switch ID */
4913 ctxt.info.valid_sections |=
4914 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4915 ctxt.info.switch_id =
4916 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4919 /* Configure port/vlan */
4920 ctxt.info.valid_sections |=
4921 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4922 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4923 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4924 hw->func_caps.enabled_tcmap);
4925 if (ret != I40E_SUCCESS) {
4927 "Failed to configure TC queue mapping");
4928 goto fail_msix_alloc;
4931 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4932 ctxt.info.valid_sections |=
4933 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4935 * Since VSI is not created yet, only configure parameter,
4936 * will add vsi below.
4939 i40e_config_qinq(hw, vsi);
4940 } else if (type == I40E_VSI_VMDQ2) {
4941 memset(&ctxt, 0, sizeof(ctxt));
4943 * For other VSI, the uplink_seid equals to uplink VSI's
4944 * uplink_seid since they share same VEB
4946 vsi->uplink_seid = uplink_vsi->uplink_seid;
4947 ctxt.pf_num = hw->pf_id;
4949 ctxt.uplink_seid = vsi->uplink_seid;
4950 ctxt.connection_type = 0x1;
4951 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4953 ctxt.info.valid_sections |=
4954 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4955 /* user_param carries flag to enable loop back */
4957 ctxt.info.switch_id =
4958 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4959 ctxt.info.switch_id |=
4960 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4963 /* Configure port/vlan */
4964 ctxt.info.valid_sections |=
4965 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4966 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4967 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4968 I40E_DEFAULT_TCMAP);
4969 if (ret != I40E_SUCCESS) {
4971 "Failed to configure TC queue mapping");
4972 goto fail_msix_alloc;
4974 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4975 ctxt.info.valid_sections |=
4976 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4977 } else if (type == I40E_VSI_FDIR) {
4978 memset(&ctxt, 0, sizeof(ctxt));
4979 vsi->uplink_seid = uplink_vsi->uplink_seid;
4980 ctxt.pf_num = hw->pf_id;
4982 ctxt.uplink_seid = vsi->uplink_seid;
4983 ctxt.connection_type = 0x1; /* regular data port */
4984 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4985 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4986 I40E_DEFAULT_TCMAP);
4987 if (ret != I40E_SUCCESS) {
4989 "Failed to configure TC queue mapping.");
4990 goto fail_msix_alloc;
4992 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4993 ctxt.info.valid_sections |=
4994 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4996 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4997 goto fail_msix_alloc;
5000 if (vsi->type != I40E_VSI_MAIN) {
5001 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5002 if (ret != I40E_SUCCESS) {
5003 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5004 hw->aq.asq_last_status);
5005 goto fail_msix_alloc;
5007 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5008 vsi->info.valid_sections = 0;
5009 vsi->seid = ctxt.seid;
5010 vsi->vsi_id = ctxt.vsi_number;
5011 vsi->sib_vsi_list.vsi = vsi;
5012 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5013 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5014 &vsi->sib_vsi_list, list);
5016 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5017 &vsi->sib_vsi_list, list);
5021 /* MAC/VLAN configuration */
5022 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5023 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5025 ret = i40e_vsi_add_mac(vsi, &filter);
5026 if (ret != I40E_SUCCESS) {
5027 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5028 goto fail_msix_alloc;
5031 /* Get VSI BW information */
5032 i40e_vsi_get_bw_config(vsi);
5035 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5037 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5043 /* Configure vlan filter on or off */
5045 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5048 struct i40e_mac_filter *f;
5050 struct i40e_mac_filter_info *mac_filter;
5051 enum rte_mac_filter_type desired_filter;
5052 int ret = I40E_SUCCESS;
5055 /* Filter to match MAC and VLAN */
5056 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5058 /* Filter to match only MAC */
5059 desired_filter = RTE_MAC_PERFECT_MATCH;
5064 mac_filter = rte_zmalloc("mac_filter_info_data",
5065 num * sizeof(*mac_filter), 0);
5066 if (mac_filter == NULL) {
5067 PMD_DRV_LOG(ERR, "failed to allocate memory");
5068 return I40E_ERR_NO_MEMORY;
5073 /* Remove all existing mac */
5074 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5075 mac_filter[i] = f->mac_info;
5076 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5078 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5079 on ? "enable" : "disable");
5085 /* Override with new filter */
5086 for (i = 0; i < num; i++) {
5087 mac_filter[i].filter_type = desired_filter;
5088 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5090 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5091 on ? "enable" : "disable");
5097 rte_free(mac_filter);
5101 /* Configure vlan stripping on or off */
5103 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5105 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5106 struct i40e_vsi_context ctxt;
5108 int ret = I40E_SUCCESS;
5110 /* Check if it has been already on or off */
5111 if (vsi->info.valid_sections &
5112 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5114 if ((vsi->info.port_vlan_flags &
5115 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5116 return 0; /* already on */
5118 if ((vsi->info.port_vlan_flags &
5119 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5120 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5121 return 0; /* already off */
5126 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5128 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5129 vsi->info.valid_sections =
5130 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5131 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5132 vsi->info.port_vlan_flags |= vlan_flags;
5133 ctxt.seid = vsi->seid;
5134 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5135 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5137 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5138 on ? "enable" : "disable");
5144 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5146 struct rte_eth_dev_data *data = dev->data;
5150 /* Apply vlan offload setting */
5151 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5152 i40e_vlan_offload_set(dev, mask);
5154 /* Apply double-vlan setting, not implemented yet */
5156 /* Apply pvid setting */
5157 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5158 data->dev_conf.txmode.hw_vlan_insert_pvid);
5160 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5166 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5168 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5170 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5174 i40e_update_flow_control(struct i40e_hw *hw)
5176 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5177 struct i40e_link_status link_status;
5178 uint32_t rxfc = 0, txfc = 0, reg;
5182 memset(&link_status, 0, sizeof(link_status));
5183 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5184 if (ret != I40E_SUCCESS) {
5185 PMD_DRV_LOG(ERR, "Failed to get link status information");
5186 goto write_reg; /* Disable flow control */
5189 an_info = hw->phy.link_info.an_info;
5190 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5191 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5192 ret = I40E_ERR_NOT_READY;
5193 goto write_reg; /* Disable flow control */
5196 * If link auto negotiation is enabled, flow control needs to
5197 * be configured according to it
5199 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5200 case I40E_LINK_PAUSE_RXTX:
5203 hw->fc.current_mode = I40E_FC_FULL;
5205 case I40E_AQ_LINK_PAUSE_RX:
5207 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5209 case I40E_AQ_LINK_PAUSE_TX:
5211 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5214 hw->fc.current_mode = I40E_FC_NONE;
5219 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5220 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5221 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5222 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5223 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5224 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5231 i40e_pf_setup(struct i40e_pf *pf)
5233 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5234 struct i40e_filter_control_settings settings;
5235 struct i40e_vsi *vsi;
5238 /* Clear all stats counters */
5239 pf->offset_loaded = FALSE;
5240 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5241 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5242 pf->internal_rx_bytes = 0;
5243 pf->internal_tx_bytes = 0;
5244 pf->internal_rx_bytes_offset = 0;
5245 pf->internal_tx_bytes_offset = 0;
5247 ret = i40e_pf_get_switch_config(pf);
5248 if (ret != I40E_SUCCESS) {
5249 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5252 if (pf->flags & I40E_FLAG_FDIR) {
5253 /* make queue allocated first, let FDIR use queue pair 0*/
5254 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5255 if (ret != I40E_FDIR_QUEUE_ID) {
5257 "queue allocation fails for FDIR: ret =%d",
5259 pf->flags &= ~I40E_FLAG_FDIR;
5262 /* main VSI setup */
5263 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5265 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5266 return I40E_ERR_NOT_READY;
5270 /* Configure filter control */
5271 memset(&settings, 0, sizeof(settings));
5272 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5273 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5274 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5275 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5277 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5278 hw->func_caps.rss_table_size);
5279 return I40E_ERR_PARAM;
5281 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5282 hw->func_caps.rss_table_size);
5283 pf->hash_lut_size = hw->func_caps.rss_table_size;
5285 /* Enable ethtype and macvlan filters */
5286 settings.enable_ethtype = TRUE;
5287 settings.enable_macvlan = TRUE;
5288 ret = i40e_set_filter_control(hw, &settings);
5290 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5293 /* Update flow control according to the auto negotiation */
5294 i40e_update_flow_control(hw);
5296 return I40E_SUCCESS;
5300 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5306 * Set or clear TX Queue Disable flags,
5307 * which is required by hardware.
5309 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5310 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5312 /* Wait until the request is finished */
5313 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5314 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5315 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5316 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5317 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5323 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5324 return I40E_SUCCESS; /* already on, skip next steps */
5326 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5327 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5329 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5330 return I40E_SUCCESS; /* already off, skip next steps */
5331 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5333 /* Write the register */
5334 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5335 /* Check the result */
5336 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5337 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5338 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5340 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5341 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5344 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5345 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5349 /* Check if it is timeout */
5350 if (j >= I40E_CHK_Q_ENA_COUNT) {
5351 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5352 (on ? "enable" : "disable"), q_idx);
5353 return I40E_ERR_TIMEOUT;
5356 return I40E_SUCCESS;
5359 /* Swith on or off the tx queues */
5361 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5363 struct rte_eth_dev_data *dev_data = pf->dev_data;
5364 struct i40e_tx_queue *txq;
5365 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5369 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5370 txq = dev_data->tx_queues[i];
5371 /* Don't operate the queue if not configured or
5372 * if starting only per queue */
5373 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5376 ret = i40e_dev_tx_queue_start(dev, i);
5378 ret = i40e_dev_tx_queue_stop(dev, i);
5379 if ( ret != I40E_SUCCESS)
5383 return I40E_SUCCESS;
5387 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5392 /* Wait until the request is finished */
5393 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5394 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5395 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5396 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5397 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5402 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5403 return I40E_SUCCESS; /* Already on, skip next steps */
5404 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5406 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5407 return I40E_SUCCESS; /* Already off, skip next steps */
5408 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5411 /* Write the register */
5412 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5413 /* Check the result */
5414 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5415 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5416 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5418 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5419 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5422 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5423 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5428 /* Check if it is timeout */
5429 if (j >= I40E_CHK_Q_ENA_COUNT) {
5430 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5431 (on ? "enable" : "disable"), q_idx);
5432 return I40E_ERR_TIMEOUT;
5435 return I40E_SUCCESS;
5437 /* Switch on or off the rx queues */
5439 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5441 struct rte_eth_dev_data *dev_data = pf->dev_data;
5442 struct i40e_rx_queue *rxq;
5443 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5447 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5448 rxq = dev_data->rx_queues[i];
5449 /* Don't operate the queue if not configured or
5450 * if starting only per queue */
5451 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5454 ret = i40e_dev_rx_queue_start(dev, i);
5456 ret = i40e_dev_rx_queue_stop(dev, i);
5457 if (ret != I40E_SUCCESS)
5461 return I40E_SUCCESS;
5464 /* Switch on or off all the rx/tx queues */
5466 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5471 /* enable rx queues before enabling tx queues */
5472 ret = i40e_dev_switch_rx_queues(pf, on);
5474 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5477 ret = i40e_dev_switch_tx_queues(pf, on);
5479 /* Stop tx queues before stopping rx queues */
5480 ret = i40e_dev_switch_tx_queues(pf, on);
5482 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5485 ret = i40e_dev_switch_rx_queues(pf, on);
5491 /* Initialize VSI for TX */
5493 i40e_dev_tx_init(struct i40e_pf *pf)
5495 struct rte_eth_dev_data *data = pf->dev_data;
5497 uint32_t ret = I40E_SUCCESS;
5498 struct i40e_tx_queue *txq;
5500 for (i = 0; i < data->nb_tx_queues; i++) {
5501 txq = data->tx_queues[i];
5502 if (!txq || !txq->q_set)
5504 ret = i40e_tx_queue_init(txq);
5505 if (ret != I40E_SUCCESS)
5508 if (ret == I40E_SUCCESS)
5509 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5515 /* Initialize VSI for RX */
5517 i40e_dev_rx_init(struct i40e_pf *pf)
5519 struct rte_eth_dev_data *data = pf->dev_data;
5520 int ret = I40E_SUCCESS;
5522 struct i40e_rx_queue *rxq;
5524 i40e_pf_config_mq_rx(pf);
5525 for (i = 0; i < data->nb_rx_queues; i++) {
5526 rxq = data->rx_queues[i];
5527 if (!rxq || !rxq->q_set)
5530 ret = i40e_rx_queue_init(rxq);
5531 if (ret != I40E_SUCCESS) {
5533 "Failed to do RX queue initialization");
5537 if (ret == I40E_SUCCESS)
5538 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5545 i40e_dev_rxtx_init(struct i40e_pf *pf)
5549 err = i40e_dev_tx_init(pf);
5551 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5554 err = i40e_dev_rx_init(pf);
5556 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5564 i40e_vmdq_setup(struct rte_eth_dev *dev)
5566 struct rte_eth_conf *conf = &dev->data->dev_conf;
5567 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5568 int i, err, conf_vsis, j, loop;
5569 struct i40e_vsi *vsi;
5570 struct i40e_vmdq_info *vmdq_info;
5571 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5572 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5575 * Disable interrupt to avoid message from VF. Furthermore, it will
5576 * avoid race condition in VSI creation/destroy.
5578 i40e_pf_disable_irq0(hw);
5580 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5581 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5585 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5586 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5587 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5588 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5589 pf->max_nb_vmdq_vsi);
5593 if (pf->vmdq != NULL) {
5594 PMD_INIT_LOG(INFO, "VMDQ already configured");
5598 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5599 sizeof(*vmdq_info) * conf_vsis, 0);
5601 if (pf->vmdq == NULL) {
5602 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5606 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5608 /* Create VMDQ VSI */
5609 for (i = 0; i < conf_vsis; i++) {
5610 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5611 vmdq_conf->enable_loop_back);
5613 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5617 vmdq_info = &pf->vmdq[i];
5619 vmdq_info->vsi = vsi;
5621 pf->nb_cfg_vmdq_vsi = conf_vsis;
5623 /* Configure Vlan */
5624 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5625 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5626 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5627 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5628 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5629 vmdq_conf->pool_map[i].vlan_id, j);
5631 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5632 vmdq_conf->pool_map[i].vlan_id);
5634 PMD_INIT_LOG(ERR, "Failed to add vlan");
5642 i40e_pf_enable_irq0(hw);
5647 for (i = 0; i < conf_vsis; i++)
5648 if (pf->vmdq[i].vsi == NULL)
5651 i40e_vsi_release(pf->vmdq[i].vsi);
5655 i40e_pf_enable_irq0(hw);
5660 i40e_stat_update_32(struct i40e_hw *hw,
5668 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5672 if (new_data >= *offset)
5673 *stat = (uint64_t)(new_data - *offset);
5675 *stat = (uint64_t)((new_data +
5676 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5680 i40e_stat_update_48(struct i40e_hw *hw,
5689 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5690 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5691 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5696 if (new_data >= *offset)
5697 *stat = new_data - *offset;
5699 *stat = (uint64_t)((new_data +
5700 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5702 *stat &= I40E_48_BIT_MASK;
5707 i40e_pf_disable_irq0(struct i40e_hw *hw)
5709 /* Disable all interrupt types */
5710 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5711 I40E_WRITE_FLUSH(hw);
5716 i40e_pf_enable_irq0(struct i40e_hw *hw)
5718 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5719 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5720 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5721 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5722 I40E_WRITE_FLUSH(hw);
5726 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5728 /* read pending request and disable first */
5729 i40e_pf_disable_irq0(hw);
5730 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5731 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5732 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5735 /* Link no queues with irq0 */
5736 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5737 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5741 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5743 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5744 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5747 uint32_t index, offset, val;
5752 * Try to find which VF trigger a reset, use absolute VF id to access
5753 * since the reg is global register.
5755 for (i = 0; i < pf->vf_num; i++) {
5756 abs_vf_id = hw->func_caps.vf_base_id + i;
5757 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5758 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5759 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5760 /* VFR event occurred */
5761 if (val & (0x1 << offset)) {
5764 /* Clear the event first */
5765 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5767 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5769 * Only notify a VF reset event occurred,
5770 * don't trigger another SW reset
5772 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5773 if (ret != I40E_SUCCESS)
5774 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5780 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5782 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5785 for (i = 0; i < pf->vf_num; i++)
5786 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5790 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5792 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5793 struct i40e_arq_event_info info;
5794 uint16_t pending, opcode;
5797 info.buf_len = I40E_AQ_BUF_SZ;
5798 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5799 if (!info.msg_buf) {
5800 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5806 ret = i40e_clean_arq_element(hw, &info, &pending);
5808 if (ret != I40E_SUCCESS) {
5810 "Failed to read msg from AdminQ, aq_err: %u",
5811 hw->aq.asq_last_status);
5814 opcode = rte_le_to_cpu_16(info.desc.opcode);
5817 case i40e_aqc_opc_send_msg_to_pf:
5818 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5819 i40e_pf_host_handle_vf_msg(dev,
5820 rte_le_to_cpu_16(info.desc.retval),
5821 rte_le_to_cpu_32(info.desc.cookie_high),
5822 rte_le_to_cpu_32(info.desc.cookie_low),
5826 case i40e_aqc_opc_get_link_status:
5827 ret = i40e_dev_link_update(dev, 0);
5829 _rte_eth_dev_callback_process(dev,
5830 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5833 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5838 rte_free(info.msg_buf);
5842 * Interrupt handler triggered by NIC for handling
5843 * specific interrupt.
5846 * Pointer to interrupt handle.
5848 * The address of parameter (struct rte_eth_dev *) regsitered before.
5854 i40e_dev_interrupt_handler(void *param)
5856 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5857 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5860 /* Disable interrupt */
5861 i40e_pf_disable_irq0(hw);
5863 /* read out interrupt causes */
5864 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5866 /* No interrupt event indicated */
5867 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5868 PMD_DRV_LOG(INFO, "No interrupt event");
5871 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5872 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5873 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5874 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5875 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5876 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5877 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5878 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5879 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5880 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5881 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5882 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5883 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5884 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5886 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5887 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5888 i40e_dev_handle_vfr_event(dev);
5890 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5891 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5892 i40e_dev_handle_aq_msg(dev);
5896 /* Enable interrupt */
5897 i40e_pf_enable_irq0(hw);
5898 rte_intr_enable(dev->intr_handle);
5902 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5903 struct i40e_macvlan_filter *filter,
5906 int ele_num, ele_buff_size;
5907 int num, actual_num, i;
5909 int ret = I40E_SUCCESS;
5910 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5911 struct i40e_aqc_add_macvlan_element_data *req_list;
5913 if (filter == NULL || total == 0)
5914 return I40E_ERR_PARAM;
5915 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5916 ele_buff_size = hw->aq.asq_buf_size;
5918 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5919 if (req_list == NULL) {
5920 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5921 return I40E_ERR_NO_MEMORY;
5926 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5927 memset(req_list, 0, ele_buff_size);
5929 for (i = 0; i < actual_num; i++) {
5930 (void)rte_memcpy(req_list[i].mac_addr,
5931 &filter[num + i].macaddr, ETH_ADDR_LEN);
5932 req_list[i].vlan_tag =
5933 rte_cpu_to_le_16(filter[num + i].vlan_id);
5935 switch (filter[num + i].filter_type) {
5936 case RTE_MAC_PERFECT_MATCH:
5937 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5938 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5940 case RTE_MACVLAN_PERFECT_MATCH:
5941 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5943 case RTE_MAC_HASH_MATCH:
5944 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5945 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5947 case RTE_MACVLAN_HASH_MATCH:
5948 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5951 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5952 ret = I40E_ERR_PARAM;
5956 req_list[i].queue_number = 0;
5958 req_list[i].flags = rte_cpu_to_le_16(flags);
5961 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5963 if (ret != I40E_SUCCESS) {
5964 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5968 } while (num < total);
5976 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5977 struct i40e_macvlan_filter *filter,
5980 int ele_num, ele_buff_size;
5981 int num, actual_num, i;
5983 int ret = I40E_SUCCESS;
5984 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5985 struct i40e_aqc_remove_macvlan_element_data *req_list;
5987 if (filter == NULL || total == 0)
5988 return I40E_ERR_PARAM;
5990 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5991 ele_buff_size = hw->aq.asq_buf_size;
5993 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5994 if (req_list == NULL) {
5995 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5996 return I40E_ERR_NO_MEMORY;
6001 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6002 memset(req_list, 0, ele_buff_size);
6004 for (i = 0; i < actual_num; i++) {
6005 (void)rte_memcpy(req_list[i].mac_addr,
6006 &filter[num + i].macaddr, ETH_ADDR_LEN);
6007 req_list[i].vlan_tag =
6008 rte_cpu_to_le_16(filter[num + i].vlan_id);
6010 switch (filter[num + i].filter_type) {
6011 case RTE_MAC_PERFECT_MATCH:
6012 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6013 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6015 case RTE_MACVLAN_PERFECT_MATCH:
6016 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6018 case RTE_MAC_HASH_MATCH:
6019 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6020 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6022 case RTE_MACVLAN_HASH_MATCH:
6023 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6026 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6027 ret = I40E_ERR_PARAM;
6030 req_list[i].flags = rte_cpu_to_le_16(flags);
6033 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6035 if (ret != I40E_SUCCESS) {
6036 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6040 } while (num < total);
6047 /* Find out specific MAC filter */
6048 static struct i40e_mac_filter *
6049 i40e_find_mac_filter(struct i40e_vsi *vsi,
6050 struct ether_addr *macaddr)
6052 struct i40e_mac_filter *f;
6054 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6055 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6063 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6066 uint32_t vid_idx, vid_bit;
6068 if (vlan_id > ETH_VLAN_ID_MAX)
6071 vid_idx = I40E_VFTA_IDX(vlan_id);
6072 vid_bit = I40E_VFTA_BIT(vlan_id);
6074 if (vsi->vfta[vid_idx] & vid_bit)
6081 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6082 uint16_t vlan_id, bool on)
6084 uint32_t vid_idx, vid_bit;
6086 vid_idx = I40E_VFTA_IDX(vlan_id);
6087 vid_bit = I40E_VFTA_BIT(vlan_id);
6090 vsi->vfta[vid_idx] |= vid_bit;
6092 vsi->vfta[vid_idx] &= ~vid_bit;
6096 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6097 uint16_t vlan_id, bool on)
6099 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6100 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6103 if (vlan_id > ETH_VLAN_ID_MAX)
6106 i40e_store_vlan_filter(vsi, vlan_id, on);
6108 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6111 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6114 ret = i40e_aq_add_vlan(hw, vsi->seid,
6115 &vlan_data, 1, NULL);
6116 if (ret != I40E_SUCCESS)
6117 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6119 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6120 &vlan_data, 1, NULL);
6121 if (ret != I40E_SUCCESS)
6123 "Failed to remove vlan filter");
6128 * Find all vlan options for specific mac addr,
6129 * return with actual vlan found.
6132 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6133 struct i40e_macvlan_filter *mv_f,
6134 int num, struct ether_addr *addr)
6140 * Not to use i40e_find_vlan_filter to decrease the loop time,
6141 * although the code looks complex.
6143 if (num < vsi->vlan_num)
6144 return I40E_ERR_PARAM;
6147 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6149 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6150 if (vsi->vfta[j] & (1 << k)) {
6153 "vlan number doesn't match");
6154 return I40E_ERR_PARAM;
6156 (void)rte_memcpy(&mv_f[i].macaddr,
6157 addr, ETH_ADDR_LEN);
6159 j * I40E_UINT32_BIT_SIZE + k;
6165 return I40E_SUCCESS;
6169 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6170 struct i40e_macvlan_filter *mv_f,
6175 struct i40e_mac_filter *f;
6177 if (num < vsi->mac_num)
6178 return I40E_ERR_PARAM;
6180 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6182 PMD_DRV_LOG(ERR, "buffer number not match");
6183 return I40E_ERR_PARAM;
6185 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6187 mv_f[i].vlan_id = vlan;
6188 mv_f[i].filter_type = f->mac_info.filter_type;
6192 return I40E_SUCCESS;
6196 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6199 struct i40e_mac_filter *f;
6200 struct i40e_macvlan_filter *mv_f;
6201 int ret = I40E_SUCCESS;
6203 if (vsi == NULL || vsi->mac_num == 0)
6204 return I40E_ERR_PARAM;
6206 /* Case that no vlan is set */
6207 if (vsi->vlan_num == 0)
6210 num = vsi->mac_num * vsi->vlan_num;
6212 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6214 PMD_DRV_LOG(ERR, "failed to allocate memory");
6215 return I40E_ERR_NO_MEMORY;
6219 if (vsi->vlan_num == 0) {
6220 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6221 (void)rte_memcpy(&mv_f[i].macaddr,
6222 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6223 mv_f[i].filter_type = f->mac_info.filter_type;
6224 mv_f[i].vlan_id = 0;
6228 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6229 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6230 vsi->vlan_num, &f->mac_info.mac_addr);
6231 if (ret != I40E_SUCCESS)
6233 for (j = i; j < i + vsi->vlan_num; j++)
6234 mv_f[j].filter_type = f->mac_info.filter_type;
6239 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6247 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6249 struct i40e_macvlan_filter *mv_f;
6251 int ret = I40E_SUCCESS;
6253 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6254 return I40E_ERR_PARAM;
6256 /* If it's already set, just return */
6257 if (i40e_find_vlan_filter(vsi,vlan))
6258 return I40E_SUCCESS;
6260 mac_num = vsi->mac_num;
6263 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6264 return I40E_ERR_PARAM;
6267 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6270 PMD_DRV_LOG(ERR, "failed to allocate memory");
6271 return I40E_ERR_NO_MEMORY;
6274 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6276 if (ret != I40E_SUCCESS)
6279 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6281 if (ret != I40E_SUCCESS)
6284 i40e_set_vlan_filter(vsi, vlan, 1);
6294 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6296 struct i40e_macvlan_filter *mv_f;
6298 int ret = I40E_SUCCESS;
6301 * Vlan 0 is the generic filter for untagged packets
6302 * and can't be removed.
6304 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6305 return I40E_ERR_PARAM;
6307 /* If can't find it, just return */
6308 if (!i40e_find_vlan_filter(vsi, vlan))
6309 return I40E_ERR_PARAM;
6311 mac_num = vsi->mac_num;
6314 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6315 return I40E_ERR_PARAM;
6318 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6321 PMD_DRV_LOG(ERR, "failed to allocate memory");
6322 return I40E_ERR_NO_MEMORY;
6325 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6327 if (ret != I40E_SUCCESS)
6330 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6332 if (ret != I40E_SUCCESS)
6335 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6336 if (vsi->vlan_num == 1) {
6337 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6338 if (ret != I40E_SUCCESS)
6341 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6342 if (ret != I40E_SUCCESS)
6346 i40e_set_vlan_filter(vsi, vlan, 0);
6356 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6358 struct i40e_mac_filter *f;
6359 struct i40e_macvlan_filter *mv_f;
6360 int i, vlan_num = 0;
6361 int ret = I40E_SUCCESS;
6363 /* If it's add and we've config it, return */
6364 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6366 return I40E_SUCCESS;
6367 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6368 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6371 * If vlan_num is 0, that's the first time to add mac,
6372 * set mask for vlan_id 0.
6374 if (vsi->vlan_num == 0) {
6375 i40e_set_vlan_filter(vsi, 0, 1);
6378 vlan_num = vsi->vlan_num;
6379 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6380 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6383 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6385 PMD_DRV_LOG(ERR, "failed to allocate memory");
6386 return I40E_ERR_NO_MEMORY;
6389 for (i = 0; i < vlan_num; i++) {
6390 mv_f[i].filter_type = mac_filter->filter_type;
6391 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6395 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6396 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6397 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6398 &mac_filter->mac_addr);
6399 if (ret != I40E_SUCCESS)
6403 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6404 if (ret != I40E_SUCCESS)
6407 /* Add the mac addr into mac list */
6408 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6410 PMD_DRV_LOG(ERR, "failed to allocate memory");
6411 ret = I40E_ERR_NO_MEMORY;
6414 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6416 f->mac_info.filter_type = mac_filter->filter_type;
6417 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6428 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6430 struct i40e_mac_filter *f;
6431 struct i40e_macvlan_filter *mv_f;
6433 enum rte_mac_filter_type filter_type;
6434 int ret = I40E_SUCCESS;
6436 /* Can't find it, return an error */
6437 f = i40e_find_mac_filter(vsi, addr);
6439 return I40E_ERR_PARAM;
6441 vlan_num = vsi->vlan_num;
6442 filter_type = f->mac_info.filter_type;
6443 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6444 filter_type == RTE_MACVLAN_HASH_MATCH) {
6445 if (vlan_num == 0) {
6446 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6447 return I40E_ERR_PARAM;
6449 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6450 filter_type == RTE_MAC_HASH_MATCH)
6453 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6455 PMD_DRV_LOG(ERR, "failed to allocate memory");
6456 return I40E_ERR_NO_MEMORY;
6459 for (i = 0; i < vlan_num; i++) {
6460 mv_f[i].filter_type = filter_type;
6461 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6464 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6465 filter_type == RTE_MACVLAN_HASH_MATCH) {
6466 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6467 if (ret != I40E_SUCCESS)
6471 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6472 if (ret != I40E_SUCCESS)
6475 /* Remove the mac addr into mac list */
6476 TAILQ_REMOVE(&vsi->mac_list, f, next);
6486 /* Configure hash enable flags for RSS */
6488 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6495 if (flags & ETH_RSS_FRAG_IPV4)
6496 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6497 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6498 if (type == I40E_MAC_X722) {
6499 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6500 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6502 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6504 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6505 if (type == I40E_MAC_X722) {
6506 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6507 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6508 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6510 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6512 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6513 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6514 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6515 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6516 if (flags & ETH_RSS_FRAG_IPV6)
6517 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6518 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6519 if (type == I40E_MAC_X722) {
6520 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6521 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6523 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6525 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6526 if (type == I40E_MAC_X722) {
6527 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6528 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6529 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6531 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6533 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6534 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6535 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6536 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6537 if (flags & ETH_RSS_L2_PAYLOAD)
6538 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6543 /* Parse the hash enable flags */
6545 i40e_parse_hena(uint64_t flags)
6547 uint64_t rss_hf = 0;
6551 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6552 rss_hf |= ETH_RSS_FRAG_IPV4;
6553 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6554 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6555 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6556 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6557 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6558 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6559 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6560 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6561 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6562 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6563 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6564 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6565 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6566 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6567 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6568 rss_hf |= ETH_RSS_FRAG_IPV6;
6569 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6570 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6571 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6572 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6573 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6574 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6575 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6576 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6577 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6578 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6579 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6580 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6581 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6582 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6583 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6584 rss_hf |= ETH_RSS_L2_PAYLOAD;
6591 i40e_pf_disable_rss(struct i40e_pf *pf)
6593 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6596 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6597 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6598 if (hw->mac.type == I40E_MAC_X722)
6599 hena &= ~I40E_RSS_HENA_ALL_X722;
6601 hena &= ~I40E_RSS_HENA_ALL;
6602 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6603 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6604 I40E_WRITE_FLUSH(hw);
6608 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6610 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6611 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6614 if (!key || key_len == 0) {
6615 PMD_DRV_LOG(DEBUG, "No key to be configured");
6617 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6619 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6623 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6624 struct i40e_aqc_get_set_rss_key_data *key_dw =
6625 (struct i40e_aqc_get_set_rss_key_data *)key;
6627 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6629 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6631 uint32_t *hash_key = (uint32_t *)key;
6634 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6635 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6636 I40E_WRITE_FLUSH(hw);
6643 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6645 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6646 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6649 if (!key || !key_len)
6652 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6653 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6654 (struct i40e_aqc_get_set_rss_key_data *)key);
6656 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6660 uint32_t *key_dw = (uint32_t *)key;
6663 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6664 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6666 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6672 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6674 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6679 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6680 rss_conf->rss_key_len);
6684 rss_hf = rss_conf->rss_hf;
6685 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6686 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6687 if (hw->mac.type == I40E_MAC_X722)
6688 hena &= ~I40E_RSS_HENA_ALL_X722;
6690 hena &= ~I40E_RSS_HENA_ALL;
6691 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6692 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6693 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6694 I40E_WRITE_FLUSH(hw);
6700 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6701 struct rte_eth_rss_conf *rss_conf)
6703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6704 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6705 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6708 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6709 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6710 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6711 ? I40E_RSS_HENA_ALL_X722
6712 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6713 if (rss_hf != 0) /* Enable RSS */
6715 return 0; /* Nothing to do */
6718 if (rss_hf == 0) /* Disable RSS */
6721 return i40e_hw_rss_hash_set(pf, rss_conf);
6725 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6726 struct rte_eth_rss_conf *rss_conf)
6728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6729 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6732 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6733 &rss_conf->rss_key_len);
6735 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6736 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6737 rss_conf->rss_hf = i40e_parse_hena(hena);
6743 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6745 switch (filter_type) {
6746 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6747 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6749 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6750 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6752 case RTE_TUNNEL_FILTER_IMAC_TENID:
6753 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6755 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6756 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6758 case ETH_TUNNEL_FILTER_IMAC:
6759 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6761 case ETH_TUNNEL_FILTER_OIP:
6762 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6764 case ETH_TUNNEL_FILTER_IIP:
6765 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6768 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6775 /* Convert tunnel filter structure */
6777 i40e_tunnel_filter_convert(
6778 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6779 struct i40e_tunnel_filter *tunnel_filter)
6781 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6782 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6783 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6784 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6785 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6786 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6787 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6788 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6789 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6791 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6792 tunnel_filter->input.flags = cld_filter->element.flags;
6793 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6794 tunnel_filter->queue = cld_filter->element.queue_number;
6795 rte_memcpy(tunnel_filter->input.general_fields,
6796 cld_filter->general_fields,
6797 sizeof(cld_filter->general_fields));
6802 /* Check if there exists the tunnel filter */
6803 struct i40e_tunnel_filter *
6804 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6805 const struct i40e_tunnel_filter_input *input)
6809 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6813 return tunnel_rule->hash_map[ret];
6816 /* Add a tunnel filter into the SW list */
6818 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6819 struct i40e_tunnel_filter *tunnel_filter)
6821 struct i40e_tunnel_rule *rule = &pf->tunnel;
6824 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6827 "Failed to insert tunnel filter to hash table %d!",
6831 rule->hash_map[ret] = tunnel_filter;
6833 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6838 /* Delete a tunnel filter from the SW list */
6840 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6841 struct i40e_tunnel_filter_input *input)
6843 struct i40e_tunnel_rule *rule = &pf->tunnel;
6844 struct i40e_tunnel_filter *tunnel_filter;
6847 ret = rte_hash_del_key(rule->hash_table, input);
6850 "Failed to delete tunnel filter to hash table %d!",
6854 tunnel_filter = rule->hash_map[ret];
6855 rule->hash_map[ret] = NULL;
6857 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6858 rte_free(tunnel_filter);
6864 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6865 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6870 uint8_t i, tun_type = 0;
6871 /* internal varialbe to convert ipv6 byte order */
6872 uint32_t convert_ipv6[4];
6874 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6875 struct i40e_vsi *vsi = pf->main_vsi;
6876 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6877 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6878 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6879 struct i40e_tunnel_filter *tunnel, *node;
6880 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6882 cld_filter = rte_zmalloc("tunnel_filter",
6883 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6886 if (NULL == cld_filter) {
6887 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6890 pfilter = cld_filter;
6892 ether_addr_copy(&tunnel_filter->outer_mac,
6893 (struct ether_addr *)&pfilter->element.outer_mac);
6894 ether_addr_copy(&tunnel_filter->inner_mac,
6895 (struct ether_addr *)&pfilter->element.inner_mac);
6897 pfilter->element.inner_vlan =
6898 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6899 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6900 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6901 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6902 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6903 &rte_cpu_to_le_32(ipv4_addr),
6904 sizeof(pfilter->element.ipaddr.v4.data));
6906 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6907 for (i = 0; i < 4; i++) {
6909 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6911 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6913 sizeof(pfilter->element.ipaddr.v6.data));
6916 /* check tunneled type */
6917 switch (tunnel_filter->tunnel_type) {
6918 case RTE_TUNNEL_TYPE_VXLAN:
6919 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6921 case RTE_TUNNEL_TYPE_NVGRE:
6922 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6924 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6925 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6928 /* Other tunnel types is not supported. */
6929 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6930 rte_free(cld_filter);
6934 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6935 &pfilter->element.flags);
6937 rte_free(cld_filter);
6941 pfilter->element.flags |= rte_cpu_to_le_16(
6942 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6943 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6944 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6945 pfilter->element.queue_number =
6946 rte_cpu_to_le_16(tunnel_filter->queue_id);
6948 /* Check if there is the filter in SW list */
6949 memset(&check_filter, 0, sizeof(check_filter));
6950 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6951 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6953 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6957 if (!add && !node) {
6958 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6963 ret = i40e_aq_add_cloud_filters(hw,
6964 vsi->seid, &cld_filter->element, 1);
6966 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6969 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6970 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6971 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6973 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6974 &cld_filter->element, 1);
6976 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6979 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6982 rte_free(cld_filter);
6986 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6987 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6988 #define I40E_TR_GENEVE_KEY_MASK 0x8
6989 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6990 #define I40E_TR_GRE_KEY_MASK 0x400
6991 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6992 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6995 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6997 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6998 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6999 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7000 enum i40e_status_code status = I40E_SUCCESS;
7002 memset(&filter_replace, 0,
7003 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7004 memset(&filter_replace_buf, 0,
7005 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7007 /* create L1 filter */
7008 filter_replace.old_filter_type =
7009 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7010 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7011 filter_replace.tr_bit = 0;
7013 /* Prepare the buffer, 3 entries */
7014 filter_replace_buf.data[0] =
7015 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7016 filter_replace_buf.data[0] |=
7017 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7018 filter_replace_buf.data[2] = 0xFF;
7019 filter_replace_buf.data[3] = 0xFF;
7020 filter_replace_buf.data[4] =
7021 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7022 filter_replace_buf.data[4] |=
7023 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7024 filter_replace_buf.data[7] = 0xF0;
7025 filter_replace_buf.data[8]
7026 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7027 filter_replace_buf.data[8] |=
7028 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7029 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7030 I40E_TR_GENEVE_KEY_MASK |
7031 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7032 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7033 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7034 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7036 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7037 &filter_replace_buf);
7042 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7044 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7045 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7046 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7047 enum i40e_status_code status = I40E_SUCCESS;
7050 memset(&filter_replace, 0,
7051 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7052 memset(&filter_replace_buf, 0,
7053 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7054 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7055 I40E_AQC_MIRROR_CLOUD_FILTER;
7056 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7057 filter_replace.new_filter_type =
7058 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7059 /* Prepare the buffer, 2 entries */
7060 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7061 filter_replace_buf.data[0] |=
7062 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7063 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7064 filter_replace_buf.data[4] |=
7065 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7066 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7067 &filter_replace_buf);
7072 memset(&filter_replace, 0,
7073 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7074 memset(&filter_replace_buf, 0,
7075 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7077 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7078 I40E_AQC_MIRROR_CLOUD_FILTER;
7079 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7080 filter_replace.new_filter_type =
7081 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7082 /* Prepare the buffer, 2 entries */
7083 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7084 filter_replace_buf.data[0] |=
7085 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7086 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7087 filter_replace_buf.data[4] |=
7088 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7090 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7091 &filter_replace_buf);
7096 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7097 struct i40e_tunnel_filter_conf *tunnel_filter,
7102 uint8_t i, tun_type = 0;
7103 /* internal variable to convert ipv6 byte order */
7104 uint32_t convert_ipv6[4];
7106 struct i40e_pf_vf *vf = NULL;
7107 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7108 struct i40e_vsi *vsi;
7109 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7110 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7111 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7112 struct i40e_tunnel_filter *tunnel, *node;
7113 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7115 bool big_buffer = 0;
7117 cld_filter = rte_zmalloc("tunnel_filter",
7118 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7121 if (cld_filter == NULL) {
7122 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7125 pfilter = cld_filter;
7127 ether_addr_copy(&tunnel_filter->outer_mac,
7128 (struct ether_addr *)&pfilter->element.outer_mac);
7129 ether_addr_copy(&tunnel_filter->inner_mac,
7130 (struct ether_addr *)&pfilter->element.inner_mac);
7132 pfilter->element.inner_vlan =
7133 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7134 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7135 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7136 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7137 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7138 &rte_cpu_to_le_32(ipv4_addr),
7139 sizeof(pfilter->element.ipaddr.v4.data));
7141 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7142 for (i = 0; i < 4; i++) {
7144 rte_cpu_to_le_32(rte_be_to_cpu_32(
7145 tunnel_filter->ip_addr.ipv6_addr[i]));
7147 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7149 sizeof(pfilter->element.ipaddr.v6.data));
7152 /* check tunneled type */
7153 switch (tunnel_filter->tunnel_type) {
7154 case I40E_TUNNEL_TYPE_VXLAN:
7155 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7157 case I40E_TUNNEL_TYPE_NVGRE:
7158 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7160 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7161 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7163 case I40E_TUNNEL_TYPE_MPLSoUDP:
7164 if (!pf->mpls_replace_flag) {
7165 i40e_replace_mpls_l1_filter(pf);
7166 i40e_replace_mpls_cloud_filter(pf);
7167 pf->mpls_replace_flag = 1;
7169 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7170 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7172 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7173 (teid_le & 0xF) << 12;
7174 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7177 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7179 case I40E_TUNNEL_TYPE_MPLSoGRE:
7180 if (!pf->mpls_replace_flag) {
7181 i40e_replace_mpls_l1_filter(pf);
7182 i40e_replace_mpls_cloud_filter(pf);
7183 pf->mpls_replace_flag = 1;
7185 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7186 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7188 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7189 (teid_le & 0xF) << 12;
7190 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7193 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7195 case I40E_TUNNEL_TYPE_QINQ:
7196 if (!pf->qinq_replace_flag) {
7197 ret = i40e_cloud_filter_qinq_create(pf);
7200 "QinQ tunnel filter already created.");
7201 pf->qinq_replace_flag = 1;
7203 /* Add in the General fields the values of
7204 * the Outer and Inner VLAN
7205 * Big Buffer should be set, see changes in
7206 * i40e_aq_add_cloud_filters
7208 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7209 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7213 /* Other tunnel types is not supported. */
7214 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7215 rte_free(cld_filter);
7219 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7220 pfilter->element.flags =
7221 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7222 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7223 pfilter->element.flags =
7224 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7225 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7226 pfilter->element.flags |=
7227 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7229 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7230 &pfilter->element.flags);
7232 rte_free(cld_filter);
7237 pfilter->element.flags |= rte_cpu_to_le_16(
7238 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7239 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7240 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7241 pfilter->element.queue_number =
7242 rte_cpu_to_le_16(tunnel_filter->queue_id);
7244 if (!tunnel_filter->is_to_vf)
7247 if (tunnel_filter->vf_id >= pf->vf_num) {
7248 PMD_DRV_LOG(ERR, "Invalid argument.");
7251 vf = &pf->vfs[tunnel_filter->vf_id];
7255 /* Check if there is the filter in SW list */
7256 memset(&check_filter, 0, sizeof(check_filter));
7257 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7258 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7259 check_filter.vf_id = tunnel_filter->vf_id;
7260 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7262 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7266 if (!add && !node) {
7267 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7273 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7274 vsi->seid, cld_filter, 1);
7276 ret = i40e_aq_add_cloud_filters(hw,
7277 vsi->seid, &cld_filter->element, 1);
7279 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7282 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7283 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7284 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7287 ret = i40e_aq_remove_cloud_filters_big_buffer(
7288 hw, vsi->seid, cld_filter, 1);
7290 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7291 &cld_filter->element, 1);
7293 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7296 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7299 rte_free(cld_filter);
7304 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7308 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7309 if (pf->vxlan_ports[i] == port)
7317 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7321 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7323 idx = i40e_get_vxlan_port_idx(pf, port);
7325 /* Check if port already exists */
7327 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7331 /* Now check if there is space to add the new port */
7332 idx = i40e_get_vxlan_port_idx(pf, 0);
7335 "Maximum number of UDP ports reached, not adding port %d",
7340 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7343 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7347 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7350 /* New port: add it and mark its index in the bitmap */
7351 pf->vxlan_ports[idx] = port;
7352 pf->vxlan_bitmap |= (1 << idx);
7354 if (!(pf->flags & I40E_FLAG_VXLAN))
7355 pf->flags |= I40E_FLAG_VXLAN;
7361 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7364 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7366 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7367 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7371 idx = i40e_get_vxlan_port_idx(pf, port);
7374 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7378 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7379 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7383 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7386 pf->vxlan_ports[idx] = 0;
7387 pf->vxlan_bitmap &= ~(1 << idx);
7389 if (!pf->vxlan_bitmap)
7390 pf->flags &= ~I40E_FLAG_VXLAN;
7395 /* Add UDP tunneling port */
7397 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7398 struct rte_eth_udp_tunnel *udp_tunnel)
7401 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7403 if (udp_tunnel == NULL)
7406 switch (udp_tunnel->prot_type) {
7407 case RTE_TUNNEL_TYPE_VXLAN:
7408 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7411 case RTE_TUNNEL_TYPE_GENEVE:
7412 case RTE_TUNNEL_TYPE_TEREDO:
7413 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7418 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7426 /* Remove UDP tunneling port */
7428 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7429 struct rte_eth_udp_tunnel *udp_tunnel)
7432 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7434 if (udp_tunnel == NULL)
7437 switch (udp_tunnel->prot_type) {
7438 case RTE_TUNNEL_TYPE_VXLAN:
7439 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7441 case RTE_TUNNEL_TYPE_GENEVE:
7442 case RTE_TUNNEL_TYPE_TEREDO:
7443 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7447 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7455 /* Calculate the maximum number of contiguous PF queues that are configured */
7457 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7459 struct rte_eth_dev_data *data = pf->dev_data;
7461 struct i40e_rx_queue *rxq;
7464 for (i = 0; i < pf->lan_nb_qps; i++) {
7465 rxq = data->rx_queues[i];
7466 if (rxq && rxq->q_set)
7477 i40e_pf_config_rss(struct i40e_pf *pf)
7479 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7480 struct rte_eth_rss_conf rss_conf;
7481 uint32_t i, lut = 0;
7485 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7486 * It's necessary to calculate the actual PF queues that are configured.
7488 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7489 num = i40e_pf_calc_configured_queues_num(pf);
7491 num = pf->dev_data->nb_rx_queues;
7493 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7494 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7498 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7502 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7505 lut = (lut << 8) | (j & ((0x1 <<
7506 hw->func_caps.rss_table_entry_width) - 1));
7508 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7511 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7512 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7513 i40e_pf_disable_rss(pf);
7516 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7517 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7518 /* Random default keys */
7519 static uint32_t rss_key_default[] = {0x6b793944,
7520 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7521 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7522 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7524 rss_conf.rss_key = (uint8_t *)rss_key_default;
7525 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7529 return i40e_hw_rss_hash_set(pf, &rss_conf);
7533 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7534 struct rte_eth_tunnel_filter_conf *filter)
7536 if (pf == NULL || filter == NULL) {
7537 PMD_DRV_LOG(ERR, "Invalid parameter");
7541 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7542 PMD_DRV_LOG(ERR, "Invalid queue ID");
7546 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7547 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7551 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7552 (is_zero_ether_addr(&filter->outer_mac))) {
7553 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7557 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7558 (is_zero_ether_addr(&filter->inner_mac))) {
7559 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7566 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7567 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7569 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7574 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7575 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7578 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7579 } else if (len == 4) {
7580 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7582 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7587 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7594 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7595 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7601 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7608 switch (cfg->cfg_type) {
7609 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7610 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7613 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7621 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7622 enum rte_filter_op filter_op,
7625 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7626 int ret = I40E_ERR_PARAM;
7628 switch (filter_op) {
7629 case RTE_ETH_FILTER_SET:
7630 ret = i40e_dev_global_config_set(hw,
7631 (struct rte_eth_global_cfg *)arg);
7634 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7642 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7643 enum rte_filter_op filter_op,
7646 struct rte_eth_tunnel_filter_conf *filter;
7647 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7648 int ret = I40E_SUCCESS;
7650 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7652 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7653 return I40E_ERR_PARAM;
7655 switch (filter_op) {
7656 case RTE_ETH_FILTER_NOP:
7657 if (!(pf->flags & I40E_FLAG_VXLAN))
7658 ret = I40E_NOT_SUPPORTED;
7660 case RTE_ETH_FILTER_ADD:
7661 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7663 case RTE_ETH_FILTER_DELETE:
7664 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7667 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7668 ret = I40E_ERR_PARAM;
7676 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7679 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7682 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7683 ret = i40e_pf_config_rss(pf);
7685 i40e_pf_disable_rss(pf);
7690 /* Get the symmetric hash enable configurations per port */
7692 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7694 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7696 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7699 /* Set the symmetric hash enable configurations per port */
7701 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7703 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7706 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7708 "Symmetric hash has already been enabled");
7711 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7713 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7715 "Symmetric hash has already been disabled");
7718 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7720 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7721 I40E_WRITE_FLUSH(hw);
7725 * Get global configurations of hash function type and symmetric hash enable
7726 * per flow type (pctype). Note that global configuration means it affects all
7727 * the ports on the same NIC.
7730 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7731 struct rte_eth_hash_global_conf *g_cfg)
7733 uint32_t reg, mask = I40E_FLOW_TYPES;
7735 enum i40e_filter_pctype pctype;
7737 memset(g_cfg, 0, sizeof(*g_cfg));
7738 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7739 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7740 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7742 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7743 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7744 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7746 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7747 if (!(mask & (1UL << i)))
7749 mask &= ~(1UL << i);
7750 /* Bit set indicats the coresponding flow type is supported */
7751 g_cfg->valid_bit_mask[0] |= (1UL << i);
7752 /* if flowtype is invalid, continue */
7753 if (!I40E_VALID_FLOW(i))
7755 pctype = i40e_flowtype_to_pctype(i);
7756 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7757 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7758 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7765 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7768 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7770 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7771 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7772 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7773 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7779 * As i40e supports less than 32 flow types, only first 32 bits need to
7782 mask0 = g_cfg->valid_bit_mask[0];
7783 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7785 /* Check if any unsupported flow type configured */
7786 if ((mask0 | i40e_mask) ^ i40e_mask)
7789 if (g_cfg->valid_bit_mask[i])
7797 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7803 * Set global configurations of hash function type and symmetric hash enable
7804 * per flow type (pctype). Note any modifying global configuration will affect
7805 * all the ports on the same NIC.
7808 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7809 struct rte_eth_hash_global_conf *g_cfg)
7814 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7815 enum i40e_filter_pctype pctype;
7817 /* Check the input parameters */
7818 ret = i40e_hash_global_config_check(g_cfg);
7822 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7823 if (!(mask0 & (1UL << i)))
7825 mask0 &= ~(1UL << i);
7826 /* if flowtype is invalid, continue */
7827 if (!I40E_VALID_FLOW(i))
7829 pctype = i40e_flowtype_to_pctype(i);
7830 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7831 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7832 if (hw->mac.type == I40E_MAC_X722) {
7833 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7834 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7835 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7836 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7837 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7839 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7840 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7842 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7843 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7844 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7845 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7846 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7848 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7849 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7850 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7851 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7852 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7854 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7855 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7857 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7858 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7859 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7860 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7861 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7864 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7868 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7872 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7873 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7875 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7877 "Hash function already set to Toeplitz");
7880 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7881 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7883 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7885 "Hash function already set to Simple XOR");
7888 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7890 /* Use the default, and keep it as it is */
7893 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7896 I40E_WRITE_FLUSH(hw);
7902 * Valid input sets for hash and flow director filters per PCTYPE
7905 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7906 enum rte_filter_type filter)
7910 static const uint64_t valid_hash_inset_table[] = {
7911 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7912 I40E_INSET_DMAC | I40E_INSET_SMAC |
7913 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7914 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7915 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7916 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7917 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7918 I40E_INSET_FLEX_PAYLOAD,
7919 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7920 I40E_INSET_DMAC | I40E_INSET_SMAC |
7921 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7922 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7923 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7924 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7925 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7926 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7927 I40E_INSET_FLEX_PAYLOAD,
7928 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7929 I40E_INSET_DMAC | I40E_INSET_SMAC |
7930 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7931 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7932 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7933 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7934 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7935 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7936 I40E_INSET_FLEX_PAYLOAD,
7937 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7938 I40E_INSET_DMAC | I40E_INSET_SMAC |
7939 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7940 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7941 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7942 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7943 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7944 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7945 I40E_INSET_FLEX_PAYLOAD,
7946 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7947 I40E_INSET_DMAC | I40E_INSET_SMAC |
7948 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7949 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7950 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7951 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7952 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7953 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7954 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7955 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7956 I40E_INSET_DMAC | I40E_INSET_SMAC |
7957 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7958 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7959 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7960 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7961 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7962 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7963 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7964 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7965 I40E_INSET_DMAC | I40E_INSET_SMAC |
7966 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7967 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7968 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7969 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7970 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7971 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7972 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7973 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7974 I40E_INSET_DMAC | I40E_INSET_SMAC |
7975 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7976 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7977 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7978 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7979 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7980 I40E_INSET_FLEX_PAYLOAD,
7981 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7982 I40E_INSET_DMAC | I40E_INSET_SMAC |
7983 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7984 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7985 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7986 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7987 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7988 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7989 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7990 I40E_INSET_DMAC | I40E_INSET_SMAC |
7991 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7992 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7993 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7994 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7995 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7996 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7997 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7998 I40E_INSET_DMAC | I40E_INSET_SMAC |
7999 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8000 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8001 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8002 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8003 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8004 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8005 I40E_INSET_FLEX_PAYLOAD,
8006 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8007 I40E_INSET_DMAC | I40E_INSET_SMAC |
8008 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8009 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8010 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8011 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8012 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8013 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8014 I40E_INSET_FLEX_PAYLOAD,
8015 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8016 I40E_INSET_DMAC | I40E_INSET_SMAC |
8017 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8018 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8019 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8020 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8021 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8022 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8023 I40E_INSET_FLEX_PAYLOAD,
8024 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8025 I40E_INSET_DMAC | I40E_INSET_SMAC |
8026 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8027 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8028 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8029 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8030 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8031 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8032 I40E_INSET_FLEX_PAYLOAD,
8033 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8034 I40E_INSET_DMAC | I40E_INSET_SMAC |
8035 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8036 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8037 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8038 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8039 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8040 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8041 I40E_INSET_FLEX_PAYLOAD,
8042 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8043 I40E_INSET_DMAC | I40E_INSET_SMAC |
8044 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8045 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8046 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8047 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8048 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8049 I40E_INSET_FLEX_PAYLOAD,
8050 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8051 I40E_INSET_DMAC | I40E_INSET_SMAC |
8052 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8053 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8054 I40E_INSET_FLEX_PAYLOAD,
8058 * Flow director supports only fields defined in
8059 * union rte_eth_fdir_flow.
8061 static const uint64_t valid_fdir_inset_table[] = {
8062 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8063 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8064 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8065 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8066 I40E_INSET_IPV4_TTL,
8067 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8069 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8070 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8071 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8072 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8073 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8074 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8075 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8076 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8077 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8078 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8079 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8080 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8081 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8082 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8083 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8084 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8085 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8086 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8087 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8088 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8089 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8090 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8091 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8092 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8093 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8094 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8095 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8096 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8098 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8099 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8100 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8101 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8102 I40E_INSET_IPV4_TTL,
8103 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8104 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8105 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8106 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8107 I40E_INSET_IPV6_HOP_LIMIT,
8108 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8109 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8110 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8111 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8112 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8113 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8114 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8115 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8116 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8117 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8118 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8119 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8120 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8121 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8122 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8123 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8124 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8125 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8126 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8127 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8128 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8129 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8130 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8131 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8132 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8133 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8134 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8135 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8136 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8137 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8139 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8140 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8141 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8142 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8143 I40E_INSET_IPV6_HOP_LIMIT,
8144 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8145 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8146 I40E_INSET_LAST_ETHER_TYPE,
8149 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8151 if (filter == RTE_ETH_FILTER_HASH)
8152 valid = valid_hash_inset_table[pctype];
8154 valid = valid_fdir_inset_table[pctype];
8160 * Validate if the input set is allowed for a specific PCTYPE
8163 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8164 enum rte_filter_type filter, uint64_t inset)
8168 valid = i40e_get_valid_input_set(pctype, filter);
8169 if (inset & (~valid))
8175 /* default input set fields combination per pctype */
8177 i40e_get_default_input_set(uint16_t pctype)
8179 static const uint64_t default_inset_table[] = {
8180 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8181 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8182 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8183 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8184 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8185 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8186 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8187 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8188 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8189 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8190 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8191 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8192 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8193 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8194 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8195 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8196 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8197 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8198 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8199 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8201 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8202 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8203 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8204 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8205 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8206 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8207 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8208 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8209 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8210 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8211 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8212 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8213 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8214 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8215 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8216 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8217 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8218 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8219 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8220 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8221 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8222 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8224 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8225 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8226 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8227 I40E_INSET_LAST_ETHER_TYPE,
8230 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8233 return default_inset_table[pctype];
8237 * Parse the input set from index to logical bit masks
8240 i40e_parse_input_set(uint64_t *inset,
8241 enum i40e_filter_pctype pctype,
8242 enum rte_eth_input_set_field *field,
8248 static const struct {
8249 enum rte_eth_input_set_field field;
8251 } inset_convert_table[] = {
8252 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8253 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8254 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8255 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8256 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8257 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8258 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8259 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8260 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8261 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8262 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8263 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8264 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8265 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8266 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8267 I40E_INSET_IPV6_NEXT_HDR},
8268 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8269 I40E_INSET_IPV6_HOP_LIMIT},
8270 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8271 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8272 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8273 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8274 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8275 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8276 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8277 I40E_INSET_SCTP_VT},
8278 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8279 I40E_INSET_TUNNEL_DMAC},
8280 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8281 I40E_INSET_VLAN_TUNNEL},
8282 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8283 I40E_INSET_TUNNEL_ID},
8284 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8285 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8286 I40E_INSET_FLEX_PAYLOAD_W1},
8287 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8288 I40E_INSET_FLEX_PAYLOAD_W2},
8289 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8290 I40E_INSET_FLEX_PAYLOAD_W3},
8291 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8292 I40E_INSET_FLEX_PAYLOAD_W4},
8293 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8294 I40E_INSET_FLEX_PAYLOAD_W5},
8295 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8296 I40E_INSET_FLEX_PAYLOAD_W6},
8297 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8298 I40E_INSET_FLEX_PAYLOAD_W7},
8299 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8300 I40E_INSET_FLEX_PAYLOAD_W8},
8303 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8306 /* Only one item allowed for default or all */
8308 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8309 *inset = i40e_get_default_input_set(pctype);
8311 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8312 *inset = I40E_INSET_NONE;
8317 for (i = 0, *inset = 0; i < size; i++) {
8318 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8319 if (field[i] == inset_convert_table[j].field) {
8320 *inset |= inset_convert_table[j].inset;
8325 /* It contains unsupported input set, return immediately */
8326 if (j == RTE_DIM(inset_convert_table))
8334 * Translate the input set from bit masks to register aware bit masks
8338 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8348 static const struct inset_map inset_map_common[] = {
8349 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8350 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8351 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8352 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8353 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8354 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8355 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8356 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8357 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8358 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8359 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8360 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8361 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8362 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8363 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8364 {I40E_INSET_TUNNEL_DMAC,
8365 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8366 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8367 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8368 {I40E_INSET_TUNNEL_SRC_PORT,
8369 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8370 {I40E_INSET_TUNNEL_DST_PORT,
8371 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8372 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8373 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8374 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8375 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8376 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8377 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8378 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8379 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8380 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8383 /* some different registers map in x722*/
8384 static const struct inset_map inset_map_diff_x722[] = {
8385 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8386 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8387 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8388 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8391 static const struct inset_map inset_map_diff_not_x722[] = {
8392 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8393 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8394 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8395 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8401 /* Translate input set to register aware inset */
8402 if (type == I40E_MAC_X722) {
8403 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8404 if (input & inset_map_diff_x722[i].inset)
8405 val |= inset_map_diff_x722[i].inset_reg;
8408 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8409 if (input & inset_map_diff_not_x722[i].inset)
8410 val |= inset_map_diff_not_x722[i].inset_reg;
8414 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8415 if (input & inset_map_common[i].inset)
8416 val |= inset_map_common[i].inset_reg;
8423 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8426 uint64_t inset_need_mask = inset;
8428 static const struct {
8431 } inset_mask_map[] = {
8432 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8433 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8434 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8435 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8436 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8437 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8438 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8439 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8442 if (!inset || !mask || !nb_elem)
8445 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8446 /* Clear the inset bit, if no MASK is required,
8447 * for example proto + ttl
8449 if ((inset & inset_mask_map[i].inset) ==
8450 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8451 inset_need_mask &= ~inset_mask_map[i].inset;
8452 if (!inset_need_mask)
8455 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8456 if ((inset_need_mask & inset_mask_map[i].inset) ==
8457 inset_mask_map[i].inset) {
8458 if (idx >= nb_elem) {
8459 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8462 mask[idx] = inset_mask_map[i].mask;
8471 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8473 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8475 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8477 i40e_write_rx_ctl(hw, addr, val);
8478 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8479 (uint32_t)i40e_read_rx_ctl(hw, addr));
8483 i40e_filter_input_set_init(struct i40e_pf *pf)
8485 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8486 enum i40e_filter_pctype pctype;
8487 uint64_t input_set, inset_reg;
8488 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8491 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8492 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8493 if (hw->mac.type == I40E_MAC_X722) {
8494 if (!I40E_VALID_PCTYPE_X722(pctype))
8497 if (!I40E_VALID_PCTYPE(pctype))
8501 input_set = i40e_get_default_input_set(pctype);
8503 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8504 I40E_INSET_MASK_NUM_REG);
8507 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8510 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8511 (uint32_t)(inset_reg & UINT32_MAX));
8512 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8513 (uint32_t)((inset_reg >>
8514 I40E_32_BIT_WIDTH) & UINT32_MAX));
8515 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8516 (uint32_t)(inset_reg & UINT32_MAX));
8517 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8518 (uint32_t)((inset_reg >>
8519 I40E_32_BIT_WIDTH) & UINT32_MAX));
8521 for (i = 0; i < num; i++) {
8522 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8524 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8527 /*clear unused mask registers of the pctype */
8528 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8529 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8531 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8534 I40E_WRITE_FLUSH(hw);
8536 /* store the default input set */
8537 pf->hash_input_set[pctype] = input_set;
8538 pf->fdir.input_set[pctype] = input_set;
8543 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8544 struct rte_eth_input_set_conf *conf)
8546 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8547 enum i40e_filter_pctype pctype;
8548 uint64_t input_set, inset_reg = 0;
8549 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8553 PMD_DRV_LOG(ERR, "Invalid pointer");
8556 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8557 conf->op != RTE_ETH_INPUT_SET_ADD) {
8558 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8562 if (!I40E_VALID_FLOW(conf->flow_type)) {
8563 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8567 if (hw->mac.type == I40E_MAC_X722) {
8568 /* get translated pctype value in fd pctype register */
8569 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8570 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8573 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8575 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8578 PMD_DRV_LOG(ERR, "Failed to parse input set");
8581 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8583 PMD_DRV_LOG(ERR, "Invalid input set");
8586 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8587 /* get inset value in register */
8588 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8589 inset_reg <<= I40E_32_BIT_WIDTH;
8590 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8591 input_set |= pf->hash_input_set[pctype];
8593 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8594 I40E_INSET_MASK_NUM_REG);
8598 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8600 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8601 (uint32_t)(inset_reg & UINT32_MAX));
8602 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8603 (uint32_t)((inset_reg >>
8604 I40E_32_BIT_WIDTH) & UINT32_MAX));
8606 for (i = 0; i < num; i++)
8607 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8609 /*clear unused mask registers of the pctype */
8610 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8611 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8613 I40E_WRITE_FLUSH(hw);
8615 pf->hash_input_set[pctype] = input_set;
8620 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8621 struct rte_eth_input_set_conf *conf)
8623 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8624 enum i40e_filter_pctype pctype;
8625 uint64_t input_set, inset_reg = 0;
8626 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8630 PMD_DRV_LOG(ERR, "Invalid pointer");
8633 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8634 conf->op != RTE_ETH_INPUT_SET_ADD) {
8635 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8639 if (!I40E_VALID_FLOW(conf->flow_type)) {
8640 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8644 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8646 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8649 PMD_DRV_LOG(ERR, "Failed to parse input set");
8652 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8654 PMD_DRV_LOG(ERR, "Invalid input set");
8658 /* get inset value in register */
8659 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8660 inset_reg <<= I40E_32_BIT_WIDTH;
8661 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8663 /* Can not change the inset reg for flex payload for fdir,
8664 * it is done by writing I40E_PRTQF_FD_FLXINSET
8665 * in i40e_set_flex_mask_on_pctype.
8667 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8668 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8670 input_set |= pf->fdir.input_set[pctype];
8671 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8672 I40E_INSET_MASK_NUM_REG);
8676 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8678 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8679 (uint32_t)(inset_reg & UINT32_MAX));
8680 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8681 (uint32_t)((inset_reg >>
8682 I40E_32_BIT_WIDTH) & UINT32_MAX));
8684 for (i = 0; i < num; i++)
8685 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8687 /*clear unused mask registers of the pctype */
8688 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8689 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8691 I40E_WRITE_FLUSH(hw);
8693 pf->fdir.input_set[pctype] = input_set;
8698 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8703 PMD_DRV_LOG(ERR, "Invalid pointer");
8707 switch (info->info_type) {
8708 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8709 i40e_get_symmetric_hash_enable_per_port(hw,
8710 &(info->info.enable));
8712 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8713 ret = i40e_get_hash_filter_global_config(hw,
8714 &(info->info.global_conf));
8717 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8727 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8732 PMD_DRV_LOG(ERR, "Invalid pointer");
8736 switch (info->info_type) {
8737 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8738 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8740 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8741 ret = i40e_set_hash_filter_global_config(hw,
8742 &(info->info.global_conf));
8744 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8745 ret = i40e_hash_filter_inset_select(hw,
8746 &(info->info.input_set_conf));
8750 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8759 /* Operations for hash function */
8761 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8762 enum rte_filter_op filter_op,
8765 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8768 switch (filter_op) {
8769 case RTE_ETH_FILTER_NOP:
8771 case RTE_ETH_FILTER_GET:
8772 ret = i40e_hash_filter_get(hw,
8773 (struct rte_eth_hash_filter_info *)arg);
8775 case RTE_ETH_FILTER_SET:
8776 ret = i40e_hash_filter_set(hw,
8777 (struct rte_eth_hash_filter_info *)arg);
8780 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8789 /* Convert ethertype filter structure */
8791 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8792 struct i40e_ethertype_filter *filter)
8794 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8795 filter->input.ether_type = input->ether_type;
8796 filter->flags = input->flags;
8797 filter->queue = input->queue;
8802 /* Check if there exists the ehtertype filter */
8803 struct i40e_ethertype_filter *
8804 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8805 const struct i40e_ethertype_filter_input *input)
8809 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8813 return ethertype_rule->hash_map[ret];
8816 /* Add ethertype filter in SW list */
8818 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8819 struct i40e_ethertype_filter *filter)
8821 struct i40e_ethertype_rule *rule = &pf->ethertype;
8824 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8827 "Failed to insert ethertype filter"
8828 " to hash table %d!",
8832 rule->hash_map[ret] = filter;
8834 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8839 /* Delete ethertype filter in SW list */
8841 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8842 struct i40e_ethertype_filter_input *input)
8844 struct i40e_ethertype_rule *rule = &pf->ethertype;
8845 struct i40e_ethertype_filter *filter;
8848 ret = rte_hash_del_key(rule->hash_table, input);
8851 "Failed to delete ethertype filter"
8852 " to hash table %d!",
8856 filter = rule->hash_map[ret];
8857 rule->hash_map[ret] = NULL;
8859 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8866 * Configure ethertype filter, which can director packet by filtering
8867 * with mac address and ether_type or only ether_type
8870 i40e_ethertype_filter_set(struct i40e_pf *pf,
8871 struct rte_eth_ethertype_filter *filter,
8874 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8875 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8876 struct i40e_ethertype_filter *ethertype_filter, *node;
8877 struct i40e_ethertype_filter check_filter;
8878 struct i40e_control_filter_stats stats;
8882 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8883 PMD_DRV_LOG(ERR, "Invalid queue ID");
8886 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8887 filter->ether_type == ETHER_TYPE_IPv6) {
8889 "unsupported ether_type(0x%04x) in control packet filter.",
8890 filter->ether_type);
8893 if (filter->ether_type == ETHER_TYPE_VLAN)
8894 PMD_DRV_LOG(WARNING,
8895 "filter vlan ether_type in first tag is not supported.");
8897 /* Check if there is the filter in SW list */
8898 memset(&check_filter, 0, sizeof(check_filter));
8899 i40e_ethertype_filter_convert(filter, &check_filter);
8900 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8901 &check_filter.input);
8903 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8907 if (!add && !node) {
8908 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8912 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8913 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8914 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8915 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8916 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8918 memset(&stats, 0, sizeof(stats));
8919 ret = i40e_aq_add_rem_control_packet_filter(hw,
8920 filter->mac_addr.addr_bytes,
8921 filter->ether_type, flags,
8923 filter->queue, add, &stats, NULL);
8926 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8927 ret, stats.mac_etype_used, stats.etype_used,
8928 stats.mac_etype_free, stats.etype_free);
8932 /* Add or delete a filter in SW list */
8934 ethertype_filter = rte_zmalloc("ethertype_filter",
8935 sizeof(*ethertype_filter), 0);
8936 rte_memcpy(ethertype_filter, &check_filter,
8937 sizeof(check_filter));
8938 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8940 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8947 * Handle operations for ethertype filter.
8950 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8951 enum rte_filter_op filter_op,
8954 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8957 if (filter_op == RTE_ETH_FILTER_NOP)
8961 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8966 switch (filter_op) {
8967 case RTE_ETH_FILTER_ADD:
8968 ret = i40e_ethertype_filter_set(pf,
8969 (struct rte_eth_ethertype_filter *)arg,
8972 case RTE_ETH_FILTER_DELETE:
8973 ret = i40e_ethertype_filter_set(pf,
8974 (struct rte_eth_ethertype_filter *)arg,
8978 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8986 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8987 enum rte_filter_type filter_type,
8988 enum rte_filter_op filter_op,
8996 switch (filter_type) {
8997 case RTE_ETH_FILTER_NONE:
8998 /* For global configuration */
8999 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9001 case RTE_ETH_FILTER_HASH:
9002 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9004 case RTE_ETH_FILTER_MACVLAN:
9005 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9007 case RTE_ETH_FILTER_ETHERTYPE:
9008 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9010 case RTE_ETH_FILTER_TUNNEL:
9011 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9013 case RTE_ETH_FILTER_FDIR:
9014 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9016 case RTE_ETH_FILTER_GENERIC:
9017 if (filter_op != RTE_ETH_FILTER_GET)
9019 *(const void **)arg = &i40e_flow_ops;
9022 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9032 * Check and enable Extended Tag.
9033 * Enabling Extended Tag is important for 40G performance.
9036 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9038 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9042 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9045 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9049 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9050 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9055 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9058 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9062 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9063 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9066 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9067 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9070 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9077 * As some registers wouldn't be reset unless a global hardware reset,
9078 * hardware initialization is needed to put those registers into an
9079 * expected initial state.
9082 i40e_hw_init(struct rte_eth_dev *dev)
9084 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9086 i40e_enable_extended_tag(dev);
9088 /* clear the PF Queue Filter control register */
9089 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9091 /* Disable symmetric hash per port */
9092 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9095 enum i40e_filter_pctype
9096 i40e_flowtype_to_pctype(uint16_t flow_type)
9098 static const enum i40e_filter_pctype pctype_table[] = {
9099 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9100 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9101 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9102 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9103 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9104 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9105 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9106 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9107 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9108 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9109 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9110 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9111 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9112 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9113 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9114 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9115 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9116 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9117 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9120 return pctype_table[flow_type];
9124 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9126 static const uint16_t flowtype_table[] = {
9127 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9128 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9129 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9130 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9131 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9132 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9133 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9134 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9135 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9136 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9137 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9138 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9139 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9140 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9141 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9142 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9143 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9144 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9145 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9146 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9147 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9148 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9149 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9150 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9151 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9152 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9153 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9154 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9155 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9156 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9157 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9160 return flowtype_table[pctype];
9164 * On X710, performance number is far from the expectation on recent firmware
9165 * versions; on XL710, performance number is also far from the expectation on
9166 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9167 * mode is enabled and port MAC address is equal to the packet destination MAC
9168 * address. The fix for this issue may not be integrated in the following
9169 * firmware version. So the workaround in software driver is needed. It needs
9170 * to modify the initial values of 3 internal only registers for both X710 and
9171 * XL710. Note that the values for X710 or XL710 could be different, and the
9172 * workaround can be removed when it is fixed in firmware in the future.
9175 /* For both X710 and XL710 */
9176 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9177 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9179 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9180 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9183 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9184 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9187 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9189 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9190 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9193 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9195 enum i40e_status_code status;
9196 struct i40e_aq_get_phy_abilities_resp phy_ab;
9199 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9203 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9212 i40e_configure_registers(struct i40e_hw *hw)
9218 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9219 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9220 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9226 for (i = 0; i < RTE_DIM(reg_table); i++) {
9227 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9228 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9230 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9231 else /* For X710/XL710/XXV710 */
9233 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9236 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9237 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9239 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9240 else /* For X710/XL710/XXV710 */
9242 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9245 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9246 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9247 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9249 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9252 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9255 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9258 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9262 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9263 reg_table[i].addr, reg);
9264 if (reg == reg_table[i].val)
9267 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9268 reg_table[i].val, NULL);
9271 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9272 reg_table[i].val, reg_table[i].addr);
9275 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9276 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9280 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9281 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9282 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9283 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9285 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9290 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9291 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9295 /* Configure for double VLAN RX stripping */
9296 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9297 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9298 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9299 ret = i40e_aq_debug_write_register(hw,
9300 I40E_VSI_TSR(vsi->vsi_id),
9303 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9305 return I40E_ERR_CONFIG;
9309 /* Configure for double VLAN TX insertion */
9310 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9311 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9312 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9313 ret = i40e_aq_debug_write_register(hw,
9314 I40E_VSI_L2TAGSTXVALID(
9315 vsi->vsi_id), reg, NULL);
9318 "Failed to update VSI_L2TAGSTXVALID[%d]",
9320 return I40E_ERR_CONFIG;
9328 * i40e_aq_add_mirror_rule
9329 * @hw: pointer to the hardware structure
9330 * @seid: VEB seid to add mirror rule to
9331 * @dst_id: destination vsi seid
9332 * @entries: Buffer which contains the entities to be mirrored
9333 * @count: number of entities contained in the buffer
9334 * @rule_id:the rule_id of the rule to be added
9336 * Add a mirror rule for a given veb.
9339 static enum i40e_status_code
9340 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9341 uint16_t seid, uint16_t dst_id,
9342 uint16_t rule_type, uint16_t *entries,
9343 uint16_t count, uint16_t *rule_id)
9345 struct i40e_aq_desc desc;
9346 struct i40e_aqc_add_delete_mirror_rule cmd;
9347 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9348 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9351 enum i40e_status_code status;
9353 i40e_fill_default_direct_cmd_desc(&desc,
9354 i40e_aqc_opc_add_mirror_rule);
9355 memset(&cmd, 0, sizeof(cmd));
9357 buff_len = sizeof(uint16_t) * count;
9358 desc.datalen = rte_cpu_to_le_16(buff_len);
9360 desc.flags |= rte_cpu_to_le_16(
9361 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9362 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9363 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9364 cmd.num_entries = rte_cpu_to_le_16(count);
9365 cmd.seid = rte_cpu_to_le_16(seid);
9366 cmd.destination = rte_cpu_to_le_16(dst_id);
9368 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9369 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9371 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9372 hw->aq.asq_last_status, resp->rule_id,
9373 resp->mirror_rules_used, resp->mirror_rules_free);
9374 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9380 * i40e_aq_del_mirror_rule
9381 * @hw: pointer to the hardware structure
9382 * @seid: VEB seid to add mirror rule to
9383 * @entries: Buffer which contains the entities to be mirrored
9384 * @count: number of entities contained in the buffer
9385 * @rule_id:the rule_id of the rule to be delete
9387 * Delete a mirror rule for a given veb.
9390 static enum i40e_status_code
9391 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9392 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9393 uint16_t count, uint16_t rule_id)
9395 struct i40e_aq_desc desc;
9396 struct i40e_aqc_add_delete_mirror_rule cmd;
9397 uint16_t buff_len = 0;
9398 enum i40e_status_code status;
9401 i40e_fill_default_direct_cmd_desc(&desc,
9402 i40e_aqc_opc_delete_mirror_rule);
9403 memset(&cmd, 0, sizeof(cmd));
9404 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9405 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9407 cmd.num_entries = count;
9408 buff_len = sizeof(uint16_t) * count;
9409 desc.datalen = rte_cpu_to_le_16(buff_len);
9410 buff = (void *)entries;
9412 /* rule id is filled in destination field for deleting mirror rule */
9413 cmd.destination = rte_cpu_to_le_16(rule_id);
9415 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9416 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9417 cmd.seid = rte_cpu_to_le_16(seid);
9419 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9420 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9426 * i40e_mirror_rule_set
9427 * @dev: pointer to the hardware structure
9428 * @mirror_conf: mirror rule info
9429 * @sw_id: mirror rule's sw_id
9430 * @on: enable/disable
9432 * set a mirror rule.
9436 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9437 struct rte_eth_mirror_conf *mirror_conf,
9438 uint8_t sw_id, uint8_t on)
9440 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9441 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9442 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9443 struct i40e_mirror_rule *parent = NULL;
9444 uint16_t seid, dst_seid, rule_id;
9448 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9450 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9452 "mirror rule can not be configured without veb or vfs.");
9455 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9456 PMD_DRV_LOG(ERR, "mirror table is full.");
9459 if (mirror_conf->dst_pool > pf->vf_num) {
9460 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9461 mirror_conf->dst_pool);
9465 seid = pf->main_vsi->veb->seid;
9467 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9468 if (sw_id <= it->index) {
9474 if (mirr_rule && sw_id == mirr_rule->index) {
9476 PMD_DRV_LOG(ERR, "mirror rule exists.");
9479 ret = i40e_aq_del_mirror_rule(hw, seid,
9480 mirr_rule->rule_type,
9482 mirr_rule->num_entries, mirr_rule->id);
9485 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9486 ret, hw->aq.asq_last_status);
9489 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9490 rte_free(mirr_rule);
9491 pf->nb_mirror_rule--;
9495 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9499 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9500 sizeof(struct i40e_mirror_rule) , 0);
9502 PMD_DRV_LOG(ERR, "failed to allocate memory");
9503 return I40E_ERR_NO_MEMORY;
9505 switch (mirror_conf->rule_type) {
9506 case ETH_MIRROR_VLAN:
9507 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9508 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9509 mirr_rule->entries[j] =
9510 mirror_conf->vlan.vlan_id[i];
9515 PMD_DRV_LOG(ERR, "vlan is not specified.");
9516 rte_free(mirr_rule);
9519 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9521 case ETH_MIRROR_VIRTUAL_POOL_UP:
9522 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9523 /* check if the specified pool bit is out of range */
9524 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9525 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9526 rte_free(mirr_rule);
9529 for (i = 0, j = 0; i < pf->vf_num; i++) {
9530 if (mirror_conf->pool_mask & (1ULL << i)) {
9531 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9535 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9536 /* add pf vsi to entries */
9537 mirr_rule->entries[j] = pf->main_vsi_seid;
9541 PMD_DRV_LOG(ERR, "pool is not specified.");
9542 rte_free(mirr_rule);
9545 /* egress and ingress in aq commands means from switch but not port */
9546 mirr_rule->rule_type =
9547 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9548 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9549 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9551 case ETH_MIRROR_UPLINK_PORT:
9552 /* egress and ingress in aq commands means from switch but not port*/
9553 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9555 case ETH_MIRROR_DOWNLINK_PORT:
9556 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9559 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9560 mirror_conf->rule_type);
9561 rte_free(mirr_rule);
9565 /* If the dst_pool is equal to vf_num, consider it as PF */
9566 if (mirror_conf->dst_pool == pf->vf_num)
9567 dst_seid = pf->main_vsi_seid;
9569 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9571 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9572 mirr_rule->rule_type, mirr_rule->entries,
9576 "failed to add mirror rule: ret = %d, aq_err = %d.",
9577 ret, hw->aq.asq_last_status);
9578 rte_free(mirr_rule);
9582 mirr_rule->index = sw_id;
9583 mirr_rule->num_entries = j;
9584 mirr_rule->id = rule_id;
9585 mirr_rule->dst_vsi_seid = dst_seid;
9588 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9590 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9592 pf->nb_mirror_rule++;
9597 * i40e_mirror_rule_reset
9598 * @dev: pointer to the device
9599 * @sw_id: mirror rule's sw_id
9601 * reset a mirror rule.
9605 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9607 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9608 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9609 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9613 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9615 seid = pf->main_vsi->veb->seid;
9617 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9618 if (sw_id == it->index) {
9624 ret = i40e_aq_del_mirror_rule(hw, seid,
9625 mirr_rule->rule_type,
9627 mirr_rule->num_entries, mirr_rule->id);
9630 "failed to remove mirror rule: status = %d, aq_err = %d.",
9631 ret, hw->aq.asq_last_status);
9634 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9635 rte_free(mirr_rule);
9636 pf->nb_mirror_rule--;
9638 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9645 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9648 uint64_t systim_cycles;
9650 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9651 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9654 return systim_cycles;
9658 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9663 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9664 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9671 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9673 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9676 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9677 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9684 i40e_start_timecounters(struct rte_eth_dev *dev)
9686 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9687 struct i40e_adapter *adapter =
9688 (struct i40e_adapter *)dev->data->dev_private;
9689 struct rte_eth_link link;
9690 uint32_t tsync_inc_l;
9691 uint32_t tsync_inc_h;
9693 /* Get current link speed. */
9694 memset(&link, 0, sizeof(link));
9695 i40e_dev_link_update(dev, 1);
9696 rte_i40e_dev_atomic_read_link_status(dev, &link);
9698 switch (link.link_speed) {
9699 case ETH_SPEED_NUM_40G:
9700 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9701 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9703 case ETH_SPEED_NUM_10G:
9704 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9705 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9707 case ETH_SPEED_NUM_1G:
9708 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9709 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9716 /* Set the timesync increment value. */
9717 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9718 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9720 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9721 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9722 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9724 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9725 adapter->systime_tc.cc_shift = 0;
9726 adapter->systime_tc.nsec_mask = 0;
9728 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9729 adapter->rx_tstamp_tc.cc_shift = 0;
9730 adapter->rx_tstamp_tc.nsec_mask = 0;
9732 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9733 adapter->tx_tstamp_tc.cc_shift = 0;
9734 adapter->tx_tstamp_tc.nsec_mask = 0;
9738 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9740 struct i40e_adapter *adapter =
9741 (struct i40e_adapter *)dev->data->dev_private;
9743 adapter->systime_tc.nsec += delta;
9744 adapter->rx_tstamp_tc.nsec += delta;
9745 adapter->tx_tstamp_tc.nsec += delta;
9751 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9754 struct i40e_adapter *adapter =
9755 (struct i40e_adapter *)dev->data->dev_private;
9757 ns = rte_timespec_to_ns(ts);
9759 /* Set the timecounters to a new value. */
9760 adapter->systime_tc.nsec = ns;
9761 adapter->rx_tstamp_tc.nsec = ns;
9762 adapter->tx_tstamp_tc.nsec = ns;
9768 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9770 uint64_t ns, systime_cycles;
9771 struct i40e_adapter *adapter =
9772 (struct i40e_adapter *)dev->data->dev_private;
9774 systime_cycles = i40e_read_systime_cyclecounter(dev);
9775 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9776 *ts = rte_ns_to_timespec(ns);
9782 i40e_timesync_enable(struct rte_eth_dev *dev)
9784 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9785 uint32_t tsync_ctl_l;
9786 uint32_t tsync_ctl_h;
9788 /* Stop the timesync system time. */
9789 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9790 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9791 /* Reset the timesync system time value. */
9792 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9793 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9795 i40e_start_timecounters(dev);
9797 /* Clear timesync registers. */
9798 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9799 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9800 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9801 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9802 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9803 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9805 /* Enable timestamping of PTP packets. */
9806 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9807 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9809 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9810 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9811 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9813 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9814 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9820 i40e_timesync_disable(struct rte_eth_dev *dev)
9822 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9823 uint32_t tsync_ctl_l;
9824 uint32_t tsync_ctl_h;
9826 /* Disable timestamping of transmitted PTP packets. */
9827 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9828 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9830 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9831 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9833 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9834 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9836 /* Reset the timesync increment value. */
9837 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9838 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9844 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9845 struct timespec *timestamp, uint32_t flags)
9847 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9848 struct i40e_adapter *adapter =
9849 (struct i40e_adapter *)dev->data->dev_private;
9851 uint32_t sync_status;
9852 uint32_t index = flags & 0x03;
9853 uint64_t rx_tstamp_cycles;
9856 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9857 if ((sync_status & (1 << index)) == 0)
9860 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9861 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9862 *timestamp = rte_ns_to_timespec(ns);
9868 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9869 struct timespec *timestamp)
9871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9872 struct i40e_adapter *adapter =
9873 (struct i40e_adapter *)dev->data->dev_private;
9875 uint32_t sync_status;
9876 uint64_t tx_tstamp_cycles;
9879 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9880 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9883 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9884 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9885 *timestamp = rte_ns_to_timespec(ns);
9891 * i40e_parse_dcb_configure - parse dcb configure from user
9892 * @dev: the device being configured
9893 * @dcb_cfg: pointer of the result of parse
9894 * @*tc_map: bit map of enabled traffic classes
9896 * Returns 0 on success, negative value on failure
9899 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9900 struct i40e_dcbx_config *dcb_cfg,
9903 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9904 uint8_t i, tc_bw, bw_lf;
9906 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9908 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9909 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9910 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9914 /* assume each tc has the same bw */
9915 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9916 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9917 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9918 /* to ensure the sum of tcbw is equal to 100 */
9919 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9920 for (i = 0; i < bw_lf; i++)
9921 dcb_cfg->etscfg.tcbwtable[i]++;
9923 /* assume each tc has the same Transmission Selection Algorithm */
9924 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9925 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9927 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9928 dcb_cfg->etscfg.prioritytable[i] =
9929 dcb_rx_conf->dcb_tc[i];
9931 /* FW needs one App to configure HW */
9932 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9933 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9934 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9935 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9937 if (dcb_rx_conf->nb_tcs == 0)
9938 *tc_map = 1; /* tc0 only */
9940 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9942 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9943 dcb_cfg->pfc.willing = 0;
9944 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9945 dcb_cfg->pfc.pfcenable = *tc_map;
9951 static enum i40e_status_code
9952 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9953 struct i40e_aqc_vsi_properties_data *info,
9954 uint8_t enabled_tcmap)
9956 enum i40e_status_code ret;
9957 int i, total_tc = 0;
9958 uint16_t qpnum_per_tc, bsf, qp_idx;
9959 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9960 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9961 uint16_t used_queues;
9963 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9964 if (ret != I40E_SUCCESS)
9967 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9968 if (enabled_tcmap & (1 << i))
9973 vsi->enabled_tc = enabled_tcmap;
9975 /* different VSI has different queues assigned */
9976 if (vsi->type == I40E_VSI_MAIN)
9977 used_queues = dev_data->nb_rx_queues -
9978 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9979 else if (vsi->type == I40E_VSI_VMDQ2)
9980 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9982 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9983 return I40E_ERR_NO_AVAILABLE_VSI;
9986 qpnum_per_tc = used_queues / total_tc;
9987 /* Number of queues per enabled TC */
9988 if (qpnum_per_tc == 0) {
9989 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9990 return I40E_ERR_INVALID_QP_ID;
9992 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9994 bsf = rte_bsf32(qpnum_per_tc);
9997 * Configure TC and queue mapping parameters, for enabled TC,
9998 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9999 * default queue will serve it.
10002 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10003 if (vsi->enabled_tc & (1 << i)) {
10004 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10005 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10006 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10007 qp_idx += qpnum_per_tc;
10009 info->tc_mapping[i] = 0;
10012 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10013 if (vsi->type == I40E_VSI_SRIOV) {
10014 info->mapping_flags |=
10015 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10016 for (i = 0; i < vsi->nb_qps; i++)
10017 info->queue_mapping[i] =
10018 rte_cpu_to_le_16(vsi->base_queue + i);
10020 info->mapping_flags |=
10021 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10022 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10024 info->valid_sections |=
10025 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10027 return I40E_SUCCESS;
10031 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10032 * @veb: VEB to be configured
10033 * @tc_map: enabled TC bitmap
10035 * Returns 0 on success, negative value on failure
10037 static enum i40e_status_code
10038 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10040 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10041 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10042 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10043 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10044 enum i40e_status_code ret = I40E_SUCCESS;
10048 /* Check if enabled_tc is same as existing or new TCs */
10049 if (veb->enabled_tc == tc_map)
10052 /* configure tc bandwidth */
10053 memset(&veb_bw, 0, sizeof(veb_bw));
10054 veb_bw.tc_valid_bits = tc_map;
10055 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10056 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10057 if (tc_map & BIT_ULL(i))
10058 veb_bw.tc_bw_share_credits[i] = 1;
10060 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10064 "AQ command Config switch_comp BW allocation per TC failed = %d",
10065 hw->aq.asq_last_status);
10069 memset(&ets_query, 0, sizeof(ets_query));
10070 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10072 if (ret != I40E_SUCCESS) {
10074 "Failed to get switch_comp ETS configuration %u",
10075 hw->aq.asq_last_status);
10078 memset(&bw_query, 0, sizeof(bw_query));
10079 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10081 if (ret != I40E_SUCCESS) {
10083 "Failed to get switch_comp bandwidth configuration %u",
10084 hw->aq.asq_last_status);
10088 /* store and print out BW info */
10089 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10090 veb->bw_info.bw_max = ets_query.tc_bw_max;
10091 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10092 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10093 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10094 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10095 I40E_16_BIT_WIDTH);
10096 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10097 veb->bw_info.bw_ets_share_credits[i] =
10098 bw_query.tc_bw_share_credits[i];
10099 veb->bw_info.bw_ets_credits[i] =
10100 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10101 /* 4 bits per TC, 4th bit is reserved */
10102 veb->bw_info.bw_ets_max[i] =
10103 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10104 RTE_LEN2MASK(3, uint8_t));
10105 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10106 veb->bw_info.bw_ets_share_credits[i]);
10107 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10108 veb->bw_info.bw_ets_credits[i]);
10109 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10110 veb->bw_info.bw_ets_max[i]);
10113 veb->enabled_tc = tc_map;
10120 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10121 * @vsi: VSI to be configured
10122 * @tc_map: enabled TC bitmap
10124 * Returns 0 on success, negative value on failure
10126 static enum i40e_status_code
10127 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10129 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10130 struct i40e_vsi_context ctxt;
10131 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10132 enum i40e_status_code ret = I40E_SUCCESS;
10135 /* Check if enabled_tc is same as existing or new TCs */
10136 if (vsi->enabled_tc == tc_map)
10139 /* configure tc bandwidth */
10140 memset(&bw_data, 0, sizeof(bw_data));
10141 bw_data.tc_valid_bits = tc_map;
10142 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10143 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10144 if (tc_map & BIT_ULL(i))
10145 bw_data.tc_bw_credits[i] = 1;
10147 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10150 "AQ command Config VSI BW allocation per TC failed = %d",
10151 hw->aq.asq_last_status);
10154 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10155 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10157 /* Update Queue Pairs Mapping for currently enabled UPs */
10158 ctxt.seid = vsi->seid;
10159 ctxt.pf_num = hw->pf_id;
10161 ctxt.uplink_seid = vsi->uplink_seid;
10162 ctxt.info = vsi->info;
10164 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10168 /* Update the VSI after updating the VSI queue-mapping information */
10169 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10171 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10172 hw->aq.asq_last_status);
10175 /* update the local VSI info with updated queue map */
10176 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10177 sizeof(vsi->info.tc_mapping));
10178 (void)rte_memcpy(&vsi->info.queue_mapping,
10179 &ctxt.info.queue_mapping,
10180 sizeof(vsi->info.queue_mapping));
10181 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10182 vsi->info.valid_sections = 0;
10184 /* query and update current VSI BW information */
10185 ret = i40e_vsi_get_bw_config(vsi);
10188 "Failed updating vsi bw info, err %s aq_err %s",
10189 i40e_stat_str(hw, ret),
10190 i40e_aq_str(hw, hw->aq.asq_last_status));
10194 vsi->enabled_tc = tc_map;
10201 * i40e_dcb_hw_configure - program the dcb setting to hw
10202 * @pf: pf the configuration is taken on
10203 * @new_cfg: new configuration
10204 * @tc_map: enabled TC bitmap
10206 * Returns 0 on success, negative value on failure
10208 static enum i40e_status_code
10209 i40e_dcb_hw_configure(struct i40e_pf *pf,
10210 struct i40e_dcbx_config *new_cfg,
10213 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10214 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10215 struct i40e_vsi *main_vsi = pf->main_vsi;
10216 struct i40e_vsi_list *vsi_list;
10217 enum i40e_status_code ret;
10221 /* Use the FW API if FW > v4.4*/
10222 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10223 (hw->aq.fw_maj_ver >= 5))) {
10225 "FW < v4.4, can not use FW LLDP API to configure DCB");
10226 return I40E_ERR_FIRMWARE_API_VERSION;
10229 /* Check if need reconfiguration */
10230 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10231 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10232 return I40E_SUCCESS;
10235 /* Copy the new config to the current config */
10236 *old_cfg = *new_cfg;
10237 old_cfg->etsrec = old_cfg->etscfg;
10238 ret = i40e_set_dcb_config(hw);
10240 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10241 i40e_stat_str(hw, ret),
10242 i40e_aq_str(hw, hw->aq.asq_last_status));
10245 /* set receive Arbiter to RR mode and ETS scheme by default */
10246 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10247 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10248 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10249 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10250 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10251 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10252 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10253 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10254 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10255 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10256 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10257 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10258 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10260 /* get local mib to check whether it is configured correctly */
10262 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10263 /* Get Local DCB Config */
10264 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10265 &hw->local_dcbx_config);
10267 /* if Veb is created, need to update TC of it at first */
10268 if (main_vsi->veb) {
10269 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10271 PMD_INIT_LOG(WARNING,
10272 "Failed configuring TC for VEB seid=%d",
10273 main_vsi->veb->seid);
10275 /* Update each VSI */
10276 i40e_vsi_config_tc(main_vsi, tc_map);
10277 if (main_vsi->veb) {
10278 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10279 /* Beside main VSI and VMDQ VSIs, only enable default
10280 * TC for other VSIs
10282 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10283 ret = i40e_vsi_config_tc(vsi_list->vsi,
10286 ret = i40e_vsi_config_tc(vsi_list->vsi,
10287 I40E_DEFAULT_TCMAP);
10289 PMD_INIT_LOG(WARNING,
10290 "Failed configuring TC for VSI seid=%d",
10291 vsi_list->vsi->seid);
10295 return I40E_SUCCESS;
10299 * i40e_dcb_init_configure - initial dcb config
10300 * @dev: device being configured
10301 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10303 * Returns 0 on success, negative value on failure
10306 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10308 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10309 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10312 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10313 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10317 /* DCB initialization:
10318 * Update DCB configuration from the Firmware and configure
10319 * LLDP MIB change event.
10321 if (sw_dcb == TRUE) {
10322 ret = i40e_init_dcb(hw);
10323 /* If lldp agent is stopped, the return value from
10324 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10325 * adminq status. Otherwise, it should return success.
10327 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10328 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10329 memset(&hw->local_dcbx_config, 0,
10330 sizeof(struct i40e_dcbx_config));
10331 /* set dcb default configuration */
10332 hw->local_dcbx_config.etscfg.willing = 0;
10333 hw->local_dcbx_config.etscfg.maxtcs = 0;
10334 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10335 hw->local_dcbx_config.etscfg.tsatable[0] =
10337 /* all UPs mapping to TC0 */
10338 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10339 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10340 hw->local_dcbx_config.etsrec =
10341 hw->local_dcbx_config.etscfg;
10342 hw->local_dcbx_config.pfc.willing = 0;
10343 hw->local_dcbx_config.pfc.pfccap =
10344 I40E_MAX_TRAFFIC_CLASS;
10345 /* FW needs one App to configure HW */
10346 hw->local_dcbx_config.numapps = 1;
10347 hw->local_dcbx_config.app[0].selector =
10348 I40E_APP_SEL_ETHTYPE;
10349 hw->local_dcbx_config.app[0].priority = 3;
10350 hw->local_dcbx_config.app[0].protocolid =
10351 I40E_APP_PROTOID_FCOE;
10352 ret = i40e_set_dcb_config(hw);
10355 "default dcb config fails. err = %d, aq_err = %d.",
10356 ret, hw->aq.asq_last_status);
10361 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10362 ret, hw->aq.asq_last_status);
10366 ret = i40e_aq_start_lldp(hw, NULL);
10367 if (ret != I40E_SUCCESS)
10368 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10370 ret = i40e_init_dcb(hw);
10372 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10374 "HW doesn't support DCBX offload.");
10379 "DCBX configuration failed, err = %d, aq_err = %d.",
10380 ret, hw->aq.asq_last_status);
10388 * i40e_dcb_setup - setup dcb related config
10389 * @dev: device being configured
10391 * Returns 0 on success, negative value on failure
10394 i40e_dcb_setup(struct rte_eth_dev *dev)
10396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10397 struct i40e_dcbx_config dcb_cfg;
10398 uint8_t tc_map = 0;
10401 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10402 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10406 if (pf->vf_num != 0)
10407 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10409 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10411 PMD_INIT_LOG(ERR, "invalid dcb config");
10414 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10416 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10424 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10425 struct rte_eth_dcb_info *dcb_info)
10427 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10428 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10429 struct i40e_vsi *vsi = pf->main_vsi;
10430 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10431 uint16_t bsf, tc_mapping;
10434 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10435 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10437 dcb_info->nb_tcs = 1;
10438 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10439 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10440 for (i = 0; i < dcb_info->nb_tcs; i++)
10441 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10443 /* get queue mapping if vmdq is disabled */
10444 if (!pf->nb_cfg_vmdq_vsi) {
10445 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10446 if (!(vsi->enabled_tc & (1 << i)))
10448 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10449 dcb_info->tc_queue.tc_rxq[j][i].base =
10450 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10451 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10452 dcb_info->tc_queue.tc_txq[j][i].base =
10453 dcb_info->tc_queue.tc_rxq[j][i].base;
10454 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10455 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10456 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10457 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10458 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10463 /* get queue mapping if vmdq is enabled */
10465 vsi = pf->vmdq[j].vsi;
10466 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10467 if (!(vsi->enabled_tc & (1 << i)))
10469 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10470 dcb_info->tc_queue.tc_rxq[j][i].base =
10471 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10472 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10473 dcb_info->tc_queue.tc_txq[j][i].base =
10474 dcb_info->tc_queue.tc_rxq[j][i].base;
10475 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10476 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10477 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10478 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10479 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10482 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10487 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10489 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10490 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10491 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10492 uint16_t interval =
10493 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10494 uint16_t msix_intr;
10496 msix_intr = intr_handle->intr_vec[queue_id];
10497 if (msix_intr == I40E_MISC_VEC_ID)
10498 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10499 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10500 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10501 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10503 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10506 I40E_PFINT_DYN_CTLN(msix_intr -
10507 I40E_RX_VEC_START),
10508 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10509 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10510 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10512 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10514 I40E_WRITE_FLUSH(hw);
10515 rte_intr_enable(&pci_dev->intr_handle);
10521 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10523 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10524 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10525 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10526 uint16_t msix_intr;
10528 msix_intr = intr_handle->intr_vec[queue_id];
10529 if (msix_intr == I40E_MISC_VEC_ID)
10530 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10533 I40E_PFINT_DYN_CTLN(msix_intr -
10534 I40E_RX_VEC_START),
10536 I40E_WRITE_FLUSH(hw);
10541 static int i40e_get_regs(struct rte_eth_dev *dev,
10542 struct rte_dev_reg_info *regs)
10544 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10545 uint32_t *ptr_data = regs->data;
10546 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10547 const struct i40e_reg_info *reg_info;
10549 if (ptr_data == NULL) {
10550 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10551 regs->width = sizeof(uint32_t);
10555 /* The first few registers have to be read using AQ operations */
10557 while (i40e_regs_adminq[reg_idx].name) {
10558 reg_info = &i40e_regs_adminq[reg_idx++];
10559 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10561 arr_idx2 <= reg_info->count2;
10563 reg_offset = arr_idx * reg_info->stride1 +
10564 arr_idx2 * reg_info->stride2;
10565 reg_offset += reg_info->base_addr;
10566 ptr_data[reg_offset >> 2] =
10567 i40e_read_rx_ctl(hw, reg_offset);
10571 /* The remaining registers can be read using primitives */
10573 while (i40e_regs_others[reg_idx].name) {
10574 reg_info = &i40e_regs_others[reg_idx++];
10575 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10577 arr_idx2 <= reg_info->count2;
10579 reg_offset = arr_idx * reg_info->stride1 +
10580 arr_idx2 * reg_info->stride2;
10581 reg_offset += reg_info->base_addr;
10582 ptr_data[reg_offset >> 2] =
10583 I40E_READ_REG(hw, reg_offset);
10590 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10592 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10594 /* Convert word count to byte count */
10595 return hw->nvm.sr_size << 1;
10598 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10599 struct rte_dev_eeprom_info *eeprom)
10601 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10602 uint16_t *data = eeprom->data;
10603 uint16_t offset, length, cnt_words;
10606 offset = eeprom->offset >> 1;
10607 length = eeprom->length >> 1;
10608 cnt_words = length;
10610 if (offset > hw->nvm.sr_size ||
10611 offset + length > hw->nvm.sr_size) {
10612 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10616 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10618 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10619 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10620 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10627 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10628 struct ether_addr *mac_addr)
10630 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10632 if (!is_valid_assigned_ether_addr(mac_addr)) {
10633 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10637 /* Flags: 0x3 updates port address */
10638 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10642 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10644 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10645 struct rte_eth_dev_data *dev_data = pf->dev_data;
10646 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10649 /* check if mtu is within the allowed range */
10650 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10653 /* mtu setting is forbidden if port is start */
10654 if (dev_data->dev_started) {
10655 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10656 dev_data->port_id);
10660 if (frame_size > ETHER_MAX_LEN)
10661 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10663 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10665 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10670 /* Restore ethertype filter */
10672 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10674 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10675 struct i40e_ethertype_filter_list
10676 *ethertype_list = &pf->ethertype.ethertype_list;
10677 struct i40e_ethertype_filter *f;
10678 struct i40e_control_filter_stats stats;
10681 TAILQ_FOREACH(f, ethertype_list, rules) {
10683 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10684 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10685 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10686 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10687 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10689 memset(&stats, 0, sizeof(stats));
10690 i40e_aq_add_rem_control_packet_filter(hw,
10691 f->input.mac_addr.addr_bytes,
10692 f->input.ether_type,
10693 flags, pf->main_vsi->seid,
10694 f->queue, 1, &stats, NULL);
10696 PMD_DRV_LOG(INFO, "Ethertype filter:"
10697 " mac_etype_used = %u, etype_used = %u,"
10698 " mac_etype_free = %u, etype_free = %u",
10699 stats.mac_etype_used, stats.etype_used,
10700 stats.mac_etype_free, stats.etype_free);
10703 /* Restore tunnel filter */
10705 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10707 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10708 struct i40e_vsi *vsi;
10709 struct i40e_pf_vf *vf;
10710 struct i40e_tunnel_filter_list
10711 *tunnel_list = &pf->tunnel.tunnel_list;
10712 struct i40e_tunnel_filter *f;
10713 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10714 bool big_buffer = 0;
10716 TAILQ_FOREACH(f, tunnel_list, rules) {
10718 vsi = pf->main_vsi;
10720 vf = &pf->vfs[f->vf_id];
10723 memset(&cld_filter, 0, sizeof(cld_filter));
10724 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10725 (struct ether_addr *)&cld_filter.element.outer_mac);
10726 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10727 (struct ether_addr *)&cld_filter.element.inner_mac);
10728 cld_filter.element.inner_vlan = f->input.inner_vlan;
10729 cld_filter.element.flags = f->input.flags;
10730 cld_filter.element.tenant_id = f->input.tenant_id;
10731 cld_filter.element.queue_number = f->queue;
10732 rte_memcpy(cld_filter.general_fields,
10733 f->input.general_fields,
10734 sizeof(f->input.general_fields));
10736 if (((f->input.flags &
10737 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10738 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10740 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10741 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10743 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10744 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10748 i40e_aq_add_cloud_filters_big_buffer(hw,
10749 vsi->seid, &cld_filter, 1);
10751 i40e_aq_add_cloud_filters(hw, vsi->seid,
10752 &cld_filter.element, 1);
10757 i40e_filter_restore(struct i40e_pf *pf)
10759 i40e_ethertype_filter_restore(pf);
10760 i40e_tunnel_filter_restore(pf);
10761 i40e_fdir_filter_restore(pf);
10765 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10767 if (strcmp(dev->device->driver->name, drv->driver.name))
10774 is_i40e_supported(struct rte_eth_dev *dev)
10776 return is_device_supported(dev, &rte_i40e_pmd);
10779 /* Create a QinQ cloud filter
10781 * The Fortville NIC has limited resources for tunnel filters,
10782 * so we can only reuse existing filters.
10784 * In step 1 we define which Field Vector fields can be used for
10786 * As we do not have the inner tag defined as a field,
10787 * we have to define it first, by reusing one of L1 entries.
10789 * In step 2 we are replacing one of existing filter types with
10790 * a new one for QinQ.
10791 * As we reusing L1 and replacing L2, some of the default filter
10792 * types will disappear,which depends on L1 and L2 entries we reuse.
10794 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10796 * 1. Create L1 filter of outer vlan (12b) which will be in use
10797 * later when we define the cloud filter.
10798 * a. Valid_flags.replace_cloud = 0
10799 * b. Old_filter = 10 (Stag_Inner_Vlan)
10800 * c. New_filter = 0x10
10801 * d. TR bit = 0xff (optional, not used here)
10802 * e. Buffer – 2 entries:
10803 * i. Byte 0 = 8 (outer vlan FV index).
10805 * Byte 2-3 = 0x0fff
10806 * ii. Byte 0 = 37 (inner vlan FV index).
10808 * Byte 2-3 = 0x0fff
10811 * 2. Create cloud filter using two L1 filters entries: stag and
10812 * new filter(outer vlan+ inner vlan)
10813 * a. Valid_flags.replace_cloud = 1
10814 * b. Old_filter = 1 (instead of outer IP)
10815 * c. New_filter = 0x10
10816 * d. Buffer – 2 entries:
10817 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10818 * Byte 1-3 = 0 (rsv)
10819 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10820 * Byte 9-11 = 0 (rsv)
10823 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10825 int ret = -ENOTSUP;
10826 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10827 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10828 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10831 memset(&filter_replace, 0,
10832 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10833 memset(&filter_replace_buf, 0,
10834 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10836 /* create L1 filter */
10837 filter_replace.old_filter_type =
10838 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10839 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10840 filter_replace.tr_bit = 0;
10842 /* Prepare the buffer, 2 entries */
10843 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10844 filter_replace_buf.data[0] |=
10845 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10846 /* Field Vector 12b mask */
10847 filter_replace_buf.data[2] = 0xff;
10848 filter_replace_buf.data[3] = 0x0f;
10849 filter_replace_buf.data[4] =
10850 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10851 filter_replace_buf.data[4] |=
10852 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10853 /* Field Vector 12b mask */
10854 filter_replace_buf.data[6] = 0xff;
10855 filter_replace_buf.data[7] = 0x0f;
10856 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10857 &filter_replace_buf);
10858 if (ret != I40E_SUCCESS)
10861 /* Apply the second L2 cloud filter */
10862 memset(&filter_replace, 0,
10863 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10864 memset(&filter_replace_buf, 0,
10865 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10867 /* create L2 filter, input for L2 filter will be L1 filter */
10868 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10869 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10870 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10872 /* Prepare the buffer, 2 entries */
10873 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10874 filter_replace_buf.data[0] |=
10875 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10876 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10877 filter_replace_buf.data[4] |=
10878 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10879 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10880 &filter_replace_buf);
10884 RTE_INIT(i40e_init_log);
10886 i40e_init_log(void)
10888 i40e_logtype_init = rte_log_register("pmd.i40e.init");
10889 if (i40e_logtype_init >= 0)
10890 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10891 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10892 if (i40e_logtype_driver >= 0)
10893 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);