drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 373                                       struct ether_addr *mac_addr);
 374
 375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 376
 377 static int i40e_ethertype_filter_convert(
 378         const struct rte_eth_ethertype_filter *input,
 379         struct i40e_ethertype_filter *filter);
 380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 381                                    struct i40e_ethertype_filter *filter);
 382
 383 static int i40e_tunnel_filter_convert(
 384         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 385         struct i40e_tunnel_filter *tunnel_filter);
 386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 387                                 struct i40e_tunnel_filter *tunnel_filter);
 388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 389
 390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 392 static void i40e_filter_restore(struct i40e_pf *pf);
 393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 394
 395 int i40e_logtype_init;
 396 int i40e_logtype_driver;
 397
 398 static const struct rte_pci_id pci_id_i40e_map[] = {
 399         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 419         { .vendor_id = 0, /* sentinel */ },
 420 };
 421
 422 static const struct eth_dev_ops i40e_eth_dev_ops = {
 423         .dev_configure                = i40e_dev_configure,
 424         .dev_start                    = i40e_dev_start,
 425         .dev_stop                     = i40e_dev_stop,
 426         .dev_close                    = i40e_dev_close,
 427         .dev_reset                    = i40e_dev_reset,
 428         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 429         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 430         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 431         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 432         .dev_set_link_up              = i40e_dev_set_link_up,
 433         .dev_set_link_down            = i40e_dev_set_link_down,
 434         .link_update                  = i40e_dev_link_update,
 435         .stats_get                    = i40e_dev_stats_get,
 436         .xstats_get                   = i40e_dev_xstats_get,
 437         .xstats_get_names             = i40e_dev_xstats_get_names,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .fw_version_get               = i40e_fw_version_get,
 442         .dev_infos_get                = i40e_dev_info_get,
 443         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 444         .vlan_filter_set              = i40e_vlan_filter_set,
 445         .vlan_tpid_set                = i40e_vlan_tpid_set,
 446         .vlan_offload_set             = i40e_vlan_offload_set,
 447         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 448         .vlan_pvid_set                = i40e_vlan_pvid_set,
 449         .rx_queue_start               = i40e_dev_rx_queue_start,
 450         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 451         .tx_queue_start               = i40e_dev_tx_queue_start,
 452         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 453         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 454         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 455         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 456         .rx_queue_release             = i40e_dev_rx_queue_release,
 457         .rx_queue_count               = i40e_dev_rx_queue_count,
 458         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 459         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 460         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 461         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 462         .tx_queue_release             = i40e_dev_tx_queue_release,
 463         .dev_led_on                   = i40e_dev_led_on,
 464         .dev_led_off                  = i40e_dev_led_off,
 465         .flow_ctrl_get                = i40e_flow_ctrl_get,
 466         .flow_ctrl_set                = i40e_flow_ctrl_set,
 467         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 468         .mac_addr_add                 = i40e_macaddr_add,
 469         .mac_addr_remove              = i40e_macaddr_remove,
 470         .reta_update                  = i40e_dev_rss_reta_update,
 471         .reta_query                   = i40e_dev_rss_reta_query,
 472         .rss_hash_update              = i40e_dev_rss_hash_update,
 473         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 474         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 475         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 476         .filter_ctrl                  = i40e_dev_filter_ctrl,
 477         .rxq_info_get                 = i40e_rxq_info_get,
 478         .txq_info_get                 = i40e_txq_info_get,
 479         .mirror_rule_set              = i40e_mirror_rule_set,
 480         .mirror_rule_reset            = i40e_mirror_rule_reset,
 481         .timesync_enable              = i40e_timesync_enable,
 482         .timesync_disable             = i40e_timesync_disable,
 483         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 484         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 485         .get_dcb_info                 = i40e_dev_get_dcb_info,
 486         .timesync_adjust_time         = i40e_timesync_adjust_time,
 487         .timesync_read_time           = i40e_timesync_read_time,
 488         .timesync_write_time          = i40e_timesync_write_time,
 489         .get_reg                      = i40e_get_regs,
 490         .get_eeprom_length            = i40e_get_eeprom_length,
 491         .get_eeprom                   = i40e_get_eeprom,
 492         .mac_addr_set                 = i40e_set_default_mac_addr,
 493         .mtu_set                      = i40e_dev_mtu_set,
 494         .tm_ops_get                   = i40e_tm_ops_get,
 495 };
 496
 497 /* store statistics names and its offset in stats structure */
 498 struct rte_i40e_xstats_name_off {
 499         char name[RTE_ETH_XSTATS_NAME_SIZE];
 500         unsigned offset;
 501 };
 502
 503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 504         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 505         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 506         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 507         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 508         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 509                 rx_unknown_protocol)},
 510         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 511         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 512         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 513         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 514 };
 515
 516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 517                 sizeof(rte_i40e_stats_strings[0]))
 518
 519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 520         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 521                 tx_dropped_link_down)},
 522         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 523         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 524                 illegal_bytes)},
 525         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 526         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 527                 mac_local_faults)},
 528         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 529                 mac_remote_faults)},
 530         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 531                 rx_length_errors)},
 532         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 533         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 534         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 535         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 536         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 537         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_127)},
 539         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 540                 rx_size_255)},
 541         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 542                 rx_size_511)},
 543         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 544                 rx_size_1023)},
 545         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_1522)},
 547         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_big)},
 549         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_undersize)},
 551         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_oversize)},
 553         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 554                 mac_short_packet_dropped)},
 555         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_fragments)},
 557         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 558         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 559         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_127)},
 561         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 tx_size_255)},
 563         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 tx_size_511)},
 565         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 tx_size_1023)},
 567         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_1522)},
 569         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_big)},
 571         {"rx_flow_director_atr_match_packets",
 572                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 573         {"rx_flow_director_sb_match_packets",
 574                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 575         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 576                 tx_lpi_status)},
 577         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 578                 rx_lpi_status)},
 579         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 580                 tx_lpi_count)},
 581         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 582                 rx_lpi_count)},
 583 };
 584
 585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 586                 sizeof(rte_i40e_hw_port_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_rx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_rx)},
 593 };
 594
 595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 596                 sizeof(rte_i40e_rxq_prio_strings[0]))
 597
 598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 599         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xon_tx)},
 601         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 602                 priority_xoff_tx)},
 603         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 604                 priority_xon_2_xoff)},
 605 };
 606
 607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 608                 sizeof(rte_i40e_txq_prio_strings[0]))
 609
 610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611         struct rte_pci_device *pci_dev)
 612 {
 613         return rte_eth_dev_pci_generic_probe(pci_dev,
 614                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 615 }
 616
 617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 618 {
 619         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 620 }
 621
 622 static struct rte_pci_driver rte_i40e_pmd = {
 623         .id_table = pci_id_i40e_map,
 624         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 625                      RTE_PCI_DRV_IOVA_AS_VA,
 626         .probe = eth_i40e_pci_probe,
 627         .remove = eth_i40e_pci_remove,
 628 };
 629
 630 static inline void
 631 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 632 {
 633         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 634         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 635                     "with value 0x%08x",
 636                     reg_addr, reg_val);
 637 }
 638
 639 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 640 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 641 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 642
 643 #ifndef I40E_GLQF_ORT
 644 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 645 #endif
 646 #ifndef I40E_GLQF_PIT
 647 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 648 #endif
 649 #ifndef I40E_GLQF_L3_MAP
 650 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 651 #endif
 652
 653 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 654 {
 655         /*
 656          * Initialize registers for parsing packet type of QinQ
 657          * This should be removed from code once proper
 658          * configuration API is added to avoid configuration conflicts
 659          * between ports of the same device.
 660          */
 661         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 662         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 663         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 664 }
 665
 666 static inline void i40e_config_automask(struct i40e_pf *pf)
 667 {
 668         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 669         uint32_t val;
 670
 671         /* INTENA flag is not auto-cleared for interrupt */
 672         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 673         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 674                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 675
 676         /* If support multi-driver, PF will use INT0. */
 677         if (!pf->support_multi_driver)
 678                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 679
 680         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 681 }
 682
 683 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 684
 685 /*
 686  * Add a ethertype filter to drop all flow control frames transmitted
 687  * from VSIs.
 688 */
 689 static void
 690 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 691 {
 692         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 693         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 694                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 695                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 696         int ret;
 697
 698         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 699                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 700                                 pf->main_vsi_seid, 0,
 701                                 TRUE, NULL, NULL);
 702         if (ret)
 703                 PMD_INIT_LOG(ERR,
 704                         "Failed to add filter to drop flow control frames from VSIs.");
 705 }
 706
 707 static int
 708 floating_veb_list_handler(__rte_unused const char *key,
 709                           const char *floating_veb_value,
 710                           void *opaque)
 711 {
 712         int idx = 0;
 713         unsigned int count = 0;
 714         char *end = NULL;
 715         int min, max;
 716         bool *vf_floating_veb = opaque;
 717
 718         while (isblank(*floating_veb_value))
 719                 floating_veb_value++;
 720
 721         /* Reset floating VEB configuration for VFs */
 722         for (idx = 0; idx < I40E_MAX_VF; idx++)
 723                 vf_floating_veb[idx] = false;
 724
 725         min = I40E_MAX_VF;
 726         do {
 727                 while (isblank(*floating_veb_value))
 728                         floating_veb_value++;
 729                 if (*floating_veb_value == '\0')
 730                         return -1;
 731                 errno = 0;
 732                 idx = strtoul(floating_veb_value, &end, 10);
 733                 if (errno || end == NULL)
 734                         return -1;
 735                 while (isblank(*end))
 736                         end++;
 737                 if (*end == '-') {
 738                         min = idx;
 739                 } else if ((*end == ';') || (*end == '\0')) {
 740                         max = idx;
 741                         if (min == I40E_MAX_VF)
 742                                 min = idx;
 743                         if (max >= I40E_MAX_VF)
 744                                 max = I40E_MAX_VF - 1;
 745                         for (idx = min; idx <= max; idx++) {
 746                                 vf_floating_veb[idx] = true;
 747                                 count++;
 748                         }
 749                         min = I40E_MAX_VF;
 750                 } else {
 751                         return -1;
 752                 }
 753                 floating_veb_value = end + 1;
 754         } while (*end != '\0');
 755
 756         if (count == 0)
 757                 return -1;
 758
 759         return 0;
 760 }
 761
 762 static void
 763 config_vf_floating_veb(struct rte_devargs *devargs,
 764                        uint16_t floating_veb,
 765                        bool *vf_floating_veb)
 766 {
 767         struct rte_kvargs *kvlist;
 768         int i;
 769         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 770
 771         if (!floating_veb)
 772                 return;
 773         /* All the VFs attach to the floating VEB by default
 774          * when the floating VEB is enabled.
 775          */
 776         for (i = 0; i < I40E_MAX_VF; i++)
 777                 vf_floating_veb[i] = true;
 778
 779         if (devargs == NULL)
 780                 return;
 781
 782         kvlist = rte_kvargs_parse(devargs->args, NULL);
 783         if (kvlist == NULL)
 784                 return;
 785
 786         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 787                 rte_kvargs_free(kvlist);
 788                 return;
 789         }
 790         /* When the floating_veb_list parameter exists, all the VFs
 791          * will attach to the legacy VEB firstly, then configure VFs
 792          * to the floating VEB according to the floating_veb_list.
 793          */
 794         if (rte_kvargs_process(kvlist, floating_veb_list,
 795                                floating_veb_list_handler,
 796                                vf_floating_veb) < 0) {
 797                 rte_kvargs_free(kvlist);
 798                 return;
 799         }
 800         rte_kvargs_free(kvlist);
 801 }
 802
 803 static int
 804 i40e_check_floating_handler(__rte_unused const char *key,
 805                             const char *value,
 806                             __rte_unused void *opaque)
 807 {
 808         if (strcmp(value, "1"))
 809                 return -1;
 810
 811         return 0;
 812 }
 813
 814 static int
 815 is_floating_veb_supported(struct rte_devargs *devargs)
 816 {
 817         struct rte_kvargs *kvlist;
 818         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 819
 820         if (devargs == NULL)
 821                 return 0;
 822
 823         kvlist = rte_kvargs_parse(devargs->args, NULL);
 824         if (kvlist == NULL)
 825                 return 0;
 826
 827         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 828                 rte_kvargs_free(kvlist);
 829                 return 0;
 830         }
 831         /* Floating VEB is enabled when there's key-value:
 832          * enable_floating_veb=1
 833          */
 834         if (rte_kvargs_process(kvlist, floating_veb_key,
 835                                i40e_check_floating_handler, NULL) < 0) {
 836                 rte_kvargs_free(kvlist);
 837                 return 0;
 838         }
 839         rte_kvargs_free(kvlist);
 840
 841         return 1;
 842 }
 843
 844 static void
 845 config_floating_veb(struct rte_eth_dev *dev)
 846 {
 847         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 850
 851         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 852
 853         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 854                 pf->floating_veb =
 855                         is_floating_veb_supported(pci_dev->device.devargs);
 856                 config_vf_floating_veb(pci_dev->device.devargs,
 857                                        pf->floating_veb,
 858                                        pf->floating_veb_list);
 859         } else {
 860                 pf->floating_veb = false;
 861         }
 862 }
 863
 864 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 865 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 866
 867 static int
 868 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 869 {
 870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 871         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 872         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 873         int ret;
 874
 875         struct rte_hash_parameters ethertype_hash_params = {
 876                 .name = ethertype_hash_name,
 877                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 878                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 879                 .hash_func = rte_hash_crc,
 880                 .hash_func_init_val = 0,
 881                 .socket_id = rte_socket_id(),
 882         };
 883
 884         /* Initialize ethertype filter rule list and hash */
 885         TAILQ_INIT(&ethertype_rule->ethertype_list);
 886         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 887                  "ethertype_%s", dev->device->name);
 888         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 889         if (!ethertype_rule->hash_table) {
 890                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 891                 return -EINVAL;
 892         }
 893         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 894                                        sizeof(struct i40e_ethertype_filter *) *
 895                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 896                                        0);
 897         if (!ethertype_rule->hash_map) {
 898                 PMD_INIT_LOG(ERR,
 899                              "Failed to allocate memory for ethertype hash map!");
 900                 ret = -ENOMEM;
 901                 goto err_ethertype_hash_map_alloc;
 902         }
 903
 904         return 0;
 905
 906 err_ethertype_hash_map_alloc:
 907         rte_hash_free(ethertype_rule->hash_table);
 908
 909         return ret;
 910 }
 911
 912 static int
 913 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 914 {
 915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 916         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 917         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 918         int ret;
 919
 920         struct rte_hash_parameters tunnel_hash_params = {
 921                 .name = tunnel_hash_name,
 922                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 923                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 924                 .hash_func = rte_hash_crc,
 925                 .hash_func_init_val = 0,
 926                 .socket_id = rte_socket_id(),
 927         };
 928
 929         /* Initialize tunnel filter rule list and hash */
 930         TAILQ_INIT(&tunnel_rule->tunnel_list);
 931         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 932                  "tunnel_%s", dev->device->name);
 933         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 934         if (!tunnel_rule->hash_table) {
 935                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 936                 return -EINVAL;
 937         }
 938         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 939                                     sizeof(struct i40e_tunnel_filter *) *
 940                                     I40E_MAX_TUNNEL_FILTER_NUM,
 941                                     0);
 942         if (!tunnel_rule->hash_map) {
 943                 PMD_INIT_LOG(ERR,
 944                              "Failed to allocate memory for tunnel hash map!");
 945                 ret = -ENOMEM;
 946                 goto err_tunnel_hash_map_alloc;
 947         }
 948
 949         return 0;
 950
 951 err_tunnel_hash_map_alloc:
 952         rte_hash_free(tunnel_rule->hash_table);
 953
 954         return ret;
 955 }
 956
 957 static int
 958 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_fdir_info *fdir_info = &pf->fdir;
 962         char fdir_hash_name[RTE_HASH_NAMESIZE];
 963         int ret;
 964
 965         struct rte_hash_parameters fdir_hash_params = {
 966                 .name = fdir_hash_name,
 967                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 968                 .key_len = sizeof(struct i40e_fdir_input),
 969                 .hash_func = rte_hash_crc,
 970                 .hash_func_init_val = 0,
 971                 .socket_id = rte_socket_id(),
 972         };
 973
 974         /* Initialize flow director filter rule list and hash */
 975         TAILQ_INIT(&fdir_info->fdir_list);
 976         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 977                  "fdir_%s", dev->device->name);
 978         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 979         if (!fdir_info->hash_table) {
 980                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 981                 return -EINVAL;
 982         }
 983         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 984                                           sizeof(struct i40e_fdir_filter *) *
 985                                           I40E_MAX_FDIR_FILTER_NUM,
 986                                           0);
 987         if (!fdir_info->hash_map) {
 988                 PMD_INIT_LOG(ERR,
 989                              "Failed to allocate memory for fdir hash map!");
 990                 ret = -ENOMEM;
 991                 goto err_fdir_hash_map_alloc;
 992         }
 993         return 0;
 994
 995 err_fdir_hash_map_alloc:
 996         rte_hash_free(fdir_info->hash_table);
 997
 998         return ret;
 999 }
1000
1001 static void
1002 i40e_init_customized_info(struct i40e_pf *pf)
1003 {
1004         int i;
1005
1006         /* Initialize customized pctype */
1007         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1008                 pf->customized_pctype[i].index = i;
1009                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1010                 pf->customized_pctype[i].valid = false;
1011         }
1012
1013         pf->gtp_support = false;
1014 }
1015
1016 void
1017 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1018 {
1019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1020         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1021         struct i40e_queue_regions *info = &pf->queue_region;
1022         uint16_t i;
1023
1024         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1025                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1026
1027         memset(info, 0, sizeof(struct i40e_queue_regions));
1028 }
1029
1030 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1031
1032 static int
1033 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1034                                const char *value,
1035                                void *opaque)
1036 {
1037         struct i40e_pf *pf;
1038         unsigned long support_multi_driver;
1039         char *end;
1040
1041         pf = (struct i40e_pf *)opaque;
1042
1043         errno = 0;
1044         support_multi_driver = strtoul(value, &end, 10);
1045         if (errno != 0 || end == value || *end != 0) {
1046                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1047                 return -(EINVAL);
1048         }
1049
1050         if (support_multi_driver == 1 || support_multi_driver == 0)
1051                 pf->support_multi_driver = (bool)support_multi_driver;
1052         else
1053                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1054                             "enable global configuration by default."
1055                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1056         return 0;
1057 }
1058
1059 static int
1060 i40e_support_multi_driver(struct rte_eth_dev *dev)
1061 {
1062         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1063         static const char *const valid_keys[] = {
1064                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1065         struct rte_kvargs *kvlist;
1066
1067         /* Enable global configuration by default */
1068         pf->support_multi_driver = false;
1069
1070         if (!dev->device->devargs)
1071                 return 0;
1072
1073         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1074         if (!kvlist)
1075                 return -EINVAL;
1076
1077         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1078                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1079                             "the first invalid or last valid one is used !",
1080                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1081
1082         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1083                                i40e_parse_multi_drv_handler, pf) < 0) {
1084                 rte_kvargs_free(kvlist);
1085                 return -EINVAL;
1086         }
1087
1088         rte_kvargs_free(kvlist);
1089         return 0;
1090 }
1091
1092 static int
1093 eth_i40e_dev_init(struct rte_eth_dev *dev)
1094 {
1095         struct rte_pci_device *pci_dev;
1096         struct rte_intr_handle *intr_handle;
1097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1098         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1099         struct i40e_vsi *vsi;
1100         int ret;
1101         uint32_t len;
1102         uint8_t aq_fail = 0;
1103
1104         PMD_INIT_FUNC_TRACE();
1105
1106         dev->dev_ops = &i40e_eth_dev_ops;
1107         dev->rx_pkt_burst = i40e_recv_pkts;
1108         dev->tx_pkt_burst = i40e_xmit_pkts;
1109         dev->tx_pkt_prepare = i40e_prep_pkts;
1110
1111         /* for secondary processes, we don't initialise any further as primary
1112          * has already done this work. Only check we don't need a different
1113          * RX function */
1114         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1115                 i40e_set_rx_function(dev);
1116                 i40e_set_tx_function(dev);
1117                 return 0;
1118         }
1119         i40e_set_default_ptype_table(dev);
1120         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1121         intr_handle = &pci_dev->intr_handle;
1122
1123         rte_eth_copy_pci_info(dev, pci_dev);
1124
1125         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1126         pf->adapter->eth_dev = dev;
1127         pf->dev_data = dev->data;
1128
1129         hw->back = I40E_PF_TO_ADAPTER(pf);
1130         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1131         if (!hw->hw_addr) {
1132                 PMD_INIT_LOG(ERR,
1133                         "Hardware is not available, as address is NULL");
1134                 return -ENODEV;
1135         }
1136
1137         hw->vendor_id = pci_dev->id.vendor_id;
1138         hw->device_id = pci_dev->id.device_id;
1139         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1140         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1141         hw->bus.device = pci_dev->addr.devid;
1142         hw->bus.func = pci_dev->addr.function;
1143         hw->adapter_stopped = 0;
1144
1145         /* Check if need to support multi-driver */
1146         i40e_support_multi_driver(dev);
1147
1148         /* Make sure all is clean before doing PF reset */
1149         i40e_clear_hw(hw);
1150
1151         /* Initialize the hardware */
1152         i40e_hw_init(dev);
1153
1154         /* Reset here to make sure all is clean for each PF */
1155         ret = i40e_pf_reset(hw);
1156         if (ret) {
1157                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1158                 return ret;
1159         }
1160
1161         /* Initialize the shared code (base driver) */
1162         ret = i40e_init_shared_code(hw);
1163         if (ret) {
1164                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1165                 return ret;
1166         }
1167
1168         i40e_config_automask(pf);
1169
1170         i40e_set_default_pctype_table(dev);
1171
1172         /*
1173          * To work around the NVM issue, initialize registers
1174          * for packet type of QinQ by software.
1175          * It should be removed once issues are fixed in NVM.
1176          */
1177         if (!pf->support_multi_driver)
1178                 i40e_GLQF_reg_init(hw);
1179
1180         /* Initialize the input set for filters (hash and fd) to default value */
1181         i40e_filter_input_set_init(pf);
1182
1183         /* Initialize the parameters for adminq */
1184         i40e_init_adminq_parameter(hw);
1185         ret = i40e_init_adminq(hw);
1186         if (ret != I40E_SUCCESS) {
1187                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1188                 return -EIO;
1189         }
1190         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1191                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1192                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1193                      ((hw->nvm.version >> 12) & 0xf),
1194                      ((hw->nvm.version >> 4) & 0xff),
1195                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1196
1197         /* initialise the L3_MAP register */
1198         if (!pf->support_multi_driver) {
1199                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1200                                                    0x00000028,  NULL);
1201                 if (ret)
1202                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1203                                      ret);
1204                 PMD_INIT_LOG(DEBUG,
1205                              "Global register 0x%08x is changed with 0x28",
1206                              I40E_GLQF_L3_MAP(40));
1207                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1208         }
1209
1210         /* Need the special FW version to support floating VEB */
1211         config_floating_veb(dev);
1212         /* Clear PXE mode */
1213         i40e_clear_pxe_mode(hw);
1214         i40e_dev_sync_phy_type(hw);
1215
1216         /*
1217          * On X710, performance number is far from the expectation on recent
1218          * firmware versions. The fix for this issue may not be integrated in
1219          * the following firmware version. So the workaround in software driver
1220          * is needed. It needs to modify the initial values of 3 internal only
1221          * registers. Note that the workaround can be removed when it is fixed
1222          * in firmware in the future.
1223          */
1224         i40e_configure_registers(hw);
1225
1226         /* Get hw capabilities */
1227         ret = i40e_get_cap(hw);
1228         if (ret != I40E_SUCCESS) {
1229                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1230                 goto err_get_capabilities;
1231         }
1232
1233         /* Initialize parameters for PF */
1234         ret = i40e_pf_parameter_init(dev);
1235         if (ret != 0) {
1236                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1237                 goto err_parameter_init;
1238         }
1239
1240         /* Initialize the queue management */
1241         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1242         if (ret < 0) {
1243                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1244                 goto err_qp_pool_init;
1245         }
1246         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1247                                 hw->func_caps.num_msix_vectors - 1);
1248         if (ret < 0) {
1249                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1250                 goto err_msix_pool_init;
1251         }
1252
1253         /* Initialize lan hmc */
1254         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1255                                 hw->func_caps.num_rx_qp, 0, 0);
1256         if (ret != I40E_SUCCESS) {
1257                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1258                 goto err_init_lan_hmc;
1259         }
1260
1261         /* Configure lan hmc */
1262         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1263         if (ret != I40E_SUCCESS) {
1264                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1265                 goto err_configure_lan_hmc;
1266         }
1267
1268         /* Get and check the mac address */
1269         i40e_get_mac_addr(hw, hw->mac.addr);
1270         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1271                 PMD_INIT_LOG(ERR, "mac address is not valid");
1272                 ret = -EIO;
1273                 goto err_get_mac_addr;
1274         }
1275         /* Copy the permanent MAC address */
1276         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1277                         (struct ether_addr *) hw->mac.perm_addr);
1278
1279         /* Disable flow control */
1280         hw->fc.requested_mode = I40E_FC_NONE;
1281         i40e_set_fc(hw, &aq_fail, TRUE);
1282
1283         /* Set the global registers with default ether type value */
1284         if (!pf->support_multi_driver) {
1285                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1286                                          ETHER_TYPE_VLAN);
1287                 if (ret != I40E_SUCCESS) {
1288                         PMD_INIT_LOG(ERR,
1289                                      "Failed to set the default outer "
1290                                      "VLAN ether type");
1291                         goto err_setup_pf_switch;
1292                 }
1293         }
1294
1295         /* PF setup, which includes VSI setup */
1296         ret = i40e_pf_setup(pf);
1297         if (ret) {
1298                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1299                 goto err_setup_pf_switch;
1300         }
1301
1302         /* reset all stats of the device, including pf and main vsi */
1303         i40e_dev_stats_reset(dev);
1304
1305         vsi = pf->main_vsi;
1306
1307         /* Disable double vlan by default */
1308         i40e_vsi_config_double_vlan(vsi, FALSE);
1309
1310         /* Disable S-TAG identification when floating_veb is disabled */
1311         if (!pf->floating_veb) {
1312                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1313                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1314                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1315                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1316                 }
1317         }
1318
1319         if (!vsi->max_macaddrs)
1320                 len = ETHER_ADDR_LEN;
1321         else
1322                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1323
1324         /* Should be after VSI initialized */
1325         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1326         if (!dev->data->mac_addrs) {
1327                 PMD_INIT_LOG(ERR,
1328                         "Failed to allocated memory for storing mac address");
1329                 goto err_mac_alloc;
1330         }
1331         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1332                                         &dev->data->mac_addrs[0]);
1333
1334         /* Init dcb to sw mode by default */
1335         ret = i40e_dcb_init_configure(dev, TRUE);
1336         if (ret != I40E_SUCCESS) {
1337                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1338                 pf->flags &= ~I40E_FLAG_DCB;
1339         }
1340         /* Update HW struct after DCB configuration */
1341         i40e_get_cap(hw);
1342
1343         /* initialize pf host driver to setup SRIOV resource if applicable */
1344         i40e_pf_host_init(dev);
1345
1346         /* register callback func to eal lib */
1347         rte_intr_callback_register(intr_handle,
1348                                    i40e_dev_interrupt_handler, dev);
1349
1350         /* configure and enable device interrupt */
1351         i40e_pf_config_irq0(hw, TRUE);
1352         i40e_pf_enable_irq0(hw);
1353
1354         /* enable uio intr after callback register */
1355         rte_intr_enable(intr_handle);
1356
1357         /* By default disable flexible payload in global configuration */
1358         if (!pf->support_multi_driver)
1359                 i40e_flex_payload_reg_set_default(hw);
1360
1361         /*
1362          * Add an ethertype filter to drop all flow control frames transmitted
1363          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1364          * frames to wire.
1365          */
1366         i40e_add_tx_flow_control_drop_filter(pf);
1367
1368         /* Set the max frame size to 0x2600 by default,
1369          * in case other drivers changed the default value.
1370          */
1371         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1372
1373         /* initialize mirror rule list */
1374         TAILQ_INIT(&pf->mirror_list);
1375
1376         /* initialize Traffic Manager configuration */
1377         i40e_tm_conf_init(dev);
1378
1379         /* Initialize customized information */
1380         i40e_init_customized_info(pf);
1381
1382         ret = i40e_init_ethtype_filter_list(dev);
1383         if (ret < 0)
1384                 goto err_init_ethtype_filter_list;
1385         ret = i40e_init_tunnel_filter_list(dev);
1386         if (ret < 0)
1387                 goto err_init_tunnel_filter_list;
1388         ret = i40e_init_fdir_filter_list(dev);
1389         if (ret < 0)
1390                 goto err_init_fdir_filter_list;
1391
1392         /* initialize queue region configuration */
1393         i40e_init_queue_region_conf(dev);
1394
1395         /* initialize rss configuration from rte_flow */
1396         memset(&pf->rss_info, 0,
1397                 sizeof(struct i40e_rte_flow_rss_conf));
1398
1399         return 0;
1400
1401 err_init_fdir_filter_list:
1402         rte_free(pf->tunnel.hash_table);
1403         rte_free(pf->tunnel.hash_map);
1404 err_init_tunnel_filter_list:
1405         rte_free(pf->ethertype.hash_table);
1406         rte_free(pf->ethertype.hash_map);
1407 err_init_ethtype_filter_list:
1408         rte_free(dev->data->mac_addrs);
1409 err_mac_alloc:
1410         i40e_vsi_release(pf->main_vsi);
1411 err_setup_pf_switch:
1412 err_get_mac_addr:
1413 err_configure_lan_hmc:
1414         (void)i40e_shutdown_lan_hmc(hw);
1415 err_init_lan_hmc:
1416         i40e_res_pool_destroy(&pf->msix_pool);
1417 err_msix_pool_init:
1418         i40e_res_pool_destroy(&pf->qp_pool);
1419 err_qp_pool_init:
1420 err_parameter_init:
1421 err_get_capabilities:
1422         (void)i40e_shutdown_adminq(hw);
1423
1424         return ret;
1425 }
1426
1427 static void
1428 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1429 {
1430         struct i40e_ethertype_filter *p_ethertype;
1431         struct i40e_ethertype_rule *ethertype_rule;
1432
1433         ethertype_rule = &pf->ethertype;
1434         /* Remove all ethertype filter rules and hash */
1435         if (ethertype_rule->hash_map)
1436                 rte_free(ethertype_rule->hash_map);
1437         if (ethertype_rule->hash_table)
1438                 rte_hash_free(ethertype_rule->hash_table);
1439
1440         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1441                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1442                              p_ethertype, rules);
1443                 rte_free(p_ethertype);
1444         }
1445 }
1446
1447 static void
1448 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1449 {
1450         struct i40e_tunnel_filter *p_tunnel;
1451         struct i40e_tunnel_rule *tunnel_rule;
1452
1453         tunnel_rule = &pf->tunnel;
1454         /* Remove all tunnel director rules and hash */
1455         if (tunnel_rule->hash_map)
1456                 rte_free(tunnel_rule->hash_map);
1457         if (tunnel_rule->hash_table)
1458                 rte_hash_free(tunnel_rule->hash_table);
1459
1460         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1461                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1462                 rte_free(p_tunnel);
1463         }
1464 }
1465
1466 static void
1467 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1468 {
1469         struct i40e_fdir_filter *p_fdir;
1470         struct i40e_fdir_info *fdir_info;
1471
1472         fdir_info = &pf->fdir;
1473         /* Remove all flow director rules and hash */
1474         if (fdir_info->hash_map)
1475                 rte_free(fdir_info->hash_map);
1476         if (fdir_info->hash_table)
1477                 rte_hash_free(fdir_info->hash_table);
1478
1479         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1480                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1481                 rte_free(p_fdir);
1482         }
1483 }
1484
1485 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1486 {
1487         /*
1488          * Disable by default flexible payload
1489          * for corresponding L2/L3/L4 layers.
1490          */
1491         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1492         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1493         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1494         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1495 }
1496
1497 static int
1498 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1499 {
1500         struct i40e_pf *pf;
1501         struct rte_pci_device *pci_dev;
1502         struct rte_intr_handle *intr_handle;
1503         struct i40e_hw *hw;
1504         struct i40e_filter_control_settings settings;
1505         struct rte_flow *p_flow;
1506         int ret;
1507         uint8_t aq_fail = 0;
1508         int retries = 0;
1509
1510         PMD_INIT_FUNC_TRACE();
1511
1512         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1513                 return 0;
1514
1515         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1516         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1518         intr_handle = &pci_dev->intr_handle;
1519
1520         if (hw->adapter_stopped == 0)
1521                 i40e_dev_close(dev);
1522
1523         dev->dev_ops = NULL;
1524         dev->rx_pkt_burst = NULL;
1525         dev->tx_pkt_burst = NULL;
1526
1527         /* Clear PXE mode */
1528         i40e_clear_pxe_mode(hw);
1529
1530         /* Unconfigure filter control */
1531         memset(&settings, 0, sizeof(settings));
1532         ret = i40e_set_filter_control(hw, &settings);
1533         if (ret)
1534                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1535                                         ret);
1536
1537         /* Disable flow control */
1538         hw->fc.requested_mode = I40E_FC_NONE;
1539         i40e_set_fc(hw, &aq_fail, TRUE);
1540
1541         /* uninitialize pf host driver */
1542         i40e_pf_host_uninit(dev);
1543
1544         rte_free(dev->data->mac_addrs);
1545         dev->data->mac_addrs = NULL;
1546
1547         /* disable uio intr before callback unregister */
1548         rte_intr_disable(intr_handle);
1549
1550         /* unregister callback func to eal lib */
1551         do {
1552                 ret = rte_intr_callback_unregister(intr_handle,
1553                                 i40e_dev_interrupt_handler, dev);
1554                 if (ret >= 0) {
1555                         break;
1556                 } else if (ret != -EAGAIN) {
1557                         PMD_INIT_LOG(ERR,
1558                                  "intr callback unregister failed: %d",
1559                                  ret);
1560                         return ret;
1561                 }
1562                 i40e_msec_delay(500);
1563         } while (retries++ < 5);
1564
1565         i40e_rm_ethtype_filter_list(pf);
1566         i40e_rm_tunnel_filter_list(pf);
1567         i40e_rm_fdir_filter_list(pf);
1568
1569         /* Remove all flows */
1570         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1571                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1572                 rte_free(p_flow);
1573         }
1574
1575         /* Remove all Traffic Manager configuration */
1576         i40e_tm_conf_uninit(dev);
1577
1578         return 0;
1579 }
1580
1581 static int
1582 i40e_dev_configure(struct rte_eth_dev *dev)
1583 {
1584         struct i40e_adapter *ad =
1585                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1586         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1589         int i, ret;
1590
1591         ret = i40e_dev_sync_phy_type(hw);
1592         if (ret)
1593                 return ret;
1594
1595         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1596          * bulk allocation or vector Rx preconditions we will reset it.
1597          */
1598         ad->rx_bulk_alloc_allowed = true;
1599         ad->rx_vec_allowed = true;
1600         ad->tx_simple_allowed = true;
1601         ad->tx_vec_allowed = true;
1602
1603         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1604                 ret = i40e_fdir_setup(pf);
1605                 if (ret != I40E_SUCCESS) {
1606                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1607                         return -ENOTSUP;
1608                 }
1609                 ret = i40e_fdir_configure(dev);
1610                 if (ret < 0) {
1611                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1612                         goto err;
1613                 }
1614         } else
1615                 i40e_fdir_teardown(pf);
1616
1617         ret = i40e_dev_init_vlan(dev);
1618         if (ret < 0)
1619                 goto err;
1620
1621         /* VMDQ setup.
1622          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1623          *  RSS setting have different requirements.
1624          *  General PMD driver call sequence are NIC init, configure,
1625          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1626          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1627          *  applicable. So, VMDQ setting has to be done before
1628          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1629          *  For RSS setting, it will try to calculate actual configured RX queue
1630          *  number, which will be available after rx_queue_setup(). dev_start()
1631          *  function is good to place RSS setup.
1632          */
1633         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1634                 ret = i40e_vmdq_setup(dev);
1635                 if (ret)
1636                         goto err;
1637         }
1638
1639         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1640                 ret = i40e_dcb_setup(dev);
1641                 if (ret) {
1642                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1643                         goto err_dcb;
1644                 }
1645         }
1646
1647         TAILQ_INIT(&pf->flow_list);
1648
1649         return 0;
1650
1651 err_dcb:
1652         /* need to release vmdq resource if exists */
1653         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1654                 i40e_vsi_release(pf->vmdq[i].vsi);
1655                 pf->vmdq[i].vsi = NULL;
1656         }
1657         rte_free(pf->vmdq);
1658         pf->vmdq = NULL;
1659 err:
1660         /* need to release fdir resource if exists */
1661         i40e_fdir_teardown(pf);
1662         return ret;
1663 }
1664
1665 void
1666 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1667 {
1668         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1669         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1670         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1671         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1672         uint16_t msix_vect = vsi->msix_intr;
1673         uint16_t i;
1674
1675         for (i = 0; i < vsi->nb_qps; i++) {
1676                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1677                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1678                 rte_wmb();
1679         }
1680
1681         if (vsi->type != I40E_VSI_SRIOV) {
1682                 if (!rte_intr_allow_others(intr_handle)) {
1683                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1684                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1685                         I40E_WRITE_REG(hw,
1686                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1687                                        0);
1688                 } else {
1689                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1690                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1691                         I40E_WRITE_REG(hw,
1692                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1693                                                        msix_vect - 1), 0);
1694                 }
1695         } else {
1696                 uint32_t reg;
1697                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1698                         vsi->user_param + (msix_vect - 1);
1699
1700                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1701                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1702         }
1703         I40E_WRITE_FLUSH(hw);
1704 }
1705
1706 static void
1707 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1708                        int base_queue, int nb_queue,
1709                        uint16_t itr_idx)
1710 {
1711         int i;
1712         uint32_t val;
1713         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1714         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1715
1716         /* Bind all RX queues to allocated MSIX interrupt */
1717         for (i = 0; i < nb_queue; i++) {
1718                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1719                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1720                         ((base_queue + i + 1) <<
1721                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1722                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1723                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1724
1725                 if (i == nb_queue - 1)
1726                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1727                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1728         }
1729
1730         /* Write first RX queue to Link list register as the head element */
1731         if (vsi->type != I40E_VSI_SRIOV) {
1732                 uint16_t interval =
1733                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1734                                                pf->support_multi_driver);
1735
1736                 if (msix_vect == I40E_MISC_VEC_ID) {
1737                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1738                                        (base_queue <<
1739                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1740                                        (0x0 <<
1741                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1742                         I40E_WRITE_REG(hw,
1743                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1744                                        interval);
1745                 } else {
1746                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1747                                        (base_queue <<
1748                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1749                                        (0x0 <<
1750                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1751                         I40E_WRITE_REG(hw,
1752                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1753                                                        msix_vect - 1),
1754                                        interval);
1755                 }
1756         } else {
1757                 uint32_t reg;
1758
1759                 if (msix_vect == I40E_MISC_VEC_ID) {
1760                         I40E_WRITE_REG(hw,
1761                                        I40E_VPINT_LNKLST0(vsi->user_param),
1762                                        (base_queue <<
1763                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1764                                        (0x0 <<
1765                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1766                 } else {
1767                         /* num_msix_vectors_vf needs to minus irq0 */
1768                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1769                                 vsi->user_param + (msix_vect - 1);
1770
1771                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1772                                        (base_queue <<
1773                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1774                                        (0x0 <<
1775                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1776                 }
1777         }
1778
1779         I40E_WRITE_FLUSH(hw);
1780 }
1781
1782 void
1783 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1784 {
1785         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1787         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1788         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1789         uint16_t msix_vect = vsi->msix_intr;
1790         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1791         uint16_t queue_idx = 0;
1792         int record = 0;
1793         int i;
1794
1795         for (i = 0; i < vsi->nb_qps; i++) {
1796                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1797                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1798         }
1799
1800         /* VF bind interrupt */
1801         if (vsi->type == I40E_VSI_SRIOV) {
1802                 __vsi_queues_bind_intr(vsi, msix_vect,
1803                                        vsi->base_queue, vsi->nb_qps,
1804                                        itr_idx);
1805                 return;
1806         }
1807
1808         /* PF & VMDq bind interrupt */
1809         if (rte_intr_dp_is_en(intr_handle)) {
1810                 if (vsi->type == I40E_VSI_MAIN) {
1811                         queue_idx = 0;
1812                         record = 1;
1813                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1814                         struct i40e_vsi *main_vsi =
1815                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1816                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1817                         record = 1;
1818                 }
1819         }
1820
1821         for (i = 0; i < vsi->nb_used_qps; i++) {
1822                 if (nb_msix <= 1) {
1823                         if (!rte_intr_allow_others(intr_handle))
1824                                 /* allow to share MISC_VEC_ID */
1825                                 msix_vect = I40E_MISC_VEC_ID;
1826
1827                         /* no enough msix_vect, map all to one */
1828                         __vsi_queues_bind_intr(vsi, msix_vect,
1829                                                vsi->base_queue + i,
1830                                                vsi->nb_used_qps - i,
1831                                                itr_idx);
1832                         for (; !!record && i < vsi->nb_used_qps; i++)
1833                                 intr_handle->intr_vec[queue_idx + i] =
1834                                         msix_vect;
1835                         break;
1836                 }
1837                 /* 1:1 queue/msix_vect mapping */
1838                 __vsi_queues_bind_intr(vsi, msix_vect,
1839                                        vsi->base_queue + i, 1,
1840                                        itr_idx);
1841                 if (!!record)
1842                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1843
1844                 msix_vect++;
1845                 nb_msix--;
1846         }
1847 }
1848
1849 static void
1850 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1851 {
1852         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1853         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1854         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1855         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1856         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1857         uint16_t msix_intr, i;
1858
1859         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1860                 for (i = 0; i < vsi->nb_msix; i++) {
1861                         msix_intr = vsi->msix_intr + i;
1862                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1863                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1864                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1865                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1866                 }
1867         else
1868                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1869                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1870                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1871                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1872
1873         I40E_WRITE_FLUSH(hw);
1874 }
1875
1876 static void
1877 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1878 {
1879         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1880         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1881         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1882         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1883         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1884         uint16_t msix_intr, i;
1885
1886         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1887                 for (i = 0; i < vsi->nb_msix; i++) {
1888                         msix_intr = vsi->msix_intr + i;
1889                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1890                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1891                 }
1892         else
1893                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1894                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1895
1896         I40E_WRITE_FLUSH(hw);
1897 }
1898
1899 static inline uint8_t
1900 i40e_parse_link_speeds(uint16_t link_speeds)
1901 {
1902         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1903
1904         if (link_speeds & ETH_LINK_SPEED_40G)
1905                 link_speed |= I40E_LINK_SPEED_40GB;
1906         if (link_speeds & ETH_LINK_SPEED_25G)
1907                 link_speed |= I40E_LINK_SPEED_25GB;
1908         if (link_speeds & ETH_LINK_SPEED_20G)
1909                 link_speed |= I40E_LINK_SPEED_20GB;
1910         if (link_speeds & ETH_LINK_SPEED_10G)
1911                 link_speed |= I40E_LINK_SPEED_10GB;
1912         if (link_speeds & ETH_LINK_SPEED_1G)
1913                 link_speed |= I40E_LINK_SPEED_1GB;
1914         if (link_speeds & ETH_LINK_SPEED_100M)
1915                 link_speed |= I40E_LINK_SPEED_100MB;
1916
1917         return link_speed;
1918 }
1919
1920 static int
1921 i40e_phy_conf_link(struct i40e_hw *hw,
1922                    uint8_t abilities,
1923                    uint8_t force_speed,
1924                    bool is_up)
1925 {
1926         enum i40e_status_code status;
1927         struct i40e_aq_get_phy_abilities_resp phy_ab;
1928         struct i40e_aq_set_phy_config phy_conf;
1929         enum i40e_aq_phy_type cnt;
1930         uint32_t phy_type_mask = 0;
1931
1932         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1933                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1934                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1935                         I40E_AQ_PHY_FLAG_LOW_POWER;
1936         const uint8_t advt = I40E_LINK_SPEED_40GB |
1937                         I40E_LINK_SPEED_25GB |
1938                         I40E_LINK_SPEED_10GB |
1939                         I40E_LINK_SPEED_1GB |
1940                         I40E_LINK_SPEED_100MB;
1941         int ret = -ENOTSUP;
1942
1943
1944         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1945                                               NULL);
1946         if (status)
1947                 return ret;
1948
1949         /* If link already up, no need to set up again */
1950         if (is_up && phy_ab.phy_type != 0)
1951                 return I40E_SUCCESS;
1952
1953         memset(&phy_conf, 0, sizeof(phy_conf));
1954
1955         /* bits 0-2 use the values from get_phy_abilities_resp */
1956         abilities &= ~mask;
1957         abilities |= phy_ab.abilities & mask;
1958
1959         /* update ablities and speed */
1960         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1961                 phy_conf.link_speed = advt;
1962         else
1963                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1964
1965         phy_conf.abilities = abilities;
1966
1967
1968
1969         /* To enable link, phy_type mask needs to include each type */
1970         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1971                 phy_type_mask |= 1 << cnt;
1972
1973         /* use get_phy_abilities_resp value for the rest */
1974         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1975         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1976                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1977                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1978         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1979         phy_conf.eee_capability = phy_ab.eee_capability;
1980         phy_conf.eeer = phy_ab.eeer_val;
1981         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1982
1983         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1984                     phy_ab.abilities, phy_ab.link_speed);
1985         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1986                     phy_conf.abilities, phy_conf.link_speed);
1987
1988         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1989         if (status)
1990                 return ret;
1991
1992         return I40E_SUCCESS;
1993 }
1994
1995 static int
1996 i40e_apply_link_speed(struct rte_eth_dev *dev)
1997 {
1998         uint8_t speed;
1999         uint8_t abilities = 0;
2000         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         struct rte_eth_conf *conf = &dev->data->dev_conf;
2002
2003         speed = i40e_parse_link_speeds(conf->link_speeds);
2004         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2005         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2006                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2007         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2008
2009         return i40e_phy_conf_link(hw, abilities, speed, true);
2010 }
2011
2012 static int
2013 i40e_dev_start(struct rte_eth_dev *dev)
2014 {
2015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         struct i40e_vsi *main_vsi = pf->main_vsi;
2018         int ret, i;
2019         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2020         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2021         uint32_t intr_vector = 0;
2022         struct i40e_vsi *vsi;
2023
2024         hw->adapter_stopped = 0;
2025
2026         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2027                 PMD_INIT_LOG(ERR,
2028                 "Invalid link_speeds for port %u, autonegotiation disabled",
2029                               dev->data->port_id);
2030                 return -EINVAL;
2031         }
2032
2033         rte_intr_disable(intr_handle);
2034
2035         if ((rte_intr_cap_multiple(intr_handle) ||
2036              !RTE_ETH_DEV_SRIOV(dev).active) &&
2037             dev->data->dev_conf.intr_conf.rxq != 0) {
2038                 intr_vector = dev->data->nb_rx_queues;
2039                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2040                 if (ret)
2041                         return ret;
2042         }
2043
2044         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2045                 intr_handle->intr_vec =
2046                         rte_zmalloc("intr_vec",
2047                                     dev->data->nb_rx_queues * sizeof(int),
2048                                     0);
2049                 if (!intr_handle->intr_vec) {
2050                         PMD_INIT_LOG(ERR,
2051                                 "Failed to allocate %d rx_queues intr_vec",
2052                                 dev->data->nb_rx_queues);
2053                         return -ENOMEM;
2054                 }
2055         }
2056
2057         /* Initialize VSI */
2058         ret = i40e_dev_rxtx_init(pf);
2059         if (ret != I40E_SUCCESS) {
2060                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2061                 goto err_up;
2062         }
2063
2064         /* Map queues with MSIX interrupt */
2065         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2066                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2067         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2068         i40e_vsi_enable_queues_intr(main_vsi);
2069
2070         /* Map VMDQ VSI queues with MSIX interrupt */
2071         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2072                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2073                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2074                                           I40E_ITR_INDEX_DEFAULT);
2075                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2076         }
2077
2078         /* enable FDIR MSIX interrupt */
2079         if (pf->fdir.fdir_vsi) {
2080                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2081                                           I40E_ITR_INDEX_NONE);
2082                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2083         }
2084
2085         /* Enable all queues which have been configured */
2086         ret = i40e_dev_switch_queues(pf, TRUE);
2087         if (ret != I40E_SUCCESS) {
2088                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2089                 goto err_up;
2090         }
2091
2092         /* Enable receiving broadcast packets */
2093         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2094         if (ret != I40E_SUCCESS)
2095                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2096
2097         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2098                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2099                                                 true, NULL);
2100                 if (ret != I40E_SUCCESS)
2101                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2102         }
2103
2104         /* Enable the VLAN promiscuous mode. */
2105         if (pf->vfs) {
2106                 for (i = 0; i < pf->vf_num; i++) {
2107                         vsi = pf->vfs[i].vsi;
2108                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2109                                                      true, NULL);
2110                 }
2111         }
2112
2113         /* Enable mac loopback mode */
2114         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2115             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2116                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2117                 if (ret != I40E_SUCCESS) {
2118                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2119                         goto err_up;
2120                 }
2121         }
2122
2123         /* Apply link configure */
2124         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2125                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2126                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2127                                 ETH_LINK_SPEED_40G)) {
2128                 PMD_DRV_LOG(ERR, "Invalid link setting");
2129                 goto err_up;
2130         }
2131         ret = i40e_apply_link_speed(dev);
2132         if (I40E_SUCCESS != ret) {
2133                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2134                 goto err_up;
2135         }
2136
2137         if (!rte_intr_allow_others(intr_handle)) {
2138                 rte_intr_callback_unregister(intr_handle,
2139                                              i40e_dev_interrupt_handler,
2140                                              (void *)dev);
2141                 /* configure and enable device interrupt */
2142                 i40e_pf_config_irq0(hw, FALSE);
2143                 i40e_pf_enable_irq0(hw);
2144
2145                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2146                         PMD_INIT_LOG(INFO,
2147                                 "lsc won't enable because of no intr multiplex");
2148         } else {
2149                 ret = i40e_aq_set_phy_int_mask(hw,
2150                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2151                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2152                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2153                 if (ret != I40E_SUCCESS)
2154                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2155
2156                 /* Call get_link_info aq commond to enable/disable LSE */
2157                 i40e_dev_link_update(dev, 0);
2158         }
2159
2160         /* enable uio intr after callback register */
2161         rte_intr_enable(intr_handle);
2162
2163         i40e_filter_restore(pf);
2164
2165         if (pf->tm_conf.root && !pf->tm_conf.committed)
2166                 PMD_DRV_LOG(WARNING,
2167                             "please call hierarchy_commit() "
2168                             "before starting the port");
2169
2170         return I40E_SUCCESS;
2171
2172 err_up:
2173         i40e_dev_switch_queues(pf, FALSE);
2174         i40e_dev_clear_queues(dev);
2175
2176         return ret;
2177 }
2178
2179 static void
2180 i40e_dev_stop(struct rte_eth_dev *dev)
2181 {
2182         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2183         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2184         struct i40e_vsi *main_vsi = pf->main_vsi;
2185         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2186         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2187         int i;
2188
2189         if (hw->adapter_stopped == 1)
2190                 return;
2191         /* Disable all queues */
2192         i40e_dev_switch_queues(pf, FALSE);
2193
2194         /* un-map queues with interrupt registers */
2195         i40e_vsi_disable_queues_intr(main_vsi);
2196         i40e_vsi_queues_unbind_intr(main_vsi);
2197
2198         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2199                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2200                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2201         }
2202
2203         if (pf->fdir.fdir_vsi) {
2204                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2205                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2206         }
2207         /* Clear all queues and release memory */
2208         i40e_dev_clear_queues(dev);
2209
2210         /* Set link down */
2211         i40e_dev_set_link_down(dev);
2212
2213         if (!rte_intr_allow_others(intr_handle))
2214                 /* resume to the default handler */
2215                 rte_intr_callback_register(intr_handle,
2216                                            i40e_dev_interrupt_handler,
2217                                            (void *)dev);
2218
2219         /* Clean datapath event and queue/vec mapping */
2220         rte_intr_efd_disable(intr_handle);
2221         if (intr_handle->intr_vec) {
2222                 rte_free(intr_handle->intr_vec);
2223                 intr_handle->intr_vec = NULL;
2224         }
2225
2226         /* reset hierarchy commit */
2227         pf->tm_conf.committed = false;
2228
2229         hw->adapter_stopped = 1;
2230 }
2231
2232 static void
2233 i40e_dev_close(struct rte_eth_dev *dev)
2234 {
2235         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2238         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2239         struct i40e_mirror_rule *p_mirror;
2240         uint32_t reg;
2241         int i;
2242         int ret;
2243
2244         PMD_INIT_FUNC_TRACE();
2245
2246         i40e_dev_stop(dev);
2247
2248         /* Remove all mirror rules */
2249         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2250                 ret = i40e_aq_del_mirror_rule(hw,
2251                                               pf->main_vsi->veb->seid,
2252                                               p_mirror->rule_type,
2253                                               p_mirror->entries,
2254                                               p_mirror->num_entries,
2255                                               p_mirror->id);
2256                 if (ret < 0)
2257                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2258                                     "status = %d, aq_err = %d.", ret,
2259                                     hw->aq.asq_last_status);
2260
2261                 /* remove mirror software resource anyway */
2262                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2263                 rte_free(p_mirror);
2264                 pf->nb_mirror_rule--;
2265         }
2266
2267         i40e_dev_free_queues(dev);
2268
2269         /* Disable interrupt */
2270         i40e_pf_disable_irq0(hw);
2271         rte_intr_disable(intr_handle);
2272
2273         /* shutdown and destroy the HMC */
2274         i40e_shutdown_lan_hmc(hw);
2275
2276         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2277                 i40e_vsi_release(pf->vmdq[i].vsi);
2278                 pf->vmdq[i].vsi = NULL;
2279         }
2280         rte_free(pf->vmdq);
2281         pf->vmdq = NULL;
2282
2283         /* release all the existing VSIs and VEBs */
2284         i40e_fdir_teardown(pf);
2285         i40e_vsi_release(pf->main_vsi);
2286
2287         /* shutdown the adminq */
2288         i40e_aq_queue_shutdown(hw, true);
2289         i40e_shutdown_adminq(hw);
2290
2291         i40e_res_pool_destroy(&pf->qp_pool);
2292         i40e_res_pool_destroy(&pf->msix_pool);
2293
2294         /* Disable flexible payload in global configuration */
2295         if (!pf->support_multi_driver)
2296                 i40e_flex_payload_reg_set_default(hw);
2297
2298         /* force a PF reset to clean anything leftover */
2299         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2300         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2301                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2302         I40E_WRITE_FLUSH(hw);
2303 }
2304
2305 /*
2306  * Reset PF device only to re-initialize resources in PMD layer
2307  */
2308 static int
2309 i40e_dev_reset(struct rte_eth_dev *dev)
2310 {
2311         int ret;
2312
2313         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2314          * its VF to make them align with it. The detailed notification
2315          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2316          * To avoid unexpected behavior in VF, currently reset of PF with
2317          * SR-IOV activation is not supported. It might be supported later.
2318          */
2319         if (dev->data->sriov.active)
2320                 return -ENOTSUP;
2321
2322         ret = eth_i40e_dev_uninit(dev);
2323         if (ret)
2324                 return ret;
2325
2326         ret = eth_i40e_dev_init(dev);
2327
2328         return ret;
2329 }
2330
2331 static void
2332 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2333 {
2334         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2335         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336         struct i40e_vsi *vsi = pf->main_vsi;
2337         int status;
2338
2339         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2340                                                      true, NULL, true);
2341         if (status != I40E_SUCCESS)
2342                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2343
2344         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2345                                                         TRUE, NULL);
2346         if (status != I40E_SUCCESS)
2347                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2348
2349 }
2350
2351 static void
2352 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2353 {
2354         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356         struct i40e_vsi *vsi = pf->main_vsi;
2357         int status;
2358
2359         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2360                                                      false, NULL, true);
2361         if (status != I40E_SUCCESS)
2362                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2363
2364         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2365                                                         false, NULL);
2366         if (status != I40E_SUCCESS)
2367                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2368 }
2369
2370 static void
2371 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2372 {
2373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375         struct i40e_vsi *vsi = pf->main_vsi;
2376         int ret;
2377
2378         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2379         if (ret != I40E_SUCCESS)
2380                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2381 }
2382
2383 static void
2384 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2385 {
2386         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         struct i40e_vsi *vsi = pf->main_vsi;
2389         int ret;
2390
2391         if (dev->data->promiscuous == 1)
2392                 return; /* must remain in all_multicast mode */
2393
2394         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2395                                 vsi->seid, FALSE, NULL);
2396         if (ret != I40E_SUCCESS)
2397                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2398 }
2399
2400 /*
2401  * Set device link up.
2402  */
2403 static int
2404 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2405 {
2406         /* re-apply link speed setting */
2407         return i40e_apply_link_speed(dev);
2408 }
2409
2410 /*
2411  * Set device link down.
2412  */
2413 static int
2414 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2415 {
2416         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2417         uint8_t abilities = 0;
2418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419
2420         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2421         return i40e_phy_conf_link(hw, abilities, speed, false);
2422 }
2423
2424 static __rte_always_inline void
2425 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2426 {
2427 /* Link status registers and values*/
2428 #define I40E_PRTMAC_LINKSTA             0x001E2420
2429 #define I40E_REG_LINK_UP                0x40000080
2430 #define I40E_PRTMAC_MACC                0x001E24E0
2431 #define I40E_REG_MACC_25GB              0x00020000
2432 #define I40E_REG_SPEED_MASK             0x38000000
2433 #define I40E_REG_SPEED_100MB            0x00000000
2434 #define I40E_REG_SPEED_1GB              0x08000000
2435 #define I40E_REG_SPEED_10GB             0x10000000
2436 #define I40E_REG_SPEED_20GB             0x20000000
2437 #define I40E_REG_SPEED_25_40GB          0x18000000
2438         uint32_t link_speed;
2439         uint32_t reg_val;
2440
2441         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2442         link_speed = reg_val & I40E_REG_SPEED_MASK;
2443         reg_val &= I40E_REG_LINK_UP;
2444         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2445
2446         if (unlikely(link->link_status != 0))
2447                 return;
2448
2449         /* Parse the link status */
2450         switch (link_speed) {
2451         case I40E_REG_SPEED_100MB:
2452                 link->link_speed = ETH_SPEED_NUM_100M;
2453                 break;
2454         case I40E_REG_SPEED_1GB:
2455                 link->link_speed = ETH_SPEED_NUM_1G;
2456                 break;
2457         case I40E_REG_SPEED_10GB:
2458                 link->link_speed = ETH_SPEED_NUM_10G;
2459                 break;
2460         case I40E_REG_SPEED_20GB:
2461                 link->link_speed = ETH_SPEED_NUM_20G;
2462                 break;
2463         case I40E_REG_SPEED_25_40GB:
2464                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2465
2466                 if (reg_val & I40E_REG_MACC_25GB)
2467                         link->link_speed = ETH_SPEED_NUM_25G;
2468                 else
2469                         link->link_speed = ETH_SPEED_NUM_40G;
2470
2471                 break;
2472         default:
2473                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2474                 break;
2475         }
2476 }
2477
2478 static __rte_always_inline void
2479 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2480         bool enable_lse)
2481 {
2482 #define CHECK_INTERVAL             100  /* 100ms */
2483 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2484         uint32_t rep_cnt = MAX_REPEAT_TIME;
2485         struct i40e_link_status link_status;
2486         int status;
2487
2488         memset(&link_status, 0, sizeof(link_status));
2489
2490         do {
2491                 memset(&link_status, 0, sizeof(link_status));
2492
2493                 /* Get link status information from hardware */
2494                 status = i40e_aq_get_link_info(hw, enable_lse,
2495                                                 &link_status, NULL);
2496                 if (unlikely(status != I40E_SUCCESS)) {
2497                         link->link_speed = ETH_SPEED_NUM_100M;
2498                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2499                         PMD_DRV_LOG(ERR, "Failed to get link info");
2500                         return;
2501                 }
2502
2503                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2504                 if (unlikely(link->link_status != 0))
2505                         return;
2506
2507                 rte_delay_ms(CHECK_INTERVAL);
2508         } while (--rep_cnt);
2509
2510         /* Parse the link status */
2511         switch (link_status.link_speed) {
2512         case I40E_LINK_SPEED_100MB:
2513                 link->link_speed = ETH_SPEED_NUM_100M;
2514                 break;
2515         case I40E_LINK_SPEED_1GB:
2516                 link->link_speed = ETH_SPEED_NUM_1G;
2517                 break;
2518         case I40E_LINK_SPEED_10GB:
2519                 link->link_speed = ETH_SPEED_NUM_10G;
2520                 break;
2521         case I40E_LINK_SPEED_20GB:
2522                 link->link_speed = ETH_SPEED_NUM_20G;
2523                 break;
2524         case I40E_LINK_SPEED_25GB:
2525                 link->link_speed = ETH_SPEED_NUM_25G;
2526                 break;
2527         case I40E_LINK_SPEED_40GB:
2528                 link->link_speed = ETH_SPEED_NUM_40G;
2529                 break;
2530         default:
2531                 link->link_speed = ETH_SPEED_NUM_100M;
2532                 break;
2533         }
2534 }
2535
2536 int
2537 i40e_dev_link_update(struct rte_eth_dev *dev,
2538                      int wait_to_complete)
2539 {
2540         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         struct rte_eth_link link;
2542         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2543         int ret;
2544
2545         memset(&link, 0, sizeof(link));
2546
2547         /* i40e uses full duplex only */
2548         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2549         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2550                         ETH_LINK_SPEED_FIXED);
2551
2552         if (!wait_to_complete)
2553                 update_link_no_wait(hw, &link);
2554         else
2555                 update_link_wait(hw, &link, enable_lse);
2556
2557         ret = rte_eth_linkstatus_set(dev, &link);
2558         i40e_notify_all_vfs_link_status(dev);
2559
2560         return ret;
2561 }
2562
2563 /* Get all the statistics of a VSI */
2564 void
2565 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2566 {
2567         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2568         struct i40e_eth_stats *nes = &vsi->eth_stats;
2569         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2570         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2571
2572         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2573                             vsi->offset_loaded, &oes->rx_bytes,
2574                             &nes->rx_bytes);
2575         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2576                             vsi->offset_loaded, &oes->rx_unicast,
2577                             &nes->rx_unicast);
2578         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2579                             vsi->offset_loaded, &oes->rx_multicast,
2580                             &nes->rx_multicast);
2581         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2582                             vsi->offset_loaded, &oes->rx_broadcast,
2583                             &nes->rx_broadcast);
2584         /* exclude CRC bytes */
2585         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2586                 nes->rx_broadcast) * ETHER_CRC_LEN;
2587
2588         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2589                             &oes->rx_discards, &nes->rx_discards);
2590         /* GLV_REPC not supported */
2591         /* GLV_RMPC not supported */
2592         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2593                             &oes->rx_unknown_protocol,
2594                             &nes->rx_unknown_protocol);
2595         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2596                             vsi->offset_loaded, &oes->tx_bytes,
2597                             &nes->tx_bytes);
2598         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2599                             vsi->offset_loaded, &oes->tx_unicast,
2600                             &nes->tx_unicast);
2601         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2602                             vsi->offset_loaded, &oes->tx_multicast,
2603                             &nes->tx_multicast);
2604         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2605                             vsi->offset_loaded,  &oes->tx_broadcast,
2606                             &nes->tx_broadcast);
2607         /* GLV_TDPC not supported */
2608         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2609                             &oes->tx_errors, &nes->tx_errors);
2610         vsi->offset_loaded = true;
2611
2612         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2613                     vsi->vsi_id);
2614         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2615         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2616         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2617         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2618         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2619         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2620                     nes->rx_unknown_protocol);
2621         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2622         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2623         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2624         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2625         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2626         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2627         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2628                     vsi->vsi_id);
2629 }
2630
2631 static void
2632 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2633 {
2634         unsigned int i;
2635         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2636         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2637
2638         /* Get rx/tx bytes of internal transfer packets */
2639         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2640                         I40E_GLV_GORCL(hw->port),
2641                         pf->offset_loaded,
2642                         &pf->internal_stats_offset.rx_bytes,
2643                         &pf->internal_stats.rx_bytes);
2644
2645         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2646                         I40E_GLV_GOTCL(hw->port),
2647                         pf->offset_loaded,
2648                         &pf->internal_stats_offset.tx_bytes,
2649                         &pf->internal_stats.tx_bytes);
2650         /* Get total internal rx packet count */
2651         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2652                             I40E_GLV_UPRCL(hw->port),
2653                             pf->offset_loaded,
2654                             &pf->internal_stats_offset.rx_unicast,
2655                             &pf->internal_stats.rx_unicast);
2656         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2657                             I40E_GLV_MPRCL(hw->port),
2658                             pf->offset_loaded,
2659                             &pf->internal_stats_offset.rx_multicast,
2660                             &pf->internal_stats.rx_multicast);
2661         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2662                             I40E_GLV_BPRCL(hw->port),
2663                             pf->offset_loaded,
2664                             &pf->internal_stats_offset.rx_broadcast,
2665                             &pf->internal_stats.rx_broadcast);
2666         /* Get total internal tx packet count */
2667         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2668                             I40E_GLV_UPTCL(hw->port),
2669                             pf->offset_loaded,
2670                             &pf->internal_stats_offset.tx_unicast,
2671                             &pf->internal_stats.tx_unicast);
2672         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2673                             I40E_GLV_MPTCL(hw->port),
2674                             pf->offset_loaded,
2675                             &pf->internal_stats_offset.tx_multicast,
2676                             &pf->internal_stats.tx_multicast);
2677         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2678                             I40E_GLV_BPTCL(hw->port),
2679                             pf->offset_loaded,
2680                             &pf->internal_stats_offset.tx_broadcast,
2681                             &pf->internal_stats.tx_broadcast);
2682
2683         /* exclude CRC size */
2684         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2685                 pf->internal_stats.rx_multicast +
2686                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2687
2688         /* Get statistics of struct i40e_eth_stats */
2689         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2690                             I40E_GLPRT_GORCL(hw->port),
2691                             pf->offset_loaded, &os->eth.rx_bytes,
2692                             &ns->eth.rx_bytes);
2693         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2694                             I40E_GLPRT_UPRCL(hw->port),
2695                             pf->offset_loaded, &os->eth.rx_unicast,
2696                             &ns->eth.rx_unicast);
2697         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2698                             I40E_GLPRT_MPRCL(hw->port),
2699                             pf->offset_loaded, &os->eth.rx_multicast,
2700                             &ns->eth.rx_multicast);
2701         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2702                             I40E_GLPRT_BPRCL(hw->port),
2703                             pf->offset_loaded, &os->eth.rx_broadcast,
2704                             &ns->eth.rx_broadcast);
2705         /* Workaround: CRC size should not be included in byte statistics,
2706          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2707          */
2708         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2709                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2710
2711         /* exclude internal rx bytes
2712          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2713          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2714          * value.
2715          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2716          */
2717         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2718                 ns->eth.rx_bytes = 0;
2719         else
2720                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2721
2722         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2723                 ns->eth.rx_unicast = 0;
2724         else
2725                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2726
2727         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2728                 ns->eth.rx_multicast = 0;
2729         else
2730                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2731
2732         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2733                 ns->eth.rx_broadcast = 0;
2734         else
2735                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2736
2737         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2738                             pf->offset_loaded, &os->eth.rx_discards,
2739                             &ns->eth.rx_discards);
2740         /* GLPRT_REPC not supported */
2741         /* GLPRT_RMPC not supported */
2742         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2743                             pf->offset_loaded,
2744                             &os->eth.rx_unknown_protocol,
2745                             &ns->eth.rx_unknown_protocol);
2746         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2747                             I40E_GLPRT_GOTCL(hw->port),
2748                             pf->offset_loaded, &os->eth.tx_bytes,
2749                             &ns->eth.tx_bytes);
2750         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2751                             I40E_GLPRT_UPTCL(hw->port),
2752                             pf->offset_loaded, &os->eth.tx_unicast,
2753                             &ns->eth.tx_unicast);
2754         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2755                             I40E_GLPRT_MPTCL(hw->port),
2756                             pf->offset_loaded, &os->eth.tx_multicast,
2757                             &ns->eth.tx_multicast);
2758         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2759                             I40E_GLPRT_BPTCL(hw->port),
2760                             pf->offset_loaded, &os->eth.tx_broadcast,
2761                             &ns->eth.tx_broadcast);
2762         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2763                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2764
2765         /* exclude internal tx bytes
2766          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2767          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2768          * value.
2769          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2770          */
2771         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2772                 ns->eth.tx_bytes = 0;
2773         else
2774                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2775
2776         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2777                 ns->eth.tx_unicast = 0;
2778         else
2779                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2780
2781         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2782                 ns->eth.tx_multicast = 0;
2783         else
2784                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2785
2786         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2787                 ns->eth.tx_broadcast = 0;
2788         else
2789                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2790
2791         /* GLPRT_TEPC not supported */
2792
2793         /* additional port specific stats */
2794         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2795                             pf->offset_loaded, &os->tx_dropped_link_down,
2796                             &ns->tx_dropped_link_down);
2797         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2798                             pf->offset_loaded, &os->crc_errors,
2799                             &ns->crc_errors);
2800         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2801                             pf->offset_loaded, &os->illegal_bytes,
2802                             &ns->illegal_bytes);
2803         /* GLPRT_ERRBC not supported */
2804         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2805                             pf->offset_loaded, &os->mac_local_faults,
2806                             &ns->mac_local_faults);
2807         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2808                             pf->offset_loaded, &os->mac_remote_faults,
2809                             &ns->mac_remote_faults);
2810         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2811                             pf->offset_loaded, &os->rx_length_errors,
2812                             &ns->rx_length_errors);
2813         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2814                             pf->offset_loaded, &os->link_xon_rx,
2815                             &ns->link_xon_rx);
2816         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2817                             pf->offset_loaded, &os->link_xoff_rx,
2818                             &ns->link_xoff_rx);
2819         for (i = 0; i < 8; i++) {
2820                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2821                                     pf->offset_loaded,
2822                                     &os->priority_xon_rx[i],
2823                                     &ns->priority_xon_rx[i]);
2824                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2825                                     pf->offset_loaded,
2826                                     &os->priority_xoff_rx[i],
2827                                     &ns->priority_xoff_rx[i]);
2828         }
2829         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2830                             pf->offset_loaded, &os->link_xon_tx,
2831                             &ns->link_xon_tx);
2832         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2833                             pf->offset_loaded, &os->link_xoff_tx,
2834                             &ns->link_xoff_tx);
2835         for (i = 0; i < 8; i++) {
2836                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2837                                     pf->offset_loaded,
2838                                     &os->priority_xon_tx[i],
2839                                     &ns->priority_xon_tx[i]);
2840                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2841                                     pf->offset_loaded,
2842                                     &os->priority_xoff_tx[i],
2843                                     &ns->priority_xoff_tx[i]);
2844                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2845                                     pf->offset_loaded,
2846                                     &os->priority_xon_2_xoff[i],
2847                                     &ns->priority_xon_2_xoff[i]);
2848         }
2849         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2850                             I40E_GLPRT_PRC64L(hw->port),
2851                             pf->offset_loaded, &os->rx_size_64,
2852                             &ns->rx_size_64);
2853         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2854                             I40E_GLPRT_PRC127L(hw->port),
2855                             pf->offset_loaded, &os->rx_size_127,
2856                             &ns->rx_size_127);
2857         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2858                             I40E_GLPRT_PRC255L(hw->port),
2859                             pf->offset_loaded, &os->rx_size_255,
2860                             &ns->rx_size_255);
2861         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2862                             I40E_GLPRT_PRC511L(hw->port),
2863                             pf->offset_loaded, &os->rx_size_511,
2864                             &ns->rx_size_511);
2865         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2866                             I40E_GLPRT_PRC1023L(hw->port),
2867                             pf->offset_loaded, &os->rx_size_1023,
2868                             &ns->rx_size_1023);
2869         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2870                             I40E_GLPRT_PRC1522L(hw->port),
2871                             pf->offset_loaded, &os->rx_size_1522,
2872                             &ns->rx_size_1522);
2873         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2874                             I40E_GLPRT_PRC9522L(hw->port),
2875                             pf->offset_loaded, &os->rx_size_big,
2876                             &ns->rx_size_big);
2877         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2878                             pf->offset_loaded, &os->rx_undersize,
2879                             &ns->rx_undersize);
2880         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2881                             pf->offset_loaded, &os->rx_fragments,
2882                             &ns->rx_fragments);
2883         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2884                             pf->offset_loaded, &os->rx_oversize,
2885                             &ns->rx_oversize);
2886         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2887                             pf->offset_loaded, &os->rx_jabber,
2888                             &ns->rx_jabber);
2889         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2890                             I40E_GLPRT_PTC64L(hw->port),
2891                             pf->offset_loaded, &os->tx_size_64,
2892                             &ns->tx_size_64);
2893         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2894                             I40E_GLPRT_PTC127L(hw->port),
2895                             pf->offset_loaded, &os->tx_size_127,
2896                             &ns->tx_size_127);
2897         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2898                             I40E_GLPRT_PTC255L(hw->port),
2899                             pf->offset_loaded, &os->tx_size_255,
2900                             &ns->tx_size_255);
2901         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2902                             I40E_GLPRT_PTC511L(hw->port),
2903                             pf->offset_loaded, &os->tx_size_511,
2904                             &ns->tx_size_511);
2905         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2906                             I40E_GLPRT_PTC1023L(hw->port),
2907                             pf->offset_loaded, &os->tx_size_1023,
2908                             &ns->tx_size_1023);
2909         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2910                             I40E_GLPRT_PTC1522L(hw->port),
2911                             pf->offset_loaded, &os->tx_size_1522,
2912                             &ns->tx_size_1522);
2913         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2914                             I40E_GLPRT_PTC9522L(hw->port),
2915                             pf->offset_loaded, &os->tx_size_big,
2916                             &ns->tx_size_big);
2917         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2918                            pf->offset_loaded,
2919                            &os->fd_sb_match, &ns->fd_sb_match);
2920         /* GLPRT_MSPDC not supported */
2921         /* GLPRT_XEC not supported */
2922
2923         pf->offset_loaded = true;
2924
2925         if (pf->main_vsi)
2926                 i40e_update_vsi_stats(pf->main_vsi);
2927 }
2928
2929 /* Get all statistics of a port */
2930 static int
2931 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2932 {
2933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2936         unsigned i;
2937
2938         /* call read registers - updates values, now write them to struct */
2939         i40e_read_stats_registers(pf, hw);
2940
2941         stats->ipackets = ns->eth.rx_unicast +
2942                         ns->eth.rx_multicast +
2943                         ns->eth.rx_broadcast -
2944                         ns->eth.rx_discards -
2945                         pf->main_vsi->eth_stats.rx_discards;
2946         stats->opackets = ns->eth.tx_unicast +
2947                         ns->eth.tx_multicast +
2948                         ns->eth.tx_broadcast;
2949         stats->ibytes   = ns->eth.rx_bytes;
2950         stats->obytes   = ns->eth.tx_bytes;
2951         stats->oerrors  = ns->eth.tx_errors +
2952                         pf->main_vsi->eth_stats.tx_errors;
2953
2954         /* Rx Errors */
2955         stats->imissed  = ns->eth.rx_discards +
2956                         pf->main_vsi->eth_stats.rx_discards;
2957         stats->ierrors  = ns->crc_errors +
2958                         ns->rx_length_errors + ns->rx_undersize +
2959                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2960
2961         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2962         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2963         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2964         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2965         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2966         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2967         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2968                     ns->eth.rx_unknown_protocol);
2969         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2970         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2971         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2972         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2973         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2974         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2975
2976         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2977                     ns->tx_dropped_link_down);
2978         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2979         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2980                     ns->illegal_bytes);
2981         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2982         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2983                     ns->mac_local_faults);
2984         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2985                     ns->mac_remote_faults);
2986         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2987                     ns->rx_length_errors);
2988         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2989         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2990         for (i = 0; i < 8; i++) {
2991                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2992                                 i, ns->priority_xon_rx[i]);
2993                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2994                                 i, ns->priority_xoff_rx[i]);
2995         }
2996         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2997         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2998         for (i = 0; i < 8; i++) {
2999                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3000                                 i, ns->priority_xon_tx[i]);
3001                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3002                                 i, ns->priority_xoff_tx[i]);
3003                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3004                                 i, ns->priority_xon_2_xoff[i]);
3005         }
3006         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3007         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3008         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3009         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3010         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3011         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3012         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3013         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3014         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3015         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3016         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3017         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3018         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3019         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3020         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3021         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3022         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3023         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3024         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3025                         ns->mac_short_packet_dropped);
3026         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3027                     ns->checksum_error);
3028         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3029         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3030         return 0;
3031 }
3032
3033 /* Reset the statistics */
3034 static void
3035 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3036 {
3037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039
3040         /* Mark PF and VSI stats to update the offset, aka "reset" */
3041         pf->offset_loaded = false;
3042         if (pf->main_vsi)
3043                 pf->main_vsi->offset_loaded = false;
3044
3045         /* read the stats, reading current register values into offset */
3046         i40e_read_stats_registers(pf, hw);
3047 }
3048
3049 static uint32_t
3050 i40e_xstats_calc_num(void)
3051 {
3052         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3053                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3054                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3055 }
3056
3057 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3058                                      struct rte_eth_xstat_name *xstats_names,
3059                                      __rte_unused unsigned limit)
3060 {
3061         unsigned count = 0;
3062         unsigned i, prio;
3063
3064         if (xstats_names == NULL)
3065                 return i40e_xstats_calc_num();
3066
3067         /* Note: limit checked in rte_eth_xstats_names() */
3068
3069         /* Get stats from i40e_eth_stats struct */
3070         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3071                 snprintf(xstats_names[count].name,
3072                          sizeof(xstats_names[count].name),
3073                          "%s", rte_i40e_stats_strings[i].name);
3074                 count++;
3075         }
3076
3077         /* Get individiual stats from i40e_hw_port struct */
3078         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3079                 snprintf(xstats_names[count].name,
3080                         sizeof(xstats_names[count].name),
3081                          "%s", rte_i40e_hw_port_strings[i].name);
3082                 count++;
3083         }
3084
3085         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3086                 for (prio = 0; prio < 8; prio++) {
3087                         snprintf(xstats_names[count].name,
3088                                  sizeof(xstats_names[count].name),
3089                                  "rx_priority%u_%s", prio,
3090                                  rte_i40e_rxq_prio_strings[i].name);
3091                         count++;
3092                 }
3093         }
3094
3095         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3096                 for (prio = 0; prio < 8; prio++) {
3097                         snprintf(xstats_names[count].name,
3098                                  sizeof(xstats_names[count].name),
3099                                  "tx_priority%u_%s", prio,
3100                                  rte_i40e_txq_prio_strings[i].name);
3101                         count++;
3102                 }
3103         }
3104         return count;
3105 }
3106
3107 static int
3108 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3109                     unsigned n)
3110 {
3111         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3112         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3113         unsigned i, count, prio;
3114         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3115
3116         count = i40e_xstats_calc_num();
3117         if (n < count)
3118                 return count;
3119
3120         i40e_read_stats_registers(pf, hw);
3121
3122         if (xstats == NULL)
3123                 return 0;
3124
3125         count = 0;
3126
3127         /* Get stats from i40e_eth_stats struct */
3128         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3129                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3130                         rte_i40e_stats_strings[i].offset);
3131                 xstats[count].id = count;
3132                 count++;
3133         }
3134
3135         /* Get individiual stats from i40e_hw_port struct */
3136         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3137                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3138                         rte_i40e_hw_port_strings[i].offset);
3139                 xstats[count].id = count;
3140                 count++;
3141         }
3142
3143         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3144                 for (prio = 0; prio < 8; prio++) {
3145                         xstats[count].value =
3146                                 *(uint64_t *)(((char *)hw_stats) +
3147                                 rte_i40e_rxq_prio_strings[i].offset +
3148                                 (sizeof(uint64_t) * prio));
3149                         xstats[count].id = count;
3150                         count++;
3151                 }
3152         }
3153
3154         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3155                 for (prio = 0; prio < 8; prio++) {
3156                         xstats[count].value =
3157                                 *(uint64_t *)(((char *)hw_stats) +
3158                                 rte_i40e_txq_prio_strings[i].offset +
3159                                 (sizeof(uint64_t) * prio));
3160                         xstats[count].id = count;
3161                         count++;
3162                 }
3163         }
3164
3165         return count;
3166 }
3167
3168 static int
3169 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3170                                  __rte_unused uint16_t queue_id,
3171                                  __rte_unused uint8_t stat_idx,
3172                                  __rte_unused uint8_t is_rx)
3173 {
3174         PMD_INIT_FUNC_TRACE();
3175
3176         return -ENOSYS;
3177 }
3178
3179 static int
3180 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3181 {
3182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183         u32 full_ver;
3184         u8 ver, patch;
3185         u16 build;
3186         int ret;
3187
3188         full_ver = hw->nvm.oem_ver;
3189         ver = (u8)(full_ver >> 24);
3190         build = (u16)((full_ver >> 8) & 0xffff);
3191         patch = (u8)(full_ver & 0xff);
3192
3193         ret = snprintf(fw_version, fw_size,
3194                  "%d.%d%d 0x%08x %d.%d.%d",
3195                  ((hw->nvm.version >> 12) & 0xf),
3196                  ((hw->nvm.version >> 4) & 0xff),
3197                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3198                  ver, build, patch);
3199
3200         ret += 1; /* add the size of '\0' */
3201         if (fw_size < (u32)ret)
3202                 return ret;
3203         else
3204                 return 0;
3205 }
3206
3207 static void
3208 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3209 {
3210         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212         struct i40e_vsi *vsi = pf->main_vsi;
3213         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3214
3215         dev_info->max_rx_queues = vsi->nb_qps;
3216         dev_info->max_tx_queues = vsi->nb_qps;
3217         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3218         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3219         dev_info->max_mac_addrs = vsi->max_macaddrs;
3220         dev_info->max_vfs = pci_dev->max_vfs;
3221         dev_info->rx_queue_offload_capa = 0;
3222         dev_info->rx_offload_capa =
3223                 DEV_RX_OFFLOAD_VLAN_STRIP |
3224                 DEV_RX_OFFLOAD_QINQ_STRIP |
3225                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3226                 DEV_RX_OFFLOAD_UDP_CKSUM |
3227                 DEV_RX_OFFLOAD_TCP_CKSUM |
3228                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3229                 DEV_RX_OFFLOAD_CRC_STRIP |
3230                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3231                 DEV_RX_OFFLOAD_VLAN_FILTER;
3232
3233         dev_info->tx_queue_offload_capa = 0;
3234         dev_info->tx_offload_capa =
3235                 DEV_TX_OFFLOAD_VLAN_INSERT |
3236                 DEV_TX_OFFLOAD_QINQ_INSERT |
3237                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3238                 DEV_TX_OFFLOAD_UDP_CKSUM |
3239                 DEV_TX_OFFLOAD_TCP_CKSUM |
3240                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3241                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3242                 DEV_TX_OFFLOAD_TCP_TSO |
3243                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3244                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3245                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3246                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3247         dev_info->dev_capa =
3248                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3249                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3250
3251         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3252                                                 sizeof(uint32_t);
3253         dev_info->reta_size = pf->hash_lut_size;
3254         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3255
3256         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3257                 .rx_thresh = {
3258                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3259                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3260                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3261                 },
3262                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3263                 .rx_drop_en = 0,
3264                 .offloads = 0,
3265         };
3266
3267         dev_info->default_txconf = (struct rte_eth_txconf) {
3268                 .tx_thresh = {
3269                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3270                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3271                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3272                 },
3273                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3274                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3275                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3276                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3277         };
3278
3279         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3280                 .nb_max = I40E_MAX_RING_DESC,
3281                 .nb_min = I40E_MIN_RING_DESC,
3282                 .nb_align = I40E_ALIGN_RING_DESC,
3283         };
3284
3285         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3286                 .nb_max = I40E_MAX_RING_DESC,
3287                 .nb_min = I40E_MIN_RING_DESC,
3288                 .nb_align = I40E_ALIGN_RING_DESC,
3289                 .nb_seg_max = I40E_TX_MAX_SEG,
3290                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3291         };
3292
3293         if (pf->flags & I40E_FLAG_VMDQ) {
3294                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3295                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3296                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3297                                                 pf->max_nb_vmdq_vsi;
3298                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3299                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3300                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3301         }
3302
3303         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3304                 /* For XL710 */
3305                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3306                 dev_info->default_rxportconf.nb_queues = 2;
3307                 dev_info->default_txportconf.nb_queues = 2;
3308                 if (dev->data->nb_rx_queues == 1)
3309                         dev_info->default_rxportconf.ring_size = 2048;
3310                 else
3311                         dev_info->default_rxportconf.ring_size = 1024;
3312                 if (dev->data->nb_tx_queues == 1)
3313                         dev_info->default_txportconf.ring_size = 1024;
3314                 else
3315                         dev_info->default_txportconf.ring_size = 512;
3316
3317         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3318                 /* For XXV710 */
3319                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3320                 dev_info->default_rxportconf.nb_queues = 1;
3321                 dev_info->default_txportconf.nb_queues = 1;
3322                 dev_info->default_rxportconf.ring_size = 256;
3323                 dev_info->default_txportconf.ring_size = 256;
3324         } else {
3325                 /* For X710 */
3326                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3327                 dev_info->default_rxportconf.nb_queues = 1;
3328                 dev_info->default_txportconf.nb_queues = 1;
3329                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3330                         dev_info->default_rxportconf.ring_size = 512;
3331                         dev_info->default_txportconf.ring_size = 256;
3332                 } else {
3333                         dev_info->default_rxportconf.ring_size = 256;
3334                         dev_info->default_txportconf.ring_size = 256;
3335                 }
3336         }
3337         dev_info->default_rxportconf.burst_size = 32;
3338         dev_info->default_txportconf.burst_size = 32;
3339 }
3340
3341 static int
3342 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3343 {
3344         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3345         struct i40e_vsi *vsi = pf->main_vsi;
3346         PMD_INIT_FUNC_TRACE();
3347
3348         if (on)
3349                 return i40e_vsi_add_vlan(vsi, vlan_id);
3350         else
3351                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3352 }
3353
3354 static int
3355 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3356                                 enum rte_vlan_type vlan_type,
3357                                 uint16_t tpid, int qinq)
3358 {
3359         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360         uint64_t reg_r = 0;
3361         uint64_t reg_w = 0;
3362         uint16_t reg_id = 3;
3363         int ret;
3364
3365         if (qinq) {
3366                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3367                         reg_id = 2;
3368         }
3369
3370         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3371                                           &reg_r, NULL);
3372         if (ret != I40E_SUCCESS) {
3373                 PMD_DRV_LOG(ERR,
3374                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3375                            reg_id);
3376                 return -EIO;
3377         }
3378         PMD_DRV_LOG(DEBUG,
3379                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3380                     reg_id, reg_r);
3381
3382         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3383         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3384         if (reg_r == reg_w) {
3385                 PMD_DRV_LOG(DEBUG, "No need to write");
3386                 return 0;
3387         }
3388
3389         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3390                                            reg_w, NULL);
3391         if (ret != I40E_SUCCESS) {
3392                 PMD_DRV_LOG(ERR,
3393                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3394                             reg_id);
3395                 return -EIO;
3396         }
3397         PMD_DRV_LOG(DEBUG,
3398                     "Global register 0x%08x is changed with value 0x%08x",
3399                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3400
3401         return 0;
3402 }
3403
3404 static int
3405 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3406                    enum rte_vlan_type vlan_type,
3407                    uint16_t tpid)
3408 {
3409         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3411         int qinq = dev->data->dev_conf.rxmode.offloads &
3412                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3413         int ret = 0;
3414
3415         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3416              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3417             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3418                 PMD_DRV_LOG(ERR,
3419                             "Unsupported vlan type.");
3420                 return -EINVAL;
3421         }
3422
3423         if (pf->support_multi_driver) {
3424                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3425                 return -ENOTSUP;
3426         }
3427
3428         /* 802.1ad frames ability is added in NVM API 1.7*/
3429         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3430                 if (qinq) {
3431                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3432                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3433                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3434                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3435                 } else {
3436                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3437                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3438                 }
3439                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3440                 if (ret != I40E_SUCCESS) {
3441                         PMD_DRV_LOG(ERR,
3442                                     "Set switch config failed aq_err: %d",
3443                                     hw->aq.asq_last_status);
3444                         ret = -EIO;
3445                 }
3446         } else
3447                 /* If NVM API < 1.7, keep the register setting */
3448                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3449                                                       tpid, qinq);
3450         i40e_global_cfg_warning(I40E_WARNING_TPID);
3451
3452         return ret;
3453 }
3454
3455 static int
3456 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3457 {
3458         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3459         struct i40e_vsi *vsi = pf->main_vsi;
3460         struct rte_eth_rxmode *rxmode;
3461
3462         rxmode = &dev->data->dev_conf.rxmode;
3463         if (mask & ETH_VLAN_FILTER_MASK) {
3464                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3465                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3466                 else
3467                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3468         }
3469
3470         if (mask & ETH_VLAN_STRIP_MASK) {
3471                 /* Enable or disable VLAN stripping */
3472                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3473                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3474                 else
3475                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3476         }
3477
3478         if (mask & ETH_VLAN_EXTEND_MASK) {
3479                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3480                         i40e_vsi_config_double_vlan(vsi, TRUE);
3481                         /* Set global registers with default ethertype. */
3482                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3483                                            ETHER_TYPE_VLAN);
3484                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3485                                            ETHER_TYPE_VLAN);
3486                 }
3487                 else
3488                         i40e_vsi_config_double_vlan(vsi, FALSE);
3489         }
3490
3491         return 0;
3492 }
3493
3494 static void
3495 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3496                           __rte_unused uint16_t queue,
3497                           __rte_unused int on)
3498 {
3499         PMD_INIT_FUNC_TRACE();
3500 }
3501
3502 static int
3503 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3504 {
3505         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3506         struct i40e_vsi *vsi = pf->main_vsi;
3507         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3508         struct i40e_vsi_vlan_pvid_info info;
3509
3510         memset(&info, 0, sizeof(info));
3511         info.on = on;
3512         if (info.on)
3513                 info.config.pvid = pvid;
3514         else {
3515                 info.config.reject.tagged =
3516                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3517                 info.config.reject.untagged =
3518                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3519         }
3520
3521         return i40e_vsi_vlan_pvid_set(vsi, &info);
3522 }
3523
3524 static int
3525 i40e_dev_led_on(struct rte_eth_dev *dev)
3526 {
3527         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3528         uint32_t mode = i40e_led_get(hw);
3529
3530         if (mode == 0)
3531                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3532
3533         return 0;
3534 }
3535
3536 static int
3537 i40e_dev_led_off(struct rte_eth_dev *dev)
3538 {
3539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3540         uint32_t mode = i40e_led_get(hw);
3541
3542         if (mode != 0)
3543                 i40e_led_set(hw, 0, false);
3544
3545         return 0;
3546 }
3547
3548 static int
3549 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3550 {
3551         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3552         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3553
3554         fc_conf->pause_time = pf->fc_conf.pause_time;
3555
3556         /* read out from register, in case they are modified by other port */
3557         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3558                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3559         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3560                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3561
3562         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3563         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3564
3565          /* Return current mode according to actual setting*/
3566         switch (hw->fc.current_mode) {
3567         case I40E_FC_FULL:
3568                 fc_conf->mode = RTE_FC_FULL;
3569                 break;
3570         case I40E_FC_TX_PAUSE:
3571                 fc_conf->mode = RTE_FC_TX_PAUSE;
3572                 break;
3573         case I40E_FC_RX_PAUSE:
3574                 fc_conf->mode = RTE_FC_RX_PAUSE;
3575                 break;
3576         case I40E_FC_NONE:
3577         default:
3578                 fc_conf->mode = RTE_FC_NONE;
3579         };
3580
3581         return 0;
3582 }
3583
3584 static int
3585 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3586 {
3587         uint32_t mflcn_reg, fctrl_reg, reg;
3588         uint32_t max_high_water;
3589         uint8_t i, aq_failure;
3590         int err;
3591         struct i40e_hw *hw;
3592         struct i40e_pf *pf;
3593         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3594                 [RTE_FC_NONE] = I40E_FC_NONE,
3595                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3596                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3597                 [RTE_FC_FULL] = I40E_FC_FULL
3598         };
3599
3600         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3601
3602         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3603         if ((fc_conf->high_water > max_high_water) ||
3604                         (fc_conf->high_water < fc_conf->low_water)) {
3605                 PMD_INIT_LOG(ERR,
3606                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3607                         max_high_water);
3608                 return -EINVAL;
3609         }
3610
3611         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3613         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3614
3615         pf->fc_conf.pause_time = fc_conf->pause_time;
3616         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3617         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3618
3619         PMD_INIT_FUNC_TRACE();
3620
3621         /* All the link flow control related enable/disable register
3622          * configuration is handle by the F/W
3623          */
3624         err = i40e_set_fc(hw, &aq_failure, true);
3625         if (err < 0)
3626                 return -ENOSYS;
3627
3628         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3629                 /* Configure flow control refresh threshold,
3630                  * the value for stat_tx_pause_refresh_timer[8]
3631                  * is used for global pause operation.
3632                  */
3633
3634                 I40E_WRITE_REG(hw,
3635                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3636                                pf->fc_conf.pause_time);
3637
3638                 /* configure the timer value included in transmitted pause
3639                  * frame,
3640                  * the value for stat_tx_pause_quanta[8] is used for global
3641                  * pause operation
3642                  */
3643                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3644                                pf->fc_conf.pause_time);
3645
3646                 fctrl_reg = I40E_READ_REG(hw,
3647                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3648
3649                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3650                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3651                 else
3652                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3653
3654                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3655                                fctrl_reg);
3656         } else {
3657                 /* Configure pause time (2 TCs per register) */
3658                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3659                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3660                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3661
3662                 /* Configure flow control refresh threshold value */
3663                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3664                                pf->fc_conf.pause_time / 2);
3665
3666                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3667
3668                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3669                  *depending on configuration
3670                  */
3671                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3672                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3673                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3674                 } else {
3675                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3676                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3677                 }
3678
3679                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3680         }
3681
3682         if (!pf->support_multi_driver) {
3683                 /* config water marker both based on the packets and bytes */
3684                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3685                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3686                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3687                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3688                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3689                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3690                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3691                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3692                                   << I40E_KILOSHIFT);
3693                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3694                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3695                                    << I40E_KILOSHIFT);
3696                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3697         } else {
3698                 PMD_DRV_LOG(ERR,
3699                             "Water marker configuration is not supported.");
3700         }
3701
3702         I40E_WRITE_FLUSH(hw);
3703
3704         return 0;
3705 }
3706
3707 static int
3708 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3709                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3710 {
3711         PMD_INIT_FUNC_TRACE();
3712
3713         return -ENOSYS;
3714 }
3715
3716 /* Add a MAC address, and update filters */
3717 static int
3718 i40e_macaddr_add(struct rte_eth_dev *dev,
3719                  struct ether_addr *mac_addr,
3720                  __rte_unused uint32_t index,
3721                  uint32_t pool)
3722 {
3723         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3724         struct i40e_mac_filter_info mac_filter;
3725         struct i40e_vsi *vsi;
3726         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3727         int ret;
3728
3729         /* If VMDQ not enabled or configured, return */
3730         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3731                           !pf->nb_cfg_vmdq_vsi)) {
3732                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3733                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3734                         pool);
3735                 return -ENOTSUP;
3736         }
3737
3738         if (pool > pf->nb_cfg_vmdq_vsi) {
3739                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3740                                 pool, pf->nb_cfg_vmdq_vsi);
3741                 return -EINVAL;
3742         }
3743
3744         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3745         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3746                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3747         else
3748                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3749
3750         if (pool == 0)
3751                 vsi = pf->main_vsi;
3752         else
3753                 vsi = pf->vmdq[pool - 1].vsi;
3754
3755         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3756         if (ret != I40E_SUCCESS) {
3757                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3758                 return -ENODEV;
3759         }
3760         return 0;
3761 }
3762
3763 /* Remove a MAC address, and update filters */
3764 static void
3765 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3766 {
3767         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3768         struct i40e_vsi *vsi;
3769         struct rte_eth_dev_data *data = dev->data;
3770         struct ether_addr *macaddr;
3771         int ret;
3772         uint32_t i;
3773         uint64_t pool_sel;
3774
3775         macaddr = &(data->mac_addrs[index]);
3776
3777         pool_sel = dev->data->mac_pool_sel[index];
3778
3779         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3780                 if (pool_sel & (1ULL << i)) {
3781                         if (i == 0)
3782                                 vsi = pf->main_vsi;
3783                         else {
3784                                 /* No VMDQ pool enabled or configured */
3785                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3786                                         (i > pf->nb_cfg_vmdq_vsi)) {
3787                                         PMD_DRV_LOG(ERR,
3788                                                 "No VMDQ pool enabled/configured");
3789                                         return;
3790                                 }
3791                                 vsi = pf->vmdq[i - 1].vsi;
3792                         }
3793                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3794
3795                         if (ret) {
3796                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3797                                 return;
3798                         }
3799                 }
3800         }
3801 }
3802
3803 /* Set perfect match or hash match of MAC and VLAN for a VF */
3804 static int
3805 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3806                  struct rte_eth_mac_filter *filter,
3807                  bool add)
3808 {
3809         struct i40e_hw *hw;
3810         struct i40e_mac_filter_info mac_filter;
3811         struct ether_addr old_mac;
3812         struct ether_addr *new_mac;
3813         struct i40e_pf_vf *vf = NULL;
3814         uint16_t vf_id;
3815         int ret;
3816
3817         if (pf == NULL) {
3818                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3819                 return -EINVAL;
3820         }
3821         hw = I40E_PF_TO_HW(pf);
3822
3823         if (filter == NULL) {
3824                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3825                 return -EINVAL;
3826         }
3827
3828         new_mac = &filter->mac_addr;
3829
3830         if (is_zero_ether_addr(new_mac)) {
3831                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3832                 return -EINVAL;
3833         }
3834
3835         vf_id = filter->dst_id;
3836
3837         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3838                 PMD_DRV_LOG(ERR, "Invalid argument.");
3839                 return -EINVAL;
3840         }
3841         vf = &pf->vfs[vf_id];
3842
3843         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3844                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3845                 return -EINVAL;
3846         }
3847
3848         if (add) {
3849                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3850                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3851                                 ETHER_ADDR_LEN);
3852                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3853                                  ETHER_ADDR_LEN);
3854
3855                 mac_filter.filter_type = filter->filter_type;
3856                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3857                 if (ret != I40E_SUCCESS) {
3858                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3859                         return -1;
3860                 }
3861                 ether_addr_copy(new_mac, &pf->dev_addr);
3862         } else {
3863                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3864                                 ETHER_ADDR_LEN);
3865                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3866                 if (ret != I40E_SUCCESS) {
3867                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3868                         return -1;
3869                 }
3870
3871                 /* Clear device address as it has been removed */
3872                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3873                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3874         }
3875
3876         return 0;
3877 }
3878
3879 /* MAC filter handle */
3880 static int
3881 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3882                 void *arg)
3883 {
3884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3885         struct rte_eth_mac_filter *filter;
3886         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3887         int ret = I40E_NOT_SUPPORTED;
3888
3889         filter = (struct rte_eth_mac_filter *)(arg);
3890
3891         switch (filter_op) {
3892         case RTE_ETH_FILTER_NOP:
3893                 ret = I40E_SUCCESS;
3894                 break;
3895         case RTE_ETH_FILTER_ADD:
3896                 i40e_pf_disable_irq0(hw);
3897                 if (filter->is_vf)
3898                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3899                 i40e_pf_enable_irq0(hw);
3900                 break;
3901         case RTE_ETH_FILTER_DELETE:
3902                 i40e_pf_disable_irq0(hw);
3903                 if (filter->is_vf)
3904                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3905                 i40e_pf_enable_irq0(hw);
3906                 break;
3907         default:
3908                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3909                 ret = I40E_ERR_PARAM;
3910                 break;
3911         }
3912
3913         return ret;
3914 }
3915
3916 static int
3917 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3918 {
3919         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3920         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3921         uint32_t reg;
3922         int ret;
3923
3924         if (!lut)
3925                 return -EINVAL;
3926
3927         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3928                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3929                                           lut, lut_size);
3930                 if (ret) {
3931                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3932                         return ret;
3933                 }
3934         } else {
3935                 uint32_t *lut_dw = (uint32_t *)lut;
3936                 uint16_t i, lut_size_dw = lut_size / 4;
3937
3938                 if (vsi->type == I40E_VSI_SRIOV) {
3939                         for (i = 0; i <= lut_size_dw; i++) {
3940                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3941                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3942                         }
3943                 } else {
3944                         for (i = 0; i < lut_size_dw; i++)
3945                                 lut_dw[i] = I40E_READ_REG(hw,
3946                                                           I40E_PFQF_HLUT(i));
3947                 }
3948         }
3949
3950         return 0;
3951 }
3952
3953 int
3954 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3955 {
3956         struct i40e_pf *pf;
3957         struct i40e_hw *hw;
3958         int ret;
3959
3960         if (!vsi || !lut)
3961                 return -EINVAL;
3962
3963         pf = I40E_VSI_TO_PF(vsi);
3964         hw = I40E_VSI_TO_HW(vsi);
3965
3966         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3967                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3968                                           lut, lut_size);
3969                 if (ret) {
3970                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3971                         return ret;
3972                 }
3973         } else {
3974                 uint32_t *lut_dw = (uint32_t *)lut;
3975                 uint16_t i, lut_size_dw = lut_size / 4;
3976
3977                 if (vsi->type == I40E_VSI_SRIOV) {
3978                         for (i = 0; i < lut_size_dw; i++)
3979                                 I40E_WRITE_REG(
3980                                         hw,
3981                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3982                                         lut_dw[i]);
3983                 } else {
3984                         for (i = 0; i < lut_size_dw; i++)
3985                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3986                                                lut_dw[i]);
3987                 }
3988                 I40E_WRITE_FLUSH(hw);
3989         }
3990
3991         return 0;
3992 }
3993
3994 static int
3995 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3996                          struct rte_eth_rss_reta_entry64 *reta_conf,
3997                          uint16_t reta_size)
3998 {
3999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4000         uint16_t i, lut_size = pf->hash_lut_size;
4001         uint16_t idx, shift;
4002         uint8_t *lut;
4003         int ret;
4004
4005         if (reta_size != lut_size ||
4006                 reta_size > ETH_RSS_RETA_SIZE_512) {
4007                 PMD_DRV_LOG(ERR,
4008                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4009                         reta_size, lut_size);
4010                 return -EINVAL;
4011         }
4012
4013         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4014         if (!lut) {
4015                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4016                 return -ENOMEM;
4017         }
4018         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4019         if (ret)
4020                 goto out;
4021         for (i = 0; i < reta_size; i++) {
4022                 idx = i / RTE_RETA_GROUP_SIZE;
4023                 shift = i % RTE_RETA_GROUP_SIZE;
4024                 if (reta_conf[idx].mask & (1ULL << shift))
4025                         lut[i] = reta_conf[idx].reta[shift];
4026         }
4027         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4028
4029 out:
4030         rte_free(lut);
4031
4032         return ret;
4033 }
4034
4035 static int
4036 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4037                         struct rte_eth_rss_reta_entry64 *reta_conf,
4038                         uint16_t reta_size)
4039 {
4040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4041         uint16_t i, lut_size = pf->hash_lut_size;
4042         uint16_t idx, shift;
4043         uint8_t *lut;
4044         int ret;
4045
4046         if (reta_size != lut_size ||
4047                 reta_size > ETH_RSS_RETA_SIZE_512) {
4048                 PMD_DRV_LOG(ERR,
4049                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4050                         reta_size, lut_size);
4051                 return -EINVAL;
4052         }
4053
4054         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4055         if (!lut) {
4056                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4057                 return -ENOMEM;
4058         }
4059
4060         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4061         if (ret)
4062                 goto out;
4063         for (i = 0; i < reta_size; i++) {
4064                 idx = i / RTE_RETA_GROUP_SIZE;
4065                 shift = i % RTE_RETA_GROUP_SIZE;
4066                 if (reta_conf[idx].mask & (1ULL << shift))
4067                         reta_conf[idx].reta[shift] = lut[i];
4068         }
4069
4070 out:
4071         rte_free(lut);
4072
4073         return ret;
4074 }
4075
4076 /**
4077  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4078  * @hw:   pointer to the HW structure
4079  * @mem:  pointer to mem struct to fill out
4080  * @size: size of memory requested
4081  * @alignment: what to align the allocation to
4082  **/
4083 enum i40e_status_code
4084 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4085                         struct i40e_dma_mem *mem,
4086                         u64 size,
4087                         u32 alignment)
4088 {
4089         const struct rte_memzone *mz = NULL;
4090         char z_name[RTE_MEMZONE_NAMESIZE];
4091
4092         if (!mem)
4093                 return I40E_ERR_PARAM;
4094
4095         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4096         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4097                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4098         if (!mz)
4099                 return I40E_ERR_NO_MEMORY;
4100
4101         mem->size = size;
4102         mem->va = mz->addr;
4103         mem->pa = mz->iova;
4104         mem->zone = (const void *)mz;
4105         PMD_DRV_LOG(DEBUG,
4106                 "memzone %s allocated with physical address: %"PRIu64,
4107                 mz->name, mem->pa);
4108
4109         return I40E_SUCCESS;
4110 }
4111
4112 /**
4113  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4114  * @hw:   pointer to the HW structure
4115  * @mem:  ptr to mem struct to free
4116  **/
4117 enum i40e_status_code
4118 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4119                     struct i40e_dma_mem *mem)
4120 {
4121         if (!mem)
4122                 return I40E_ERR_PARAM;
4123
4124         PMD_DRV_LOG(DEBUG,
4125                 "memzone %s to be freed with physical address: %"PRIu64,
4126                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4127         rte_memzone_free((const struct rte_memzone *)mem->zone);
4128         mem->zone = NULL;
4129         mem->va = NULL;
4130         mem->pa = (u64)0;
4131
4132         return I40E_SUCCESS;
4133 }
4134
4135 /**
4136  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4137  * @hw:   pointer to the HW structure
4138  * @mem:  pointer to mem struct to fill out
4139  * @size: size of memory requested
4140  **/
4141 enum i40e_status_code
4142 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4143                          struct i40e_virt_mem *mem,
4144                          u32 size)
4145 {
4146         if (!mem)
4147                 return I40E_ERR_PARAM;
4148
4149         mem->size = size;
4150         mem->va = rte_zmalloc("i40e", size, 0);
4151
4152         if (mem->va)
4153                 return I40E_SUCCESS;
4154         else
4155                 return I40E_ERR_NO_MEMORY;
4156 }
4157
4158 /**
4159  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4160  * @hw:   pointer to the HW structure
4161  * @mem:  pointer to mem struct to free
4162  **/
4163 enum i40e_status_code
4164 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4165                      struct i40e_virt_mem *mem)
4166 {
4167         if (!mem)
4168                 return I40E_ERR_PARAM;
4169
4170         rte_free(mem->va);
4171         mem->va = NULL;
4172
4173         return I40E_SUCCESS;
4174 }
4175
4176 void
4177 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4178 {
4179         rte_spinlock_init(&sp->spinlock);
4180 }
4181
4182 void
4183 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4184 {
4185         rte_spinlock_lock(&sp->spinlock);
4186 }
4187
4188 void
4189 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4190 {
4191         rte_spinlock_unlock(&sp->spinlock);
4192 }
4193
4194 void
4195 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4196 {
4197         return;
4198 }
4199
4200 /**
4201  * Get the hardware capabilities, which will be parsed
4202  * and saved into struct i40e_hw.
4203  */
4204 static int
4205 i40e_get_cap(struct i40e_hw *hw)
4206 {
4207         struct i40e_aqc_list_capabilities_element_resp *buf;
4208         uint16_t len, size = 0;
4209         int ret;
4210
4211         /* Calculate a huge enough buff for saving response data temporarily */
4212         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4213                                                 I40E_MAX_CAP_ELE_NUM;
4214         buf = rte_zmalloc("i40e", len, 0);
4215         if (!buf) {
4216                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4217                 return I40E_ERR_NO_MEMORY;
4218         }
4219
4220         /* Get, parse the capabilities and save it to hw */
4221         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4222                         i40e_aqc_opc_list_func_capabilities, NULL);
4223         if (ret != I40E_SUCCESS)
4224                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4225
4226         /* Free the temporary buffer after being used */
4227         rte_free(buf);
4228
4229         return ret;
4230 }
4231
4232 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4233 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4234
4235 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4236                 const char *value,
4237                 void *opaque)
4238 {
4239         struct i40e_pf *pf;
4240         unsigned long num;
4241         char *end;
4242
4243         pf = (struct i40e_pf *)opaque;
4244         RTE_SET_USED(key);
4245
4246         errno = 0;
4247         num = strtoul(value, &end, 0);
4248         if (errno != 0 || end == value || *end != 0) {
4249                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4250                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4251                 return -(EINVAL);
4252         }
4253
4254         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4255                 pf->vf_nb_qp_max = (uint16_t)num;
4256         else
4257                 /* here return 0 to make next valid same argument work */
4258                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4259                             "power of 2 and equal or less than 16 !, Now it is "
4260                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4261
4262         return 0;
4263 }
4264
4265 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4266 {
4267         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4268         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4269         struct rte_kvargs *kvlist;
4270
4271         /* set default queue number per VF as 4 */
4272         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4273
4274         if (dev->device->devargs == NULL)
4275                 return 0;
4276
4277         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4278         if (kvlist == NULL)
4279                 return -(EINVAL);
4280
4281         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4282                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4283                             "the first invalid or last valid one is used !",
4284                             QUEUE_NUM_PER_VF_ARG);
4285
4286         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4287                            i40e_pf_parse_vf_queue_number_handler, pf);
4288
4289         rte_kvargs_free(kvlist);
4290
4291         return 0;
4292 }
4293
4294 static int
4295 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4296 {
4297         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4298         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4299         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4300         uint16_t qp_count = 0, vsi_count = 0;
4301
4302         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4303                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4304                 return -EINVAL;
4305         }
4306
4307         i40e_pf_config_vf_rxq_number(dev);
4308
4309         /* Add the parameter init for LFC */
4310         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4311         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4312         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4313
4314         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4315         pf->max_num_vsi = hw->func_caps.num_vsis;
4316         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4317         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4318
4319         /* FDir queue/VSI allocation */
4320         pf->fdir_qp_offset = 0;
4321         if (hw->func_caps.fd) {
4322                 pf->flags |= I40E_FLAG_FDIR;
4323                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4324         } else {
4325                 pf->fdir_nb_qps = 0;
4326         }
4327         qp_count += pf->fdir_nb_qps;
4328         vsi_count += 1;
4329
4330         /* LAN queue/VSI allocation */
4331         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4332         if (!hw->func_caps.rss) {
4333                 pf->lan_nb_qps = 1;
4334         } else {
4335                 pf->flags |= I40E_FLAG_RSS;
4336                 if (hw->mac.type == I40E_MAC_X722)
4337                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4338                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4339         }
4340         qp_count += pf->lan_nb_qps;
4341         vsi_count += 1;
4342
4343         /* VF queue/VSI allocation */
4344         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4345         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4346                 pf->flags |= I40E_FLAG_SRIOV;
4347                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4348                 pf->vf_num = pci_dev->max_vfs;
4349                 PMD_DRV_LOG(DEBUG,
4350                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4351                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4352         } else {
4353                 pf->vf_nb_qps = 0;
4354                 pf->vf_num = 0;
4355         }
4356         qp_count += pf->vf_nb_qps * pf->vf_num;
4357         vsi_count += pf->vf_num;
4358
4359         /* VMDq queue/VSI allocation */
4360         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4361         pf->vmdq_nb_qps = 0;
4362         pf->max_nb_vmdq_vsi = 0;
4363         if (hw->func_caps.vmdq) {
4364                 if (qp_count < hw->func_caps.num_tx_qp &&
4365                         vsi_count < hw->func_caps.num_vsis) {
4366                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4367                                 qp_count) / pf->vmdq_nb_qp_max;
4368
4369                         /* Limit the maximum number of VMDq vsi to the maximum
4370                          * ethdev can support
4371                          */
4372                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4373                                 hw->func_caps.num_vsis - vsi_count);
4374                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4375                                 ETH_64_POOLS);
4376                         if (pf->max_nb_vmdq_vsi) {
4377                                 pf->flags |= I40E_FLAG_VMDQ;
4378                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4379                                 PMD_DRV_LOG(DEBUG,
4380                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4381                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4382                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4383                         } else {
4384                                 PMD_DRV_LOG(INFO,
4385                                         "No enough queues left for VMDq");
4386                         }
4387                 } else {
4388                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4389                 }
4390         }
4391         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4392         vsi_count += pf->max_nb_vmdq_vsi;
4393
4394         if (hw->func_caps.dcb)
4395                 pf->flags |= I40E_FLAG_DCB;
4396
4397         if (qp_count > hw->func_caps.num_tx_qp) {
4398                 PMD_DRV_LOG(ERR,
4399                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4400                         qp_count, hw->func_caps.num_tx_qp);
4401                 return -EINVAL;
4402         }
4403         if (vsi_count > hw->func_caps.num_vsis) {
4404                 PMD_DRV_LOG(ERR,
4405                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4406                         vsi_count, hw->func_caps.num_vsis);
4407                 return -EINVAL;
4408         }
4409
4410         return 0;
4411 }
4412
4413 static int
4414 i40e_pf_get_switch_config(struct i40e_pf *pf)
4415 {
4416         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4417         struct i40e_aqc_get_switch_config_resp *switch_config;
4418         struct i40e_aqc_switch_config_element_resp *element;
4419         uint16_t start_seid = 0, num_reported;
4420         int ret;
4421
4422         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4423                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4424         if (!switch_config) {
4425                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4426                 return -ENOMEM;
4427         }
4428
4429         /* Get the switch configurations */
4430         ret = i40e_aq_get_switch_config(hw, switch_config,
4431                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4432         if (ret != I40E_SUCCESS) {
4433                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4434                 goto fail;
4435         }
4436         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4437         if (num_reported != 1) { /* The number should be 1 */
4438                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4439                 goto fail;
4440         }
4441
4442         /* Parse the switch configuration elements */
4443         element = &(switch_config->element[0]);
4444         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4445                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4446                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4447         } else
4448                 PMD_DRV_LOG(INFO, "Unknown element type");
4449
4450 fail:
4451         rte_free(switch_config);
4452
4453         return ret;
4454 }
4455
4456 static int
4457 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4458                         uint32_t num)
4459 {
4460         struct pool_entry *entry;
4461
4462         if (pool == NULL || num == 0)
4463                 return -EINVAL;
4464
4465         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4466         if (entry == NULL) {
4467                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4468                 return -ENOMEM;
4469         }
4470
4471         /* queue heap initialize */
4472         pool->num_free = num;
4473         pool->num_alloc = 0;
4474         pool->base = base;
4475         LIST_INIT(&pool->alloc_list);
4476         LIST_INIT(&pool->free_list);
4477
4478         /* Initialize element  */
4479         entry->base = 0;
4480         entry->len = num;
4481
4482         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4483         return 0;
4484 }
4485
4486 static void
4487 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4488 {
4489         struct pool_entry *entry, *next_entry;
4490
4491         if (pool == NULL)
4492                 return;
4493
4494         for (entry = LIST_FIRST(&pool->alloc_list);
4495                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4496                         entry = next_entry) {
4497                 LIST_REMOVE(entry, next);
4498                 rte_free(entry);
4499         }
4500
4501         for (entry = LIST_FIRST(&pool->free_list);
4502                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4503                         entry = next_entry) {
4504                 LIST_REMOVE(entry, next);
4505                 rte_free(entry);
4506         }
4507
4508         pool->num_free = 0;
4509         pool->num_alloc = 0;
4510         pool->base = 0;
4511         LIST_INIT(&pool->alloc_list);
4512         LIST_INIT(&pool->free_list);
4513 }
4514
4515 static int
4516 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4517                        uint32_t base)
4518 {
4519         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4520         uint32_t pool_offset;
4521         int insert;
4522
4523         if (pool == NULL) {
4524                 PMD_DRV_LOG(ERR, "Invalid parameter");
4525                 return -EINVAL;
4526         }
4527
4528         pool_offset = base - pool->base;
4529         /* Lookup in alloc list */
4530         LIST_FOREACH(entry, &pool->alloc_list, next) {
4531                 if (entry->base == pool_offset) {
4532                         valid_entry = entry;
4533                         LIST_REMOVE(entry, next);
4534                         break;
4535                 }
4536         }
4537
4538         /* Not find, return */
4539         if (valid_entry == NULL) {
4540                 PMD_DRV_LOG(ERR, "Failed to find entry");
4541                 return -EINVAL;
4542         }
4543
4544         /**
4545          * Found it, move it to free list  and try to merge.
4546          * In order to make merge easier, always sort it by qbase.
4547          * Find adjacent prev and last entries.
4548          */
4549         prev = next = NULL;
4550         LIST_FOREACH(entry, &pool->free_list, next) {
4551                 if (entry->base > valid_entry->base) {
4552                         next = entry;
4553                         break;
4554                 }
4555                 prev = entry;
4556         }
4557
4558         insert = 0;
4559         /* Try to merge with next one*/
4560         if (next != NULL) {
4561                 /* Merge with next one */
4562                 if (valid_entry->base + valid_entry->len == next->base) {
4563                         next->base = valid_entry->base;
4564                         next->len += valid_entry->len;
4565                         rte_free(valid_entry);
4566                         valid_entry = next;
4567                         insert = 1;
4568                 }
4569         }
4570
4571         if (prev != NULL) {
4572                 /* Merge with previous one */
4573                 if (prev->base + prev->len == valid_entry->base) {
4574                         prev->len += valid_entry->len;
4575                         /* If it merge with next one, remove next node */
4576                         if (insert == 1) {
4577                                 LIST_REMOVE(valid_entry, next);
4578                                 rte_free(valid_entry);
4579                         } else {
4580                                 rte_free(valid_entry);
4581                                 insert = 1;
4582                         }
4583                 }
4584         }
4585
4586         /* Not find any entry to merge, insert */
4587         if (insert == 0) {
4588                 if (prev != NULL)
4589                         LIST_INSERT_AFTER(prev, valid_entry, next);
4590                 else if (next != NULL)
4591                         LIST_INSERT_BEFORE(next, valid_entry, next);
4592                 else /* It's empty list, insert to head */
4593                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4594         }
4595
4596         pool->num_free += valid_entry->len;
4597         pool->num_alloc -= valid_entry->len;
4598
4599         return 0;
4600 }
4601
4602 static int
4603 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4604                        uint16_t num)
4605 {
4606         struct pool_entry *entry, *valid_entry;
4607
4608         if (pool == NULL || num == 0) {
4609                 PMD_DRV_LOG(ERR, "Invalid parameter");
4610                 return -EINVAL;
4611         }
4612
4613         if (pool->num_free < num) {
4614                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4615                             num, pool->num_free);
4616                 return -ENOMEM;
4617         }
4618
4619         valid_entry = NULL;
4620         /* Lookup  in free list and find most fit one */
4621         LIST_FOREACH(entry, &pool->free_list, next) {
4622                 if (entry->len >= num) {
4623                         /* Find best one */
4624                         if (entry->len == num) {
4625                                 valid_entry = entry;
4626                                 break;
4627                         }
4628                         if (valid_entry == NULL || valid_entry->len > entry->len)
4629                                 valid_entry = entry;
4630                 }
4631         }
4632
4633         /* Not find one to satisfy the request, return */
4634         if (valid_entry == NULL) {
4635                 PMD_DRV_LOG(ERR, "No valid entry found");
4636                 return -ENOMEM;
4637         }
4638         /**
4639          * The entry have equal queue number as requested,
4640          * remove it from alloc_list.
4641          */
4642         if (valid_entry->len == num) {
4643                 LIST_REMOVE(valid_entry, next);
4644         } else {
4645                 /**
4646                  * The entry have more numbers than requested,
4647                  * create a new entry for alloc_list and minus its
4648                  * queue base and number in free_list.
4649                  */
4650                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4651                 if (entry == NULL) {
4652                         PMD_DRV_LOG(ERR,
4653                                 "Failed to allocate memory for resource pool");
4654                         return -ENOMEM;
4655                 }
4656                 entry->base = valid_entry->base;
4657                 entry->len = num;
4658                 valid_entry->base += num;
4659                 valid_entry->len -= num;
4660                 valid_entry = entry;
4661         }
4662
4663         /* Insert it into alloc list, not sorted */
4664         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4665
4666         pool->num_free -= valid_entry->len;
4667         pool->num_alloc += valid_entry->len;
4668
4669         return valid_entry->base + pool->base;
4670 }
4671
4672 /**
4673  * bitmap_is_subset - Check whether src2 is subset of src1
4674  **/
4675 static inline int
4676 bitmap_is_subset(uint8_t src1, uint8_t src2)
4677 {
4678         return !((src1 ^ src2) & src2);
4679 }
4680
4681 static enum i40e_status_code
4682 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4683 {
4684         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4685
4686         /* If DCB is not supported, only default TC is supported */
4687         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4688                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4689                 return I40E_NOT_SUPPORTED;
4690         }
4691
4692         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4693                 PMD_DRV_LOG(ERR,
4694                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4695                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4696                 return I40E_NOT_SUPPORTED;
4697         }
4698         return I40E_SUCCESS;
4699 }
4700
4701 int
4702 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4703                                 struct i40e_vsi_vlan_pvid_info *info)
4704 {
4705         struct i40e_hw *hw;
4706         struct i40e_vsi_context ctxt;
4707         uint8_t vlan_flags = 0;
4708         int ret;
4709
4710         if (vsi == NULL || info == NULL) {
4711                 PMD_DRV_LOG(ERR, "invalid parameters");
4712                 return I40E_ERR_PARAM;
4713         }
4714
4715         if (info->on) {
4716                 vsi->info.pvid = info->config.pvid;
4717                 /**
4718                  * If insert pvid is enabled, only tagged pkts are
4719                  * allowed to be sent out.
4720                  */
4721                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4722                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4723         } else {
4724                 vsi->info.pvid = 0;
4725                 if (info->config.reject.tagged == 0)
4726                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4727
4728                 if (info->config.reject.untagged == 0)
4729                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4730         }
4731         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4732                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4733         vsi->info.port_vlan_flags |= vlan_flags;
4734         vsi->info.valid_sections =
4735                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4736         memset(&ctxt, 0, sizeof(ctxt));
4737         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4738         ctxt.seid = vsi->seid;
4739
4740         hw = I40E_VSI_TO_HW(vsi);
4741         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4742         if (ret != I40E_SUCCESS)
4743                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4744
4745         return ret;
4746 }
4747
4748 static int
4749 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4750 {
4751         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4752         int i, ret;
4753         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4754
4755         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4756         if (ret != I40E_SUCCESS)
4757                 return ret;
4758
4759         if (!vsi->seid) {
4760                 PMD_DRV_LOG(ERR, "seid not valid");
4761                 return -EINVAL;
4762         }
4763
4764         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4765         tc_bw_data.tc_valid_bits = enabled_tcmap;
4766         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4767                 tc_bw_data.tc_bw_credits[i] =
4768                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4769
4770         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4771         if (ret != I40E_SUCCESS) {
4772                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4773                 return ret;
4774         }
4775
4776         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4777                                         sizeof(vsi->info.qs_handle));
4778         return I40E_SUCCESS;
4779 }
4780
4781 static enum i40e_status_code
4782 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4783                                  struct i40e_aqc_vsi_properties_data *info,
4784                                  uint8_t enabled_tcmap)
4785 {
4786         enum i40e_status_code ret;
4787         int i, total_tc = 0;
4788         uint16_t qpnum_per_tc, bsf, qp_idx;
4789
4790         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4791         if (ret != I40E_SUCCESS)
4792                 return ret;
4793
4794         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4795                 if (enabled_tcmap & (1 << i))
4796                         total_tc++;
4797         if (total_tc == 0)
4798                 total_tc = 1;
4799         vsi->enabled_tc = enabled_tcmap;
4800
4801         /* Number of queues per enabled TC */
4802         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4803         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4804         bsf = rte_bsf32(qpnum_per_tc);
4805
4806         /* Adjust the queue number to actual queues that can be applied */
4807         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4808                 vsi->nb_qps = qpnum_per_tc * total_tc;
4809
4810         /**
4811          * Configure TC and queue mapping parameters, for enabled TC,
4812          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4813          * default queue will serve it.
4814          */
4815         qp_idx = 0;
4816         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4817                 if (vsi->enabled_tc & (1 << i)) {
4818                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4819                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4820                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4821                         qp_idx += qpnum_per_tc;
4822                 } else
4823                         info->tc_mapping[i] = 0;
4824         }
4825
4826         /* Associate queue number with VSI */
4827         if (vsi->type == I40E_VSI_SRIOV) {
4828                 info->mapping_flags |=
4829                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4830                 for (i = 0; i < vsi->nb_qps; i++)
4831                         info->queue_mapping[i] =
4832                                 rte_cpu_to_le_16(vsi->base_queue + i);
4833         } else {
4834                 info->mapping_flags |=
4835                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4836                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4837         }
4838         info->valid_sections |=
4839                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4840
4841         return I40E_SUCCESS;
4842 }
4843
4844 static int
4845 i40e_veb_release(struct i40e_veb *veb)
4846 {
4847         struct i40e_vsi *vsi;
4848         struct i40e_hw *hw;
4849
4850         if (veb == NULL)
4851                 return -EINVAL;
4852
4853         if (!TAILQ_EMPTY(&veb->head)) {
4854                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4855                 return -EACCES;
4856         }
4857         /* associate_vsi field is NULL for floating VEB */
4858         if (veb->associate_vsi != NULL) {
4859                 vsi = veb->associate_vsi;
4860                 hw = I40E_VSI_TO_HW(vsi);
4861
4862                 vsi->uplink_seid = veb->uplink_seid;
4863                 vsi->veb = NULL;
4864         } else {
4865                 veb->associate_pf->main_vsi->floating_veb = NULL;
4866                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4867         }
4868
4869         i40e_aq_delete_element(hw, veb->seid, NULL);
4870         rte_free(veb);
4871         return I40E_SUCCESS;
4872 }
4873
4874 /* Setup a veb */
4875 static struct i40e_veb *
4876 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4877 {
4878         struct i40e_veb *veb;
4879         int ret;
4880         struct i40e_hw *hw;
4881
4882         if (pf == NULL) {
4883                 PMD_DRV_LOG(ERR,
4884                             "veb setup failed, associated PF shouldn't null");
4885                 return NULL;
4886         }
4887         hw = I40E_PF_TO_HW(pf);
4888
4889         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4890         if (!veb) {
4891                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4892                 goto fail;
4893         }
4894
4895         veb->associate_vsi = vsi;
4896         veb->associate_pf = pf;
4897         TAILQ_INIT(&veb->head);
4898         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4899
4900         /* create floating veb if vsi is NULL */
4901         if (vsi != NULL) {
4902                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4903                                       I40E_DEFAULT_TCMAP, false,
4904                                       &veb->seid, false, NULL);
4905         } else {
4906                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4907                                       true, &veb->seid, false, NULL);
4908         }
4909
4910         if (ret != I40E_SUCCESS) {
4911                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4912                             hw->aq.asq_last_status);
4913                 goto fail;
4914         }
4915         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4916
4917         /* get statistics index */
4918         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4919                                 &veb->stats_idx, NULL, NULL, NULL);
4920         if (ret != I40E_SUCCESS) {
4921                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4922                             hw->aq.asq_last_status);
4923                 goto fail;
4924         }
4925         /* Get VEB bandwidth, to be implemented */
4926         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4927         if (vsi)
4928                 vsi->uplink_seid = veb->seid;
4929
4930         return veb;
4931 fail:
4932         rte_free(veb);
4933         return NULL;
4934 }
4935
4936 int
4937 i40e_vsi_release(struct i40e_vsi *vsi)
4938 {
4939         struct i40e_pf *pf;
4940         struct i40e_hw *hw;
4941         struct i40e_vsi_list *vsi_list;
4942         void *temp;
4943         int ret;
4944         struct i40e_mac_filter *f;
4945         uint16_t user_param;
4946
4947         if (!vsi)
4948                 return I40E_SUCCESS;
4949
4950         if (!vsi->adapter)
4951                 return -EFAULT;
4952
4953         user_param = vsi->user_param;
4954
4955         pf = I40E_VSI_TO_PF(vsi);
4956         hw = I40E_VSI_TO_HW(vsi);
4957
4958         /* VSI has child to attach, release child first */
4959         if (vsi->veb) {
4960                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4961                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4962                                 return -1;
4963                 }
4964                 i40e_veb_release(vsi->veb);
4965         }
4966
4967         if (vsi->floating_veb) {
4968                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4969                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4970                                 return -1;
4971                 }
4972         }
4973
4974         /* Remove all macvlan filters of the VSI */
4975         i40e_vsi_remove_all_macvlan_filter(vsi);
4976         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4977                 rte_free(f);
4978
4979         if (vsi->type != I40E_VSI_MAIN &&
4980             ((vsi->type != I40E_VSI_SRIOV) ||
4981             !pf->floating_veb_list[user_param])) {
4982                 /* Remove vsi from parent's sibling list */
4983                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4984                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4985                         return I40E_ERR_PARAM;
4986                 }
4987                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4988                                 &vsi->sib_vsi_list, list);
4989
4990                 /* Remove all switch element of the VSI */
4991                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4992                 if (ret != I40E_SUCCESS)
4993                         PMD_DRV_LOG(ERR, "Failed to delete element");
4994         }
4995
4996         if ((vsi->type == I40E_VSI_SRIOV) &&
4997             pf->floating_veb_list[user_param]) {
4998                 /* Remove vsi from parent's sibling list */
4999                 if (vsi->parent_vsi == NULL ||
5000                     vsi->parent_vsi->floating_veb == NULL) {
5001                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5002                         return I40E_ERR_PARAM;
5003                 }
5004                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5005                              &vsi->sib_vsi_list, list);
5006
5007                 /* Remove all switch element of the VSI */
5008                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5009                 if (ret != I40E_SUCCESS)
5010                         PMD_DRV_LOG(ERR, "Failed to delete element");
5011         }
5012
5013         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5014
5015         if (vsi->type != I40E_VSI_SRIOV)
5016                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5017         rte_free(vsi);
5018
5019         return I40E_SUCCESS;
5020 }
5021
5022 static int
5023 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5024 {
5025         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5026         struct i40e_aqc_remove_macvlan_element_data def_filter;
5027         struct i40e_mac_filter_info filter;
5028         int ret;
5029
5030         if (vsi->type != I40E_VSI_MAIN)
5031                 return I40E_ERR_CONFIG;
5032         memset(&def_filter, 0, sizeof(def_filter));
5033         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5034                                         ETH_ADDR_LEN);
5035         def_filter.vlan_tag = 0;
5036         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5037                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5038         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5039         if (ret != I40E_SUCCESS) {
5040                 struct i40e_mac_filter *f;
5041                 struct ether_addr *mac;
5042
5043                 PMD_DRV_LOG(DEBUG,
5044                             "Cannot remove the default macvlan filter");
5045                 /* It needs to add the permanent mac into mac list */
5046                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5047                 if (f == NULL) {
5048                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5049                         return I40E_ERR_NO_MEMORY;
5050                 }
5051                 mac = &f->mac_info.mac_addr;
5052                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5053                                 ETH_ADDR_LEN);
5054                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5055                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5056                 vsi->mac_num++;
5057
5058                 return ret;
5059         }
5060         rte_memcpy(&filter.mac_addr,
5061                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5062         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5063         return i40e_vsi_add_mac(vsi, &filter);
5064 }
5065
5066 /*
5067  * i40e_vsi_get_bw_config - Query VSI BW Information
5068  * @vsi: the VSI to be queried
5069  *
5070  * Returns 0 on success, negative value on failure
5071  */
5072 static enum i40e_status_code
5073 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5074 {
5075         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5076         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5077         struct i40e_hw *hw = &vsi->adapter->hw;
5078         i40e_status ret;
5079         int i;
5080         uint32_t bw_max;
5081
5082         memset(&bw_config, 0, sizeof(bw_config));
5083         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5084         if (ret != I40E_SUCCESS) {
5085                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5086                             hw->aq.asq_last_status);
5087                 return ret;
5088         }
5089
5090         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5091         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5092                                         &ets_sla_config, NULL);
5093         if (ret != I40E_SUCCESS) {
5094                 PMD_DRV_LOG(ERR,
5095                         "VSI failed to get TC bandwdith configuration %u",
5096                         hw->aq.asq_last_status);
5097                 return ret;
5098         }
5099
5100         /* store and print out BW info */
5101         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5102         vsi->bw_info.bw_max = bw_config.max_bw;
5103         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5104         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5105         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5106                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5107                      I40E_16_BIT_WIDTH);
5108         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5109                 vsi->bw_info.bw_ets_share_credits[i] =
5110                                 ets_sla_config.share_credits[i];
5111                 vsi->bw_info.bw_ets_credits[i] =
5112                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5113                 /* 4 bits per TC, 4th bit is reserved */
5114                 vsi->bw_info.bw_ets_max[i] =
5115                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5116                                   RTE_LEN2MASK(3, uint8_t));
5117                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5118                             vsi->bw_info.bw_ets_share_credits[i]);
5119                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5120                             vsi->bw_info.bw_ets_credits[i]);
5121                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5122                             vsi->bw_info.bw_ets_max[i]);
5123         }
5124
5125         return I40E_SUCCESS;
5126 }
5127
5128 /* i40e_enable_pf_lb
5129  * @pf: pointer to the pf structure
5130  *
5131  * allow loopback on pf
5132  */
5133 static inline void
5134 i40e_enable_pf_lb(struct i40e_pf *pf)
5135 {
5136         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5137         struct i40e_vsi_context ctxt;
5138         int ret;
5139
5140         /* Use the FW API if FW >= v5.0 */
5141         if (hw->aq.fw_maj_ver < 5) {
5142                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5143                 return;
5144         }
5145
5146         memset(&ctxt, 0, sizeof(ctxt));
5147         ctxt.seid = pf->main_vsi_seid;
5148         ctxt.pf_num = hw->pf_id;
5149         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5150         if (ret) {
5151                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5152                             ret, hw->aq.asq_last_status);
5153                 return;
5154         }
5155         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5156         ctxt.info.valid_sections =
5157                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5158         ctxt.info.switch_id |=
5159                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5160
5161         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5162         if (ret)
5163                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5164                             hw->aq.asq_last_status);
5165 }
5166
5167 /* Setup a VSI */
5168 struct i40e_vsi *
5169 i40e_vsi_setup(struct i40e_pf *pf,
5170                enum i40e_vsi_type type,
5171                struct i40e_vsi *uplink_vsi,
5172                uint16_t user_param)
5173 {
5174         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5175         struct i40e_vsi *vsi;
5176         struct i40e_mac_filter_info filter;
5177         int ret;
5178         struct i40e_vsi_context ctxt;
5179         struct ether_addr broadcast =
5180                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5181
5182         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5183             uplink_vsi == NULL) {
5184                 PMD_DRV_LOG(ERR,
5185                         "VSI setup failed, VSI link shouldn't be NULL");
5186                 return NULL;
5187         }
5188
5189         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5190                 PMD_DRV_LOG(ERR,
5191                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5192                 return NULL;
5193         }
5194
5195         /* two situations
5196          * 1.type is not MAIN and uplink vsi is not NULL
5197          * If uplink vsi didn't setup VEB, create one first under veb field
5198          * 2.type is SRIOV and the uplink is NULL
5199          * If floating VEB is NULL, create one veb under floating veb field
5200          */
5201
5202         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5203             uplink_vsi->veb == NULL) {
5204                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5205
5206                 if (uplink_vsi->veb == NULL) {
5207                         PMD_DRV_LOG(ERR, "VEB setup failed");
5208                         return NULL;
5209                 }
5210                 /* set ALLOWLOOPBACk on pf, when veb is created */
5211                 i40e_enable_pf_lb(pf);
5212         }
5213
5214         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5215             pf->main_vsi->floating_veb == NULL) {
5216                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5217
5218                 if (pf->main_vsi->floating_veb == NULL) {
5219                         PMD_DRV_LOG(ERR, "VEB setup failed");
5220                         return NULL;
5221                 }
5222         }
5223
5224         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5225         if (!vsi) {
5226                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5227                 return NULL;
5228         }
5229         TAILQ_INIT(&vsi->mac_list);
5230         vsi->type = type;
5231         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5232         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5233         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5234         vsi->user_param = user_param;
5235         vsi->vlan_anti_spoof_on = 0;
5236         vsi->vlan_filter_on = 0;
5237         /* Allocate queues */
5238         switch (vsi->type) {
5239         case I40E_VSI_MAIN  :
5240                 vsi->nb_qps = pf->lan_nb_qps;
5241                 break;
5242         case I40E_VSI_SRIOV :
5243                 vsi->nb_qps = pf->vf_nb_qps;
5244                 break;
5245         case I40E_VSI_VMDQ2:
5246                 vsi->nb_qps = pf->vmdq_nb_qps;
5247                 break;
5248         case I40E_VSI_FDIR:
5249                 vsi->nb_qps = pf->fdir_nb_qps;
5250                 break;
5251         default:
5252                 goto fail_mem;
5253         }
5254         /*
5255          * The filter status descriptor is reported in rx queue 0,
5256          * while the tx queue for fdir filter programming has no
5257          * such constraints, can be non-zero queues.
5258          * To simplify it, choose FDIR vsi use queue 0 pair.
5259          * To make sure it will use queue 0 pair, queue allocation
5260          * need be done before this function is called
5261          */
5262         if (type != I40E_VSI_FDIR) {
5263                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5264                         if (ret < 0) {
5265                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5266                                                 vsi->seid, ret);
5267                                 goto fail_mem;
5268                         }
5269                         vsi->base_queue = ret;
5270         } else
5271                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5272
5273         /* VF has MSIX interrupt in VF range, don't allocate here */
5274         if (type == I40E_VSI_MAIN) {
5275                 if (pf->support_multi_driver) {
5276                         /* If support multi-driver, need to use INT0 instead of
5277                          * allocating from msix pool. The Msix pool is init from
5278                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5279                          * to 1 without calling i40e_res_pool_alloc.
5280                          */
5281                         vsi->msix_intr = 0;
5282                         vsi->nb_msix = 1;
5283                 } else {
5284                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5285                                                   RTE_MIN(vsi->nb_qps,
5286                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5287                         if (ret < 0) {
5288                                 PMD_DRV_LOG(ERR,
5289                                             "VSI MAIN %d get heap failed %d",
5290                                             vsi->seid, ret);
5291                                 goto fail_queue_alloc;
5292                         }
5293                         vsi->msix_intr = ret;
5294                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5295                                                RTE_MAX_RXTX_INTR_VEC_ID);
5296                 }
5297         } else if (type != I40E_VSI_SRIOV) {
5298                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5299                 if (ret < 0) {
5300                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5301                         goto fail_queue_alloc;
5302                 }
5303                 vsi->msix_intr = ret;
5304                 vsi->nb_msix = 1;
5305         } else {
5306                 vsi->msix_intr = 0;
5307                 vsi->nb_msix = 0;
5308         }
5309
5310         /* Add VSI */
5311         if (type == I40E_VSI_MAIN) {
5312                 /* For main VSI, no need to add since it's default one */
5313                 vsi->uplink_seid = pf->mac_seid;
5314                 vsi->seid = pf->main_vsi_seid;
5315                 /* Bind queues with specific MSIX interrupt */
5316                 /**
5317                  * Needs 2 interrupt at least, one for misc cause which will
5318                  * enabled from OS side, Another for queues binding the
5319                  * interrupt from device side only.
5320                  */
5321
5322                 /* Get default VSI parameters from hardware */
5323                 memset(&ctxt, 0, sizeof(ctxt));
5324                 ctxt.seid = vsi->seid;
5325                 ctxt.pf_num = hw->pf_id;
5326                 ctxt.uplink_seid = vsi->uplink_seid;
5327                 ctxt.vf_num = 0;
5328                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5329                 if (ret != I40E_SUCCESS) {
5330                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5331                         goto fail_msix_alloc;
5332                 }
5333                 rte_memcpy(&vsi->info, &ctxt.info,
5334                         sizeof(struct i40e_aqc_vsi_properties_data));
5335                 vsi->vsi_id = ctxt.vsi_number;
5336                 vsi->info.valid_sections = 0;
5337
5338                 /* Configure tc, enabled TC0 only */
5339                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5340                         I40E_SUCCESS) {
5341                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5342                         goto fail_msix_alloc;
5343                 }
5344
5345                 /* TC, queue mapping */
5346                 memset(&ctxt, 0, sizeof(ctxt));
5347                 vsi->info.valid_sections |=
5348                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5349                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5350                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5351                 rte_memcpy(&ctxt.info, &vsi->info,
5352                         sizeof(struct i40e_aqc_vsi_properties_data));
5353                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5354                                                 I40E_DEFAULT_TCMAP);
5355                 if (ret != I40E_SUCCESS) {
5356                         PMD_DRV_LOG(ERR,
5357                                 "Failed to configure TC queue mapping");
5358                         goto fail_msix_alloc;
5359                 }
5360                 ctxt.seid = vsi->seid;
5361                 ctxt.pf_num = hw->pf_id;
5362                 ctxt.uplink_seid = vsi->uplink_seid;
5363                 ctxt.vf_num = 0;
5364
5365                 /* Update VSI parameters */
5366                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5367                 if (ret != I40E_SUCCESS) {
5368                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5369                         goto fail_msix_alloc;
5370                 }
5371
5372                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5373                                                 sizeof(vsi->info.tc_mapping));
5374                 rte_memcpy(&vsi->info.queue_mapping,
5375                                 &ctxt.info.queue_mapping,
5376                         sizeof(vsi->info.queue_mapping));
5377                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5378                 vsi->info.valid_sections = 0;
5379
5380                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5381                                 ETH_ADDR_LEN);
5382
5383                 /**
5384                  * Updating default filter settings are necessary to prevent
5385                  * reception of tagged packets.
5386                  * Some old firmware configurations load a default macvlan
5387                  * filter which accepts both tagged and untagged packets.
5388                  * The updating is to use a normal filter instead if needed.
5389                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5390                  * The firmware with correct configurations load the default
5391                  * macvlan filter which is expected and cannot be removed.
5392                  */
5393                 i40e_update_default_filter_setting(vsi);
5394                 i40e_config_qinq(hw, vsi);
5395         } else if (type == I40E_VSI_SRIOV) {
5396                 memset(&ctxt, 0, sizeof(ctxt));
5397                 /**
5398                  * For other VSI, the uplink_seid equals to uplink VSI's
5399                  * uplink_seid since they share same VEB
5400                  */
5401                 if (uplink_vsi == NULL)
5402                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5403                 else
5404                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5405                 ctxt.pf_num = hw->pf_id;
5406                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5407                 ctxt.uplink_seid = vsi->uplink_seid;
5408                 ctxt.connection_type = 0x1;
5409                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5410
5411                 /* Use the VEB configuration if FW >= v5.0 */
5412                 if (hw->aq.fw_maj_ver >= 5) {
5413                         /* Configure switch ID */
5414                         ctxt.info.valid_sections |=
5415                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5416                         ctxt.info.switch_id =
5417                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5418                 }
5419
5420                 /* Configure port/vlan */
5421                 ctxt.info.valid_sections |=
5422                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5423                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5424                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5425                                                 hw->func_caps.enabled_tcmap);
5426                 if (ret != I40E_SUCCESS) {
5427                         PMD_DRV_LOG(ERR,
5428                                 "Failed to configure TC queue mapping");
5429                         goto fail_msix_alloc;
5430                 }
5431
5432                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5433                 ctxt.info.valid_sections |=
5434                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5435                 /**
5436                  * Since VSI is not created yet, only configure parameter,
5437                  * will add vsi below.
5438                  */
5439
5440                 i40e_config_qinq(hw, vsi);
5441         } else if (type == I40E_VSI_VMDQ2) {
5442                 memset(&ctxt, 0, sizeof(ctxt));
5443                 /*
5444                  * For other VSI, the uplink_seid equals to uplink VSI's
5445                  * uplink_seid since they share same VEB
5446                  */
5447                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5448                 ctxt.pf_num = hw->pf_id;
5449                 ctxt.vf_num = 0;
5450                 ctxt.uplink_seid = vsi->uplink_seid;
5451                 ctxt.connection_type = 0x1;
5452                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5453
5454                 ctxt.info.valid_sections |=
5455                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5456                 /* user_param carries flag to enable loop back */
5457                 if (user_param) {
5458                         ctxt.info.switch_id =
5459                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5460                         ctxt.info.switch_id |=
5461                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5462                 }
5463
5464                 /* Configure port/vlan */
5465                 ctxt.info.valid_sections |=
5466                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5467                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5468                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5469                                                 I40E_DEFAULT_TCMAP);
5470                 if (ret != I40E_SUCCESS) {
5471                         PMD_DRV_LOG(ERR,
5472                                 "Failed to configure TC queue mapping");
5473                         goto fail_msix_alloc;
5474                 }
5475                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5476                 ctxt.info.valid_sections |=
5477                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5478         } else if (type == I40E_VSI_FDIR) {
5479                 memset(&ctxt, 0, sizeof(ctxt));
5480                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5481                 ctxt.pf_num = hw->pf_id;
5482                 ctxt.vf_num = 0;
5483                 ctxt.uplink_seid = vsi->uplink_seid;
5484                 ctxt.connection_type = 0x1;     /* regular data port */
5485                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5486                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5487                                                 I40E_DEFAULT_TCMAP);
5488                 if (ret != I40E_SUCCESS) {
5489                         PMD_DRV_LOG(ERR,
5490                                 "Failed to configure TC queue mapping.");
5491                         goto fail_msix_alloc;
5492                 }
5493                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5494                 ctxt.info.valid_sections |=
5495                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5496         } else {
5497                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5498                 goto fail_msix_alloc;
5499         }
5500
5501         if (vsi->type != I40E_VSI_MAIN) {
5502                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5503                 if (ret != I40E_SUCCESS) {
5504                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5505                                     hw->aq.asq_last_status);
5506                         goto fail_msix_alloc;
5507                 }
5508                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5509                 vsi->info.valid_sections = 0;
5510                 vsi->seid = ctxt.seid;
5511                 vsi->vsi_id = ctxt.vsi_number;
5512                 vsi->sib_vsi_list.vsi = vsi;
5513                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5514                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5515                                           &vsi->sib_vsi_list, list);
5516                 } else {
5517                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5518                                           &vsi->sib_vsi_list, list);
5519                 }
5520         }
5521
5522         /* MAC/VLAN configuration */
5523         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5524         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5525
5526         ret = i40e_vsi_add_mac(vsi, &filter);
5527         if (ret != I40E_SUCCESS) {
5528                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5529                 goto fail_msix_alloc;
5530         }
5531
5532         /* Get VSI BW information */
5533         i40e_vsi_get_bw_config(vsi);
5534         return vsi;
5535 fail_msix_alloc:
5536         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5537 fail_queue_alloc:
5538         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5539 fail_mem:
5540         rte_free(vsi);
5541         return NULL;
5542 }
5543
5544 /* Configure vlan filter on or off */
5545 int
5546 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5547 {
5548         int i, num;
5549         struct i40e_mac_filter *f;
5550         void *temp;
5551         struct i40e_mac_filter_info *mac_filter;
5552         enum rte_mac_filter_type desired_filter;
5553         int ret = I40E_SUCCESS;
5554
5555         if (on) {
5556                 /* Filter to match MAC and VLAN */
5557                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5558         } else {
5559                 /* Filter to match only MAC */
5560                 desired_filter = RTE_MAC_PERFECT_MATCH;
5561         }
5562
5563         num = vsi->mac_num;
5564
5565         mac_filter = rte_zmalloc("mac_filter_info_data",
5566                                  num * sizeof(*mac_filter), 0);
5567         if (mac_filter == NULL) {
5568                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5569                 return I40E_ERR_NO_MEMORY;
5570         }
5571
5572         i = 0;
5573
5574         /* Remove all existing mac */
5575         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5576                 mac_filter[i] = f->mac_info;
5577                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5578                 if (ret) {
5579                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5580                                     on ? "enable" : "disable");
5581                         goto DONE;
5582                 }
5583                 i++;
5584         }
5585
5586         /* Override with new filter */
5587         for (i = 0; i < num; i++) {
5588                 mac_filter[i].filter_type = desired_filter;
5589                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5590                 if (ret) {
5591                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5592                                     on ? "enable" : "disable");
5593                         goto DONE;
5594                 }
5595         }
5596
5597 DONE:
5598         rte_free(mac_filter);
5599         return ret;
5600 }
5601
5602 /* Configure vlan stripping on or off */
5603 int
5604 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5605 {
5606         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5607         struct i40e_vsi_context ctxt;
5608         uint8_t vlan_flags;
5609         int ret = I40E_SUCCESS;
5610
5611         /* Check if it has been already on or off */
5612         if (vsi->info.valid_sections &
5613                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5614                 if (on) {
5615                         if ((vsi->info.port_vlan_flags &
5616                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5617                                 return 0; /* already on */
5618                 } else {
5619                         if ((vsi->info.port_vlan_flags &
5620                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5621                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5622                                 return 0; /* already off */
5623                 }
5624         }
5625
5626         if (on)
5627                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5628         else
5629                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5630         vsi->info.valid_sections =
5631                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5632         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5633         vsi->info.port_vlan_flags |= vlan_flags;
5634         ctxt.seid = vsi->seid;
5635         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5636         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5637         if (ret)
5638                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5639                             on ? "enable" : "disable");
5640
5641         return ret;
5642 }
5643
5644 static int
5645 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5646 {
5647         struct rte_eth_dev_data *data = dev->data;
5648         int ret;
5649         int mask = 0;
5650
5651         /* Apply vlan offload setting */
5652         mask = ETH_VLAN_STRIP_MASK |
5653                ETH_VLAN_FILTER_MASK |
5654                ETH_VLAN_EXTEND_MASK;
5655         ret = i40e_vlan_offload_set(dev, mask);
5656         if (ret) {
5657                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5658                 return ret;
5659         }
5660
5661         /* Apply pvid setting */
5662         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5663                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5664         if (ret)
5665                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5666
5667         return ret;
5668 }
5669
5670 static int
5671 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5672 {
5673         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5674
5675         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5676 }
5677
5678 static int
5679 i40e_update_flow_control(struct i40e_hw *hw)
5680 {
5681 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5682         struct i40e_link_status link_status;
5683         uint32_t rxfc = 0, txfc = 0, reg;
5684         uint8_t an_info;
5685         int ret;
5686
5687         memset(&link_status, 0, sizeof(link_status));
5688         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5689         if (ret != I40E_SUCCESS) {
5690                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5691                 goto write_reg; /* Disable flow control */
5692         }
5693
5694         an_info = hw->phy.link_info.an_info;
5695         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5696                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5697                 ret = I40E_ERR_NOT_READY;
5698                 goto write_reg; /* Disable flow control */
5699         }
5700         /**
5701          * If link auto negotiation is enabled, flow control needs to
5702          * be configured according to it
5703          */
5704         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5705         case I40E_LINK_PAUSE_RXTX:
5706                 rxfc = 1;
5707                 txfc = 1;
5708                 hw->fc.current_mode = I40E_FC_FULL;
5709                 break;
5710         case I40E_AQ_LINK_PAUSE_RX:
5711                 rxfc = 1;
5712                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5713                 break;
5714         case I40E_AQ_LINK_PAUSE_TX:
5715                 txfc = 1;
5716                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5717                 break;
5718         default:
5719                 hw->fc.current_mode = I40E_FC_NONE;
5720                 break;
5721         }
5722
5723 write_reg:
5724         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5725                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5726         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5727         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5728         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5729         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5730
5731         return ret;
5732 }
5733
5734 /* PF setup */
5735 static int
5736 i40e_pf_setup(struct i40e_pf *pf)
5737 {
5738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5739         struct i40e_filter_control_settings settings;
5740         struct i40e_vsi *vsi;
5741         int ret;
5742
5743         /* Clear all stats counters */
5744         pf->offset_loaded = FALSE;
5745         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5746         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5747         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5748         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5749
5750         ret = i40e_pf_get_switch_config(pf);
5751         if (ret != I40E_SUCCESS) {
5752                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5753                 return ret;
5754         }
5755         if (pf->flags & I40E_FLAG_FDIR) {
5756                 /* make queue allocated first, let FDIR use queue pair 0*/
5757                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5758                 if (ret != I40E_FDIR_QUEUE_ID) {
5759                         PMD_DRV_LOG(ERR,
5760                                 "queue allocation fails for FDIR: ret =%d",
5761                                 ret);
5762                         pf->flags &= ~I40E_FLAG_FDIR;
5763                 }
5764         }
5765         /*  main VSI setup */
5766         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5767         if (!vsi) {
5768                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5769                 return I40E_ERR_NOT_READY;
5770         }
5771         pf->main_vsi = vsi;
5772
5773         /* Configure filter control */
5774         memset(&settings, 0, sizeof(settings));
5775         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5776                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5777         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5778                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5779         else {
5780                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5781                         hw->func_caps.rss_table_size);
5782                 return I40E_ERR_PARAM;
5783         }
5784         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5785                 hw->func_caps.rss_table_size);
5786         pf->hash_lut_size = hw->func_caps.rss_table_size;
5787
5788         /* Enable ethtype and macvlan filters */
5789         settings.enable_ethtype = TRUE;
5790         settings.enable_macvlan = TRUE;
5791         ret = i40e_set_filter_control(hw, &settings);
5792         if (ret)
5793                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5794                                                                 ret);
5795
5796         /* Update flow control according to the auto negotiation */
5797         i40e_update_flow_control(hw);
5798
5799         return I40E_SUCCESS;
5800 }
5801
5802 int
5803 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5804 {
5805         uint32_t reg;
5806         uint16_t j;
5807
5808         /**
5809          * Set or clear TX Queue Disable flags,
5810          * which is required by hardware.
5811          */
5812         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5813         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5814
5815         /* Wait until the request is finished */
5816         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5817                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5818                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5819                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5820                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5821                                                         & 0x1))) {
5822                         break;
5823                 }
5824         }
5825         if (on) {
5826                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5827                         return I40E_SUCCESS; /* already on, skip next steps */
5828
5829                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5830                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5831         } else {
5832                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5833                         return I40E_SUCCESS; /* already off, skip next steps */
5834                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5835         }
5836         /* Write the register */
5837         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5838         /* Check the result */
5839         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5840                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5841                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5842                 if (on) {
5843                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5844                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5845                                 break;
5846                 } else {
5847                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5848                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5849                                 break;
5850                 }
5851         }
5852         /* Check if it is timeout */
5853         if (j >= I40E_CHK_Q_ENA_COUNT) {
5854                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5855                             (on ? "enable" : "disable"), q_idx);
5856                 return I40E_ERR_TIMEOUT;
5857         }
5858
5859         return I40E_SUCCESS;
5860 }
5861
5862 /* Swith on or off the tx queues */
5863 static int
5864 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5865 {
5866         struct rte_eth_dev_data *dev_data = pf->dev_data;
5867         struct i40e_tx_queue *txq;
5868         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5869         uint16_t i;
5870         int ret;
5871
5872         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5873                 txq = dev_data->tx_queues[i];
5874                 /* Don't operate the queue if not configured or
5875                  * if starting only per queue */
5876                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5877                         continue;
5878                 if (on)
5879                         ret = i40e_dev_tx_queue_start(dev, i);
5880                 else
5881                         ret = i40e_dev_tx_queue_stop(dev, i);
5882                 if ( ret != I40E_SUCCESS)
5883                         return ret;
5884         }
5885
5886         return I40E_SUCCESS;
5887 }
5888
5889 int
5890 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5891 {
5892         uint32_t reg;
5893         uint16_t j;
5894
5895         /* Wait until the request is finished */
5896         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5897                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5898                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5899                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5900                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5901                         break;
5902         }
5903
5904         if (on) {
5905                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5906                         return I40E_SUCCESS; /* Already on, skip next steps */
5907                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5908         } else {
5909                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5910                         return I40E_SUCCESS; /* Already off, skip next steps */
5911                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5912         }
5913
5914         /* Write the register */
5915         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5916         /* Check the result */
5917         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5918                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5919                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5920                 if (on) {
5921                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5922                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5923                                 break;
5924                 } else {
5925                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5926                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5927                                 break;
5928                 }
5929         }
5930
5931         /* Check if it is timeout */
5932         if (j >= I40E_CHK_Q_ENA_COUNT) {
5933                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5934                             (on ? "enable" : "disable"), q_idx);
5935                 return I40E_ERR_TIMEOUT;
5936         }
5937
5938         return I40E_SUCCESS;
5939 }
5940 /* Switch on or off the rx queues */
5941 static int
5942 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5943 {
5944         struct rte_eth_dev_data *dev_data = pf->dev_data;
5945         struct i40e_rx_queue *rxq;
5946         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5947         uint16_t i;
5948         int ret;
5949
5950         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5951                 rxq = dev_data->rx_queues[i];
5952                 /* Don't operate the queue if not configured or
5953                  * if starting only per queue */
5954                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5955                         continue;
5956                 if (on)
5957                         ret = i40e_dev_rx_queue_start(dev, i);
5958                 else
5959                         ret = i40e_dev_rx_queue_stop(dev, i);
5960                 if (ret != I40E_SUCCESS)
5961                         return ret;
5962         }
5963
5964         return I40E_SUCCESS;
5965 }
5966
5967 /* Switch on or off all the rx/tx queues */
5968 int
5969 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5970 {
5971         int ret;
5972
5973         if (on) {
5974                 /* enable rx queues before enabling tx queues */
5975                 ret = i40e_dev_switch_rx_queues(pf, on);
5976                 if (ret) {
5977                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5978                         return ret;
5979                 }
5980                 ret = i40e_dev_switch_tx_queues(pf, on);
5981         } else {
5982                 /* Stop tx queues before stopping rx queues */
5983                 ret = i40e_dev_switch_tx_queues(pf, on);
5984                 if (ret) {
5985                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5986                         return ret;
5987                 }
5988                 ret = i40e_dev_switch_rx_queues(pf, on);
5989         }
5990
5991         return ret;
5992 }
5993
5994 /* Initialize VSI for TX */
5995 static int
5996 i40e_dev_tx_init(struct i40e_pf *pf)
5997 {
5998         struct rte_eth_dev_data *data = pf->dev_data;
5999         uint16_t i;
6000         uint32_t ret = I40E_SUCCESS;
6001         struct i40e_tx_queue *txq;
6002
6003         for (i = 0; i < data->nb_tx_queues; i++) {
6004                 txq = data->tx_queues[i];
6005                 if (!txq || !txq->q_set)
6006                         continue;
6007                 ret = i40e_tx_queue_init(txq);
6008                 if (ret != I40E_SUCCESS)
6009                         break;
6010         }
6011         if (ret == I40E_SUCCESS)
6012                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6013                                      ->eth_dev);
6014
6015         return ret;
6016 }
6017
6018 /* Initialize VSI for RX */
6019 static int
6020 i40e_dev_rx_init(struct i40e_pf *pf)
6021 {
6022         struct rte_eth_dev_data *data = pf->dev_data;
6023         int ret = I40E_SUCCESS;
6024         uint16_t i;
6025         struct i40e_rx_queue *rxq;
6026
6027         i40e_pf_config_mq_rx(pf);
6028         for (i = 0; i < data->nb_rx_queues; i++) {
6029                 rxq = data->rx_queues[i];
6030                 if (!rxq || !rxq->q_set)
6031                         continue;
6032
6033                 ret = i40e_rx_queue_init(rxq);
6034                 if (ret != I40E_SUCCESS) {
6035                         PMD_DRV_LOG(ERR,
6036                                 "Failed to do RX queue initialization");
6037                         break;
6038                 }
6039         }
6040         if (ret == I40E_SUCCESS)
6041                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6042                                      ->eth_dev);
6043
6044         return ret;
6045 }
6046
6047 static int
6048 i40e_dev_rxtx_init(struct i40e_pf *pf)
6049 {
6050         int err;
6051
6052         err = i40e_dev_tx_init(pf);
6053         if (err) {
6054                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6055                 return err;
6056         }
6057         err = i40e_dev_rx_init(pf);
6058         if (err) {
6059                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6060                 return err;
6061         }
6062
6063         return err;
6064 }
6065
6066 static int
6067 i40e_vmdq_setup(struct rte_eth_dev *dev)
6068 {
6069         struct rte_eth_conf *conf = &dev->data->dev_conf;
6070         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6071         int i, err, conf_vsis, j, loop;
6072         struct i40e_vsi *vsi;
6073         struct i40e_vmdq_info *vmdq_info;
6074         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6075         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6076
6077         /*
6078          * Disable interrupt to avoid message from VF. Furthermore, it will
6079          * avoid race condition in VSI creation/destroy.
6080          */
6081         i40e_pf_disable_irq0(hw);
6082
6083         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6084                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6085                 return -ENOTSUP;
6086         }
6087
6088         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6089         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6090                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6091                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6092                         pf->max_nb_vmdq_vsi);
6093                 return -ENOTSUP;
6094         }
6095
6096         if (pf->vmdq != NULL) {
6097                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6098                 return 0;
6099         }
6100
6101         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6102                                 sizeof(*vmdq_info) * conf_vsis, 0);
6103
6104         if (pf->vmdq == NULL) {
6105                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6106                 return -ENOMEM;
6107         }
6108
6109         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6110
6111         /* Create VMDQ VSI */
6112         for (i = 0; i < conf_vsis; i++) {
6113                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6114                                 vmdq_conf->enable_loop_back);
6115                 if (vsi == NULL) {
6116                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6117                         err = -1;
6118                         goto err_vsi_setup;
6119                 }
6120                 vmdq_info = &pf->vmdq[i];
6121                 vmdq_info->pf = pf;
6122                 vmdq_info->vsi = vsi;
6123         }
6124         pf->nb_cfg_vmdq_vsi = conf_vsis;
6125
6126         /* Configure Vlan */
6127         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6128         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6129                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6130                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6131                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6132                                         vmdq_conf->pool_map[i].vlan_id, j);
6133
6134                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6135                                                 vmdq_conf->pool_map[i].vlan_id);
6136                                 if (err) {
6137                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6138                                         err = -1;
6139                                         goto err_vsi_setup;
6140                                 }
6141                         }
6142                 }
6143         }
6144
6145         i40e_pf_enable_irq0(hw);
6146
6147         return 0;
6148
6149 err_vsi_setup:
6150         for (i = 0; i < conf_vsis; i++)
6151                 if (pf->vmdq[i].vsi == NULL)
6152                         break;
6153                 else
6154                         i40e_vsi_release(pf->vmdq[i].vsi);
6155
6156         rte_free(pf->vmdq);
6157         pf->vmdq = NULL;
6158         i40e_pf_enable_irq0(hw);
6159         return err;
6160 }
6161
6162 static void
6163 i40e_stat_update_32(struct i40e_hw *hw,
6164                    uint32_t reg,
6165                    bool offset_loaded,
6166                    uint64_t *offset,
6167                    uint64_t *stat)
6168 {
6169         uint64_t new_data;
6170
6171         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6172         if (!offset_loaded)
6173                 *offset = new_data;
6174
6175         if (new_data >= *offset)
6176                 *stat = (uint64_t)(new_data - *offset);
6177         else
6178                 *stat = (uint64_t)((new_data +
6179                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6180 }
6181
6182 static void
6183 i40e_stat_update_48(struct i40e_hw *hw,
6184                    uint32_t hireg,
6185                    uint32_t loreg,
6186                    bool offset_loaded,
6187                    uint64_t *offset,
6188                    uint64_t *stat)
6189 {
6190         uint64_t new_data;
6191
6192         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6193         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6194                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6195
6196         if (!offset_loaded)
6197                 *offset = new_data;
6198
6199         if (new_data >= *offset)
6200                 *stat = new_data - *offset;
6201         else
6202                 *stat = (uint64_t)((new_data +
6203                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6204
6205         *stat &= I40E_48_BIT_MASK;
6206 }
6207
6208 /* Disable IRQ0 */
6209 void
6210 i40e_pf_disable_irq0(struct i40e_hw *hw)
6211 {
6212         /* Disable all interrupt types */
6213         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6214                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6215         I40E_WRITE_FLUSH(hw);
6216 }
6217
6218 /* Enable IRQ0 */
6219 void
6220 i40e_pf_enable_irq0(struct i40e_hw *hw)
6221 {
6222         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6223                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6224                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6225                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6226         I40E_WRITE_FLUSH(hw);
6227 }
6228
6229 static void
6230 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6231 {
6232         /* read pending request and disable first */
6233         i40e_pf_disable_irq0(hw);
6234         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6235         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6236                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6237
6238         if (no_queue)
6239                 /* Link no queues with irq0 */
6240                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6241                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6242 }
6243
6244 static void
6245 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6246 {
6247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6248         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6249         int i;
6250         uint16_t abs_vf_id;
6251         uint32_t index, offset, val;
6252
6253         if (!pf->vfs)
6254                 return;
6255         /**
6256          * Try to find which VF trigger a reset, use absolute VF id to access
6257          * since the reg is global register.
6258          */
6259         for (i = 0; i < pf->vf_num; i++) {
6260                 abs_vf_id = hw->func_caps.vf_base_id + i;
6261                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6262                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6263                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6264                 /* VFR event occurred */
6265                 if (val & (0x1 << offset)) {
6266                         int ret;
6267
6268                         /* Clear the event first */
6269                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6270                                                         (0x1 << offset));
6271                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6272                         /**
6273                          * Only notify a VF reset event occurred,
6274                          * don't trigger another SW reset
6275                          */
6276                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6277                         if (ret != I40E_SUCCESS)
6278                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6279                 }
6280         }
6281 }
6282
6283 static void
6284 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6285 {
6286         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6287         int i;
6288
6289         for (i = 0; i < pf->vf_num; i++)
6290                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6291 }
6292
6293 static void
6294 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6295 {
6296         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6297         struct i40e_arq_event_info info;
6298         uint16_t pending, opcode;
6299         int ret;
6300
6301         info.buf_len = I40E_AQ_BUF_SZ;
6302         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6303         if (!info.msg_buf) {
6304                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6305                 return;
6306         }
6307
6308         pending = 1;
6309         while (pending) {
6310                 ret = i40e_clean_arq_element(hw, &info, &pending);
6311
6312                 if (ret != I40E_SUCCESS) {
6313                         PMD_DRV_LOG(INFO,
6314                                 "Failed to read msg from AdminQ, aq_err: %u",
6315                                 hw->aq.asq_last_status);
6316                         break;
6317                 }
6318                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6319
6320                 switch (opcode) {
6321                 case i40e_aqc_opc_send_msg_to_pf:
6322                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6323                         i40e_pf_host_handle_vf_msg(dev,
6324                                         rte_le_to_cpu_16(info.desc.retval),
6325                                         rte_le_to_cpu_32(info.desc.cookie_high),
6326                                         rte_le_to_cpu_32(info.desc.cookie_low),
6327                                         info.msg_buf,
6328                                         info.msg_len);
6329                         break;
6330                 case i40e_aqc_opc_get_link_status:
6331                         ret = i40e_dev_link_update(dev, 0);
6332                         if (!ret)
6333                                 _rte_eth_dev_callback_process(dev,
6334                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6335                         break;
6336                 default:
6337                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6338                                     opcode);
6339                         break;
6340                 }
6341         }
6342         rte_free(info.msg_buf);
6343 }
6344
6345 /**
6346  * Interrupt handler triggered by NIC  for handling
6347  * specific interrupt.
6348  *
6349  * @param handle
6350  *  Pointer to interrupt handle.
6351  * @param param
6352  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6353  *
6354  * @return
6355  *  void
6356  */
6357 static void
6358 i40e_dev_interrupt_handler(void *param)
6359 {
6360         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6361         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6362         uint32_t icr0;
6363
6364         /* Disable interrupt */
6365         i40e_pf_disable_irq0(hw);
6366
6367         /* read out interrupt causes */
6368         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6369
6370         /* No interrupt event indicated */
6371         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6372                 PMD_DRV_LOG(INFO, "No interrupt event");
6373                 goto done;
6374         }
6375         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6376                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6377         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6378                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6379         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6380                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6381         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6382                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6383         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6384                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6385         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6386                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6387         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6388                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6389
6390         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6391                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6392                 i40e_dev_handle_vfr_event(dev);
6393         }
6394         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6395                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6396                 i40e_dev_handle_aq_msg(dev);
6397         }
6398
6399 done:
6400         /* Enable interrupt */
6401         i40e_pf_enable_irq0(hw);
6402         rte_intr_enable(dev->intr_handle);
6403 }
6404
6405 int
6406 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6407                          struct i40e_macvlan_filter *filter,
6408                          int total)
6409 {
6410         int ele_num, ele_buff_size;
6411         int num, actual_num, i;
6412         uint16_t flags;
6413         int ret = I40E_SUCCESS;
6414         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6415         struct i40e_aqc_add_macvlan_element_data *req_list;
6416
6417         if (filter == NULL  || total == 0)
6418                 return I40E_ERR_PARAM;
6419         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6420         ele_buff_size = hw->aq.asq_buf_size;
6421
6422         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6423         if (req_list == NULL) {
6424                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6425                 return I40E_ERR_NO_MEMORY;
6426         }
6427
6428         num = 0;
6429         do {
6430                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6431                 memset(req_list, 0, ele_buff_size);
6432
6433                 for (i = 0; i < actual_num; i++) {
6434                         rte_memcpy(req_list[i].mac_addr,
6435                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6436                         req_list[i].vlan_tag =
6437                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6438
6439                         switch (filter[num + i].filter_type) {
6440                         case RTE_MAC_PERFECT_MATCH:
6441                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6442                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6443                                 break;
6444                         case RTE_MACVLAN_PERFECT_MATCH:
6445                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6446                                 break;
6447                         case RTE_MAC_HASH_MATCH:
6448                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6449                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6450                                 break;
6451                         case RTE_MACVLAN_HASH_MATCH:
6452                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6453                                 break;
6454                         default:
6455                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6456                                 ret = I40E_ERR_PARAM;
6457                                 goto DONE;
6458                         }
6459
6460                         req_list[i].queue_number = 0;
6461
6462                         req_list[i].flags = rte_cpu_to_le_16(flags);
6463                 }
6464
6465                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6466                                                 actual_num, NULL);
6467                 if (ret != I40E_SUCCESS) {
6468                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6469                         goto DONE;
6470                 }
6471                 num += actual_num;
6472         } while (num < total);
6473
6474 DONE:
6475         rte_free(req_list);
6476         return ret;
6477 }
6478
6479 int
6480 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6481                             struct i40e_macvlan_filter *filter,
6482                             int total)
6483 {
6484         int ele_num, ele_buff_size;
6485         int num, actual_num, i;
6486         uint16_t flags;
6487         int ret = I40E_SUCCESS;
6488         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6489         struct i40e_aqc_remove_macvlan_element_data *req_list;
6490
6491         if (filter == NULL  || total == 0)
6492                 return I40E_ERR_PARAM;
6493
6494         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6495         ele_buff_size = hw->aq.asq_buf_size;
6496
6497         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6498         if (req_list == NULL) {
6499                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6500                 return I40E_ERR_NO_MEMORY;
6501         }
6502
6503         num = 0;
6504         do {
6505                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6506                 memset(req_list, 0, ele_buff_size);
6507
6508                 for (i = 0; i < actual_num; i++) {
6509                         rte_memcpy(req_list[i].mac_addr,
6510                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6511                         req_list[i].vlan_tag =
6512                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6513
6514                         switch (filter[num + i].filter_type) {
6515                         case RTE_MAC_PERFECT_MATCH:
6516                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6517                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6518                                 break;
6519                         case RTE_MACVLAN_PERFECT_MATCH:
6520                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6521                                 break;
6522                         case RTE_MAC_HASH_MATCH:
6523                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6524                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6525                                 break;
6526                         case RTE_MACVLAN_HASH_MATCH:
6527                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6528                                 break;
6529                         default:
6530                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6531                                 ret = I40E_ERR_PARAM;
6532                                 goto DONE;
6533                         }
6534                         req_list[i].flags = rte_cpu_to_le_16(flags);
6535                 }
6536
6537                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6538                                                 actual_num, NULL);
6539                 if (ret != I40E_SUCCESS) {
6540                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6541                         goto DONE;
6542                 }
6543                 num += actual_num;
6544         } while (num < total);
6545
6546 DONE:
6547         rte_free(req_list);
6548         return ret;
6549 }
6550
6551 /* Find out specific MAC filter */
6552 static struct i40e_mac_filter *
6553 i40e_find_mac_filter(struct i40e_vsi *vsi,
6554                          struct ether_addr *macaddr)
6555 {
6556         struct i40e_mac_filter *f;
6557
6558         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6559                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6560                         return f;
6561         }
6562
6563         return NULL;
6564 }
6565
6566 static bool
6567 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6568                          uint16_t vlan_id)
6569 {
6570         uint32_t vid_idx, vid_bit;
6571
6572         if (vlan_id > ETH_VLAN_ID_MAX)
6573                 return 0;
6574
6575         vid_idx = I40E_VFTA_IDX(vlan_id);
6576         vid_bit = I40E_VFTA_BIT(vlan_id);
6577
6578         if (vsi->vfta[vid_idx] & vid_bit)
6579                 return 1;
6580         else
6581                 return 0;
6582 }
6583
6584 static void
6585 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6586                        uint16_t vlan_id, bool on)
6587 {
6588         uint32_t vid_idx, vid_bit;
6589
6590         vid_idx = I40E_VFTA_IDX(vlan_id);
6591         vid_bit = I40E_VFTA_BIT(vlan_id);
6592
6593         if (on)
6594                 vsi->vfta[vid_idx] |= vid_bit;
6595         else
6596                 vsi->vfta[vid_idx] &= ~vid_bit;
6597 }
6598
6599 void
6600 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6601                      uint16_t vlan_id, bool on)
6602 {
6603         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6604         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6605         int ret;
6606
6607         if (vlan_id > ETH_VLAN_ID_MAX)
6608                 return;
6609
6610         i40e_store_vlan_filter(vsi, vlan_id, on);
6611
6612         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6613                 return;
6614
6615         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6616
6617         if (on) {
6618                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6619                                        &vlan_data, 1, NULL);
6620                 if (ret != I40E_SUCCESS)
6621                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6622         } else {
6623                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6624                                           &vlan_data, 1, NULL);
6625                 if (ret != I40E_SUCCESS)
6626                         PMD_DRV_LOG(ERR,
6627                                     "Failed to remove vlan filter");
6628         }
6629 }
6630
6631 /**
6632  * Find all vlan options for specific mac addr,
6633  * return with actual vlan found.
6634  */
6635 int
6636 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6637                            struct i40e_macvlan_filter *mv_f,
6638                            int num, struct ether_addr *addr)
6639 {
6640         int i;
6641         uint32_t j, k;
6642
6643         /**
6644          * Not to use i40e_find_vlan_filter to decrease the loop time,
6645          * although the code looks complex.
6646           */
6647         if (num < vsi->vlan_num)
6648                 return I40E_ERR_PARAM;
6649
6650         i = 0;
6651         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6652                 if (vsi->vfta[j]) {
6653                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6654                                 if (vsi->vfta[j] & (1 << k)) {
6655                                         if (i > num - 1) {
6656                                                 PMD_DRV_LOG(ERR,
6657                                                         "vlan number doesn't match");
6658                                                 return I40E_ERR_PARAM;
6659                                         }
6660                                         rte_memcpy(&mv_f[i].macaddr,
6661                                                         addr, ETH_ADDR_LEN);
6662                                         mv_f[i].vlan_id =
6663                                                 j * I40E_UINT32_BIT_SIZE + k;
6664                                         i++;
6665                                 }
6666                         }
6667                 }
6668         }
6669         return I40E_SUCCESS;
6670 }
6671
6672 static inline int
6673 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6674                            struct i40e_macvlan_filter *mv_f,
6675                            int num,
6676                            uint16_t vlan)
6677 {
6678         int i = 0;
6679         struct i40e_mac_filter *f;
6680
6681         if (num < vsi->mac_num)
6682                 return I40E_ERR_PARAM;
6683
6684         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6685                 if (i > num - 1) {
6686                         PMD_DRV_LOG(ERR, "buffer number not match");
6687                         return I40E_ERR_PARAM;
6688                 }
6689                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6690                                 ETH_ADDR_LEN);
6691                 mv_f[i].vlan_id = vlan;
6692                 mv_f[i].filter_type = f->mac_info.filter_type;
6693                 i++;
6694         }
6695
6696         return I40E_SUCCESS;
6697 }
6698
6699 static int
6700 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6701 {
6702         int i, j, num;
6703         struct i40e_mac_filter *f;
6704         struct i40e_macvlan_filter *mv_f;
6705         int ret = I40E_SUCCESS;
6706
6707         if (vsi == NULL || vsi->mac_num == 0)
6708                 return I40E_ERR_PARAM;
6709
6710         /* Case that no vlan is set */
6711         if (vsi->vlan_num == 0)
6712                 num = vsi->mac_num;
6713         else
6714                 num = vsi->mac_num * vsi->vlan_num;
6715
6716         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6717         if (mv_f == NULL) {
6718                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6719                 return I40E_ERR_NO_MEMORY;
6720         }
6721
6722         i = 0;
6723         if (vsi->vlan_num == 0) {
6724                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6725                         rte_memcpy(&mv_f[i].macaddr,
6726                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6727                         mv_f[i].filter_type = f->mac_info.filter_type;
6728                         mv_f[i].vlan_id = 0;
6729                         i++;
6730                 }
6731         } else {
6732                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6733                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6734                                         vsi->vlan_num, &f->mac_info.mac_addr);
6735                         if (ret != I40E_SUCCESS)
6736                                 goto DONE;
6737                         for (j = i; j < i + vsi->vlan_num; j++)
6738                                 mv_f[j].filter_type = f->mac_info.filter_type;
6739                         i += vsi->vlan_num;
6740                 }
6741         }
6742
6743         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6744 DONE:
6745         rte_free(mv_f);
6746
6747         return ret;
6748 }
6749
6750 int
6751 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6752 {
6753         struct i40e_macvlan_filter *mv_f;
6754         int mac_num;
6755         int ret = I40E_SUCCESS;
6756
6757         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6758                 return I40E_ERR_PARAM;
6759
6760         /* If it's already set, just return */
6761         if (i40e_find_vlan_filter(vsi,vlan))
6762                 return I40E_SUCCESS;
6763
6764         mac_num = vsi->mac_num;
6765
6766         if (mac_num == 0) {
6767                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6768                 return I40E_ERR_PARAM;
6769         }
6770
6771         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6772
6773         if (mv_f == NULL) {
6774                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6775                 return I40E_ERR_NO_MEMORY;
6776         }
6777
6778         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6779
6780         if (ret != I40E_SUCCESS)
6781                 goto DONE;
6782
6783         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6784
6785         if (ret != I40E_SUCCESS)
6786                 goto DONE;
6787
6788         i40e_set_vlan_filter(vsi, vlan, 1);
6789
6790         vsi->vlan_num++;
6791         ret = I40E_SUCCESS;
6792 DONE:
6793         rte_free(mv_f);
6794         return ret;
6795 }
6796
6797 int
6798 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6799 {
6800         struct i40e_macvlan_filter *mv_f;
6801         int mac_num;
6802         int ret = I40E_SUCCESS;
6803
6804         /**
6805          * Vlan 0 is the generic filter for untagged packets
6806          * and can't be removed.
6807          */
6808         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6809                 return I40E_ERR_PARAM;
6810
6811         /* If can't find it, just return */
6812         if (!i40e_find_vlan_filter(vsi, vlan))
6813                 return I40E_ERR_PARAM;
6814
6815         mac_num = vsi->mac_num;
6816
6817         if (mac_num == 0) {
6818                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6819                 return I40E_ERR_PARAM;
6820         }
6821
6822         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6823
6824         if (mv_f == NULL) {
6825                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6826                 return I40E_ERR_NO_MEMORY;
6827         }
6828
6829         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6830
6831         if (ret != I40E_SUCCESS)
6832                 goto DONE;
6833
6834         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6835
6836         if (ret != I40E_SUCCESS)
6837                 goto DONE;
6838
6839         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6840         if (vsi->vlan_num == 1) {
6841                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6842                 if (ret != I40E_SUCCESS)
6843                         goto DONE;
6844
6845                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6846                 if (ret != I40E_SUCCESS)
6847                         goto DONE;
6848         }
6849
6850         i40e_set_vlan_filter(vsi, vlan, 0);
6851
6852         vsi->vlan_num--;
6853         ret = I40E_SUCCESS;
6854 DONE:
6855         rte_free(mv_f);
6856         return ret;
6857 }
6858
6859 int
6860 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6861 {
6862         struct i40e_mac_filter *f;
6863         struct i40e_macvlan_filter *mv_f;
6864         int i, vlan_num = 0;
6865         int ret = I40E_SUCCESS;
6866
6867         /* If it's add and we've config it, return */
6868         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6869         if (f != NULL)
6870                 return I40E_SUCCESS;
6871         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6872                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6873
6874                 /**
6875                  * If vlan_num is 0, that's the first time to add mac,
6876                  * set mask for vlan_id 0.
6877                  */
6878                 if (vsi->vlan_num == 0) {
6879                         i40e_set_vlan_filter(vsi, 0, 1);
6880                         vsi->vlan_num = 1;
6881                 }
6882                 vlan_num = vsi->vlan_num;
6883         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6884                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6885                 vlan_num = 1;
6886
6887         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6888         if (mv_f == NULL) {
6889                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6890                 return I40E_ERR_NO_MEMORY;
6891         }
6892
6893         for (i = 0; i < vlan_num; i++) {
6894                 mv_f[i].filter_type = mac_filter->filter_type;
6895                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6896                                 ETH_ADDR_LEN);
6897         }
6898
6899         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6900                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6901                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6902                                         &mac_filter->mac_addr);
6903                 if (ret != I40E_SUCCESS)
6904                         goto DONE;
6905         }
6906
6907         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6908         if (ret != I40E_SUCCESS)
6909                 goto DONE;
6910
6911         /* Add the mac addr into mac list */
6912         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6913         if (f == NULL) {
6914                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6915                 ret = I40E_ERR_NO_MEMORY;
6916                 goto DONE;
6917         }
6918         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6919                         ETH_ADDR_LEN);
6920         f->mac_info.filter_type = mac_filter->filter_type;
6921         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6922         vsi->mac_num++;
6923
6924         ret = I40E_SUCCESS;
6925 DONE:
6926         rte_free(mv_f);
6927
6928         return ret;
6929 }
6930
6931 int
6932 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6933 {
6934         struct i40e_mac_filter *f;
6935         struct i40e_macvlan_filter *mv_f;
6936         int i, vlan_num;
6937         enum rte_mac_filter_type filter_type;
6938         int ret = I40E_SUCCESS;
6939
6940         /* Can't find it, return an error */
6941         f = i40e_find_mac_filter(vsi, addr);
6942         if (f == NULL)
6943                 return I40E_ERR_PARAM;
6944
6945         vlan_num = vsi->vlan_num;
6946         filter_type = f->mac_info.filter_type;
6947         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6948                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6949                 if (vlan_num == 0) {
6950                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6951                         return I40E_ERR_PARAM;
6952                 }
6953         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6954                         filter_type == RTE_MAC_HASH_MATCH)
6955                 vlan_num = 1;
6956
6957         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6958         if (mv_f == NULL) {
6959                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6960                 return I40E_ERR_NO_MEMORY;
6961         }
6962
6963         for (i = 0; i < vlan_num; i++) {
6964                 mv_f[i].filter_type = filter_type;
6965                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6966                                 ETH_ADDR_LEN);
6967         }
6968         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6969                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6970                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6971                 if (ret != I40E_SUCCESS)
6972                         goto DONE;
6973         }
6974
6975         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6976         if (ret != I40E_SUCCESS)
6977                 goto DONE;
6978
6979         /* Remove the mac addr into mac list */
6980         TAILQ_REMOVE(&vsi->mac_list, f, next);
6981         rte_free(f);
6982         vsi->mac_num--;
6983
6984         ret = I40E_SUCCESS;
6985 DONE:
6986         rte_free(mv_f);
6987         return ret;
6988 }
6989
6990 /* Configure hash enable flags for RSS */
6991 uint64_t
6992 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6993 {
6994         uint64_t hena = 0;
6995         int i;
6996
6997         if (!flags)
6998                 return hena;
6999
7000         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7001                 if (flags & (1ULL << i))
7002                         hena |= adapter->pctypes_tbl[i];
7003         }
7004
7005         return hena;
7006 }
7007
7008 /* Parse the hash enable flags */
7009 uint64_t
7010 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7011 {
7012         uint64_t rss_hf = 0;
7013
7014         if (!flags)
7015                 return rss_hf;
7016         int i;
7017
7018         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7019                 if (flags & adapter->pctypes_tbl[i])
7020                         rss_hf |= (1ULL << i);
7021         }
7022         return rss_hf;
7023 }
7024
7025 /* Disable RSS */
7026 static void
7027 i40e_pf_disable_rss(struct i40e_pf *pf)
7028 {
7029         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7030
7031         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7032         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7033         I40E_WRITE_FLUSH(hw);
7034 }
7035
7036 int
7037 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7038 {
7039         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7040         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7041         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7042                            I40E_VFQF_HKEY_MAX_INDEX :
7043                            I40E_PFQF_HKEY_MAX_INDEX;
7044         int ret = 0;
7045
7046         if (!key || key_len == 0) {
7047                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7048                 return 0;
7049         } else if (key_len != (key_idx + 1) *
7050                 sizeof(uint32_t)) {
7051                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7052                 return -EINVAL;
7053         }
7054
7055         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7056                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7057                         (struct i40e_aqc_get_set_rss_key_data *)key;
7058
7059                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7060                 if (ret)
7061                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7062         } else {
7063                 uint32_t *hash_key = (uint32_t *)key;
7064                 uint16_t i;
7065
7066                 if (vsi->type == I40E_VSI_SRIOV) {
7067                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7068                                 I40E_WRITE_REG(
7069                                         hw,
7070                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7071                                         hash_key[i]);
7072
7073                 } else {
7074                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7075                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7076                                                hash_key[i]);
7077                 }
7078                 I40E_WRITE_FLUSH(hw);
7079         }
7080
7081         return ret;
7082 }
7083
7084 static int
7085 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7086 {
7087         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7088         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7089         uint32_t reg;
7090         int ret;
7091
7092         if (!key || !key_len)
7093                 return -EINVAL;
7094
7095         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7096                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7097                         (struct i40e_aqc_get_set_rss_key_data *)key);
7098                 if (ret) {
7099                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7100                         return ret;
7101                 }
7102         } else {
7103                 uint32_t *key_dw = (uint32_t *)key;
7104                 uint16_t i;
7105
7106                 if (vsi->type == I40E_VSI_SRIOV) {
7107                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7108                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7109                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7110                         }
7111                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7112                                    sizeof(uint32_t);
7113                 } else {
7114                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7115                                 reg = I40E_PFQF_HKEY(i);
7116                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7117                         }
7118                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7119                                    sizeof(uint32_t);
7120                 }
7121         }
7122         return 0;
7123 }
7124
7125 static int
7126 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7127 {
7128         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7129         uint64_t hena;
7130         int ret;
7131
7132         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7133                                rss_conf->rss_key_len);
7134         if (ret)
7135                 return ret;
7136
7137         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7138         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7139         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7140         I40E_WRITE_FLUSH(hw);
7141
7142         return 0;
7143 }
7144
7145 static int
7146 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7147                          struct rte_eth_rss_conf *rss_conf)
7148 {
7149         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7152         uint64_t hena;
7153
7154         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7155         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7156
7157         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7158                 if (rss_hf != 0) /* Enable RSS */
7159                         return -EINVAL;
7160                 return 0; /* Nothing to do */
7161         }
7162         /* RSS enabled */
7163         if (rss_hf == 0) /* Disable RSS */
7164                 return -EINVAL;
7165
7166         return i40e_hw_rss_hash_set(pf, rss_conf);
7167 }
7168
7169 static int
7170 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7171                            struct rte_eth_rss_conf *rss_conf)
7172 {
7173         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7174         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7175         uint64_t hena;
7176
7177         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7178                          &rss_conf->rss_key_len);
7179
7180         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7181         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7182         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7183
7184         return 0;
7185 }
7186
7187 static int
7188 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7189 {
7190         switch (filter_type) {
7191         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7192                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7193                 break;
7194         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7195                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7196                 break;
7197         case RTE_TUNNEL_FILTER_IMAC_TENID:
7198                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7199                 break;
7200         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7201                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7202                 break;
7203         case ETH_TUNNEL_FILTER_IMAC:
7204                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7205                 break;
7206         case ETH_TUNNEL_FILTER_OIP:
7207                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7208                 break;
7209         case ETH_TUNNEL_FILTER_IIP:
7210                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7211                 break;
7212         default:
7213                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7214                 return -EINVAL;
7215         }
7216
7217         return 0;
7218 }
7219
7220 /* Convert tunnel filter structure */
7221 static int
7222 i40e_tunnel_filter_convert(
7223         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7224         struct i40e_tunnel_filter *tunnel_filter)
7225 {
7226         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7227                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7228         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7229                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7230         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7231         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7232              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7233             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7234                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7235         else
7236                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7237         tunnel_filter->input.flags = cld_filter->element.flags;
7238         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7239         tunnel_filter->queue = cld_filter->element.queue_number;
7240         rte_memcpy(tunnel_filter->input.general_fields,
7241                    cld_filter->general_fields,
7242                    sizeof(cld_filter->general_fields));
7243
7244         return 0;
7245 }
7246
7247 /* Check if there exists the tunnel filter */
7248 struct i40e_tunnel_filter *
7249 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7250                              const struct i40e_tunnel_filter_input *input)
7251 {
7252         int ret;
7253
7254         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7255         if (ret < 0)
7256                 return NULL;
7257
7258         return tunnel_rule->hash_map[ret];
7259 }
7260
7261 /* Add a tunnel filter into the SW list */
7262 static int
7263 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7264                              struct i40e_tunnel_filter *tunnel_filter)
7265 {
7266         struct i40e_tunnel_rule *rule = &pf->tunnel;
7267         int ret;
7268
7269         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7270         if (ret < 0) {
7271                 PMD_DRV_LOG(ERR,
7272                             "Failed to insert tunnel filter to hash table %d!",
7273                             ret);
7274                 return ret;
7275         }
7276         rule->hash_map[ret] = tunnel_filter;
7277
7278         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7279
7280         return 0;
7281 }
7282
7283 /* Delete a tunnel filter from the SW list */
7284 int
7285 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7286                           struct i40e_tunnel_filter_input *input)
7287 {
7288         struct i40e_tunnel_rule *rule = &pf->tunnel;
7289         struct i40e_tunnel_filter *tunnel_filter;
7290         int ret;
7291
7292         ret = rte_hash_del_key(rule->hash_table, input);
7293         if (ret < 0) {
7294                 PMD_DRV_LOG(ERR,
7295                             "Failed to delete tunnel filter to hash table %d!",
7296                             ret);
7297                 return ret;
7298         }
7299         tunnel_filter = rule->hash_map[ret];
7300         rule->hash_map[ret] = NULL;
7301
7302         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7303         rte_free(tunnel_filter);
7304
7305         return 0;
7306 }
7307
7308 int
7309 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7310                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7311                         uint8_t add)
7312 {
7313         uint16_t ip_type;
7314         uint32_t ipv4_addr, ipv4_addr_le;
7315         uint8_t i, tun_type = 0;
7316         /* internal varialbe to convert ipv6 byte order */
7317         uint32_t convert_ipv6[4];
7318         int val, ret = 0;
7319         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7320         struct i40e_vsi *vsi = pf->main_vsi;
7321         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7322         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7323         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7324         struct i40e_tunnel_filter *tunnel, *node;
7325         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7326
7327         cld_filter = rte_zmalloc("tunnel_filter",
7328                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7329         0);
7330
7331         if (NULL == cld_filter) {
7332                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7333                 return -ENOMEM;
7334         }
7335         pfilter = cld_filter;
7336
7337         ether_addr_copy(&tunnel_filter->outer_mac,
7338                         (struct ether_addr *)&pfilter->element.outer_mac);
7339         ether_addr_copy(&tunnel_filter->inner_mac,
7340                         (struct ether_addr *)&pfilter->element.inner_mac);
7341
7342         pfilter->element.inner_vlan =
7343                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7344         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7345                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7346                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7347                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7348                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7349                                 &ipv4_addr_le,
7350                                 sizeof(pfilter->element.ipaddr.v4.data));
7351         } else {
7352                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7353                 for (i = 0; i < 4; i++) {
7354                         convert_ipv6[i] =
7355                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7356                 }
7357                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7358                            &convert_ipv6,
7359                            sizeof(pfilter->element.ipaddr.v6.data));
7360         }
7361
7362         /* check tunneled type */
7363         switch (tunnel_filter->tunnel_type) {
7364         case RTE_TUNNEL_TYPE_VXLAN:
7365                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7366                 break;
7367         case RTE_TUNNEL_TYPE_NVGRE:
7368                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7369                 break;
7370         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7371                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7372                 break;
7373         default:
7374                 /* Other tunnel types is not supported. */
7375                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7376                 rte_free(cld_filter);
7377                 return -EINVAL;
7378         }
7379
7380         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7381                                        &pfilter->element.flags);
7382         if (val < 0) {
7383                 rte_free(cld_filter);
7384                 return -EINVAL;
7385         }
7386
7387         pfilter->element.flags |= rte_cpu_to_le_16(
7388                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7389                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7390         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7391         pfilter->element.queue_number =
7392                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7393
7394         /* Check if there is the filter in SW list */
7395         memset(&check_filter, 0, sizeof(check_filter));
7396         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7397         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7398         if (add && node) {
7399                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7400                 rte_free(cld_filter);
7401                 return -EINVAL;
7402         }
7403
7404         if (!add && !node) {
7405                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7406                 rte_free(cld_filter);
7407                 return -EINVAL;
7408         }
7409
7410         if (add) {
7411                 ret = i40e_aq_add_cloud_filters(hw,
7412                                         vsi->seid, &cld_filter->element, 1);
7413                 if (ret < 0) {
7414                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7415                         rte_free(cld_filter);
7416                         return -ENOTSUP;
7417                 }
7418                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7419                 if (tunnel == NULL) {
7420                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7421                         rte_free(cld_filter);
7422                         return -ENOMEM;
7423                 }
7424
7425                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7426                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7427                 if (ret < 0)
7428                         rte_free(tunnel);
7429         } else {
7430                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7431                                                    &cld_filter->element, 1);
7432                 if (ret < 0) {
7433                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7434                         rte_free(cld_filter);
7435                         return -ENOTSUP;
7436                 }
7437                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7438         }
7439
7440         rte_free(cld_filter);
7441         return ret;
7442 }
7443
7444 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7445 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7446 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7447 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7448 #define I40E_TR_GRE_KEY_MASK                    0x400
7449 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7450 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7451
7452 static enum
7453 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7454 {
7455         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7456         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7457         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7458         enum i40e_status_code status = I40E_SUCCESS;
7459
7460         if (pf->support_multi_driver) {
7461                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7462                 return I40E_NOT_SUPPORTED;
7463         }
7464
7465         memset(&filter_replace, 0,
7466                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7467         memset(&filter_replace_buf, 0,
7468                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7469
7470         /* create L1 filter */
7471         filter_replace.old_filter_type =
7472                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7473         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7474         filter_replace.tr_bit = 0;
7475
7476         /* Prepare the buffer, 3 entries */
7477         filter_replace_buf.data[0] =
7478                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7479         filter_replace_buf.data[0] |=
7480                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7481         filter_replace_buf.data[2] = 0xFF;
7482         filter_replace_buf.data[3] = 0xFF;
7483         filter_replace_buf.data[4] =
7484                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7485         filter_replace_buf.data[4] |=
7486                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7487         filter_replace_buf.data[7] = 0xF0;
7488         filter_replace_buf.data[8]
7489                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7490         filter_replace_buf.data[8] |=
7491                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7492         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7493                 I40E_TR_GENEVE_KEY_MASK |
7494                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7495         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7496                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7497                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7498
7499         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7500                                                &filter_replace_buf);
7501         if (!status) {
7502                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7503                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7504                             "cloud l1 type is changed from 0x%x to 0x%x",
7505                             filter_replace.old_filter_type,
7506                             filter_replace.new_filter_type);
7507         }
7508         return status;
7509 }
7510
7511 static enum
7512 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7513 {
7514         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7515         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7516         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7517         enum i40e_status_code status = I40E_SUCCESS;
7518
7519         if (pf->support_multi_driver) {
7520                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7521                 return I40E_NOT_SUPPORTED;
7522         }
7523
7524         /* For MPLSoUDP */
7525         memset(&filter_replace, 0,
7526                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7527         memset(&filter_replace_buf, 0,
7528                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7529         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7530                 I40E_AQC_MIRROR_CLOUD_FILTER;
7531         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7532         filter_replace.new_filter_type =
7533                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7534         /* Prepare the buffer, 2 entries */
7535         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7536         filter_replace_buf.data[0] |=
7537                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7538         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7539         filter_replace_buf.data[4] |=
7540                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7541         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7542                                                &filter_replace_buf);
7543         if (status < 0)
7544                 return status;
7545         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7546                     "cloud filter type is changed from 0x%x to 0x%x",
7547                     filter_replace.old_filter_type,
7548                     filter_replace.new_filter_type);
7549
7550         /* For MPLSoGRE */
7551         memset(&filter_replace, 0,
7552                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7553         memset(&filter_replace_buf, 0,
7554                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7555
7556         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7557                 I40E_AQC_MIRROR_CLOUD_FILTER;
7558         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7559         filter_replace.new_filter_type =
7560                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7561         /* Prepare the buffer, 2 entries */
7562         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7563         filter_replace_buf.data[0] |=
7564                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7565         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7566         filter_replace_buf.data[4] |=
7567                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7568
7569         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7570                                                &filter_replace_buf);
7571         if (!status) {
7572                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7573                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7574                             "cloud filter type is changed from 0x%x to 0x%x",
7575                             filter_replace.old_filter_type,
7576                             filter_replace.new_filter_type);
7577         }
7578         return status;
7579 }
7580
7581 static enum i40e_status_code
7582 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7583 {
7584         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7585         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7586         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7587         enum i40e_status_code status = I40E_SUCCESS;
7588
7589         if (pf->support_multi_driver) {
7590                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7591                 return I40E_NOT_SUPPORTED;
7592         }
7593
7594         /* For GTP-C */
7595         memset(&filter_replace, 0,
7596                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7597         memset(&filter_replace_buf, 0,
7598                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7599         /* create L1 filter */
7600         filter_replace.old_filter_type =
7601                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7602         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7603         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7604                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7605         /* Prepare the buffer, 2 entries */
7606         filter_replace_buf.data[0] =
7607                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7608         filter_replace_buf.data[0] |=
7609                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7610         filter_replace_buf.data[2] = 0xFF;
7611         filter_replace_buf.data[3] = 0xFF;
7612         filter_replace_buf.data[4] =
7613                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7614         filter_replace_buf.data[4] |=
7615                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7616         filter_replace_buf.data[6] = 0xFF;
7617         filter_replace_buf.data[7] = 0xFF;
7618         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7619                                                &filter_replace_buf);
7620         if (status < 0)
7621                 return status;
7622         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7623                     "cloud l1 type is changed from 0x%x to 0x%x",
7624                     filter_replace.old_filter_type,
7625                     filter_replace.new_filter_type);
7626
7627         /* for GTP-U */
7628         memset(&filter_replace, 0,
7629                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7630         memset(&filter_replace_buf, 0,
7631                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7632         /* create L1 filter */
7633         filter_replace.old_filter_type =
7634                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7635         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7636         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7637                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7638         /* Prepare the buffer, 2 entries */
7639         filter_replace_buf.data[0] =
7640                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7641         filter_replace_buf.data[0] |=
7642                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7643         filter_replace_buf.data[2] = 0xFF;
7644         filter_replace_buf.data[3] = 0xFF;
7645         filter_replace_buf.data[4] =
7646                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7647         filter_replace_buf.data[4] |=
7648                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7649         filter_replace_buf.data[6] = 0xFF;
7650         filter_replace_buf.data[7] = 0xFF;
7651
7652         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7653                                                &filter_replace_buf);
7654         if (!status) {
7655                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7656                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7657                             "cloud l1 type is changed from 0x%x to 0x%x",
7658                             filter_replace.old_filter_type,
7659                             filter_replace.new_filter_type);
7660         }
7661         return status;
7662 }
7663
7664 static enum
7665 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7666 {
7667         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7668         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7669         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7670         enum i40e_status_code status = I40E_SUCCESS;
7671
7672         if (pf->support_multi_driver) {
7673                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7674                 return I40E_NOT_SUPPORTED;
7675         }
7676
7677         /* for GTP-C */
7678         memset(&filter_replace, 0,
7679                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7680         memset(&filter_replace_buf, 0,
7681                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7682         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7683         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7684         filter_replace.new_filter_type =
7685                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7686         /* Prepare the buffer, 2 entries */
7687         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7688         filter_replace_buf.data[0] |=
7689                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7690         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7691         filter_replace_buf.data[4] |=
7692                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7693         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7694                                                &filter_replace_buf);
7695         if (status < 0)
7696                 return status;
7697         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7698                     "cloud filter type is changed from 0x%x to 0x%x",
7699                     filter_replace.old_filter_type,
7700                     filter_replace.new_filter_type);
7701
7702         /* for GTP-U */
7703         memset(&filter_replace, 0,
7704                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7705         memset(&filter_replace_buf, 0,
7706                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7707         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7708         filter_replace.old_filter_type =
7709                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7710         filter_replace.new_filter_type =
7711                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7712         /* Prepare the buffer, 2 entries */
7713         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7714         filter_replace_buf.data[0] |=
7715                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7716         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7717         filter_replace_buf.data[4] |=
7718                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7719
7720         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7721                                                &filter_replace_buf);
7722         if (!status) {
7723                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7724                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7725                             "cloud filter type is changed from 0x%x to 0x%x",
7726                             filter_replace.old_filter_type,
7727                             filter_replace.new_filter_type);
7728         }
7729         return status;
7730 }
7731
7732 int
7733 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7734                       struct i40e_tunnel_filter_conf *tunnel_filter,
7735                       uint8_t add)
7736 {
7737         uint16_t ip_type;
7738         uint32_t ipv4_addr, ipv4_addr_le;
7739         uint8_t i, tun_type = 0;
7740         /* internal variable to convert ipv6 byte order */
7741         uint32_t convert_ipv6[4];
7742         int val, ret = 0;
7743         struct i40e_pf_vf *vf = NULL;
7744         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7745         struct i40e_vsi *vsi;
7746         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7747         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7748         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7749         struct i40e_tunnel_filter *tunnel, *node;
7750         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7751         uint32_t teid_le;
7752         bool big_buffer = 0;
7753
7754         cld_filter = rte_zmalloc("tunnel_filter",
7755                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7756                          0);
7757
7758         if (cld_filter == NULL) {
7759                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7760                 return -ENOMEM;
7761         }
7762         pfilter = cld_filter;
7763
7764         ether_addr_copy(&tunnel_filter->outer_mac,
7765                         (struct ether_addr *)&pfilter->element.outer_mac);
7766         ether_addr_copy(&tunnel_filter->inner_mac,
7767                         (struct ether_addr *)&pfilter->element.inner_mac);
7768
7769         pfilter->element.inner_vlan =
7770                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7771         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7772                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7773                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7774                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7775                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7776                                 &ipv4_addr_le,
7777                                 sizeof(pfilter->element.ipaddr.v4.data));
7778         } else {
7779                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7780                 for (i = 0; i < 4; i++) {
7781                         convert_ipv6[i] =
7782                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7783                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7784                 }
7785                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7786                            &convert_ipv6,
7787                            sizeof(pfilter->element.ipaddr.v6.data));
7788         }
7789
7790         /* check tunneled type */
7791         switch (tunnel_filter->tunnel_type) {
7792         case I40E_TUNNEL_TYPE_VXLAN:
7793                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7794                 break;
7795         case I40E_TUNNEL_TYPE_NVGRE:
7796                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7797                 break;
7798         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7799                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7800                 break;
7801         case I40E_TUNNEL_TYPE_MPLSoUDP:
7802                 if (!pf->mpls_replace_flag) {
7803                         i40e_replace_mpls_l1_filter(pf);
7804                         i40e_replace_mpls_cloud_filter(pf);
7805                         pf->mpls_replace_flag = 1;
7806                 }
7807                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7808                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7809                         teid_le >> 4;
7810                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7811                         (teid_le & 0xF) << 12;
7812                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7813                         0x40;
7814                 big_buffer = 1;
7815                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7816                 break;
7817         case I40E_TUNNEL_TYPE_MPLSoGRE:
7818                 if (!pf->mpls_replace_flag) {
7819                         i40e_replace_mpls_l1_filter(pf);
7820                         i40e_replace_mpls_cloud_filter(pf);
7821                         pf->mpls_replace_flag = 1;
7822                 }
7823                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7824                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7825                         teid_le >> 4;
7826                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7827                         (teid_le & 0xF) << 12;
7828                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7829                         0x0;
7830                 big_buffer = 1;
7831                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7832                 break;
7833         case I40E_TUNNEL_TYPE_GTPC:
7834                 if (!pf->gtp_replace_flag) {
7835                         i40e_replace_gtp_l1_filter(pf);
7836                         i40e_replace_gtp_cloud_filter(pf);
7837                         pf->gtp_replace_flag = 1;
7838                 }
7839                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7840                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7841                         (teid_le >> 16) & 0xFFFF;
7842                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7843                         teid_le & 0xFFFF;
7844                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7845                         0x0;
7846                 big_buffer = 1;
7847                 break;
7848         case I40E_TUNNEL_TYPE_GTPU:
7849                 if (!pf->gtp_replace_flag) {
7850                         i40e_replace_gtp_l1_filter(pf);
7851                         i40e_replace_gtp_cloud_filter(pf);
7852                         pf->gtp_replace_flag = 1;
7853                 }
7854                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7855                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7856                         (teid_le >> 16) & 0xFFFF;
7857                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7858                         teid_le & 0xFFFF;
7859                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7860                         0x0;
7861                 big_buffer = 1;
7862                 break;
7863         case I40E_TUNNEL_TYPE_QINQ:
7864                 if (!pf->qinq_replace_flag) {
7865                         ret = i40e_cloud_filter_qinq_create(pf);
7866                         if (ret < 0)
7867                                 PMD_DRV_LOG(DEBUG,
7868                                             "QinQ tunnel filter already created.");
7869                         pf->qinq_replace_flag = 1;
7870                 }
7871                 /*      Add in the General fields the values of
7872                  *      the Outer and Inner VLAN
7873                  *      Big Buffer should be set, see changes in
7874                  *      i40e_aq_add_cloud_filters
7875                  */
7876                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7877                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7878                 big_buffer = 1;
7879                 break;
7880         default:
7881                 /* Other tunnel types is not supported. */
7882                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7883                 rte_free(cld_filter);
7884                 return -EINVAL;
7885         }
7886
7887         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7888                 pfilter->element.flags =
7889                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7890         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7891                 pfilter->element.flags =
7892                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7893         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7894                 pfilter->element.flags =
7895                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7896         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7897                 pfilter->element.flags =
7898                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7899         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7900                 pfilter->element.flags |=
7901                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7902         else {
7903                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7904                                                 &pfilter->element.flags);
7905                 if (val < 0) {
7906                         rte_free(cld_filter);
7907                         return -EINVAL;
7908                 }
7909         }
7910
7911         pfilter->element.flags |= rte_cpu_to_le_16(
7912                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7913                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7914         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7915         pfilter->element.queue_number =
7916                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7917
7918         if (!tunnel_filter->is_to_vf)
7919                 vsi = pf->main_vsi;
7920         else {
7921                 if (tunnel_filter->vf_id >= pf->vf_num) {
7922                         PMD_DRV_LOG(ERR, "Invalid argument.");
7923                         rte_free(cld_filter);
7924                         return -EINVAL;
7925                 }
7926                 vf = &pf->vfs[tunnel_filter->vf_id];
7927                 vsi = vf->vsi;
7928         }
7929
7930         /* Check if there is the filter in SW list */
7931         memset(&check_filter, 0, sizeof(check_filter));
7932         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7933         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7934         check_filter.vf_id = tunnel_filter->vf_id;
7935         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7936         if (add && node) {
7937                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7938                 rte_free(cld_filter);
7939                 return -EINVAL;
7940         }
7941
7942         if (!add && !node) {
7943                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7944                 rte_free(cld_filter);
7945                 return -EINVAL;
7946         }
7947
7948         if (add) {
7949                 if (big_buffer)
7950                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7951                                                    vsi->seid, cld_filter, 1);
7952                 else
7953                         ret = i40e_aq_add_cloud_filters(hw,
7954                                         vsi->seid, &cld_filter->element, 1);
7955                 if (ret < 0) {
7956                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7957                         rte_free(cld_filter);
7958                         return -ENOTSUP;
7959                 }
7960                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7961                 if (tunnel == NULL) {
7962                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7963                         rte_free(cld_filter);
7964                         return -ENOMEM;
7965                 }
7966
7967                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7968                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7969                 if (ret < 0)
7970                         rte_free(tunnel);
7971         } else {
7972                 if (big_buffer)
7973                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7974                                 hw, vsi->seid, cld_filter, 1);
7975                 else
7976                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7977                                                    &cld_filter->element, 1);
7978                 if (ret < 0) {
7979                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7980                         rte_free(cld_filter);
7981                         return -ENOTSUP;
7982                 }
7983                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7984         }
7985
7986         rte_free(cld_filter);
7987         return ret;
7988 }
7989
7990 static int
7991 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7992 {
7993         uint8_t i;
7994
7995         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7996                 if (pf->vxlan_ports[i] == port)
7997                         return i;
7998         }
7999
8000         return -1;
8001 }
8002
8003 static int
8004 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8005 {
8006         int  idx, ret;
8007         uint8_t filter_idx;
8008         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8009
8010         idx = i40e_get_vxlan_port_idx(pf, port);
8011
8012         /* Check if port already exists */
8013         if (idx >= 0) {
8014                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8015                 return -EINVAL;
8016         }
8017
8018         /* Now check if there is space to add the new port */
8019         idx = i40e_get_vxlan_port_idx(pf, 0);
8020         if (idx < 0) {
8021                 PMD_DRV_LOG(ERR,
8022                         "Maximum number of UDP ports reached, not adding port %d",
8023                         port);
8024                 return -ENOSPC;
8025         }
8026
8027         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8028                                         &filter_idx, NULL);
8029         if (ret < 0) {
8030                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8031                 return -1;
8032         }
8033
8034         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8035                          port,  filter_idx);
8036
8037         /* New port: add it and mark its index in the bitmap */
8038         pf->vxlan_ports[idx] = port;
8039         pf->vxlan_bitmap |= (1 << idx);
8040
8041         if (!(pf->flags & I40E_FLAG_VXLAN))
8042                 pf->flags |= I40E_FLAG_VXLAN;
8043
8044         return 0;
8045 }
8046
8047 static int
8048 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8049 {
8050         int idx;
8051         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8052
8053         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8054                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8055                 return -EINVAL;
8056         }
8057
8058         idx = i40e_get_vxlan_port_idx(pf, port);
8059
8060         if (idx < 0) {
8061                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8062                 return -EINVAL;
8063         }
8064
8065         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8066                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8067                 return -1;
8068         }
8069
8070         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8071                         port, idx);
8072
8073         pf->vxlan_ports[idx] = 0;
8074         pf->vxlan_bitmap &= ~(1 << idx);
8075
8076         if (!pf->vxlan_bitmap)
8077                 pf->flags &= ~I40E_FLAG_VXLAN;
8078
8079         return 0;
8080 }
8081
8082 /* Add UDP tunneling port */
8083 static int
8084 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8085                              struct rte_eth_udp_tunnel *udp_tunnel)
8086 {
8087         int ret = 0;
8088         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8089
8090         if (udp_tunnel == NULL)
8091                 return -EINVAL;
8092
8093         switch (udp_tunnel->prot_type) {
8094         case RTE_TUNNEL_TYPE_VXLAN:
8095                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8096                 break;
8097
8098         case RTE_TUNNEL_TYPE_GENEVE:
8099         case RTE_TUNNEL_TYPE_TEREDO:
8100                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8101                 ret = -1;
8102                 break;
8103
8104         default:
8105                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8106                 ret = -1;
8107                 break;
8108         }
8109
8110         return ret;
8111 }
8112
8113 /* Remove UDP tunneling port */
8114 static int
8115 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8116                              struct rte_eth_udp_tunnel *udp_tunnel)
8117 {
8118         int ret = 0;
8119         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8120
8121         if (udp_tunnel == NULL)
8122                 return -EINVAL;
8123
8124         switch (udp_tunnel->prot_type) {
8125         case RTE_TUNNEL_TYPE_VXLAN:
8126                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8127                 break;
8128         case RTE_TUNNEL_TYPE_GENEVE:
8129         case RTE_TUNNEL_TYPE_TEREDO:
8130                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8131                 ret = -1;
8132                 break;
8133         default:
8134                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8135                 ret = -1;
8136                 break;
8137         }
8138
8139         return ret;
8140 }
8141
8142 /* Calculate the maximum number of contiguous PF queues that are configured */
8143 static int
8144 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8145 {
8146         struct rte_eth_dev_data *data = pf->dev_data;
8147         int i, num;
8148         struct i40e_rx_queue *rxq;
8149
8150         num = 0;
8151         for (i = 0; i < pf->lan_nb_qps; i++) {
8152                 rxq = data->rx_queues[i];
8153                 if (rxq && rxq->q_set)
8154                         num++;
8155                 else
8156                         break;
8157         }
8158
8159         return num;
8160 }
8161
8162 /* Configure RSS */
8163 static int
8164 i40e_pf_config_rss(struct i40e_pf *pf)
8165 {
8166         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8167         struct rte_eth_rss_conf rss_conf;
8168         uint32_t i, lut = 0;
8169         uint16_t j, num;
8170
8171         /*
8172          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8173          * It's necessary to calculate the actual PF queues that are configured.
8174          */
8175         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8176                 num = i40e_pf_calc_configured_queues_num(pf);
8177         else
8178                 num = pf->dev_data->nb_rx_queues;
8179
8180         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8181         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8182                         num);
8183
8184         if (num == 0) {
8185                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8186                 return -ENOTSUP;
8187         }
8188
8189         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8190                 if (j == num)
8191                         j = 0;
8192                 lut = (lut << 8) | (j & ((0x1 <<
8193                         hw->func_caps.rss_table_entry_width) - 1));
8194                 if ((i & 3) == 3)
8195                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8196         }
8197
8198         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8199         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8200                 i40e_pf_disable_rss(pf);
8201                 return 0;
8202         }
8203         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8204                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8205                 /* Random default keys */
8206                 static uint32_t rss_key_default[] = {0x6b793944,
8207                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8208                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8209                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8210
8211                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8212                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8213                                                         sizeof(uint32_t);
8214         }
8215
8216         return i40e_hw_rss_hash_set(pf, &rss_conf);
8217 }
8218
8219 static int
8220 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8221                                struct rte_eth_tunnel_filter_conf *filter)
8222 {
8223         if (pf == NULL || filter == NULL) {
8224                 PMD_DRV_LOG(ERR, "Invalid parameter");
8225                 return -EINVAL;
8226         }
8227
8228         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8229                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8230                 return -EINVAL;
8231         }
8232
8233         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8234                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8235                 return -EINVAL;
8236         }
8237
8238         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8239                 (is_zero_ether_addr(&filter->outer_mac))) {
8240                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8241                 return -EINVAL;
8242         }
8243
8244         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8245                 (is_zero_ether_addr(&filter->inner_mac))) {
8246                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8247                 return -EINVAL;
8248         }
8249
8250         return 0;
8251 }
8252
8253 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8254 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8255 static int
8256 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8257 {
8258         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8259         uint32_t val, reg;
8260         int ret = -EINVAL;
8261
8262         if (pf->support_multi_driver) {
8263                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8264                 return -ENOTSUP;
8265         }
8266
8267         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8268         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8269
8270         if (len == 3) {
8271                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8272         } else if (len == 4) {
8273                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8274         } else {
8275                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8276                 return ret;
8277         }
8278
8279         if (reg != val) {
8280                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8281                                                    reg, NULL);
8282                 if (ret != 0)
8283                         return ret;
8284                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8285                             "with value 0x%08x",
8286                             I40E_GL_PRS_FVBM(2), reg);
8287                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8288         } else {
8289                 ret = 0;
8290         }
8291         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8292                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8293
8294         return ret;
8295 }
8296
8297 static int
8298 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8299 {
8300         int ret = -EINVAL;
8301
8302         if (!hw || !cfg)
8303                 return -EINVAL;
8304
8305         switch (cfg->cfg_type) {
8306         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8307                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8308                 break;
8309         default:
8310                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8311                 break;
8312         }
8313
8314         return ret;
8315 }
8316
8317 static int
8318 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8319                                enum rte_filter_op filter_op,
8320                                void *arg)
8321 {
8322         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8323         int ret = I40E_ERR_PARAM;
8324
8325         switch (filter_op) {
8326         case RTE_ETH_FILTER_SET:
8327                 ret = i40e_dev_global_config_set(hw,
8328                         (struct rte_eth_global_cfg *)arg);
8329                 break;
8330         default:
8331                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8332                 break;
8333         }
8334
8335         return ret;
8336 }
8337
8338 static int
8339 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8340                           enum rte_filter_op filter_op,
8341                           void *arg)
8342 {
8343         struct rte_eth_tunnel_filter_conf *filter;
8344         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8345         int ret = I40E_SUCCESS;
8346
8347         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8348
8349         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8350                 return I40E_ERR_PARAM;
8351
8352         switch (filter_op) {
8353         case RTE_ETH_FILTER_NOP:
8354                 if (!(pf->flags & I40E_FLAG_VXLAN))
8355                         ret = I40E_NOT_SUPPORTED;
8356                 break;
8357         case RTE_ETH_FILTER_ADD:
8358                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8359                 break;
8360         case RTE_ETH_FILTER_DELETE:
8361                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8362                 break;
8363         default:
8364                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8365                 ret = I40E_ERR_PARAM;
8366                 break;
8367         }
8368
8369         return ret;
8370 }
8371
8372 static int
8373 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8374 {
8375         int ret = 0;
8376         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8377
8378         /* RSS setup */
8379         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8380                 ret = i40e_pf_config_rss(pf);
8381         else
8382                 i40e_pf_disable_rss(pf);
8383
8384         return ret;
8385 }
8386
8387 /* Get the symmetric hash enable configurations per port */
8388 static void
8389 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8390 {
8391         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8392
8393         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8394 }
8395
8396 /* Set the symmetric hash enable configurations per port */
8397 static void
8398 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8399 {
8400         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8401
8402         if (enable > 0) {
8403                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8404                         PMD_DRV_LOG(INFO,
8405                                 "Symmetric hash has already been enabled");
8406                         return;
8407                 }
8408                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8409         } else {
8410                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8411                         PMD_DRV_LOG(INFO,
8412                                 "Symmetric hash has already been disabled");
8413                         return;
8414                 }
8415                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8416         }
8417         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8418         I40E_WRITE_FLUSH(hw);
8419 }
8420
8421 /*
8422  * Get global configurations of hash function type and symmetric hash enable
8423  * per flow type (pctype). Note that global configuration means it affects all
8424  * the ports on the same NIC.
8425  */
8426 static int
8427 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8428                                    struct rte_eth_hash_global_conf *g_cfg)
8429 {
8430         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8431         uint32_t reg;
8432         uint16_t i, j;
8433
8434         memset(g_cfg, 0, sizeof(*g_cfg));
8435         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8436         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8437                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8438         else
8439                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8440         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8441                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8442
8443         /*
8444          * As i40e supports less than 64 flow types, only first 64 bits need to
8445          * be checked.
8446          */
8447         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8448                 g_cfg->valid_bit_mask[i] = 0ULL;
8449                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8450         }
8451
8452         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8453
8454         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8455                 if (!adapter->pctypes_tbl[i])
8456                         continue;
8457                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8458                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8459                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8460                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8461                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8462                                         g_cfg->sym_hash_enable_mask[0] |=
8463                                                                 (1ULL << i);
8464                                 }
8465                         }
8466                 }
8467         }
8468
8469         return 0;
8470 }
8471
8472 static int
8473 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8474                               const struct rte_eth_hash_global_conf *g_cfg)
8475 {
8476         uint32_t i;
8477         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8478
8479         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8480                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8481                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8482                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8483                                                 g_cfg->hash_func);
8484                 return -EINVAL;
8485         }
8486
8487         /*
8488          * As i40e supports less than 64 flow types, only first 64 bits need to
8489          * be checked.
8490          */
8491         mask0 = g_cfg->valid_bit_mask[0];
8492         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8493                 if (i == 0) {
8494                         /* Check if any unsupported flow type configured */
8495                         if ((mask0 | i40e_mask) ^ i40e_mask)
8496                                 goto mask_err;
8497                 } else {
8498                         if (g_cfg->valid_bit_mask[i])
8499                                 goto mask_err;
8500                 }
8501         }
8502
8503         return 0;
8504
8505 mask_err:
8506         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8507
8508         return -EINVAL;
8509 }
8510
8511 /*
8512  * Set global configurations of hash function type and symmetric hash enable
8513  * per flow type (pctype). Note any modifying global configuration will affect
8514  * all the ports on the same NIC.
8515  */
8516 static int
8517 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8518                                    struct rte_eth_hash_global_conf *g_cfg)
8519 {
8520         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8521         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8522         int ret;
8523         uint16_t i, j;
8524         uint32_t reg;
8525         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8526
8527         if (pf->support_multi_driver) {
8528                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8529                 return -ENOTSUP;
8530         }
8531
8532         /* Check the input parameters */
8533         ret = i40e_hash_global_config_check(adapter, g_cfg);
8534         if (ret < 0)
8535                 return ret;
8536
8537         /*
8538          * As i40e supports less than 64 flow types, only first 64 bits need to
8539          * be configured.
8540          */
8541         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8542                 if (mask0 & (1UL << i)) {
8543                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8544                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8545
8546                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8547                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8548                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8549                                         i40e_write_global_rx_ctl(hw,
8550                                                           I40E_GLQF_HSYM(j),
8551                                                           reg);
8552                         }
8553                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8554                 }
8555         }
8556
8557         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8558         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8559                 /* Toeplitz */
8560                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8561                         PMD_DRV_LOG(DEBUG,
8562                                 "Hash function already set to Toeplitz");
8563                         goto out;
8564                 }
8565                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8566         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8567                 /* Simple XOR */
8568                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8569                         PMD_DRV_LOG(DEBUG,
8570                                 "Hash function already set to Simple XOR");
8571                         goto out;
8572                 }
8573                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8574         } else
8575                 /* Use the default, and keep it as it is */
8576                 goto out;
8577
8578         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8579         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8580
8581 out:
8582         I40E_WRITE_FLUSH(hw);
8583
8584         return 0;
8585 }
8586
8587 /**
8588  * Valid input sets for hash and flow director filters per PCTYPE
8589  */
8590 static uint64_t
8591 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8592                 enum rte_filter_type filter)
8593 {
8594         uint64_t valid;
8595
8596         static const uint64_t valid_hash_inset_table[] = {
8597                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8598                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8599                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8600                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8601                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8602                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8603                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8604                         I40E_INSET_FLEX_PAYLOAD,
8605                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8606                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8607                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8608                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8609                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8610                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8611                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8612                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8613                         I40E_INSET_FLEX_PAYLOAD,
8614                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8615                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8616                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8617                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8618                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8619                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8620                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8621                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8622                         I40E_INSET_FLEX_PAYLOAD,
8623                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8624                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8625                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8626                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8627                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8628                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8629                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8630                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8631                         I40E_INSET_FLEX_PAYLOAD,
8632                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8633                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8634                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8635                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8636                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8637                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8638                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8639                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8640                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8641                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8642                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8643                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8644                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8645                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8646                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8647                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8648                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8649                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8650                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8651                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8652                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8653                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8654                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8655                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8656                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8657                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8658                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8659                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8660                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8661                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8662                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8663                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8664                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8665                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8666                         I40E_INSET_FLEX_PAYLOAD,
8667                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8668                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8669                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8670                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8671                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8672                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8673                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8674                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8675                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8676                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8677                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8678                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8679                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8680                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8681                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8682                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8683                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8684                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8685                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8686                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8687                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8688                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8689                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8690                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8691                         I40E_INSET_FLEX_PAYLOAD,
8692                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8693                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8694                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8695                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8696                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8697                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8698                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8699                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8700                         I40E_INSET_FLEX_PAYLOAD,
8701                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8702                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8703                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8704                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8705                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8706                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8707                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8708                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8709                         I40E_INSET_FLEX_PAYLOAD,
8710                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8711                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8712                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8713                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8714                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8715                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8716                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8717                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8718                         I40E_INSET_FLEX_PAYLOAD,
8719                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8720                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8721                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8722                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8723                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8724                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8725                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8726                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8727                         I40E_INSET_FLEX_PAYLOAD,
8728                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8729                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8730                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8731                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8732                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8733                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8734                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8735                         I40E_INSET_FLEX_PAYLOAD,
8736                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8737                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8738                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8739                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8740                         I40E_INSET_FLEX_PAYLOAD,
8741         };
8742
8743         /**
8744          * Flow director supports only fields defined in
8745          * union rte_eth_fdir_flow.
8746          */
8747         static const uint64_t valid_fdir_inset_table[] = {
8748                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8749                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8750                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8751                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8752                 I40E_INSET_IPV4_TTL,
8753                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8754                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8755                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8756                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8757                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8758                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8759                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8760                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8761                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8762                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8763                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8764                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8765                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8766                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8767                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8768                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8769                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8770                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8771                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8772                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8773                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8774                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8775                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8776                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8777                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8778                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8779                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8780                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8781                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8782                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8783                 I40E_INSET_SCTP_VT,
8784                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8785                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8786                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8787                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8788                 I40E_INSET_IPV4_TTL,
8789                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8790                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8791                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8792                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8793                 I40E_INSET_IPV6_HOP_LIMIT,
8794                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8795                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8796                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8797                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8798                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8799                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8800                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8801                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8802                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8803                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8804                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8805                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8806                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8807                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8808                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8809                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8810                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8811                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8812                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8813                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8814                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8815                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8816                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8817                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8818                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8819                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8820                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8821                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8822                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8823                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8824                 I40E_INSET_SCTP_VT,
8825                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8826                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8827                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8828                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8829                 I40E_INSET_IPV6_HOP_LIMIT,
8830                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8831                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8832                 I40E_INSET_LAST_ETHER_TYPE,
8833         };
8834
8835         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8836                 return 0;
8837         if (filter == RTE_ETH_FILTER_HASH)
8838                 valid = valid_hash_inset_table[pctype];
8839         else
8840                 valid = valid_fdir_inset_table[pctype];
8841
8842         return valid;
8843 }
8844
8845 /**
8846  * Validate if the input set is allowed for a specific PCTYPE
8847  */
8848 int
8849 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8850                 enum rte_filter_type filter, uint64_t inset)
8851 {
8852         uint64_t valid;
8853
8854         valid = i40e_get_valid_input_set(pctype, filter);
8855         if (inset & (~valid))
8856                 return -EINVAL;
8857
8858         return 0;
8859 }
8860
8861 /* default input set fields combination per pctype */
8862 uint64_t
8863 i40e_get_default_input_set(uint16_t pctype)
8864 {
8865         static const uint64_t default_inset_table[] = {
8866                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8867                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8868                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8869                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8870                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8871                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8872                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8873                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8874                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8875                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8876                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8877                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8878                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8879                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8880                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8881                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8882                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8883                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8884                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8885                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8886                         I40E_INSET_SCTP_VT,
8887                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8888                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8889                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8890                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8891                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8892                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8893                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8894                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8895                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8896                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8897                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8898                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8899                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8900                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8901                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8902                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8903                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8904                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8905                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8906                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8907                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8908                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8909                         I40E_INSET_SCTP_VT,
8910                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8911                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8912                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8913                         I40E_INSET_LAST_ETHER_TYPE,
8914         };
8915
8916         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8917                 return 0;
8918
8919         return default_inset_table[pctype];
8920 }
8921
8922 /**
8923  * Parse the input set from index to logical bit masks
8924  */
8925 static int
8926 i40e_parse_input_set(uint64_t *inset,
8927                      enum i40e_filter_pctype pctype,
8928                      enum rte_eth_input_set_field *field,
8929                      uint16_t size)
8930 {
8931         uint16_t i, j;
8932         int ret = -EINVAL;
8933
8934         static const struct {
8935                 enum rte_eth_input_set_field field;
8936                 uint64_t inset;
8937         } inset_convert_table[] = {
8938                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8939                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8940                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8941                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8942                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8943                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8944                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8945                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8946                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8947                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8948                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8949                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8950                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8951                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8952                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8953                         I40E_INSET_IPV6_NEXT_HDR},
8954                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8955                         I40E_INSET_IPV6_HOP_LIMIT},
8956                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8957                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8958                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8959                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8960                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8961                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8962                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8963                         I40E_INSET_SCTP_VT},
8964                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8965                         I40E_INSET_TUNNEL_DMAC},
8966                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8967                         I40E_INSET_VLAN_TUNNEL},
8968                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8969                         I40E_INSET_TUNNEL_ID},
8970                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8971                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8972                         I40E_INSET_FLEX_PAYLOAD_W1},
8973                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8974                         I40E_INSET_FLEX_PAYLOAD_W2},
8975                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8976                         I40E_INSET_FLEX_PAYLOAD_W3},
8977                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8978                         I40E_INSET_FLEX_PAYLOAD_W4},
8979                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8980                         I40E_INSET_FLEX_PAYLOAD_W5},
8981                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8982                         I40E_INSET_FLEX_PAYLOAD_W6},
8983                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8984                         I40E_INSET_FLEX_PAYLOAD_W7},
8985                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8986                         I40E_INSET_FLEX_PAYLOAD_W8},
8987         };
8988
8989         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8990                 return ret;
8991
8992         /* Only one item allowed for default or all */
8993         if (size == 1) {
8994                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8995                         *inset = i40e_get_default_input_set(pctype);
8996                         return 0;
8997                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8998                         *inset = I40E_INSET_NONE;
8999                         return 0;
9000                 }
9001         }
9002
9003         for (i = 0, *inset = 0; i < size; i++) {
9004                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9005                         if (field[i] == inset_convert_table[j].field) {
9006                                 *inset |= inset_convert_table[j].inset;
9007                                 break;
9008                         }
9009                 }
9010
9011                 /* It contains unsupported input set, return immediately */
9012                 if (j == RTE_DIM(inset_convert_table))
9013                         return ret;
9014         }
9015
9016         return 0;
9017 }
9018
9019 /**
9020  * Translate the input set from bit masks to register aware bit masks
9021  * and vice versa
9022  */
9023 uint64_t
9024 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9025 {
9026         uint64_t val = 0;
9027         uint16_t i;
9028
9029         struct inset_map {
9030                 uint64_t inset;
9031                 uint64_t inset_reg;
9032         };
9033
9034         static const struct inset_map inset_map_common[] = {
9035                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9036                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9037                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9038                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9039                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9040                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9041                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9042                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9043                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9044                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9045                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9046                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9047                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9048                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9049                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9050                 {I40E_INSET_TUNNEL_DMAC,
9051                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9052                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9053                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9054                 {I40E_INSET_TUNNEL_SRC_PORT,
9055                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9056                 {I40E_INSET_TUNNEL_DST_PORT,
9057                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9058                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9059                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9060                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9061                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9062                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9063                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9064                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9065                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9066                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9067         };
9068
9069     /* some different registers map in x722*/
9070         static const struct inset_map inset_map_diff_x722[] = {
9071                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9072                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9073                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9074                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9075         };
9076
9077         static const struct inset_map inset_map_diff_not_x722[] = {
9078                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9079                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9080                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9081                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9082         };
9083
9084         if (input == 0)
9085                 return val;
9086
9087         /* Translate input set to register aware inset */
9088         if (type == I40E_MAC_X722) {
9089                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9090                         if (input & inset_map_diff_x722[i].inset)
9091                                 val |= inset_map_diff_x722[i].inset_reg;
9092                 }
9093         } else {
9094                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9095                         if (input & inset_map_diff_not_x722[i].inset)
9096                                 val |= inset_map_diff_not_x722[i].inset_reg;
9097                 }
9098         }
9099
9100         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9101                 if (input & inset_map_common[i].inset)
9102                         val |= inset_map_common[i].inset_reg;
9103         }
9104
9105         return val;
9106 }
9107
9108 int
9109 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9110 {
9111         uint8_t i, idx = 0;
9112         uint64_t inset_need_mask = inset;
9113
9114         static const struct {
9115                 uint64_t inset;
9116                 uint32_t mask;
9117         } inset_mask_map[] = {
9118                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9119                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9120                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9121                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9122                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9123                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9124                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9125                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9126         };
9127
9128         if (!inset || !mask || !nb_elem)
9129                 return 0;
9130
9131         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9132                 /* Clear the inset bit, if no MASK is required,
9133                  * for example proto + ttl
9134                  */
9135                 if ((inset & inset_mask_map[i].inset) ==
9136                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9137                         inset_need_mask &= ~inset_mask_map[i].inset;
9138                 if (!inset_need_mask)
9139                         return 0;
9140         }
9141         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9142                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9143                     inset_mask_map[i].inset) {
9144                         if (idx >= nb_elem) {
9145                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9146                                 return -EINVAL;
9147                         }
9148                         mask[idx] = inset_mask_map[i].mask;
9149                         idx++;
9150                 }
9151         }
9152
9153         return idx;
9154 }
9155
9156 void
9157 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9158 {
9159         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9160
9161         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9162         if (reg != val)
9163                 i40e_write_rx_ctl(hw, addr, val);
9164         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9165                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9166 }
9167
9168 void
9169 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9170 {
9171         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9172
9173         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9174         if (reg != val)
9175                 i40e_write_global_rx_ctl(hw, addr, val);
9176         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9177                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9178 }
9179
9180 static void
9181 i40e_filter_input_set_init(struct i40e_pf *pf)
9182 {
9183         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9184         enum i40e_filter_pctype pctype;
9185         uint64_t input_set, inset_reg;
9186         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9187         int num, i;
9188         uint16_t flow_type;
9189
9190         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9191              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9192                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9193
9194                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9195                         continue;
9196
9197                 input_set = i40e_get_default_input_set(pctype);
9198
9199                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9200                                                    I40E_INSET_MASK_NUM_REG);
9201                 if (num < 0)
9202                         return;
9203                 if (pf->support_multi_driver && num > 0) {
9204                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9205                         return;
9206                 }
9207                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9208                                         input_set);
9209
9210                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9211                                       (uint32_t)(inset_reg & UINT32_MAX));
9212                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9213                                      (uint32_t)((inset_reg >>
9214                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9215                 if (!pf->support_multi_driver) {
9216                         i40e_check_write_global_reg(hw,
9217                                             I40E_GLQF_HASH_INSET(0, pctype),
9218                                             (uint32_t)(inset_reg & UINT32_MAX));
9219                         i40e_check_write_global_reg(hw,
9220                                              I40E_GLQF_HASH_INSET(1, pctype),
9221                                              (uint32_t)((inset_reg >>
9222                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9223
9224                         for (i = 0; i < num; i++) {
9225                                 i40e_check_write_global_reg(hw,
9226                                                     I40E_GLQF_FD_MSK(i, pctype),
9227                                                     mask_reg[i]);
9228                                 i40e_check_write_global_reg(hw,
9229                                                   I40E_GLQF_HASH_MSK(i, pctype),
9230                                                   mask_reg[i]);
9231                         }
9232                         /*clear unused mask registers of the pctype */
9233                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9234                                 i40e_check_write_global_reg(hw,
9235                                                     I40E_GLQF_FD_MSK(i, pctype),
9236                                                     0);
9237                                 i40e_check_write_global_reg(hw,
9238                                                   I40E_GLQF_HASH_MSK(i, pctype),
9239                                                   0);
9240                         }
9241                 } else {
9242                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9243                 }
9244                 I40E_WRITE_FLUSH(hw);
9245
9246                 /* store the default input set */
9247                 if (!pf->support_multi_driver)
9248                         pf->hash_input_set[pctype] = input_set;
9249                 pf->fdir.input_set[pctype] = input_set;
9250         }
9251
9252         if (!pf->support_multi_driver) {
9253                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9254                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9255                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9256         }
9257 }
9258
9259 int
9260 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9261                          struct rte_eth_input_set_conf *conf)
9262 {
9263         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9264         enum i40e_filter_pctype pctype;
9265         uint64_t input_set, inset_reg = 0;
9266         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9267         int ret, i, num;
9268
9269         if (!conf) {
9270                 PMD_DRV_LOG(ERR, "Invalid pointer");
9271                 return -EFAULT;
9272         }
9273         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9274             conf->op != RTE_ETH_INPUT_SET_ADD) {
9275                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9276                 return -EINVAL;
9277         }
9278
9279         if (pf->support_multi_driver) {
9280                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9281                 return -ENOTSUP;
9282         }
9283
9284         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9285         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9286                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9287                 return -EINVAL;
9288         }
9289
9290         if (hw->mac.type == I40E_MAC_X722) {
9291                 /* get translated pctype value in fd pctype register */
9292                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9293                         I40E_GLQF_FD_PCTYPES((int)pctype));
9294         }
9295
9296         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9297                                    conf->inset_size);
9298         if (ret) {
9299                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9300                 return -EINVAL;
9301         }
9302
9303         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9304                 /* get inset value in register */
9305                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9306                 inset_reg <<= I40E_32_BIT_WIDTH;
9307                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9308                 input_set |= pf->hash_input_set[pctype];
9309         }
9310         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9311                                            I40E_INSET_MASK_NUM_REG);
9312         if (num < 0)
9313                 return -EINVAL;
9314
9315         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9316
9317         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9318                                     (uint32_t)(inset_reg & UINT32_MAX));
9319         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9320                                     (uint32_t)((inset_reg >>
9321                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9322         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9323
9324         for (i = 0; i < num; i++)
9325                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9326                                             mask_reg[i]);
9327         /*clear unused mask registers of the pctype */
9328         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9329                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9330                                             0);
9331         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9332         I40E_WRITE_FLUSH(hw);
9333
9334         pf->hash_input_set[pctype] = input_set;
9335         return 0;
9336 }
9337
9338 int
9339 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9340                          struct rte_eth_input_set_conf *conf)
9341 {
9342         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9343         enum i40e_filter_pctype pctype;
9344         uint64_t input_set, inset_reg = 0;
9345         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9346         int ret, i, num;
9347
9348         if (!hw || !conf) {
9349                 PMD_DRV_LOG(ERR, "Invalid pointer");
9350                 return -EFAULT;
9351         }
9352         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9353             conf->op != RTE_ETH_INPUT_SET_ADD) {
9354                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9355                 return -EINVAL;
9356         }
9357
9358         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9359
9360         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9361                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9362                 return -EINVAL;
9363         }
9364
9365         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9366                                    conf->inset_size);
9367         if (ret) {
9368                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9369                 return -EINVAL;
9370         }
9371
9372         /* get inset value in register */
9373         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9374         inset_reg <<= I40E_32_BIT_WIDTH;
9375         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9376
9377         /* Can not change the inset reg for flex payload for fdir,
9378          * it is done by writing I40E_PRTQF_FD_FLXINSET
9379          * in i40e_set_flex_mask_on_pctype.
9380          */
9381         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9382                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9383         else
9384                 input_set |= pf->fdir.input_set[pctype];
9385         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9386                                            I40E_INSET_MASK_NUM_REG);
9387         if (num < 0)
9388                 return -EINVAL;
9389         if (pf->support_multi_driver && num > 0) {
9390                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9391                 return -ENOTSUP;
9392         }
9393
9394         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9395
9396         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9397                               (uint32_t)(inset_reg & UINT32_MAX));
9398         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9399                              (uint32_t)((inset_reg >>
9400                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9401
9402         if (!pf->support_multi_driver) {
9403                 for (i = 0; i < num; i++)
9404                         i40e_check_write_global_reg(hw,
9405                                                     I40E_GLQF_FD_MSK(i, pctype),
9406                                                     mask_reg[i]);
9407                 /*clear unused mask registers of the pctype */
9408                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9409                         i40e_check_write_global_reg(hw,
9410                                                     I40E_GLQF_FD_MSK(i, pctype),
9411                                                     0);
9412                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9413         } else {
9414                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9415         }
9416         I40E_WRITE_FLUSH(hw);
9417
9418         pf->fdir.input_set[pctype] = input_set;
9419         return 0;
9420 }
9421
9422 static int
9423 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9424 {
9425         int ret = 0;
9426
9427         if (!hw || !info) {
9428                 PMD_DRV_LOG(ERR, "Invalid pointer");
9429                 return -EFAULT;
9430         }
9431
9432         switch (info->info_type) {
9433         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9434                 i40e_get_symmetric_hash_enable_per_port(hw,
9435                                         &(info->info.enable));
9436                 break;
9437         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9438                 ret = i40e_get_hash_filter_global_config(hw,
9439                                 &(info->info.global_conf));
9440                 break;
9441         default:
9442                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9443                                                         info->info_type);
9444                 ret = -EINVAL;
9445                 break;
9446         }
9447
9448         return ret;
9449 }
9450
9451 static int
9452 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9453 {
9454         int ret = 0;
9455
9456         if (!hw || !info) {
9457                 PMD_DRV_LOG(ERR, "Invalid pointer");
9458                 return -EFAULT;
9459         }
9460
9461         switch (info->info_type) {
9462         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9463                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9464                 break;
9465         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9466                 ret = i40e_set_hash_filter_global_config(hw,
9467                                 &(info->info.global_conf));
9468                 break;
9469         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9470                 ret = i40e_hash_filter_inset_select(hw,
9471                                                &(info->info.input_set_conf));
9472                 break;
9473
9474         default:
9475                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9476                                                         info->info_type);
9477                 ret = -EINVAL;
9478                 break;
9479         }
9480
9481         return ret;
9482 }
9483
9484 /* Operations for hash function */
9485 static int
9486 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9487                       enum rte_filter_op filter_op,
9488                       void *arg)
9489 {
9490         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9491         int ret = 0;
9492
9493         switch (filter_op) {
9494         case RTE_ETH_FILTER_NOP:
9495                 break;
9496         case RTE_ETH_FILTER_GET:
9497                 ret = i40e_hash_filter_get(hw,
9498                         (struct rte_eth_hash_filter_info *)arg);
9499                 break;
9500         case RTE_ETH_FILTER_SET:
9501                 ret = i40e_hash_filter_set(hw,
9502                         (struct rte_eth_hash_filter_info *)arg);
9503                 break;
9504         default:
9505                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9506                                                                 filter_op);
9507                 ret = -ENOTSUP;
9508                 break;
9509         }
9510
9511         return ret;
9512 }
9513
9514 /* Convert ethertype filter structure */
9515 static int
9516 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9517                               struct i40e_ethertype_filter *filter)
9518 {
9519         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9520         filter->input.ether_type = input->ether_type;
9521         filter->flags = input->flags;
9522         filter->queue = input->queue;
9523
9524         return 0;
9525 }
9526
9527 /* Check if there exists the ehtertype filter */
9528 struct i40e_ethertype_filter *
9529 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9530                                 const struct i40e_ethertype_filter_input *input)
9531 {
9532         int ret;
9533
9534         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9535         if (ret < 0)
9536                 return NULL;
9537
9538         return ethertype_rule->hash_map[ret];
9539 }
9540
9541 /* Add ethertype filter in SW list */
9542 static int
9543 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9544                                 struct i40e_ethertype_filter *filter)
9545 {
9546         struct i40e_ethertype_rule *rule = &pf->ethertype;
9547         int ret;
9548
9549         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9550         if (ret < 0) {
9551                 PMD_DRV_LOG(ERR,
9552                             "Failed to insert ethertype filter"
9553                             " to hash table %d!",
9554                             ret);
9555                 return ret;
9556         }
9557         rule->hash_map[ret] = filter;
9558
9559         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9560
9561         return 0;
9562 }
9563
9564 /* Delete ethertype filter in SW list */
9565 int
9566 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9567                              struct i40e_ethertype_filter_input *input)
9568 {
9569         struct i40e_ethertype_rule *rule = &pf->ethertype;
9570         struct i40e_ethertype_filter *filter;
9571         int ret;
9572
9573         ret = rte_hash_del_key(rule->hash_table, input);
9574         if (ret < 0) {
9575                 PMD_DRV_LOG(ERR,
9576                             "Failed to delete ethertype filter"
9577                             " to hash table %d!",
9578                             ret);
9579                 return ret;
9580         }
9581         filter = rule->hash_map[ret];
9582         rule->hash_map[ret] = NULL;
9583
9584         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9585         rte_free(filter);
9586
9587         return 0;
9588 }
9589
9590 /*
9591  * Configure ethertype filter, which can director packet by filtering
9592  * with mac address and ether_type or only ether_type
9593  */
9594 int
9595 i40e_ethertype_filter_set(struct i40e_pf *pf,
9596                         struct rte_eth_ethertype_filter *filter,
9597                         bool add)
9598 {
9599         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9600         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9601         struct i40e_ethertype_filter *ethertype_filter, *node;
9602         struct i40e_ethertype_filter check_filter;
9603         struct i40e_control_filter_stats stats;
9604         uint16_t flags = 0;
9605         int ret;
9606
9607         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9608                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9609                 return -EINVAL;
9610         }
9611         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9612                 filter->ether_type == ETHER_TYPE_IPv6) {
9613                 PMD_DRV_LOG(ERR,
9614                         "unsupported ether_type(0x%04x) in control packet filter.",
9615                         filter->ether_type);
9616                 return -EINVAL;
9617         }
9618         if (filter->ether_type == ETHER_TYPE_VLAN)
9619                 PMD_DRV_LOG(WARNING,
9620                         "filter vlan ether_type in first tag is not supported.");
9621
9622         /* Check if there is the filter in SW list */
9623         memset(&check_filter, 0, sizeof(check_filter));
9624         i40e_ethertype_filter_convert(filter, &check_filter);
9625         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9626                                                &check_filter.input);
9627         if (add && node) {
9628                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9629                 return -EINVAL;
9630         }
9631
9632         if (!add && !node) {
9633                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9634                 return -EINVAL;
9635         }
9636
9637         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9638                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9639         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9640                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9641         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9642
9643         memset(&stats, 0, sizeof(stats));
9644         ret = i40e_aq_add_rem_control_packet_filter(hw,
9645                         filter->mac_addr.addr_bytes,
9646                         filter->ether_type, flags,
9647                         pf->main_vsi->seid,
9648                         filter->queue, add, &stats, NULL);
9649
9650         PMD_DRV_LOG(INFO,
9651                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9652                 ret, stats.mac_etype_used, stats.etype_used,
9653                 stats.mac_etype_free, stats.etype_free);
9654         if (ret < 0)
9655                 return -ENOSYS;
9656
9657         /* Add or delete a filter in SW list */
9658         if (add) {
9659                 ethertype_filter = rte_zmalloc("ethertype_filter",
9660                                        sizeof(*ethertype_filter), 0);
9661                 if (ethertype_filter == NULL) {
9662                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9663                         return -ENOMEM;
9664                 }
9665
9666                 rte_memcpy(ethertype_filter, &check_filter,
9667                            sizeof(check_filter));
9668                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9669                 if (ret < 0)
9670                         rte_free(ethertype_filter);
9671         } else {
9672                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9673         }
9674
9675         return ret;
9676 }
9677
9678 /*
9679  * Handle operations for ethertype filter.
9680  */
9681 static int
9682 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9683                                 enum rte_filter_op filter_op,
9684                                 void *arg)
9685 {
9686         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9687         int ret = 0;
9688
9689         if (filter_op == RTE_ETH_FILTER_NOP)
9690                 return ret;
9691
9692         if (arg == NULL) {
9693                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9694                             filter_op);
9695                 return -EINVAL;
9696         }
9697
9698         switch (filter_op) {
9699         case RTE_ETH_FILTER_ADD:
9700                 ret = i40e_ethertype_filter_set(pf,
9701                         (struct rte_eth_ethertype_filter *)arg,
9702                         TRUE);
9703                 break;
9704         case RTE_ETH_FILTER_DELETE:
9705                 ret = i40e_ethertype_filter_set(pf,
9706                         (struct rte_eth_ethertype_filter *)arg,
9707                         FALSE);
9708                 break;
9709         default:
9710                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9711                 ret = -ENOSYS;
9712                 break;
9713         }
9714         return ret;
9715 }
9716
9717 static int
9718 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9719                      enum rte_filter_type filter_type,
9720                      enum rte_filter_op filter_op,
9721                      void *arg)
9722 {
9723         int ret = 0;
9724
9725         if (dev == NULL)
9726                 return -EINVAL;
9727
9728         switch (filter_type) {
9729         case RTE_ETH_FILTER_NONE:
9730                 /* For global configuration */
9731                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9732                 break;
9733         case RTE_ETH_FILTER_HASH:
9734                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9735                 break;
9736         case RTE_ETH_FILTER_MACVLAN:
9737                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9738                 break;
9739         case RTE_ETH_FILTER_ETHERTYPE:
9740                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9741                 break;
9742         case RTE_ETH_FILTER_TUNNEL:
9743                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9744                 break;
9745         case RTE_ETH_FILTER_FDIR:
9746                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9747                 break;
9748         case RTE_ETH_FILTER_GENERIC:
9749                 if (filter_op != RTE_ETH_FILTER_GET)
9750                         return -EINVAL;
9751                 *(const void **)arg = &i40e_flow_ops;
9752                 break;
9753         default:
9754                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9755                                                         filter_type);
9756                 ret = -EINVAL;
9757                 break;
9758         }
9759
9760         return ret;
9761 }
9762
9763 /*
9764  * Check and enable Extended Tag.
9765  * Enabling Extended Tag is important for 40G performance.
9766  */
9767 static void
9768 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9769 {
9770         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9771         uint32_t buf = 0;
9772         int ret;
9773
9774         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9775                                       PCI_DEV_CAP_REG);
9776         if (ret < 0) {
9777                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9778                             PCI_DEV_CAP_REG);
9779                 return;
9780         }
9781         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9782                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9783                 return;
9784         }
9785
9786         buf = 0;
9787         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9788                                       PCI_DEV_CTRL_REG);
9789         if (ret < 0) {
9790                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9791                             PCI_DEV_CTRL_REG);
9792                 return;
9793         }
9794         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9795                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9796                 return;
9797         }
9798         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9799         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9800                                        PCI_DEV_CTRL_REG);
9801         if (ret < 0) {
9802                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9803                             PCI_DEV_CTRL_REG);
9804                 return;
9805         }
9806 }
9807
9808 /*
9809  * As some registers wouldn't be reset unless a global hardware reset,
9810  * hardware initialization is needed to put those registers into an
9811  * expected initial state.
9812  */
9813 static void
9814 i40e_hw_init(struct rte_eth_dev *dev)
9815 {
9816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9817
9818         i40e_enable_extended_tag(dev);
9819
9820         /* clear the PF Queue Filter control register */
9821         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9822
9823         /* Disable symmetric hash per port */
9824         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9825 }
9826
9827 /*
9828  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9829  * however this function will return only one highest pctype index,
9830  * which is not quite correct. This is known problem of i40e driver
9831  * and needs to be fixed later.
9832  */
9833 enum i40e_filter_pctype
9834 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9835 {
9836         int i;
9837         uint64_t pctype_mask;
9838
9839         if (flow_type < I40E_FLOW_TYPE_MAX) {
9840                 pctype_mask = adapter->pctypes_tbl[flow_type];
9841                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9842                         if (pctype_mask & (1ULL << i))
9843                                 return (enum i40e_filter_pctype)i;
9844                 }
9845         }
9846         return I40E_FILTER_PCTYPE_INVALID;
9847 }
9848
9849 uint16_t
9850 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9851                         enum i40e_filter_pctype pctype)
9852 {
9853         uint16_t flowtype;
9854         uint64_t pctype_mask = 1ULL << pctype;
9855
9856         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9857              flowtype++) {
9858                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9859                         return flowtype;
9860         }
9861
9862         return RTE_ETH_FLOW_UNKNOWN;
9863 }
9864
9865 /*
9866  * On X710, performance number is far from the expectation on recent firmware
9867  * versions; on XL710, performance number is also far from the expectation on
9868  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9869  * mode is enabled and port MAC address is equal to the packet destination MAC
9870  * address. The fix for this issue may not be integrated in the following
9871  * firmware version. So the workaround in software driver is needed. It needs
9872  * to modify the initial values of 3 internal only registers for both X710 and
9873  * XL710. Note that the values for X710 or XL710 could be different, and the
9874  * workaround can be removed when it is fixed in firmware in the future.
9875  */
9876
9877 /* For both X710 and XL710 */
9878 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9879 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9880 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9881
9882 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9883 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9884
9885 /* For X722 */
9886 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9887 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9888
9889 /* For X710 */
9890 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9891 /* For XL710 */
9892 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9893 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9894
9895 static int
9896 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9897 {
9898         enum i40e_status_code status;
9899         struct i40e_aq_get_phy_abilities_resp phy_ab;
9900         int ret = -ENOTSUP;
9901         int retries = 0;
9902
9903         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9904                                               NULL);
9905
9906         while (status) {
9907                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9908                         status);
9909                 retries++;
9910                 rte_delay_us(100000);
9911                 if  (retries < 5)
9912                         status = i40e_aq_get_phy_capabilities(hw, false,
9913                                         true, &phy_ab, NULL);
9914                 else
9915                         return ret;
9916         }
9917         return 0;
9918 }
9919
9920 static void
9921 i40e_configure_registers(struct i40e_hw *hw)
9922 {
9923         static struct {
9924                 uint32_t addr;
9925                 uint64_t val;
9926         } reg_table[] = {
9927                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9928                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9929                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9930         };
9931         uint64_t reg;
9932         uint32_t i;
9933         int ret;
9934
9935         for (i = 0; i < RTE_DIM(reg_table); i++) {
9936                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9937                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9938                                 reg_table[i].val =
9939                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9940                         else /* For X710/XL710/XXV710 */
9941                                 if (hw->aq.fw_maj_ver < 6)
9942                                         reg_table[i].val =
9943                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9944                                 else
9945                                         reg_table[i].val =
9946                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9947                 }
9948
9949                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9950                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9951                                 reg_table[i].val =
9952                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9953                         else /* For X710/XL710/XXV710 */
9954                                 reg_table[i].val =
9955                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9956                 }
9957
9958                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9959                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9960                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9961                                 reg_table[i].val =
9962                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9963                         else /* For X710 */
9964                                 reg_table[i].val =
9965                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9966                 }
9967
9968                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9969                                                         &reg, NULL);
9970                 if (ret < 0) {
9971                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9972                                                         reg_table[i].addr);
9973                         break;
9974                 }
9975                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9976                                                 reg_table[i].addr, reg);
9977                 if (reg == reg_table[i].val)
9978                         continue;
9979
9980                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9981                                                 reg_table[i].val, NULL);
9982                 if (ret < 0) {
9983                         PMD_DRV_LOG(ERR,
9984                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9985                                 reg_table[i].val, reg_table[i].addr);
9986                         break;
9987                 }
9988                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9989                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9990         }
9991 }
9992
9993 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9994 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9995 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9996 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9997 static int
9998 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9999 {
10000         uint32_t reg;
10001         int ret;
10002
10003         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10004                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10005                 return -EINVAL;
10006         }
10007
10008         /* Configure for double VLAN RX stripping */
10009         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10010         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10011                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10012                 ret = i40e_aq_debug_write_register(hw,
10013                                                    I40E_VSI_TSR(vsi->vsi_id),
10014                                                    reg, NULL);
10015                 if (ret < 0) {
10016                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10017                                     vsi->vsi_id);
10018                         return I40E_ERR_CONFIG;
10019                 }
10020         }
10021
10022         /* Configure for double VLAN TX insertion */
10023         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10024         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10025                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10026                 ret = i40e_aq_debug_write_register(hw,
10027                                                    I40E_VSI_L2TAGSTXVALID(
10028                                                    vsi->vsi_id), reg, NULL);
10029                 if (ret < 0) {
10030                         PMD_DRV_LOG(ERR,
10031                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10032                                 vsi->vsi_id);
10033                         return I40E_ERR_CONFIG;
10034                 }
10035         }
10036
10037         return 0;
10038 }
10039
10040 /**
10041  * i40e_aq_add_mirror_rule
10042  * @hw: pointer to the hardware structure
10043  * @seid: VEB seid to add mirror rule to
10044  * @dst_id: destination vsi seid
10045  * @entries: Buffer which contains the entities to be mirrored
10046  * @count: number of entities contained in the buffer
10047  * @rule_id:the rule_id of the rule to be added
10048  *
10049  * Add a mirror rule for a given veb.
10050  *
10051  **/
10052 static enum i40e_status_code
10053 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10054                         uint16_t seid, uint16_t dst_id,
10055                         uint16_t rule_type, uint16_t *entries,
10056                         uint16_t count, uint16_t *rule_id)
10057 {
10058         struct i40e_aq_desc desc;
10059         struct i40e_aqc_add_delete_mirror_rule cmd;
10060         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10061                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10062                 &desc.params.raw;
10063         uint16_t buff_len;
10064         enum i40e_status_code status;
10065
10066         i40e_fill_default_direct_cmd_desc(&desc,
10067                                           i40e_aqc_opc_add_mirror_rule);
10068         memset(&cmd, 0, sizeof(cmd));
10069
10070         buff_len = sizeof(uint16_t) * count;
10071         desc.datalen = rte_cpu_to_le_16(buff_len);
10072         if (buff_len > 0)
10073                 desc.flags |= rte_cpu_to_le_16(
10074                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10075         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10076                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10077         cmd.num_entries = rte_cpu_to_le_16(count);
10078         cmd.seid = rte_cpu_to_le_16(seid);
10079         cmd.destination = rte_cpu_to_le_16(dst_id);
10080
10081         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10082         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10083         PMD_DRV_LOG(INFO,
10084                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10085                 hw->aq.asq_last_status, resp->rule_id,
10086                 resp->mirror_rules_used, resp->mirror_rules_free);
10087         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10088
10089         return status;
10090 }
10091
10092 /**
10093  * i40e_aq_del_mirror_rule
10094  * @hw: pointer to the hardware structure
10095  * @seid: VEB seid to add mirror rule to
10096  * @entries: Buffer which contains the entities to be mirrored
10097  * @count: number of entities contained in the buffer
10098  * @rule_id:the rule_id of the rule to be delete
10099  *
10100  * Delete a mirror rule for a given veb.
10101  *
10102  **/
10103 static enum i40e_status_code
10104 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10105                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10106                 uint16_t count, uint16_t rule_id)
10107 {
10108         struct i40e_aq_desc desc;
10109         struct i40e_aqc_add_delete_mirror_rule cmd;
10110         uint16_t buff_len = 0;
10111         enum i40e_status_code status;
10112         void *buff = NULL;
10113
10114         i40e_fill_default_direct_cmd_desc(&desc,
10115                                           i40e_aqc_opc_delete_mirror_rule);
10116         memset(&cmd, 0, sizeof(cmd));
10117         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10118                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10119                                                           I40E_AQ_FLAG_RD));
10120                 cmd.num_entries = count;
10121                 buff_len = sizeof(uint16_t) * count;
10122                 desc.datalen = rte_cpu_to_le_16(buff_len);
10123                 buff = (void *)entries;
10124         } else
10125                 /* rule id is filled in destination field for deleting mirror rule */
10126                 cmd.destination = rte_cpu_to_le_16(rule_id);
10127
10128         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10129                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10130         cmd.seid = rte_cpu_to_le_16(seid);
10131
10132         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10133         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10134
10135         return status;
10136 }
10137
10138 /**
10139  * i40e_mirror_rule_set
10140  * @dev: pointer to the hardware structure
10141  * @mirror_conf: mirror rule info
10142  * @sw_id: mirror rule's sw_id
10143  * @on: enable/disable
10144  *
10145  * set a mirror rule.
10146  *
10147  **/
10148 static int
10149 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10150                         struct rte_eth_mirror_conf *mirror_conf,
10151                         uint8_t sw_id, uint8_t on)
10152 {
10153         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10154         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10155         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10156         struct i40e_mirror_rule *parent = NULL;
10157         uint16_t seid, dst_seid, rule_id;
10158         uint16_t i, j = 0;
10159         int ret;
10160
10161         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10162
10163         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10164                 PMD_DRV_LOG(ERR,
10165                         "mirror rule can not be configured without veb or vfs.");
10166                 return -ENOSYS;
10167         }
10168         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10169                 PMD_DRV_LOG(ERR, "mirror table is full.");
10170                 return -ENOSPC;
10171         }
10172         if (mirror_conf->dst_pool > pf->vf_num) {
10173                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10174                                  mirror_conf->dst_pool);
10175                 return -EINVAL;
10176         }
10177
10178         seid = pf->main_vsi->veb->seid;
10179
10180         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10181                 if (sw_id <= it->index) {
10182                         mirr_rule = it;
10183                         break;
10184                 }
10185                 parent = it;
10186         }
10187         if (mirr_rule && sw_id == mirr_rule->index) {
10188                 if (on) {
10189                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10190                         return -EEXIST;
10191                 } else {
10192                         ret = i40e_aq_del_mirror_rule(hw, seid,
10193                                         mirr_rule->rule_type,
10194                                         mirr_rule->entries,
10195                                         mirr_rule->num_entries, mirr_rule->id);
10196                         if (ret < 0) {
10197                                 PMD_DRV_LOG(ERR,
10198                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10199                                         ret, hw->aq.asq_last_status);
10200                                 return -ENOSYS;
10201                         }
10202                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10203                         rte_free(mirr_rule);
10204                         pf->nb_mirror_rule--;
10205                         return 0;
10206                 }
10207         } else if (!on) {
10208                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10209                 return -ENOENT;
10210         }
10211
10212         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10213                                 sizeof(struct i40e_mirror_rule) , 0);
10214         if (!mirr_rule) {
10215                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10216                 return I40E_ERR_NO_MEMORY;
10217         }
10218         switch (mirror_conf->rule_type) {
10219         case ETH_MIRROR_VLAN:
10220                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10221                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10222                                 mirr_rule->entries[j] =
10223                                         mirror_conf->vlan.vlan_id[i];
10224                                 j++;
10225                         }
10226                 }
10227                 if (j == 0) {
10228                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10229                         rte_free(mirr_rule);
10230                         return -EINVAL;
10231                 }
10232                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10233                 break;
10234         case ETH_MIRROR_VIRTUAL_POOL_UP:
10235         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10236                 /* check if the specified pool bit is out of range */
10237                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10238                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10239                         rte_free(mirr_rule);
10240                         return -EINVAL;
10241                 }
10242                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10243                         if (mirror_conf->pool_mask & (1ULL << i)) {
10244                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10245                                 j++;
10246                         }
10247                 }
10248                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10249                         /* add pf vsi to entries */
10250                         mirr_rule->entries[j] = pf->main_vsi_seid;
10251                         j++;
10252                 }
10253                 if (j == 0) {
10254                         PMD_DRV_LOG(ERR, "pool is not specified.");
10255                         rte_free(mirr_rule);
10256                         return -EINVAL;
10257                 }
10258                 /* egress and ingress in aq commands means from switch but not port */
10259                 mirr_rule->rule_type =
10260                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10261                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10262                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10263                 break;
10264         case ETH_MIRROR_UPLINK_PORT:
10265                 /* egress and ingress in aq commands means from switch but not port*/
10266                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10267                 break;
10268         case ETH_MIRROR_DOWNLINK_PORT:
10269                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10270                 break;
10271         default:
10272                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10273                         mirror_conf->rule_type);
10274                 rte_free(mirr_rule);
10275                 return -EINVAL;
10276         }
10277
10278         /* If the dst_pool is equal to vf_num, consider it as PF */
10279         if (mirror_conf->dst_pool == pf->vf_num)
10280                 dst_seid = pf->main_vsi_seid;
10281         else
10282                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10283
10284         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10285                                       mirr_rule->rule_type, mirr_rule->entries,
10286                                       j, &rule_id);
10287         if (ret < 0) {
10288                 PMD_DRV_LOG(ERR,
10289                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10290                         ret, hw->aq.asq_last_status);
10291                 rte_free(mirr_rule);
10292                 return -ENOSYS;
10293         }
10294
10295         mirr_rule->index = sw_id;
10296         mirr_rule->num_entries = j;
10297         mirr_rule->id = rule_id;
10298         mirr_rule->dst_vsi_seid = dst_seid;
10299
10300         if (parent)
10301                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10302         else
10303                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10304
10305         pf->nb_mirror_rule++;
10306         return 0;
10307 }
10308
10309 /**
10310  * i40e_mirror_rule_reset
10311  * @dev: pointer to the device
10312  * @sw_id: mirror rule's sw_id
10313  *
10314  * reset a mirror rule.
10315  *
10316  **/
10317 static int
10318 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10319 {
10320         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10321         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10322         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10323         uint16_t seid;
10324         int ret;
10325
10326         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10327
10328         seid = pf->main_vsi->veb->seid;
10329
10330         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10331                 if (sw_id == it->index) {
10332                         mirr_rule = it;
10333                         break;
10334                 }
10335         }
10336         if (mirr_rule) {
10337                 ret = i40e_aq_del_mirror_rule(hw, seid,
10338                                 mirr_rule->rule_type,
10339                                 mirr_rule->entries,
10340                                 mirr_rule->num_entries, mirr_rule->id);
10341                 if (ret < 0) {
10342                         PMD_DRV_LOG(ERR,
10343                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10344                                 ret, hw->aq.asq_last_status);
10345                         return -ENOSYS;
10346                 }
10347                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10348                 rte_free(mirr_rule);
10349                 pf->nb_mirror_rule--;
10350         } else {
10351                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10352                 return -ENOENT;
10353         }
10354         return 0;
10355 }
10356
10357 static uint64_t
10358 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10359 {
10360         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10361         uint64_t systim_cycles;
10362
10363         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10364         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10365                         << 32;
10366
10367         return systim_cycles;
10368 }
10369
10370 static uint64_t
10371 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10372 {
10373         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10374         uint64_t rx_tstamp;
10375
10376         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10377         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10378                         << 32;
10379
10380         return rx_tstamp;
10381 }
10382
10383 static uint64_t
10384 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10385 {
10386         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10387         uint64_t tx_tstamp;
10388
10389         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10390         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10391                         << 32;
10392
10393         return tx_tstamp;
10394 }
10395
10396 static void
10397 i40e_start_timecounters(struct rte_eth_dev *dev)
10398 {
10399         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10400         struct i40e_adapter *adapter =
10401                         (struct i40e_adapter *)dev->data->dev_private;
10402         struct rte_eth_link link;
10403         uint32_t tsync_inc_l;
10404         uint32_t tsync_inc_h;
10405
10406         /* Get current link speed. */
10407         i40e_dev_link_update(dev, 1);
10408         rte_eth_linkstatus_get(dev, &link);
10409
10410         switch (link.link_speed) {
10411         case ETH_SPEED_NUM_40G:
10412                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10413                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10414                 break;
10415         case ETH_SPEED_NUM_10G:
10416                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10417                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10418                 break;
10419         case ETH_SPEED_NUM_1G:
10420                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10421                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10422                 break;
10423         default:
10424                 tsync_inc_l = 0x0;
10425                 tsync_inc_h = 0x0;
10426         }
10427
10428         /* Set the timesync increment value. */
10429         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10430         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10431
10432         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10433         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10434         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10435
10436         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10437         adapter->systime_tc.cc_shift = 0;
10438         adapter->systime_tc.nsec_mask = 0;
10439
10440         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10441         adapter->rx_tstamp_tc.cc_shift = 0;
10442         adapter->rx_tstamp_tc.nsec_mask = 0;
10443
10444         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10445         adapter->tx_tstamp_tc.cc_shift = 0;
10446         adapter->tx_tstamp_tc.nsec_mask = 0;
10447 }
10448
10449 static int
10450 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10451 {
10452         struct i40e_adapter *adapter =
10453                         (struct i40e_adapter *)dev->data->dev_private;
10454
10455         adapter->systime_tc.nsec += delta;
10456         adapter->rx_tstamp_tc.nsec += delta;
10457         adapter->tx_tstamp_tc.nsec += delta;
10458
10459         return 0;
10460 }
10461
10462 static int
10463 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10464 {
10465         uint64_t ns;
10466         struct i40e_adapter *adapter =
10467                         (struct i40e_adapter *)dev->data->dev_private;
10468
10469         ns = rte_timespec_to_ns(ts);
10470
10471         /* Set the timecounters to a new value. */
10472         adapter->systime_tc.nsec = ns;
10473         adapter->rx_tstamp_tc.nsec = ns;
10474         adapter->tx_tstamp_tc.nsec = ns;
10475
10476         return 0;
10477 }
10478
10479 static int
10480 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10481 {
10482         uint64_t ns, systime_cycles;
10483         struct i40e_adapter *adapter =
10484                         (struct i40e_adapter *)dev->data->dev_private;
10485
10486         systime_cycles = i40e_read_systime_cyclecounter(dev);
10487         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10488         *ts = rte_ns_to_timespec(ns);
10489
10490         return 0;
10491 }
10492
10493 static int
10494 i40e_timesync_enable(struct rte_eth_dev *dev)
10495 {
10496         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10497         uint32_t tsync_ctl_l;
10498         uint32_t tsync_ctl_h;
10499
10500         /* Stop the timesync system time. */
10501         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10502         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10503         /* Reset the timesync system time value. */
10504         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10505         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10506
10507         i40e_start_timecounters(dev);
10508
10509         /* Clear timesync registers. */
10510         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10511         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10512         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10513         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10514         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10515         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10516
10517         /* Enable timestamping of PTP packets. */
10518         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10519         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10520
10521         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10522         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10523         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10524
10525         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10526         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10527
10528         return 0;
10529 }
10530
10531 static int
10532 i40e_timesync_disable(struct rte_eth_dev *dev)
10533 {
10534         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10535         uint32_t tsync_ctl_l;
10536         uint32_t tsync_ctl_h;
10537
10538         /* Disable timestamping of transmitted PTP packets. */
10539         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10540         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10541
10542         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10543         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10544
10545         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10546         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10547
10548         /* Reset the timesync increment value. */
10549         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10550         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10551
10552         return 0;
10553 }
10554
10555 static int
10556 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10557                                 struct timespec *timestamp, uint32_t flags)
10558 {
10559         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10560         struct i40e_adapter *adapter =
10561                 (struct i40e_adapter *)dev->data->dev_private;
10562
10563         uint32_t sync_status;
10564         uint32_t index = flags & 0x03;
10565         uint64_t rx_tstamp_cycles;
10566         uint64_t ns;
10567
10568         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10569         if ((sync_status & (1 << index)) == 0)
10570                 return -EINVAL;
10571
10572         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10573         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10574         *timestamp = rte_ns_to_timespec(ns);
10575
10576         return 0;
10577 }
10578
10579 static int
10580 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10581                                 struct timespec *timestamp)
10582 {
10583         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10584         struct i40e_adapter *adapter =
10585                 (struct i40e_adapter *)dev->data->dev_private;
10586
10587         uint32_t sync_status;
10588         uint64_t tx_tstamp_cycles;
10589         uint64_t ns;
10590
10591         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10592         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10593                 return -EINVAL;
10594
10595         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10596         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10597         *timestamp = rte_ns_to_timespec(ns);
10598
10599         return 0;
10600 }
10601
10602 /*
10603  * i40e_parse_dcb_configure - parse dcb configure from user
10604  * @dev: the device being configured
10605  * @dcb_cfg: pointer of the result of parse
10606  * @*tc_map: bit map of enabled traffic classes
10607  *
10608  * Returns 0 on success, negative value on failure
10609  */
10610 static int
10611 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10612                          struct i40e_dcbx_config *dcb_cfg,
10613                          uint8_t *tc_map)
10614 {
10615         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10616         uint8_t i, tc_bw, bw_lf;
10617
10618         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10619
10620         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10621         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10622                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10623                 return -EINVAL;
10624         }
10625
10626         /* assume each tc has the same bw */
10627         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10628         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10629                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10630         /* to ensure the sum of tcbw is equal to 100 */
10631         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10632         for (i = 0; i < bw_lf; i++)
10633                 dcb_cfg->etscfg.tcbwtable[i]++;
10634
10635         /* assume each tc has the same Transmission Selection Algorithm */
10636         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10637                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10638
10639         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10640                 dcb_cfg->etscfg.prioritytable[i] =
10641                                 dcb_rx_conf->dcb_tc[i];
10642
10643         /* FW needs one App to configure HW */
10644         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10645         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10646         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10647         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10648
10649         if (dcb_rx_conf->nb_tcs == 0)
10650                 *tc_map = 1; /* tc0 only */
10651         else
10652                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10653
10654         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10655                 dcb_cfg->pfc.willing = 0;
10656                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10657                 dcb_cfg->pfc.pfcenable = *tc_map;
10658         }
10659         return 0;
10660 }
10661
10662
10663 static enum i40e_status_code
10664 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10665                               struct i40e_aqc_vsi_properties_data *info,
10666                               uint8_t enabled_tcmap)
10667 {
10668         enum i40e_status_code ret;
10669         int i, total_tc = 0;
10670         uint16_t qpnum_per_tc, bsf, qp_idx;
10671         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10672         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10673         uint16_t used_queues;
10674
10675         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10676         if (ret != I40E_SUCCESS)
10677                 return ret;
10678
10679         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10680                 if (enabled_tcmap & (1 << i))
10681                         total_tc++;
10682         }
10683         if (total_tc == 0)
10684                 total_tc = 1;
10685         vsi->enabled_tc = enabled_tcmap;
10686
10687         /* different VSI has different queues assigned */
10688         if (vsi->type == I40E_VSI_MAIN)
10689                 used_queues = dev_data->nb_rx_queues -
10690                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10691         else if (vsi->type == I40E_VSI_VMDQ2)
10692                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10693         else {
10694                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10695                 return I40E_ERR_NO_AVAILABLE_VSI;
10696         }
10697
10698         qpnum_per_tc = used_queues / total_tc;
10699         /* Number of queues per enabled TC */
10700         if (qpnum_per_tc == 0) {
10701                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10702                 return I40E_ERR_INVALID_QP_ID;
10703         }
10704         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10705                                 I40E_MAX_Q_PER_TC);
10706         bsf = rte_bsf32(qpnum_per_tc);
10707
10708         /**
10709          * Configure TC and queue mapping parameters, for enabled TC,
10710          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10711          * default queue will serve it.
10712          */
10713         qp_idx = 0;
10714         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10715                 if (vsi->enabled_tc & (1 << i)) {
10716                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10717                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10718                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10719                         qp_idx += qpnum_per_tc;
10720                 } else
10721                         info->tc_mapping[i] = 0;
10722         }
10723
10724         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10725         if (vsi->type == I40E_VSI_SRIOV) {
10726                 info->mapping_flags |=
10727                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10728                 for (i = 0; i < vsi->nb_qps; i++)
10729                         info->queue_mapping[i] =
10730                                 rte_cpu_to_le_16(vsi->base_queue + i);
10731         } else {
10732                 info->mapping_flags |=
10733                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10734                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10735         }
10736         info->valid_sections |=
10737                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10738
10739         return I40E_SUCCESS;
10740 }
10741
10742 /*
10743  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10744  * @veb: VEB to be configured
10745  * @tc_map: enabled TC bitmap
10746  *
10747  * Returns 0 on success, negative value on failure
10748  */
10749 static enum i40e_status_code
10750 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10751 {
10752         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10753         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10754         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10755         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10756         enum i40e_status_code ret = I40E_SUCCESS;
10757         int i;
10758         uint32_t bw_max;
10759
10760         /* Check if enabled_tc is same as existing or new TCs */
10761         if (veb->enabled_tc == tc_map)
10762                 return ret;
10763
10764         /* configure tc bandwidth */
10765         memset(&veb_bw, 0, sizeof(veb_bw));
10766         veb_bw.tc_valid_bits = tc_map;
10767         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10768         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10769                 if (tc_map & BIT_ULL(i))
10770                         veb_bw.tc_bw_share_credits[i] = 1;
10771         }
10772         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10773                                                    &veb_bw, NULL);
10774         if (ret) {
10775                 PMD_INIT_LOG(ERR,
10776                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10777                         hw->aq.asq_last_status);
10778                 return ret;
10779         }
10780
10781         memset(&ets_query, 0, sizeof(ets_query));
10782         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10783                                                    &ets_query, NULL);
10784         if (ret != I40E_SUCCESS) {
10785                 PMD_DRV_LOG(ERR,
10786                         "Failed to get switch_comp ETS configuration %u",
10787                         hw->aq.asq_last_status);
10788                 return ret;
10789         }
10790         memset(&bw_query, 0, sizeof(bw_query));
10791         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10792                                                   &bw_query, NULL);
10793         if (ret != I40E_SUCCESS) {
10794                 PMD_DRV_LOG(ERR,
10795                         "Failed to get switch_comp bandwidth configuration %u",
10796                         hw->aq.asq_last_status);
10797                 return ret;
10798         }
10799
10800         /* store and print out BW info */
10801         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10802         veb->bw_info.bw_max = ets_query.tc_bw_max;
10803         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10804         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10805         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10806                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10807                      I40E_16_BIT_WIDTH);
10808         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10809                 veb->bw_info.bw_ets_share_credits[i] =
10810                                 bw_query.tc_bw_share_credits[i];
10811                 veb->bw_info.bw_ets_credits[i] =
10812                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10813                 /* 4 bits per TC, 4th bit is reserved */
10814                 veb->bw_info.bw_ets_max[i] =
10815                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10816                                   RTE_LEN2MASK(3, uint8_t));
10817                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10818                             veb->bw_info.bw_ets_share_credits[i]);
10819                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10820                             veb->bw_info.bw_ets_credits[i]);
10821                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10822                             veb->bw_info.bw_ets_max[i]);
10823         }
10824
10825         veb->enabled_tc = tc_map;
10826
10827         return ret;
10828 }
10829
10830
10831 /*
10832  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10833  * @vsi: VSI to be configured
10834  * @tc_map: enabled TC bitmap
10835  *
10836  * Returns 0 on success, negative value on failure
10837  */
10838 static enum i40e_status_code
10839 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10840 {
10841         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10842         struct i40e_vsi_context ctxt;
10843         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10844         enum i40e_status_code ret = I40E_SUCCESS;
10845         int i;
10846
10847         /* Check if enabled_tc is same as existing or new TCs */
10848         if (vsi->enabled_tc == tc_map)
10849                 return ret;
10850
10851         /* configure tc bandwidth */
10852         memset(&bw_data, 0, sizeof(bw_data));
10853         bw_data.tc_valid_bits = tc_map;
10854         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10855         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10856                 if (tc_map & BIT_ULL(i))
10857                         bw_data.tc_bw_credits[i] = 1;
10858         }
10859         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10860         if (ret) {
10861                 PMD_INIT_LOG(ERR,
10862                         "AQ command Config VSI BW allocation per TC failed = %d",
10863                         hw->aq.asq_last_status);
10864                 goto out;
10865         }
10866         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10867                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10868
10869         /* Update Queue Pairs Mapping for currently enabled UPs */
10870         ctxt.seid = vsi->seid;
10871         ctxt.pf_num = hw->pf_id;
10872         ctxt.vf_num = 0;
10873         ctxt.uplink_seid = vsi->uplink_seid;
10874         ctxt.info = vsi->info;
10875         i40e_get_cap(hw);
10876         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10877         if (ret)
10878                 goto out;
10879
10880         /* Update the VSI after updating the VSI queue-mapping information */
10881         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10882         if (ret) {
10883                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10884                         hw->aq.asq_last_status);
10885                 goto out;
10886         }
10887         /* update the local VSI info with updated queue map */
10888         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10889                                         sizeof(vsi->info.tc_mapping));
10890         rte_memcpy(&vsi->info.queue_mapping,
10891                         &ctxt.info.queue_mapping,
10892                 sizeof(vsi->info.queue_mapping));
10893         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10894         vsi->info.valid_sections = 0;
10895
10896         /* query and update current VSI BW information */
10897         ret = i40e_vsi_get_bw_config(vsi);
10898         if (ret) {
10899                 PMD_INIT_LOG(ERR,
10900                          "Failed updating vsi bw info, err %s aq_err %s",
10901                          i40e_stat_str(hw, ret),
10902                          i40e_aq_str(hw, hw->aq.asq_last_status));
10903                 goto out;
10904         }
10905
10906         vsi->enabled_tc = tc_map;
10907
10908 out:
10909         return ret;
10910 }
10911
10912 /*
10913  * i40e_dcb_hw_configure - program the dcb setting to hw
10914  * @pf: pf the configuration is taken on
10915  * @new_cfg: new configuration
10916  * @tc_map: enabled TC bitmap
10917  *
10918  * Returns 0 on success, negative value on failure
10919  */
10920 static enum i40e_status_code
10921 i40e_dcb_hw_configure(struct i40e_pf *pf,
10922                       struct i40e_dcbx_config *new_cfg,
10923                       uint8_t tc_map)
10924 {
10925         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10926         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10927         struct i40e_vsi *main_vsi = pf->main_vsi;
10928         struct i40e_vsi_list *vsi_list;
10929         enum i40e_status_code ret;
10930         int i;
10931         uint32_t val;
10932
10933         /* Use the FW API if FW > v4.4*/
10934         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10935               (hw->aq.fw_maj_ver >= 5))) {
10936                 PMD_INIT_LOG(ERR,
10937                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10938                 return I40E_ERR_FIRMWARE_API_VERSION;
10939         }
10940
10941         /* Check if need reconfiguration */
10942         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10943                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10944                 return I40E_SUCCESS;
10945         }
10946
10947         /* Copy the new config to the current config */
10948         *old_cfg = *new_cfg;
10949         old_cfg->etsrec = old_cfg->etscfg;
10950         ret = i40e_set_dcb_config(hw);
10951         if (ret) {
10952                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10953                          i40e_stat_str(hw, ret),
10954                          i40e_aq_str(hw, hw->aq.asq_last_status));
10955                 return ret;
10956         }
10957         /* set receive Arbiter to RR mode and ETS scheme by default */
10958         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10959                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10960                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10961                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10962                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10963                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10964                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10965                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10966                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10967                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10968                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10969                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10970                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10971         }
10972         /* get local mib to check whether it is configured correctly */
10973         /* IEEE mode */
10974         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10975         /* Get Local DCB Config */
10976         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10977                                      &hw->local_dcbx_config);
10978
10979         /* if Veb is created, need to update TC of it at first */
10980         if (main_vsi->veb) {
10981                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10982                 if (ret)
10983                         PMD_INIT_LOG(WARNING,
10984                                  "Failed configuring TC for VEB seid=%d",
10985                                  main_vsi->veb->seid);
10986         }
10987         /* Update each VSI */
10988         i40e_vsi_config_tc(main_vsi, tc_map);
10989         if (main_vsi->veb) {
10990                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10991                         /* Beside main VSI and VMDQ VSIs, only enable default
10992                          * TC for other VSIs
10993                          */
10994                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10995                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10996                                                          tc_map);
10997                         else
10998                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10999                                                          I40E_DEFAULT_TCMAP);
11000                         if (ret)
11001                                 PMD_INIT_LOG(WARNING,
11002                                         "Failed configuring TC for VSI seid=%d",
11003                                         vsi_list->vsi->seid);
11004                         /* continue */
11005                 }
11006         }
11007         return I40E_SUCCESS;
11008 }
11009
11010 /*
11011  * i40e_dcb_init_configure - initial dcb config
11012  * @dev: device being configured
11013  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11014  *
11015  * Returns 0 on success, negative value on failure
11016  */
11017 int
11018 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11019 {
11020         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11021         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11022         int i, ret = 0;
11023
11024         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11025                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11026                 return -ENOTSUP;
11027         }
11028
11029         /* DCB initialization:
11030          * Update DCB configuration from the Firmware and configure
11031          * LLDP MIB change event.
11032          */
11033         if (sw_dcb == TRUE) {
11034                 ret = i40e_init_dcb(hw);
11035                 /* If lldp agent is stopped, the return value from
11036                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11037                  * adminq status. Otherwise, it should return success.
11038                  */
11039                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11040                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11041                         memset(&hw->local_dcbx_config, 0,
11042                                 sizeof(struct i40e_dcbx_config));
11043                         /* set dcb default configuration */
11044                         hw->local_dcbx_config.etscfg.willing = 0;
11045                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11046                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11047                         hw->local_dcbx_config.etscfg.tsatable[0] =
11048                                                 I40E_IEEE_TSA_ETS;
11049                         /* all UPs mapping to TC0 */
11050                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11051                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11052                         hw->local_dcbx_config.etsrec =
11053                                 hw->local_dcbx_config.etscfg;
11054                         hw->local_dcbx_config.pfc.willing = 0;
11055                         hw->local_dcbx_config.pfc.pfccap =
11056                                                 I40E_MAX_TRAFFIC_CLASS;
11057                         /* FW needs one App to configure HW */
11058                         hw->local_dcbx_config.numapps = 1;
11059                         hw->local_dcbx_config.app[0].selector =
11060                                                 I40E_APP_SEL_ETHTYPE;
11061                         hw->local_dcbx_config.app[0].priority = 3;
11062                         hw->local_dcbx_config.app[0].protocolid =
11063                                                 I40E_APP_PROTOID_FCOE;
11064                         ret = i40e_set_dcb_config(hw);
11065                         if (ret) {
11066                                 PMD_INIT_LOG(ERR,
11067                                         "default dcb config fails. err = %d, aq_err = %d.",
11068                                         ret, hw->aq.asq_last_status);
11069                                 return -ENOSYS;
11070                         }
11071                 } else {
11072                         PMD_INIT_LOG(ERR,
11073                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11074                                 ret, hw->aq.asq_last_status);
11075                         return -ENOTSUP;
11076                 }
11077         } else {
11078                 ret = i40e_aq_start_lldp(hw, NULL);
11079                 if (ret != I40E_SUCCESS)
11080                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11081
11082                 ret = i40e_init_dcb(hw);
11083                 if (!ret) {
11084                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11085                                 PMD_INIT_LOG(ERR,
11086                                         "HW doesn't support DCBX offload.");
11087                                 return -ENOTSUP;
11088                         }
11089                 } else {
11090                         PMD_INIT_LOG(ERR,
11091                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11092                                 ret, hw->aq.asq_last_status);
11093                         return -ENOTSUP;
11094                 }
11095         }
11096         return 0;
11097 }
11098
11099 /*
11100  * i40e_dcb_setup - setup dcb related config
11101  * @dev: device being configured
11102  *
11103  * Returns 0 on success, negative value on failure
11104  */
11105 static int
11106 i40e_dcb_setup(struct rte_eth_dev *dev)
11107 {
11108         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11109         struct i40e_dcbx_config dcb_cfg;
11110         uint8_t tc_map = 0;
11111         int ret = 0;
11112
11113         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11114                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11115                 return -ENOTSUP;
11116         }
11117
11118         if (pf->vf_num != 0)
11119                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11120
11121         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11122         if (ret) {
11123                 PMD_INIT_LOG(ERR, "invalid dcb config");
11124                 return -EINVAL;
11125         }
11126         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11127         if (ret) {
11128                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11129                 return -ENOSYS;
11130         }
11131
11132         return 0;
11133 }
11134
11135 static int
11136 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11137                       struct rte_eth_dcb_info *dcb_info)
11138 {
11139         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11140         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11141         struct i40e_vsi *vsi = pf->main_vsi;
11142         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11143         uint16_t bsf, tc_mapping;
11144         int i, j = 0;
11145
11146         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11147                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11148         else
11149                 dcb_info->nb_tcs = 1;
11150         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11151                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11152         for (i = 0; i < dcb_info->nb_tcs; i++)
11153                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11154
11155         /* get queue mapping if vmdq is disabled */
11156         if (!pf->nb_cfg_vmdq_vsi) {
11157                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11158                         if (!(vsi->enabled_tc & (1 << i)))
11159                                 continue;
11160                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11161                         dcb_info->tc_queue.tc_rxq[j][i].base =
11162                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11163                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11164                         dcb_info->tc_queue.tc_txq[j][i].base =
11165                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11166                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11167                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11168                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11169                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11170                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11171                 }
11172                 return 0;
11173         }
11174
11175         /* get queue mapping if vmdq is enabled */
11176         do {
11177                 vsi = pf->vmdq[j].vsi;
11178                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11179                         if (!(vsi->enabled_tc & (1 << i)))
11180                                 continue;
11181                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11182                         dcb_info->tc_queue.tc_rxq[j][i].base =
11183                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11184                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11185                         dcb_info->tc_queue.tc_txq[j][i].base =
11186                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11187                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11188                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11189                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11190                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11191                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11192                 }
11193                 j++;
11194         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11195         return 0;
11196 }
11197
11198 static int
11199 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11200 {
11201         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11202         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11203         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11204         uint16_t msix_intr;
11205
11206         msix_intr = intr_handle->intr_vec[queue_id];
11207         if (msix_intr == I40E_MISC_VEC_ID)
11208                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11209                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11210                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11211                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11212         else
11213                 I40E_WRITE_REG(hw,
11214                                I40E_PFINT_DYN_CTLN(msix_intr -
11215                                                    I40E_RX_VEC_START),
11216                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11217                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11218                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11219
11220         I40E_WRITE_FLUSH(hw);
11221         rte_intr_enable(&pci_dev->intr_handle);
11222
11223         return 0;
11224 }
11225
11226 static int
11227 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11228 {
11229         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11230         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11231         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11232         uint16_t msix_intr;
11233
11234         msix_intr = intr_handle->intr_vec[queue_id];
11235         if (msix_intr == I40E_MISC_VEC_ID)
11236                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11237                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11238         else
11239                 I40E_WRITE_REG(hw,
11240                                I40E_PFINT_DYN_CTLN(msix_intr -
11241                                                    I40E_RX_VEC_START),
11242                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11243         I40E_WRITE_FLUSH(hw);
11244
11245         return 0;
11246 }
11247
11248 static int i40e_get_regs(struct rte_eth_dev *dev,
11249                          struct rte_dev_reg_info *regs)
11250 {
11251         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11252         uint32_t *ptr_data = regs->data;
11253         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11254         const struct i40e_reg_info *reg_info;
11255
11256         if (ptr_data == NULL) {
11257                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11258                 regs->width = sizeof(uint32_t);
11259                 return 0;
11260         }
11261
11262         /* The first few registers have to be read using AQ operations */
11263         reg_idx = 0;
11264         while (i40e_regs_adminq[reg_idx].name) {
11265                 reg_info = &i40e_regs_adminq[reg_idx++];
11266                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11267                         for (arr_idx2 = 0;
11268                                         arr_idx2 <= reg_info->count2;
11269                                         arr_idx2++) {
11270                                 reg_offset = arr_idx * reg_info->stride1 +
11271                                         arr_idx2 * reg_info->stride2;
11272                                 reg_offset += reg_info->base_addr;
11273                                 ptr_data[reg_offset >> 2] =
11274                                         i40e_read_rx_ctl(hw, reg_offset);
11275                         }
11276         }
11277
11278         /* The remaining registers can be read using primitives */
11279         reg_idx = 0;
11280         while (i40e_regs_others[reg_idx].name) {
11281                 reg_info = &i40e_regs_others[reg_idx++];
11282                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11283                         for (arr_idx2 = 0;
11284                                         arr_idx2 <= reg_info->count2;
11285                                         arr_idx2++) {
11286                                 reg_offset = arr_idx * reg_info->stride1 +
11287                                         arr_idx2 * reg_info->stride2;
11288                                 reg_offset += reg_info->base_addr;
11289                                 ptr_data[reg_offset >> 2] =
11290                                         I40E_READ_REG(hw, reg_offset);
11291                         }
11292         }
11293
11294         return 0;
11295 }
11296
11297 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11298 {
11299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11300
11301         /* Convert word count to byte count */
11302         return hw->nvm.sr_size << 1;
11303 }
11304
11305 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11306                            struct rte_dev_eeprom_info *eeprom)
11307 {
11308         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11309         uint16_t *data = eeprom->data;
11310         uint16_t offset, length, cnt_words;
11311         int ret_code;
11312
11313         offset = eeprom->offset >> 1;
11314         length = eeprom->length >> 1;
11315         cnt_words = length;
11316
11317         if (offset > hw->nvm.sr_size ||
11318                 offset + length > hw->nvm.sr_size) {
11319                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11320                 return -EINVAL;
11321         }
11322
11323         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11324
11325         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11326         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11327                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11328                 return -EIO;
11329         }
11330
11331         return 0;
11332 }
11333
11334 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11335                                      struct ether_addr *mac_addr)
11336 {
11337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11338         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11339         struct i40e_vsi *vsi = pf->main_vsi;
11340         struct i40e_mac_filter_info mac_filter;
11341         struct i40e_mac_filter *f;
11342         int ret;
11343
11344         if (!is_valid_assigned_ether_addr(mac_addr)) {
11345                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11346                 return -EINVAL;
11347         }
11348
11349         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11350                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11351                         break;
11352         }
11353
11354         if (f == NULL) {
11355                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11356                 return -EIO;
11357         }
11358
11359         mac_filter = f->mac_info;
11360         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11361         if (ret != I40E_SUCCESS) {
11362                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11363                 return -EIO;
11364         }
11365         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11366         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11367         if (ret != I40E_SUCCESS) {
11368                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11369                 return -EIO;
11370         }
11371         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11372
11373         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11374                                         mac_addr->addr_bytes, NULL);
11375         if (ret != I40E_SUCCESS) {
11376                 PMD_DRV_LOG(ERR, "Failed to change mac");
11377                 return -EIO;
11378         }
11379
11380         return 0;
11381 }
11382
11383 static int
11384 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11385 {
11386         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11387         struct rte_eth_dev_data *dev_data = pf->dev_data;
11388         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11389         int ret = 0;
11390
11391         /* check if mtu is within the allowed range */
11392         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11393                 return -EINVAL;
11394
11395         /* mtu setting is forbidden if port is start */
11396         if (dev_data->dev_started) {
11397                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11398                             dev_data->port_id);
11399                 return -EBUSY;
11400         }
11401
11402         if (frame_size > ETHER_MAX_LEN)
11403                 dev_data->dev_conf.rxmode.offloads |=
11404                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11405         else
11406                 dev_data->dev_conf.rxmode.offloads &=
11407                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11408
11409         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11410
11411         return ret;
11412 }
11413
11414 /* Restore ethertype filter */
11415 static void
11416 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11417 {
11418         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11419         struct i40e_ethertype_filter_list
11420                 *ethertype_list = &pf->ethertype.ethertype_list;
11421         struct i40e_ethertype_filter *f;
11422         struct i40e_control_filter_stats stats;
11423         uint16_t flags;
11424
11425         TAILQ_FOREACH(f, ethertype_list, rules) {
11426                 flags = 0;
11427                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11428                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11429                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11430                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11431                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11432
11433                 memset(&stats, 0, sizeof(stats));
11434                 i40e_aq_add_rem_control_packet_filter(hw,
11435                                             f->input.mac_addr.addr_bytes,
11436                                             f->input.ether_type,
11437                                             flags, pf->main_vsi->seid,
11438                                             f->queue, 1, &stats, NULL);
11439         }
11440         PMD_DRV_LOG(INFO, "Ethertype filter:"
11441                     " mac_etype_used = %u, etype_used = %u,"
11442                     " mac_etype_free = %u, etype_free = %u",
11443                     stats.mac_etype_used, stats.etype_used,
11444                     stats.mac_etype_free, stats.etype_free);
11445 }
11446
11447 /* Restore tunnel filter */
11448 static void
11449 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11450 {
11451         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11452         struct i40e_vsi *vsi;
11453         struct i40e_pf_vf *vf;
11454         struct i40e_tunnel_filter_list
11455                 *tunnel_list = &pf->tunnel.tunnel_list;
11456         struct i40e_tunnel_filter *f;
11457         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11458         bool big_buffer = 0;
11459
11460         TAILQ_FOREACH(f, tunnel_list, rules) {
11461                 if (!f->is_to_vf)
11462                         vsi = pf->main_vsi;
11463                 else {
11464                         vf = &pf->vfs[f->vf_id];
11465                         vsi = vf->vsi;
11466                 }
11467                 memset(&cld_filter, 0, sizeof(cld_filter));
11468                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11469                         (struct ether_addr *)&cld_filter.element.outer_mac);
11470                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11471                         (struct ether_addr *)&cld_filter.element.inner_mac);
11472                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11473                 cld_filter.element.flags = f->input.flags;
11474                 cld_filter.element.tenant_id = f->input.tenant_id;
11475                 cld_filter.element.queue_number = f->queue;
11476                 rte_memcpy(cld_filter.general_fields,
11477                            f->input.general_fields,
11478                            sizeof(f->input.general_fields));
11479
11480                 if (((f->input.flags &
11481                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11482                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11483                     ((f->input.flags &
11484                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11485                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11486                     ((f->input.flags &
11487                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11488                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11489                         big_buffer = 1;
11490
11491                 if (big_buffer)
11492                         i40e_aq_add_cloud_filters_big_buffer(hw,
11493                                              vsi->seid, &cld_filter, 1);
11494                 else
11495                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11496                                                   &cld_filter.element, 1);
11497         }
11498 }
11499
11500 /* Restore rss filter */
11501 static inline void
11502 i40e_rss_filter_restore(struct i40e_pf *pf)
11503 {
11504         struct i40e_rte_flow_rss_conf *conf =
11505                                         &pf->rss_info;
11506         if (conf->num)
11507                 i40e_config_rss_filter(pf, conf, TRUE);
11508 }
11509
11510 static void
11511 i40e_filter_restore(struct i40e_pf *pf)
11512 {
11513         i40e_ethertype_filter_restore(pf);
11514         i40e_tunnel_filter_restore(pf);
11515         i40e_fdir_filter_restore(pf);
11516         i40e_rss_filter_restore(pf);
11517 }
11518
11519 static bool
11520 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11521 {
11522         if (strcmp(dev->device->driver->name, drv->driver.name))
11523                 return false;
11524
11525         return true;
11526 }
11527
11528 bool
11529 is_i40e_supported(struct rte_eth_dev *dev)
11530 {
11531         return is_device_supported(dev, &rte_i40e_pmd);
11532 }
11533
11534 struct i40e_customized_pctype*
11535 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11536 {
11537         int i;
11538
11539         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11540                 if (pf->customized_pctype[i].index == index)
11541                         return &pf->customized_pctype[i];
11542         }
11543         return NULL;
11544 }
11545
11546 static int
11547 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11548                               uint32_t pkg_size, uint32_t proto_num,
11549                               struct rte_pmd_i40e_proto_info *proto,
11550                               enum rte_pmd_i40e_package_op op)
11551 {
11552         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11553         uint32_t pctype_num;
11554         struct rte_pmd_i40e_ptype_info *pctype;
11555         uint32_t buff_size;
11556         struct i40e_customized_pctype *new_pctype = NULL;
11557         uint8_t proto_id;
11558         uint8_t pctype_value;
11559         char name[64];
11560         uint32_t i, j, n;
11561         int ret;
11562
11563         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11564             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11565                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11566                 return -1;
11567         }
11568
11569         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11570                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11571                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11572         if (ret) {
11573                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11574                 return -1;
11575         }
11576         if (!pctype_num) {
11577                 PMD_DRV_LOG(INFO, "No new pctype added");
11578                 return -1;
11579         }
11580
11581         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11582         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11583         if (!pctype) {
11584                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11585                 return -1;
11586         }
11587         /* get information about new pctype list */
11588         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11589                                         (uint8_t *)pctype, buff_size,
11590                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11591         if (ret) {
11592                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11593                 rte_free(pctype);
11594                 return -1;
11595         }
11596
11597         /* Update customized pctype. */
11598         for (i = 0; i < pctype_num; i++) {
11599                 pctype_value = pctype[i].ptype_id;
11600                 memset(name, 0, sizeof(name));
11601                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11602                         proto_id = pctype[i].protocols[j];
11603                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11604                                 continue;
11605                         for (n = 0; n < proto_num; n++) {
11606                                 if (proto[n].proto_id != proto_id)
11607                                         continue;
11608                                 strcat(name, proto[n].name);
11609                                 strcat(name, "_");
11610                                 break;
11611                         }
11612                 }
11613                 name[strlen(name) - 1] = '\0';
11614                 if (!strcmp(name, "GTPC"))
11615                         new_pctype =
11616                                 i40e_find_customized_pctype(pf,
11617                                                       I40E_CUSTOMIZED_GTPC);
11618                 else if (!strcmp(name, "GTPU_IPV4"))
11619                         new_pctype =
11620                                 i40e_find_customized_pctype(pf,
11621                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11622                 else if (!strcmp(name, "GTPU_IPV6"))
11623                         new_pctype =
11624                                 i40e_find_customized_pctype(pf,
11625                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11626                 else if (!strcmp(name, "GTPU"))
11627                         new_pctype =
11628                                 i40e_find_customized_pctype(pf,
11629                                                       I40E_CUSTOMIZED_GTPU);
11630                 if (new_pctype) {
11631                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11632                                 new_pctype->pctype = pctype_value;
11633                                 new_pctype->valid = true;
11634                         } else {
11635                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11636                                 new_pctype->valid = false;
11637                         }
11638                 }
11639         }
11640
11641         rte_free(pctype);
11642         return 0;
11643 }
11644
11645 static int
11646 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11647                              uint32_t pkg_size, uint32_t proto_num,
11648                              struct rte_pmd_i40e_proto_info *proto,
11649                              enum rte_pmd_i40e_package_op op)
11650 {
11651         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11652         uint16_t port_id = dev->data->port_id;
11653         uint32_t ptype_num;
11654         struct rte_pmd_i40e_ptype_info *ptype;
11655         uint32_t buff_size;
11656         uint8_t proto_id;
11657         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11658         uint32_t i, j, n;
11659         bool in_tunnel;
11660         int ret;
11661
11662         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11663             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11664                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11665                 return -1;
11666         }
11667
11668         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11669                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11670                 return 0;
11671         }
11672
11673         /* get information about new ptype num */
11674         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11675                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11676                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11677         if (ret) {
11678                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11679                 return ret;
11680         }
11681         if (!ptype_num) {
11682                 PMD_DRV_LOG(INFO, "No new ptype added");
11683                 return -1;
11684         }
11685
11686         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11687         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11688         if (!ptype) {
11689                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11690                 return -1;
11691         }
11692
11693         /* get information about new ptype list */
11694         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11695                                         (uint8_t *)ptype, buff_size,
11696                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11697         if (ret) {
11698                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11699                 rte_free(ptype);
11700                 return ret;
11701         }
11702
11703         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11704         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11705         if (!ptype_mapping) {
11706                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11707                 rte_free(ptype);
11708                 return -1;
11709         }
11710
11711         /* Update ptype mapping table. */
11712         for (i = 0; i < ptype_num; i++) {
11713                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11714                 ptype_mapping[i].sw_ptype = 0;
11715                 in_tunnel = false;
11716                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11717                         proto_id = ptype[i].protocols[j];
11718                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11719                                 continue;
11720                         for (n = 0; n < proto_num; n++) {
11721                                 if (proto[n].proto_id != proto_id)
11722                                         continue;
11723                                 memset(name, 0, sizeof(name));
11724                                 strcpy(name, proto[n].name);
11725                                 if (!strncasecmp(name, "PPPOE", 5))
11726                                         ptype_mapping[i].sw_ptype |=
11727                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11728                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11729                                          !in_tunnel) {
11730                                         ptype_mapping[i].sw_ptype |=
11731                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11732                                         ptype_mapping[i].sw_ptype |=
11733                                                 RTE_PTYPE_L4_FRAG;
11734                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11735                                            in_tunnel) {
11736                                         ptype_mapping[i].sw_ptype |=
11737                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11738                                         ptype_mapping[i].sw_ptype |=
11739                                                 RTE_PTYPE_INNER_L4_FRAG;
11740                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11741                                         ptype_mapping[i].sw_ptype |=
11742                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11743                                         in_tunnel = true;
11744                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11745                                            !in_tunnel)
11746                                         ptype_mapping[i].sw_ptype |=
11747                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11748                                 else if (!strncasecmp(name, "IPV4", 4) &&
11749                                          in_tunnel)
11750                                         ptype_mapping[i].sw_ptype |=
11751                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11752                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11753                                          !in_tunnel) {
11754                                         ptype_mapping[i].sw_ptype |=
11755                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11756                                         ptype_mapping[i].sw_ptype |=
11757                                                 RTE_PTYPE_L4_FRAG;
11758                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11759                                            in_tunnel) {
11760                                         ptype_mapping[i].sw_ptype |=
11761                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11762                                         ptype_mapping[i].sw_ptype |=
11763                                                 RTE_PTYPE_INNER_L4_FRAG;
11764                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11765                                         ptype_mapping[i].sw_ptype |=
11766                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11767                                         in_tunnel = true;
11768                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11769                                            !in_tunnel)
11770                                         ptype_mapping[i].sw_ptype |=
11771                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11772                                 else if (!strncasecmp(name, "IPV6", 4) &&
11773                                          in_tunnel)
11774                                         ptype_mapping[i].sw_ptype |=
11775                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11776                                 else if (!strncasecmp(name, "UDP", 3) &&
11777                                          !in_tunnel)
11778                                         ptype_mapping[i].sw_ptype |=
11779                                                 RTE_PTYPE_L4_UDP;
11780                                 else if (!strncasecmp(name, "UDP", 3) &&
11781                                          in_tunnel)
11782                                         ptype_mapping[i].sw_ptype |=
11783                                                 RTE_PTYPE_INNER_L4_UDP;
11784                                 else if (!strncasecmp(name, "TCP", 3) &&
11785                                          !in_tunnel)
11786                                         ptype_mapping[i].sw_ptype |=
11787                                                 RTE_PTYPE_L4_TCP;
11788                                 else if (!strncasecmp(name, "TCP", 3) &&
11789                                          in_tunnel)
11790                                         ptype_mapping[i].sw_ptype |=
11791                                                 RTE_PTYPE_INNER_L4_TCP;
11792                                 else if (!strncasecmp(name, "SCTP", 4) &&
11793                                          !in_tunnel)
11794                                         ptype_mapping[i].sw_ptype |=
11795                                                 RTE_PTYPE_L4_SCTP;
11796                                 else if (!strncasecmp(name, "SCTP", 4) &&
11797                                          in_tunnel)
11798                                         ptype_mapping[i].sw_ptype |=
11799                                                 RTE_PTYPE_INNER_L4_SCTP;
11800                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11801                                           !strncasecmp(name, "ICMPV6", 6)) &&
11802                                          !in_tunnel)
11803                                         ptype_mapping[i].sw_ptype |=
11804                                                 RTE_PTYPE_L4_ICMP;
11805                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11806                                           !strncasecmp(name, "ICMPV6", 6)) &&
11807                                          in_tunnel)
11808                                         ptype_mapping[i].sw_ptype |=
11809                                                 RTE_PTYPE_INNER_L4_ICMP;
11810                                 else if (!strncasecmp(name, "GTPC", 4)) {
11811                                         ptype_mapping[i].sw_ptype |=
11812                                                 RTE_PTYPE_TUNNEL_GTPC;
11813                                         in_tunnel = true;
11814                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11815                                         ptype_mapping[i].sw_ptype |=
11816                                                 RTE_PTYPE_TUNNEL_GTPU;
11817                                         in_tunnel = true;
11818                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11819                                         ptype_mapping[i].sw_ptype |=
11820                                                 RTE_PTYPE_TUNNEL_GRENAT;
11821                                         in_tunnel = true;
11822                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11823                                         ptype_mapping[i].sw_ptype |=
11824                                                 RTE_PTYPE_TUNNEL_L2TP;
11825                                         in_tunnel = true;
11826                                 }
11827
11828                                 break;
11829                         }
11830                 }
11831         }
11832
11833         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11834                                                 ptype_num, 0);
11835         if (ret)
11836                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11837
11838         rte_free(ptype_mapping);
11839         rte_free(ptype);
11840         return ret;
11841 }
11842
11843 void
11844 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11845                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11846 {
11847         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11848         uint32_t proto_num;
11849         struct rte_pmd_i40e_proto_info *proto;
11850         uint32_t buff_size;
11851         uint32_t i;
11852         int ret;
11853
11854         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11855             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11856                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11857                 return;
11858         }
11859
11860         /* get information about protocol number */
11861         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11862                                        (uint8_t *)&proto_num, sizeof(proto_num),
11863                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11864         if (ret) {
11865                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11866                 return;
11867         }
11868         if (!proto_num) {
11869                 PMD_DRV_LOG(INFO, "No new protocol added");
11870                 return;
11871         }
11872
11873         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11874         proto = rte_zmalloc("new_proto", buff_size, 0);
11875         if (!proto) {
11876                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11877                 return;
11878         }
11879
11880         /* get information about protocol list */
11881         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11882                                         (uint8_t *)proto, buff_size,
11883                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11884         if (ret) {
11885                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11886                 rte_free(proto);
11887                 return;
11888         }
11889
11890         /* Check if GTP is supported. */
11891         for (i = 0; i < proto_num; i++) {
11892                 if (!strncmp(proto[i].name, "GTP", 3)) {
11893                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11894                                 pf->gtp_support = true;
11895                         else
11896                                 pf->gtp_support = false;
11897                         break;
11898                 }
11899         }
11900
11901         /* Update customized pctype info */
11902         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11903                                             proto_num, proto, op);
11904         if (ret)
11905                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11906
11907         /* Update customized ptype info */
11908         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11909                                            proto_num, proto, op);
11910         if (ret)
11911                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11912
11913         rte_free(proto);
11914 }
11915
11916 /* Create a QinQ cloud filter
11917  *
11918  * The Fortville NIC has limited resources for tunnel filters,
11919  * so we can only reuse existing filters.
11920  *
11921  * In step 1 we define which Field Vector fields can be used for
11922  * filter types.
11923  * As we do not have the inner tag defined as a field,
11924  * we have to define it first, by reusing one of L1 entries.
11925  *
11926  * In step 2 we are replacing one of existing filter types with
11927  * a new one for QinQ.
11928  * As we reusing L1 and replacing L2, some of the default filter
11929  * types will disappear,which depends on L1 and L2 entries we reuse.
11930  *
11931  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11932  *
11933  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11934  *              later when we define the cloud filter.
11935  *      a.      Valid_flags.replace_cloud = 0
11936  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11937  *      c.      New_filter = 0x10
11938  *      d.      TR bit = 0xff (optional, not used here)
11939  *      e.      Buffer – 2 entries:
11940  *              i.      Byte 0 = 8 (outer vlan FV index).
11941  *                      Byte 1 = 0 (rsv)
11942  *                      Byte 2-3 = 0x0fff
11943  *              ii.     Byte 0 = 37 (inner vlan FV index).
11944  *                      Byte 1 =0 (rsv)
11945  *                      Byte 2-3 = 0x0fff
11946  *
11947  * Step 2:
11948  * 2.   Create cloud filter using two L1 filters entries: stag and
11949  *              new filter(outer vlan+ inner vlan)
11950  *      a.      Valid_flags.replace_cloud = 1
11951  *      b.      Old_filter = 1 (instead of outer IP)
11952  *      c.      New_filter = 0x10
11953  *      d.      Buffer – 2 entries:
11954  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11955  *                      Byte 1-3 = 0 (rsv)
11956  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11957  *                      Byte 9-11 = 0 (rsv)
11958  */
11959 static int
11960 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11961 {
11962         int ret = -ENOTSUP;
11963         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11964         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11965         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11966
11967         if (pf->support_multi_driver) {
11968                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
11969                 return ret;
11970         }
11971
11972         /* Init */
11973         memset(&filter_replace, 0,
11974                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11975         memset(&filter_replace_buf, 0,
11976                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11977
11978         /* create L1 filter */
11979         filter_replace.old_filter_type =
11980                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11981         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11982         filter_replace.tr_bit = 0;
11983
11984         /* Prepare the buffer, 2 entries */
11985         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11986         filter_replace_buf.data[0] |=
11987                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11988         /* Field Vector 12b mask */
11989         filter_replace_buf.data[2] = 0xff;
11990         filter_replace_buf.data[3] = 0x0f;
11991         filter_replace_buf.data[4] =
11992                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11993         filter_replace_buf.data[4] |=
11994                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11995         /* Field Vector 12b mask */
11996         filter_replace_buf.data[6] = 0xff;
11997         filter_replace_buf.data[7] = 0x0f;
11998         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11999                         &filter_replace_buf);
12000         if (ret != I40E_SUCCESS)
12001                 return ret;
12002         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12003                     "cloud l1 type is changed from 0x%x to 0x%x",
12004                     filter_replace.old_filter_type,
12005                     filter_replace.new_filter_type);
12006
12007         /* Apply the second L2 cloud filter */
12008         memset(&filter_replace, 0,
12009                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12010         memset(&filter_replace_buf, 0,
12011                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12012
12013         /* create L2 filter, input for L2 filter will be L1 filter  */
12014         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12015         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12016         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12017
12018         /* Prepare the buffer, 2 entries */
12019         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12020         filter_replace_buf.data[0] |=
12021                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12022         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12023         filter_replace_buf.data[4] |=
12024                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12025         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12026                         &filter_replace_buf);
12027         if (!ret) {
12028                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
12029                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12030                             "cloud filter type is changed from 0x%x to 0x%x",
12031                             filter_replace.old_filter_type,
12032                             filter_replace.new_filter_type);
12033         }
12034         return ret;
12035 }
12036
12037 int
12038 i40e_config_rss_filter(struct i40e_pf *pf,
12039                 struct i40e_rte_flow_rss_conf *conf, bool add)
12040 {
12041         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12042         uint32_t i, lut = 0;
12043         uint16_t j, num;
12044         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
12045         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12046
12047         if (!add) {
12048                 if (memcmp(conf, rss_info,
12049                         sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
12050                         i40e_pf_disable_rss(pf);
12051                         memset(rss_info, 0,
12052                                 sizeof(struct i40e_rte_flow_rss_conf));
12053                         return 0;
12054                 }
12055                 return -EINVAL;
12056         }
12057
12058         if (rss_info->num)
12059                 return -EINVAL;
12060
12061         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12062          * It's necessary to calculate the actual PF queues that are configured.
12063          */
12064         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12065                 num = i40e_pf_calc_configured_queues_num(pf);
12066         else
12067                 num = pf->dev_data->nb_rx_queues;
12068
12069         num = RTE_MIN(num, conf->num);
12070         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12071                         num);
12072
12073         if (num == 0) {
12074                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12075                 return -ENOTSUP;
12076         }
12077
12078         /* Fill in redirection table */
12079         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12080                 if (j == num)
12081                         j = 0;
12082                 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
12083                         hw->func_caps.rss_table_entry_width) - 1));
12084                 if ((i & 3) == 3)
12085                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12086         }
12087
12088         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12089                 i40e_pf_disable_rss(pf);
12090                 return 0;
12091         }
12092         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12093                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12094                 /* Random default keys */
12095                 static uint32_t rss_key_default[] = {0x6b793944,
12096                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12097                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12098                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12099
12100                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12101                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12102                                                         sizeof(uint32_t);
12103         }
12104
12105         i40e_hw_rss_hash_set(pf, &rss_conf);
12106
12107         rte_memcpy(rss_info,
12108                 conf, sizeof(struct i40e_rte_flow_rss_conf));
12109
12110         return 0;
12111 }
12112
12113 RTE_INIT(i40e_init_log);
12114 static void
12115 i40e_init_log(void)
12116 {
12117         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12118         if (i40e_logtype_init >= 0)
12119                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12120         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12121         if (i40e_logtype_driver >= 0)
12122                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12123 }
12124
12125 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12126                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12127                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");