drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 /* Additional timesync values. */
 129 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 130 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 131 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 132 #define I40E_PRTTSYN_TSYNENA     0x80000000
 133 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 134 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 135
 136 #define I40E_MAX_PERCENT            100
 137 #define I40E_DEFAULT_DCB_APP_NUM    1
 138 #define I40E_DEFAULT_DCB_APP_PRIO   3
 139
 140 #define I40E_INSET_NONE            0x00000000000000000ULL
 141
 142 /* bit0 ~ bit 7 */
 143 #define I40E_INSET_DMAC            0x0000000000000001ULL
 144 #define I40E_INSET_SMAC            0x0000000000000002ULL
 145 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 146 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 147 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 148
 149 /* bit 8 ~ bit 15 */
 150 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 151 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 152 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 153 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 154 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 155 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 156 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 157
 158 /* bit 16 ~ bit 31 */
 159 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 160 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 161 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 162 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 163 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 164 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 165 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 166 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 167
 168 /* bit 32 ~ bit 47, tunnel fields */
 169 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 170 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 171 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 172 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 173 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 174 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 175
 176 /* bit 48 ~ bit 55 */
 177 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 178
 179 /* bit 56 ~ bit 63, Flex Payload */
 180 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 181 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD \
 189         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 190         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 191         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 192         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 193
 194 /**
 195  * Below are values for writing un-exposed registers suggested
 196  * by silicon experts
 197  */
 198 /* Destination MAC address */
 199 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 200 /* Source MAC address */
 201 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 202 /* VLAN tag in the outer L2 header */
 203 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0080000000000000ULL
 204 /* VLAN tag in the inner L2 header */
 205 #define I40E_REG_INSET_L2_INNER_VLAN             0x0100000000000000ULL
 206 /* Source IPv4 address */
 207 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 208 /* Destination IPv4 address */
 209 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 210 /* IPv4 Type of Service (TOS) */
 211 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 212 /* IPv4 Protocol */
 213 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 214 /* Source IPv6 address */
 215 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 216 /* Destination IPv6 address */
 217 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 218 /* IPv6 Traffic Class (TC) */
 219 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 220 /* IPv6 Next Header */
 221 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 222 /* Source L4 port */
 223 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 224 /* Destination L4 port */
 225 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 226 /* SCTP verification tag */
 227 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 228 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 229 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 230 /* Source port of tunneling UDP */
 231 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 232 /* Destination port of tunneling UDP */
 233 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 234 /* UDP Tunneling ID, NVGRE/GRE key */
 235 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 236 /* Last ether type */
 237 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 238 /* Tunneling outer destination IPv4 address */
 239 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 240 /* Tunneling outer destination IPv6 address */
 241 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 242 /* 1st word of flex payload */
 243 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 244 /* 2nd word of flex payload */
 245 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 246 /* 3rd word of flex payload */
 247 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 248 /* 4th word of flex payload */
 249 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 250 /* 5th word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 252 /* 6th word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 254 /* 7th word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 256 /* 8th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 258
 259 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 260
 261 #define I40E_TRANSLATE_INSET 0
 262 #define I40E_TRANSLATE_REG   1
 263
 264 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 265 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 266 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 267 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 268
 269 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 270 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 271 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 272         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 273
 274 /* PCI offset for querying capability */
 275 #define PCI_DEV_CAP_REG            0xA4
 276 /* PCI offset for enabling/disabling Extended Tag */
 277 #define PCI_DEV_CTRL_REG           0xA8
 278 /* Bit mask of Extended Tag capability */
 279 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 280 /* Bit shift of Extended Tag enable/disable */
 281 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 282 /* Bit mask of Extended Tag enable/disable */
 283 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 284
 285 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 286 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 287 static int i40e_dev_configure(struct rte_eth_dev *dev);
 288 static int i40e_dev_start(struct rte_eth_dev *dev);
 289 static void i40e_dev_stop(struct rte_eth_dev *dev);
 290 static void i40e_dev_close(struct rte_eth_dev *dev);
 291 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 292 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 293 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 294 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 295 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 296 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 297 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 298                                struct rte_eth_stats *stats);
 299 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 300                                struct rte_eth_xstats *xstats, unsigned n);
 301 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 302 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 303                                             uint16_t queue_id,
 304                                             uint8_t stat_idx,
 305                                             uint8_t is_rx);
 306 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 307                               struct rte_eth_dev_info *dev_info);
 308 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 309                                 uint16_t vlan_id,
 310                                 int on);
 311 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 312                               enum rte_vlan_type vlan_type,
 313                               uint16_t tpid);
 314 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 315 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 316                                       uint16_t queue,
 317                                       int on);
 318 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 319 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 320 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 321 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 322                               struct rte_eth_fc_conf *fc_conf);
 323 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 324                               struct rte_eth_fc_conf *fc_conf);
 325 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 326                                        struct rte_eth_pfc_conf *pfc_conf);
 327 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 328                           struct ether_addr *mac_addr,
 329                           uint32_t index,
 330                           uint32_t pool);
 331 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 332 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 333                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 334                                     uint16_t reta_size);
 335 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 336                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 337                                    uint16_t reta_size);
 338
 339 static int i40e_get_cap(struct i40e_hw *hw);
 340 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 341 static int i40e_pf_setup(struct i40e_pf *pf);
 342 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 343 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 344 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 345 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 346 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 347                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 348 static void i40e_stat_update_48(struct i40e_hw *hw,
 349                                uint32_t hireg,
 350                                uint32_t loreg,
 351                                bool offset_loaded,
 352                                uint64_t *offset,
 353                                uint64_t *stat);
 354 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 355 static void i40e_dev_interrupt_handler(
 356                 __rte_unused struct rte_intr_handle *handle, void *param);
 357 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 358                                 uint32_t base, uint32_t num);
 359 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 360 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 361                         uint32_t base);
 362 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 363                         uint16_t num);
 364 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 365 static int i40e_veb_release(struct i40e_veb *veb);
 366 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 367                                                 struct i40e_vsi *vsi);
 368 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 369 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 370 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 371                                              struct i40e_macvlan_filter *mv_f,
 372                                              int num,
 373                                              struct ether_addr *addr);
 374 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 375                                              struct i40e_macvlan_filter *mv_f,
 376                                              int num,
 377                                              uint16_t vlan);
 378 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 379 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 380                                     struct rte_eth_rss_conf *rss_conf);
 381 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 382                                       struct rte_eth_rss_conf *rss_conf);
 383 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                         struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                         struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 388                         struct rte_eth_ethertype_filter *filter,
 389                         bool add);
 390 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 391                                 enum rte_filter_op filter_op,
 392                                 void *arg);
 393 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 394                                 enum rte_filter_type filter_type,
 395                                 enum rte_filter_op filter_op,
 396                                 void *arg);
 397 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 398                                   struct rte_eth_dcb_info *dcb_info);
 399 static void i40e_configure_registers(struct i40e_hw *hw);
 400 static void i40e_hw_init(struct rte_eth_dev *dev);
 401 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 402 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 403                         struct rte_eth_mirror_conf *mirror_conf,
 404                         uint8_t sw_id, uint8_t on);
 405 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 406
 407 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 408 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 409 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 410                                            struct timespec *timestamp,
 411                                            uint32_t flags);
 412 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 413                                            struct timespec *timestamp);
 414 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 415
 416 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 417
 418 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 419                                    struct timespec *timestamp);
 420 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 421                                     const struct timespec *timestamp);
 422
 423 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 424                                          uint16_t queue_id);
 425 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 426                                           uint16_t queue_id);
 427
 428
 429 static const struct rte_pci_id pci_id_i40e_map[] = {
 430 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 431 #include "rte_pci_dev_ids.h"
 432 { .vendor_id = 0, /* sentinel */ },
 433 };
 434
 435 static const struct eth_dev_ops i40e_eth_dev_ops = {
 436         .dev_configure                = i40e_dev_configure,
 437         .dev_start                    = i40e_dev_start,
 438         .dev_stop                     = i40e_dev_stop,
 439         .dev_close                    = i40e_dev_close,
 440         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 441         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 442         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 443         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 444         .dev_set_link_up              = i40e_dev_set_link_up,
 445         .dev_set_link_down            = i40e_dev_set_link_down,
 446         .link_update                  = i40e_dev_link_update,
 447         .stats_get                    = i40e_dev_stats_get,
 448         .xstats_get                   = i40e_dev_xstats_get,
 449         .stats_reset                  = i40e_dev_stats_reset,
 450         .xstats_reset                 = i40e_dev_stats_reset,
 451         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 452         .dev_infos_get                = i40e_dev_info_get,
 453         .vlan_filter_set              = i40e_vlan_filter_set,
 454         .vlan_tpid_set                = i40e_vlan_tpid_set,
 455         .vlan_offload_set             = i40e_vlan_offload_set,
 456         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 457         .vlan_pvid_set                = i40e_vlan_pvid_set,
 458         .rx_queue_start               = i40e_dev_rx_queue_start,
 459         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 460         .tx_queue_start               = i40e_dev_tx_queue_start,
 461         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 462         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 463         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 464         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 465         .rx_queue_release             = i40e_dev_rx_queue_release,
 466         .rx_queue_count               = i40e_dev_rx_queue_count,
 467         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 468         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 469         .tx_queue_release             = i40e_dev_tx_queue_release,
 470         .dev_led_on                   = i40e_dev_led_on,
 471         .dev_led_off                  = i40e_dev_led_off,
 472         .flow_ctrl_get                = i40e_flow_ctrl_get,
 473         .flow_ctrl_set                = i40e_flow_ctrl_set,
 474         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 475         .mac_addr_add                 = i40e_macaddr_add,
 476         .mac_addr_remove              = i40e_macaddr_remove,
 477         .reta_update                  = i40e_dev_rss_reta_update,
 478         .reta_query                   = i40e_dev_rss_reta_query,
 479         .rss_hash_update              = i40e_dev_rss_hash_update,
 480         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 481         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 482         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 483         .filter_ctrl                  = i40e_dev_filter_ctrl,
 484         .rxq_info_get                 = i40e_rxq_info_get,
 485         .txq_info_get                 = i40e_txq_info_get,
 486         .mirror_rule_set              = i40e_mirror_rule_set,
 487         .mirror_rule_reset            = i40e_mirror_rule_reset,
 488         .timesync_enable              = i40e_timesync_enable,
 489         .timesync_disable             = i40e_timesync_disable,
 490         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 491         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 492         .get_dcb_info                 = i40e_dev_get_dcb_info,
 493         .timesync_adjust_time         = i40e_timesync_adjust_time,
 494         .timesync_read_time           = i40e_timesync_read_time,
 495         .timesync_write_time          = i40e_timesync_write_time,
 496 };
 497
 498 /* store statistics names and its offset in stats structure */
 499 struct rte_i40e_xstats_name_off {
 500         char name[RTE_ETH_XSTATS_NAME_SIZE];
 501         unsigned offset;
 502 };
 503
 504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 505         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 506         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 507         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 508         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 509         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 510                 rx_unknown_protocol)},
 511         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 512         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 513         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 514         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 515 };
 516
 517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 518                 sizeof(rte_i40e_stats_strings[0]))
 519
 520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 521         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 522                 tx_dropped_link_down)},
 523         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 524         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 525                 illegal_bytes)},
 526         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 527         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 528                 mac_local_faults)},
 529         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 530                 mac_remote_faults)},
 531         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 532                 rx_length_errors)},
 533         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 534         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 535         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 536         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 537         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 538         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 539                 rx_size_127)},
 540         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 541                 rx_size_255)},
 542         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 543                 rx_size_511)},
 544         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 545                 rx_size_1023)},
 546         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 547                 rx_size_1522)},
 548         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 549                 rx_size_big)},
 550         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_undersize)},
 552         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_oversize)},
 554         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 555                 mac_short_packet_dropped)},
 556         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_fragments)},
 558         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 559         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 560         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 tx_size_127)},
 562         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 tx_size_255)},
 564         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 tx_size_511)},
 566         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 tx_size_1023)},
 568         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 tx_size_1522)},
 570         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 tx_size_big)},
 572         {"rx_flow_director_atr_match_packets",
 573                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 574         {"rx_flow_director_sb_match_packets",
 575                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 576         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 577                 tx_lpi_status)},
 578         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 579                 rx_lpi_status)},
 580         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 581                 tx_lpi_count)},
 582         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 583                 rx_lpi_count)},
 584 };
 585
 586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 587                 sizeof(rte_i40e_hw_port_strings[0]))
 588
 589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 590         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 591                 priority_xon_rx)},
 592         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 593                 priority_xoff_rx)},
 594 };
 595
 596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 597                 sizeof(rte_i40e_rxq_prio_strings[0]))
 598
 599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 600         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 601                 priority_xon_tx)},
 602         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 603                 priority_xoff_tx)},
 604         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 605                 priority_xon_2_xoff)},
 606 };
 607
 608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 609                 sizeof(rte_i40e_txq_prio_strings[0]))
 610
 611 static struct eth_driver rte_i40e_pmd = {
 612         .pci_drv = {
 613                 .name = "rte_i40e_pmd",
 614                 .id_table = pci_id_i40e_map,
 615                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 616                         RTE_PCI_DRV_DETACHABLE,
 617         },
 618         .eth_dev_init = eth_i40e_dev_init,
 619         .eth_dev_uninit = eth_i40e_dev_uninit,
 620         .dev_private_size = sizeof(struct i40e_adapter),
 621 };
 622
 623 static inline int
 624 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 625                                      struct rte_eth_link *link)
 626 {
 627         struct rte_eth_link *dst = link;
 628         struct rte_eth_link *src = &(dev->data->dev_link);
 629
 630         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 631                                         *(uint64_t *)src) == 0)
 632                 return -1;
 633
 634         return 0;
 635 }
 636
 637 static inline int
 638 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 639                                       struct rte_eth_link *link)
 640 {
 641         struct rte_eth_link *dst = &(dev->data->dev_link);
 642         struct rte_eth_link *src = link;
 643
 644         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 645                                         *(uint64_t *)src) == 0)
 646                 return -1;
 647
 648         return 0;
 649 }
 650
 651 /*
 652  * Driver initialization routine.
 653  * Invoked once at EAL init time.
 654  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 655  */
 656 static int
 657 rte_i40e_pmd_init(const char *name __rte_unused,
 658                   const char *params __rte_unused)
 659 {
 660         PMD_INIT_FUNC_TRACE();
 661         rte_eth_driver_register(&rte_i40e_pmd);
 662
 663         return 0;
 664 }
 665
 666 static struct rte_driver rte_i40e_driver = {
 667         .type = PMD_PDEV,
 668         .init = rte_i40e_pmd_init,
 669 };
 670
 671 PMD_REGISTER_DRIVER(rte_i40e_driver);
 672
 673 /*
 674  * Initialize registers for flexible payload, which should be set by NVM.
 675  * This should be removed from code once it is fixed in NVM.
 676  */
 677 #ifndef I40E_GLQF_ORT
 678 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 679 #endif
 680 #ifndef I40E_GLQF_PIT
 681 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 682 #endif
 683
 684 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 685 {
 686         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 687         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 688         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 696
 697         /* GLQF_PIT Registers */
 698         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 699         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 700 }
 701
 702 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 703
 704 /*
 705  * Add a ethertype filter to drop all flow control frames transmitted
 706  * from VSIs.
 707 */
 708 static void
 709 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 710 {
 711         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 712         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 713                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 714                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 715         int ret;
 716
 717         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 718                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 719                                 pf->main_vsi_seid, 0,
 720                                 TRUE, NULL, NULL);
 721         if (ret)
 722                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 723                                   " frames from VSIs.");
 724 }
 725
 726 static int
 727 eth_i40e_dev_init(struct rte_eth_dev *dev)
 728 {
 729         struct rte_pci_device *pci_dev;
 730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 731         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 732         struct i40e_vsi *vsi;
 733         int ret;
 734         uint32_t len;
 735         uint8_t aq_fail = 0;
 736
 737         PMD_INIT_FUNC_TRACE();
 738
 739         dev->dev_ops = &i40e_eth_dev_ops;
 740         dev->rx_pkt_burst = i40e_recv_pkts;
 741         dev->tx_pkt_burst = i40e_xmit_pkts;
 742
 743         /* for secondary processes, we don't initialise any further as primary
 744          * has already done this work. Only check we don't need a different
 745          * RX function */
 746         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 747                 i40e_set_rx_function(dev);
 748                 i40e_set_tx_function(dev);
 749                 return 0;
 750         }
 751         pci_dev = dev->pci_dev;
 752
 753         rte_eth_copy_pci_info(dev, pci_dev);
 754
 755         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 756         pf->adapter->eth_dev = dev;
 757         pf->dev_data = dev->data;
 758
 759         hw->back = I40E_PF_TO_ADAPTER(pf);
 760         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 761         if (!hw->hw_addr) {
 762                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 763                              "as address is NULL");
 764                 return -ENODEV;
 765         }
 766
 767         hw->vendor_id = pci_dev->id.vendor_id;
 768         hw->device_id = pci_dev->id.device_id;
 769         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 770         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 771         hw->bus.device = pci_dev->addr.devid;
 772         hw->bus.func = pci_dev->addr.function;
 773         hw->adapter_stopped = 0;
 774
 775         /* Make sure all is clean before doing PF reset */
 776         i40e_clear_hw(hw);
 777
 778         /* Initialize the hardware */
 779         i40e_hw_init(dev);
 780
 781         /* Reset here to make sure all is clean for each PF */
 782         ret = i40e_pf_reset(hw);
 783         if (ret) {
 784                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 785                 return ret;
 786         }
 787
 788         /* Initialize the shared code (base driver) */
 789         ret = i40e_init_shared_code(hw);
 790         if (ret) {
 791                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 792                 return ret;
 793         }
 794
 795         /*
 796          * To work around the NVM issue,initialize registers
 797          * for flexible payload by software.
 798          * It should be removed once issues are fixed in NVM.
 799          */
 800         i40e_flex_payload_reg_init(hw);
 801
 802         /* Initialize the parameters for adminq */
 803         i40e_init_adminq_parameter(hw);
 804         ret = i40e_init_adminq(hw);
 805         if (ret != I40E_SUCCESS) {
 806                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 807                 return -EIO;
 808         }
 809         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 810                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 811                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 812                      ((hw->nvm.version >> 12) & 0xf),
 813                      ((hw->nvm.version >> 4) & 0xff),
 814                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 815
 816         /* Clear PXE mode */
 817         i40e_clear_pxe_mode(hw);
 818
 819         /*
 820          * On X710, performance number is far from the expectation on recent
 821          * firmware versions. The fix for this issue may not be integrated in
 822          * the following firmware version. So the workaround in software driver
 823          * is needed. It needs to modify the initial values of 3 internal only
 824          * registers. Note that the workaround can be removed when it is fixed
 825          * in firmware in the future.
 826          */
 827         i40e_configure_registers(hw);
 828
 829         /* Get hw capabilities */
 830         ret = i40e_get_cap(hw);
 831         if (ret != I40E_SUCCESS) {
 832                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 833                 goto err_get_capabilities;
 834         }
 835
 836         /* Initialize parameters for PF */
 837         ret = i40e_pf_parameter_init(dev);
 838         if (ret != 0) {
 839                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 840                 goto err_parameter_init;
 841         }
 842
 843         /* Initialize the queue management */
 844         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 845         if (ret < 0) {
 846                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 847                 goto err_qp_pool_init;
 848         }
 849         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 850                                 hw->func_caps.num_msix_vectors - 1);
 851         if (ret < 0) {
 852                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 853                 goto err_msix_pool_init;
 854         }
 855
 856         /* Initialize lan hmc */
 857         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 858                                 hw->func_caps.num_rx_qp, 0, 0);
 859         if (ret != I40E_SUCCESS) {
 860                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 861                 goto err_init_lan_hmc;
 862         }
 863
 864         /* Configure lan hmc */
 865         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 866         if (ret != I40E_SUCCESS) {
 867                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 868                 goto err_configure_lan_hmc;
 869         }
 870
 871         /* Get and check the mac address */
 872         i40e_get_mac_addr(hw, hw->mac.addr);
 873         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 874                 PMD_INIT_LOG(ERR, "mac address is not valid");
 875                 ret = -EIO;
 876                 goto err_get_mac_addr;
 877         }
 878         /* Copy the permanent MAC address */
 879         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 880                         (struct ether_addr *) hw->mac.perm_addr);
 881
 882         /* Disable flow control */
 883         hw->fc.requested_mode = I40E_FC_NONE;
 884         i40e_set_fc(hw, &aq_fail, TRUE);
 885
 886         /* Set the global registers with default ether type value */
 887         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 888         if (ret != I40E_SUCCESS) {
 889                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 890                              "VLAN ether type");
 891                 goto err_setup_pf_switch;
 892         }
 893         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
 894         if (ret != I40E_SUCCESS) {
 895                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 896                              "VLAN ether type");
 897                 goto err_setup_pf_switch;
 898         }
 899
 900         /* PF setup, which includes VSI setup */
 901         ret = i40e_pf_setup(pf);
 902         if (ret) {
 903                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 904                 goto err_setup_pf_switch;
 905         }
 906
 907         vsi = pf->main_vsi;
 908
 909         /* Disable double vlan by default */
 910         i40e_vsi_config_double_vlan(vsi, FALSE);
 911
 912         if (!vsi->max_macaddrs)
 913                 len = ETHER_ADDR_LEN;
 914         else
 915                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 916
 917         /* Should be after VSI initialized */
 918         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 919         if (!dev->data->mac_addrs) {
 920                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 921                                         "for storing mac address");
 922                 goto err_mac_alloc;
 923         }
 924         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 925                                         &dev->data->mac_addrs[0]);
 926
 927         /* initialize pf host driver to setup SRIOV resource if applicable */
 928         i40e_pf_host_init(dev);
 929
 930         /* register callback func to eal lib */
 931         rte_intr_callback_register(&(pci_dev->intr_handle),
 932                 i40e_dev_interrupt_handler, (void *)dev);
 933
 934         /* configure and enable device interrupt */
 935         i40e_pf_config_irq0(hw, TRUE);
 936         i40e_pf_enable_irq0(hw);
 937
 938         /* enable uio intr after callback register */
 939         rte_intr_enable(&(pci_dev->intr_handle));
 940         /*
 941          * Add an ethertype filter to drop all flow control frames transmitted
 942          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 943          * frames to wire.
 944          */
 945         i40e_add_tx_flow_control_drop_filter(pf);
 946
 947         /* Set the max frame size to 0x2600 by default,
 948          * in case other drivers changed the default value.
 949          */
 950         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 951
 952         /* initialize mirror rule list */
 953         TAILQ_INIT(&pf->mirror_list);
 954
 955         /* Init dcb to sw mode by default */
 956         ret = i40e_dcb_init_configure(dev, TRUE);
 957         if (ret != I40E_SUCCESS) {
 958                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 959                 pf->flags &= ~I40E_FLAG_DCB;
 960         }
 961
 962         return 0;
 963
 964 err_mac_alloc:
 965         i40e_vsi_release(pf->main_vsi);
 966 err_setup_pf_switch:
 967 err_get_mac_addr:
 968 err_configure_lan_hmc:
 969         (void)i40e_shutdown_lan_hmc(hw);
 970 err_init_lan_hmc:
 971         i40e_res_pool_destroy(&pf->msix_pool);
 972 err_msix_pool_init:
 973         i40e_res_pool_destroy(&pf->qp_pool);
 974 err_qp_pool_init:
 975 err_parameter_init:
 976 err_get_capabilities:
 977         (void)i40e_shutdown_adminq(hw);
 978
 979         return ret;
 980 }
 981
 982 static int
 983 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 984 {
 985         struct rte_pci_device *pci_dev;
 986         struct i40e_hw *hw;
 987         struct i40e_filter_control_settings settings;
 988         int ret;
 989         uint8_t aq_fail = 0;
 990
 991         PMD_INIT_FUNC_TRACE();
 992
 993         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 994                 return 0;
 995
 996         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997         pci_dev = dev->pci_dev;
 998
 999         if (hw->adapter_stopped == 0)
1000                 i40e_dev_close(dev);
1001
1002         dev->dev_ops = NULL;
1003         dev->rx_pkt_burst = NULL;
1004         dev->tx_pkt_burst = NULL;
1005
1006         /* Disable LLDP */
1007         ret = i40e_aq_stop_lldp(hw, true, NULL);
1008         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1009                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1010
1011         /* Clear PXE mode */
1012         i40e_clear_pxe_mode(hw);
1013
1014         /* Unconfigure filter control */
1015         memset(&settings, 0, sizeof(settings));
1016         ret = i40e_set_filter_control(hw, &settings);
1017         if (ret)
1018                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1019                                         ret);
1020
1021         /* Disable flow control */
1022         hw->fc.requested_mode = I40E_FC_NONE;
1023         i40e_set_fc(hw, &aq_fail, TRUE);
1024
1025         /* uninitialize pf host driver */
1026         i40e_pf_host_uninit(dev);
1027
1028         rte_free(dev->data->mac_addrs);
1029         dev->data->mac_addrs = NULL;
1030
1031         /* disable uio intr before callback unregister */
1032         rte_intr_disable(&(pci_dev->intr_handle));
1033
1034         /* register callback func to eal lib */
1035         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1036                 i40e_dev_interrupt_handler, (void *)dev);
1037
1038         return 0;
1039 }
1040
1041 static int
1042 i40e_dev_configure(struct rte_eth_dev *dev)
1043 {
1044         struct i40e_adapter *ad =
1045                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1046         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1048         int i, ret;
1049
1050         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1051          * bulk allocation or vector Rx preconditions we will reset it.
1052          */
1053         ad->rx_bulk_alloc_allowed = true;
1054         ad->rx_vec_allowed = true;
1055         ad->tx_simple_allowed = true;
1056         ad->tx_vec_allowed = true;
1057
1058         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1059                 ret = i40e_fdir_setup(pf);
1060                 if (ret != I40E_SUCCESS) {
1061                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1062                         return -ENOTSUP;
1063                 }
1064                 ret = i40e_fdir_configure(dev);
1065                 if (ret < 0) {
1066                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1067                         goto err;
1068                 }
1069         } else
1070                 i40e_fdir_teardown(pf);
1071
1072         ret = i40e_dev_init_vlan(dev);
1073         if (ret < 0)
1074                 goto err;
1075
1076         /* VMDQ setup.
1077          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1078          *  RSS setting have different requirements.
1079          *  General PMD driver call sequence are NIC init, configure,
1080          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1081          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1082          *  applicable. So, VMDQ setting has to be done before
1083          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1084          *  For RSS setting, it will try to calculate actual configured RX queue
1085          *  number, which will be available after rx_queue_setup(). dev_start()
1086          *  function is good to place RSS setup.
1087          */
1088         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1089                 ret = i40e_vmdq_setup(dev);
1090                 if (ret)
1091                         goto err;
1092         }
1093
1094         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1095                 ret = i40e_dcb_setup(dev);
1096                 if (ret) {
1097                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1098                         goto err_dcb;
1099                 }
1100         }
1101
1102         return 0;
1103
1104 err_dcb:
1105         /* need to release vmdq resource if exists */
1106         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1107                 i40e_vsi_release(pf->vmdq[i].vsi);
1108                 pf->vmdq[i].vsi = NULL;
1109         }
1110         rte_free(pf->vmdq);
1111         pf->vmdq = NULL;
1112 err:
1113         /* need to release fdir resource if exists */
1114         i40e_fdir_teardown(pf);
1115         return ret;
1116 }
1117
1118 void
1119 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1120 {
1121         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1122         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1123         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1124         uint16_t msix_vect = vsi->msix_intr;
1125         uint16_t i;
1126
1127         for (i = 0; i < vsi->nb_qps; i++) {
1128                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1129                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1130                 rte_wmb();
1131         }
1132
1133         if (vsi->type != I40E_VSI_SRIOV) {
1134                 if (!rte_intr_allow_others(intr_handle)) {
1135                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1136                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1137                         I40E_WRITE_REG(hw,
1138                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1139                                        0);
1140                 } else {
1141                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1142                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1143                         I40E_WRITE_REG(hw,
1144                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1145                                                        msix_vect - 1), 0);
1146                 }
1147         } else {
1148                 uint32_t reg;
1149                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1150                         vsi->user_param + (msix_vect - 1);
1151
1152                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1153                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1154         }
1155         I40E_WRITE_FLUSH(hw);
1156 }
1157
1158 static void
1159 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1160                        int base_queue, int nb_queue)
1161 {
1162         int i;
1163         uint32_t val;
1164         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1165
1166         /* Bind all RX queues to allocated MSIX interrupt */
1167         for (i = 0; i < nb_queue; i++) {
1168                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1169                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1170                         ((base_queue + i + 1) <<
1171                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1172                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1173                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1174
1175                 if (i == nb_queue - 1)
1176                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1177                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1178         }
1179
1180         /* Write first RX queue to Link list register as the head element */
1181         if (vsi->type != I40E_VSI_SRIOV) {
1182                 uint16_t interval =
1183                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1184
1185                 if (msix_vect == I40E_MISC_VEC_ID) {
1186                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1187                                        (base_queue <<
1188                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1189                                        (0x0 <<
1190                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1191                         I40E_WRITE_REG(hw,
1192                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1193                                        interval);
1194                 } else {
1195                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1196                                        (base_queue <<
1197                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1198                                        (0x0 <<
1199                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1200                         I40E_WRITE_REG(hw,
1201                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1202                                                        msix_vect - 1),
1203                                        interval);
1204                 }
1205         } else {
1206                 uint32_t reg;
1207
1208                 if (msix_vect == I40E_MISC_VEC_ID) {
1209                         I40E_WRITE_REG(hw,
1210                                        I40E_VPINT_LNKLST0(vsi->user_param),
1211                                        (base_queue <<
1212                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1213                                        (0x0 <<
1214                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1215                 } else {
1216                         /* num_msix_vectors_vf needs to minus irq0 */
1217                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1218                                 vsi->user_param + (msix_vect - 1);
1219
1220                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1221                                        (base_queue <<
1222                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1223                                        (0x0 <<
1224                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1225                 }
1226         }
1227
1228         I40E_WRITE_FLUSH(hw);
1229 }
1230
1231 void
1232 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1233 {
1234         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1235         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1236         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1237         uint16_t msix_vect = vsi->msix_intr;
1238         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1239         uint16_t queue_idx = 0;
1240         int record = 0;
1241         uint32_t val;
1242         int i;
1243
1244         for (i = 0; i < vsi->nb_qps; i++) {
1245                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1246                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1247         }
1248
1249         /* INTENA flag is not auto-cleared for interrupt */
1250         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1251         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1252                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1253                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1254         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1255
1256         /* VF bind interrupt */
1257         if (vsi->type == I40E_VSI_SRIOV) {
1258                 __vsi_queues_bind_intr(vsi, msix_vect,
1259                                        vsi->base_queue, vsi->nb_qps);
1260                 return;
1261         }
1262
1263         /* PF & VMDq bind interrupt */
1264         if (rte_intr_dp_is_en(intr_handle)) {
1265                 if (vsi->type == I40E_VSI_MAIN) {
1266                         queue_idx = 0;
1267                         record = 1;
1268                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1269                         struct i40e_vsi *main_vsi =
1270                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1271                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1272                         record = 1;
1273                 }
1274         }
1275
1276         for (i = 0; i < vsi->nb_used_qps; i++) {
1277                 if (nb_msix <= 1) {
1278                         if (!rte_intr_allow_others(intr_handle))
1279                                 /* allow to share MISC_VEC_ID */
1280                                 msix_vect = I40E_MISC_VEC_ID;
1281
1282                         /* no enough msix_vect, map all to one */
1283                         __vsi_queues_bind_intr(vsi, msix_vect,
1284                                                vsi->base_queue + i,
1285                                                vsi->nb_used_qps - i);
1286                         for (; !!record && i < vsi->nb_used_qps; i++)
1287                                 intr_handle->intr_vec[queue_idx + i] =
1288                                         msix_vect;
1289                         break;
1290                 }
1291                 /* 1:1 queue/msix_vect mapping */
1292                 __vsi_queues_bind_intr(vsi, msix_vect,
1293                                        vsi->base_queue + i, 1);
1294                 if (!!record)
1295                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1296
1297                 msix_vect++;
1298                 nb_msix--;
1299         }
1300 }
1301
1302 static void
1303 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1304 {
1305         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1306         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1307         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1308         uint16_t interval = i40e_calc_itr_interval(\
1309                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1310         uint16_t msix_intr, i;
1311
1312         if (rte_intr_allow_others(intr_handle))
1313                 for (i = 0; i < vsi->nb_msix; i++) {
1314                         msix_intr = vsi->msix_intr + i;
1315                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1316                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1317                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1318                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1319                                 (interval <<
1320                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1321                 }
1322         else
1323                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1324                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1325                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1326                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1327                                (interval <<
1328                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1329
1330         I40E_WRITE_FLUSH(hw);
1331 }
1332
1333 static void
1334 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1335 {
1336         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1337         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1338         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1339         uint16_t msix_intr, i;
1340
1341         if (rte_intr_allow_others(intr_handle))
1342                 for (i = 0; i < vsi->nb_msix; i++) {
1343                         msix_intr = vsi->msix_intr + i;
1344                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1345                                        0);
1346                 }
1347         else
1348                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1349
1350         I40E_WRITE_FLUSH(hw);
1351 }
1352
1353 static inline uint8_t
1354 i40e_parse_link_speed(uint16_t eth_link_speed)
1355 {
1356         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1357
1358         switch (eth_link_speed) {
1359         case ETH_LINK_SPEED_40G:
1360                 link_speed = I40E_LINK_SPEED_40GB;
1361                 break;
1362         case ETH_LINK_SPEED_20G:
1363                 link_speed = I40E_LINK_SPEED_20GB;
1364                 break;
1365         case ETH_LINK_SPEED_10G:
1366                 link_speed = I40E_LINK_SPEED_10GB;
1367                 break;
1368         case ETH_LINK_SPEED_1000:
1369                 link_speed = I40E_LINK_SPEED_1GB;
1370                 break;
1371         case ETH_LINK_SPEED_100:
1372                 link_speed = I40E_LINK_SPEED_100MB;
1373                 break;
1374         }
1375
1376         return link_speed;
1377 }
1378
1379 static int
1380 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1381                    __rte_unused uint8_t abilities,
1382                    __rte_unused uint8_t force_speed)
1383 {
1384         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1385          * for the link control limitation of that all link control should be
1386          * handled by firmware. It should follow up if link control will be
1387          * opened to software driver in future firmware versions.
1388          */
1389         return I40E_SUCCESS;
1390 }
1391
1392 static int
1393 i40e_apply_link_speed(struct rte_eth_dev *dev)
1394 {
1395         uint8_t speed;
1396         uint8_t abilities = 0;
1397         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398         struct rte_eth_conf *conf = &dev->data->dev_conf;
1399
1400         speed = i40e_parse_link_speed(conf->link_speed);
1401         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1402         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1403                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1404         else
1405                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1406
1407         return i40e_phy_conf_link(hw, abilities, speed);
1408 }
1409
1410 static int
1411 i40e_dev_start(struct rte_eth_dev *dev)
1412 {
1413         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1414         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415         struct i40e_vsi *main_vsi = pf->main_vsi;
1416         int ret, i;
1417         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1418         uint32_t intr_vector = 0;
1419
1420         hw->adapter_stopped = 0;
1421
1422         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1423                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1424                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1425                              dev->data->dev_conf.link_duplex,
1426                              dev->data->port_id);
1427                 return -EINVAL;
1428         }
1429
1430         rte_intr_disable(intr_handle);
1431
1432         if ((rte_intr_cap_multiple(intr_handle) ||
1433              !RTE_ETH_DEV_SRIOV(dev).active) &&
1434             dev->data->dev_conf.intr_conf.rxq != 0) {
1435                 intr_vector = dev->data->nb_rx_queues;
1436                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1437                         return -1;
1438         }
1439
1440         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1441                 intr_handle->intr_vec =
1442                         rte_zmalloc("intr_vec",
1443                                     dev->data->nb_rx_queues * sizeof(int),
1444                                     0);
1445                 if (!intr_handle->intr_vec) {
1446                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1447                                      " intr_vec\n", dev->data->nb_rx_queues);
1448                         return -ENOMEM;
1449                 }
1450         }
1451
1452         /* Initialize VSI */
1453         ret = i40e_dev_rxtx_init(pf);
1454         if (ret != I40E_SUCCESS) {
1455                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1456                 goto err_up;
1457         }
1458
1459         /* Map queues with MSIX interrupt */
1460         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1461                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1462         i40e_vsi_queues_bind_intr(main_vsi);
1463         i40e_vsi_enable_queues_intr(main_vsi);
1464
1465         /* Map VMDQ VSI queues with MSIX interrupt */
1466         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1467                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1468                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1469                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1470         }
1471
1472         /* enable FDIR MSIX interrupt */
1473         if (pf->fdir.fdir_vsi) {
1474                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1475                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1476         }
1477
1478         /* Enable all queues which have been configured */
1479         ret = i40e_dev_switch_queues(pf, TRUE);
1480         if (ret != I40E_SUCCESS) {
1481                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1482                 goto err_up;
1483         }
1484
1485         /* Enable receiving broadcast packets */
1486         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1487         if (ret != I40E_SUCCESS)
1488                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1489
1490         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1491                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1492                                                 true, NULL);
1493                 if (ret != I40E_SUCCESS)
1494                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1495         }
1496
1497         /* Apply link configure */
1498         ret = i40e_apply_link_speed(dev);
1499         if (I40E_SUCCESS != ret) {
1500                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1501                 goto err_up;
1502         }
1503
1504         if (!rte_intr_allow_others(intr_handle)) {
1505                 rte_intr_callback_unregister(intr_handle,
1506                                              i40e_dev_interrupt_handler,
1507                                              (void *)dev);
1508                 /* configure and enable device interrupt */
1509                 i40e_pf_config_irq0(hw, FALSE);
1510                 i40e_pf_enable_irq0(hw);
1511
1512                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1513                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1514                                      " no intr multiplex\n");
1515         }
1516
1517         /* enable uio intr after callback register */
1518         rte_intr_enable(intr_handle);
1519
1520         return I40E_SUCCESS;
1521
1522 err_up:
1523         i40e_dev_switch_queues(pf, FALSE);
1524         i40e_dev_clear_queues(dev);
1525
1526         return ret;
1527 }
1528
1529 static void
1530 i40e_dev_stop(struct rte_eth_dev *dev)
1531 {
1532         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1533         struct i40e_vsi *main_vsi = pf->main_vsi;
1534         struct i40e_mirror_rule *p_mirror;
1535         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1536         int i;
1537
1538         /* Disable all queues */
1539         i40e_dev_switch_queues(pf, FALSE);
1540
1541         /* un-map queues with interrupt registers */
1542         i40e_vsi_disable_queues_intr(main_vsi);
1543         i40e_vsi_queues_unbind_intr(main_vsi);
1544
1545         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1546                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1547                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1548         }
1549
1550         if (pf->fdir.fdir_vsi) {
1551                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1552                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1553         }
1554         /* Clear all queues and release memory */
1555         i40e_dev_clear_queues(dev);
1556
1557         /* Set link down */
1558         i40e_dev_set_link_down(dev);
1559
1560         /* Remove all mirror rules */
1561         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1562                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1563                 rte_free(p_mirror);
1564         }
1565         pf->nb_mirror_rule = 0;
1566
1567         if (!rte_intr_allow_others(intr_handle))
1568                 /* resume to the default handler */
1569                 rte_intr_callback_register(intr_handle,
1570                                            i40e_dev_interrupt_handler,
1571                                            (void *)dev);
1572
1573         /* Clean datapath event and queue/vec mapping */
1574         rte_intr_efd_disable(intr_handle);
1575         if (intr_handle->intr_vec) {
1576                 rte_free(intr_handle->intr_vec);
1577                 intr_handle->intr_vec = NULL;
1578         }
1579 }
1580
1581 static void
1582 i40e_dev_close(struct rte_eth_dev *dev)
1583 {
1584         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586         uint32_t reg;
1587         int i;
1588
1589         PMD_INIT_FUNC_TRACE();
1590
1591         i40e_dev_stop(dev);
1592         hw->adapter_stopped = 1;
1593         i40e_dev_free_queues(dev);
1594
1595         /* Disable interrupt */
1596         i40e_pf_disable_irq0(hw);
1597         rte_intr_disable(&(dev->pci_dev->intr_handle));
1598
1599         /* shutdown and destroy the HMC */
1600         i40e_shutdown_lan_hmc(hw);
1601
1602         /* release all the existing VSIs and VEBs */
1603         i40e_fdir_teardown(pf);
1604         i40e_vsi_release(pf->main_vsi);
1605
1606         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1607                 i40e_vsi_release(pf->vmdq[i].vsi);
1608                 pf->vmdq[i].vsi = NULL;
1609         }
1610
1611         rte_free(pf->vmdq);
1612         pf->vmdq = NULL;
1613
1614         /* shutdown the adminq */
1615         i40e_aq_queue_shutdown(hw, true);
1616         i40e_shutdown_adminq(hw);
1617
1618         i40e_res_pool_destroy(&pf->qp_pool);
1619         i40e_res_pool_destroy(&pf->msix_pool);
1620
1621         /* force a PF reset to clean anything leftover */
1622         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1623         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1624                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1625         I40E_WRITE_FLUSH(hw);
1626 }
1627
1628 static void
1629 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1630 {
1631         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         struct i40e_vsi *vsi = pf->main_vsi;
1634         int status;
1635
1636         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1637                                                         true, NULL);
1638         if (status != I40E_SUCCESS)
1639                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1640
1641         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1642                                                         TRUE, NULL);
1643         if (status != I40E_SUCCESS)
1644                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1645
1646 }
1647
1648 static void
1649 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1650 {
1651         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         struct i40e_vsi *vsi = pf->main_vsi;
1654         int status;
1655
1656         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1657                                                         false, NULL);
1658         if (status != I40E_SUCCESS)
1659                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1660
1661         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1662                                                         false, NULL);
1663         if (status != I40E_SUCCESS)
1664                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1665 }
1666
1667 static void
1668 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1669 {
1670         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1672         struct i40e_vsi *vsi = pf->main_vsi;
1673         int ret;
1674
1675         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1676         if (ret != I40E_SUCCESS)
1677                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1678 }
1679
1680 static void
1681 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1682 {
1683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         struct i40e_vsi *vsi = pf->main_vsi;
1686         int ret;
1687
1688         if (dev->data->promiscuous == 1)
1689                 return; /* must remain in all_multicast mode */
1690
1691         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1692                                 vsi->seid, FALSE, NULL);
1693         if (ret != I40E_SUCCESS)
1694                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1695 }
1696
1697 /*
1698  * Set device link up.
1699  */
1700 static int
1701 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1702 {
1703         /* re-apply link speed setting */
1704         return i40e_apply_link_speed(dev);
1705 }
1706
1707 /*
1708  * Set device link down.
1709  */
1710 static int
1711 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1712 {
1713         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1714         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716
1717         return i40e_phy_conf_link(hw, abilities, speed);
1718 }
1719
1720 int
1721 i40e_dev_link_update(struct rte_eth_dev *dev,
1722                      int wait_to_complete)
1723 {
1724 #define CHECK_INTERVAL 100  /* 100ms */
1725 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1726         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727         struct i40e_link_status link_status;
1728         struct rte_eth_link link, old;
1729         int status;
1730         unsigned rep_cnt = MAX_REPEAT_TIME;
1731
1732         memset(&link, 0, sizeof(link));
1733         memset(&old, 0, sizeof(old));
1734         memset(&link_status, 0, sizeof(link_status));
1735         rte_i40e_dev_atomic_read_link_status(dev, &old);
1736
1737         do {
1738                 /* Get link status information from hardware */
1739                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1740                 if (status != I40E_SUCCESS) {
1741                         link.link_speed = ETH_LINK_SPEED_100;
1742                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1743                         PMD_DRV_LOG(ERR, "Failed to get link info");
1744                         goto out;
1745                 }
1746
1747                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1748                 if (!wait_to_complete)
1749                         break;
1750
1751                 rte_delay_ms(CHECK_INTERVAL);
1752         } while (!link.link_status && rep_cnt--);
1753
1754         if (!link.link_status)
1755                 goto out;
1756
1757         /* i40e uses full duplex only */
1758         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1759
1760         /* Parse the link status */
1761         switch (link_status.link_speed) {
1762         case I40E_LINK_SPEED_100MB:
1763                 link.link_speed = ETH_LINK_SPEED_100;
1764                 break;
1765         case I40E_LINK_SPEED_1GB:
1766                 link.link_speed = ETH_LINK_SPEED_1000;
1767                 break;
1768         case I40E_LINK_SPEED_10GB:
1769                 link.link_speed = ETH_LINK_SPEED_10G;
1770                 break;
1771         case I40E_LINK_SPEED_20GB:
1772                 link.link_speed = ETH_LINK_SPEED_20G;
1773                 break;
1774         case I40E_LINK_SPEED_40GB:
1775                 link.link_speed = ETH_LINK_SPEED_40G;
1776                 break;
1777         default:
1778                 link.link_speed = ETH_LINK_SPEED_100;
1779                 break;
1780         }
1781
1782 out:
1783         rte_i40e_dev_atomic_write_link_status(dev, &link);
1784         if (link.link_status == old.link_status)
1785                 return -1;
1786
1787         return 0;
1788 }
1789
1790 /* Get all the statistics of a VSI */
1791 void
1792 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1793 {
1794         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1795         struct i40e_eth_stats *nes = &vsi->eth_stats;
1796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1797         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1798
1799         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1800                             vsi->offset_loaded, &oes->rx_bytes,
1801                             &nes->rx_bytes);
1802         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1803                             vsi->offset_loaded, &oes->rx_unicast,
1804                             &nes->rx_unicast);
1805         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1806                             vsi->offset_loaded, &oes->rx_multicast,
1807                             &nes->rx_multicast);
1808         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1809                             vsi->offset_loaded, &oes->rx_broadcast,
1810                             &nes->rx_broadcast);
1811         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1812                             &oes->rx_discards, &nes->rx_discards);
1813         /* GLV_REPC not supported */
1814         /* GLV_RMPC not supported */
1815         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1816                             &oes->rx_unknown_protocol,
1817                             &nes->rx_unknown_protocol);
1818         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1819                             vsi->offset_loaded, &oes->tx_bytes,
1820                             &nes->tx_bytes);
1821         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1822                             vsi->offset_loaded, &oes->tx_unicast,
1823                             &nes->tx_unicast);
1824         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1825                             vsi->offset_loaded, &oes->tx_multicast,
1826                             &nes->tx_multicast);
1827         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1828                             vsi->offset_loaded,  &oes->tx_broadcast,
1829                             &nes->tx_broadcast);
1830         /* GLV_TDPC not supported */
1831         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1832                             &oes->tx_errors, &nes->tx_errors);
1833         vsi->offset_loaded = true;
1834
1835         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1836                     vsi->vsi_id);
1837         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1838         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1839         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1840         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1841         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1842         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1843                     nes->rx_unknown_protocol);
1844         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1845         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1846         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1847         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1848         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1849         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1850         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1851                     vsi->vsi_id);
1852 }
1853
1854 static void
1855 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1856 {
1857         unsigned int i;
1858         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1859         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1860
1861         /* Get statistics of struct i40e_eth_stats */
1862         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1863                             I40E_GLPRT_GORCL(hw->port),
1864                             pf->offset_loaded, &os->eth.rx_bytes,
1865                             &ns->eth.rx_bytes);
1866         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1867                             I40E_GLPRT_UPRCL(hw->port),
1868                             pf->offset_loaded, &os->eth.rx_unicast,
1869                             &ns->eth.rx_unicast);
1870         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1871                             I40E_GLPRT_MPRCL(hw->port),
1872                             pf->offset_loaded, &os->eth.rx_multicast,
1873                             &ns->eth.rx_multicast);
1874         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1875                             I40E_GLPRT_BPRCL(hw->port),
1876                             pf->offset_loaded, &os->eth.rx_broadcast,
1877                             &ns->eth.rx_broadcast);
1878         /* Workaround: CRC size should not be included in byte statistics,
1879          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1880          */
1881         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1882                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1883
1884         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1885                             pf->offset_loaded, &os->eth.rx_discards,
1886                             &ns->eth.rx_discards);
1887         /* GLPRT_REPC not supported */
1888         /* GLPRT_RMPC not supported */
1889         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1890                             pf->offset_loaded,
1891                             &os->eth.rx_unknown_protocol,
1892                             &ns->eth.rx_unknown_protocol);
1893         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1894                             I40E_GLPRT_GOTCL(hw->port),
1895                             pf->offset_loaded, &os->eth.tx_bytes,
1896                             &ns->eth.tx_bytes);
1897         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1898                             I40E_GLPRT_UPTCL(hw->port),
1899                             pf->offset_loaded, &os->eth.tx_unicast,
1900                             &ns->eth.tx_unicast);
1901         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1902                             I40E_GLPRT_MPTCL(hw->port),
1903                             pf->offset_loaded, &os->eth.tx_multicast,
1904                             &ns->eth.tx_multicast);
1905         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1906                             I40E_GLPRT_BPTCL(hw->port),
1907                             pf->offset_loaded, &os->eth.tx_broadcast,
1908                             &ns->eth.tx_broadcast);
1909         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1910                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1911         /* GLPRT_TEPC not supported */
1912
1913         /* additional port specific stats */
1914         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1915                             pf->offset_loaded, &os->tx_dropped_link_down,
1916                             &ns->tx_dropped_link_down);
1917         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1918                             pf->offset_loaded, &os->crc_errors,
1919                             &ns->crc_errors);
1920         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1921                             pf->offset_loaded, &os->illegal_bytes,
1922                             &ns->illegal_bytes);
1923         /* GLPRT_ERRBC not supported */
1924         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1925                             pf->offset_loaded, &os->mac_local_faults,
1926                             &ns->mac_local_faults);
1927         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1928                             pf->offset_loaded, &os->mac_remote_faults,
1929                             &ns->mac_remote_faults);
1930         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1931                             pf->offset_loaded, &os->rx_length_errors,
1932                             &ns->rx_length_errors);
1933         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1934                             pf->offset_loaded, &os->link_xon_rx,
1935                             &ns->link_xon_rx);
1936         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1937                             pf->offset_loaded, &os->link_xoff_rx,
1938                             &ns->link_xoff_rx);
1939         for (i = 0; i < 8; i++) {
1940                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1941                                     pf->offset_loaded,
1942                                     &os->priority_xon_rx[i],
1943                                     &ns->priority_xon_rx[i]);
1944                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1945                                     pf->offset_loaded,
1946                                     &os->priority_xoff_rx[i],
1947                                     &ns->priority_xoff_rx[i]);
1948         }
1949         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1950                             pf->offset_loaded, &os->link_xon_tx,
1951                             &ns->link_xon_tx);
1952         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1953                             pf->offset_loaded, &os->link_xoff_tx,
1954                             &ns->link_xoff_tx);
1955         for (i = 0; i < 8; i++) {
1956                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1957                                     pf->offset_loaded,
1958                                     &os->priority_xon_tx[i],
1959                                     &ns->priority_xon_tx[i]);
1960                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1961                                     pf->offset_loaded,
1962                                     &os->priority_xoff_tx[i],
1963                                     &ns->priority_xoff_tx[i]);
1964                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1965                                     pf->offset_loaded,
1966                                     &os->priority_xon_2_xoff[i],
1967                                     &ns->priority_xon_2_xoff[i]);
1968         }
1969         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1970                             I40E_GLPRT_PRC64L(hw->port),
1971                             pf->offset_loaded, &os->rx_size_64,
1972                             &ns->rx_size_64);
1973         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1974                             I40E_GLPRT_PRC127L(hw->port),
1975                             pf->offset_loaded, &os->rx_size_127,
1976                             &ns->rx_size_127);
1977         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1978                             I40E_GLPRT_PRC255L(hw->port),
1979                             pf->offset_loaded, &os->rx_size_255,
1980                             &ns->rx_size_255);
1981         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1982                             I40E_GLPRT_PRC511L(hw->port),
1983                             pf->offset_loaded, &os->rx_size_511,
1984                             &ns->rx_size_511);
1985         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1986                             I40E_GLPRT_PRC1023L(hw->port),
1987                             pf->offset_loaded, &os->rx_size_1023,
1988                             &ns->rx_size_1023);
1989         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1990                             I40E_GLPRT_PRC1522L(hw->port),
1991                             pf->offset_loaded, &os->rx_size_1522,
1992                             &ns->rx_size_1522);
1993         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1994                             I40E_GLPRT_PRC9522L(hw->port),
1995                             pf->offset_loaded, &os->rx_size_big,
1996                             &ns->rx_size_big);
1997         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1998                             pf->offset_loaded, &os->rx_undersize,
1999                             &ns->rx_undersize);
2000         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2001                             pf->offset_loaded, &os->rx_fragments,
2002                             &ns->rx_fragments);
2003         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2004                             pf->offset_loaded, &os->rx_oversize,
2005                             &ns->rx_oversize);
2006         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2007                             pf->offset_loaded, &os->rx_jabber,
2008                             &ns->rx_jabber);
2009         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2010                             I40E_GLPRT_PTC64L(hw->port),
2011                             pf->offset_loaded, &os->tx_size_64,
2012                             &ns->tx_size_64);
2013         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2014                             I40E_GLPRT_PTC127L(hw->port),
2015                             pf->offset_loaded, &os->tx_size_127,
2016                             &ns->tx_size_127);
2017         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2018                             I40E_GLPRT_PTC255L(hw->port),
2019                             pf->offset_loaded, &os->tx_size_255,
2020                             &ns->tx_size_255);
2021         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2022                             I40E_GLPRT_PTC511L(hw->port),
2023                             pf->offset_loaded, &os->tx_size_511,
2024                             &ns->tx_size_511);
2025         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2026                             I40E_GLPRT_PTC1023L(hw->port),
2027                             pf->offset_loaded, &os->tx_size_1023,
2028                             &ns->tx_size_1023);
2029         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2030                             I40E_GLPRT_PTC1522L(hw->port),
2031                             pf->offset_loaded, &os->tx_size_1522,
2032                             &ns->tx_size_1522);
2033         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2034                             I40E_GLPRT_PTC9522L(hw->port),
2035                             pf->offset_loaded, &os->tx_size_big,
2036                             &ns->tx_size_big);
2037         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2038                            pf->offset_loaded,
2039                            &os->fd_sb_match, &ns->fd_sb_match);
2040         /* GLPRT_MSPDC not supported */
2041         /* GLPRT_XEC not supported */
2042
2043         pf->offset_loaded = true;
2044
2045         if (pf->main_vsi)
2046                 i40e_update_vsi_stats(pf->main_vsi);
2047 }
2048
2049 /* Get all statistics of a port */
2050 static void
2051 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2052 {
2053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2056         unsigned i;
2057
2058         /* call read registers - updates values, now write them to struct */
2059         i40e_read_stats_registers(pf, hw);
2060
2061         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2062                         pf->main_vsi->eth_stats.rx_multicast +
2063                         pf->main_vsi->eth_stats.rx_broadcast -
2064                         pf->main_vsi->eth_stats.rx_discards;
2065         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2066                         pf->main_vsi->eth_stats.tx_multicast +
2067                         pf->main_vsi->eth_stats.tx_broadcast;
2068         stats->ibytes   = ns->eth.rx_bytes;
2069         stats->obytes   = ns->eth.tx_bytes;
2070         stats->oerrors  = ns->eth.tx_errors +
2071                         pf->main_vsi->eth_stats.tx_errors;
2072         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2073
2074         /* Rx Errors */
2075         stats->imissed  = ns->eth.rx_discards +
2076                         pf->main_vsi->eth_stats.rx_discards;
2077         stats->ierrors  = ns->crc_errors +
2078                         ns->rx_length_errors + ns->rx_undersize +
2079                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2080                         stats->imissed;
2081
2082         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2083         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2084         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2085         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2086         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2087         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2088         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2089                     ns->eth.rx_unknown_protocol);
2090         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2091         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2092         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2093         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2094         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2095         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2096
2097         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2098                     ns->tx_dropped_link_down);
2099         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2100         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2101                     ns->illegal_bytes);
2102         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2103         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2104                     ns->mac_local_faults);
2105         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2106                     ns->mac_remote_faults);
2107         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2108                     ns->rx_length_errors);
2109         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2110         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2111         for (i = 0; i < 8; i++) {
2112                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2113                                 i, ns->priority_xon_rx[i]);
2114                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2115                                 i, ns->priority_xoff_rx[i]);
2116         }
2117         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2118         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2119         for (i = 0; i < 8; i++) {
2120                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2121                                 i, ns->priority_xon_tx[i]);
2122                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2123                                 i, ns->priority_xoff_tx[i]);
2124                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2125                                 i, ns->priority_xon_2_xoff[i]);
2126         }
2127         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2128         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2129         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2130         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2131         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2132         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2133         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2134         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2135         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2136         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2137         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2138         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2139         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2140         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2141         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2142         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2143         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2144         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2145         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2146                         ns->mac_short_packet_dropped);
2147         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2148                     ns->checksum_error);
2149         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2150         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2151 }
2152
2153 /* Reset the statistics */
2154 static void
2155 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2156 {
2157         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159
2160         /* Mark PF and VSI stats to update the offset, aka "reset" */
2161         pf->offset_loaded = false;
2162         if (pf->main_vsi)
2163                 pf->main_vsi->offset_loaded = false;
2164
2165         /* read the stats, reading current register values into offset */
2166         i40e_read_stats_registers(pf, hw);
2167 }
2168
2169 static uint32_t
2170 i40e_xstats_calc_num(void)
2171 {
2172         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2173                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2174                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2175 }
2176
2177 static int
2178 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2179                     unsigned n)
2180 {
2181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183         unsigned i, count, prio;
2184         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2185
2186         count = i40e_xstats_calc_num();
2187         if (n < count)
2188                 return count;
2189
2190         i40e_read_stats_registers(pf, hw);
2191
2192         if (xstats == NULL)
2193                 return 0;
2194
2195         count = 0;
2196
2197         /* Get stats from i40e_eth_stats struct */
2198         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2199                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2200                          "%s", rte_i40e_stats_strings[i].name);
2201                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2202                         rte_i40e_stats_strings[i].offset);
2203                 count++;
2204         }
2205
2206         /* Get individiual stats from i40e_hw_port struct */
2207         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2208                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2209                          "%s", rte_i40e_hw_port_strings[i].name);
2210                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2211                                 rte_i40e_hw_port_strings[i].offset);
2212                 count++;
2213         }
2214
2215         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2216                 for (prio = 0; prio < 8; prio++) {
2217                         snprintf(xstats[count].name,
2218                                  sizeof(xstats[count].name),
2219                                  "rx_priority%u_%s", prio,
2220                                  rte_i40e_rxq_prio_strings[i].name);
2221                         xstats[count].value =
2222                                 *(uint64_t *)(((char *)hw_stats) +
2223                                 rte_i40e_rxq_prio_strings[i].offset +
2224                                 (sizeof(uint64_t) * prio));
2225                         count++;
2226                 }
2227         }
2228
2229         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2230                 for (prio = 0; prio < 8; prio++) {
2231                         snprintf(xstats[count].name,
2232                                  sizeof(xstats[count].name),
2233                                  "tx_priority%u_%s", prio,
2234                                  rte_i40e_txq_prio_strings[i].name);
2235                         xstats[count].value =
2236                                 *(uint64_t *)(((char *)hw_stats) +
2237                                 rte_i40e_txq_prio_strings[i].offset +
2238                                 (sizeof(uint64_t) * prio));
2239                         count++;
2240                 }
2241         }
2242
2243         return count;
2244 }
2245
2246 static int
2247 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2248                                  __rte_unused uint16_t queue_id,
2249                                  __rte_unused uint8_t stat_idx,
2250                                  __rte_unused uint8_t is_rx)
2251 {
2252         PMD_INIT_FUNC_TRACE();
2253
2254         return -ENOSYS;
2255 }
2256
2257 static void
2258 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2259 {
2260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2261         struct i40e_vsi *vsi = pf->main_vsi;
2262
2263         dev_info->max_rx_queues = vsi->nb_qps;
2264         dev_info->max_tx_queues = vsi->nb_qps;
2265         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2266         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2267         dev_info->max_mac_addrs = vsi->max_macaddrs;
2268         dev_info->max_vfs = dev->pci_dev->max_vfs;
2269         dev_info->rx_offload_capa =
2270                 DEV_RX_OFFLOAD_VLAN_STRIP |
2271                 DEV_RX_OFFLOAD_QINQ_STRIP |
2272                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2273                 DEV_RX_OFFLOAD_UDP_CKSUM |
2274                 DEV_RX_OFFLOAD_TCP_CKSUM;
2275         dev_info->tx_offload_capa =
2276                 DEV_TX_OFFLOAD_VLAN_INSERT |
2277                 DEV_TX_OFFLOAD_QINQ_INSERT |
2278                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2279                 DEV_TX_OFFLOAD_UDP_CKSUM |
2280                 DEV_TX_OFFLOAD_TCP_CKSUM |
2281                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2282                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2283                 DEV_TX_OFFLOAD_TCP_TSO;
2284         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2285                                                 sizeof(uint32_t);
2286         dev_info->reta_size = pf->hash_lut_size;
2287         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2288
2289         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2290                 .rx_thresh = {
2291                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2292                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2293                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2294                 },
2295                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2296                 .rx_drop_en = 0,
2297         };
2298
2299         dev_info->default_txconf = (struct rte_eth_txconf) {
2300                 .tx_thresh = {
2301                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2302                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2303                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2304                 },
2305                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2306                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2307                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2308                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2309         };
2310
2311         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2312                 .nb_max = I40E_MAX_RING_DESC,
2313                 .nb_min = I40E_MIN_RING_DESC,
2314                 .nb_align = I40E_ALIGN_RING_DESC,
2315         };
2316
2317         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2318                 .nb_max = I40E_MAX_RING_DESC,
2319                 .nb_min = I40E_MIN_RING_DESC,
2320                 .nb_align = I40E_ALIGN_RING_DESC,
2321         };
2322
2323         if (pf->flags & I40E_FLAG_VMDQ) {
2324                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2325                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2326                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2327                                                 pf->max_nb_vmdq_vsi;
2328                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2329                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2330                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2331         }
2332 }
2333
2334 static int
2335 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2336 {
2337         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2338         struct i40e_vsi *vsi = pf->main_vsi;
2339         PMD_INIT_FUNC_TRACE();
2340
2341         if (on)
2342                 return i40e_vsi_add_vlan(vsi, vlan_id);
2343         else
2344                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2345 }
2346
2347 static int
2348 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2349                    enum rte_vlan_type vlan_type,
2350                    uint16_t tpid)
2351 {
2352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353         uint64_t reg_r = 0, reg_w = 0;
2354         uint16_t reg_id = 0;
2355         int ret = 0;
2356
2357         switch (vlan_type) {
2358         case ETH_VLAN_TYPE_OUTER:
2359                 reg_id = 2;
2360                 break;
2361         case ETH_VLAN_TYPE_INNER:
2362                 reg_id = 3;
2363                 break;
2364         default:
2365                 ret = -EINVAL;
2366                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2367                 return ret;
2368         }
2369         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2370                                           &reg_r, NULL);
2371         if (ret != I40E_SUCCESS) {
2372                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2373                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2374                 ret = -EIO;
2375                 return ret;
2376         }
2377         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2378                     "0x%08"PRIx64"", reg_id, reg_r);
2379
2380         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2381         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2382         if (reg_r == reg_w) {
2383                 ret = 0;
2384                 PMD_DRV_LOG(DEBUG, "No need to write");
2385                 return ret;
2386         }
2387
2388         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2389                                            reg_w, NULL);
2390         if (ret != I40E_SUCCESS) {
2391                 ret = -EIO;
2392                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2393                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2394                 return ret;
2395         }
2396         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2397                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2398
2399         return ret;
2400 }
2401
2402 static void
2403 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2404 {
2405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2406         struct i40e_vsi *vsi = pf->main_vsi;
2407
2408         if (mask & ETH_VLAN_FILTER_MASK) {
2409                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2410                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2411                 else
2412                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2413         }
2414
2415         if (mask & ETH_VLAN_STRIP_MASK) {
2416                 /* Enable or disable VLAN stripping */
2417                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2418                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2419                 else
2420                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2421         }
2422
2423         if (mask & ETH_VLAN_EXTEND_MASK) {
2424                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2425                         i40e_vsi_config_double_vlan(vsi, TRUE);
2426                 else
2427                         i40e_vsi_config_double_vlan(vsi, FALSE);
2428         }
2429 }
2430
2431 static void
2432 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2433                           __rte_unused uint16_t queue,
2434                           __rte_unused int on)
2435 {
2436         PMD_INIT_FUNC_TRACE();
2437 }
2438
2439 static int
2440 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2441 {
2442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2443         struct i40e_vsi *vsi = pf->main_vsi;
2444         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2445         struct i40e_vsi_vlan_pvid_info info;
2446
2447         memset(&info, 0, sizeof(info));
2448         info.on = on;
2449         if (info.on)
2450                 info.config.pvid = pvid;
2451         else {
2452                 info.config.reject.tagged =
2453                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2454                 info.config.reject.untagged =
2455                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2456         }
2457
2458         return i40e_vsi_vlan_pvid_set(vsi, &info);
2459 }
2460
2461 static int
2462 i40e_dev_led_on(struct rte_eth_dev *dev)
2463 {
2464         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465         uint32_t mode = i40e_led_get(hw);
2466
2467         if (mode == 0)
2468                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2469
2470         return 0;
2471 }
2472
2473 static int
2474 i40e_dev_led_off(struct rte_eth_dev *dev)
2475 {
2476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477         uint32_t mode = i40e_led_get(hw);
2478
2479         if (mode != 0)
2480                 i40e_led_set(hw, 0, false);
2481
2482         return 0;
2483 }
2484
2485 static int
2486 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2487 {
2488         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2490
2491         fc_conf->pause_time = pf->fc_conf.pause_time;
2492         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2493         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2494
2495          /* Return current mode according to actual setting*/
2496         switch (hw->fc.current_mode) {
2497         case I40E_FC_FULL:
2498                 fc_conf->mode = RTE_FC_FULL;
2499                 break;
2500         case I40E_FC_TX_PAUSE:
2501                 fc_conf->mode = RTE_FC_TX_PAUSE;
2502                 break;
2503         case I40E_FC_RX_PAUSE:
2504                 fc_conf->mode = RTE_FC_RX_PAUSE;
2505                 break;
2506         case I40E_FC_NONE:
2507         default:
2508                 fc_conf->mode = RTE_FC_NONE;
2509         };
2510
2511         return 0;
2512 }
2513
2514 static int
2515 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2516 {
2517         uint32_t mflcn_reg, fctrl_reg, reg;
2518         uint32_t max_high_water;
2519         uint8_t i, aq_failure;
2520         int err;
2521         struct i40e_hw *hw;
2522         struct i40e_pf *pf;
2523         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2524                 [RTE_FC_NONE] = I40E_FC_NONE,
2525                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2526                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2527                 [RTE_FC_FULL] = I40E_FC_FULL
2528         };
2529
2530         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2531
2532         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2533         if ((fc_conf->high_water > max_high_water) ||
2534                         (fc_conf->high_water < fc_conf->low_water)) {
2535                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2536                         "High_water must <= %d.", max_high_water);
2537                 return -EINVAL;
2538         }
2539
2540         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2542         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2543
2544         pf->fc_conf.pause_time = fc_conf->pause_time;
2545         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2546         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2547
2548         PMD_INIT_FUNC_TRACE();
2549
2550         /* All the link flow control related enable/disable register
2551          * configuration is handle by the F/W
2552          */
2553         err = i40e_set_fc(hw, &aq_failure, true);
2554         if (err < 0)
2555                 return -ENOSYS;
2556
2557         if (i40e_is_40G_device(hw->device_id)) {
2558                 /* Configure flow control refresh threshold,
2559                  * the value for stat_tx_pause_refresh_timer[8]
2560                  * is used for global pause operation.
2561                  */
2562
2563                 I40E_WRITE_REG(hw,
2564                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2565                                pf->fc_conf.pause_time);
2566
2567                 /* configure the timer value included in transmitted pause
2568                  * frame,
2569                  * the value for stat_tx_pause_quanta[8] is used for global
2570                  * pause operation
2571                  */
2572                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2573                                pf->fc_conf.pause_time);
2574
2575                 fctrl_reg = I40E_READ_REG(hw,
2576                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2577
2578                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2579                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2580                 else
2581                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2582
2583                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2584                                fctrl_reg);
2585         } else {
2586                 /* Configure pause time (2 TCs per register) */
2587                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2588                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2589                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2590
2591                 /* Configure flow control refresh threshold value */
2592                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2593                                pf->fc_conf.pause_time / 2);
2594
2595                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2596
2597                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2598                  *depending on configuration
2599                  */
2600                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2601                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2602                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2603                 } else {
2604                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2605                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2606                 }
2607
2608                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2609         }
2610
2611         /* config the water marker both based on the packets and bytes */
2612         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2613                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2614                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2615         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2616                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2617                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2618         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2619                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2620                        << I40E_KILOSHIFT);
2621         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2622                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2623                        << I40E_KILOSHIFT);
2624
2625         I40E_WRITE_FLUSH(hw);
2626
2627         return 0;
2628 }
2629
2630 static int
2631 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2632                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2633 {
2634         PMD_INIT_FUNC_TRACE();
2635
2636         return -ENOSYS;
2637 }
2638
2639 /* Add a MAC address, and update filters */
2640 static void
2641 i40e_macaddr_add(struct rte_eth_dev *dev,
2642                  struct ether_addr *mac_addr,
2643                  __rte_unused uint32_t index,
2644                  uint32_t pool)
2645 {
2646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2647         struct i40e_mac_filter_info mac_filter;
2648         struct i40e_vsi *vsi;
2649         int ret;
2650
2651         /* If VMDQ not enabled or configured, return */
2652         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2653                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2654                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2655                         pool);
2656                 return;
2657         }
2658
2659         if (pool > pf->nb_cfg_vmdq_vsi) {
2660                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2661                                 pool, pf->nb_cfg_vmdq_vsi);
2662                 return;
2663         }
2664
2665         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2666         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2667                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2668         else
2669                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2670
2671         if (pool == 0)
2672                 vsi = pf->main_vsi;
2673         else
2674                 vsi = pf->vmdq[pool - 1].vsi;
2675
2676         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2677         if (ret != I40E_SUCCESS) {
2678                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2679                 return;
2680         }
2681 }
2682
2683 /* Remove a MAC address, and update filters */
2684 static void
2685 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2686 {
2687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688         struct i40e_vsi *vsi;
2689         struct rte_eth_dev_data *data = dev->data;
2690         struct ether_addr *macaddr;
2691         int ret;
2692         uint32_t i;
2693         uint64_t pool_sel;
2694
2695         macaddr = &(data->mac_addrs[index]);
2696
2697         pool_sel = dev->data->mac_pool_sel[index];
2698
2699         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2700                 if (pool_sel & (1ULL << i)) {
2701                         if (i == 0)
2702                                 vsi = pf->main_vsi;
2703                         else {
2704                                 /* No VMDQ pool enabled or configured */
2705                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2706                                         (i > pf->nb_cfg_vmdq_vsi)) {
2707                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2708                                                         "/configured");
2709                                         return;
2710                                 }
2711                                 vsi = pf->vmdq[i - 1].vsi;
2712                         }
2713                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2714
2715                         if (ret) {
2716                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2717                                 return;
2718                         }
2719                 }
2720         }
2721 }
2722
2723 /* Set perfect match or hash match of MAC and VLAN for a VF */
2724 static int
2725 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2726                  struct rte_eth_mac_filter *filter,
2727                  bool add)
2728 {
2729         struct i40e_hw *hw;
2730         struct i40e_mac_filter_info mac_filter;
2731         struct ether_addr old_mac;
2732         struct ether_addr *new_mac;
2733         struct i40e_pf_vf *vf = NULL;
2734         uint16_t vf_id;
2735         int ret;
2736
2737         if (pf == NULL) {
2738                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2739                 return -EINVAL;
2740         }
2741         hw = I40E_PF_TO_HW(pf);
2742
2743         if (filter == NULL) {
2744                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2745                 return -EINVAL;
2746         }
2747
2748         new_mac = &filter->mac_addr;
2749
2750         if (is_zero_ether_addr(new_mac)) {
2751                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2752                 return -EINVAL;
2753         }
2754
2755         vf_id = filter->dst_id;
2756
2757         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2758                 PMD_DRV_LOG(ERR, "Invalid argument.");
2759                 return -EINVAL;
2760         }
2761         vf = &pf->vfs[vf_id];
2762
2763         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2764                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2765                 return -EINVAL;
2766         }
2767
2768         if (add) {
2769                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2770                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2771                                 ETHER_ADDR_LEN);
2772                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2773                                  ETHER_ADDR_LEN);
2774
2775                 mac_filter.filter_type = filter->filter_type;
2776                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2777                 if (ret != I40E_SUCCESS) {
2778                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2779                         return -1;
2780                 }
2781                 ether_addr_copy(new_mac, &pf->dev_addr);
2782         } else {
2783                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2784                                 ETHER_ADDR_LEN);
2785                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2786                 if (ret != I40E_SUCCESS) {
2787                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2788                         return -1;
2789                 }
2790
2791                 /* Clear device address as it has been removed */
2792                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2793                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2794         }
2795
2796         return 0;
2797 }
2798
2799 /* MAC filter handle */
2800 static int
2801 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2802                 void *arg)
2803 {
2804         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2805         struct rte_eth_mac_filter *filter;
2806         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2807         int ret = I40E_NOT_SUPPORTED;
2808
2809         filter = (struct rte_eth_mac_filter *)(arg);
2810
2811         switch (filter_op) {
2812         case RTE_ETH_FILTER_NOP:
2813                 ret = I40E_SUCCESS;
2814                 break;
2815         case RTE_ETH_FILTER_ADD:
2816                 i40e_pf_disable_irq0(hw);
2817                 if (filter->is_vf)
2818                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2819                 i40e_pf_enable_irq0(hw);
2820                 break;
2821         case RTE_ETH_FILTER_DELETE:
2822                 i40e_pf_disable_irq0(hw);
2823                 if (filter->is_vf)
2824                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2825                 i40e_pf_enable_irq0(hw);
2826                 break;
2827         default:
2828                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2829                 ret = I40E_ERR_PARAM;
2830                 break;
2831         }
2832
2833         return ret;
2834 }
2835
2836 static int
2837 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2838 {
2839         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2840         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2841         int ret;
2842
2843         if (!lut)
2844                 return -EINVAL;
2845
2846         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2847                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2848                                           lut, lut_size);
2849                 if (ret) {
2850                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2851                         return ret;
2852                 }
2853         } else {
2854                 uint32_t *lut_dw = (uint32_t *)lut;
2855                 uint16_t i, lut_size_dw = lut_size / 4;
2856
2857                 for (i = 0; i < lut_size_dw; i++)
2858                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2859         }
2860
2861         return 0;
2862 }
2863
2864 static int
2865 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2866 {
2867         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2868         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2869         int ret;
2870
2871         if (!vsi || !lut)
2872                 return -EINVAL;
2873
2874         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2875                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2876                                           lut, lut_size);
2877                 if (ret) {
2878                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2879                         return ret;
2880                 }
2881         } else {
2882                 uint32_t *lut_dw = (uint32_t *)lut;
2883                 uint16_t i, lut_size_dw = lut_size / 4;
2884
2885                 for (i = 0; i < lut_size_dw; i++)
2886                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2887                 I40E_WRITE_FLUSH(hw);
2888         }
2889
2890         return 0;
2891 }
2892
2893 static int
2894 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2895                          struct rte_eth_rss_reta_entry64 *reta_conf,
2896                          uint16_t reta_size)
2897 {
2898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2899         uint16_t i, lut_size = pf->hash_lut_size;
2900         uint16_t idx, shift;
2901         uint8_t *lut;
2902         int ret;
2903
2904         if (reta_size != lut_size ||
2905                 reta_size > ETH_RSS_RETA_SIZE_512) {
2906                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2907                         "(%d) doesn't match the number hardware can supported "
2908                                         "(%d)\n", reta_size, lut_size);
2909                 return -EINVAL;
2910         }
2911
2912         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2913         if (!lut) {
2914                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2915                 return -ENOMEM;
2916         }
2917         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2918         if (ret)
2919                 goto out;
2920         for (i = 0; i < reta_size; i++) {
2921                 idx = i / RTE_RETA_GROUP_SIZE;
2922                 shift = i % RTE_RETA_GROUP_SIZE;
2923                 if (reta_conf[idx].mask & (1ULL << shift))
2924                         lut[i] = reta_conf[idx].reta[shift];
2925         }
2926         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2927
2928 out:
2929         rte_free(lut);
2930
2931         return ret;
2932 }
2933
2934 static int
2935 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2936                         struct rte_eth_rss_reta_entry64 *reta_conf,
2937                         uint16_t reta_size)
2938 {
2939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2940         uint16_t i, lut_size = pf->hash_lut_size;
2941         uint16_t idx, shift;
2942         uint8_t *lut;
2943         int ret;
2944
2945         if (reta_size != lut_size ||
2946                 reta_size > ETH_RSS_RETA_SIZE_512) {
2947                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2948                         "(%d) doesn't match the number hardware can supported "
2949                                         "(%d)\n", reta_size, lut_size);
2950                 return -EINVAL;
2951         }
2952
2953         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2954         if (!lut) {
2955                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2956                 return -ENOMEM;
2957         }
2958
2959         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2960         if (ret)
2961                 goto out;
2962         for (i = 0; i < reta_size; i++) {
2963                 idx = i / RTE_RETA_GROUP_SIZE;
2964                 shift = i % RTE_RETA_GROUP_SIZE;
2965                 if (reta_conf[idx].mask & (1ULL << shift))
2966                         reta_conf[idx].reta[shift] = lut[i];
2967         }
2968
2969 out:
2970         rte_free(lut);
2971
2972         return ret;
2973 }
2974
2975 /**
2976  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2977  * @hw:   pointer to the HW structure
2978  * @mem:  pointer to mem struct to fill out
2979  * @size: size of memory requested
2980  * @alignment: what to align the allocation to
2981  **/
2982 enum i40e_status_code
2983 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2984                         struct i40e_dma_mem *mem,
2985                         u64 size,
2986                         u32 alignment)
2987 {
2988         const struct rte_memzone *mz = NULL;
2989         char z_name[RTE_MEMZONE_NAMESIZE];
2990
2991         if (!mem)
2992                 return I40E_ERR_PARAM;
2993
2994         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2995         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2996                                          alignment, RTE_PGSIZE_2M);
2997         if (!mz)
2998                 return I40E_ERR_NO_MEMORY;
2999
3000         mem->size = size;
3001         mem->va = mz->addr;
3002         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3003         mem->zone = (const void *)mz;
3004         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3005                     "%"PRIu64, mz->name, mem->pa);
3006
3007         return I40E_SUCCESS;
3008 }
3009
3010 /**
3011  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3012  * @hw:   pointer to the HW structure
3013  * @mem:  ptr to mem struct to free
3014  **/
3015 enum i40e_status_code
3016 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3017                     struct i40e_dma_mem *mem)
3018 {
3019         if (!mem)
3020                 return I40E_ERR_PARAM;
3021
3022         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3023                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3024                     mem->pa);
3025         rte_memzone_free((const struct rte_memzone *)mem->zone);
3026         mem->zone = NULL;
3027         mem->va = NULL;
3028         mem->pa = (u64)0;
3029
3030         return I40E_SUCCESS;
3031 }
3032
3033 /**
3034  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3035  * @hw:   pointer to the HW structure
3036  * @mem:  pointer to mem struct to fill out
3037  * @size: size of memory requested
3038  **/
3039 enum i40e_status_code
3040 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3041                          struct i40e_virt_mem *mem,
3042                          u32 size)
3043 {
3044         if (!mem)
3045                 return I40E_ERR_PARAM;
3046
3047         mem->size = size;
3048         mem->va = rte_zmalloc("i40e", size, 0);
3049
3050         if (mem->va)
3051                 return I40E_SUCCESS;
3052         else
3053                 return I40E_ERR_NO_MEMORY;
3054 }
3055
3056 /**
3057  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3058  * @hw:   pointer to the HW structure
3059  * @mem:  pointer to mem struct to free
3060  **/
3061 enum i40e_status_code
3062 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3063                      struct i40e_virt_mem *mem)
3064 {
3065         if (!mem)
3066                 return I40E_ERR_PARAM;
3067
3068         rte_free(mem->va);
3069         mem->va = NULL;
3070
3071         return I40E_SUCCESS;
3072 }
3073
3074 void
3075 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3076 {
3077         rte_spinlock_init(&sp->spinlock);
3078 }
3079
3080 void
3081 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3082 {
3083         rte_spinlock_lock(&sp->spinlock);
3084 }
3085
3086 void
3087 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3088 {
3089         rte_spinlock_unlock(&sp->spinlock);
3090 }
3091
3092 void
3093 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3094 {
3095         return;
3096 }
3097
3098 /**
3099  * Get the hardware capabilities, which will be parsed
3100  * and saved into struct i40e_hw.
3101  */
3102 static int
3103 i40e_get_cap(struct i40e_hw *hw)
3104 {
3105         struct i40e_aqc_list_capabilities_element_resp *buf;
3106         uint16_t len, size = 0;
3107         int ret;
3108
3109         /* Calculate a huge enough buff for saving response data temporarily */
3110         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3111                                                 I40E_MAX_CAP_ELE_NUM;
3112         buf = rte_zmalloc("i40e", len, 0);
3113         if (!buf) {
3114                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3115                 return I40E_ERR_NO_MEMORY;
3116         }
3117
3118         /* Get, parse the capabilities and save it to hw */
3119         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3120                         i40e_aqc_opc_list_func_capabilities, NULL);
3121         if (ret != I40E_SUCCESS)
3122                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3123
3124         /* Free the temporary buffer after being used */
3125         rte_free(buf);
3126
3127         return ret;
3128 }
3129
3130 static int
3131 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3132 {
3133         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3134         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3135         uint16_t qp_count = 0, vsi_count = 0;
3136
3137         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3138                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3139                 return -EINVAL;
3140         }
3141         /* Add the parameter init for LFC */
3142         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3143         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3144         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3145
3146         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3147         pf->max_num_vsi = hw->func_caps.num_vsis;
3148         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3149         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3150         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3151
3152         /* FDir queue/VSI allocation */
3153         pf->fdir_qp_offset = 0;
3154         if (hw->func_caps.fd) {
3155                 pf->flags |= I40E_FLAG_FDIR;
3156                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3157         } else {
3158                 pf->fdir_nb_qps = 0;
3159         }
3160         qp_count += pf->fdir_nb_qps;
3161         vsi_count += 1;
3162
3163         /* LAN queue/VSI allocation */
3164         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3165         if (!hw->func_caps.rss) {
3166                 pf->lan_nb_qps = 1;
3167         } else {
3168                 pf->flags |= I40E_FLAG_RSS;
3169                 if (hw->mac.type == I40E_MAC_X722)
3170                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3171                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3172         }
3173         qp_count += pf->lan_nb_qps;
3174         vsi_count += 1;
3175
3176         /* VF queue/VSI allocation */
3177         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3178         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3179                 pf->flags |= I40E_FLAG_SRIOV;
3180                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3181                 pf->vf_num = dev->pci_dev->max_vfs;
3182                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3183                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3184                             pf->vf_nb_qps * pf->vf_num);
3185         } else {
3186                 pf->vf_nb_qps = 0;
3187                 pf->vf_num = 0;
3188         }
3189         qp_count += pf->vf_nb_qps * pf->vf_num;
3190         vsi_count += pf->vf_num;
3191
3192         /* VMDq queue/VSI allocation */
3193         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3194         pf->vmdq_nb_qps = 0;
3195         pf->max_nb_vmdq_vsi = 0;
3196         if (hw->func_caps.vmdq) {
3197                 if (qp_count < hw->func_caps.num_tx_qp &&
3198                         vsi_count < hw->func_caps.num_vsis) {
3199                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3200                                 qp_count) / pf->vmdq_nb_qp_max;
3201
3202                         /* Limit the maximum number of VMDq vsi to the maximum
3203                          * ethdev can support
3204                          */
3205                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3206                                 hw->func_caps.num_vsis - vsi_count);
3207                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3208                                 ETH_64_POOLS);
3209                         if (pf->max_nb_vmdq_vsi) {
3210                                 pf->flags |= I40E_FLAG_VMDQ;
3211                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3212                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3213                                             "per VMDQ VSI, in total %u queues",
3214                                             pf->max_nb_vmdq_vsi,
3215                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3216                                             pf->max_nb_vmdq_vsi);
3217                         } else {
3218                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3219                                             "VMDq");
3220                         }
3221                 } else {
3222                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3223                 }
3224         }
3225         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3226         vsi_count += pf->max_nb_vmdq_vsi;
3227
3228         if (hw->func_caps.dcb)
3229                 pf->flags |= I40E_FLAG_DCB;
3230
3231         if (qp_count > hw->func_caps.num_tx_qp) {
3232                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3233                             "the hardware maximum %u", qp_count,
3234                             hw->func_caps.num_tx_qp);
3235                 return -EINVAL;
3236         }
3237         if (vsi_count > hw->func_caps.num_vsis) {
3238                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3239                             "the hardware maximum %u", vsi_count,
3240                             hw->func_caps.num_vsis);
3241                 return -EINVAL;
3242         }
3243
3244         return 0;
3245 }
3246
3247 static int
3248 i40e_pf_get_switch_config(struct i40e_pf *pf)
3249 {
3250         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3251         struct i40e_aqc_get_switch_config_resp *switch_config;
3252         struct i40e_aqc_switch_config_element_resp *element;
3253         uint16_t start_seid = 0, num_reported;
3254         int ret;
3255
3256         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3257                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3258         if (!switch_config) {
3259                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3260                 return -ENOMEM;
3261         }
3262
3263         /* Get the switch configurations */
3264         ret = i40e_aq_get_switch_config(hw, switch_config,
3265                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3266         if (ret != I40E_SUCCESS) {
3267                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3268                 goto fail;
3269         }
3270         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3271         if (num_reported != 1) { /* The number should be 1 */
3272                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3273                 goto fail;
3274         }
3275
3276         /* Parse the switch configuration elements */
3277         element = &(switch_config->element[0]);
3278         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3279                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3280                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3281         } else
3282                 PMD_DRV_LOG(INFO, "Unknown element type");
3283
3284 fail:
3285         rte_free(switch_config);
3286
3287         return ret;
3288 }
3289
3290 static int
3291 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3292                         uint32_t num)
3293 {
3294         struct pool_entry *entry;
3295
3296         if (pool == NULL || num == 0)
3297                 return -EINVAL;
3298
3299         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3300         if (entry == NULL) {
3301                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3302                 return -ENOMEM;
3303         }
3304
3305         /* queue heap initialize */
3306         pool->num_free = num;
3307         pool->num_alloc = 0;
3308         pool->base = base;
3309         LIST_INIT(&pool->alloc_list);
3310         LIST_INIT(&pool->free_list);
3311
3312         /* Initialize element  */
3313         entry->base = 0;
3314         entry->len = num;
3315
3316         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3317         return 0;
3318 }
3319
3320 static void
3321 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3322 {
3323         struct pool_entry *entry;
3324
3325         if (pool == NULL)
3326                 return;
3327
3328         LIST_FOREACH(entry, &pool->alloc_list, next) {
3329                 LIST_REMOVE(entry, next);
3330                 rte_free(entry);
3331         }
3332
3333         LIST_FOREACH(entry, &pool->free_list, next) {
3334                 LIST_REMOVE(entry, next);
3335                 rte_free(entry);
3336         }
3337
3338         pool->num_free = 0;
3339         pool->num_alloc = 0;
3340         pool->base = 0;
3341         LIST_INIT(&pool->alloc_list);
3342         LIST_INIT(&pool->free_list);
3343 }
3344
3345 static int
3346 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3347                        uint32_t base)
3348 {
3349         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3350         uint32_t pool_offset;
3351         int insert;
3352
3353         if (pool == NULL) {
3354                 PMD_DRV_LOG(ERR, "Invalid parameter");
3355                 return -EINVAL;
3356         }
3357
3358         pool_offset = base - pool->base;
3359         /* Lookup in alloc list */
3360         LIST_FOREACH(entry, &pool->alloc_list, next) {
3361                 if (entry->base == pool_offset) {
3362                         valid_entry = entry;
3363                         LIST_REMOVE(entry, next);
3364                         break;
3365                 }
3366         }
3367
3368         /* Not find, return */
3369         if (valid_entry == NULL) {
3370                 PMD_DRV_LOG(ERR, "Failed to find entry");
3371                 return -EINVAL;
3372         }
3373
3374         /**
3375          * Found it, move it to free list  and try to merge.
3376          * In order to make merge easier, always sort it by qbase.
3377          * Find adjacent prev and last entries.
3378          */
3379         prev = next = NULL;
3380         LIST_FOREACH(entry, &pool->free_list, next) {
3381                 if (entry->base > valid_entry->base) {
3382                         next = entry;
3383                         break;
3384                 }
3385                 prev = entry;
3386         }
3387
3388         insert = 0;
3389         /* Try to merge with next one*/
3390         if (next != NULL) {
3391                 /* Merge with next one */
3392                 if (valid_entry->base + valid_entry->len == next->base) {
3393                         next->base = valid_entry->base;
3394                         next->len += valid_entry->len;
3395                         rte_free(valid_entry);
3396                         valid_entry = next;
3397                         insert = 1;
3398                 }
3399         }
3400
3401         if (prev != NULL) {
3402                 /* Merge with previous one */
3403                 if (prev->base + prev->len == valid_entry->base) {
3404                         prev->len += valid_entry->len;
3405                         /* If it merge with next one, remove next node */
3406                         if (insert == 1) {
3407                                 LIST_REMOVE(valid_entry, next);
3408                                 rte_free(valid_entry);
3409                         } else {
3410                                 rte_free(valid_entry);
3411                                 insert = 1;
3412                         }
3413                 }
3414         }
3415
3416         /* Not find any entry to merge, insert */
3417         if (insert == 0) {
3418                 if (prev != NULL)
3419                         LIST_INSERT_AFTER(prev, valid_entry, next);
3420                 else if (next != NULL)
3421                         LIST_INSERT_BEFORE(next, valid_entry, next);
3422                 else /* It's empty list, insert to head */
3423                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3424         }
3425
3426         pool->num_free += valid_entry->len;
3427         pool->num_alloc -= valid_entry->len;
3428
3429         return 0;
3430 }
3431
3432 static int
3433 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3434                        uint16_t num)
3435 {
3436         struct pool_entry *entry, *valid_entry;
3437
3438         if (pool == NULL || num == 0) {
3439                 PMD_DRV_LOG(ERR, "Invalid parameter");
3440                 return -EINVAL;
3441         }
3442
3443         if (pool->num_free < num) {
3444                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3445                             num, pool->num_free);
3446                 return -ENOMEM;
3447         }
3448
3449         valid_entry = NULL;
3450         /* Lookup  in free list and find most fit one */
3451         LIST_FOREACH(entry, &pool->free_list, next) {
3452                 if (entry->len >= num) {
3453                         /* Find best one */
3454                         if (entry->len == num) {
3455                                 valid_entry = entry;
3456                                 break;
3457                         }
3458                         if (valid_entry == NULL || valid_entry->len > entry->len)
3459                                 valid_entry = entry;
3460                 }
3461         }
3462
3463         /* Not find one to satisfy the request, return */
3464         if (valid_entry == NULL) {
3465                 PMD_DRV_LOG(ERR, "No valid entry found");
3466                 return -ENOMEM;
3467         }
3468         /**
3469          * The entry have equal queue number as requested,
3470          * remove it from alloc_list.
3471          */
3472         if (valid_entry->len == num) {
3473                 LIST_REMOVE(valid_entry, next);
3474         } else {
3475                 /**
3476                  * The entry have more numbers than requested,
3477                  * create a new entry for alloc_list and minus its
3478                  * queue base and number in free_list.
3479                  */
3480                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3481                 if (entry == NULL) {
3482                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3483                                     "resource pool");
3484                         return -ENOMEM;
3485                 }
3486                 entry->base = valid_entry->base;
3487                 entry->len = num;
3488                 valid_entry->base += num;
3489                 valid_entry->len -= num;
3490                 valid_entry = entry;
3491         }
3492
3493         /* Insert it into alloc list, not sorted */
3494         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3495
3496         pool->num_free -= valid_entry->len;
3497         pool->num_alloc += valid_entry->len;
3498
3499         return valid_entry->base + pool->base;
3500 }
3501
3502 /**
3503  * bitmap_is_subset - Check whether src2 is subset of src1
3504  **/
3505 static inline int
3506 bitmap_is_subset(uint8_t src1, uint8_t src2)
3507 {
3508         return !((src1 ^ src2) & src2);
3509 }
3510
3511 static enum i40e_status_code
3512 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3513 {
3514         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3515
3516         /* If DCB is not supported, only default TC is supported */
3517         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3518                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3519                 return I40E_NOT_SUPPORTED;
3520         }
3521
3522         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3523                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3524                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3525                             enabled_tcmap);
3526                 return I40E_NOT_SUPPORTED;
3527         }
3528         return I40E_SUCCESS;
3529 }
3530
3531 int
3532 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3533                                 struct i40e_vsi_vlan_pvid_info *info)
3534 {
3535         struct i40e_hw *hw;
3536         struct i40e_vsi_context ctxt;
3537         uint8_t vlan_flags = 0;
3538         int ret;
3539
3540         if (vsi == NULL || info == NULL) {
3541                 PMD_DRV_LOG(ERR, "invalid parameters");
3542                 return I40E_ERR_PARAM;
3543         }
3544
3545         if (info->on) {
3546                 vsi->info.pvid = info->config.pvid;
3547                 /**
3548                  * If insert pvid is enabled, only tagged pkts are
3549                  * allowed to be sent out.
3550                  */
3551                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3552                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3553         } else {
3554                 vsi->info.pvid = 0;
3555                 if (info->config.reject.tagged == 0)
3556                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3557
3558                 if (info->config.reject.untagged == 0)
3559                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3560         }
3561         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3562                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3563         vsi->info.port_vlan_flags |= vlan_flags;
3564         vsi->info.valid_sections =
3565                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3566         memset(&ctxt, 0, sizeof(ctxt));
3567         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3568         ctxt.seid = vsi->seid;
3569
3570         hw = I40E_VSI_TO_HW(vsi);
3571         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3572         if (ret != I40E_SUCCESS)
3573                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3574
3575         return ret;
3576 }
3577
3578 static int
3579 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3580 {
3581         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3582         int i, ret;
3583         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3584
3585         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3586         if (ret != I40E_SUCCESS)
3587                 return ret;
3588
3589         if (!vsi->seid) {
3590                 PMD_DRV_LOG(ERR, "seid not valid");
3591                 return -EINVAL;
3592         }
3593
3594         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3595         tc_bw_data.tc_valid_bits = enabled_tcmap;
3596         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3597                 tc_bw_data.tc_bw_credits[i] =
3598                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3599
3600         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3601         if (ret != I40E_SUCCESS) {
3602                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3603                 return ret;
3604         }
3605
3606         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3607                                         sizeof(vsi->info.qs_handle));
3608         return I40E_SUCCESS;
3609 }
3610
3611 static enum i40e_status_code
3612 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3613                                  struct i40e_aqc_vsi_properties_data *info,
3614                                  uint8_t enabled_tcmap)
3615 {
3616         enum i40e_status_code ret;
3617         int i, total_tc = 0;
3618         uint16_t qpnum_per_tc, bsf, qp_idx;
3619
3620         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3621         if (ret != I40E_SUCCESS)
3622                 return ret;
3623
3624         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3625                 if (enabled_tcmap & (1 << i))
3626                         total_tc++;
3627         vsi->enabled_tc = enabled_tcmap;
3628
3629         /* Number of queues per enabled TC */
3630         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3631         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3632         bsf = rte_bsf32(qpnum_per_tc);
3633
3634         /* Adjust the queue number to actual queues that can be applied */
3635         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3636                 vsi->nb_qps = qpnum_per_tc * total_tc;
3637
3638         /**
3639          * Configure TC and queue mapping parameters, for enabled TC,
3640          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3641          * default queue will serve it.
3642          */
3643         qp_idx = 0;
3644         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3645                 if (vsi->enabled_tc & (1 << i)) {
3646                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3647                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3648                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3649                         qp_idx += qpnum_per_tc;
3650                 } else
3651                         info->tc_mapping[i] = 0;
3652         }
3653
3654         /* Associate queue number with VSI */
3655         if (vsi->type == I40E_VSI_SRIOV) {
3656                 info->mapping_flags |=
3657                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3658                 for (i = 0; i < vsi->nb_qps; i++)
3659                         info->queue_mapping[i] =
3660                                 rte_cpu_to_le_16(vsi->base_queue + i);
3661         } else {
3662                 info->mapping_flags |=
3663                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3664                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3665         }
3666         info->valid_sections |=
3667                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3668
3669         return I40E_SUCCESS;
3670 }
3671
3672 static int
3673 i40e_veb_release(struct i40e_veb *veb)
3674 {
3675         struct i40e_vsi *vsi;
3676         struct i40e_hw *hw;
3677
3678         if (veb == NULL || veb->associate_vsi == NULL)
3679                 return -EINVAL;
3680
3681         if (!TAILQ_EMPTY(&veb->head)) {
3682                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3683                 return -EACCES;
3684         }
3685
3686         vsi = veb->associate_vsi;
3687         hw = I40E_VSI_TO_HW(vsi);
3688
3689         vsi->uplink_seid = veb->uplink_seid;
3690         i40e_aq_delete_element(hw, veb->seid, NULL);
3691         rte_free(veb);
3692         vsi->veb = NULL;
3693         return I40E_SUCCESS;
3694 }
3695
3696 /* Setup a veb */
3697 static struct i40e_veb *
3698 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3699 {
3700         struct i40e_veb *veb;
3701         int ret;
3702         struct i40e_hw *hw;
3703
3704         if (NULL == pf || vsi == NULL) {
3705                 PMD_DRV_LOG(ERR, "veb setup failed, "
3706                             "associated VSI shouldn't null");
3707                 return NULL;
3708         }
3709         hw = I40E_PF_TO_HW(pf);
3710
3711         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3712         if (!veb) {
3713                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3714                 goto fail;
3715         }
3716
3717         veb->associate_vsi = vsi;
3718         TAILQ_INIT(&veb->head);
3719         veb->uplink_seid = vsi->uplink_seid;
3720
3721         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3722                 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3723
3724         if (ret != I40E_SUCCESS) {
3725                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3726                             hw->aq.asq_last_status);
3727                 goto fail;
3728         }
3729
3730         /* get statistics index */
3731         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3732                                 &veb->stats_idx, NULL, NULL, NULL);
3733         if (ret != I40E_SUCCESS) {
3734                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3735                             hw->aq.asq_last_status);
3736                 goto fail;
3737         }
3738
3739         /* Get VEB bandwidth, to be implemented */
3740         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3741         vsi->uplink_seid = veb->seid;
3742
3743         return veb;
3744 fail:
3745         rte_free(veb);
3746         return NULL;
3747 }
3748
3749 int
3750 i40e_vsi_release(struct i40e_vsi *vsi)
3751 {
3752         struct i40e_pf *pf;
3753         struct i40e_hw *hw;
3754         struct i40e_vsi_list *vsi_list;
3755         int ret;
3756         struct i40e_mac_filter *f;
3757
3758         if (!vsi)
3759                 return I40E_SUCCESS;
3760
3761         pf = I40E_VSI_TO_PF(vsi);
3762         hw = I40E_VSI_TO_HW(vsi);
3763
3764         /* VSI has child to attach, release child first */
3765         if (vsi->veb) {
3766                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3767                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3768                                 return -1;
3769                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3770                 }
3771                 i40e_veb_release(vsi->veb);
3772         }
3773
3774         /* Remove all macvlan filters of the VSI */
3775         i40e_vsi_remove_all_macvlan_filter(vsi);
3776         TAILQ_FOREACH(f, &vsi->mac_list, next)
3777                 rte_free(f);
3778
3779         if (vsi->type != I40E_VSI_MAIN) {
3780                 /* Remove vsi from parent's sibling list */
3781                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3782                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3783                         return I40E_ERR_PARAM;
3784                 }
3785                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3786                                 &vsi->sib_vsi_list, list);
3787
3788                 /* Remove all switch element of the VSI */
3789                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3790                 if (ret != I40E_SUCCESS)
3791                         PMD_DRV_LOG(ERR, "Failed to delete element");
3792         }
3793         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3794
3795         if (vsi->type != I40E_VSI_SRIOV)
3796                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3797         rte_free(vsi);
3798
3799         return I40E_SUCCESS;
3800 }
3801
3802 static int
3803 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3804 {
3805         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3806         struct i40e_aqc_remove_macvlan_element_data def_filter;
3807         struct i40e_mac_filter_info filter;
3808         int ret;
3809
3810         if (vsi->type != I40E_VSI_MAIN)
3811                 return I40E_ERR_CONFIG;
3812         memset(&def_filter, 0, sizeof(def_filter));
3813         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3814                                         ETH_ADDR_LEN);
3815         def_filter.vlan_tag = 0;
3816         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3817                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3818         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3819         if (ret != I40E_SUCCESS) {
3820                 struct i40e_mac_filter *f;
3821                 struct ether_addr *mac;
3822
3823                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3824                             "macvlan filter");
3825                 /* It needs to add the permanent mac into mac list */
3826                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3827                 if (f == NULL) {
3828                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3829                         return I40E_ERR_NO_MEMORY;
3830                 }
3831                 mac = &f->mac_info.mac_addr;
3832                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3833                                 ETH_ADDR_LEN);
3834                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3835                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3836                 vsi->mac_num++;
3837
3838                 return ret;
3839         }
3840         (void)rte_memcpy(&filter.mac_addr,
3841                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3842         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3843         return i40e_vsi_add_mac(vsi, &filter);
3844 }
3845
3846 /*
3847  * i40e_vsi_get_bw_config - Query VSI BW Information
3848  * @vsi: the VSI to be queried
3849  *
3850  * Returns 0 on success, negative value on failure
3851  */
3852 static enum i40e_status_code
3853 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3854 {
3855         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3856         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3857         struct i40e_hw *hw = &vsi->adapter->hw;
3858         i40e_status ret;
3859         int i;
3860         uint32_t bw_max;
3861
3862         memset(&bw_config, 0, sizeof(bw_config));
3863         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3864         if (ret != I40E_SUCCESS) {
3865                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3866                             hw->aq.asq_last_status);
3867                 return ret;
3868         }
3869
3870         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3871         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3872                                         &ets_sla_config, NULL);
3873         if (ret != I40E_SUCCESS) {
3874                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3875                             "configuration %u", hw->aq.asq_last_status);
3876                 return ret;
3877         }
3878
3879         /* store and print out BW info */
3880         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3881         vsi->bw_info.bw_max = bw_config.max_bw;
3882         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3883         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3884         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3885                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3886                      I40E_16_BIT_WIDTH);
3887         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3888                 vsi->bw_info.bw_ets_share_credits[i] =
3889                                 ets_sla_config.share_credits[i];
3890                 vsi->bw_info.bw_ets_credits[i] =
3891                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3892                 /* 4 bits per TC, 4th bit is reserved */
3893                 vsi->bw_info.bw_ets_max[i] =
3894                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3895                                   RTE_LEN2MASK(3, uint8_t));
3896                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3897                             vsi->bw_info.bw_ets_share_credits[i]);
3898                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3899                             vsi->bw_info.bw_ets_credits[i]);
3900                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3901                             vsi->bw_info.bw_ets_max[i]);
3902         }
3903
3904         return I40E_SUCCESS;
3905 }
3906
3907 /* i40e_enable_pf_lb
3908  * @pf: pointer to the pf structure
3909  *
3910  * allow loopback on pf
3911  */
3912 static inline void
3913 i40e_enable_pf_lb(struct i40e_pf *pf)
3914 {
3915         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3916         struct i40e_vsi_context ctxt;
3917         int ret;
3918
3919         /* Use the FW API if FW >= v5.0 */
3920         if (hw->aq.fw_maj_ver < 5) {
3921                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3922                 return;
3923         }
3924
3925         memset(&ctxt, 0, sizeof(ctxt));
3926         ctxt.seid = pf->main_vsi_seid;
3927         ctxt.pf_num = hw->pf_id;
3928         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3929         if (ret) {
3930                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3931                             ret, hw->aq.asq_last_status);
3932                 return;
3933         }
3934         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3935         ctxt.info.valid_sections =
3936                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3937         ctxt.info.switch_id |=
3938                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3939
3940         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3941         if (ret)
3942                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3943                             hw->aq.asq_last_status);
3944 }
3945
3946 /* Setup a VSI */
3947 struct i40e_vsi *
3948 i40e_vsi_setup(struct i40e_pf *pf,
3949                enum i40e_vsi_type type,
3950                struct i40e_vsi *uplink_vsi,
3951                uint16_t user_param)
3952 {
3953         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3954         struct i40e_vsi *vsi;
3955         struct i40e_mac_filter_info filter;
3956         int ret;
3957         struct i40e_vsi_context ctxt;
3958         struct ether_addr broadcast =
3959                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3960
3961         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3962                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3963                             "VSI link shouldn't be NULL");
3964                 return NULL;
3965         }
3966
3967         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3968                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3969                             "uplink VSI should be NULL");
3970                 return NULL;
3971         }
3972
3973         /* If uplink vsi didn't setup VEB, create one first */
3974         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3975                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3976
3977                 if (NULL == uplink_vsi->veb) {
3978                         PMD_DRV_LOG(ERR, "VEB setup failed");
3979                         return NULL;
3980                 }
3981                 /* set ALLOWLOOPBACk on pf, when veb is created */
3982                 i40e_enable_pf_lb(pf);
3983         }
3984
3985         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3986         if (!vsi) {
3987                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3988                 return NULL;
3989         }
3990         TAILQ_INIT(&vsi->mac_list);
3991         vsi->type = type;
3992         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3993         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3994         vsi->parent_vsi = uplink_vsi;
3995         vsi->user_param = user_param;
3996         /* Allocate queues */
3997         switch (vsi->type) {
3998         case I40E_VSI_MAIN  :
3999                 vsi->nb_qps = pf->lan_nb_qps;
4000                 break;
4001         case I40E_VSI_SRIOV :
4002                 vsi->nb_qps = pf->vf_nb_qps;
4003                 break;
4004         case I40E_VSI_VMDQ2:
4005                 vsi->nb_qps = pf->vmdq_nb_qps;
4006                 break;
4007         case I40E_VSI_FDIR:
4008                 vsi->nb_qps = pf->fdir_nb_qps;
4009                 break;
4010         default:
4011                 goto fail_mem;
4012         }
4013         /*
4014          * The filter status descriptor is reported in rx queue 0,
4015          * while the tx queue for fdir filter programming has no
4016          * such constraints, can be non-zero queues.
4017          * To simplify it, choose FDIR vsi use queue 0 pair.
4018          * To make sure it will use queue 0 pair, queue allocation
4019          * need be done before this function is called
4020          */
4021         if (type != I40E_VSI_FDIR) {
4022                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4023                         if (ret < 0) {
4024                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4025                                                 vsi->seid, ret);
4026                                 goto fail_mem;
4027                         }
4028                         vsi->base_queue = ret;
4029         } else
4030                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4031
4032         /* VF has MSIX interrupt in VF range, don't allocate here */
4033         if (type == I40E_VSI_MAIN) {
4034                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4035                                           RTE_MIN(vsi->nb_qps,
4036                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4037                 if (ret < 0) {
4038                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4039                                     vsi->seid, ret);
4040                         goto fail_queue_alloc;
4041                 }
4042                 vsi->msix_intr = ret;
4043                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4044         } else if (type != I40E_VSI_SRIOV) {
4045                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4046                 if (ret < 0) {
4047                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4048                         goto fail_queue_alloc;
4049                 }
4050                 vsi->msix_intr = ret;
4051                 vsi->nb_msix = 1;
4052         } else {
4053                 vsi->msix_intr = 0;
4054                 vsi->nb_msix = 0;
4055         }
4056
4057         /* Add VSI */
4058         if (type == I40E_VSI_MAIN) {
4059                 /* For main VSI, no need to add since it's default one */
4060                 vsi->uplink_seid = pf->mac_seid;
4061                 vsi->seid = pf->main_vsi_seid;
4062                 /* Bind queues with specific MSIX interrupt */
4063                 /**
4064                  * Needs 2 interrupt at least, one for misc cause which will
4065                  * enabled from OS side, Another for queues binding the
4066                  * interrupt from device side only.
4067                  */
4068
4069                 /* Get default VSI parameters from hardware */
4070                 memset(&ctxt, 0, sizeof(ctxt));
4071                 ctxt.seid = vsi->seid;
4072                 ctxt.pf_num = hw->pf_id;
4073                 ctxt.uplink_seid = vsi->uplink_seid;
4074                 ctxt.vf_num = 0;
4075                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4076                 if (ret != I40E_SUCCESS) {
4077                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4078                         goto fail_msix_alloc;
4079                 }
4080                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4081                         sizeof(struct i40e_aqc_vsi_properties_data));
4082                 vsi->vsi_id = ctxt.vsi_number;
4083                 vsi->info.valid_sections = 0;
4084
4085                 /* Configure tc, enabled TC0 only */
4086                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4087                         I40E_SUCCESS) {
4088                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4089                         goto fail_msix_alloc;
4090                 }
4091
4092                 /* TC, queue mapping */
4093                 memset(&ctxt, 0, sizeof(ctxt));
4094                 vsi->info.valid_sections |=
4095                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4096                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4097                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4098                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4099                         sizeof(struct i40e_aqc_vsi_properties_data));
4100                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4101                                                 I40E_DEFAULT_TCMAP);
4102                 if (ret != I40E_SUCCESS) {
4103                         PMD_DRV_LOG(ERR, "Failed to configure "
4104                                     "TC queue mapping");
4105                         goto fail_msix_alloc;
4106                 }
4107                 ctxt.seid = vsi->seid;
4108                 ctxt.pf_num = hw->pf_id;
4109                 ctxt.uplink_seid = vsi->uplink_seid;
4110                 ctxt.vf_num = 0;
4111
4112                 /* Update VSI parameters */
4113                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4114                 if (ret != I40E_SUCCESS) {
4115                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4116                         goto fail_msix_alloc;
4117                 }
4118
4119                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4120                                                 sizeof(vsi->info.tc_mapping));
4121                 (void)rte_memcpy(&vsi->info.queue_mapping,
4122                                 &ctxt.info.queue_mapping,
4123                         sizeof(vsi->info.queue_mapping));
4124                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4125                 vsi->info.valid_sections = 0;
4126
4127                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4128                                 ETH_ADDR_LEN);
4129
4130                 /**
4131                  * Updating default filter settings are necessary to prevent
4132                  * reception of tagged packets.
4133                  * Some old firmware configurations load a default macvlan
4134                  * filter which accepts both tagged and untagged packets.
4135                  * The updating is to use a normal filter instead if needed.
4136                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4137                  * The firmware with correct configurations load the default
4138                  * macvlan filter which is expected and cannot be removed.
4139                  */
4140                 i40e_update_default_filter_setting(vsi);
4141                 i40e_config_qinq(hw, vsi);
4142         } else if (type == I40E_VSI_SRIOV) {
4143                 memset(&ctxt, 0, sizeof(ctxt));
4144                 /**
4145                  * For other VSI, the uplink_seid equals to uplink VSI's
4146                  * uplink_seid since they share same VEB
4147                  */
4148                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4149                 ctxt.pf_num = hw->pf_id;
4150                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4151                 ctxt.uplink_seid = vsi->uplink_seid;
4152                 ctxt.connection_type = 0x1;
4153                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4154
4155                 /* Use the VEB configuration if FW >= v5.0 */
4156                 if (hw->aq.fw_maj_ver >= 5) {
4157                         /* Configure switch ID */
4158                         ctxt.info.valid_sections |=
4159                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4160                         ctxt.info.switch_id =
4161                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4162                 }
4163
4164                 /* Configure port/vlan */
4165                 ctxt.info.valid_sections |=
4166                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4167                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4168                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4169                                                 I40E_DEFAULT_TCMAP);
4170                 if (ret != I40E_SUCCESS) {
4171                         PMD_DRV_LOG(ERR, "Failed to configure "
4172                                     "TC queue mapping");
4173                         goto fail_msix_alloc;
4174                 }
4175                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4176                 ctxt.info.valid_sections |=
4177                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4178                 /**
4179                  * Since VSI is not created yet, only configure parameter,
4180                  * will add vsi below.
4181                  */
4182
4183                 i40e_config_qinq(hw, vsi);
4184         } else if (type == I40E_VSI_VMDQ2) {
4185                 memset(&ctxt, 0, sizeof(ctxt));
4186                 /*
4187                  * For other VSI, the uplink_seid equals to uplink VSI's
4188                  * uplink_seid since they share same VEB
4189                  */
4190                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4191                 ctxt.pf_num = hw->pf_id;
4192                 ctxt.vf_num = 0;
4193                 ctxt.uplink_seid = vsi->uplink_seid;
4194                 ctxt.connection_type = 0x1;
4195                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4196
4197                 ctxt.info.valid_sections |=
4198                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4199                 /* user_param carries flag to enable loop back */
4200                 if (user_param) {
4201                         ctxt.info.switch_id =
4202                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4203                         ctxt.info.switch_id |=
4204                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4205                 }
4206
4207                 /* Configure port/vlan */
4208                 ctxt.info.valid_sections |=
4209                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4210                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4211                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4212                                                 I40E_DEFAULT_TCMAP);
4213                 if (ret != I40E_SUCCESS) {
4214                         PMD_DRV_LOG(ERR, "Failed to configure "
4215                                         "TC queue mapping");
4216                         goto fail_msix_alloc;
4217                 }
4218                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4219                 ctxt.info.valid_sections |=
4220                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4221         } else if (type == I40E_VSI_FDIR) {
4222                 memset(&ctxt, 0, sizeof(ctxt));
4223                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4224                 ctxt.pf_num = hw->pf_id;
4225                 ctxt.vf_num = 0;
4226                 ctxt.uplink_seid = vsi->uplink_seid;
4227                 ctxt.connection_type = 0x1;     /* regular data port */
4228                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4229                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4230                                                 I40E_DEFAULT_TCMAP);
4231                 if (ret != I40E_SUCCESS) {
4232                         PMD_DRV_LOG(ERR, "Failed to configure "
4233                                         "TC queue mapping.");
4234                         goto fail_msix_alloc;
4235                 }
4236                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4237                 ctxt.info.valid_sections |=
4238                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4239         } else {
4240                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4241                 goto fail_msix_alloc;
4242         }
4243
4244         if (vsi->type != I40E_VSI_MAIN) {
4245                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4246                 if (ret != I40E_SUCCESS) {
4247                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4248                                     hw->aq.asq_last_status);
4249                         goto fail_msix_alloc;
4250                 }
4251                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4252                 vsi->info.valid_sections = 0;
4253                 vsi->seid = ctxt.seid;
4254                 vsi->vsi_id = ctxt.vsi_number;
4255                 vsi->sib_vsi_list.vsi = vsi;
4256                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4257                                 &vsi->sib_vsi_list, list);
4258         }
4259
4260         /* MAC/VLAN configuration */
4261         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4262         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4263
4264         ret = i40e_vsi_add_mac(vsi, &filter);
4265         if (ret != I40E_SUCCESS) {
4266                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4267                 goto fail_msix_alloc;
4268         }
4269
4270         /* Get VSI BW information */
4271         i40e_vsi_get_bw_config(vsi);
4272         return vsi;
4273 fail_msix_alloc:
4274         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4275 fail_queue_alloc:
4276         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4277 fail_mem:
4278         rte_free(vsi);
4279         return NULL;
4280 }
4281
4282 /* Configure vlan filter on or off */
4283 int
4284 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4285 {
4286         int i, num;
4287         struct i40e_mac_filter *f;
4288         struct i40e_mac_filter_info *mac_filter;
4289         enum rte_mac_filter_type desired_filter;
4290         int ret = I40E_SUCCESS;
4291
4292         if (on) {
4293                 /* Filter to match MAC and VLAN */
4294                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4295         } else {
4296                 /* Filter to match only MAC */
4297                 desired_filter = RTE_MAC_PERFECT_MATCH;
4298         }
4299
4300         num = vsi->mac_num;
4301
4302         mac_filter = rte_zmalloc("mac_filter_info_data",
4303                                  num * sizeof(*mac_filter), 0);
4304         if (mac_filter == NULL) {
4305                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4306                 return I40E_ERR_NO_MEMORY;
4307         }
4308
4309         i = 0;
4310
4311         /* Remove all existing mac */
4312         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4313                 mac_filter[i] = f->mac_info;
4314                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4315                 if (ret) {
4316                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4317                                     on ? "enable" : "disable");
4318                         goto DONE;
4319                 }
4320                 i++;
4321         }
4322
4323         /* Override with new filter */
4324         for (i = 0; i < num; i++) {
4325                 mac_filter[i].filter_type = desired_filter;
4326                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4327                 if (ret) {
4328                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4329                                     on ? "enable" : "disable");
4330                         goto DONE;
4331                 }
4332         }
4333
4334 DONE:
4335         rte_free(mac_filter);
4336         return ret;
4337 }
4338
4339 /* Configure vlan stripping on or off */
4340 int
4341 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4342 {
4343         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4344         struct i40e_vsi_context ctxt;
4345         uint8_t vlan_flags;
4346         int ret = I40E_SUCCESS;
4347
4348         /* Check if it has been already on or off */
4349         if (vsi->info.valid_sections &
4350                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4351                 if (on) {
4352                         if ((vsi->info.port_vlan_flags &
4353                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4354                                 return 0; /* already on */
4355                 } else {
4356                         if ((vsi->info.port_vlan_flags &
4357                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4358                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4359                                 return 0; /* already off */
4360                 }
4361         }
4362
4363         if (on)
4364                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4365         else
4366                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4367         vsi->info.valid_sections =
4368                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4369         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4370         vsi->info.port_vlan_flags |= vlan_flags;
4371         ctxt.seid = vsi->seid;
4372         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4373         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4374         if (ret)
4375                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4376                             on ? "enable" : "disable");
4377
4378         return ret;
4379 }
4380
4381 static int
4382 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4383 {
4384         struct rte_eth_dev_data *data = dev->data;
4385         int ret;
4386         int mask = 0;
4387
4388         /* Apply vlan offload setting */
4389         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4390         i40e_vlan_offload_set(dev, mask);
4391
4392         /* Apply double-vlan setting, not implemented yet */
4393
4394         /* Apply pvid setting */
4395         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4396                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4397         if (ret)
4398                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4399
4400         return ret;
4401 }
4402
4403 static int
4404 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4405 {
4406         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4407
4408         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4409 }
4410
4411 static int
4412 i40e_update_flow_control(struct i40e_hw *hw)
4413 {
4414 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4415         struct i40e_link_status link_status;
4416         uint32_t rxfc = 0, txfc = 0, reg;
4417         uint8_t an_info;
4418         int ret;
4419
4420         memset(&link_status, 0, sizeof(link_status));
4421         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4422         if (ret != I40E_SUCCESS) {
4423                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4424                 goto write_reg; /* Disable flow control */
4425         }
4426
4427         an_info = hw->phy.link_info.an_info;
4428         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4429                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4430                 ret = I40E_ERR_NOT_READY;
4431                 goto write_reg; /* Disable flow control */
4432         }
4433         /**
4434          * If link auto negotiation is enabled, flow control needs to
4435          * be configured according to it
4436          */
4437         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4438         case I40E_LINK_PAUSE_RXTX:
4439                 rxfc = 1;
4440                 txfc = 1;
4441                 hw->fc.current_mode = I40E_FC_FULL;
4442                 break;
4443         case I40E_AQ_LINK_PAUSE_RX:
4444                 rxfc = 1;
4445                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4446                 break;
4447         case I40E_AQ_LINK_PAUSE_TX:
4448                 txfc = 1;
4449                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4450                 break;
4451         default:
4452                 hw->fc.current_mode = I40E_FC_NONE;
4453                 break;
4454         }
4455
4456 write_reg:
4457         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4458                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4459         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4460         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4461         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4462         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4463
4464         return ret;
4465 }
4466
4467 /* PF setup */
4468 static int
4469 i40e_pf_setup(struct i40e_pf *pf)
4470 {
4471         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4472         struct i40e_filter_control_settings settings;
4473         struct i40e_vsi *vsi;
4474         int ret;
4475
4476         /* Clear all stats counters */
4477         pf->offset_loaded = FALSE;
4478         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4479         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4480
4481         ret = i40e_pf_get_switch_config(pf);
4482         if (ret != I40E_SUCCESS) {
4483                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4484                 return ret;
4485         }
4486         if (pf->flags & I40E_FLAG_FDIR) {
4487                 /* make queue allocated first, let FDIR use queue pair 0*/
4488                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4489                 if (ret != I40E_FDIR_QUEUE_ID) {
4490                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4491                                     " ret =%d", ret);
4492                         pf->flags &= ~I40E_FLAG_FDIR;
4493                 }
4494         }
4495         /*  main VSI setup */
4496         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4497         if (!vsi) {
4498                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4499                 return I40E_ERR_NOT_READY;
4500         }
4501         pf->main_vsi = vsi;
4502
4503         /* Configure filter control */
4504         memset(&settings, 0, sizeof(settings));
4505         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4506                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4507         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4508                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4509         else {
4510                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4511                                                 hw->func_caps.rss_table_size);
4512                 return I40E_ERR_PARAM;
4513         }
4514         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4515                         "size: %u\n", hw->func_caps.rss_table_size);
4516         pf->hash_lut_size = hw->func_caps.rss_table_size;
4517
4518         /* Enable ethtype and macvlan filters */
4519         settings.enable_ethtype = TRUE;
4520         settings.enable_macvlan = TRUE;
4521         ret = i40e_set_filter_control(hw, &settings);
4522         if (ret)
4523                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4524                                                                 ret);
4525
4526         /* Update flow control according to the auto negotiation */
4527         i40e_update_flow_control(hw);
4528
4529         return I40E_SUCCESS;
4530 }
4531
4532 int
4533 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4534 {
4535         uint32_t reg;
4536         uint16_t j;
4537
4538         /**
4539          * Set or clear TX Queue Disable flags,
4540          * which is required by hardware.
4541          */
4542         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4543         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4544
4545         /* Wait until the request is finished */
4546         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4547                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4548                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4549                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4550                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4551                                                         & 0x1))) {
4552                         break;
4553                 }
4554         }
4555         if (on) {
4556                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4557                         return I40E_SUCCESS; /* already on, skip next steps */
4558
4559                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4560                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4561         } else {
4562                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4563                         return I40E_SUCCESS; /* already off, skip next steps */
4564                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4565         }
4566         /* Write the register */
4567         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4568         /* Check the result */
4569         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4570                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4571                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4572                 if (on) {
4573                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4574                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4575                                 break;
4576                 } else {
4577                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4578                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4579                                 break;
4580                 }
4581         }
4582         /* Check if it is timeout */
4583         if (j >= I40E_CHK_Q_ENA_COUNT) {
4584                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4585                             (on ? "enable" : "disable"), q_idx);
4586                 return I40E_ERR_TIMEOUT;
4587         }
4588
4589         return I40E_SUCCESS;
4590 }
4591
4592 /* Swith on or off the tx queues */
4593 static int
4594 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4595 {
4596         struct rte_eth_dev_data *dev_data = pf->dev_data;
4597         struct i40e_tx_queue *txq;
4598         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4599         uint16_t i;
4600         int ret;
4601
4602         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4603                 txq = dev_data->tx_queues[i];
4604                 /* Don't operate the queue if not configured or
4605                  * if starting only per queue */
4606                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4607                         continue;
4608                 if (on)
4609                         ret = i40e_dev_tx_queue_start(dev, i);
4610                 else
4611                         ret = i40e_dev_tx_queue_stop(dev, i);
4612                 if ( ret != I40E_SUCCESS)
4613                         return ret;
4614         }
4615
4616         return I40E_SUCCESS;
4617 }
4618
4619 int
4620 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4621 {
4622         uint32_t reg;
4623         uint16_t j;
4624
4625         /* Wait until the request is finished */
4626         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4627                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4628                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4629                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4630                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4631                         break;
4632         }
4633
4634         if (on) {
4635                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4636                         return I40E_SUCCESS; /* Already on, skip next steps */
4637                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4638         } else {
4639                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4640                         return I40E_SUCCESS; /* Already off, skip next steps */
4641                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4642         }
4643
4644         /* Write the register */
4645         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4646         /* Check the result */
4647         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4648                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4649                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4650                 if (on) {
4651                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4652                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4653                                 break;
4654                 } else {
4655                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4656                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4657                                 break;
4658                 }
4659         }
4660
4661         /* Check if it is timeout */
4662         if (j >= I40E_CHK_Q_ENA_COUNT) {
4663                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4664                             (on ? "enable" : "disable"), q_idx);
4665                 return I40E_ERR_TIMEOUT;
4666         }
4667
4668         return I40E_SUCCESS;
4669 }
4670 /* Switch on or off the rx queues */
4671 static int
4672 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4673 {
4674         struct rte_eth_dev_data *dev_data = pf->dev_data;
4675         struct i40e_rx_queue *rxq;
4676         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4677         uint16_t i;
4678         int ret;
4679
4680         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4681                 rxq = dev_data->rx_queues[i];
4682                 /* Don't operate the queue if not configured or
4683                  * if starting only per queue */
4684                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4685                         continue;
4686                 if (on)
4687                         ret = i40e_dev_rx_queue_start(dev, i);
4688                 else
4689                         ret = i40e_dev_rx_queue_stop(dev, i);
4690                 if (ret != I40E_SUCCESS)
4691                         return ret;
4692         }
4693
4694         return I40E_SUCCESS;
4695 }
4696
4697 /* Switch on or off all the rx/tx queues */
4698 int
4699 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4700 {
4701         int ret;
4702
4703         if (on) {
4704                 /* enable rx queues before enabling tx queues */
4705                 ret = i40e_dev_switch_rx_queues(pf, on);
4706                 if (ret) {
4707                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4708                         return ret;
4709                 }
4710                 ret = i40e_dev_switch_tx_queues(pf, on);
4711         } else {
4712                 /* Stop tx queues before stopping rx queues */
4713                 ret = i40e_dev_switch_tx_queues(pf, on);
4714                 if (ret) {
4715                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4716                         return ret;
4717                 }
4718                 ret = i40e_dev_switch_rx_queues(pf, on);
4719         }
4720
4721         return ret;
4722 }
4723
4724 /* Initialize VSI for TX */
4725 static int
4726 i40e_dev_tx_init(struct i40e_pf *pf)
4727 {
4728         struct rte_eth_dev_data *data = pf->dev_data;
4729         uint16_t i;
4730         uint32_t ret = I40E_SUCCESS;
4731         struct i40e_tx_queue *txq;
4732
4733         for (i = 0; i < data->nb_tx_queues; i++) {
4734                 txq = data->tx_queues[i];
4735                 if (!txq || !txq->q_set)
4736                         continue;
4737                 ret = i40e_tx_queue_init(txq);
4738                 if (ret != I40E_SUCCESS)
4739                         break;
4740         }
4741         if (ret == I40E_SUCCESS)
4742                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4743                                      ->eth_dev);
4744
4745         return ret;
4746 }
4747
4748 /* Initialize VSI for RX */
4749 static int
4750 i40e_dev_rx_init(struct i40e_pf *pf)
4751 {
4752         struct rte_eth_dev_data *data = pf->dev_data;
4753         int ret = I40E_SUCCESS;
4754         uint16_t i;
4755         struct i40e_rx_queue *rxq;
4756
4757         i40e_pf_config_mq_rx(pf);
4758         for (i = 0; i < data->nb_rx_queues; i++) {
4759                 rxq = data->rx_queues[i];
4760                 if (!rxq || !rxq->q_set)
4761                         continue;
4762
4763                 ret = i40e_rx_queue_init(rxq);
4764                 if (ret != I40E_SUCCESS) {
4765                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4766                                     "initialization");
4767                         break;
4768                 }
4769         }
4770         if (ret == I40E_SUCCESS)
4771                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4772                                      ->eth_dev);
4773
4774         return ret;
4775 }
4776
4777 static int
4778 i40e_dev_rxtx_init(struct i40e_pf *pf)
4779 {
4780         int err;
4781
4782         err = i40e_dev_tx_init(pf);
4783         if (err) {
4784                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4785                 return err;
4786         }
4787         err = i40e_dev_rx_init(pf);
4788         if (err) {
4789                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4790                 return err;
4791         }
4792
4793         return err;
4794 }
4795
4796 static int
4797 i40e_vmdq_setup(struct rte_eth_dev *dev)
4798 {
4799         struct rte_eth_conf *conf = &dev->data->dev_conf;
4800         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4801         int i, err, conf_vsis, j, loop;
4802         struct i40e_vsi *vsi;
4803         struct i40e_vmdq_info *vmdq_info;
4804         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4805         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4806
4807         /*
4808          * Disable interrupt to avoid message from VF. Furthermore, it will
4809          * avoid race condition in VSI creation/destroy.
4810          */
4811         i40e_pf_disable_irq0(hw);
4812
4813         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4814                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4815                 return -ENOTSUP;
4816         }
4817
4818         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4819         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4820                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4821                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4822                         pf->max_nb_vmdq_vsi);
4823                 return -ENOTSUP;
4824         }
4825
4826         if (pf->vmdq != NULL) {
4827                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4828                 return 0;
4829         }
4830
4831         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4832                                 sizeof(*vmdq_info) * conf_vsis, 0);
4833
4834         if (pf->vmdq == NULL) {
4835                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4836                 return -ENOMEM;
4837         }
4838
4839         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4840
4841         /* Create VMDQ VSI */
4842         for (i = 0; i < conf_vsis; i++) {
4843                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4844                                 vmdq_conf->enable_loop_back);
4845                 if (vsi == NULL) {
4846                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4847                         err = -1;
4848                         goto err_vsi_setup;
4849                 }
4850                 vmdq_info = &pf->vmdq[i];
4851                 vmdq_info->pf = pf;
4852                 vmdq_info->vsi = vsi;
4853         }
4854         pf->nb_cfg_vmdq_vsi = conf_vsis;
4855
4856         /* Configure Vlan */
4857         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4858         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4859                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4860                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4861                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4862                                         vmdq_conf->pool_map[i].vlan_id, j);
4863
4864                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4865                                                 vmdq_conf->pool_map[i].vlan_id);
4866                                 if (err) {
4867                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4868                                         err = -1;
4869                                         goto err_vsi_setup;
4870                                 }
4871                         }
4872                 }
4873         }
4874
4875         i40e_pf_enable_irq0(hw);
4876
4877         return 0;
4878
4879 err_vsi_setup:
4880         for (i = 0; i < conf_vsis; i++)
4881                 if (pf->vmdq[i].vsi == NULL)
4882                         break;
4883                 else
4884                         i40e_vsi_release(pf->vmdq[i].vsi);
4885
4886         rte_free(pf->vmdq);
4887         pf->vmdq = NULL;
4888         i40e_pf_enable_irq0(hw);
4889         return err;
4890 }
4891
4892 static void
4893 i40e_stat_update_32(struct i40e_hw *hw,
4894                    uint32_t reg,
4895                    bool offset_loaded,
4896                    uint64_t *offset,
4897                    uint64_t *stat)
4898 {
4899         uint64_t new_data;
4900
4901         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4902         if (!offset_loaded)
4903                 *offset = new_data;
4904
4905         if (new_data >= *offset)
4906                 *stat = (uint64_t)(new_data - *offset);
4907         else
4908                 *stat = (uint64_t)((new_data +
4909                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4910 }
4911
4912 static void
4913 i40e_stat_update_48(struct i40e_hw *hw,
4914                    uint32_t hireg,
4915                    uint32_t loreg,
4916                    bool offset_loaded,
4917                    uint64_t *offset,
4918                    uint64_t *stat)
4919 {
4920         uint64_t new_data;
4921
4922         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4923         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4924                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4925
4926         if (!offset_loaded)
4927                 *offset = new_data;
4928
4929         if (new_data >= *offset)
4930                 *stat = new_data - *offset;
4931         else
4932                 *stat = (uint64_t)((new_data +
4933                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4934
4935         *stat &= I40E_48_BIT_MASK;
4936 }
4937
4938 /* Disable IRQ0 */
4939 void
4940 i40e_pf_disable_irq0(struct i40e_hw *hw)
4941 {
4942         /* Disable all interrupt types */
4943         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4944         I40E_WRITE_FLUSH(hw);
4945 }
4946
4947 /* Enable IRQ0 */
4948 void
4949 i40e_pf_enable_irq0(struct i40e_hw *hw)
4950 {
4951         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4952                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4953                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4954                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4955         I40E_WRITE_FLUSH(hw);
4956 }
4957
4958 static void
4959 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4960 {
4961         /* read pending request and disable first */
4962         i40e_pf_disable_irq0(hw);
4963         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4964         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4965                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4966
4967         if (no_queue)
4968                 /* Link no queues with irq0 */
4969                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4970                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4971 }
4972
4973 static void
4974 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4975 {
4976         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4977         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4978         int i;
4979         uint16_t abs_vf_id;
4980         uint32_t index, offset, val;
4981
4982         if (!pf->vfs)
4983                 return;
4984         /**
4985          * Try to find which VF trigger a reset, use absolute VF id to access
4986          * since the reg is global register.
4987          */
4988         for (i = 0; i < pf->vf_num; i++) {
4989                 abs_vf_id = hw->func_caps.vf_base_id + i;
4990                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4991                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4992                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4993                 /* VFR event occured */
4994                 if (val & (0x1 << offset)) {
4995                         int ret;
4996
4997                         /* Clear the event first */
4998                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4999                                                         (0x1 << offset));
5000                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5001                         /**
5002                          * Only notify a VF reset event occured,
5003                          * don't trigger another SW reset
5004                          */
5005                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5006                         if (ret != I40E_SUCCESS)
5007                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5008                 }
5009         }
5010 }
5011
5012 static void
5013 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5014 {
5015         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5016         struct i40e_arq_event_info info;
5017         uint16_t pending, opcode;
5018         int ret;
5019
5020         info.buf_len = I40E_AQ_BUF_SZ;
5021         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5022         if (!info.msg_buf) {
5023                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5024                 return;
5025         }
5026
5027         pending = 1;
5028         while (pending) {
5029                 ret = i40e_clean_arq_element(hw, &info, &pending);
5030
5031                 if (ret != I40E_SUCCESS) {
5032                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5033                                     "aq_err: %u", hw->aq.asq_last_status);
5034                         break;
5035                 }
5036                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5037
5038                 switch (opcode) {
5039                 case i40e_aqc_opc_send_msg_to_pf:
5040                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5041                         i40e_pf_host_handle_vf_msg(dev,
5042                                         rte_le_to_cpu_16(info.desc.retval),
5043                                         rte_le_to_cpu_32(info.desc.cookie_high),
5044                                         rte_le_to_cpu_32(info.desc.cookie_low),
5045                                         info.msg_buf,
5046                                         info.msg_len);
5047                         break;
5048                 default:
5049                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5050                                     opcode);
5051                         break;
5052                 }
5053         }
5054         rte_free(info.msg_buf);
5055 }
5056
5057 /*
5058  * Interrupt handler is registered as the alarm callback for handling LSC
5059  * interrupt in a definite of time, in order to wait the NIC into a stable
5060  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5061  * no need for link down interrupt.
5062  */
5063 static void
5064 i40e_dev_interrupt_delayed_handler(void *param)
5065 {
5066         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5068         uint32_t icr0;
5069
5070         /* read interrupt causes again */
5071         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5072
5073 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5074         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5075                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5076         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5077                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5078         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5079                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5080         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5081                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5082         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5083                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5084                                                                 "state\n");
5085         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5086                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5087         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5088                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5089 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5090
5091         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5092                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5093                 i40e_dev_handle_vfr_event(dev);
5094         }
5095         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5096                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5097                 i40e_dev_handle_aq_msg(dev);
5098         }
5099
5100         /* handle the link up interrupt in an alarm callback */
5101         i40e_dev_link_update(dev, 0);
5102         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5103
5104         i40e_pf_enable_irq0(hw);
5105         rte_intr_enable(&(dev->pci_dev->intr_handle));
5106 }
5107
5108 /**
5109  * Interrupt handler triggered by NIC  for handling
5110  * specific interrupt.
5111  *
5112  * @param handle
5113  *  Pointer to interrupt handle.
5114  * @param param
5115  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5116  *
5117  * @return
5118  *  void
5119  */
5120 static void
5121 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5122                            void *param)
5123 {
5124         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5126         uint32_t icr0;
5127
5128         /* Disable interrupt */
5129         i40e_pf_disable_irq0(hw);
5130
5131         /* read out interrupt causes */
5132         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5133
5134         /* No interrupt event indicated */
5135         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5136                 PMD_DRV_LOG(INFO, "No interrupt event");
5137                 goto done;
5138         }
5139 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5140         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5141                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5142         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5143                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5144         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5145                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5146         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5147                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5148         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5149                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5150         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5151                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5152         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5153                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5154 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5155
5156         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5157                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5158                 i40e_dev_handle_vfr_event(dev);
5159         }
5160         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5161                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5162                 i40e_dev_handle_aq_msg(dev);
5163         }
5164
5165         /* Link Status Change interrupt */
5166         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5167 #define I40E_US_PER_SECOND 1000000
5168                 struct rte_eth_link link;
5169
5170                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5171                 memset(&link, 0, sizeof(link));
5172                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5173                 i40e_dev_link_update(dev, 0);
5174
5175                 /*
5176                  * For link up interrupt, it needs to wait 1 second to let the
5177                  * hardware be a stable state. Otherwise several consecutive
5178                  * interrupts can be observed.
5179                  * For link down interrupt, no need to wait.
5180                  */
5181                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5182                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5183                         return;
5184                 else
5185                         _rte_eth_dev_callback_process(dev,
5186                                 RTE_ETH_EVENT_INTR_LSC);
5187         }
5188
5189 done:
5190         /* Enable interrupt */
5191         i40e_pf_enable_irq0(hw);
5192         rte_intr_enable(&(dev->pci_dev->intr_handle));
5193 }
5194
5195 static int
5196 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5197                          struct i40e_macvlan_filter *filter,
5198                          int total)
5199 {
5200         int ele_num, ele_buff_size;
5201         int num, actual_num, i;
5202         uint16_t flags;
5203         int ret = I40E_SUCCESS;
5204         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5205         struct i40e_aqc_add_macvlan_element_data *req_list;
5206
5207         if (filter == NULL  || total == 0)
5208                 return I40E_ERR_PARAM;
5209         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5210         ele_buff_size = hw->aq.asq_buf_size;
5211
5212         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5213         if (req_list == NULL) {
5214                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5215                 return I40E_ERR_NO_MEMORY;
5216         }
5217
5218         num = 0;
5219         do {
5220                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5221                 memset(req_list, 0, ele_buff_size);
5222
5223                 for (i = 0; i < actual_num; i++) {
5224                         (void)rte_memcpy(req_list[i].mac_addr,
5225                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5226                         req_list[i].vlan_tag =
5227                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5228
5229                         switch (filter[num + i].filter_type) {
5230                         case RTE_MAC_PERFECT_MATCH:
5231                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5232                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5233                                 break;
5234                         case RTE_MACVLAN_PERFECT_MATCH:
5235                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5236                                 break;
5237                         case RTE_MAC_HASH_MATCH:
5238                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5239                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5240                                 break;
5241                         case RTE_MACVLAN_HASH_MATCH:
5242                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5243                                 break;
5244                         default:
5245                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5246                                 ret = I40E_ERR_PARAM;
5247                                 goto DONE;
5248                         }
5249
5250                         req_list[i].queue_number = 0;
5251
5252                         req_list[i].flags = rte_cpu_to_le_16(flags);
5253                 }
5254
5255                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5256                                                 actual_num, NULL);
5257                 if (ret != I40E_SUCCESS) {
5258                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5259                         goto DONE;
5260                 }
5261                 num += actual_num;
5262         } while (num < total);
5263
5264 DONE:
5265         rte_free(req_list);
5266         return ret;
5267 }
5268
5269 static int
5270 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5271                             struct i40e_macvlan_filter *filter,
5272                             int total)
5273 {
5274         int ele_num, ele_buff_size;
5275         int num, actual_num, i;
5276         uint16_t flags;
5277         int ret = I40E_SUCCESS;
5278         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5279         struct i40e_aqc_remove_macvlan_element_data *req_list;
5280
5281         if (filter == NULL  || total == 0)
5282                 return I40E_ERR_PARAM;
5283
5284         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5285         ele_buff_size = hw->aq.asq_buf_size;
5286
5287         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5288         if (req_list == NULL) {
5289                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5290                 return I40E_ERR_NO_MEMORY;
5291         }
5292
5293         num = 0;
5294         do {
5295                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5296                 memset(req_list, 0, ele_buff_size);
5297
5298                 for (i = 0; i < actual_num; i++) {
5299                         (void)rte_memcpy(req_list[i].mac_addr,
5300                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5301                         req_list[i].vlan_tag =
5302                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5303
5304                         switch (filter[num + i].filter_type) {
5305                         case RTE_MAC_PERFECT_MATCH:
5306                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5307                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5308                                 break;
5309                         case RTE_MACVLAN_PERFECT_MATCH:
5310                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5311                                 break;
5312                         case RTE_MAC_HASH_MATCH:
5313                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5314                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5315                                 break;
5316                         case RTE_MACVLAN_HASH_MATCH:
5317                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5318                                 break;
5319                         default:
5320                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5321                                 ret = I40E_ERR_PARAM;
5322                                 goto DONE;
5323                         }
5324                         req_list[i].flags = rte_cpu_to_le_16(flags);
5325                 }
5326
5327                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5328                                                 actual_num, NULL);
5329                 if (ret != I40E_SUCCESS) {
5330                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5331                         goto DONE;
5332                 }
5333                 num += actual_num;
5334         } while (num < total);
5335
5336 DONE:
5337         rte_free(req_list);
5338         return ret;
5339 }
5340
5341 /* Find out specific MAC filter */
5342 static struct i40e_mac_filter *
5343 i40e_find_mac_filter(struct i40e_vsi *vsi,
5344                          struct ether_addr *macaddr)
5345 {
5346         struct i40e_mac_filter *f;
5347
5348         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5349                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5350                         return f;
5351         }
5352
5353         return NULL;
5354 }
5355
5356 static bool
5357 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5358                          uint16_t vlan_id)
5359 {
5360         uint32_t vid_idx, vid_bit;
5361
5362         if (vlan_id > ETH_VLAN_ID_MAX)
5363                 return 0;
5364
5365         vid_idx = I40E_VFTA_IDX(vlan_id);
5366         vid_bit = I40E_VFTA_BIT(vlan_id);
5367
5368         if (vsi->vfta[vid_idx] & vid_bit)
5369                 return 1;
5370         else
5371                 return 0;
5372 }
5373
5374 static void
5375 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5376                          uint16_t vlan_id, bool on)
5377 {
5378         uint32_t vid_idx, vid_bit;
5379
5380         if (vlan_id > ETH_VLAN_ID_MAX)
5381                 return;
5382
5383         vid_idx = I40E_VFTA_IDX(vlan_id);
5384         vid_bit = I40E_VFTA_BIT(vlan_id);
5385
5386         if (on)
5387                 vsi->vfta[vid_idx] |= vid_bit;
5388         else
5389                 vsi->vfta[vid_idx] &= ~vid_bit;
5390 }
5391
5392 /**
5393  * Find all vlan options for specific mac addr,
5394  * return with actual vlan found.
5395  */
5396 static inline int
5397 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5398                            struct i40e_macvlan_filter *mv_f,
5399                            int num, struct ether_addr *addr)
5400 {
5401         int i;
5402         uint32_t j, k;
5403
5404         /**
5405          * Not to use i40e_find_vlan_filter to decrease the loop time,
5406          * although the code looks complex.
5407           */
5408         if (num < vsi->vlan_num)
5409                 return I40E_ERR_PARAM;
5410
5411         i = 0;
5412         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5413                 if (vsi->vfta[j]) {
5414                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5415                                 if (vsi->vfta[j] & (1 << k)) {
5416                                         if (i > num - 1) {
5417                                                 PMD_DRV_LOG(ERR, "vlan number "
5418                                                             "not match");
5419                                                 return I40E_ERR_PARAM;
5420                                         }
5421                                         (void)rte_memcpy(&mv_f[i].macaddr,
5422                                                         addr, ETH_ADDR_LEN);
5423                                         mv_f[i].vlan_id =
5424                                                 j * I40E_UINT32_BIT_SIZE + k;
5425                                         i++;
5426                                 }
5427                         }
5428                 }
5429         }
5430         return I40E_SUCCESS;
5431 }
5432
5433 static inline int
5434 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5435                            struct i40e_macvlan_filter *mv_f,
5436                            int num,
5437                            uint16_t vlan)
5438 {
5439         int i = 0;
5440         struct i40e_mac_filter *f;
5441
5442         if (num < vsi->mac_num)
5443                 return I40E_ERR_PARAM;
5444
5445         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5446                 if (i > num - 1) {
5447                         PMD_DRV_LOG(ERR, "buffer number not match");
5448                         return I40E_ERR_PARAM;
5449                 }
5450                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5451                                 ETH_ADDR_LEN);
5452                 mv_f[i].vlan_id = vlan;
5453                 mv_f[i].filter_type = f->mac_info.filter_type;
5454                 i++;
5455         }
5456
5457         return I40E_SUCCESS;
5458 }
5459
5460 static int
5461 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5462 {
5463         int i, num;
5464         struct i40e_mac_filter *f;
5465         struct i40e_macvlan_filter *mv_f;
5466         int ret = I40E_SUCCESS;
5467
5468         if (vsi == NULL || vsi->mac_num == 0)
5469                 return I40E_ERR_PARAM;
5470
5471         /* Case that no vlan is set */
5472         if (vsi->vlan_num == 0)
5473                 num = vsi->mac_num;
5474         else
5475                 num = vsi->mac_num * vsi->vlan_num;
5476
5477         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5478         if (mv_f == NULL) {
5479                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5480                 return I40E_ERR_NO_MEMORY;
5481         }
5482
5483         i = 0;
5484         if (vsi->vlan_num == 0) {
5485                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5486                         (void)rte_memcpy(&mv_f[i].macaddr,
5487                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5488                         mv_f[i].vlan_id = 0;
5489                         i++;
5490                 }
5491         } else {
5492                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5493                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5494                                         vsi->vlan_num, &f->mac_info.mac_addr);
5495                         if (ret != I40E_SUCCESS)
5496                                 goto DONE;
5497                         i += vsi->vlan_num;
5498                 }
5499         }
5500
5501         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5502 DONE:
5503         rte_free(mv_f);
5504
5505         return ret;
5506 }
5507
5508 int
5509 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5510 {
5511         struct i40e_macvlan_filter *mv_f;
5512         int mac_num;
5513         int ret = I40E_SUCCESS;
5514
5515         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5516                 return I40E_ERR_PARAM;
5517
5518         /* If it's already set, just return */
5519         if (i40e_find_vlan_filter(vsi,vlan))
5520                 return I40E_SUCCESS;
5521
5522         mac_num = vsi->mac_num;
5523
5524         if (mac_num == 0) {
5525                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5526                 return I40E_ERR_PARAM;
5527         }
5528
5529         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5530
5531         if (mv_f == NULL) {
5532                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5533                 return I40E_ERR_NO_MEMORY;
5534         }
5535
5536         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5537
5538         if (ret != I40E_SUCCESS)
5539                 goto DONE;
5540
5541         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5542
5543         if (ret != I40E_SUCCESS)
5544                 goto DONE;
5545
5546         i40e_set_vlan_filter(vsi, vlan, 1);
5547
5548         vsi->vlan_num++;
5549         ret = I40E_SUCCESS;
5550 DONE:
5551         rte_free(mv_f);
5552         return ret;
5553 }
5554
5555 int
5556 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5557 {
5558         struct i40e_macvlan_filter *mv_f;
5559         int mac_num;
5560         int ret = I40E_SUCCESS;
5561
5562         /**
5563          * Vlan 0 is the generic filter for untagged packets
5564          * and can't be removed.
5565          */
5566         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5567                 return I40E_ERR_PARAM;
5568
5569         /* If can't find it, just return */
5570         if (!i40e_find_vlan_filter(vsi, vlan))
5571                 return I40E_ERR_PARAM;
5572
5573         mac_num = vsi->mac_num;
5574
5575         if (mac_num == 0) {
5576                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5577                 return I40E_ERR_PARAM;
5578         }
5579
5580         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5581
5582         if (mv_f == NULL) {
5583                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5584                 return I40E_ERR_NO_MEMORY;
5585         }
5586
5587         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5588
5589         if (ret != I40E_SUCCESS)
5590                 goto DONE;
5591
5592         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5593
5594         if (ret != I40E_SUCCESS)
5595                 goto DONE;
5596
5597         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5598         if (vsi->vlan_num == 1) {
5599                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5600                 if (ret != I40E_SUCCESS)
5601                         goto DONE;
5602
5603                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5604                 if (ret != I40E_SUCCESS)
5605                         goto DONE;
5606         }
5607
5608         i40e_set_vlan_filter(vsi, vlan, 0);
5609
5610         vsi->vlan_num--;
5611         ret = I40E_SUCCESS;
5612 DONE:
5613         rte_free(mv_f);
5614         return ret;
5615 }
5616
5617 int
5618 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5619 {
5620         struct i40e_mac_filter *f;
5621         struct i40e_macvlan_filter *mv_f;
5622         int i, vlan_num = 0;
5623         int ret = I40E_SUCCESS;
5624
5625         /* If it's add and we've config it, return */
5626         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5627         if (f != NULL)
5628                 return I40E_SUCCESS;
5629         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5630                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5631
5632                 /**
5633                  * If vlan_num is 0, that's the first time to add mac,
5634                  * set mask for vlan_id 0.
5635                  */
5636                 if (vsi->vlan_num == 0) {
5637                         i40e_set_vlan_filter(vsi, 0, 1);
5638                         vsi->vlan_num = 1;
5639                 }
5640                 vlan_num = vsi->vlan_num;
5641         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5642                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5643                 vlan_num = 1;
5644
5645         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5646         if (mv_f == NULL) {
5647                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5648                 return I40E_ERR_NO_MEMORY;
5649         }
5650
5651         for (i = 0; i < vlan_num; i++) {
5652                 mv_f[i].filter_type = mac_filter->filter_type;
5653                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5654                                 ETH_ADDR_LEN);
5655         }
5656
5657         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5658                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5659                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5660                                         &mac_filter->mac_addr);
5661                 if (ret != I40E_SUCCESS)
5662                         goto DONE;
5663         }
5664
5665         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5666         if (ret != I40E_SUCCESS)
5667                 goto DONE;
5668
5669         /* Add the mac addr into mac list */
5670         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5671         if (f == NULL) {
5672                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5673                 ret = I40E_ERR_NO_MEMORY;
5674                 goto DONE;
5675         }
5676         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5677                         ETH_ADDR_LEN);
5678         f->mac_info.filter_type = mac_filter->filter_type;
5679         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5680         vsi->mac_num++;
5681
5682         ret = I40E_SUCCESS;
5683 DONE:
5684         rte_free(mv_f);
5685
5686         return ret;
5687 }
5688
5689 int
5690 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5691 {
5692         struct i40e_mac_filter *f;
5693         struct i40e_macvlan_filter *mv_f;
5694         int i, vlan_num;
5695         enum rte_mac_filter_type filter_type;
5696         int ret = I40E_SUCCESS;
5697
5698         /* Can't find it, return an error */
5699         f = i40e_find_mac_filter(vsi, addr);
5700         if (f == NULL)
5701                 return I40E_ERR_PARAM;
5702
5703         vlan_num = vsi->vlan_num;
5704         filter_type = f->mac_info.filter_type;
5705         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5706                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5707                 if (vlan_num == 0) {
5708                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5709                         return I40E_ERR_PARAM;
5710                 }
5711         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5712                         filter_type == RTE_MAC_HASH_MATCH)
5713                 vlan_num = 1;
5714
5715         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5716         if (mv_f == NULL) {
5717                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5718                 return I40E_ERR_NO_MEMORY;
5719         }
5720
5721         for (i = 0; i < vlan_num; i++) {
5722                 mv_f[i].filter_type = filter_type;
5723                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5724                                 ETH_ADDR_LEN);
5725         }
5726         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5727                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5728                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5729                 if (ret != I40E_SUCCESS)
5730                         goto DONE;
5731         }
5732
5733         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5734         if (ret != I40E_SUCCESS)
5735                 goto DONE;
5736
5737         /* Remove the mac addr into mac list */
5738         TAILQ_REMOVE(&vsi->mac_list, f, next);
5739         rte_free(f);
5740         vsi->mac_num--;
5741
5742         ret = I40E_SUCCESS;
5743 DONE:
5744         rte_free(mv_f);
5745         return ret;
5746 }
5747
5748 /* Configure hash enable flags for RSS */
5749 uint64_t
5750 i40e_config_hena(uint64_t flags)
5751 {
5752         uint64_t hena = 0;
5753
5754         if (!flags)
5755                 return hena;
5756
5757         if (flags & ETH_RSS_FRAG_IPV4)
5758                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5759         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5760                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5761         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5762                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5763         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5764                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5765         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5766                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5767         if (flags & ETH_RSS_FRAG_IPV6)
5768                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5769         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5770                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5771         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5772                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5773         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5774                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5775         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5776                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5777         if (flags & ETH_RSS_L2_PAYLOAD)
5778                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5779
5780         return hena;
5781 }
5782
5783 /* Parse the hash enable flags */
5784 uint64_t
5785 i40e_parse_hena(uint64_t flags)
5786 {
5787         uint64_t rss_hf = 0;
5788
5789         if (!flags)
5790                 return rss_hf;
5791         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5792                 rss_hf |= ETH_RSS_FRAG_IPV4;
5793         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5794                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5795         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5796                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5797         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5798                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5799         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5800                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5801         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5802                 rss_hf |= ETH_RSS_FRAG_IPV6;
5803         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5804                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5805         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5806                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5807         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5808                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5809         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5810                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5811         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5812                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5813
5814         return rss_hf;
5815 }
5816
5817 /* Disable RSS */
5818 static void
5819 i40e_pf_disable_rss(struct i40e_pf *pf)
5820 {
5821         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5822         uint64_t hena;
5823
5824         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5825         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5826         hena &= ~I40E_RSS_HENA_ALL;
5827         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5828         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5829         I40E_WRITE_FLUSH(hw);
5830 }
5831
5832 static int
5833 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5834 {
5835         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5836         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5837         int ret = 0;
5838
5839         if (!key || key_len == 0) {
5840                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5841                 return 0;
5842         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5843                 sizeof(uint32_t)) {
5844                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5845                 return -EINVAL;
5846         }
5847
5848         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5849                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5850                         (struct i40e_aqc_get_set_rss_key_data *)key;
5851
5852                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5853                 if (ret)
5854                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5855                                      "via AQ");
5856         } else {
5857                 uint32_t *hash_key = (uint32_t *)key;
5858                 uint16_t i;
5859
5860                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5861                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5862                 I40E_WRITE_FLUSH(hw);
5863         }
5864
5865         return ret;
5866 }
5867
5868 static int
5869 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5870 {
5871         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5872         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5873         int ret;
5874
5875         if (!key || !key_len)
5876                 return -EINVAL;
5877
5878         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5879                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5880                         (struct i40e_aqc_get_set_rss_key_data *)key);
5881                 if (ret) {
5882                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5883                         return ret;
5884                 }
5885         } else {
5886                 uint32_t *key_dw = (uint32_t *)key;
5887                 uint16_t i;
5888
5889                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5890                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5891         }
5892         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5893
5894         return 0;
5895 }
5896
5897 static int
5898 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5899 {
5900         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5901         uint64_t rss_hf;
5902         uint64_t hena;
5903         int ret;
5904
5905         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5906                                rss_conf->rss_key_len);
5907         if (ret)
5908                 return ret;
5909
5910         rss_hf = rss_conf->rss_hf;
5911         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5912         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5913         hena &= ~I40E_RSS_HENA_ALL;
5914         hena |= i40e_config_hena(rss_hf);
5915         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5916         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5917         I40E_WRITE_FLUSH(hw);
5918
5919         return 0;
5920 }
5921
5922 static int
5923 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5924                          struct rte_eth_rss_conf *rss_conf)
5925 {
5926         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5928         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5929         uint64_t hena;
5930
5931         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5932         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5933         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5934                 if (rss_hf != 0) /* Enable RSS */
5935                         return -EINVAL;
5936                 return 0; /* Nothing to do */
5937         }
5938         /* RSS enabled */
5939         if (rss_hf == 0) /* Disable RSS */
5940                 return -EINVAL;
5941
5942         return i40e_hw_rss_hash_set(pf, rss_conf);
5943 }
5944
5945 static int
5946 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5947                            struct rte_eth_rss_conf *rss_conf)
5948 {
5949         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5950         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5951         uint64_t hena;
5952
5953         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5954                          &rss_conf->rss_key_len);
5955
5956         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5957         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5958         rss_conf->rss_hf = i40e_parse_hena(hena);
5959
5960         return 0;
5961 }
5962
5963 static int
5964 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5965 {
5966         switch (filter_type) {
5967         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5968                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5969                 break;
5970         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5971                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5972                 break;
5973         case RTE_TUNNEL_FILTER_IMAC_TENID:
5974                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5975                 break;
5976         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5977                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5978                 break;
5979         case ETH_TUNNEL_FILTER_IMAC:
5980                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5981                 break;
5982         case ETH_TUNNEL_FILTER_OIP:
5983                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
5984                 break;
5985         case ETH_TUNNEL_FILTER_IIP:
5986                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
5987                 break;
5988         default:
5989                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5990                 return -EINVAL;
5991         }
5992
5993         return 0;
5994 }
5995
5996 static int
5997 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5998                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5999                         uint8_t add)
6000 {
6001         uint16_t ip_type;
6002         uint8_t i, tun_type = 0;
6003         /* internal varialbe to convert ipv6 byte order */
6004         uint32_t convert_ipv6[4];
6005         int val, ret = 0;
6006         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6007         struct i40e_vsi *vsi = pf->main_vsi;
6008         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6009         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6010
6011         cld_filter = rte_zmalloc("tunnel_filter",
6012                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6013                 0);
6014
6015         if (NULL == cld_filter) {
6016                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6017                 return -EINVAL;
6018         }
6019         pfilter = cld_filter;
6020
6021         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6022         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6023
6024         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6025         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6026                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6027                 rte_memcpy(&pfilter->ipaddr.v4.data,
6028                                 &rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv4_addr),
6029                                 sizeof(pfilter->ipaddr.v4.data));
6030         } else {
6031                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6032                 for (i = 0; i < 4; i++) {
6033                         convert_ipv6[i] =
6034                         rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv6_addr[i]);
6035                 }
6036                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6037                                 sizeof(pfilter->ipaddr.v6.data));
6038         }
6039
6040         /* check tunneled type */
6041         switch (tunnel_filter->tunnel_type) {
6042         case RTE_TUNNEL_TYPE_VXLAN:
6043                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6044                 break;
6045         case RTE_TUNNEL_TYPE_NVGRE:
6046                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6047                 break;
6048         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6049                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6050                 break;
6051         default:
6052                 /* Other tunnel types is not supported. */
6053                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6054                 rte_free(cld_filter);
6055                 return -EINVAL;
6056         }
6057
6058         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6059                                                 &pfilter->flags);
6060         if (val < 0) {
6061                 rte_free(cld_filter);
6062                 return -EINVAL;
6063         }
6064
6065         pfilter->flags |= rte_cpu_to_le_16(
6066                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6067                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6068         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6069         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6070
6071         if (add)
6072                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6073         else
6074                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6075                                                 cld_filter, 1);
6076
6077         rte_free(cld_filter);
6078         return ret;
6079 }
6080
6081 static int
6082 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6083 {
6084         uint8_t i;
6085
6086         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6087                 if (pf->vxlan_ports[i] == port)
6088                         return i;
6089         }
6090
6091         return -1;
6092 }
6093
6094 static int
6095 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6096 {
6097         int  idx, ret;
6098         uint8_t filter_idx;
6099         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6100
6101         idx = i40e_get_vxlan_port_idx(pf, port);
6102
6103         /* Check if port already exists */
6104         if (idx >= 0) {
6105                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6106                 return -EINVAL;
6107         }
6108
6109         /* Now check if there is space to add the new port */
6110         idx = i40e_get_vxlan_port_idx(pf, 0);
6111         if (idx < 0) {
6112                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6113                         "not adding port %d", port);
6114                 return -ENOSPC;
6115         }
6116
6117         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6118                                         &filter_idx, NULL);
6119         if (ret < 0) {
6120                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6121                 return -1;
6122         }
6123
6124         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6125                          port,  filter_idx);
6126
6127         /* New port: add it and mark its index in the bitmap */
6128         pf->vxlan_ports[idx] = port;
6129         pf->vxlan_bitmap |= (1 << idx);
6130
6131         if (!(pf->flags & I40E_FLAG_VXLAN))
6132                 pf->flags |= I40E_FLAG_VXLAN;
6133
6134         return 0;
6135 }
6136
6137 static int
6138 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6139 {
6140         int idx;
6141         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6142
6143         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6144                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6145                 return -EINVAL;
6146         }
6147
6148         idx = i40e_get_vxlan_port_idx(pf, port);
6149
6150         if (idx < 0) {
6151                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6152                 return -EINVAL;
6153         }
6154
6155         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6156                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6157                 return -1;
6158         }
6159
6160         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6161                         port, idx);
6162
6163         pf->vxlan_ports[idx] = 0;
6164         pf->vxlan_bitmap &= ~(1 << idx);
6165
6166         if (!pf->vxlan_bitmap)
6167                 pf->flags &= ~I40E_FLAG_VXLAN;
6168
6169         return 0;
6170 }
6171
6172 /* Add UDP tunneling port */
6173 static int
6174 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6175                              struct rte_eth_udp_tunnel *udp_tunnel)
6176 {
6177         int ret = 0;
6178         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6179
6180         if (udp_tunnel == NULL)
6181                 return -EINVAL;
6182
6183         switch (udp_tunnel->prot_type) {
6184         case RTE_TUNNEL_TYPE_VXLAN:
6185                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6186                 break;
6187
6188         case RTE_TUNNEL_TYPE_GENEVE:
6189         case RTE_TUNNEL_TYPE_TEREDO:
6190                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6191                 ret = -1;
6192                 break;
6193
6194         default:
6195                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6196                 ret = -1;
6197                 break;
6198         }
6199
6200         return ret;
6201 }
6202
6203 /* Remove UDP tunneling port */
6204 static int
6205 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6206                              struct rte_eth_udp_tunnel *udp_tunnel)
6207 {
6208         int ret = 0;
6209         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6210
6211         if (udp_tunnel == NULL)
6212                 return -EINVAL;
6213
6214         switch (udp_tunnel->prot_type) {
6215         case RTE_TUNNEL_TYPE_VXLAN:
6216                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6217                 break;
6218         case RTE_TUNNEL_TYPE_GENEVE:
6219         case RTE_TUNNEL_TYPE_TEREDO:
6220                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6221                 ret = -1;
6222                 break;
6223         default:
6224                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6225                 ret = -1;
6226                 break;
6227         }
6228
6229         return ret;
6230 }
6231
6232 /* Calculate the maximum number of contiguous PF queues that are configured */
6233 static int
6234 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6235 {
6236         struct rte_eth_dev_data *data = pf->dev_data;
6237         int i, num;
6238         struct i40e_rx_queue *rxq;
6239
6240         num = 0;
6241         for (i = 0; i < pf->lan_nb_qps; i++) {
6242                 rxq = data->rx_queues[i];
6243                 if (rxq && rxq->q_set)
6244                         num++;
6245                 else
6246                         break;
6247         }
6248
6249         return num;
6250 }
6251
6252 /* Configure RSS */
6253 static int
6254 i40e_pf_config_rss(struct i40e_pf *pf)
6255 {
6256         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6257         struct rte_eth_rss_conf rss_conf;
6258         uint32_t i, lut = 0;
6259         uint16_t j, num;
6260
6261         /*
6262          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6263          * It's necessary to calulate the actual PF queues that are configured.
6264          */
6265         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6266                 num = i40e_pf_calc_configured_queues_num(pf);
6267         else
6268                 num = pf->dev_data->nb_rx_queues;
6269
6270         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6271         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6272                         num);
6273
6274         if (num == 0) {
6275                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6276                 return -ENOTSUP;
6277         }
6278
6279         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6280                 if (j == num)
6281                         j = 0;
6282                 lut = (lut << 8) | (j & ((0x1 <<
6283                         hw->func_caps.rss_table_entry_width) - 1));
6284                 if ((i & 3) == 3)
6285                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6286         }
6287
6288         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6289         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6290                 i40e_pf_disable_rss(pf);
6291                 return 0;
6292         }
6293         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6294                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6295                 /* Random default keys */
6296                 static uint32_t rss_key_default[] = {0x6b793944,
6297                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6298                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6299                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6300
6301                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6302                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6303                                                         sizeof(uint32_t);
6304         }
6305
6306         return i40e_hw_rss_hash_set(pf, &rss_conf);
6307 }
6308
6309 static int
6310 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6311                                struct rte_eth_tunnel_filter_conf *filter)
6312 {
6313         if (pf == NULL || filter == NULL) {
6314                 PMD_DRV_LOG(ERR, "Invalid parameter");
6315                 return -EINVAL;
6316         }
6317
6318         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6319                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6320                 return -EINVAL;
6321         }
6322
6323         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6324                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6325                 return -EINVAL;
6326         }
6327
6328         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6329                 (is_zero_ether_addr(&filter->outer_mac))) {
6330                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6331                 return -EINVAL;
6332         }
6333
6334         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6335                 (is_zero_ether_addr(&filter->inner_mac))) {
6336                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6337                 return -EINVAL;
6338         }
6339
6340         return 0;
6341 }
6342
6343 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6344 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6345 static int
6346 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6347 {
6348         uint32_t val, reg;
6349         int ret = -EINVAL;
6350
6351         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6352         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6353
6354         if (len == 3) {
6355                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6356         } else if (len == 4) {
6357                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6358         } else {
6359                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6360                 return ret;
6361         }
6362
6363         if (reg != val) {
6364                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6365                                                    reg, NULL);
6366                 if (ret != 0)
6367                         return ret;
6368         } else {
6369                 ret = 0;
6370         }
6371         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6372                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6373
6374         return ret;
6375 }
6376
6377 static int
6378 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6379 {
6380         int ret = -EINVAL;
6381
6382         if (!hw || !cfg)
6383                 return -EINVAL;
6384
6385         switch (cfg->cfg_type) {
6386         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6387                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6388                 break;
6389         default:
6390                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6391                 break;
6392         }
6393
6394         return ret;
6395 }
6396
6397 static int
6398 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6399                                enum rte_filter_op filter_op,
6400                                void *arg)
6401 {
6402         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6403         int ret = I40E_ERR_PARAM;
6404
6405         switch (filter_op) {
6406         case RTE_ETH_FILTER_SET:
6407                 ret = i40e_dev_global_config_set(hw,
6408                         (struct rte_eth_global_cfg *)arg);
6409                 break;
6410         default:
6411                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6412                 break;
6413         }
6414
6415         return ret;
6416 }
6417
6418 static int
6419 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6420                           enum rte_filter_op filter_op,
6421                           void *arg)
6422 {
6423         struct rte_eth_tunnel_filter_conf *filter;
6424         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6425         int ret = I40E_SUCCESS;
6426
6427         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6428
6429         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6430                 return I40E_ERR_PARAM;
6431
6432         switch (filter_op) {
6433         case RTE_ETH_FILTER_NOP:
6434                 if (!(pf->flags & I40E_FLAG_VXLAN))
6435                         ret = I40E_NOT_SUPPORTED;
6436                 break;
6437         case RTE_ETH_FILTER_ADD:
6438                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6439                 break;
6440         case RTE_ETH_FILTER_DELETE:
6441                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6442                 break;
6443         default:
6444                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6445                 ret = I40E_ERR_PARAM;
6446                 break;
6447         }
6448
6449         return ret;
6450 }
6451
6452 static int
6453 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6454 {
6455         int ret = 0;
6456         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6457
6458         /* RSS setup */
6459         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6460                 ret = i40e_pf_config_rss(pf);
6461         else
6462                 i40e_pf_disable_rss(pf);
6463
6464         return ret;
6465 }
6466
6467 /* Get the symmetric hash enable configurations per port */
6468 static void
6469 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6470 {
6471         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6472
6473         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6474 }
6475
6476 /* Set the symmetric hash enable configurations per port */
6477 static void
6478 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6479 {
6480         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6481
6482         if (enable > 0) {
6483                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6484                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6485                                                         "been enabled");
6486                         return;
6487                 }
6488                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6489         } else {
6490                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6491                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6492                                                         "been disabled");
6493                         return;
6494                 }
6495                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6496         }
6497         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6498         I40E_WRITE_FLUSH(hw);
6499 }
6500
6501 /*
6502  * Get global configurations of hash function type and symmetric hash enable
6503  * per flow type (pctype). Note that global configuration means it affects all
6504  * the ports on the same NIC.
6505  */
6506 static int
6507 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6508                                    struct rte_eth_hash_global_conf *g_cfg)
6509 {
6510         uint32_t reg, mask = I40E_FLOW_TYPES;
6511         uint16_t i;
6512         enum i40e_filter_pctype pctype;
6513
6514         memset(g_cfg, 0, sizeof(*g_cfg));
6515         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6516         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6517                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6518         else
6519                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6520         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6521                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6522
6523         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6524                 if (!(mask & (1UL << i)))
6525                         continue;
6526                 mask &= ~(1UL << i);
6527                 /* Bit set indicats the coresponding flow type is supported */
6528                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6529                 pctype = i40e_flowtype_to_pctype(i);
6530                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6531                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6532                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6533         }
6534
6535         return 0;
6536 }
6537
6538 static int
6539 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6540 {
6541         uint32_t i;
6542         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6543
6544         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6545                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6546                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6547                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6548                                                 g_cfg->hash_func);
6549                 return -EINVAL;
6550         }
6551
6552         /*
6553          * As i40e supports less than 32 flow types, only first 32 bits need to
6554          * be checked.
6555          */
6556         mask0 = g_cfg->valid_bit_mask[0];
6557         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6558                 if (i == 0) {
6559                         /* Check if any unsupported flow type configured */
6560                         if ((mask0 | i40e_mask) ^ i40e_mask)
6561                                 goto mask_err;
6562                 } else {
6563                         if (g_cfg->valid_bit_mask[i])
6564                                 goto mask_err;
6565                 }
6566         }
6567
6568         return 0;
6569
6570 mask_err:
6571         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6572
6573         return -EINVAL;
6574 }
6575
6576 /*
6577  * Set global configurations of hash function type and symmetric hash enable
6578  * per flow type (pctype). Note any modifying global configuration will affect
6579  * all the ports on the same NIC.
6580  */
6581 static int
6582 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6583                                    struct rte_eth_hash_global_conf *g_cfg)
6584 {
6585         int ret;
6586         uint16_t i;
6587         uint32_t reg;
6588         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6589         enum i40e_filter_pctype pctype;
6590
6591         /* Check the input parameters */
6592         ret = i40e_hash_global_config_check(g_cfg);
6593         if (ret < 0)
6594                 return ret;
6595
6596         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6597                 if (!(mask0 & (1UL << i)))
6598                         continue;
6599                 mask0 &= ~(1UL << i);
6600                 pctype = i40e_flowtype_to_pctype(i);
6601                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6602                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6603                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6604         }
6605
6606         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6607         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6608                 /* Toeplitz */
6609                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6610                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6611                                                                 "Toeplitz");
6612                         goto out;
6613                 }
6614                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6615         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6616                 /* Simple XOR */
6617                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6618                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6619                                                         "Simple XOR");
6620                         goto out;
6621                 }
6622                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6623         } else
6624                 /* Use the default, and keep it as it is */
6625                 goto out;
6626
6627         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6628
6629 out:
6630         I40E_WRITE_FLUSH(hw);
6631
6632         return 0;
6633 }
6634
6635 /**
6636  * Valid input sets for hash and flow director filters per PCTYPE
6637  */
6638 static uint64_t
6639 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6640                 enum rte_filter_type filter)
6641 {
6642         uint64_t valid;
6643
6644         static const uint64_t valid_hash_inset_table[] = {
6645                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6646                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6647                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6648                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6649                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6650                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6651                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6652                         I40E_INSET_FLEX_PAYLOAD,
6653                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6654                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6655                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6656                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6657                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6658                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6659                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6660                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6661                         I40E_INSET_FLEX_PAYLOAD,
6662                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6663                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6664                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6665                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6666                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6667                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6668                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6669                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6670                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6671                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6672                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6673                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6674                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6675                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6676                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6677                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6678                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6679                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6680                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6681                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6682                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6683                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6684                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6685                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6686                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6687                         I40E_INSET_FLEX_PAYLOAD,
6688                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6689                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6690                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6691                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6692                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6693                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6694                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6695                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6696                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6697                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6698                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6699                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6700                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6701                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6702                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6703                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6704                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6705                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6706                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6707                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6708                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6709                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6710                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6711                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6712                         I40E_INSET_FLEX_PAYLOAD,
6713                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6714                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6715                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6716                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6717                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6718                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6719                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6720                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6721                         I40E_INSET_FLEX_PAYLOAD,
6722                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6723                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6724                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6725                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6726                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6727                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6728                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6729                         I40E_INSET_FLEX_PAYLOAD,
6730                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6731                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6732                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6733                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6734                         I40E_INSET_FLEX_PAYLOAD,
6735         };
6736
6737         /**
6738          * Flow director supports only fields defined in
6739          * union rte_eth_fdir_flow.
6740          */
6741         static const uint64_t valid_fdir_inset_table[] = {
6742                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6743                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6744                 I40E_INSET_FLEX_PAYLOAD,
6745                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6746                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6747                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6748                 I40E_INSET_FLEX_PAYLOAD,
6749                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6750                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6751                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6752                 I40E_INSET_FLEX_PAYLOAD,
6753                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6754                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6755                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6756                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6757                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6758                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6759                 I40E_INSET_FLEX_PAYLOAD,
6760                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6761                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6762                 I40E_INSET_FLEX_PAYLOAD,
6763                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6764                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6765                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6766                 I40E_INSET_FLEX_PAYLOAD,
6767                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6768                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6769                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6770                 I40E_INSET_FLEX_PAYLOAD,
6771                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6772                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6773                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6774                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6775                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6776                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6777                 I40E_INSET_FLEX_PAYLOAD,
6778                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6779                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6780         };
6781
6782         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6783                 return 0;
6784         if (filter == RTE_ETH_FILTER_HASH)
6785                 valid = valid_hash_inset_table[pctype];
6786         else
6787                 valid = valid_fdir_inset_table[pctype];
6788
6789         return valid;
6790 }
6791
6792 /**
6793  * Validate if the input set is allowed for a specific PCTYPE
6794  */
6795 static int
6796 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6797                 enum rte_filter_type filter, uint64_t inset)
6798 {
6799         uint64_t valid;
6800
6801         valid = i40e_get_valid_input_set(pctype, filter);
6802         if (inset & (~valid))
6803                 return -EINVAL;
6804
6805         return 0;
6806 }
6807
6808 /* default input set fields combination per pctype */
6809 static uint64_t
6810 i40e_get_default_input_set(uint16_t pctype)
6811 {
6812         static const uint64_t default_inset_table[] = {
6813                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6814                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6815                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6816                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6817                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6818                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6819                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6820                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6821                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6822                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6823                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6824                         I40E_INSET_SCTP_VT,
6825                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6826                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6827                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6828                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6829                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6830                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6831                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6832                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6833                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6834                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6835                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6836                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6837                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6838                         I40E_INSET_SCTP_VT,
6839                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6840                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6841                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6842                         I40E_INSET_LAST_ETHER_TYPE,
6843         };
6844
6845         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6846                 return 0;
6847
6848         return default_inset_table[pctype];
6849 }
6850
6851 /**
6852  * Parse the input set from index to logical bit masks
6853  */
6854 static int
6855 i40e_parse_input_set(uint64_t *inset,
6856                      enum i40e_filter_pctype pctype,
6857                      enum rte_eth_input_set_field *field,
6858                      uint16_t size)
6859 {
6860         uint16_t i, j;
6861         int ret = -EINVAL;
6862
6863         static const struct {
6864                 enum rte_eth_input_set_field field;
6865                 uint64_t inset;
6866         } inset_convert_table[] = {
6867                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6868                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6869                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6870                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6871                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6872                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6873                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6874                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6875                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6876                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6877                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6878                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6879                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6880                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6881                         I40E_INSET_IPV6_NEXT_HDR},
6882                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6883                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6884                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6885                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6886                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6887                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6888                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6889                         I40E_INSET_SCTP_VT},
6890                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6891                         I40E_INSET_TUNNEL_DMAC},
6892                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6893                         I40E_INSET_VLAN_TUNNEL},
6894                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6895                         I40E_INSET_TUNNEL_ID},
6896                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6897                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6898                         I40E_INSET_FLEX_PAYLOAD_W1},
6899                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6900                         I40E_INSET_FLEX_PAYLOAD_W2},
6901                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6902                         I40E_INSET_FLEX_PAYLOAD_W3},
6903                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6904                         I40E_INSET_FLEX_PAYLOAD_W4},
6905                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6906                         I40E_INSET_FLEX_PAYLOAD_W5},
6907                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6908                         I40E_INSET_FLEX_PAYLOAD_W6},
6909                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6910                         I40E_INSET_FLEX_PAYLOAD_W7},
6911                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6912                         I40E_INSET_FLEX_PAYLOAD_W8},
6913         };
6914
6915         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6916                 return ret;
6917
6918         /* Only one item allowed for default or all */
6919         if (size == 1) {
6920                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6921                         *inset = i40e_get_default_input_set(pctype);
6922                         return 0;
6923                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6924                         *inset = I40E_INSET_NONE;
6925                         return 0;
6926                 }
6927         }
6928
6929         for (i = 0, *inset = 0; i < size; i++) {
6930                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6931                         if (field[i] == inset_convert_table[j].field) {
6932                                 *inset |= inset_convert_table[j].inset;
6933                                 break;
6934                         }
6935                 }
6936
6937                 /* It contains unsupported input set, return immediately */
6938                 if (j == RTE_DIM(inset_convert_table))
6939                         return ret;
6940         }
6941
6942         return 0;
6943 }
6944
6945 /**
6946  * Translate the input set from bit masks to register aware bit masks
6947  * and vice versa
6948  */
6949 static uint64_t
6950 i40e_translate_input_set_reg(uint64_t input)
6951 {
6952         uint64_t val = 0;
6953         uint16_t i;
6954
6955         static const struct {
6956                 uint64_t inset;
6957                 uint64_t inset_reg;
6958         } inset_map[] = {
6959                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6960                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6961                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6962                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6963                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6964                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6965                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6966                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6967                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6968                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6969                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6970                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6971                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6972                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6973                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6974                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6975                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6976                 {I40E_INSET_TUNNEL_DMAC,
6977                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6978                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6979                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6980                 {I40E_INSET_TUNNEL_SRC_PORT,
6981                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6982                 {I40E_INSET_TUNNEL_DST_PORT,
6983                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6984                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6985                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6986                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6987                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6988                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6989                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6990                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6991                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6992                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6993         };
6994
6995         if (input == 0)
6996                 return val;
6997
6998         /* Translate input set to register aware inset */
6999         for (i = 0; i < RTE_DIM(inset_map); i++) {
7000                 if (input & inset_map[i].inset)
7001                         val |= inset_map[i].inset_reg;
7002         }
7003
7004         return val;
7005 }
7006
7007 static uint8_t
7008 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7009 {
7010         uint8_t i, idx = 0;
7011
7012         static const struct {
7013                 uint64_t inset;
7014                 uint32_t mask;
7015         } inset_mask_map[] = {
7016                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7017                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7018                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7019                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7020         };
7021
7022         if (!inset || !mask || !nb_elem)
7023                 return 0;
7024
7025         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
7026                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
7027                         mask[i] = 0;
7028                 return I40E_INSET_MASK_NUM_REG;
7029         }
7030
7031         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7032                 if (idx >= nb_elem)
7033                         break;
7034                 if (inset & inset_mask_map[i].inset) {
7035                         mask[idx] = inset_mask_map[i].mask;
7036                         idx++;
7037                 }
7038         }
7039
7040         return idx;
7041 }
7042
7043 static uint64_t
7044 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
7045                             enum i40e_filter_pctype pctype)
7046 {
7047         uint64_t reg = 0;
7048
7049         if (filter == RTE_ETH_FILTER_HASH) {
7050                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7051                 reg <<= I40E_32_BIT_WIDTH;
7052                 reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7053         } else if (filter == RTE_ETH_FILTER_FDIR) {
7054                 reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7055                 reg <<= I40E_32_BIT_WIDTH;
7056                 reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7057         }
7058
7059         return reg;
7060 }
7061
7062 static void
7063 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7064 {
7065         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7066
7067         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7068         if (reg != val)
7069                 i40e_write_rx_ctl(hw, addr, val);
7070         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7071                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7072 }
7073
7074 static int
7075 i40e_set_hash_inset_mask(struct i40e_hw *hw,
7076                          enum i40e_filter_pctype pctype,
7077                          enum rte_filter_input_set_op op,
7078                          uint32_t *mask_reg,
7079                          uint8_t num)
7080 {
7081         uint32_t reg;
7082         uint8_t i;
7083
7084         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7085                 return -EINVAL;
7086
7087         if (op == RTE_ETH_INPUT_SET_SELECT) {
7088                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7089                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7090                                              0);
7091                         if (i >= num)
7092                                 continue;
7093                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7094                                              mask_reg[i]);
7095                 }
7096         } else if (op == RTE_ETH_INPUT_SET_ADD) {
7097                 uint8_t j, count = 0;
7098
7099                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7100                         reg = i40e_read_rx_ctl(hw,
7101                                                I40E_GLQF_HASH_MSK(i, pctype));
7102                         if (reg & I40E_GLQF_HASH_MSK_MASK_MASK)
7103                                 count++;
7104                 }
7105                 if (count + num > I40E_INSET_MASK_NUM_REG)
7106                         return -EINVAL;
7107
7108                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7109                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7110                                              mask_reg[j]);
7111         }
7112
7113         return 0;
7114 }
7115
7116 static int
7117 i40e_set_fd_inset_mask(struct i40e_hw *hw,
7118                        enum i40e_filter_pctype pctype,
7119                        enum rte_filter_input_set_op op,
7120                        uint32_t *mask_reg,
7121                        uint8_t num)
7122 {
7123         uint32_t reg;
7124         uint8_t i;
7125
7126         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7127                 return -EINVAL;
7128
7129         if (op == RTE_ETH_INPUT_SET_SELECT) {
7130                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7131                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7132                                              0);
7133                         if (i >= num)
7134                                 continue;
7135                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7136                                              mask_reg[i]);
7137                 }
7138         } else if (op == RTE_ETH_INPUT_SET_ADD) {
7139                 uint8_t j, count = 0;
7140
7141                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7142                         reg = i40e_read_rx_ctl(hw,
7143                                                I40E_GLQF_FD_MSK(i, pctype));
7144                         if (reg & I40E_GLQF_FD_MSK_MASK_MASK)
7145                                 count++;
7146                 }
7147                 if (count + num > I40E_INSET_MASK_NUM_REG)
7148                         return -EINVAL;
7149
7150                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7151                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7152                                              mask_reg[j]);
7153         }
7154
7155         return 0;
7156 }
7157
7158 int
7159 i40e_filter_inset_select(struct i40e_hw *hw,
7160                          struct rte_eth_input_set_conf *conf,
7161                          enum rte_filter_type filter)
7162 {
7163         enum i40e_filter_pctype pctype;
7164         uint64_t inset_reg = 0, input_set;
7165         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
7166         uint8_t num;
7167         int ret;
7168
7169         if (!hw || !conf) {
7170                 PMD_DRV_LOG(ERR, "Invalid pointer");
7171                 return -EFAULT;
7172         }
7173
7174         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7175         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7176                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7177                             conf->flow_type);
7178                 return -EINVAL;
7179         }
7180         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
7181                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7182                 return -EINVAL;
7183         }
7184
7185         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7186                                    conf->inset_size);
7187         if (ret) {
7188                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7189                 return -EINVAL;
7190         }
7191         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
7192                 PMD_DRV_LOG(ERR, "Invalid input set");
7193                 return -EINVAL;
7194         }
7195
7196         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7197                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7198         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7199                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7200                 return -EINVAL;
7201         }
7202         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7203                                            I40E_INSET_MASK_NUM_REG);
7204         inset_reg |= i40e_translate_input_set_reg(input_set);
7205
7206         if (filter == RTE_ETH_FILTER_HASH) {
7207                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7208                                                num);
7209                 if (ret)
7210                         return -EINVAL;
7211
7212                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7213                                       (uint32_t)(inset_reg & UINT32_MAX));
7214                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7215                                      (uint32_t)((inset_reg >>
7216                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7217         } else if (filter == RTE_ETH_FILTER_FDIR) {
7218                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7219                                              num);
7220                 if (ret)
7221                         return -EINVAL;
7222
7223                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7224                                       (uint32_t)(inset_reg & UINT32_MAX));
7225                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7226                                      (uint32_t)((inset_reg >>
7227                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7228         } else {
7229                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7230                 return -EINVAL;
7231         }
7232         I40E_WRITE_FLUSH(hw);
7233
7234         return 0;
7235 }
7236
7237 static int
7238 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7239 {
7240         int ret = 0;
7241
7242         if (!hw || !info) {
7243                 PMD_DRV_LOG(ERR, "Invalid pointer");
7244                 return -EFAULT;
7245         }
7246
7247         switch (info->info_type) {
7248         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7249                 i40e_get_symmetric_hash_enable_per_port(hw,
7250                                         &(info->info.enable));
7251                 break;
7252         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7253                 ret = i40e_get_hash_filter_global_config(hw,
7254                                 &(info->info.global_conf));
7255                 break;
7256         default:
7257                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7258                                                         info->info_type);
7259                 ret = -EINVAL;
7260                 break;
7261         }
7262
7263         return ret;
7264 }
7265
7266 static int
7267 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7268 {
7269         int ret = 0;
7270
7271         if (!hw || !info) {
7272                 PMD_DRV_LOG(ERR, "Invalid pointer");
7273                 return -EFAULT;
7274         }
7275
7276         switch (info->info_type) {
7277         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7278                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7279                 break;
7280         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7281                 ret = i40e_set_hash_filter_global_config(hw,
7282                                 &(info->info.global_conf));
7283                 break;
7284         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7285                 ret = i40e_filter_inset_select(hw,
7286                                                &(info->info.input_set_conf),
7287                                                RTE_ETH_FILTER_HASH);
7288                 break;
7289
7290         default:
7291                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7292                                                         info->info_type);
7293                 ret = -EINVAL;
7294                 break;
7295         }
7296
7297         return ret;
7298 }
7299
7300 /* Operations for hash function */
7301 static int
7302 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7303                       enum rte_filter_op filter_op,
7304                       void *arg)
7305 {
7306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7307         int ret = 0;
7308
7309         switch (filter_op) {
7310         case RTE_ETH_FILTER_NOP:
7311                 break;
7312         case RTE_ETH_FILTER_GET:
7313                 ret = i40e_hash_filter_get(hw,
7314                         (struct rte_eth_hash_filter_info *)arg);
7315                 break;
7316         case RTE_ETH_FILTER_SET:
7317                 ret = i40e_hash_filter_set(hw,
7318                         (struct rte_eth_hash_filter_info *)arg);
7319                 break;
7320         default:
7321                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7322                                                                 filter_op);
7323                 ret = -ENOTSUP;
7324                 break;
7325         }
7326
7327         return ret;
7328 }
7329
7330 /*
7331  * Configure ethertype filter, which can director packet by filtering
7332  * with mac address and ether_type or only ether_type
7333  */
7334 static int
7335 i40e_ethertype_filter_set(struct i40e_pf *pf,
7336                         struct rte_eth_ethertype_filter *filter,
7337                         bool add)
7338 {
7339         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7340         struct i40e_control_filter_stats stats;
7341         uint16_t flags = 0;
7342         int ret;
7343
7344         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7345                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7346                 return -EINVAL;
7347         }
7348         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7349                 filter->ether_type == ETHER_TYPE_IPv6) {
7350                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7351                         " control packet filter.", filter->ether_type);
7352                 return -EINVAL;
7353         }
7354         if (filter->ether_type == ETHER_TYPE_VLAN)
7355                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7356                         " not supported.");
7357
7358         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7359                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7360         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7361                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7362         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7363
7364         memset(&stats, 0, sizeof(stats));
7365         ret = i40e_aq_add_rem_control_packet_filter(hw,
7366                         filter->mac_addr.addr_bytes,
7367                         filter->ether_type, flags,
7368                         pf->main_vsi->seid,
7369                         filter->queue, add, &stats, NULL);
7370
7371         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7372                          " mac_etype_used = %u, etype_used = %u,"
7373                          " mac_etype_free = %u, etype_free = %u\n",
7374                          ret, stats.mac_etype_used, stats.etype_used,
7375                          stats.mac_etype_free, stats.etype_free);
7376         if (ret < 0)
7377                 return -ENOSYS;
7378         return 0;
7379 }
7380
7381 /*
7382  * Handle operations for ethertype filter.
7383  */
7384 static int
7385 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7386                                 enum rte_filter_op filter_op,
7387                                 void *arg)
7388 {
7389         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7390         int ret = 0;
7391
7392         if (filter_op == RTE_ETH_FILTER_NOP)
7393                 return ret;
7394
7395         if (arg == NULL) {
7396                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7397                             filter_op);
7398                 return -EINVAL;
7399         }
7400
7401         switch (filter_op) {
7402         case RTE_ETH_FILTER_ADD:
7403                 ret = i40e_ethertype_filter_set(pf,
7404                         (struct rte_eth_ethertype_filter *)arg,
7405                         TRUE);
7406                 break;
7407         case RTE_ETH_FILTER_DELETE:
7408                 ret = i40e_ethertype_filter_set(pf,
7409                         (struct rte_eth_ethertype_filter *)arg,
7410                         FALSE);
7411                 break;
7412         default:
7413                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7414                 ret = -ENOSYS;
7415                 break;
7416         }
7417         return ret;
7418 }
7419
7420 static int
7421 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7422                      enum rte_filter_type filter_type,
7423                      enum rte_filter_op filter_op,
7424                      void *arg)
7425 {
7426         int ret = 0;
7427
7428         if (dev == NULL)
7429                 return -EINVAL;
7430
7431         switch (filter_type) {
7432         case RTE_ETH_FILTER_NONE:
7433                 /* For global configuration */
7434                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7435                 break;
7436         case RTE_ETH_FILTER_HASH:
7437                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7438                 break;
7439         case RTE_ETH_FILTER_MACVLAN:
7440                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7441                 break;
7442         case RTE_ETH_FILTER_ETHERTYPE:
7443                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7444                 break;
7445         case RTE_ETH_FILTER_TUNNEL:
7446                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7447                 break;
7448         case RTE_ETH_FILTER_FDIR:
7449                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7450                 break;
7451         default:
7452                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7453                                                         filter_type);
7454                 ret = -EINVAL;
7455                 break;
7456         }
7457
7458         return ret;
7459 }
7460
7461 /*
7462  * Check and enable Extended Tag.
7463  * Enabling Extended Tag is important for 40G performance.
7464  */
7465 static void
7466 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7467 {
7468         uint32_t buf = 0;
7469         int ret;
7470
7471         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7472                                       PCI_DEV_CAP_REG);
7473         if (ret < 0) {
7474                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7475                             PCI_DEV_CAP_REG);
7476                 return;
7477         }
7478         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7479                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7480                 return;
7481         }
7482
7483         buf = 0;
7484         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7485                                       PCI_DEV_CTRL_REG);
7486         if (ret < 0) {
7487                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7488                             PCI_DEV_CTRL_REG);
7489                 return;
7490         }
7491         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7492                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7493                 return;
7494         }
7495         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7496         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7497                                        PCI_DEV_CTRL_REG);
7498         if (ret < 0) {
7499                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7500                             PCI_DEV_CTRL_REG);
7501                 return;
7502         }
7503 }
7504
7505 /*
7506  * As some registers wouldn't be reset unless a global hardware reset,
7507  * hardware initialization is needed to put those registers into an
7508  * expected initial state.
7509  */
7510 static void
7511 i40e_hw_init(struct rte_eth_dev *dev)
7512 {
7513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7514
7515         i40e_enable_extended_tag(dev);
7516
7517         /* clear the PF Queue Filter control register */
7518         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7519
7520         /* Disable symmetric hash per port */
7521         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7522 }
7523
7524 enum i40e_filter_pctype
7525 i40e_flowtype_to_pctype(uint16_t flow_type)
7526 {
7527         static const enum i40e_filter_pctype pctype_table[] = {
7528                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7529                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7530                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7531                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7532                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7533                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7534                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7535                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7536                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7537                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7538                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7539                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7540                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7541                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7542                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7543                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7544                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7545                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7546                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7547         };
7548
7549         return pctype_table[flow_type];
7550 }
7551
7552 uint16_t
7553 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7554 {
7555         static const uint16_t flowtype_table[] = {
7556                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7557                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7558                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7559                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7560                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7561                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7562                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7563                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7564                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7565                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7566                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7567                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7568                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7569                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7570                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7571                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7572                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7573                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7574                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7575         };
7576
7577         return flowtype_table[pctype];
7578 }
7579
7580 /*
7581  * On X710, performance number is far from the expectation on recent firmware
7582  * versions; on XL710, performance number is also far from the expectation on
7583  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7584  * mode is enabled and port MAC address is equal to the packet destination MAC
7585  * address. The fix for this issue may not be integrated in the following
7586  * firmware version. So the workaround in software driver is needed. It needs
7587  * to modify the initial values of 3 internal only registers for both X710 and
7588  * XL710. Note that the values for X710 or XL710 could be different, and the
7589  * workaround can be removed when it is fixed in firmware in the future.
7590  */
7591
7592 /* For both X710 and XL710 */
7593 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7594 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7595
7596 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7597 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7598
7599 /* For X710 */
7600 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7601 /* For XL710 */
7602 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7603 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7604
7605 static void
7606 i40e_configure_registers(struct i40e_hw *hw)
7607 {
7608         static struct {
7609                 uint32_t addr;
7610                 uint64_t val;
7611         } reg_table[] = {
7612                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7613                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7614                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7615         };
7616         uint64_t reg;
7617         uint32_t i;
7618         int ret;
7619
7620         for (i = 0; i < RTE_DIM(reg_table); i++) {
7621                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7622                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7623                                 reg_table[i].val =
7624                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7625                         else /* For X710 */
7626                                 reg_table[i].val =
7627                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7628                 }
7629
7630                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7631                                                         &reg, NULL);
7632                 if (ret < 0) {
7633                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7634                                                         reg_table[i].addr);
7635                         break;
7636                 }
7637                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7638                                                 reg_table[i].addr, reg);
7639                 if (reg == reg_table[i].val)
7640                         continue;
7641
7642                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7643                                                 reg_table[i].val, NULL);
7644                 if (ret < 0) {
7645                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7646                                 "address of 0x%"PRIx32, reg_table[i].val,
7647                                                         reg_table[i].addr);
7648                         break;
7649                 }
7650                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7651                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7652         }
7653 }
7654
7655 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7656 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7657 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7658 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7659 static int
7660 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7661 {
7662         uint32_t reg;
7663         int ret;
7664
7665         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7666                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7667                 return -EINVAL;
7668         }
7669
7670         /* Configure for double VLAN RX stripping */
7671         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7672         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7673                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7674                 ret = i40e_aq_debug_write_register(hw,
7675                                                    I40E_VSI_TSR(vsi->vsi_id),
7676                                                    reg, NULL);
7677                 if (ret < 0) {
7678                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7679                                     vsi->vsi_id);
7680                         return I40E_ERR_CONFIG;
7681                 }
7682         }
7683
7684         /* Configure for double VLAN TX insertion */
7685         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7686         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7687                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7688                 ret = i40e_aq_debug_write_register(hw,
7689                                                    I40E_VSI_L2TAGSTXVALID(
7690                                                    vsi->vsi_id), reg, NULL);
7691                 if (ret < 0) {
7692                         PMD_DRV_LOG(ERR, "Failed to update "
7693                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7694                         return I40E_ERR_CONFIG;
7695                 }
7696         }
7697
7698         return 0;
7699 }
7700
7701 /**
7702  * i40e_aq_add_mirror_rule
7703  * @hw: pointer to the hardware structure
7704  * @seid: VEB seid to add mirror rule to
7705  * @dst_id: destination vsi seid
7706  * @entries: Buffer which contains the entities to be mirrored
7707  * @count: number of entities contained in the buffer
7708  * @rule_id:the rule_id of the rule to be added
7709  *
7710  * Add a mirror rule for a given veb.
7711  *
7712  **/
7713 static enum i40e_status_code
7714 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7715                         uint16_t seid, uint16_t dst_id,
7716                         uint16_t rule_type, uint16_t *entries,
7717                         uint16_t count, uint16_t *rule_id)
7718 {
7719         struct i40e_aq_desc desc;
7720         struct i40e_aqc_add_delete_mirror_rule cmd;
7721         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7722                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7723                 &desc.params.raw;
7724         uint16_t buff_len;
7725         enum i40e_status_code status;
7726
7727         i40e_fill_default_direct_cmd_desc(&desc,
7728                                           i40e_aqc_opc_add_mirror_rule);
7729         memset(&cmd, 0, sizeof(cmd));
7730
7731         buff_len = sizeof(uint16_t) * count;
7732         desc.datalen = rte_cpu_to_le_16(buff_len);
7733         if (buff_len > 0)
7734                 desc.flags |= rte_cpu_to_le_16(
7735                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7736         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7737                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7738         cmd.num_entries = rte_cpu_to_le_16(count);
7739         cmd.seid = rte_cpu_to_le_16(seid);
7740         cmd.destination = rte_cpu_to_le_16(dst_id);
7741
7742         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7743         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7744         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7745                          "rule_id = %u"
7746                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7747                          hw->aq.asq_last_status, resp->rule_id,
7748                          resp->mirror_rules_used, resp->mirror_rules_free);
7749         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7750
7751         return status;
7752 }
7753
7754 /**
7755  * i40e_aq_del_mirror_rule
7756  * @hw: pointer to the hardware structure
7757  * @seid: VEB seid to add mirror rule to
7758  * @entries: Buffer which contains the entities to be mirrored
7759  * @count: number of entities contained in the buffer
7760  * @rule_id:the rule_id of the rule to be delete
7761  *
7762  * Delete a mirror rule for a given veb.
7763  *
7764  **/
7765 static enum i40e_status_code
7766 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7767                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7768                 uint16_t count, uint16_t rule_id)
7769 {
7770         struct i40e_aq_desc desc;
7771         struct i40e_aqc_add_delete_mirror_rule cmd;
7772         uint16_t buff_len = 0;
7773         enum i40e_status_code status;
7774         void *buff = NULL;
7775
7776         i40e_fill_default_direct_cmd_desc(&desc,
7777                                           i40e_aqc_opc_delete_mirror_rule);
7778         memset(&cmd, 0, sizeof(cmd));
7779         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7780                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7781                                                           I40E_AQ_FLAG_RD));
7782                 cmd.num_entries = count;
7783                 buff_len = sizeof(uint16_t) * count;
7784                 desc.datalen = rte_cpu_to_le_16(buff_len);
7785                 buff = (void *)entries;
7786         } else
7787                 /* rule id is filled in destination field for deleting mirror rule */
7788                 cmd.destination = rte_cpu_to_le_16(rule_id);
7789
7790         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7791                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7792         cmd.seid = rte_cpu_to_le_16(seid);
7793
7794         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7795         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7796
7797         return status;
7798 }
7799
7800 /**
7801  * i40e_mirror_rule_set
7802  * @dev: pointer to the hardware structure
7803  * @mirror_conf: mirror rule info
7804  * @sw_id: mirror rule's sw_id
7805  * @on: enable/disable
7806  *
7807  * set a mirror rule.
7808  *
7809  **/
7810 static int
7811 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7812                         struct rte_eth_mirror_conf *mirror_conf,
7813                         uint8_t sw_id, uint8_t on)
7814 {
7815         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7817         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7818         struct i40e_mirror_rule *parent = NULL;
7819         uint16_t seid, dst_seid, rule_id;
7820         uint16_t i, j = 0;
7821         int ret;
7822
7823         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7824
7825         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7826                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7827                         " without veb or vfs.");
7828                 return -ENOSYS;
7829         }
7830         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7831                 PMD_DRV_LOG(ERR, "mirror table is full.");
7832                 return -ENOSPC;
7833         }
7834         if (mirror_conf->dst_pool > pf->vf_num) {
7835                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7836                                  mirror_conf->dst_pool);
7837                 return -EINVAL;
7838         }
7839
7840         seid = pf->main_vsi->veb->seid;
7841
7842         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7843                 if (sw_id <= it->index) {
7844                         mirr_rule = it;
7845                         break;
7846                 }
7847                 parent = it;
7848         }
7849         if (mirr_rule && sw_id == mirr_rule->index) {
7850                 if (on) {
7851                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7852                         return -EEXIST;
7853                 } else {
7854                         ret = i40e_aq_del_mirror_rule(hw, seid,
7855                                         mirr_rule->rule_type,
7856                                         mirr_rule->entries,
7857                                         mirr_rule->num_entries, mirr_rule->id);
7858                         if (ret < 0) {
7859                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7860                                                    " ret = %d, aq_err = %d.",
7861                                                    ret, hw->aq.asq_last_status);
7862                                 return -ENOSYS;
7863                         }
7864                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7865                         rte_free(mirr_rule);
7866                         pf->nb_mirror_rule--;
7867                         return 0;
7868                 }
7869         } else if (!on) {
7870                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7871                 return -ENOENT;
7872         }
7873
7874         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7875                                 sizeof(struct i40e_mirror_rule) , 0);
7876         if (!mirr_rule) {
7877                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7878                 return I40E_ERR_NO_MEMORY;
7879         }
7880         switch (mirror_conf->rule_type) {
7881         case ETH_MIRROR_VLAN:
7882                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7883                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7884                                 mirr_rule->entries[j] =
7885                                         mirror_conf->vlan.vlan_id[i];
7886                                 j++;
7887                         }
7888                 }
7889                 if (j == 0) {
7890                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7891                         rte_free(mirr_rule);
7892                         return -EINVAL;
7893                 }
7894                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7895                 break;
7896         case ETH_MIRROR_VIRTUAL_POOL_UP:
7897         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7898                 /* check if the specified pool bit is out of range */
7899                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7900                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7901                         rte_free(mirr_rule);
7902                         return -EINVAL;
7903                 }
7904                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7905                         if (mirror_conf->pool_mask & (1ULL << i)) {
7906                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7907                                 j++;
7908                         }
7909                 }
7910                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7911                         /* add pf vsi to entries */
7912                         mirr_rule->entries[j] = pf->main_vsi_seid;
7913                         j++;
7914                 }
7915                 if (j == 0) {
7916                         PMD_DRV_LOG(ERR, "pool is not specified.");
7917                         rte_free(mirr_rule);
7918                         return -EINVAL;
7919                 }
7920                 /* egress and ingress in aq commands means from switch but not port */
7921                 mirr_rule->rule_type =
7922                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7923                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7924                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7925                 break;
7926         case ETH_MIRROR_UPLINK_PORT:
7927                 /* egress and ingress in aq commands means from switch but not port*/
7928                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7929                 break;
7930         case ETH_MIRROR_DOWNLINK_PORT:
7931                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7932                 break;
7933         default:
7934                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7935                         mirror_conf->rule_type);
7936                 rte_free(mirr_rule);
7937                 return -EINVAL;
7938         }
7939
7940         /* If the dst_pool is equal to vf_num, consider it as PF */
7941         if (mirror_conf->dst_pool == pf->vf_num)
7942                 dst_seid = pf->main_vsi_seid;
7943         else
7944                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7945
7946         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7947                                       mirr_rule->rule_type, mirr_rule->entries,
7948                                       j, &rule_id);
7949         if (ret < 0) {
7950                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7951                                    " ret = %d, aq_err = %d.",
7952                                    ret, hw->aq.asq_last_status);
7953                 rte_free(mirr_rule);
7954                 return -ENOSYS;
7955         }
7956
7957         mirr_rule->index = sw_id;
7958         mirr_rule->num_entries = j;
7959         mirr_rule->id = rule_id;
7960         mirr_rule->dst_vsi_seid = dst_seid;
7961
7962         if (parent)
7963                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7964         else
7965                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7966
7967         pf->nb_mirror_rule++;
7968         return 0;
7969 }
7970
7971 /**
7972  * i40e_mirror_rule_reset
7973  * @dev: pointer to the device
7974  * @sw_id: mirror rule's sw_id
7975  *
7976  * reset a mirror rule.
7977  *
7978  **/
7979 static int
7980 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7981 {
7982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7984         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7985         uint16_t seid;
7986         int ret;
7987
7988         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7989
7990         seid = pf->main_vsi->veb->seid;
7991
7992         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7993                 if (sw_id == it->index) {
7994                         mirr_rule = it;
7995                         break;
7996                 }
7997         }
7998         if (mirr_rule) {
7999                 ret = i40e_aq_del_mirror_rule(hw, seid,
8000                                 mirr_rule->rule_type,
8001                                 mirr_rule->entries,
8002                                 mirr_rule->num_entries, mirr_rule->id);
8003                 if (ret < 0) {
8004                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8005                                            " status = %d, aq_err = %d.",
8006                                            ret, hw->aq.asq_last_status);
8007                         return -ENOSYS;
8008                 }
8009                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8010                 rte_free(mirr_rule);
8011                 pf->nb_mirror_rule--;
8012         } else {
8013                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8014                 return -ENOENT;
8015         }
8016         return 0;
8017 }
8018
8019 static uint64_t
8020 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8021 {
8022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8023         uint64_t systim_cycles;
8024
8025         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8026         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8027                         << 32;
8028
8029         return systim_cycles;
8030 }
8031
8032 static uint64_t
8033 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8034 {
8035         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8036         uint64_t rx_tstamp;
8037
8038         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8039         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8040                         << 32;
8041
8042         return rx_tstamp;
8043 }
8044
8045 static uint64_t
8046 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8047 {
8048         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8049         uint64_t tx_tstamp;
8050
8051         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8052         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8053                         << 32;
8054
8055         return tx_tstamp;
8056 }
8057
8058 static void
8059 i40e_start_timecounters(struct rte_eth_dev *dev)
8060 {
8061         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8062         struct i40e_adapter *adapter =
8063                         (struct i40e_adapter *)dev->data->dev_private;
8064         struct rte_eth_link link;
8065         uint32_t tsync_inc_l;
8066         uint32_t tsync_inc_h;
8067
8068         /* Get current link speed. */
8069         memset(&link, 0, sizeof(link));
8070         i40e_dev_link_update(dev, 1);
8071         rte_i40e_dev_atomic_read_link_status(dev, &link);
8072
8073         switch (link.link_speed) {
8074         case ETH_LINK_SPEED_40G:
8075                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8076                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8077                 break;
8078         case ETH_LINK_SPEED_10G:
8079                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8080                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8081                 break;
8082         case ETH_LINK_SPEED_1000:
8083                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8084                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8085                 break;
8086         default:
8087                 tsync_inc_l = 0x0;
8088                 tsync_inc_h = 0x0;
8089         }
8090
8091         /* Set the timesync increment value. */
8092         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8093         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8094
8095         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8096         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8097         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8098
8099         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8100         adapter->systime_tc.cc_shift = 0;
8101         adapter->systime_tc.nsec_mask = 0;
8102
8103         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8104         adapter->rx_tstamp_tc.cc_shift = 0;
8105         adapter->rx_tstamp_tc.nsec_mask = 0;
8106
8107         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8108         adapter->tx_tstamp_tc.cc_shift = 0;
8109         adapter->tx_tstamp_tc.nsec_mask = 0;
8110 }
8111
8112 static int
8113 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8114 {
8115         struct i40e_adapter *adapter =
8116                         (struct i40e_adapter *)dev->data->dev_private;
8117
8118         adapter->systime_tc.nsec += delta;
8119         adapter->rx_tstamp_tc.nsec += delta;
8120         adapter->tx_tstamp_tc.nsec += delta;
8121
8122         return 0;
8123 }
8124
8125 static int
8126 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8127 {
8128         uint64_t ns;
8129         struct i40e_adapter *adapter =
8130                         (struct i40e_adapter *)dev->data->dev_private;
8131
8132         ns = rte_timespec_to_ns(ts);
8133
8134         /* Set the timecounters to a new value. */
8135         adapter->systime_tc.nsec = ns;
8136         adapter->rx_tstamp_tc.nsec = ns;
8137         adapter->tx_tstamp_tc.nsec = ns;
8138
8139         return 0;
8140 }
8141
8142 static int
8143 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8144 {
8145         uint64_t ns, systime_cycles;
8146         struct i40e_adapter *adapter =
8147                         (struct i40e_adapter *)dev->data->dev_private;
8148
8149         systime_cycles = i40e_read_systime_cyclecounter(dev);
8150         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8151         *ts = rte_ns_to_timespec(ns);
8152
8153         return 0;
8154 }
8155
8156 static int
8157 i40e_timesync_enable(struct rte_eth_dev *dev)
8158 {
8159         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8160         uint32_t tsync_ctl_l;
8161         uint32_t tsync_ctl_h;
8162
8163         /* Stop the timesync system time. */
8164         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8165         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8166         /* Reset the timesync system time value. */
8167         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8168         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8169
8170         i40e_start_timecounters(dev);
8171
8172         /* Clear timesync registers. */
8173         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8174         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8175         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8176         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8177         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8178         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8179
8180         /* Enable timestamping of PTP packets. */
8181         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8182         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8183
8184         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8185         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8186         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8187
8188         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8189         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8190
8191         return 0;
8192 }
8193
8194 static int
8195 i40e_timesync_disable(struct rte_eth_dev *dev)
8196 {
8197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8198         uint32_t tsync_ctl_l;
8199         uint32_t tsync_ctl_h;
8200
8201         /* Disable timestamping of transmitted PTP packets. */
8202         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8203         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8204
8205         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8206         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8207
8208         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8209         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8210
8211         /* Reset the timesync increment value. */
8212         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8213         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8214
8215         return 0;
8216 }
8217
8218 static int
8219 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8220                                 struct timespec *timestamp, uint32_t flags)
8221 {
8222         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8223         struct i40e_adapter *adapter =
8224                 (struct i40e_adapter *)dev->data->dev_private;
8225
8226         uint32_t sync_status;
8227         uint32_t index = flags & 0x03;
8228         uint64_t rx_tstamp_cycles;
8229         uint64_t ns;
8230
8231         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8232         if ((sync_status & (1 << index)) == 0)
8233                 return -EINVAL;
8234
8235         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8236         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8237         *timestamp = rte_ns_to_timespec(ns);
8238
8239         return 0;
8240 }
8241
8242 static int
8243 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8244                                 struct timespec *timestamp)
8245 {
8246         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8247         struct i40e_adapter *adapter =
8248                 (struct i40e_adapter *)dev->data->dev_private;
8249
8250         uint32_t sync_status;
8251         uint64_t tx_tstamp_cycles;
8252         uint64_t ns;
8253
8254         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8255         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8256                 return -EINVAL;
8257
8258         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8259         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8260         *timestamp = rte_ns_to_timespec(ns);
8261
8262         return 0;
8263 }
8264
8265 /*
8266  * i40e_parse_dcb_configure - parse dcb configure from user
8267  * @dev: the device being configured
8268  * @dcb_cfg: pointer of the result of parse
8269  * @*tc_map: bit map of enabled traffic classes
8270  *
8271  * Returns 0 on success, negative value on failure
8272  */
8273 static int
8274 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8275                          struct i40e_dcbx_config *dcb_cfg,
8276                          uint8_t *tc_map)
8277 {
8278         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8279         uint8_t i, tc_bw, bw_lf;
8280
8281         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8282
8283         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8284         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8285                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8286                 return -EINVAL;
8287         }
8288
8289         /* assume each tc has the same bw */
8290         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8291         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8292                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8293         /* to ensure the sum of tcbw is equal to 100 */
8294         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8295         for (i = 0; i < bw_lf; i++)
8296                 dcb_cfg->etscfg.tcbwtable[i]++;
8297
8298         /* assume each tc has the same Transmission Selection Algorithm */
8299         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8300                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8301
8302         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8303                 dcb_cfg->etscfg.prioritytable[i] =
8304                                 dcb_rx_conf->dcb_tc[i];
8305
8306         /* FW needs one App to configure HW */
8307         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8308         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8309         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8310         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8311
8312         if (dcb_rx_conf->nb_tcs == 0)
8313                 *tc_map = 1; /* tc0 only */
8314         else
8315                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8316
8317         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8318                 dcb_cfg->pfc.willing = 0;
8319                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8320                 dcb_cfg->pfc.pfcenable = *tc_map;
8321         }
8322         return 0;
8323 }
8324
8325
8326 static enum i40e_status_code
8327 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8328                               struct i40e_aqc_vsi_properties_data *info,
8329                               uint8_t enabled_tcmap)
8330 {
8331         enum i40e_status_code ret;
8332         int i, total_tc = 0;
8333         uint16_t qpnum_per_tc, bsf, qp_idx;
8334         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8335         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8336         uint16_t used_queues;
8337
8338         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8339         if (ret != I40E_SUCCESS)
8340                 return ret;
8341
8342         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8343                 if (enabled_tcmap & (1 << i))
8344                         total_tc++;
8345         }
8346         if (total_tc == 0)
8347                 total_tc = 1;
8348         vsi->enabled_tc = enabled_tcmap;
8349
8350         /* different VSI has different queues assigned */
8351         if (vsi->type == I40E_VSI_MAIN)
8352                 used_queues = dev_data->nb_rx_queues -
8353                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8354         else if (vsi->type == I40E_VSI_VMDQ2)
8355                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8356         else {
8357                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8358                 return I40E_ERR_NO_AVAILABLE_VSI;
8359         }
8360
8361         qpnum_per_tc = used_queues / total_tc;
8362         /* Number of queues per enabled TC */
8363         if (qpnum_per_tc == 0) {
8364                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8365                 return I40E_ERR_INVALID_QP_ID;
8366         }
8367         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8368                                 I40E_MAX_Q_PER_TC);
8369         bsf = rte_bsf32(qpnum_per_tc);
8370
8371         /**
8372          * Configure TC and queue mapping parameters, for enabled TC,
8373          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8374          * default queue will serve it.
8375          */
8376         qp_idx = 0;
8377         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8378                 if (vsi->enabled_tc & (1 << i)) {
8379                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8380                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8381                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8382                         qp_idx += qpnum_per_tc;
8383                 } else
8384                         info->tc_mapping[i] = 0;
8385         }
8386
8387         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8388         if (vsi->type == I40E_VSI_SRIOV) {
8389                 info->mapping_flags |=
8390                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8391                 for (i = 0; i < vsi->nb_qps; i++)
8392                         info->queue_mapping[i] =
8393                                 rte_cpu_to_le_16(vsi->base_queue + i);
8394         } else {
8395                 info->mapping_flags |=
8396                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8397                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8398         }
8399         info->valid_sections |=
8400                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8401
8402         return I40E_SUCCESS;
8403 }
8404
8405 /*
8406  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8407  * @veb: VEB to be configured
8408  * @tc_map: enabled TC bitmap
8409  *
8410  * Returns 0 on success, negative value on failure
8411  */
8412 static enum i40e_status_code
8413 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8414 {
8415         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8416         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8417         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8418         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8419         enum i40e_status_code ret = I40E_SUCCESS;
8420         int i;
8421         uint32_t bw_max;
8422
8423         /* Check if enabled_tc is same as existing or new TCs */
8424         if (veb->enabled_tc == tc_map)
8425                 return ret;
8426
8427         /* configure tc bandwidth */
8428         memset(&veb_bw, 0, sizeof(veb_bw));
8429         veb_bw.tc_valid_bits = tc_map;
8430         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8431         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8432                 if (tc_map & BIT_ULL(i))
8433                         veb_bw.tc_bw_share_credits[i] = 1;
8434         }
8435         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8436                                                    &veb_bw, NULL);
8437         if (ret) {
8438                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8439                                   " per TC failed = %d",
8440                                   hw->aq.asq_last_status);
8441                 return ret;
8442         }
8443
8444         memset(&ets_query, 0, sizeof(ets_query));
8445         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8446                                                    &ets_query, NULL);
8447         if (ret != I40E_SUCCESS) {
8448                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8449                                  " configuration %u", hw->aq.asq_last_status);
8450                 return ret;
8451         }
8452         memset(&bw_query, 0, sizeof(bw_query));
8453         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8454                                                   &bw_query, NULL);
8455         if (ret != I40E_SUCCESS) {
8456                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8457                                  " configuration %u", hw->aq.asq_last_status);
8458                 return ret;
8459         }
8460
8461         /* store and print out BW info */
8462         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8463         veb->bw_info.bw_max = ets_query.tc_bw_max;
8464         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8465         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8466         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8467                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8468                      I40E_16_BIT_WIDTH);
8469         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8470                 veb->bw_info.bw_ets_share_credits[i] =
8471                                 bw_query.tc_bw_share_credits[i];
8472                 veb->bw_info.bw_ets_credits[i] =
8473                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8474                 /* 4 bits per TC, 4th bit is reserved */
8475                 veb->bw_info.bw_ets_max[i] =
8476                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8477                                   RTE_LEN2MASK(3, uint8_t));
8478                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8479                             veb->bw_info.bw_ets_share_credits[i]);
8480                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8481                             veb->bw_info.bw_ets_credits[i]);
8482                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8483                             veb->bw_info.bw_ets_max[i]);
8484         }
8485
8486         veb->enabled_tc = tc_map;
8487
8488         return ret;
8489 }
8490
8491
8492 /*
8493  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8494  * @vsi: VSI to be configured
8495  * @tc_map: enabled TC bitmap
8496  *
8497  * Returns 0 on success, negative value on failure
8498  */
8499 static enum i40e_status_code
8500 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8501 {
8502         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8503         struct i40e_vsi_context ctxt;
8504         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8505         enum i40e_status_code ret = I40E_SUCCESS;
8506         int i;
8507
8508         /* Check if enabled_tc is same as existing or new TCs */
8509         if (vsi->enabled_tc == tc_map)
8510                 return ret;
8511
8512         /* configure tc bandwidth */
8513         memset(&bw_data, 0, sizeof(bw_data));
8514         bw_data.tc_valid_bits = tc_map;
8515         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8516         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8517                 if (tc_map & BIT_ULL(i))
8518                         bw_data.tc_bw_credits[i] = 1;
8519         }
8520         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8521         if (ret) {
8522                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8523                         " per TC failed = %d",
8524                         hw->aq.asq_last_status);
8525                 goto out;
8526         }
8527         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8528                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8529
8530         /* Update Queue Pairs Mapping for currently enabled UPs */
8531         ctxt.seid = vsi->seid;
8532         ctxt.pf_num = hw->pf_id;
8533         ctxt.vf_num = 0;
8534         ctxt.uplink_seid = vsi->uplink_seid;
8535         ctxt.info = vsi->info;
8536         i40e_get_cap(hw);
8537         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8538         if (ret)
8539                 goto out;
8540
8541         /* Update the VSI after updating the VSI queue-mapping information */
8542         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8543         if (ret) {
8544                 PMD_INIT_LOG(ERR, "Failed to configure "
8545                             "TC queue mapping = %d",
8546                             hw->aq.asq_last_status);
8547                 goto out;
8548         }
8549         /* update the local VSI info with updated queue map */
8550         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8551                                         sizeof(vsi->info.tc_mapping));
8552         (void)rte_memcpy(&vsi->info.queue_mapping,
8553                         &ctxt.info.queue_mapping,
8554                 sizeof(vsi->info.queue_mapping));
8555         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8556         vsi->info.valid_sections = 0;
8557
8558         /* query and update current VSI BW information */
8559         ret = i40e_vsi_get_bw_config(vsi);
8560         if (ret) {
8561                 PMD_INIT_LOG(ERR,
8562                          "Failed updating vsi bw info, err %s aq_err %s",
8563                          i40e_stat_str(hw, ret),
8564                          i40e_aq_str(hw, hw->aq.asq_last_status));
8565                 goto out;
8566         }
8567
8568         vsi->enabled_tc = tc_map;
8569
8570 out:
8571         return ret;
8572 }
8573
8574 /*
8575  * i40e_dcb_hw_configure - program the dcb setting to hw
8576  * @pf: pf the configuration is taken on
8577  * @new_cfg: new configuration
8578  * @tc_map: enabled TC bitmap
8579  *
8580  * Returns 0 on success, negative value on failure
8581  */
8582 static enum i40e_status_code
8583 i40e_dcb_hw_configure(struct i40e_pf *pf,
8584                       struct i40e_dcbx_config *new_cfg,
8585                       uint8_t tc_map)
8586 {
8587         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8588         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8589         struct i40e_vsi *main_vsi = pf->main_vsi;
8590         struct i40e_vsi_list *vsi_list;
8591         enum i40e_status_code ret;
8592         int i;
8593         uint32_t val;
8594
8595         /* Use the FW API if FW > v4.4*/
8596         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8597               (hw->aq.fw_maj_ver >= 5))) {
8598                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8599                                   " to configure DCB");
8600                 return I40E_ERR_FIRMWARE_API_VERSION;
8601         }
8602
8603         /* Check if need reconfiguration */
8604         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8605                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8606                 return I40E_SUCCESS;
8607         }
8608
8609         /* Copy the new config to the current config */
8610         *old_cfg = *new_cfg;
8611         old_cfg->etsrec = old_cfg->etscfg;
8612         ret = i40e_set_dcb_config(hw);
8613         if (ret) {
8614                 PMD_INIT_LOG(ERR,
8615                          "Set DCB Config failed, err %s aq_err %s\n",
8616                          i40e_stat_str(hw, ret),
8617                          i40e_aq_str(hw, hw->aq.asq_last_status));
8618                 return ret;
8619         }
8620         /* set receive Arbiter to RR mode and ETS scheme by default */
8621         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8622                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8623                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8624                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8625                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8626                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8627                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8628                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8629                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8630                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8631                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8632                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8633                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8634         }
8635         /* get local mib to check whether it is configured correctly */
8636         /* IEEE mode */
8637         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8638         /* Get Local DCB Config */
8639         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8640                                      &hw->local_dcbx_config);
8641
8642         /* if Veb is created, need to update TC of it at first */
8643         if (main_vsi->veb) {
8644                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8645                 if (ret)
8646                         PMD_INIT_LOG(WARNING,
8647                                  "Failed configuring TC for VEB seid=%d\n",
8648                                  main_vsi->veb->seid);
8649         }
8650         /* Update each VSI */
8651         i40e_vsi_config_tc(main_vsi, tc_map);
8652         if (main_vsi->veb) {
8653                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8654                         /* Beside main VSI and VMDQ VSIs, only enable default
8655                          * TC for other VSIs
8656                          */
8657                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8658                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8659                                                          tc_map);
8660                         else
8661                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8662                                                          I40E_DEFAULT_TCMAP);
8663                         if (ret)
8664                                 PMD_INIT_LOG(WARNING,
8665                                          "Failed configuring TC for VSI seid=%d\n",
8666                                          vsi_list->vsi->seid);
8667                         /* continue */
8668                 }
8669         }
8670         return I40E_SUCCESS;
8671 }
8672
8673 /*
8674  * i40e_dcb_init_configure - initial dcb config
8675  * @dev: device being configured
8676  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8677  *
8678  * Returns 0 on success, negative value on failure
8679  */
8680 static int
8681 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8682 {
8683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8685         int ret = 0;
8686
8687         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8688                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8689                 return -ENOTSUP;
8690         }
8691
8692         /* DCB initialization:
8693          * Update DCB configuration from the Firmware and configure
8694          * LLDP MIB change event.
8695          */
8696         if (sw_dcb == TRUE) {
8697                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8698                 if (ret != I40E_SUCCESS)
8699                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8700
8701                 ret = i40e_init_dcb(hw);
8702                 /* if sw_dcb, lldp agent is stopped, the return from
8703                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8704                  * adminq status.
8705                  */
8706                 if (ret != I40E_SUCCESS &&
8707                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8708                         memset(&hw->local_dcbx_config, 0,
8709                                 sizeof(struct i40e_dcbx_config));
8710                         /* set dcb default configuration */
8711                         hw->local_dcbx_config.etscfg.willing = 0;
8712                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8713                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8714                         hw->local_dcbx_config.etscfg.tsatable[0] =
8715                                                 I40E_IEEE_TSA_ETS;
8716                         hw->local_dcbx_config.etsrec =
8717                                 hw->local_dcbx_config.etscfg;
8718                         hw->local_dcbx_config.pfc.willing = 0;
8719                         hw->local_dcbx_config.pfc.pfccap =
8720                                                 I40E_MAX_TRAFFIC_CLASS;
8721                         /* FW needs one App to configure HW */
8722                         hw->local_dcbx_config.numapps = 1;
8723                         hw->local_dcbx_config.app[0].selector =
8724                                                 I40E_APP_SEL_ETHTYPE;
8725                         hw->local_dcbx_config.app[0].priority = 3;
8726                         hw->local_dcbx_config.app[0].protocolid =
8727                                                 I40E_APP_PROTOID_FCOE;
8728                         ret = i40e_set_dcb_config(hw);
8729                         if (ret) {
8730                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8731                                         " err = %d, aq_err = %d.", ret,
8732                                           hw->aq.asq_last_status);
8733                                 return -ENOSYS;
8734                         }
8735                 } else {
8736                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8737                                           " aq_err = %d.", ret,
8738                                           hw->aq.asq_last_status);
8739                         return -ENOTSUP;
8740                 }
8741         } else {
8742                 ret = i40e_aq_start_lldp(hw, NULL);
8743                 if (ret != I40E_SUCCESS)
8744                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8745
8746                 ret = i40e_init_dcb(hw);
8747                 if (!ret) {
8748                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8749                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8750                                                   " DCBX offload.");
8751                                 return -ENOTSUP;
8752                         }
8753                 } else {
8754                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8755                                           " aq_err = %d.", ret,
8756                                           hw->aq.asq_last_status);
8757                         return -ENOTSUP;
8758                 }
8759         }
8760         return 0;
8761 }
8762
8763 /*
8764  * i40e_dcb_setup - setup dcb related config
8765  * @dev: device being configured
8766  *
8767  * Returns 0 on success, negative value on failure
8768  */
8769 static int
8770 i40e_dcb_setup(struct rte_eth_dev *dev)
8771 {
8772         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8773         struct i40e_dcbx_config dcb_cfg;
8774         uint8_t tc_map = 0;
8775         int ret = 0;
8776
8777         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8778                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8779                 return -ENOTSUP;
8780         }
8781
8782         if (pf->vf_num != 0)
8783                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8784
8785         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8786         if (ret) {
8787                 PMD_INIT_LOG(ERR, "invalid dcb config");
8788                 return -EINVAL;
8789         }
8790         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8791         if (ret) {
8792                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8793                 return -ENOSYS;
8794         }
8795
8796         return 0;
8797 }
8798
8799 static int
8800 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8801                       struct rte_eth_dcb_info *dcb_info)
8802 {
8803         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8804         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8805         struct i40e_vsi *vsi = pf->main_vsi;
8806         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8807         uint16_t bsf, tc_mapping;
8808         int i, j;
8809
8810         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8811                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8812         else
8813                 dcb_info->nb_tcs = 1;
8814         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8815                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8816         for (i = 0; i < dcb_info->nb_tcs; i++)
8817                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8818
8819         j = 0;
8820         do {
8821                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8822                         if (!(vsi->enabled_tc & (1 << i)))
8823                                 continue;
8824                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8825                         /* only main vsi support multi TCs */
8826                         dcb_info->tc_queue.tc_rxq[j][i].base =
8827                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8828                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8829                         dcb_info->tc_queue.tc_txq[j][i].base =
8830                                 dcb_info->tc_queue.tc_rxq[j][i].base;
8831                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8832                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8833                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8834                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8835                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8836                 }
8837                 vsi = pf->vmdq[j].vsi;
8838                 j++;
8839         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8840         return 0;
8841 }
8842
8843 static int
8844 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8845 {
8846         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8848         uint16_t interval =
8849                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8850         uint16_t msix_intr;
8851
8852         msix_intr = intr_handle->intr_vec[queue_id];
8853         if (msix_intr == I40E_MISC_VEC_ID)
8854                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8855                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8856                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8857                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8858                                (interval <<
8859                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8860         else
8861                 I40E_WRITE_REG(hw,
8862                                I40E_PFINT_DYN_CTLN(msix_intr -
8863                                                    I40E_RX_VEC_START),
8864                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8865                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8866                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8867                                (interval <<
8868                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8869
8870         I40E_WRITE_FLUSH(hw);
8871         rte_intr_enable(&dev->pci_dev->intr_handle);
8872
8873         return 0;
8874 }
8875
8876 static int
8877 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8878 {
8879         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8880         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8881         uint16_t msix_intr;
8882
8883         msix_intr = intr_handle->intr_vec[queue_id];
8884         if (msix_intr == I40E_MISC_VEC_ID)
8885                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8886         else
8887                 I40E_WRITE_REG(hw,
8888                                I40E_PFINT_DYN_CTLN(msix_intr -
8889                                                    I40E_RX_VEC_START),
8890                                0);
8891         I40E_WRITE_FLUSH(hw);
8892
8893         return 0;
8894 }