drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 373                                       struct ether_addr *mac_addr);
 374
 375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 376
 377 static int i40e_ethertype_filter_convert(
 378         const struct rte_eth_ethertype_filter *input,
 379         struct i40e_ethertype_filter *filter);
 380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 381                                    struct i40e_ethertype_filter *filter);
 382
 383 static int i40e_tunnel_filter_convert(
 384         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 385         struct i40e_tunnel_filter *tunnel_filter);
 386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 387                                 struct i40e_tunnel_filter *tunnel_filter);
 388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 389
 390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 392 static void i40e_filter_restore(struct i40e_pf *pf);
 393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 394
 395 int i40e_logtype_init;
 396 int i40e_logtype_driver;
 397
 398 static const struct rte_pci_id pci_id_i40e_map[] = {
 399         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 419         { .vendor_id = 0, /* sentinel */ },
 420 };
 421
 422 static const struct eth_dev_ops i40e_eth_dev_ops = {
 423         .dev_configure                = i40e_dev_configure,
 424         .dev_start                    = i40e_dev_start,
 425         .dev_stop                     = i40e_dev_stop,
 426         .dev_close                    = i40e_dev_close,
 427         .dev_reset                    = i40e_dev_reset,
 428         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 429         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 430         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 431         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 432         .dev_set_link_up              = i40e_dev_set_link_up,
 433         .dev_set_link_down            = i40e_dev_set_link_down,
 434         .link_update                  = i40e_dev_link_update,
 435         .stats_get                    = i40e_dev_stats_get,
 436         .xstats_get                   = i40e_dev_xstats_get,
 437         .xstats_get_names             = i40e_dev_xstats_get_names,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .fw_version_get               = i40e_fw_version_get,
 442         .dev_infos_get                = i40e_dev_info_get,
 443         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 444         .vlan_filter_set              = i40e_vlan_filter_set,
 445         .vlan_tpid_set                = i40e_vlan_tpid_set,
 446         .vlan_offload_set             = i40e_vlan_offload_set,
 447         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 448         .vlan_pvid_set                = i40e_vlan_pvid_set,
 449         .rx_queue_start               = i40e_dev_rx_queue_start,
 450         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 451         .tx_queue_start               = i40e_dev_tx_queue_start,
 452         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 453         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 454         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 455         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 456         .rx_queue_release             = i40e_dev_rx_queue_release,
 457         .rx_queue_count               = i40e_dev_rx_queue_count,
 458         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 459         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 460         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 461         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 462         .tx_queue_release             = i40e_dev_tx_queue_release,
 463         .dev_led_on                   = i40e_dev_led_on,
 464         .dev_led_off                  = i40e_dev_led_off,
 465         .flow_ctrl_get                = i40e_flow_ctrl_get,
 466         .flow_ctrl_set                = i40e_flow_ctrl_set,
 467         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 468         .mac_addr_add                 = i40e_macaddr_add,
 469         .mac_addr_remove              = i40e_macaddr_remove,
 470         .reta_update                  = i40e_dev_rss_reta_update,
 471         .reta_query                   = i40e_dev_rss_reta_query,
 472         .rss_hash_update              = i40e_dev_rss_hash_update,
 473         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 474         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 475         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 476         .filter_ctrl                  = i40e_dev_filter_ctrl,
 477         .rxq_info_get                 = i40e_rxq_info_get,
 478         .txq_info_get                 = i40e_txq_info_get,
 479         .mirror_rule_set              = i40e_mirror_rule_set,
 480         .mirror_rule_reset            = i40e_mirror_rule_reset,
 481         .timesync_enable              = i40e_timesync_enable,
 482         .timesync_disable             = i40e_timesync_disable,
 483         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 484         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 485         .get_dcb_info                 = i40e_dev_get_dcb_info,
 486         .timesync_adjust_time         = i40e_timesync_adjust_time,
 487         .timesync_read_time           = i40e_timesync_read_time,
 488         .timesync_write_time          = i40e_timesync_write_time,
 489         .get_reg                      = i40e_get_regs,
 490         .get_eeprom_length            = i40e_get_eeprom_length,
 491         .get_eeprom                   = i40e_get_eeprom,
 492         .mac_addr_set                 = i40e_set_default_mac_addr,
 493         .mtu_set                      = i40e_dev_mtu_set,
 494         .tm_ops_get                   = i40e_tm_ops_get,
 495 };
 496
 497 /* store statistics names and its offset in stats structure */
 498 struct rte_i40e_xstats_name_off {
 499         char name[RTE_ETH_XSTATS_NAME_SIZE];
 500         unsigned offset;
 501 };
 502
 503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 504         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 505         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 506         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 507         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 508         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 509                 rx_unknown_protocol)},
 510         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 511         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 512         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 513         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 514 };
 515
 516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 517                 sizeof(rte_i40e_stats_strings[0]))
 518
 519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 520         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 521                 tx_dropped_link_down)},
 522         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 523         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 524                 illegal_bytes)},
 525         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 526         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 527                 mac_local_faults)},
 528         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 529                 mac_remote_faults)},
 530         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 531                 rx_length_errors)},
 532         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 533         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 534         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 535         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 536         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 537         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_127)},
 539         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 540                 rx_size_255)},
 541         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 542                 rx_size_511)},
 543         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 544                 rx_size_1023)},
 545         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_1522)},
 547         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_big)},
 549         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_undersize)},
 551         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_oversize)},
 553         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 554                 mac_short_packet_dropped)},
 555         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_fragments)},
 557         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 558         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 559         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_127)},
 561         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 tx_size_255)},
 563         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 tx_size_511)},
 565         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 tx_size_1023)},
 567         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_1522)},
 569         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_big)},
 571         {"rx_flow_director_atr_match_packets",
 572                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 573         {"rx_flow_director_sb_match_packets",
 574                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 575         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 576                 tx_lpi_status)},
 577         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 578                 rx_lpi_status)},
 579         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 580                 tx_lpi_count)},
 581         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 582                 rx_lpi_count)},
 583 };
 584
 585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 586                 sizeof(rte_i40e_hw_port_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_rx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_rx)},
 593 };
 594
 595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 596                 sizeof(rte_i40e_rxq_prio_strings[0]))
 597
 598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 599         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xon_tx)},
 601         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 602                 priority_xoff_tx)},
 603         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 604                 priority_xon_2_xoff)},
 605 };
 606
 607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 608                 sizeof(rte_i40e_txq_prio_strings[0]))
 609
 610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611         struct rte_pci_device *pci_dev)
 612 {
 613         return rte_eth_dev_pci_generic_probe(pci_dev,
 614                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 615 }
 616
 617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 618 {
 619         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 620 }
 621
 622 static struct rte_pci_driver rte_i40e_pmd = {
 623         .id_table = pci_id_i40e_map,
 624         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 625                      RTE_PCI_DRV_IOVA_AS_VA,
 626         .probe = eth_i40e_pci_probe,
 627         .remove = eth_i40e_pci_remove,
 628 };
 629
 630 static inline int
 631 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 632                                      struct rte_eth_link *link)
 633 {
 634         struct rte_eth_link *dst = link;
 635         struct rte_eth_link *src = &(dev->data->dev_link);
 636
 637         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 638                                         *(uint64_t *)src) == 0)
 639                 return -1;
 640
 641         return 0;
 642 }
 643
 644 static inline int
 645 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 646                                       struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = &(dev->data->dev_link);
 649         struct rte_eth_link *src = link;
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 static inline void
 659 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 660 {
 661         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 662         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 663                     "with value 0x%08x",
 664                     reg_addr, reg_val);
 665 }
 666
 667 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 668 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 669 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 670
 671 #ifndef I40E_GLQF_ORT
 672 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 673 #endif
 674 #ifndef I40E_GLQF_PIT
 675 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 676 #endif
 677 #ifndef I40E_GLQF_L3_MAP
 678 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 679 #endif
 680
 681 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 682 {
 683         /*
 684          * Initialize registers for parsing packet type of QinQ
 685          * This should be removed from code once proper
 686          * configuration API is added to avoid configuration conflicts
 687          * between ports of the same device.
 688          */
 689         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 690         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 691         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 692 }
 693
 694 static inline void i40e_config_automask(struct i40e_pf *pf)
 695 {
 696         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 697         uint32_t val;
 698
 699         /* INTENA flag is not auto-cleared for interrupt */
 700         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 701         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 702                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 703
 704         /* If support multi-driver, PF will use INT0. */
 705         if (!pf->support_multi_driver)
 706                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 707
 708         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 709 }
 710
 711 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 712
 713 /*
 714  * Add a ethertype filter to drop all flow control frames transmitted
 715  * from VSIs.
 716 */
 717 static void
 718 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 719 {
 720         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 721         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 722                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 723                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 724         int ret;
 725
 726         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 727                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 728                                 pf->main_vsi_seid, 0,
 729                                 TRUE, NULL, NULL);
 730         if (ret)
 731                 PMD_INIT_LOG(ERR,
 732                         "Failed to add filter to drop flow control frames from VSIs.");
 733 }
 734
 735 static int
 736 floating_veb_list_handler(__rte_unused const char *key,
 737                           const char *floating_veb_value,
 738                           void *opaque)
 739 {
 740         int idx = 0;
 741         unsigned int count = 0;
 742         char *end = NULL;
 743         int min, max;
 744         bool *vf_floating_veb = opaque;
 745
 746         while (isblank(*floating_veb_value))
 747                 floating_veb_value++;
 748
 749         /* Reset floating VEB configuration for VFs */
 750         for (idx = 0; idx < I40E_MAX_VF; idx++)
 751                 vf_floating_veb[idx] = false;
 752
 753         min = I40E_MAX_VF;
 754         do {
 755                 while (isblank(*floating_veb_value))
 756                         floating_veb_value++;
 757                 if (*floating_veb_value == '\0')
 758                         return -1;
 759                 errno = 0;
 760                 idx = strtoul(floating_veb_value, &end, 10);
 761                 if (errno || end == NULL)
 762                         return -1;
 763                 while (isblank(*end))
 764                         end++;
 765                 if (*end == '-') {
 766                         min = idx;
 767                 } else if ((*end == ';') || (*end == '\0')) {
 768                         max = idx;
 769                         if (min == I40E_MAX_VF)
 770                                 min = idx;
 771                         if (max >= I40E_MAX_VF)
 772                                 max = I40E_MAX_VF - 1;
 773                         for (idx = min; idx <= max; idx++) {
 774                                 vf_floating_veb[idx] = true;
 775                                 count++;
 776                         }
 777                         min = I40E_MAX_VF;
 778                 } else {
 779                         return -1;
 780                 }
 781                 floating_veb_value = end + 1;
 782         } while (*end != '\0');
 783
 784         if (count == 0)
 785                 return -1;
 786
 787         return 0;
 788 }
 789
 790 static void
 791 config_vf_floating_veb(struct rte_devargs *devargs,
 792                        uint16_t floating_veb,
 793                        bool *vf_floating_veb)
 794 {
 795         struct rte_kvargs *kvlist;
 796         int i;
 797         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 798
 799         if (!floating_veb)
 800                 return;
 801         /* All the VFs attach to the floating VEB by default
 802          * when the floating VEB is enabled.
 803          */
 804         for (i = 0; i < I40E_MAX_VF; i++)
 805                 vf_floating_veb[i] = true;
 806
 807         if (devargs == NULL)
 808                 return;
 809
 810         kvlist = rte_kvargs_parse(devargs->args, NULL);
 811         if (kvlist == NULL)
 812                 return;
 813
 814         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 815                 rte_kvargs_free(kvlist);
 816                 return;
 817         }
 818         /* When the floating_veb_list parameter exists, all the VFs
 819          * will attach to the legacy VEB firstly, then configure VFs
 820          * to the floating VEB according to the floating_veb_list.
 821          */
 822         if (rte_kvargs_process(kvlist, floating_veb_list,
 823                                floating_veb_list_handler,
 824                                vf_floating_veb) < 0) {
 825                 rte_kvargs_free(kvlist);
 826                 return;
 827         }
 828         rte_kvargs_free(kvlist);
 829 }
 830
 831 static int
 832 i40e_check_floating_handler(__rte_unused const char *key,
 833                             const char *value,
 834                             __rte_unused void *opaque)
 835 {
 836         if (strcmp(value, "1"))
 837                 return -1;
 838
 839         return 0;
 840 }
 841
 842 static int
 843 is_floating_veb_supported(struct rte_devargs *devargs)
 844 {
 845         struct rte_kvargs *kvlist;
 846         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 847
 848         if (devargs == NULL)
 849                 return 0;
 850
 851         kvlist = rte_kvargs_parse(devargs->args, NULL);
 852         if (kvlist == NULL)
 853                 return 0;
 854
 855         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 856                 rte_kvargs_free(kvlist);
 857                 return 0;
 858         }
 859         /* Floating VEB is enabled when there's key-value:
 860          * enable_floating_veb=1
 861          */
 862         if (rte_kvargs_process(kvlist, floating_veb_key,
 863                                i40e_check_floating_handler, NULL) < 0) {
 864                 rte_kvargs_free(kvlist);
 865                 return 0;
 866         }
 867         rte_kvargs_free(kvlist);
 868
 869         return 1;
 870 }
 871
 872 static void
 873 config_floating_veb(struct rte_eth_dev *dev)
 874 {
 875         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 876         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 877         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 878
 879         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 880
 881         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 882                 pf->floating_veb =
 883                         is_floating_veb_supported(pci_dev->device.devargs);
 884                 config_vf_floating_veb(pci_dev->device.devargs,
 885                                        pf->floating_veb,
 886                                        pf->floating_veb_list);
 887         } else {
 888                 pf->floating_veb = false;
 889         }
 890 }
 891
 892 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 893 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 894
 895 static int
 896 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 897 {
 898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 899         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 900         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 901         int ret;
 902
 903         struct rte_hash_parameters ethertype_hash_params = {
 904                 .name = ethertype_hash_name,
 905                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 906                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 907                 .hash_func = rte_hash_crc,
 908                 .hash_func_init_val = 0,
 909                 .socket_id = rte_socket_id(),
 910         };
 911
 912         /* Initialize ethertype filter rule list and hash */
 913         TAILQ_INIT(&ethertype_rule->ethertype_list);
 914         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 915                  "ethertype_%s", dev->device->name);
 916         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 917         if (!ethertype_rule->hash_table) {
 918                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 919                 return -EINVAL;
 920         }
 921         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 922                                        sizeof(struct i40e_ethertype_filter *) *
 923                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 924                                        0);
 925         if (!ethertype_rule->hash_map) {
 926                 PMD_INIT_LOG(ERR,
 927                              "Failed to allocate memory for ethertype hash map!");
 928                 ret = -ENOMEM;
 929                 goto err_ethertype_hash_map_alloc;
 930         }
 931
 932         return 0;
 933
 934 err_ethertype_hash_map_alloc:
 935         rte_hash_free(ethertype_rule->hash_table);
 936
 937         return ret;
 938 }
 939
 940 static int
 941 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 942 {
 943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 944         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 945         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 946         int ret;
 947
 948         struct rte_hash_parameters tunnel_hash_params = {
 949                 .name = tunnel_hash_name,
 950                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 951                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 952                 .hash_func = rte_hash_crc,
 953                 .hash_func_init_val = 0,
 954                 .socket_id = rte_socket_id(),
 955         };
 956
 957         /* Initialize tunnel filter rule list and hash */
 958         TAILQ_INIT(&tunnel_rule->tunnel_list);
 959         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 960                  "tunnel_%s", dev->device->name);
 961         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 962         if (!tunnel_rule->hash_table) {
 963                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 964                 return -EINVAL;
 965         }
 966         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 967                                     sizeof(struct i40e_tunnel_filter *) *
 968                                     I40E_MAX_TUNNEL_FILTER_NUM,
 969                                     0);
 970         if (!tunnel_rule->hash_map) {
 971                 PMD_INIT_LOG(ERR,
 972                              "Failed to allocate memory for tunnel hash map!");
 973                 ret = -ENOMEM;
 974                 goto err_tunnel_hash_map_alloc;
 975         }
 976
 977         return 0;
 978
 979 err_tunnel_hash_map_alloc:
 980         rte_hash_free(tunnel_rule->hash_table);
 981
 982         return ret;
 983 }
 984
 985 static int
 986 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 987 {
 988         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 989         struct i40e_fdir_info *fdir_info = &pf->fdir;
 990         char fdir_hash_name[RTE_HASH_NAMESIZE];
 991         int ret;
 992
 993         struct rte_hash_parameters fdir_hash_params = {
 994                 .name = fdir_hash_name,
 995                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 996                 .key_len = sizeof(struct i40e_fdir_input),
 997                 .hash_func = rte_hash_crc,
 998                 .hash_func_init_val = 0,
 999                 .socket_id = rte_socket_id(),
1000         };
1001
1002         /* Initialize flow director filter rule list and hash */
1003         TAILQ_INIT(&fdir_info->fdir_list);
1004         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1005                  "fdir_%s", dev->device->name);
1006         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1007         if (!fdir_info->hash_table) {
1008                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1009                 return -EINVAL;
1010         }
1011         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1012                                           sizeof(struct i40e_fdir_filter *) *
1013                                           I40E_MAX_FDIR_FILTER_NUM,
1014                                           0);
1015         if (!fdir_info->hash_map) {
1016                 PMD_INIT_LOG(ERR,
1017                              "Failed to allocate memory for fdir hash map!");
1018                 ret = -ENOMEM;
1019                 goto err_fdir_hash_map_alloc;
1020         }
1021         return 0;
1022
1023 err_fdir_hash_map_alloc:
1024         rte_hash_free(fdir_info->hash_table);
1025
1026         return ret;
1027 }
1028
1029 static void
1030 i40e_init_customized_info(struct i40e_pf *pf)
1031 {
1032         int i;
1033
1034         /* Initialize customized pctype */
1035         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1036                 pf->customized_pctype[i].index = i;
1037                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1038                 pf->customized_pctype[i].valid = false;
1039         }
1040
1041         pf->gtp_support = false;
1042 }
1043
1044 void
1045 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1046 {
1047         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049         struct i40e_queue_regions *info = &pf->queue_region;
1050         uint16_t i;
1051
1052         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1053                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1054
1055         memset(info, 0, sizeof(struct i40e_queue_regions));
1056 }
1057
1058 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1059
1060 static int
1061 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1062                                const char *value,
1063                                void *opaque)
1064 {
1065         struct i40e_pf *pf;
1066         unsigned long support_multi_driver;
1067         char *end;
1068
1069         pf = (struct i40e_pf *)opaque;
1070
1071         errno = 0;
1072         support_multi_driver = strtoul(value, &end, 10);
1073         if (errno != 0 || end == value || *end != 0) {
1074                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1075                 return -(EINVAL);
1076         }
1077
1078         if (support_multi_driver == 1 || support_multi_driver == 0)
1079                 pf->support_multi_driver = (bool)support_multi_driver;
1080         else
1081                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1082                             "enable global configuration by default."
1083                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1084         return 0;
1085 }
1086
1087 static int
1088 i40e_support_multi_driver(struct rte_eth_dev *dev)
1089 {
1090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1091         static const char *const valid_keys[] = {
1092                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1093         struct rte_kvargs *kvlist;
1094
1095         /* Enable global configuration by default */
1096         pf->support_multi_driver = false;
1097
1098         if (!dev->device->devargs)
1099                 return 0;
1100
1101         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1102         if (!kvlist)
1103                 return -EINVAL;
1104
1105         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1106                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1107                             "the first invalid or last valid one is used !",
1108                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1109
1110         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1111                                i40e_parse_multi_drv_handler, pf) < 0) {
1112                 rte_kvargs_free(kvlist);
1113                 return -EINVAL;
1114         }
1115
1116         rte_kvargs_free(kvlist);
1117         return 0;
1118 }
1119
1120 static int
1121 eth_i40e_dev_init(struct rte_eth_dev *dev)
1122 {
1123         struct rte_pci_device *pci_dev;
1124         struct rte_intr_handle *intr_handle;
1125         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1126         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         struct i40e_vsi *vsi;
1128         int ret;
1129         uint32_t len;
1130         uint8_t aq_fail = 0;
1131
1132         PMD_INIT_FUNC_TRACE();
1133
1134         dev->dev_ops = &i40e_eth_dev_ops;
1135         dev->rx_pkt_burst = i40e_recv_pkts;
1136         dev->tx_pkt_burst = i40e_xmit_pkts;
1137         dev->tx_pkt_prepare = i40e_prep_pkts;
1138
1139         /* for secondary processes, we don't initialise any further as primary
1140          * has already done this work. Only check we don't need a different
1141          * RX function */
1142         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1143                 i40e_set_rx_function(dev);
1144                 i40e_set_tx_function(dev);
1145                 return 0;
1146         }
1147         i40e_set_default_ptype_table(dev);
1148         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1149         intr_handle = &pci_dev->intr_handle;
1150
1151         rte_eth_copy_pci_info(dev, pci_dev);
1152
1153         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1154         pf->adapter->eth_dev = dev;
1155         pf->dev_data = dev->data;
1156
1157         hw->back = I40E_PF_TO_ADAPTER(pf);
1158         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1159         if (!hw->hw_addr) {
1160                 PMD_INIT_LOG(ERR,
1161                         "Hardware is not available, as address is NULL");
1162                 return -ENODEV;
1163         }
1164
1165         hw->vendor_id = pci_dev->id.vendor_id;
1166         hw->device_id = pci_dev->id.device_id;
1167         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1168         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1169         hw->bus.device = pci_dev->addr.devid;
1170         hw->bus.func = pci_dev->addr.function;
1171         hw->adapter_stopped = 0;
1172
1173         /* Check if need to support multi-driver */
1174         i40e_support_multi_driver(dev);
1175
1176         /* Make sure all is clean before doing PF reset */
1177         i40e_clear_hw(hw);
1178
1179         /* Initialize the hardware */
1180         i40e_hw_init(dev);
1181
1182         /* Reset here to make sure all is clean for each PF */
1183         ret = i40e_pf_reset(hw);
1184         if (ret) {
1185                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1186                 return ret;
1187         }
1188
1189         /* Initialize the shared code (base driver) */
1190         ret = i40e_init_shared_code(hw);
1191         if (ret) {
1192                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1193                 return ret;
1194         }
1195
1196         i40e_config_automask(pf);
1197
1198         i40e_set_default_pctype_table(dev);
1199
1200         /*
1201          * To work around the NVM issue, initialize registers
1202          * for packet type of QinQ by software.
1203          * It should be removed once issues are fixed in NVM.
1204          */
1205         if (!pf->support_multi_driver)
1206                 i40e_GLQF_reg_init(hw);
1207
1208         /* Initialize the input set for filters (hash and fd) to default value */
1209         i40e_filter_input_set_init(pf);
1210
1211         /* Initialize the parameters for adminq */
1212         i40e_init_adminq_parameter(hw);
1213         ret = i40e_init_adminq(hw);
1214         if (ret != I40E_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1216                 return -EIO;
1217         }
1218         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1219                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1220                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1221                      ((hw->nvm.version >> 12) & 0xf),
1222                      ((hw->nvm.version >> 4) & 0xff),
1223                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1224
1225         /* initialise the L3_MAP register */
1226         if (!pf->support_multi_driver) {
1227                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1228                                                    0x00000028,  NULL);
1229                 if (ret)
1230                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1231                                      ret);
1232                 PMD_INIT_LOG(DEBUG,
1233                              "Global register 0x%08x is changed with 0x28",
1234                              I40E_GLQF_L3_MAP(40));
1235                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1236         }
1237
1238         /* Need the special FW version to support floating VEB */
1239         config_floating_veb(dev);
1240         /* Clear PXE mode */
1241         i40e_clear_pxe_mode(hw);
1242         i40e_dev_sync_phy_type(hw);
1243
1244         /*
1245          * On X710, performance number is far from the expectation on recent
1246          * firmware versions. The fix for this issue may not be integrated in
1247          * the following firmware version. So the workaround in software driver
1248          * is needed. It needs to modify the initial values of 3 internal only
1249          * registers. Note that the workaround can be removed when it is fixed
1250          * in firmware in the future.
1251          */
1252         i40e_configure_registers(hw);
1253
1254         /* Get hw capabilities */
1255         ret = i40e_get_cap(hw);
1256         if (ret != I40E_SUCCESS) {
1257                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1258                 goto err_get_capabilities;
1259         }
1260
1261         /* Initialize parameters for PF */
1262         ret = i40e_pf_parameter_init(dev);
1263         if (ret != 0) {
1264                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1265                 goto err_parameter_init;
1266         }
1267
1268         /* Initialize the queue management */
1269         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1270         if (ret < 0) {
1271                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1272                 goto err_qp_pool_init;
1273         }
1274         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1275                                 hw->func_caps.num_msix_vectors - 1);
1276         if (ret < 0) {
1277                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1278                 goto err_msix_pool_init;
1279         }
1280
1281         /* Initialize lan hmc */
1282         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1283                                 hw->func_caps.num_rx_qp, 0, 0);
1284         if (ret != I40E_SUCCESS) {
1285                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1286                 goto err_init_lan_hmc;
1287         }
1288
1289         /* Configure lan hmc */
1290         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1291         if (ret != I40E_SUCCESS) {
1292                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1293                 goto err_configure_lan_hmc;
1294         }
1295
1296         /* Get and check the mac address */
1297         i40e_get_mac_addr(hw, hw->mac.addr);
1298         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1299                 PMD_INIT_LOG(ERR, "mac address is not valid");
1300                 ret = -EIO;
1301                 goto err_get_mac_addr;
1302         }
1303         /* Copy the permanent MAC address */
1304         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1305                         (struct ether_addr *) hw->mac.perm_addr);
1306
1307         /* Disable flow control */
1308         hw->fc.requested_mode = I40E_FC_NONE;
1309         i40e_set_fc(hw, &aq_fail, TRUE);
1310
1311         /* Set the global registers with default ether type value */
1312         if (!pf->support_multi_driver) {
1313                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1314                                          ETHER_TYPE_VLAN);
1315                 if (ret != I40E_SUCCESS) {
1316                         PMD_INIT_LOG(ERR,
1317                                      "Failed to set the default outer "
1318                                      "VLAN ether type");
1319                         goto err_setup_pf_switch;
1320                 }
1321         }
1322
1323         /* PF setup, which includes VSI setup */
1324         ret = i40e_pf_setup(pf);
1325         if (ret) {
1326                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1327                 goto err_setup_pf_switch;
1328         }
1329
1330         /* reset all stats of the device, including pf and main vsi */
1331         i40e_dev_stats_reset(dev);
1332
1333         vsi = pf->main_vsi;
1334
1335         /* Disable double vlan by default */
1336         i40e_vsi_config_double_vlan(vsi, FALSE);
1337
1338         /* Disable S-TAG identification when floating_veb is disabled */
1339         if (!pf->floating_veb) {
1340                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1341                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1342                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1343                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1344                 }
1345         }
1346
1347         if (!vsi->max_macaddrs)
1348                 len = ETHER_ADDR_LEN;
1349         else
1350                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1351
1352         /* Should be after VSI initialized */
1353         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1354         if (!dev->data->mac_addrs) {
1355                 PMD_INIT_LOG(ERR,
1356                         "Failed to allocated memory for storing mac address");
1357                 goto err_mac_alloc;
1358         }
1359         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1360                                         &dev->data->mac_addrs[0]);
1361
1362         /* Init dcb to sw mode by default */
1363         ret = i40e_dcb_init_configure(dev, TRUE);
1364         if (ret != I40E_SUCCESS) {
1365                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1366                 pf->flags &= ~I40E_FLAG_DCB;
1367         }
1368         /* Update HW struct after DCB configuration */
1369         i40e_get_cap(hw);
1370
1371         /* initialize pf host driver to setup SRIOV resource if applicable */
1372         i40e_pf_host_init(dev);
1373
1374         /* register callback func to eal lib */
1375         rte_intr_callback_register(intr_handle,
1376                                    i40e_dev_interrupt_handler, dev);
1377
1378         /* configure and enable device interrupt */
1379         i40e_pf_config_irq0(hw, TRUE);
1380         i40e_pf_enable_irq0(hw);
1381
1382         /* enable uio intr after callback register */
1383         rte_intr_enable(intr_handle);
1384
1385         /* By default disable flexible payload in global configuration */
1386         if (!pf->support_multi_driver)
1387                 i40e_flex_payload_reg_set_default(hw);
1388
1389         /*
1390          * Add an ethertype filter to drop all flow control frames transmitted
1391          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1392          * frames to wire.
1393          */
1394         i40e_add_tx_flow_control_drop_filter(pf);
1395
1396         /* Set the max frame size to 0x2600 by default,
1397          * in case other drivers changed the default value.
1398          */
1399         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1400
1401         /* initialize mirror rule list */
1402         TAILQ_INIT(&pf->mirror_list);
1403
1404         /* initialize Traffic Manager configuration */
1405         i40e_tm_conf_init(dev);
1406
1407         /* Initialize customized information */
1408         i40e_init_customized_info(pf);
1409
1410         ret = i40e_init_ethtype_filter_list(dev);
1411         if (ret < 0)
1412                 goto err_init_ethtype_filter_list;
1413         ret = i40e_init_tunnel_filter_list(dev);
1414         if (ret < 0)
1415                 goto err_init_tunnel_filter_list;
1416         ret = i40e_init_fdir_filter_list(dev);
1417         if (ret < 0)
1418                 goto err_init_fdir_filter_list;
1419
1420         /* initialize queue region configuration */
1421         i40e_init_queue_region_conf(dev);
1422
1423         /* initialize rss configuration from rte_flow */
1424         memset(&pf->rss_info, 0,
1425                 sizeof(struct i40e_rte_flow_rss_conf));
1426
1427         return 0;
1428
1429 err_init_fdir_filter_list:
1430         rte_free(pf->tunnel.hash_table);
1431         rte_free(pf->tunnel.hash_map);
1432 err_init_tunnel_filter_list:
1433         rte_free(pf->ethertype.hash_table);
1434         rte_free(pf->ethertype.hash_map);
1435 err_init_ethtype_filter_list:
1436         rte_free(dev->data->mac_addrs);
1437 err_mac_alloc:
1438         i40e_vsi_release(pf->main_vsi);
1439 err_setup_pf_switch:
1440 err_get_mac_addr:
1441 err_configure_lan_hmc:
1442         (void)i40e_shutdown_lan_hmc(hw);
1443 err_init_lan_hmc:
1444         i40e_res_pool_destroy(&pf->msix_pool);
1445 err_msix_pool_init:
1446         i40e_res_pool_destroy(&pf->qp_pool);
1447 err_qp_pool_init:
1448 err_parameter_init:
1449 err_get_capabilities:
1450         (void)i40e_shutdown_adminq(hw);
1451
1452         return ret;
1453 }
1454
1455 static void
1456 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1457 {
1458         struct i40e_ethertype_filter *p_ethertype;
1459         struct i40e_ethertype_rule *ethertype_rule;
1460
1461         ethertype_rule = &pf->ethertype;
1462         /* Remove all ethertype filter rules and hash */
1463         if (ethertype_rule->hash_map)
1464                 rte_free(ethertype_rule->hash_map);
1465         if (ethertype_rule->hash_table)
1466                 rte_hash_free(ethertype_rule->hash_table);
1467
1468         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1469                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1470                              p_ethertype, rules);
1471                 rte_free(p_ethertype);
1472         }
1473 }
1474
1475 static void
1476 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1477 {
1478         struct i40e_tunnel_filter *p_tunnel;
1479         struct i40e_tunnel_rule *tunnel_rule;
1480
1481         tunnel_rule = &pf->tunnel;
1482         /* Remove all tunnel director rules and hash */
1483         if (tunnel_rule->hash_map)
1484                 rte_free(tunnel_rule->hash_map);
1485         if (tunnel_rule->hash_table)
1486                 rte_hash_free(tunnel_rule->hash_table);
1487
1488         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1489                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1490                 rte_free(p_tunnel);
1491         }
1492 }
1493
1494 static void
1495 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1496 {
1497         struct i40e_fdir_filter *p_fdir;
1498         struct i40e_fdir_info *fdir_info;
1499
1500         fdir_info = &pf->fdir;
1501         /* Remove all flow director rules and hash */
1502         if (fdir_info->hash_map)
1503                 rte_free(fdir_info->hash_map);
1504         if (fdir_info->hash_table)
1505                 rte_hash_free(fdir_info->hash_table);
1506
1507         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1508                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1509                 rte_free(p_fdir);
1510         }
1511 }
1512
1513 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1514 {
1515         /*
1516          * Disable by default flexible payload
1517          * for corresponding L2/L3/L4 layers.
1518          */
1519         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1520         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1521         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1522         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1523 }
1524
1525 static int
1526 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1527 {
1528         struct i40e_pf *pf;
1529         struct rte_pci_device *pci_dev;
1530         struct rte_intr_handle *intr_handle;
1531         struct i40e_hw *hw;
1532         struct i40e_filter_control_settings settings;
1533         struct rte_flow *p_flow;
1534         int ret;
1535         uint8_t aq_fail = 0;
1536
1537         PMD_INIT_FUNC_TRACE();
1538
1539         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1540                 return 0;
1541
1542         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1543         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1544         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1545         intr_handle = &pci_dev->intr_handle;
1546
1547         if (hw->adapter_stopped == 0)
1548                 i40e_dev_close(dev);
1549
1550         dev->dev_ops = NULL;
1551         dev->rx_pkt_burst = NULL;
1552         dev->tx_pkt_burst = NULL;
1553
1554         /* Clear PXE mode */
1555         i40e_clear_pxe_mode(hw);
1556
1557         /* Unconfigure filter control */
1558         memset(&settings, 0, sizeof(settings));
1559         ret = i40e_set_filter_control(hw, &settings);
1560         if (ret)
1561                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1562                                         ret);
1563
1564         /* Disable flow control */
1565         hw->fc.requested_mode = I40E_FC_NONE;
1566         i40e_set_fc(hw, &aq_fail, TRUE);
1567
1568         /* uninitialize pf host driver */
1569         i40e_pf_host_uninit(dev);
1570
1571         rte_free(dev->data->mac_addrs);
1572         dev->data->mac_addrs = NULL;
1573
1574         /* disable uio intr before callback unregister */
1575         rte_intr_disable(intr_handle);
1576
1577         /* register callback func to eal lib */
1578         rte_intr_callback_unregister(intr_handle,
1579                                      i40e_dev_interrupt_handler, dev);
1580
1581         i40e_rm_ethtype_filter_list(pf);
1582         i40e_rm_tunnel_filter_list(pf);
1583         i40e_rm_fdir_filter_list(pf);
1584
1585         /* Remove all flows */
1586         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1587                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1588                 rte_free(p_flow);
1589         }
1590
1591         /* Remove all Traffic Manager configuration */
1592         i40e_tm_conf_uninit(dev);
1593
1594         return 0;
1595 }
1596
1597 static int
1598 i40e_dev_configure(struct rte_eth_dev *dev)
1599 {
1600         struct i40e_adapter *ad =
1601                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1602         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1605         int i, ret;
1606
1607         ret = i40e_dev_sync_phy_type(hw);
1608         if (ret)
1609                 return ret;
1610
1611         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1612          * bulk allocation or vector Rx preconditions we will reset it.
1613          */
1614         ad->rx_bulk_alloc_allowed = true;
1615         ad->rx_vec_allowed = true;
1616         ad->tx_simple_allowed = true;
1617         ad->tx_vec_allowed = true;
1618
1619         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1620                 ret = i40e_fdir_setup(pf);
1621                 if (ret != I40E_SUCCESS) {
1622                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1623                         return -ENOTSUP;
1624                 }
1625                 ret = i40e_fdir_configure(dev);
1626                 if (ret < 0) {
1627                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1628                         goto err;
1629                 }
1630         } else
1631                 i40e_fdir_teardown(pf);
1632
1633         ret = i40e_dev_init_vlan(dev);
1634         if (ret < 0)
1635                 goto err;
1636
1637         /* VMDQ setup.
1638          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1639          *  RSS setting have different requirements.
1640          *  General PMD driver call sequence are NIC init, configure,
1641          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1642          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1643          *  applicable. So, VMDQ setting has to be done before
1644          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1645          *  For RSS setting, it will try to calculate actual configured RX queue
1646          *  number, which will be available after rx_queue_setup(). dev_start()
1647          *  function is good to place RSS setup.
1648          */
1649         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1650                 ret = i40e_vmdq_setup(dev);
1651                 if (ret)
1652                         goto err;
1653         }
1654
1655         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1656                 ret = i40e_dcb_setup(dev);
1657                 if (ret) {
1658                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1659                         goto err_dcb;
1660                 }
1661         }
1662
1663         TAILQ_INIT(&pf->flow_list);
1664
1665         return 0;
1666
1667 err_dcb:
1668         /* need to release vmdq resource if exists */
1669         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1670                 i40e_vsi_release(pf->vmdq[i].vsi);
1671                 pf->vmdq[i].vsi = NULL;
1672         }
1673         rte_free(pf->vmdq);
1674         pf->vmdq = NULL;
1675 err:
1676         /* need to release fdir resource if exists */
1677         i40e_fdir_teardown(pf);
1678         return ret;
1679 }
1680
1681 void
1682 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1683 {
1684         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1685         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1686         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1687         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1688         uint16_t msix_vect = vsi->msix_intr;
1689         uint16_t i;
1690
1691         for (i = 0; i < vsi->nb_qps; i++) {
1692                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1693                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1694                 rte_wmb();
1695         }
1696
1697         if (vsi->type != I40E_VSI_SRIOV) {
1698                 if (!rte_intr_allow_others(intr_handle)) {
1699                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1700                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1701                         I40E_WRITE_REG(hw,
1702                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1703                                        0);
1704                 } else {
1705                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1706                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1707                         I40E_WRITE_REG(hw,
1708                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1709                                                        msix_vect - 1), 0);
1710                 }
1711         } else {
1712                 uint32_t reg;
1713                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1714                         vsi->user_param + (msix_vect - 1);
1715
1716                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1717                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1718         }
1719         I40E_WRITE_FLUSH(hw);
1720 }
1721
1722 static void
1723 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1724                        int base_queue, int nb_queue,
1725                        uint16_t itr_idx)
1726 {
1727         int i;
1728         uint32_t val;
1729         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1730         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1731
1732         /* Bind all RX queues to allocated MSIX interrupt */
1733         for (i = 0; i < nb_queue; i++) {
1734                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1735                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1736                         ((base_queue + i + 1) <<
1737                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1738                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1739                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1740
1741                 if (i == nb_queue - 1)
1742                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1743                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1744         }
1745
1746         /* Write first RX queue to Link list register as the head element */
1747         if (vsi->type != I40E_VSI_SRIOV) {
1748                 uint16_t interval =
1749                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1750                                                pf->support_multi_driver);
1751
1752                 if (msix_vect == I40E_MISC_VEC_ID) {
1753                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1754                                        (base_queue <<
1755                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1756                                        (0x0 <<
1757                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1758                         I40E_WRITE_REG(hw,
1759                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1760                                        interval);
1761                 } else {
1762                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1763                                        (base_queue <<
1764                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1765                                        (0x0 <<
1766                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1767                         I40E_WRITE_REG(hw,
1768                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1769                                                        msix_vect - 1),
1770                                        interval);
1771                 }
1772         } else {
1773                 uint32_t reg;
1774
1775                 if (msix_vect == I40E_MISC_VEC_ID) {
1776                         I40E_WRITE_REG(hw,
1777                                        I40E_VPINT_LNKLST0(vsi->user_param),
1778                                        (base_queue <<
1779                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1780                                        (0x0 <<
1781                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1782                 } else {
1783                         /* num_msix_vectors_vf needs to minus irq0 */
1784                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1785                                 vsi->user_param + (msix_vect - 1);
1786
1787                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1788                                        (base_queue <<
1789                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1790                                        (0x0 <<
1791                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1792                 }
1793         }
1794
1795         I40E_WRITE_FLUSH(hw);
1796 }
1797
1798 void
1799 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1800 {
1801         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1802         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1803         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1804         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1805         uint16_t msix_vect = vsi->msix_intr;
1806         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1807         uint16_t queue_idx = 0;
1808         int record = 0;
1809         int i;
1810
1811         for (i = 0; i < vsi->nb_qps; i++) {
1812                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1813                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1814         }
1815
1816         /* VF bind interrupt */
1817         if (vsi->type == I40E_VSI_SRIOV) {
1818                 __vsi_queues_bind_intr(vsi, msix_vect,
1819                                        vsi->base_queue, vsi->nb_qps,
1820                                        itr_idx);
1821                 return;
1822         }
1823
1824         /* PF & VMDq bind interrupt */
1825         if (rte_intr_dp_is_en(intr_handle)) {
1826                 if (vsi->type == I40E_VSI_MAIN) {
1827                         queue_idx = 0;
1828                         record = 1;
1829                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1830                         struct i40e_vsi *main_vsi =
1831                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1832                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1833                         record = 1;
1834                 }
1835         }
1836
1837         for (i = 0; i < vsi->nb_used_qps; i++) {
1838                 if (nb_msix <= 1) {
1839                         if (!rte_intr_allow_others(intr_handle))
1840                                 /* allow to share MISC_VEC_ID */
1841                                 msix_vect = I40E_MISC_VEC_ID;
1842
1843                         /* no enough msix_vect, map all to one */
1844                         __vsi_queues_bind_intr(vsi, msix_vect,
1845                                                vsi->base_queue + i,
1846                                                vsi->nb_used_qps - i,
1847                                                itr_idx);
1848                         for (; !!record && i < vsi->nb_used_qps; i++)
1849                                 intr_handle->intr_vec[queue_idx + i] =
1850                                         msix_vect;
1851                         break;
1852                 }
1853                 /* 1:1 queue/msix_vect mapping */
1854                 __vsi_queues_bind_intr(vsi, msix_vect,
1855                                        vsi->base_queue + i, 1,
1856                                        itr_idx);
1857                 if (!!record)
1858                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1859
1860                 msix_vect++;
1861                 nb_msix--;
1862         }
1863 }
1864
1865 static void
1866 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1867 {
1868         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1869         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1870         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1871         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1872         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1873         uint16_t msix_intr, i;
1874
1875         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1876                 for (i = 0; i < vsi->nb_msix; i++) {
1877                         msix_intr = vsi->msix_intr + i;
1878                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1879                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1880                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1881                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1882                 }
1883         else
1884                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1885                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1886                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1887                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1888
1889         I40E_WRITE_FLUSH(hw);
1890 }
1891
1892 static void
1893 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1894 {
1895         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1896         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1897         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1898         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1899         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1900         uint16_t msix_intr, i;
1901
1902         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1903                 for (i = 0; i < vsi->nb_msix; i++) {
1904                         msix_intr = vsi->msix_intr + i;
1905                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1906                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1907                 }
1908         else
1909                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1910                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1911
1912         I40E_WRITE_FLUSH(hw);
1913 }
1914
1915 static inline uint8_t
1916 i40e_parse_link_speeds(uint16_t link_speeds)
1917 {
1918         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1919
1920         if (link_speeds & ETH_LINK_SPEED_40G)
1921                 link_speed |= I40E_LINK_SPEED_40GB;
1922         if (link_speeds & ETH_LINK_SPEED_25G)
1923                 link_speed |= I40E_LINK_SPEED_25GB;
1924         if (link_speeds & ETH_LINK_SPEED_20G)
1925                 link_speed |= I40E_LINK_SPEED_20GB;
1926         if (link_speeds & ETH_LINK_SPEED_10G)
1927                 link_speed |= I40E_LINK_SPEED_10GB;
1928         if (link_speeds & ETH_LINK_SPEED_1G)
1929                 link_speed |= I40E_LINK_SPEED_1GB;
1930         if (link_speeds & ETH_LINK_SPEED_100M)
1931                 link_speed |= I40E_LINK_SPEED_100MB;
1932
1933         return link_speed;
1934 }
1935
1936 static int
1937 i40e_phy_conf_link(struct i40e_hw *hw,
1938                    uint8_t abilities,
1939                    uint8_t force_speed,
1940                    bool is_up)
1941 {
1942         enum i40e_status_code status;
1943         struct i40e_aq_get_phy_abilities_resp phy_ab;
1944         struct i40e_aq_set_phy_config phy_conf;
1945         enum i40e_aq_phy_type cnt;
1946         uint32_t phy_type_mask = 0;
1947
1948         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1949                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1950                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1951                         I40E_AQ_PHY_FLAG_LOW_POWER;
1952         const uint8_t advt = I40E_LINK_SPEED_40GB |
1953                         I40E_LINK_SPEED_25GB |
1954                         I40E_LINK_SPEED_10GB |
1955                         I40E_LINK_SPEED_1GB |
1956                         I40E_LINK_SPEED_100MB;
1957         int ret = -ENOTSUP;
1958
1959
1960         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1961                                               NULL);
1962         if (status)
1963                 return ret;
1964
1965         /* If link already up, no need to set up again */
1966         if (is_up && phy_ab.phy_type != 0)
1967                 return I40E_SUCCESS;
1968
1969         memset(&phy_conf, 0, sizeof(phy_conf));
1970
1971         /* bits 0-2 use the values from get_phy_abilities_resp */
1972         abilities &= ~mask;
1973         abilities |= phy_ab.abilities & mask;
1974
1975         /* update ablities and speed */
1976         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1977                 phy_conf.link_speed = advt;
1978         else
1979                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1980
1981         phy_conf.abilities = abilities;
1982
1983
1984
1985         /* To enable link, phy_type mask needs to include each type */
1986         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1987                 phy_type_mask |= 1 << cnt;
1988
1989         /* use get_phy_abilities_resp value for the rest */
1990         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1991         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1992                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1993                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1994         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1995         phy_conf.eee_capability = phy_ab.eee_capability;
1996         phy_conf.eeer = phy_ab.eeer_val;
1997         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1998
1999         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2000                     phy_ab.abilities, phy_ab.link_speed);
2001         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2002                     phy_conf.abilities, phy_conf.link_speed);
2003
2004         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2005         if (status)
2006                 return ret;
2007
2008         return I40E_SUCCESS;
2009 }
2010
2011 static int
2012 i40e_apply_link_speed(struct rte_eth_dev *dev)
2013 {
2014         uint8_t speed;
2015         uint8_t abilities = 0;
2016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         struct rte_eth_conf *conf = &dev->data->dev_conf;
2018
2019         speed = i40e_parse_link_speeds(conf->link_speeds);
2020         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2021         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2022                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2023         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2024
2025         return i40e_phy_conf_link(hw, abilities, speed, true);
2026 }
2027
2028 static int
2029 i40e_dev_start(struct rte_eth_dev *dev)
2030 {
2031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2032         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033         struct i40e_vsi *main_vsi = pf->main_vsi;
2034         int ret, i;
2035         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2036         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2037         uint32_t intr_vector = 0;
2038         struct i40e_vsi *vsi;
2039
2040         hw->adapter_stopped = 0;
2041
2042         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2043                 PMD_INIT_LOG(ERR,
2044                 "Invalid link_speeds for port %u, autonegotiation disabled",
2045                               dev->data->port_id);
2046                 return -EINVAL;
2047         }
2048
2049         rte_intr_disable(intr_handle);
2050
2051         if ((rte_intr_cap_multiple(intr_handle) ||
2052              !RTE_ETH_DEV_SRIOV(dev).active) &&
2053             dev->data->dev_conf.intr_conf.rxq != 0) {
2054                 intr_vector = dev->data->nb_rx_queues;
2055                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2056                 if (ret)
2057                         return ret;
2058         }
2059
2060         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2061                 intr_handle->intr_vec =
2062                         rte_zmalloc("intr_vec",
2063                                     dev->data->nb_rx_queues * sizeof(int),
2064                                     0);
2065                 if (!intr_handle->intr_vec) {
2066                         PMD_INIT_LOG(ERR,
2067                                 "Failed to allocate %d rx_queues intr_vec",
2068                                 dev->data->nb_rx_queues);
2069                         return -ENOMEM;
2070                 }
2071         }
2072
2073         /* Initialize VSI */
2074         ret = i40e_dev_rxtx_init(pf);
2075         if (ret != I40E_SUCCESS) {
2076                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2077                 goto err_up;
2078         }
2079
2080         /* Map queues with MSIX interrupt */
2081         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2082                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2083         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2084         i40e_vsi_enable_queues_intr(main_vsi);
2085
2086         /* Map VMDQ VSI queues with MSIX interrupt */
2087         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2088                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2089                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2090                                           I40E_ITR_INDEX_DEFAULT);
2091                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2092         }
2093
2094         /* enable FDIR MSIX interrupt */
2095         if (pf->fdir.fdir_vsi) {
2096                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2097                                           I40E_ITR_INDEX_NONE);
2098                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2099         }
2100
2101         /* Enable all queues which have been configured */
2102         ret = i40e_dev_switch_queues(pf, TRUE);
2103         if (ret != I40E_SUCCESS) {
2104                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2105                 goto err_up;
2106         }
2107
2108         /* Enable receiving broadcast packets */
2109         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2110         if (ret != I40E_SUCCESS)
2111                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2112
2113         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2115                                                 true, NULL);
2116                 if (ret != I40E_SUCCESS)
2117                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2118         }
2119
2120         /* Enable the VLAN promiscuous mode. */
2121         if (pf->vfs) {
2122                 for (i = 0; i < pf->vf_num; i++) {
2123                         vsi = pf->vfs[i].vsi;
2124                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2125                                                      true, NULL);
2126                 }
2127         }
2128
2129         /* Enable mac loopback mode */
2130         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2131             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2132                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2133                 if (ret != I40E_SUCCESS) {
2134                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2135                         goto err_up;
2136                 }
2137         }
2138
2139         /* Apply link configure */
2140         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2141                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2142                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2143                                 ETH_LINK_SPEED_40G)) {
2144                 PMD_DRV_LOG(ERR, "Invalid link setting");
2145                 goto err_up;
2146         }
2147         ret = i40e_apply_link_speed(dev);
2148         if (I40E_SUCCESS != ret) {
2149                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2150                 goto err_up;
2151         }
2152
2153         if (!rte_intr_allow_others(intr_handle)) {
2154                 rte_intr_callback_unregister(intr_handle,
2155                                              i40e_dev_interrupt_handler,
2156                                              (void *)dev);
2157                 /* configure and enable device interrupt */
2158                 i40e_pf_config_irq0(hw, FALSE);
2159                 i40e_pf_enable_irq0(hw);
2160
2161                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2162                         PMD_INIT_LOG(INFO,
2163                                 "lsc won't enable because of no intr multiplex");
2164         } else {
2165                 ret = i40e_aq_set_phy_int_mask(hw,
2166                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2167                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2168                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2169                 if (ret != I40E_SUCCESS)
2170                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2171
2172                 /* Call get_link_info aq commond to enable/disable LSE */
2173                 i40e_dev_link_update(dev, 0);
2174         }
2175
2176         /* enable uio intr after callback register */
2177         rte_intr_enable(intr_handle);
2178
2179         i40e_filter_restore(pf);
2180
2181         if (pf->tm_conf.root && !pf->tm_conf.committed)
2182                 PMD_DRV_LOG(WARNING,
2183                             "please call hierarchy_commit() "
2184                             "before starting the port");
2185
2186         return I40E_SUCCESS;
2187
2188 err_up:
2189         i40e_dev_switch_queues(pf, FALSE);
2190         i40e_dev_clear_queues(dev);
2191
2192         return ret;
2193 }
2194
2195 static void
2196 i40e_dev_stop(struct rte_eth_dev *dev)
2197 {
2198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         struct i40e_vsi *main_vsi = pf->main_vsi;
2201         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2202         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2203         int i;
2204
2205         if (hw->adapter_stopped == 1)
2206                 return;
2207         /* Disable all queues */
2208         i40e_dev_switch_queues(pf, FALSE);
2209
2210         /* un-map queues with interrupt registers */
2211         i40e_vsi_disable_queues_intr(main_vsi);
2212         i40e_vsi_queues_unbind_intr(main_vsi);
2213
2214         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2215                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2216                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2217         }
2218
2219         if (pf->fdir.fdir_vsi) {
2220                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2221                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2222         }
2223         /* Clear all queues and release memory */
2224         i40e_dev_clear_queues(dev);
2225
2226         /* Set link down */
2227         i40e_dev_set_link_down(dev);
2228
2229         if (!rte_intr_allow_others(intr_handle))
2230                 /* resume to the default handler */
2231                 rte_intr_callback_register(intr_handle,
2232                                            i40e_dev_interrupt_handler,
2233                                            (void *)dev);
2234
2235         /* Clean datapath event and queue/vec mapping */
2236         rte_intr_efd_disable(intr_handle);
2237         if (intr_handle->intr_vec) {
2238                 rte_free(intr_handle->intr_vec);
2239                 intr_handle->intr_vec = NULL;
2240         }
2241
2242         /* reset hierarchy commit */
2243         pf->tm_conf.committed = false;
2244
2245         hw->adapter_stopped = 1;
2246 }
2247
2248 static void
2249 i40e_dev_close(struct rte_eth_dev *dev)
2250 {
2251         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2252         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2254         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2255         struct i40e_mirror_rule *p_mirror;
2256         uint32_t reg;
2257         int i;
2258         int ret;
2259
2260         PMD_INIT_FUNC_TRACE();
2261
2262         i40e_dev_stop(dev);
2263
2264         /* Remove all mirror rules */
2265         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2266                 ret = i40e_aq_del_mirror_rule(hw,
2267                                               pf->main_vsi->veb->seid,
2268                                               p_mirror->rule_type,
2269                                               p_mirror->entries,
2270                                               p_mirror->num_entries,
2271                                               p_mirror->id);
2272                 if (ret < 0)
2273                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2274                                     "status = %d, aq_err = %d.", ret,
2275                                     hw->aq.asq_last_status);
2276
2277                 /* remove mirror software resource anyway */
2278                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2279                 rte_free(p_mirror);
2280                 pf->nb_mirror_rule--;
2281         }
2282
2283         i40e_dev_free_queues(dev);
2284
2285         /* Disable interrupt */
2286         i40e_pf_disable_irq0(hw);
2287         rte_intr_disable(intr_handle);
2288
2289         /* shutdown and destroy the HMC */
2290         i40e_shutdown_lan_hmc(hw);
2291
2292         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2293                 i40e_vsi_release(pf->vmdq[i].vsi);
2294                 pf->vmdq[i].vsi = NULL;
2295         }
2296         rte_free(pf->vmdq);
2297         pf->vmdq = NULL;
2298
2299         /* release all the existing VSIs and VEBs */
2300         i40e_fdir_teardown(pf);
2301         i40e_vsi_release(pf->main_vsi);
2302
2303         /* shutdown the adminq */
2304         i40e_aq_queue_shutdown(hw, true);
2305         i40e_shutdown_adminq(hw);
2306
2307         i40e_res_pool_destroy(&pf->qp_pool);
2308         i40e_res_pool_destroy(&pf->msix_pool);
2309
2310         /* Disable flexible payload in global configuration */
2311         if (!pf->support_multi_driver)
2312                 i40e_flex_payload_reg_set_default(hw);
2313
2314         /* force a PF reset to clean anything leftover */
2315         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2316         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2317                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2318         I40E_WRITE_FLUSH(hw);
2319 }
2320
2321 /*
2322  * Reset PF device only to re-initialize resources in PMD layer
2323  */
2324 static int
2325 i40e_dev_reset(struct rte_eth_dev *dev)
2326 {
2327         int ret;
2328
2329         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2330          * its VF to make them align with it. The detailed notification
2331          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2332          * To avoid unexpected behavior in VF, currently reset of PF with
2333          * SR-IOV activation is not supported. It might be supported later.
2334          */
2335         if (dev->data->sriov.active)
2336                 return -ENOTSUP;
2337
2338         ret = eth_i40e_dev_uninit(dev);
2339         if (ret)
2340                 return ret;
2341
2342         ret = eth_i40e_dev_init(dev);
2343
2344         return ret;
2345 }
2346
2347 static void
2348 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2349 {
2350         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2351         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352         struct i40e_vsi *vsi = pf->main_vsi;
2353         int status;
2354
2355         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2356                                                      true, NULL, true);
2357         if (status != I40E_SUCCESS)
2358                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2359
2360         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2361                                                         TRUE, NULL);
2362         if (status != I40E_SUCCESS)
2363                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2364
2365 }
2366
2367 static void
2368 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2369 {
2370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2371         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372         struct i40e_vsi *vsi = pf->main_vsi;
2373         int status;
2374
2375         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2376                                                      false, NULL, true);
2377         if (status != I40E_SUCCESS)
2378                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2379
2380         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2381                                                         false, NULL);
2382         if (status != I40E_SUCCESS)
2383                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2384 }
2385
2386 static void
2387 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2388 {
2389         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2390         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391         struct i40e_vsi *vsi = pf->main_vsi;
2392         int ret;
2393
2394         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2395         if (ret != I40E_SUCCESS)
2396                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2397 }
2398
2399 static void
2400 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2401 {
2402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404         struct i40e_vsi *vsi = pf->main_vsi;
2405         int ret;
2406
2407         if (dev->data->promiscuous == 1)
2408                 return; /* must remain in all_multicast mode */
2409
2410         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2411                                 vsi->seid, FALSE, NULL);
2412         if (ret != I40E_SUCCESS)
2413                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2414 }
2415
2416 /*
2417  * Set device link up.
2418  */
2419 static int
2420 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2421 {
2422         /* re-apply link speed setting */
2423         return i40e_apply_link_speed(dev);
2424 }
2425
2426 /*
2427  * Set device link down.
2428  */
2429 static int
2430 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2431 {
2432         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2433         uint8_t abilities = 0;
2434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435
2436         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2437         return i40e_phy_conf_link(hw, abilities, speed, false);
2438 }
2439
2440 int
2441 i40e_dev_link_update(struct rte_eth_dev *dev,
2442                      int wait_to_complete)
2443 {
2444 #define CHECK_INTERVAL 100  /* 100ms */
2445 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2446         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2447         struct i40e_link_status link_status;
2448         struct rte_eth_link link, old;
2449         int status;
2450         unsigned rep_cnt = MAX_REPEAT_TIME;
2451         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2452
2453         memset(&link, 0, sizeof(link));
2454         memset(&old, 0, sizeof(old));
2455         memset(&link_status, 0, sizeof(link_status));
2456         rte_i40e_dev_atomic_read_link_status(dev, &old);
2457
2458         do {
2459                 /* Get link status information from hardware */
2460                 status = i40e_aq_get_link_info(hw, enable_lse,
2461                                                 &link_status, NULL);
2462                 if (status != I40E_SUCCESS) {
2463                         link.link_speed = ETH_SPEED_NUM_100M;
2464                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2465                         PMD_DRV_LOG(ERR, "Failed to get link info");
2466                         goto out;
2467                 }
2468
2469                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2470                 if (!wait_to_complete || link.link_status)
2471                         break;
2472
2473                 rte_delay_ms(CHECK_INTERVAL);
2474         } while (--rep_cnt);
2475
2476         if (!link.link_status)
2477                 goto out;
2478
2479         /* i40e uses full duplex only */
2480         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2481
2482         /* Parse the link status */
2483         switch (link_status.link_speed) {
2484         case I40E_LINK_SPEED_100MB:
2485                 link.link_speed = ETH_SPEED_NUM_100M;
2486                 break;
2487         case I40E_LINK_SPEED_1GB:
2488                 link.link_speed = ETH_SPEED_NUM_1G;
2489                 break;
2490         case I40E_LINK_SPEED_10GB:
2491                 link.link_speed = ETH_SPEED_NUM_10G;
2492                 break;
2493         case I40E_LINK_SPEED_20GB:
2494                 link.link_speed = ETH_SPEED_NUM_20G;
2495                 break;
2496         case I40E_LINK_SPEED_25GB:
2497                 link.link_speed = ETH_SPEED_NUM_25G;
2498                 break;
2499         case I40E_LINK_SPEED_40GB:
2500                 link.link_speed = ETH_SPEED_NUM_40G;
2501                 break;
2502         default:
2503                 link.link_speed = ETH_SPEED_NUM_100M;
2504                 break;
2505         }
2506
2507         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2508                         ETH_LINK_SPEED_FIXED);
2509
2510 out:
2511         rte_i40e_dev_atomic_write_link_status(dev, &link);
2512         if (link.link_status == old.link_status)
2513                 return -1;
2514
2515         i40e_notify_all_vfs_link_status(dev);
2516
2517         return 0;
2518 }
2519
2520 /* Get all the statistics of a VSI */
2521 void
2522 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2523 {
2524         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2525         struct i40e_eth_stats *nes = &vsi->eth_stats;
2526         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2527         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2528
2529         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2530                             vsi->offset_loaded, &oes->rx_bytes,
2531                             &nes->rx_bytes);
2532         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2533                             vsi->offset_loaded, &oes->rx_unicast,
2534                             &nes->rx_unicast);
2535         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2536                             vsi->offset_loaded, &oes->rx_multicast,
2537                             &nes->rx_multicast);
2538         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2539                             vsi->offset_loaded, &oes->rx_broadcast,
2540                             &nes->rx_broadcast);
2541         /* exclude CRC bytes */
2542         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2543                 nes->rx_broadcast) * ETHER_CRC_LEN;
2544
2545         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2546                             &oes->rx_discards, &nes->rx_discards);
2547         /* GLV_REPC not supported */
2548         /* GLV_RMPC not supported */
2549         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2550                             &oes->rx_unknown_protocol,
2551                             &nes->rx_unknown_protocol);
2552         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2553                             vsi->offset_loaded, &oes->tx_bytes,
2554                             &nes->tx_bytes);
2555         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2556                             vsi->offset_loaded, &oes->tx_unicast,
2557                             &nes->tx_unicast);
2558         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2559                             vsi->offset_loaded, &oes->tx_multicast,
2560                             &nes->tx_multicast);
2561         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2562                             vsi->offset_loaded,  &oes->tx_broadcast,
2563                             &nes->tx_broadcast);
2564         /* GLV_TDPC not supported */
2565         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2566                             &oes->tx_errors, &nes->tx_errors);
2567         vsi->offset_loaded = true;
2568
2569         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2570                     vsi->vsi_id);
2571         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2572         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2573         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2574         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2575         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2576         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2577                     nes->rx_unknown_protocol);
2578         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2579         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2580         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2581         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2582         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2583         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2584         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2585                     vsi->vsi_id);
2586 }
2587
2588 static void
2589 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2590 {
2591         unsigned int i;
2592         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2593         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2594
2595         /* Get rx/tx bytes of internal transfer packets */
2596         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2597                         I40E_GLV_GORCL(hw->port),
2598                         pf->offset_loaded,
2599                         &pf->internal_stats_offset.rx_bytes,
2600                         &pf->internal_stats.rx_bytes);
2601
2602         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2603                         I40E_GLV_GOTCL(hw->port),
2604                         pf->offset_loaded,
2605                         &pf->internal_stats_offset.tx_bytes,
2606                         &pf->internal_stats.tx_bytes);
2607         /* Get total internal rx packet count */
2608         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2609                             I40E_GLV_UPRCL(hw->port),
2610                             pf->offset_loaded,
2611                             &pf->internal_stats_offset.rx_unicast,
2612                             &pf->internal_stats.rx_unicast);
2613         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2614                             I40E_GLV_MPRCL(hw->port),
2615                             pf->offset_loaded,
2616                             &pf->internal_stats_offset.rx_multicast,
2617                             &pf->internal_stats.rx_multicast);
2618         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2619                             I40E_GLV_BPRCL(hw->port),
2620                             pf->offset_loaded,
2621                             &pf->internal_stats_offset.rx_broadcast,
2622                             &pf->internal_stats.rx_broadcast);
2623         /* Get total internal tx packet count */
2624         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2625                             I40E_GLV_UPTCL(hw->port),
2626                             pf->offset_loaded,
2627                             &pf->internal_stats_offset.tx_unicast,
2628                             &pf->internal_stats.tx_unicast);
2629         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2630                             I40E_GLV_MPTCL(hw->port),
2631                             pf->offset_loaded,
2632                             &pf->internal_stats_offset.tx_multicast,
2633                             &pf->internal_stats.tx_multicast);
2634         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2635                             I40E_GLV_BPTCL(hw->port),
2636                             pf->offset_loaded,
2637                             &pf->internal_stats_offset.tx_broadcast,
2638                             &pf->internal_stats.tx_broadcast);
2639
2640         /* exclude CRC size */
2641         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2642                 pf->internal_stats.rx_multicast +
2643                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2644
2645         /* Get statistics of struct i40e_eth_stats */
2646         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2647                             I40E_GLPRT_GORCL(hw->port),
2648                             pf->offset_loaded, &os->eth.rx_bytes,
2649                             &ns->eth.rx_bytes);
2650         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2651                             I40E_GLPRT_UPRCL(hw->port),
2652                             pf->offset_loaded, &os->eth.rx_unicast,
2653                             &ns->eth.rx_unicast);
2654         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2655                             I40E_GLPRT_MPRCL(hw->port),
2656                             pf->offset_loaded, &os->eth.rx_multicast,
2657                             &ns->eth.rx_multicast);
2658         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2659                             I40E_GLPRT_BPRCL(hw->port),
2660                             pf->offset_loaded, &os->eth.rx_broadcast,
2661                             &ns->eth.rx_broadcast);
2662         /* Workaround: CRC size should not be included in byte statistics,
2663          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2664          */
2665         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2666                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2667
2668         /* exclude internal rx bytes
2669          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2670          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2671          * value.
2672          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2673          */
2674         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2675                 ns->eth.rx_bytes = 0;
2676         else
2677                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2678
2679         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2680                 ns->eth.rx_unicast = 0;
2681         else
2682                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2683
2684         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2685                 ns->eth.rx_multicast = 0;
2686         else
2687                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2688
2689         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2690                 ns->eth.rx_broadcast = 0;
2691         else
2692                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2693
2694         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2695                             pf->offset_loaded, &os->eth.rx_discards,
2696                             &ns->eth.rx_discards);
2697         /* GLPRT_REPC not supported */
2698         /* GLPRT_RMPC not supported */
2699         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2700                             pf->offset_loaded,
2701                             &os->eth.rx_unknown_protocol,
2702                             &ns->eth.rx_unknown_protocol);
2703         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2704                             I40E_GLPRT_GOTCL(hw->port),
2705                             pf->offset_loaded, &os->eth.tx_bytes,
2706                             &ns->eth.tx_bytes);
2707         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2708                             I40E_GLPRT_UPTCL(hw->port),
2709                             pf->offset_loaded, &os->eth.tx_unicast,
2710                             &ns->eth.tx_unicast);
2711         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2712                             I40E_GLPRT_MPTCL(hw->port),
2713                             pf->offset_loaded, &os->eth.tx_multicast,
2714                             &ns->eth.tx_multicast);
2715         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2716                             I40E_GLPRT_BPTCL(hw->port),
2717                             pf->offset_loaded, &os->eth.tx_broadcast,
2718                             &ns->eth.tx_broadcast);
2719         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2720                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2721
2722         /* exclude internal tx bytes
2723          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2724          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2725          * value.
2726          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2727          */
2728         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2729                 ns->eth.tx_bytes = 0;
2730         else
2731                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2732
2733         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2734                 ns->eth.tx_unicast = 0;
2735         else
2736                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2737
2738         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2739                 ns->eth.tx_multicast = 0;
2740         else
2741                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2742
2743         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2744                 ns->eth.tx_broadcast = 0;
2745         else
2746                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2747
2748         /* GLPRT_TEPC not supported */
2749
2750         /* additional port specific stats */
2751         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2752                             pf->offset_loaded, &os->tx_dropped_link_down,
2753                             &ns->tx_dropped_link_down);
2754         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2755                             pf->offset_loaded, &os->crc_errors,
2756                             &ns->crc_errors);
2757         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2758                             pf->offset_loaded, &os->illegal_bytes,
2759                             &ns->illegal_bytes);
2760         /* GLPRT_ERRBC not supported */
2761         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2762                             pf->offset_loaded, &os->mac_local_faults,
2763                             &ns->mac_local_faults);
2764         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2765                             pf->offset_loaded, &os->mac_remote_faults,
2766                             &ns->mac_remote_faults);
2767         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2768                             pf->offset_loaded, &os->rx_length_errors,
2769                             &ns->rx_length_errors);
2770         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2771                             pf->offset_loaded, &os->link_xon_rx,
2772                             &ns->link_xon_rx);
2773         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2774                             pf->offset_loaded, &os->link_xoff_rx,
2775                             &ns->link_xoff_rx);
2776         for (i = 0; i < 8; i++) {
2777                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2778                                     pf->offset_loaded,
2779                                     &os->priority_xon_rx[i],
2780                                     &ns->priority_xon_rx[i]);
2781                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2782                                     pf->offset_loaded,
2783                                     &os->priority_xoff_rx[i],
2784                                     &ns->priority_xoff_rx[i]);
2785         }
2786         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2787                             pf->offset_loaded, &os->link_xon_tx,
2788                             &ns->link_xon_tx);
2789         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2790                             pf->offset_loaded, &os->link_xoff_tx,
2791                             &ns->link_xoff_tx);
2792         for (i = 0; i < 8; i++) {
2793                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2794                                     pf->offset_loaded,
2795                                     &os->priority_xon_tx[i],
2796                                     &ns->priority_xon_tx[i]);
2797                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2798                                     pf->offset_loaded,
2799                                     &os->priority_xoff_tx[i],
2800                                     &ns->priority_xoff_tx[i]);
2801                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2802                                     pf->offset_loaded,
2803                                     &os->priority_xon_2_xoff[i],
2804                                     &ns->priority_xon_2_xoff[i]);
2805         }
2806         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2807                             I40E_GLPRT_PRC64L(hw->port),
2808                             pf->offset_loaded, &os->rx_size_64,
2809                             &ns->rx_size_64);
2810         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2811                             I40E_GLPRT_PRC127L(hw->port),
2812                             pf->offset_loaded, &os->rx_size_127,
2813                             &ns->rx_size_127);
2814         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2815                             I40E_GLPRT_PRC255L(hw->port),
2816                             pf->offset_loaded, &os->rx_size_255,
2817                             &ns->rx_size_255);
2818         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2819                             I40E_GLPRT_PRC511L(hw->port),
2820                             pf->offset_loaded, &os->rx_size_511,
2821                             &ns->rx_size_511);
2822         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2823                             I40E_GLPRT_PRC1023L(hw->port),
2824                             pf->offset_loaded, &os->rx_size_1023,
2825                             &ns->rx_size_1023);
2826         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2827                             I40E_GLPRT_PRC1522L(hw->port),
2828                             pf->offset_loaded, &os->rx_size_1522,
2829                             &ns->rx_size_1522);
2830         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2831                             I40E_GLPRT_PRC9522L(hw->port),
2832                             pf->offset_loaded, &os->rx_size_big,
2833                             &ns->rx_size_big);
2834         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2835                             pf->offset_loaded, &os->rx_undersize,
2836                             &ns->rx_undersize);
2837         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2838                             pf->offset_loaded, &os->rx_fragments,
2839                             &ns->rx_fragments);
2840         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2841                             pf->offset_loaded, &os->rx_oversize,
2842                             &ns->rx_oversize);
2843         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2844                             pf->offset_loaded, &os->rx_jabber,
2845                             &ns->rx_jabber);
2846         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2847                             I40E_GLPRT_PTC64L(hw->port),
2848                             pf->offset_loaded, &os->tx_size_64,
2849                             &ns->tx_size_64);
2850         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2851                             I40E_GLPRT_PTC127L(hw->port),
2852                             pf->offset_loaded, &os->tx_size_127,
2853                             &ns->tx_size_127);
2854         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2855                             I40E_GLPRT_PTC255L(hw->port),
2856                             pf->offset_loaded, &os->tx_size_255,
2857                             &ns->tx_size_255);
2858         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2859                             I40E_GLPRT_PTC511L(hw->port),
2860                             pf->offset_loaded, &os->tx_size_511,
2861                             &ns->tx_size_511);
2862         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2863                             I40E_GLPRT_PTC1023L(hw->port),
2864                             pf->offset_loaded, &os->tx_size_1023,
2865                             &ns->tx_size_1023);
2866         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2867                             I40E_GLPRT_PTC1522L(hw->port),
2868                             pf->offset_loaded, &os->tx_size_1522,
2869                             &ns->tx_size_1522);
2870         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2871                             I40E_GLPRT_PTC9522L(hw->port),
2872                             pf->offset_loaded, &os->tx_size_big,
2873                             &ns->tx_size_big);
2874         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2875                            pf->offset_loaded,
2876                            &os->fd_sb_match, &ns->fd_sb_match);
2877         /* GLPRT_MSPDC not supported */
2878         /* GLPRT_XEC not supported */
2879
2880         pf->offset_loaded = true;
2881
2882         if (pf->main_vsi)
2883                 i40e_update_vsi_stats(pf->main_vsi);
2884 }
2885
2886 /* Get all statistics of a port */
2887 static int
2888 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2889 {
2890         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2892         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2893         unsigned i;
2894
2895         /* call read registers - updates values, now write them to struct */
2896         i40e_read_stats_registers(pf, hw);
2897
2898         stats->ipackets = ns->eth.rx_unicast +
2899                         ns->eth.rx_multicast +
2900                         ns->eth.rx_broadcast -
2901                         ns->eth.rx_discards -
2902                         pf->main_vsi->eth_stats.rx_discards;
2903         stats->opackets = ns->eth.tx_unicast +
2904                         ns->eth.tx_multicast +
2905                         ns->eth.tx_broadcast;
2906         stats->ibytes   = ns->eth.rx_bytes;
2907         stats->obytes   = ns->eth.tx_bytes;
2908         stats->oerrors  = ns->eth.tx_errors +
2909                         pf->main_vsi->eth_stats.tx_errors;
2910
2911         /* Rx Errors */
2912         stats->imissed  = ns->eth.rx_discards +
2913                         pf->main_vsi->eth_stats.rx_discards;
2914         stats->ierrors  = ns->crc_errors +
2915                         ns->rx_length_errors + ns->rx_undersize +
2916                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2917
2918         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2919         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2920         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2921         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2922         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2923         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2924         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2925                     ns->eth.rx_unknown_protocol);
2926         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2927         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2928         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2929         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2930         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2931         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2932
2933         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2934                     ns->tx_dropped_link_down);
2935         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2936         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2937                     ns->illegal_bytes);
2938         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2939         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2940                     ns->mac_local_faults);
2941         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2942                     ns->mac_remote_faults);
2943         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2944                     ns->rx_length_errors);
2945         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2946         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2947         for (i = 0; i < 8; i++) {
2948                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2949                                 i, ns->priority_xon_rx[i]);
2950                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2951                                 i, ns->priority_xoff_rx[i]);
2952         }
2953         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2954         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2955         for (i = 0; i < 8; i++) {
2956                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2957                                 i, ns->priority_xon_tx[i]);
2958                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2959                                 i, ns->priority_xoff_tx[i]);
2960                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2961                                 i, ns->priority_xon_2_xoff[i]);
2962         }
2963         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2964         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2965         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2966         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2967         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2968         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2969         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2970         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2971         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2972         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2973         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2974         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2975         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2976         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2977         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2978         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2979         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2980         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2981         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2982                         ns->mac_short_packet_dropped);
2983         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2984                     ns->checksum_error);
2985         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2986         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2987         return 0;
2988 }
2989
2990 /* Reset the statistics */
2991 static void
2992 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2993 {
2994         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2995         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2996
2997         /* Mark PF and VSI stats to update the offset, aka "reset" */
2998         pf->offset_loaded = false;
2999         if (pf->main_vsi)
3000                 pf->main_vsi->offset_loaded = false;
3001
3002         /* read the stats, reading current register values into offset */
3003         i40e_read_stats_registers(pf, hw);
3004 }
3005
3006 static uint32_t
3007 i40e_xstats_calc_num(void)
3008 {
3009         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3010                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3011                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3012 }
3013
3014 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3015                                      struct rte_eth_xstat_name *xstats_names,
3016                                      __rte_unused unsigned limit)
3017 {
3018         unsigned count = 0;
3019         unsigned i, prio;
3020
3021         if (xstats_names == NULL)
3022                 return i40e_xstats_calc_num();
3023
3024         /* Note: limit checked in rte_eth_xstats_names() */
3025
3026         /* Get stats from i40e_eth_stats struct */
3027         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3028                 snprintf(xstats_names[count].name,
3029                          sizeof(xstats_names[count].name),
3030                          "%s", rte_i40e_stats_strings[i].name);
3031                 count++;
3032         }
3033
3034         /* Get individiual stats from i40e_hw_port struct */
3035         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3036                 snprintf(xstats_names[count].name,
3037                         sizeof(xstats_names[count].name),
3038                          "%s", rte_i40e_hw_port_strings[i].name);
3039                 count++;
3040         }
3041
3042         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3043                 for (prio = 0; prio < 8; prio++) {
3044                         snprintf(xstats_names[count].name,
3045                                  sizeof(xstats_names[count].name),
3046                                  "rx_priority%u_%s", prio,
3047                                  rte_i40e_rxq_prio_strings[i].name);
3048                         count++;
3049                 }
3050         }
3051
3052         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3053                 for (prio = 0; prio < 8; prio++) {
3054                         snprintf(xstats_names[count].name,
3055                                  sizeof(xstats_names[count].name),
3056                                  "tx_priority%u_%s", prio,
3057                                  rte_i40e_txq_prio_strings[i].name);
3058                         count++;
3059                 }
3060         }
3061         return count;
3062 }
3063
3064 static int
3065 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3066                     unsigned n)
3067 {
3068         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3069         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3070         unsigned i, count, prio;
3071         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3072
3073         count = i40e_xstats_calc_num();
3074         if (n < count)
3075                 return count;
3076
3077         i40e_read_stats_registers(pf, hw);
3078
3079         if (xstats == NULL)
3080                 return 0;
3081
3082         count = 0;
3083
3084         /* Get stats from i40e_eth_stats struct */
3085         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3086                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3087                         rte_i40e_stats_strings[i].offset);
3088                 xstats[count].id = count;
3089                 count++;
3090         }
3091
3092         /* Get individiual stats from i40e_hw_port struct */
3093         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3094                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3095                         rte_i40e_hw_port_strings[i].offset);
3096                 xstats[count].id = count;
3097                 count++;
3098         }
3099
3100         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3101                 for (prio = 0; prio < 8; prio++) {
3102                         xstats[count].value =
3103                                 *(uint64_t *)(((char *)hw_stats) +
3104                                 rte_i40e_rxq_prio_strings[i].offset +
3105                                 (sizeof(uint64_t) * prio));
3106                         xstats[count].id = count;
3107                         count++;
3108                 }
3109         }
3110
3111         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3112                 for (prio = 0; prio < 8; prio++) {
3113                         xstats[count].value =
3114                                 *(uint64_t *)(((char *)hw_stats) +
3115                                 rte_i40e_txq_prio_strings[i].offset +
3116                                 (sizeof(uint64_t) * prio));
3117                         xstats[count].id = count;
3118                         count++;
3119                 }
3120         }
3121
3122         return count;
3123 }
3124
3125 static int
3126 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3127                                  __rte_unused uint16_t queue_id,
3128                                  __rte_unused uint8_t stat_idx,
3129                                  __rte_unused uint8_t is_rx)
3130 {
3131         PMD_INIT_FUNC_TRACE();
3132
3133         return -ENOSYS;
3134 }
3135
3136 static int
3137 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3138 {
3139         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3140         u32 full_ver;
3141         u8 ver, patch;
3142         u16 build;
3143         int ret;
3144
3145         full_ver = hw->nvm.oem_ver;
3146         ver = (u8)(full_ver >> 24);
3147         build = (u16)((full_ver >> 8) & 0xffff);
3148         patch = (u8)(full_ver & 0xff);
3149
3150         ret = snprintf(fw_version, fw_size,
3151                  "%d.%d%d 0x%08x %d.%d.%d",
3152                  ((hw->nvm.version >> 12) & 0xf),
3153                  ((hw->nvm.version >> 4) & 0xff),
3154                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3155                  ver, build, patch);
3156
3157         ret += 1; /* add the size of '\0' */
3158         if (fw_size < (u32)ret)
3159                 return ret;
3160         else
3161                 return 0;
3162 }
3163
3164 static void
3165 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3166 {
3167         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3168         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169         struct i40e_vsi *vsi = pf->main_vsi;
3170         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3171
3172         dev_info->pci_dev = pci_dev;
3173         dev_info->max_rx_queues = vsi->nb_qps;
3174         dev_info->max_tx_queues = vsi->nb_qps;
3175         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3176         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3177         dev_info->max_mac_addrs = vsi->max_macaddrs;
3178         dev_info->max_vfs = pci_dev->max_vfs;
3179         dev_info->rx_offload_capa =
3180                 DEV_RX_OFFLOAD_VLAN_STRIP |
3181                 DEV_RX_OFFLOAD_QINQ_STRIP |
3182                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3183                 DEV_RX_OFFLOAD_UDP_CKSUM |
3184                 DEV_RX_OFFLOAD_TCP_CKSUM |
3185                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3186                 DEV_RX_OFFLOAD_CRC_STRIP;
3187         dev_info->tx_offload_capa =
3188                 DEV_TX_OFFLOAD_VLAN_INSERT |
3189                 DEV_TX_OFFLOAD_QINQ_INSERT |
3190                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3191                 DEV_TX_OFFLOAD_UDP_CKSUM |
3192                 DEV_TX_OFFLOAD_TCP_CKSUM |
3193                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3194                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3195                 DEV_TX_OFFLOAD_TCP_TSO |
3196                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3197                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3198                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3199                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3200         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3201                                                 sizeof(uint32_t);
3202         dev_info->reta_size = pf->hash_lut_size;
3203         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3204
3205         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3206                 .rx_thresh = {
3207                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3208                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3209                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3210                 },
3211                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3212                 .rx_drop_en = 0,
3213         };
3214
3215         dev_info->default_txconf = (struct rte_eth_txconf) {
3216                 .tx_thresh = {
3217                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3218                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3219                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3220                 },
3221                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3222                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3223                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3224                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3225         };
3226
3227         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3228                 .nb_max = I40E_MAX_RING_DESC,
3229                 .nb_min = I40E_MIN_RING_DESC,
3230                 .nb_align = I40E_ALIGN_RING_DESC,
3231         };
3232
3233         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3234                 .nb_max = I40E_MAX_RING_DESC,
3235                 .nb_min = I40E_MIN_RING_DESC,
3236                 .nb_align = I40E_ALIGN_RING_DESC,
3237                 .nb_seg_max = I40E_TX_MAX_SEG,
3238                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3239         };
3240
3241         if (pf->flags & I40E_FLAG_VMDQ) {
3242                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3243                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3244                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3245                                                 pf->max_nb_vmdq_vsi;
3246                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3247                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3248                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3249         }
3250
3251         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3252                 /* For XL710 */
3253                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3254         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3255                 /* For XXV710 */
3256                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3257         else
3258                 /* For X710 */
3259                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3260 }
3261
3262 static int
3263 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3264 {
3265         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3266         struct i40e_vsi *vsi = pf->main_vsi;
3267         PMD_INIT_FUNC_TRACE();
3268
3269         if (on)
3270                 return i40e_vsi_add_vlan(vsi, vlan_id);
3271         else
3272                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3273 }
3274
3275 static int
3276 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3277                                 enum rte_vlan_type vlan_type,
3278                                 uint16_t tpid, int qinq)
3279 {
3280         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281         uint64_t reg_r = 0;
3282         uint64_t reg_w = 0;
3283         uint16_t reg_id = 3;
3284         int ret;
3285
3286         if (qinq) {
3287                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3288                         reg_id = 2;
3289         }
3290
3291         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3292                                           &reg_r, NULL);
3293         if (ret != I40E_SUCCESS) {
3294                 PMD_DRV_LOG(ERR,
3295                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3296                            reg_id);
3297                 return -EIO;
3298         }
3299         PMD_DRV_LOG(DEBUG,
3300                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3301                     reg_id, reg_r);
3302
3303         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3304         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3305         if (reg_r == reg_w) {
3306                 PMD_DRV_LOG(DEBUG, "No need to write");
3307                 return 0;
3308         }
3309
3310         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3311                                            reg_w, NULL);
3312         if (ret != I40E_SUCCESS) {
3313                 PMD_DRV_LOG(ERR,
3314                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3315                             reg_id);
3316                 return -EIO;
3317         }
3318         PMD_DRV_LOG(DEBUG,
3319                     "Global register 0x%08x is changed with value 0x%08x",
3320                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3321
3322         return 0;
3323 }
3324
3325 static int
3326 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3327                    enum rte_vlan_type vlan_type,
3328                    uint16_t tpid)
3329 {
3330         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3332         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3333         int ret = 0;
3334
3335         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3336              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3337             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3338                 PMD_DRV_LOG(ERR,
3339                             "Unsupported vlan type.");
3340                 return -EINVAL;
3341         }
3342
3343         if (pf->support_multi_driver) {
3344                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3345                 return -ENOTSUP;
3346         }
3347
3348         /* 802.1ad frames ability is added in NVM API 1.7*/
3349         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3350                 if (qinq) {
3351                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3352                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3353                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3354                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3355                 } else {
3356                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3357                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3358                 }
3359                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3360                 if (ret != I40E_SUCCESS) {
3361                         PMD_DRV_LOG(ERR,
3362                                     "Set switch config failed aq_err: %d",
3363                                     hw->aq.asq_last_status);
3364                         ret = -EIO;
3365                 }
3366         } else
3367                 /* If NVM API < 1.7, keep the register setting */
3368                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3369                                                       tpid, qinq);
3370         i40e_global_cfg_warning(I40E_WARNING_TPID);
3371
3372         return ret;
3373 }
3374
3375 static int
3376 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3377 {
3378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3379         struct i40e_vsi *vsi = pf->main_vsi;
3380
3381         if (mask & ETH_VLAN_FILTER_MASK) {
3382                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3383                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3384                 else
3385                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3386         }
3387
3388         if (mask & ETH_VLAN_STRIP_MASK) {
3389                 /* Enable or disable VLAN stripping */
3390                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3391                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3392                 else
3393                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3394         }
3395
3396         if (mask & ETH_VLAN_EXTEND_MASK) {
3397                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3398                         i40e_vsi_config_double_vlan(vsi, TRUE);
3399                         /* Set global registers with default ethertype. */
3400                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3401                                            ETHER_TYPE_VLAN);
3402                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3403                                            ETHER_TYPE_VLAN);
3404                 }
3405                 else
3406                         i40e_vsi_config_double_vlan(vsi, FALSE);
3407         }
3408
3409         return 0;
3410 }
3411
3412 static void
3413 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3414                           __rte_unused uint16_t queue,
3415                           __rte_unused int on)
3416 {
3417         PMD_INIT_FUNC_TRACE();
3418 }
3419
3420 static int
3421 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3422 {
3423         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3424         struct i40e_vsi *vsi = pf->main_vsi;
3425         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3426         struct i40e_vsi_vlan_pvid_info info;
3427
3428         memset(&info, 0, sizeof(info));
3429         info.on = on;
3430         if (info.on)
3431                 info.config.pvid = pvid;
3432         else {
3433                 info.config.reject.tagged =
3434                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3435                 info.config.reject.untagged =
3436                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3437         }
3438
3439         return i40e_vsi_vlan_pvid_set(vsi, &info);
3440 }
3441
3442 static int
3443 i40e_dev_led_on(struct rte_eth_dev *dev)
3444 {
3445         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3446         uint32_t mode = i40e_led_get(hw);
3447
3448         if (mode == 0)
3449                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3450
3451         return 0;
3452 }
3453
3454 static int
3455 i40e_dev_led_off(struct rte_eth_dev *dev)
3456 {
3457         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458         uint32_t mode = i40e_led_get(hw);
3459
3460         if (mode != 0)
3461                 i40e_led_set(hw, 0, false);
3462
3463         return 0;
3464 }
3465
3466 static int
3467 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3468 {
3469         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3470         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3471
3472         fc_conf->pause_time = pf->fc_conf.pause_time;
3473
3474         /* read out from register, in case they are modified by other port */
3475         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3476                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3477         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3478                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3479
3480         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3481         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3482
3483          /* Return current mode according to actual setting*/
3484         switch (hw->fc.current_mode) {
3485         case I40E_FC_FULL:
3486                 fc_conf->mode = RTE_FC_FULL;
3487                 break;
3488         case I40E_FC_TX_PAUSE:
3489                 fc_conf->mode = RTE_FC_TX_PAUSE;
3490                 break;
3491         case I40E_FC_RX_PAUSE:
3492                 fc_conf->mode = RTE_FC_RX_PAUSE;
3493                 break;
3494         case I40E_FC_NONE:
3495         default:
3496                 fc_conf->mode = RTE_FC_NONE;
3497         };
3498
3499         return 0;
3500 }
3501
3502 static int
3503 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3504 {
3505         uint32_t mflcn_reg, fctrl_reg, reg;
3506         uint32_t max_high_water;
3507         uint8_t i, aq_failure;
3508         int err;
3509         struct i40e_hw *hw;
3510         struct i40e_pf *pf;
3511         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3512                 [RTE_FC_NONE] = I40E_FC_NONE,
3513                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3514                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3515                 [RTE_FC_FULL] = I40E_FC_FULL
3516         };
3517
3518         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3519
3520         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3521         if ((fc_conf->high_water > max_high_water) ||
3522                         (fc_conf->high_water < fc_conf->low_water)) {
3523                 PMD_INIT_LOG(ERR,
3524                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3525                         max_high_water);
3526                 return -EINVAL;
3527         }
3528
3529         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3530         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3531         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3532
3533         pf->fc_conf.pause_time = fc_conf->pause_time;
3534         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3535         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3536
3537         PMD_INIT_FUNC_TRACE();
3538
3539         /* All the link flow control related enable/disable register
3540          * configuration is handle by the F/W
3541          */
3542         err = i40e_set_fc(hw, &aq_failure, true);
3543         if (err < 0)
3544                 return -ENOSYS;
3545
3546         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3547                 /* Configure flow control refresh threshold,
3548                  * the value for stat_tx_pause_refresh_timer[8]
3549                  * is used for global pause operation.
3550                  */
3551
3552                 I40E_WRITE_REG(hw,
3553                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3554                                pf->fc_conf.pause_time);
3555
3556                 /* configure the timer value included in transmitted pause
3557                  * frame,
3558                  * the value for stat_tx_pause_quanta[8] is used for global
3559                  * pause operation
3560                  */
3561                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3562                                pf->fc_conf.pause_time);
3563
3564                 fctrl_reg = I40E_READ_REG(hw,
3565                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3566
3567                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3568                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3569                 else
3570                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3571
3572                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3573                                fctrl_reg);
3574         } else {
3575                 /* Configure pause time (2 TCs per register) */
3576                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3577                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3578                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3579
3580                 /* Configure flow control refresh threshold value */
3581                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3582                                pf->fc_conf.pause_time / 2);
3583
3584                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3585
3586                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3587                  *depending on configuration
3588                  */
3589                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3590                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3591                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3592                 } else {
3593                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3594                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3595                 }
3596
3597                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3598         }
3599
3600         if (!pf->support_multi_driver) {
3601                 /* config water marker both based on the packets and bytes */
3602                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3603                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3604                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3605                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3606                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3607                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3608                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3609                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3610                                   << I40E_KILOSHIFT);
3611                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3612                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3613                                    << I40E_KILOSHIFT);
3614                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3615         } else {
3616                 PMD_DRV_LOG(ERR,
3617                             "Water marker configuration is not supported.");
3618         }
3619
3620         I40E_WRITE_FLUSH(hw);
3621
3622         return 0;
3623 }
3624
3625 static int
3626 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3627                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3628 {
3629         PMD_INIT_FUNC_TRACE();
3630
3631         return -ENOSYS;
3632 }
3633
3634 /* Add a MAC address, and update filters */
3635 static int
3636 i40e_macaddr_add(struct rte_eth_dev *dev,
3637                  struct ether_addr *mac_addr,
3638                  __rte_unused uint32_t index,
3639                  uint32_t pool)
3640 {
3641         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3642         struct i40e_mac_filter_info mac_filter;
3643         struct i40e_vsi *vsi;
3644         int ret;
3645
3646         /* If VMDQ not enabled or configured, return */
3647         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3648                           !pf->nb_cfg_vmdq_vsi)) {
3649                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3650                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3651                         pool);
3652                 return -ENOTSUP;
3653         }
3654
3655         if (pool > pf->nb_cfg_vmdq_vsi) {
3656                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3657                                 pool, pf->nb_cfg_vmdq_vsi);
3658                 return -EINVAL;
3659         }
3660
3661         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3662         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3663                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3664         else
3665                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3666
3667         if (pool == 0)
3668                 vsi = pf->main_vsi;
3669         else
3670                 vsi = pf->vmdq[pool - 1].vsi;
3671
3672         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3673         if (ret != I40E_SUCCESS) {
3674                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3675                 return -ENODEV;
3676         }
3677         return 0;
3678 }
3679
3680 /* Remove a MAC address, and update filters */
3681 static void
3682 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3683 {
3684         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3685         struct i40e_vsi *vsi;
3686         struct rte_eth_dev_data *data = dev->data;
3687         struct ether_addr *macaddr;
3688         int ret;
3689         uint32_t i;
3690         uint64_t pool_sel;
3691
3692         macaddr = &(data->mac_addrs[index]);
3693
3694         pool_sel = dev->data->mac_pool_sel[index];
3695
3696         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3697                 if (pool_sel & (1ULL << i)) {
3698                         if (i == 0)
3699                                 vsi = pf->main_vsi;
3700                         else {
3701                                 /* No VMDQ pool enabled or configured */
3702                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3703                                         (i > pf->nb_cfg_vmdq_vsi)) {
3704                                         PMD_DRV_LOG(ERR,
3705                                                 "No VMDQ pool enabled/configured");
3706                                         return;
3707                                 }
3708                                 vsi = pf->vmdq[i - 1].vsi;
3709                         }
3710                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3711
3712                         if (ret) {
3713                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3714                                 return;
3715                         }
3716                 }
3717         }
3718 }
3719
3720 /* Set perfect match or hash match of MAC and VLAN for a VF */
3721 static int
3722 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3723                  struct rte_eth_mac_filter *filter,
3724                  bool add)
3725 {
3726         struct i40e_hw *hw;
3727         struct i40e_mac_filter_info mac_filter;
3728         struct ether_addr old_mac;
3729         struct ether_addr *new_mac;
3730         struct i40e_pf_vf *vf = NULL;
3731         uint16_t vf_id;
3732         int ret;
3733
3734         if (pf == NULL) {
3735                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3736                 return -EINVAL;
3737         }
3738         hw = I40E_PF_TO_HW(pf);
3739
3740         if (filter == NULL) {
3741                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3742                 return -EINVAL;
3743         }
3744
3745         new_mac = &filter->mac_addr;
3746
3747         if (is_zero_ether_addr(new_mac)) {
3748                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3749                 return -EINVAL;
3750         }
3751
3752         vf_id = filter->dst_id;
3753
3754         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3755                 PMD_DRV_LOG(ERR, "Invalid argument.");
3756                 return -EINVAL;
3757         }
3758         vf = &pf->vfs[vf_id];
3759
3760         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3761                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3762                 return -EINVAL;
3763         }
3764
3765         if (add) {
3766                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3767                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3768                                 ETHER_ADDR_LEN);
3769                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3770                                  ETHER_ADDR_LEN);
3771
3772                 mac_filter.filter_type = filter->filter_type;
3773                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3774                 if (ret != I40E_SUCCESS) {
3775                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3776                         return -1;
3777                 }
3778                 ether_addr_copy(new_mac, &pf->dev_addr);
3779         } else {
3780                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3781                                 ETHER_ADDR_LEN);
3782                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3783                 if (ret != I40E_SUCCESS) {
3784                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3785                         return -1;
3786                 }
3787
3788                 /* Clear device address as it has been removed */
3789                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3790                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3791         }
3792
3793         return 0;
3794 }
3795
3796 /* MAC filter handle */
3797 static int
3798 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3799                 void *arg)
3800 {
3801         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3802         struct rte_eth_mac_filter *filter;
3803         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3804         int ret = I40E_NOT_SUPPORTED;
3805
3806         filter = (struct rte_eth_mac_filter *)(arg);
3807
3808         switch (filter_op) {
3809         case RTE_ETH_FILTER_NOP:
3810                 ret = I40E_SUCCESS;
3811                 break;
3812         case RTE_ETH_FILTER_ADD:
3813                 i40e_pf_disable_irq0(hw);
3814                 if (filter->is_vf)
3815                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3816                 i40e_pf_enable_irq0(hw);
3817                 break;
3818         case RTE_ETH_FILTER_DELETE:
3819                 i40e_pf_disable_irq0(hw);
3820                 if (filter->is_vf)
3821                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3822                 i40e_pf_enable_irq0(hw);
3823                 break;
3824         default:
3825                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3826                 ret = I40E_ERR_PARAM;
3827                 break;
3828         }
3829
3830         return ret;
3831 }
3832
3833 static int
3834 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3835 {
3836         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3837         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3838         uint32_t reg;
3839         int ret;
3840
3841         if (!lut)
3842                 return -EINVAL;
3843
3844         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3845                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3846                                           lut, lut_size);
3847                 if (ret) {
3848                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3849                         return ret;
3850                 }
3851         } else {
3852                 uint32_t *lut_dw = (uint32_t *)lut;
3853                 uint16_t i, lut_size_dw = lut_size / 4;
3854
3855                 if (vsi->type == I40E_VSI_SRIOV) {
3856                         for (i = 0; i <= lut_size_dw; i++) {
3857                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3858                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3859                         }
3860                 } else {
3861                         for (i = 0; i < lut_size_dw; i++)
3862                                 lut_dw[i] = I40E_READ_REG(hw,
3863                                                           I40E_PFQF_HLUT(i));
3864                 }
3865         }
3866
3867         return 0;
3868 }
3869
3870 int
3871 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3872 {
3873         struct i40e_pf *pf;
3874         struct i40e_hw *hw;
3875         int ret;
3876
3877         if (!vsi || !lut)
3878                 return -EINVAL;
3879
3880         pf = I40E_VSI_TO_PF(vsi);
3881         hw = I40E_VSI_TO_HW(vsi);
3882
3883         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3884                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3885                                           lut, lut_size);
3886                 if (ret) {
3887                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3888                         return ret;
3889                 }
3890         } else {
3891                 uint32_t *lut_dw = (uint32_t *)lut;
3892                 uint16_t i, lut_size_dw = lut_size / 4;
3893
3894                 if (vsi->type == I40E_VSI_SRIOV) {
3895                         for (i = 0; i < lut_size_dw; i++)
3896                                 I40E_WRITE_REG(
3897                                         hw,
3898                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3899                                         lut_dw[i]);
3900                 } else {
3901                         for (i = 0; i < lut_size_dw; i++)
3902                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3903                                                lut_dw[i]);
3904                 }
3905                 I40E_WRITE_FLUSH(hw);
3906         }
3907
3908         return 0;
3909 }
3910
3911 static int
3912 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3913                          struct rte_eth_rss_reta_entry64 *reta_conf,
3914                          uint16_t reta_size)
3915 {
3916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3917         uint16_t i, lut_size = pf->hash_lut_size;
3918         uint16_t idx, shift;
3919         uint8_t *lut;
3920         int ret;
3921
3922         if (reta_size != lut_size ||
3923                 reta_size > ETH_RSS_RETA_SIZE_512) {
3924                 PMD_DRV_LOG(ERR,
3925                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3926                         reta_size, lut_size);
3927                 return -EINVAL;
3928         }
3929
3930         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3931         if (!lut) {
3932                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3933                 return -ENOMEM;
3934         }
3935         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3936         if (ret)
3937                 goto out;
3938         for (i = 0; i < reta_size; i++) {
3939                 idx = i / RTE_RETA_GROUP_SIZE;
3940                 shift = i % RTE_RETA_GROUP_SIZE;
3941                 if (reta_conf[idx].mask & (1ULL << shift))
3942                         lut[i] = reta_conf[idx].reta[shift];
3943         }
3944         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3945
3946 out:
3947         rte_free(lut);
3948
3949         return ret;
3950 }
3951
3952 static int
3953 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3954                         struct rte_eth_rss_reta_entry64 *reta_conf,
3955                         uint16_t reta_size)
3956 {
3957         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3958         uint16_t i, lut_size = pf->hash_lut_size;
3959         uint16_t idx, shift;
3960         uint8_t *lut;
3961         int ret;
3962
3963         if (reta_size != lut_size ||
3964                 reta_size > ETH_RSS_RETA_SIZE_512) {
3965                 PMD_DRV_LOG(ERR,
3966                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3967                         reta_size, lut_size);
3968                 return -EINVAL;
3969         }
3970
3971         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3972         if (!lut) {
3973                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3974                 return -ENOMEM;
3975         }
3976
3977         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3978         if (ret)
3979                 goto out;
3980         for (i = 0; i < reta_size; i++) {
3981                 idx = i / RTE_RETA_GROUP_SIZE;
3982                 shift = i % RTE_RETA_GROUP_SIZE;
3983                 if (reta_conf[idx].mask & (1ULL << shift))
3984                         reta_conf[idx].reta[shift] = lut[i];
3985         }
3986
3987 out:
3988         rte_free(lut);
3989
3990         return ret;
3991 }
3992
3993 /**
3994  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3995  * @hw:   pointer to the HW structure
3996  * @mem:  pointer to mem struct to fill out
3997  * @size: size of memory requested
3998  * @alignment: what to align the allocation to
3999  **/
4000 enum i40e_status_code
4001 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4002                         struct i40e_dma_mem *mem,
4003                         u64 size,
4004                         u32 alignment)
4005 {
4006         const struct rte_memzone *mz = NULL;
4007         char z_name[RTE_MEMZONE_NAMESIZE];
4008
4009         if (!mem)
4010                 return I40E_ERR_PARAM;
4011
4012         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4013         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
4014                                          alignment, RTE_PGSIZE_2M);
4015         if (!mz)
4016                 return I40E_ERR_NO_MEMORY;
4017
4018         mem->size = size;
4019         mem->va = mz->addr;
4020         mem->pa = mz->iova;
4021         mem->zone = (const void *)mz;
4022         PMD_DRV_LOG(DEBUG,
4023                 "memzone %s allocated with physical address: %"PRIu64,
4024                 mz->name, mem->pa);
4025
4026         return I40E_SUCCESS;
4027 }
4028
4029 /**
4030  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4031  * @hw:   pointer to the HW structure
4032  * @mem:  ptr to mem struct to free
4033  **/
4034 enum i40e_status_code
4035 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4036                     struct i40e_dma_mem *mem)
4037 {
4038         if (!mem)
4039                 return I40E_ERR_PARAM;
4040
4041         PMD_DRV_LOG(DEBUG,
4042                 "memzone %s to be freed with physical address: %"PRIu64,
4043                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4044         rte_memzone_free((const struct rte_memzone *)mem->zone);
4045         mem->zone = NULL;
4046         mem->va = NULL;
4047         mem->pa = (u64)0;
4048
4049         return I40E_SUCCESS;
4050 }
4051
4052 /**
4053  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4054  * @hw:   pointer to the HW structure
4055  * @mem:  pointer to mem struct to fill out
4056  * @size: size of memory requested
4057  **/
4058 enum i40e_status_code
4059 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4060                          struct i40e_virt_mem *mem,
4061                          u32 size)
4062 {
4063         if (!mem)
4064                 return I40E_ERR_PARAM;
4065
4066         mem->size = size;
4067         mem->va = rte_zmalloc("i40e", size, 0);
4068
4069         if (mem->va)
4070                 return I40E_SUCCESS;
4071         else
4072                 return I40E_ERR_NO_MEMORY;
4073 }
4074
4075 /**
4076  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4077  * @hw:   pointer to the HW structure
4078  * @mem:  pointer to mem struct to free
4079  **/
4080 enum i40e_status_code
4081 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4082                      struct i40e_virt_mem *mem)
4083 {
4084         if (!mem)
4085                 return I40E_ERR_PARAM;
4086
4087         rte_free(mem->va);
4088         mem->va = NULL;
4089
4090         return I40E_SUCCESS;
4091 }
4092
4093 void
4094 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4095 {
4096         rte_spinlock_init(&sp->spinlock);
4097 }
4098
4099 void
4100 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4101 {
4102         rte_spinlock_lock(&sp->spinlock);
4103 }
4104
4105 void
4106 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4107 {
4108         rte_spinlock_unlock(&sp->spinlock);
4109 }
4110
4111 void
4112 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4113 {
4114         return;
4115 }
4116
4117 /**
4118  * Get the hardware capabilities, which will be parsed
4119  * and saved into struct i40e_hw.
4120  */
4121 static int
4122 i40e_get_cap(struct i40e_hw *hw)
4123 {
4124         struct i40e_aqc_list_capabilities_element_resp *buf;
4125         uint16_t len, size = 0;
4126         int ret;
4127
4128         /* Calculate a huge enough buff for saving response data temporarily */
4129         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4130                                                 I40E_MAX_CAP_ELE_NUM;
4131         buf = rte_zmalloc("i40e", len, 0);
4132         if (!buf) {
4133                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4134                 return I40E_ERR_NO_MEMORY;
4135         }
4136
4137         /* Get, parse the capabilities and save it to hw */
4138         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4139                         i40e_aqc_opc_list_func_capabilities, NULL);
4140         if (ret != I40E_SUCCESS)
4141                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4142
4143         /* Free the temporary buffer after being used */
4144         rte_free(buf);
4145
4146         return ret;
4147 }
4148
4149 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4150 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4151
4152 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4153                 const char *value,
4154                 void *opaque)
4155 {
4156         struct i40e_pf *pf;
4157         unsigned long num;
4158         char *end;
4159
4160         pf = (struct i40e_pf *)opaque;
4161         RTE_SET_USED(key);
4162
4163         errno = 0;
4164         num = strtoul(value, &end, 0);
4165         if (errno != 0 || end == value || *end != 0) {
4166                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4167                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4168                 return -(EINVAL);
4169         }
4170
4171         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4172                 pf->vf_nb_qp_max = (uint16_t)num;
4173         else
4174                 /* here return 0 to make next valid same argument work */
4175                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4176                             "power of 2 and equal or less than 16 !, Now it is "
4177                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4178
4179         return 0;
4180 }
4181
4182 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4183 {
4184         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4185         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4186         struct rte_kvargs *kvlist;
4187
4188         /* set default queue number per VF as 4 */
4189         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4190
4191         if (dev->device->devargs == NULL)
4192                 return 0;
4193
4194         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4195         if (kvlist == NULL)
4196                 return -(EINVAL);
4197
4198         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4199                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4200                             "the first invalid or last valid one is used !",
4201                             QUEUE_NUM_PER_VF_ARG);
4202
4203         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4204                            i40e_pf_parse_vf_queue_number_handler, pf);
4205
4206         rte_kvargs_free(kvlist);
4207
4208         return 0;
4209 }
4210
4211 static int
4212 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4213 {
4214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4215         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4216         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4217         uint16_t qp_count = 0, vsi_count = 0;
4218
4219         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4220                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4221                 return -EINVAL;
4222         }
4223
4224         i40e_pf_config_vf_rxq_number(dev);
4225
4226         /* Add the parameter init for LFC */
4227         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4228         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4229         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4230
4231         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4232         pf->max_num_vsi = hw->func_caps.num_vsis;
4233         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4234         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4235
4236         /* FDir queue/VSI allocation */
4237         pf->fdir_qp_offset = 0;
4238         if (hw->func_caps.fd) {
4239                 pf->flags |= I40E_FLAG_FDIR;
4240                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4241         } else {
4242                 pf->fdir_nb_qps = 0;
4243         }
4244         qp_count += pf->fdir_nb_qps;
4245         vsi_count += 1;
4246
4247         /* LAN queue/VSI allocation */
4248         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4249         if (!hw->func_caps.rss) {
4250                 pf->lan_nb_qps = 1;
4251         } else {
4252                 pf->flags |= I40E_FLAG_RSS;
4253                 if (hw->mac.type == I40E_MAC_X722)
4254                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4255                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4256         }
4257         qp_count += pf->lan_nb_qps;
4258         vsi_count += 1;
4259
4260         /* VF queue/VSI allocation */
4261         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4262         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4263                 pf->flags |= I40E_FLAG_SRIOV;
4264                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4265                 pf->vf_num = pci_dev->max_vfs;
4266                 PMD_DRV_LOG(DEBUG,
4267                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4268                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4269         } else {
4270                 pf->vf_nb_qps = 0;
4271                 pf->vf_num = 0;
4272         }
4273         qp_count += pf->vf_nb_qps * pf->vf_num;
4274         vsi_count += pf->vf_num;
4275
4276         /* VMDq queue/VSI allocation */
4277         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4278         pf->vmdq_nb_qps = 0;
4279         pf->max_nb_vmdq_vsi = 0;
4280         if (hw->func_caps.vmdq) {
4281                 if (qp_count < hw->func_caps.num_tx_qp &&
4282                         vsi_count < hw->func_caps.num_vsis) {
4283                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4284                                 qp_count) / pf->vmdq_nb_qp_max;
4285
4286                         /* Limit the maximum number of VMDq vsi to the maximum
4287                          * ethdev can support
4288                          */
4289                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4290                                 hw->func_caps.num_vsis - vsi_count);
4291                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4292                                 ETH_64_POOLS);
4293                         if (pf->max_nb_vmdq_vsi) {
4294                                 pf->flags |= I40E_FLAG_VMDQ;
4295                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4296                                 PMD_DRV_LOG(DEBUG,
4297                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4298                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4299                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4300                         } else {
4301                                 PMD_DRV_LOG(INFO,
4302                                         "No enough queues left for VMDq");
4303                         }
4304                 } else {
4305                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4306                 }
4307         }
4308         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4309         vsi_count += pf->max_nb_vmdq_vsi;
4310
4311         if (hw->func_caps.dcb)
4312                 pf->flags |= I40E_FLAG_DCB;
4313
4314         if (qp_count > hw->func_caps.num_tx_qp) {
4315                 PMD_DRV_LOG(ERR,
4316                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4317                         qp_count, hw->func_caps.num_tx_qp);
4318                 return -EINVAL;
4319         }
4320         if (vsi_count > hw->func_caps.num_vsis) {
4321                 PMD_DRV_LOG(ERR,
4322                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4323                         vsi_count, hw->func_caps.num_vsis);
4324                 return -EINVAL;
4325         }
4326
4327         return 0;
4328 }
4329
4330 static int
4331 i40e_pf_get_switch_config(struct i40e_pf *pf)
4332 {
4333         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4334         struct i40e_aqc_get_switch_config_resp *switch_config;
4335         struct i40e_aqc_switch_config_element_resp *element;
4336         uint16_t start_seid = 0, num_reported;
4337         int ret;
4338
4339         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4340                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4341         if (!switch_config) {
4342                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4343                 return -ENOMEM;
4344         }
4345
4346         /* Get the switch configurations */
4347         ret = i40e_aq_get_switch_config(hw, switch_config,
4348                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4349         if (ret != I40E_SUCCESS) {
4350                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4351                 goto fail;
4352         }
4353         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4354         if (num_reported != 1) { /* The number should be 1 */
4355                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4356                 goto fail;
4357         }
4358
4359         /* Parse the switch configuration elements */
4360         element = &(switch_config->element[0]);
4361         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4362                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4363                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4364         } else
4365                 PMD_DRV_LOG(INFO, "Unknown element type");
4366
4367 fail:
4368         rte_free(switch_config);
4369
4370         return ret;
4371 }
4372
4373 static int
4374 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4375                         uint32_t num)
4376 {
4377         struct pool_entry *entry;
4378
4379         if (pool == NULL || num == 0)
4380                 return -EINVAL;
4381
4382         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4383         if (entry == NULL) {
4384                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4385                 return -ENOMEM;
4386         }
4387
4388         /* queue heap initialize */
4389         pool->num_free = num;
4390         pool->num_alloc = 0;
4391         pool->base = base;
4392         LIST_INIT(&pool->alloc_list);
4393         LIST_INIT(&pool->free_list);
4394
4395         /* Initialize element  */
4396         entry->base = 0;
4397         entry->len = num;
4398
4399         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4400         return 0;
4401 }
4402
4403 static void
4404 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4405 {
4406         struct pool_entry *entry, *next_entry;
4407
4408         if (pool == NULL)
4409                 return;
4410
4411         for (entry = LIST_FIRST(&pool->alloc_list);
4412                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4413                         entry = next_entry) {
4414                 LIST_REMOVE(entry, next);
4415                 rte_free(entry);
4416         }
4417
4418         for (entry = LIST_FIRST(&pool->free_list);
4419                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4420                         entry = next_entry) {
4421                 LIST_REMOVE(entry, next);
4422                 rte_free(entry);
4423         }
4424
4425         pool->num_free = 0;
4426         pool->num_alloc = 0;
4427         pool->base = 0;
4428         LIST_INIT(&pool->alloc_list);
4429         LIST_INIT(&pool->free_list);
4430 }
4431
4432 static int
4433 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4434                        uint32_t base)
4435 {
4436         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4437         uint32_t pool_offset;
4438         int insert;
4439
4440         if (pool == NULL) {
4441                 PMD_DRV_LOG(ERR, "Invalid parameter");
4442                 return -EINVAL;
4443         }
4444
4445         pool_offset = base - pool->base;
4446         /* Lookup in alloc list */
4447         LIST_FOREACH(entry, &pool->alloc_list, next) {
4448                 if (entry->base == pool_offset) {
4449                         valid_entry = entry;
4450                         LIST_REMOVE(entry, next);
4451                         break;
4452                 }
4453         }
4454
4455         /* Not find, return */
4456         if (valid_entry == NULL) {
4457                 PMD_DRV_LOG(ERR, "Failed to find entry");
4458                 return -EINVAL;
4459         }
4460
4461         /**
4462          * Found it, move it to free list  and try to merge.
4463          * In order to make merge easier, always sort it by qbase.
4464          * Find adjacent prev and last entries.
4465          */
4466         prev = next = NULL;
4467         LIST_FOREACH(entry, &pool->free_list, next) {
4468                 if (entry->base > valid_entry->base) {
4469                         next = entry;
4470                         break;
4471                 }
4472                 prev = entry;
4473         }
4474
4475         insert = 0;
4476         /* Try to merge with next one*/
4477         if (next != NULL) {
4478                 /* Merge with next one */
4479                 if (valid_entry->base + valid_entry->len == next->base) {
4480                         next->base = valid_entry->base;
4481                         next->len += valid_entry->len;
4482                         rte_free(valid_entry);
4483                         valid_entry = next;
4484                         insert = 1;
4485                 }
4486         }
4487
4488         if (prev != NULL) {
4489                 /* Merge with previous one */
4490                 if (prev->base + prev->len == valid_entry->base) {
4491                         prev->len += valid_entry->len;
4492                         /* If it merge with next one, remove next node */
4493                         if (insert == 1) {
4494                                 LIST_REMOVE(valid_entry, next);
4495                                 rte_free(valid_entry);
4496                         } else {
4497                                 rte_free(valid_entry);
4498                                 insert = 1;
4499                         }
4500                 }
4501         }
4502
4503         /* Not find any entry to merge, insert */
4504         if (insert == 0) {
4505                 if (prev != NULL)
4506                         LIST_INSERT_AFTER(prev, valid_entry, next);
4507                 else if (next != NULL)
4508                         LIST_INSERT_BEFORE(next, valid_entry, next);
4509                 else /* It's empty list, insert to head */
4510                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4511         }
4512
4513         pool->num_free += valid_entry->len;
4514         pool->num_alloc -= valid_entry->len;
4515
4516         return 0;
4517 }
4518
4519 static int
4520 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4521                        uint16_t num)
4522 {
4523         struct pool_entry *entry, *valid_entry;
4524
4525         if (pool == NULL || num == 0) {
4526                 PMD_DRV_LOG(ERR, "Invalid parameter");
4527                 return -EINVAL;
4528         }
4529
4530         if (pool->num_free < num) {
4531                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4532                             num, pool->num_free);
4533                 return -ENOMEM;
4534         }
4535
4536         valid_entry = NULL;
4537         /* Lookup  in free list and find most fit one */
4538         LIST_FOREACH(entry, &pool->free_list, next) {
4539                 if (entry->len >= num) {
4540                         /* Find best one */
4541                         if (entry->len == num) {
4542                                 valid_entry = entry;
4543                                 break;
4544                         }
4545                         if (valid_entry == NULL || valid_entry->len > entry->len)
4546                                 valid_entry = entry;
4547                 }
4548         }
4549
4550         /* Not find one to satisfy the request, return */
4551         if (valid_entry == NULL) {
4552                 PMD_DRV_LOG(ERR, "No valid entry found");
4553                 return -ENOMEM;
4554         }
4555         /**
4556          * The entry have equal queue number as requested,
4557          * remove it from alloc_list.
4558          */
4559         if (valid_entry->len == num) {
4560                 LIST_REMOVE(valid_entry, next);
4561         } else {
4562                 /**
4563                  * The entry have more numbers than requested,
4564                  * create a new entry for alloc_list and minus its
4565                  * queue base and number in free_list.
4566                  */
4567                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4568                 if (entry == NULL) {
4569                         PMD_DRV_LOG(ERR,
4570                                 "Failed to allocate memory for resource pool");
4571                         return -ENOMEM;
4572                 }
4573                 entry->base = valid_entry->base;
4574                 entry->len = num;
4575                 valid_entry->base += num;
4576                 valid_entry->len -= num;
4577                 valid_entry = entry;
4578         }
4579
4580         /* Insert it into alloc list, not sorted */
4581         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4582
4583         pool->num_free -= valid_entry->len;
4584         pool->num_alloc += valid_entry->len;
4585
4586         return valid_entry->base + pool->base;
4587 }
4588
4589 /**
4590  * bitmap_is_subset - Check whether src2 is subset of src1
4591  **/
4592 static inline int
4593 bitmap_is_subset(uint8_t src1, uint8_t src2)
4594 {
4595         return !((src1 ^ src2) & src2);
4596 }
4597
4598 static enum i40e_status_code
4599 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4600 {
4601         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4602
4603         /* If DCB is not supported, only default TC is supported */
4604         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4605                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4606                 return I40E_NOT_SUPPORTED;
4607         }
4608
4609         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4610                 PMD_DRV_LOG(ERR,
4611                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4612                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4613                 return I40E_NOT_SUPPORTED;
4614         }
4615         return I40E_SUCCESS;
4616 }
4617
4618 int
4619 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4620                                 struct i40e_vsi_vlan_pvid_info *info)
4621 {
4622         struct i40e_hw *hw;
4623         struct i40e_vsi_context ctxt;
4624         uint8_t vlan_flags = 0;
4625         int ret;
4626
4627         if (vsi == NULL || info == NULL) {
4628                 PMD_DRV_LOG(ERR, "invalid parameters");
4629                 return I40E_ERR_PARAM;
4630         }
4631
4632         if (info->on) {
4633                 vsi->info.pvid = info->config.pvid;
4634                 /**
4635                  * If insert pvid is enabled, only tagged pkts are
4636                  * allowed to be sent out.
4637                  */
4638                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4639                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4640         } else {
4641                 vsi->info.pvid = 0;
4642                 if (info->config.reject.tagged == 0)
4643                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4644
4645                 if (info->config.reject.untagged == 0)
4646                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4647         }
4648         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4649                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4650         vsi->info.port_vlan_flags |= vlan_flags;
4651         vsi->info.valid_sections =
4652                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4653         memset(&ctxt, 0, sizeof(ctxt));
4654         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4655         ctxt.seid = vsi->seid;
4656
4657         hw = I40E_VSI_TO_HW(vsi);
4658         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4659         if (ret != I40E_SUCCESS)
4660                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4661
4662         return ret;
4663 }
4664
4665 static int
4666 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4667 {
4668         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4669         int i, ret;
4670         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4671
4672         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4673         if (ret != I40E_SUCCESS)
4674                 return ret;
4675
4676         if (!vsi->seid) {
4677                 PMD_DRV_LOG(ERR, "seid not valid");
4678                 return -EINVAL;
4679         }
4680
4681         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4682         tc_bw_data.tc_valid_bits = enabled_tcmap;
4683         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4684                 tc_bw_data.tc_bw_credits[i] =
4685                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4686
4687         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4688         if (ret != I40E_SUCCESS) {
4689                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4690                 return ret;
4691         }
4692
4693         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4694                                         sizeof(vsi->info.qs_handle));
4695         return I40E_SUCCESS;
4696 }
4697
4698 static enum i40e_status_code
4699 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4700                                  struct i40e_aqc_vsi_properties_data *info,
4701                                  uint8_t enabled_tcmap)
4702 {
4703         enum i40e_status_code ret;
4704         int i, total_tc = 0;
4705         uint16_t qpnum_per_tc, bsf, qp_idx;
4706
4707         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4708         if (ret != I40E_SUCCESS)
4709                 return ret;
4710
4711         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4712                 if (enabled_tcmap & (1 << i))
4713                         total_tc++;
4714         if (total_tc == 0)
4715                 total_tc = 1;
4716         vsi->enabled_tc = enabled_tcmap;
4717
4718         /* Number of queues per enabled TC */
4719         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4720         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4721         bsf = rte_bsf32(qpnum_per_tc);
4722
4723         /* Adjust the queue number to actual queues that can be applied */
4724         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4725                 vsi->nb_qps = qpnum_per_tc * total_tc;
4726
4727         /**
4728          * Configure TC and queue mapping parameters, for enabled TC,
4729          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4730          * default queue will serve it.
4731          */
4732         qp_idx = 0;
4733         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4734                 if (vsi->enabled_tc & (1 << i)) {
4735                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4736                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4737                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4738                         qp_idx += qpnum_per_tc;
4739                 } else
4740                         info->tc_mapping[i] = 0;
4741         }
4742
4743         /* Associate queue number with VSI */
4744         if (vsi->type == I40E_VSI_SRIOV) {
4745                 info->mapping_flags |=
4746                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4747                 for (i = 0; i < vsi->nb_qps; i++)
4748                         info->queue_mapping[i] =
4749                                 rte_cpu_to_le_16(vsi->base_queue + i);
4750         } else {
4751                 info->mapping_flags |=
4752                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4753                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4754         }
4755         info->valid_sections |=
4756                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4757
4758         return I40E_SUCCESS;
4759 }
4760
4761 static int
4762 i40e_veb_release(struct i40e_veb *veb)
4763 {
4764         struct i40e_vsi *vsi;
4765         struct i40e_hw *hw;
4766
4767         if (veb == NULL)
4768                 return -EINVAL;
4769
4770         if (!TAILQ_EMPTY(&veb->head)) {
4771                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4772                 return -EACCES;
4773         }
4774         /* associate_vsi field is NULL for floating VEB */
4775         if (veb->associate_vsi != NULL) {
4776                 vsi = veb->associate_vsi;
4777                 hw = I40E_VSI_TO_HW(vsi);
4778
4779                 vsi->uplink_seid = veb->uplink_seid;
4780                 vsi->veb = NULL;
4781         } else {
4782                 veb->associate_pf->main_vsi->floating_veb = NULL;
4783                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4784         }
4785
4786         i40e_aq_delete_element(hw, veb->seid, NULL);
4787         rte_free(veb);
4788         return I40E_SUCCESS;
4789 }
4790
4791 /* Setup a veb */
4792 static struct i40e_veb *
4793 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4794 {
4795         struct i40e_veb *veb;
4796         int ret;
4797         struct i40e_hw *hw;
4798
4799         if (pf == NULL) {
4800                 PMD_DRV_LOG(ERR,
4801                             "veb setup failed, associated PF shouldn't null");
4802                 return NULL;
4803         }
4804         hw = I40E_PF_TO_HW(pf);
4805
4806         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4807         if (!veb) {
4808                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4809                 goto fail;
4810         }
4811
4812         veb->associate_vsi = vsi;
4813         veb->associate_pf = pf;
4814         TAILQ_INIT(&veb->head);
4815         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4816
4817         /* create floating veb if vsi is NULL */
4818         if (vsi != NULL) {
4819                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4820                                       I40E_DEFAULT_TCMAP, false,
4821                                       &veb->seid, false, NULL);
4822         } else {
4823                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4824                                       true, &veb->seid, false, NULL);
4825         }
4826
4827         if (ret != I40E_SUCCESS) {
4828                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4829                             hw->aq.asq_last_status);
4830                 goto fail;
4831         }
4832         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4833
4834         /* get statistics index */
4835         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4836                                 &veb->stats_idx, NULL, NULL, NULL);
4837         if (ret != I40E_SUCCESS) {
4838                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4839                             hw->aq.asq_last_status);
4840                 goto fail;
4841         }
4842         /* Get VEB bandwidth, to be implemented */
4843         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4844         if (vsi)
4845                 vsi->uplink_seid = veb->seid;
4846
4847         return veb;
4848 fail:
4849         rte_free(veb);
4850         return NULL;
4851 }
4852
4853 int
4854 i40e_vsi_release(struct i40e_vsi *vsi)
4855 {
4856         struct i40e_pf *pf;
4857         struct i40e_hw *hw;
4858         struct i40e_vsi_list *vsi_list;
4859         void *temp;
4860         int ret;
4861         struct i40e_mac_filter *f;
4862         uint16_t user_param;
4863
4864         if (!vsi)
4865                 return I40E_SUCCESS;
4866
4867         if (!vsi->adapter)
4868                 return -EFAULT;
4869
4870         user_param = vsi->user_param;
4871
4872         pf = I40E_VSI_TO_PF(vsi);
4873         hw = I40E_VSI_TO_HW(vsi);
4874
4875         /* VSI has child to attach, release child first */
4876         if (vsi->veb) {
4877                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4878                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4879                                 return -1;
4880                 }
4881                 i40e_veb_release(vsi->veb);
4882         }
4883
4884         if (vsi->floating_veb) {
4885                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4886                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4887                                 return -1;
4888                 }
4889         }
4890
4891         /* Remove all macvlan filters of the VSI */
4892         i40e_vsi_remove_all_macvlan_filter(vsi);
4893         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4894                 rte_free(f);
4895
4896         if (vsi->type != I40E_VSI_MAIN &&
4897             ((vsi->type != I40E_VSI_SRIOV) ||
4898             !pf->floating_veb_list[user_param])) {
4899                 /* Remove vsi from parent's sibling list */
4900                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4901                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4902                         return I40E_ERR_PARAM;
4903                 }
4904                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4905                                 &vsi->sib_vsi_list, list);
4906
4907                 /* Remove all switch element of the VSI */
4908                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4909                 if (ret != I40E_SUCCESS)
4910                         PMD_DRV_LOG(ERR, "Failed to delete element");
4911         }
4912
4913         if ((vsi->type == I40E_VSI_SRIOV) &&
4914             pf->floating_veb_list[user_param]) {
4915                 /* Remove vsi from parent's sibling list */
4916                 if (vsi->parent_vsi == NULL ||
4917                     vsi->parent_vsi->floating_veb == NULL) {
4918                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4919                         return I40E_ERR_PARAM;
4920                 }
4921                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4922                              &vsi->sib_vsi_list, list);
4923
4924                 /* Remove all switch element of the VSI */
4925                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4926                 if (ret != I40E_SUCCESS)
4927                         PMD_DRV_LOG(ERR, "Failed to delete element");
4928         }
4929
4930         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4931
4932         if (vsi->type != I40E_VSI_SRIOV)
4933                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4934         rte_free(vsi);
4935
4936         return I40E_SUCCESS;
4937 }
4938
4939 static int
4940 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4941 {
4942         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4943         struct i40e_aqc_remove_macvlan_element_data def_filter;
4944         struct i40e_mac_filter_info filter;
4945         int ret;
4946
4947         if (vsi->type != I40E_VSI_MAIN)
4948                 return I40E_ERR_CONFIG;
4949         memset(&def_filter, 0, sizeof(def_filter));
4950         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4951                                         ETH_ADDR_LEN);
4952         def_filter.vlan_tag = 0;
4953         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4954                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4955         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4956         if (ret != I40E_SUCCESS) {
4957                 struct i40e_mac_filter *f;
4958                 struct ether_addr *mac;
4959
4960                 PMD_DRV_LOG(DEBUG,
4961                             "Cannot remove the default macvlan filter");
4962                 /* It needs to add the permanent mac into mac list */
4963                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4964                 if (f == NULL) {
4965                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4966                         return I40E_ERR_NO_MEMORY;
4967                 }
4968                 mac = &f->mac_info.mac_addr;
4969                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4970                                 ETH_ADDR_LEN);
4971                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4972                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4973                 vsi->mac_num++;
4974
4975                 return ret;
4976         }
4977         rte_memcpy(&filter.mac_addr,
4978                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4979         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4980         return i40e_vsi_add_mac(vsi, &filter);
4981 }
4982
4983 /*
4984  * i40e_vsi_get_bw_config - Query VSI BW Information
4985  * @vsi: the VSI to be queried
4986  *
4987  * Returns 0 on success, negative value on failure
4988  */
4989 static enum i40e_status_code
4990 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4991 {
4992         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4993         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4994         struct i40e_hw *hw = &vsi->adapter->hw;
4995         i40e_status ret;
4996         int i;
4997         uint32_t bw_max;
4998
4999         memset(&bw_config, 0, sizeof(bw_config));
5000         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5001         if (ret != I40E_SUCCESS) {
5002                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5003                             hw->aq.asq_last_status);
5004                 return ret;
5005         }
5006
5007         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5008         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5009                                         &ets_sla_config, NULL);
5010         if (ret != I40E_SUCCESS) {
5011                 PMD_DRV_LOG(ERR,
5012                         "VSI failed to get TC bandwdith configuration %u",
5013                         hw->aq.asq_last_status);
5014                 return ret;
5015         }
5016
5017         /* store and print out BW info */
5018         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5019         vsi->bw_info.bw_max = bw_config.max_bw;
5020         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5021         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5022         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5023                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5024                      I40E_16_BIT_WIDTH);
5025         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5026                 vsi->bw_info.bw_ets_share_credits[i] =
5027                                 ets_sla_config.share_credits[i];
5028                 vsi->bw_info.bw_ets_credits[i] =
5029                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5030                 /* 4 bits per TC, 4th bit is reserved */
5031                 vsi->bw_info.bw_ets_max[i] =
5032                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5033                                   RTE_LEN2MASK(3, uint8_t));
5034                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5035                             vsi->bw_info.bw_ets_share_credits[i]);
5036                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5037                             vsi->bw_info.bw_ets_credits[i]);
5038                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5039                             vsi->bw_info.bw_ets_max[i]);
5040         }
5041
5042         return I40E_SUCCESS;
5043 }
5044
5045 /* i40e_enable_pf_lb
5046  * @pf: pointer to the pf structure
5047  *
5048  * allow loopback on pf
5049  */
5050 static inline void
5051 i40e_enable_pf_lb(struct i40e_pf *pf)
5052 {
5053         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5054         struct i40e_vsi_context ctxt;
5055         int ret;
5056
5057         /* Use the FW API if FW >= v5.0 */
5058         if (hw->aq.fw_maj_ver < 5) {
5059                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5060                 return;
5061         }
5062
5063         memset(&ctxt, 0, sizeof(ctxt));
5064         ctxt.seid = pf->main_vsi_seid;
5065         ctxt.pf_num = hw->pf_id;
5066         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5067         if (ret) {
5068                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5069                             ret, hw->aq.asq_last_status);
5070                 return;
5071         }
5072         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5073         ctxt.info.valid_sections =
5074                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5075         ctxt.info.switch_id |=
5076                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5077
5078         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5079         if (ret)
5080                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5081                             hw->aq.asq_last_status);
5082 }
5083
5084 /* Setup a VSI */
5085 struct i40e_vsi *
5086 i40e_vsi_setup(struct i40e_pf *pf,
5087                enum i40e_vsi_type type,
5088                struct i40e_vsi *uplink_vsi,
5089                uint16_t user_param)
5090 {
5091         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5092         struct i40e_vsi *vsi;
5093         struct i40e_mac_filter_info filter;
5094         int ret;
5095         struct i40e_vsi_context ctxt;
5096         struct ether_addr broadcast =
5097                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5098
5099         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5100             uplink_vsi == NULL) {
5101                 PMD_DRV_LOG(ERR,
5102                         "VSI setup failed, VSI link shouldn't be NULL");
5103                 return NULL;
5104         }
5105
5106         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5107                 PMD_DRV_LOG(ERR,
5108                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5109                 return NULL;
5110         }
5111
5112         /* two situations
5113          * 1.type is not MAIN and uplink vsi is not NULL
5114          * If uplink vsi didn't setup VEB, create one first under veb field
5115          * 2.type is SRIOV and the uplink is NULL
5116          * If floating VEB is NULL, create one veb under floating veb field
5117          */
5118
5119         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5120             uplink_vsi->veb == NULL) {
5121                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5122
5123                 if (uplink_vsi->veb == NULL) {
5124                         PMD_DRV_LOG(ERR, "VEB setup failed");
5125                         return NULL;
5126                 }
5127                 /* set ALLOWLOOPBACk on pf, when veb is created */
5128                 i40e_enable_pf_lb(pf);
5129         }
5130
5131         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5132             pf->main_vsi->floating_veb == NULL) {
5133                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5134
5135                 if (pf->main_vsi->floating_veb == NULL) {
5136                         PMD_DRV_LOG(ERR, "VEB setup failed");
5137                         return NULL;
5138                 }
5139         }
5140
5141         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5142         if (!vsi) {
5143                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5144                 return NULL;
5145         }
5146         TAILQ_INIT(&vsi->mac_list);
5147         vsi->type = type;
5148         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5149         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5150         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5151         vsi->user_param = user_param;
5152         vsi->vlan_anti_spoof_on = 0;
5153         vsi->vlan_filter_on = 0;
5154         /* Allocate queues */
5155         switch (vsi->type) {
5156         case I40E_VSI_MAIN  :
5157                 vsi->nb_qps = pf->lan_nb_qps;
5158                 break;
5159         case I40E_VSI_SRIOV :
5160                 vsi->nb_qps = pf->vf_nb_qps;
5161                 break;
5162         case I40E_VSI_VMDQ2:
5163                 vsi->nb_qps = pf->vmdq_nb_qps;
5164                 break;
5165         case I40E_VSI_FDIR:
5166                 vsi->nb_qps = pf->fdir_nb_qps;
5167                 break;
5168         default:
5169                 goto fail_mem;
5170         }
5171         /*
5172          * The filter status descriptor is reported in rx queue 0,
5173          * while the tx queue for fdir filter programming has no
5174          * such constraints, can be non-zero queues.
5175          * To simplify it, choose FDIR vsi use queue 0 pair.
5176          * To make sure it will use queue 0 pair, queue allocation
5177          * need be done before this function is called
5178          */
5179         if (type != I40E_VSI_FDIR) {
5180                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5181                         if (ret < 0) {
5182                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5183                                                 vsi->seid, ret);
5184                                 goto fail_mem;
5185                         }
5186                         vsi->base_queue = ret;
5187         } else
5188                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5189
5190         /* VF has MSIX interrupt in VF range, don't allocate here */
5191         if (type == I40E_VSI_MAIN) {
5192                 if (pf->support_multi_driver) {
5193                         /* If support multi-driver, need to use INT0 instead of
5194                          * allocating from msix pool. The Msix pool is init from
5195                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5196                          * to 1 without calling i40e_res_pool_alloc.
5197                          */
5198                         vsi->msix_intr = 0;
5199                         vsi->nb_msix = 1;
5200                 } else {
5201                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5202                                                   RTE_MIN(vsi->nb_qps,
5203                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5204                         if (ret < 0) {
5205                                 PMD_DRV_LOG(ERR,
5206                                             "VSI MAIN %d get heap failed %d",
5207                                             vsi->seid, ret);
5208                                 goto fail_queue_alloc;
5209                         }
5210                         vsi->msix_intr = ret;
5211                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5212                                                RTE_MAX_RXTX_INTR_VEC_ID);
5213                 }
5214         } else if (type != I40E_VSI_SRIOV) {
5215                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5216                 if (ret < 0) {
5217                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5218                         goto fail_queue_alloc;
5219                 }
5220                 vsi->msix_intr = ret;
5221                 vsi->nb_msix = 1;
5222         } else {
5223                 vsi->msix_intr = 0;
5224                 vsi->nb_msix = 0;
5225         }
5226
5227         /* Add VSI */
5228         if (type == I40E_VSI_MAIN) {
5229                 /* For main VSI, no need to add since it's default one */
5230                 vsi->uplink_seid = pf->mac_seid;
5231                 vsi->seid = pf->main_vsi_seid;
5232                 /* Bind queues with specific MSIX interrupt */
5233                 /**
5234                  * Needs 2 interrupt at least, one for misc cause which will
5235                  * enabled from OS side, Another for queues binding the
5236                  * interrupt from device side only.
5237                  */
5238
5239                 /* Get default VSI parameters from hardware */
5240                 memset(&ctxt, 0, sizeof(ctxt));
5241                 ctxt.seid = vsi->seid;
5242                 ctxt.pf_num = hw->pf_id;
5243                 ctxt.uplink_seid = vsi->uplink_seid;
5244                 ctxt.vf_num = 0;
5245                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5246                 if (ret != I40E_SUCCESS) {
5247                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5248                         goto fail_msix_alloc;
5249                 }
5250                 rte_memcpy(&vsi->info, &ctxt.info,
5251                         sizeof(struct i40e_aqc_vsi_properties_data));
5252                 vsi->vsi_id = ctxt.vsi_number;
5253                 vsi->info.valid_sections = 0;
5254
5255                 /* Configure tc, enabled TC0 only */
5256                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5257                         I40E_SUCCESS) {
5258                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5259                         goto fail_msix_alloc;
5260                 }
5261
5262                 /* TC, queue mapping */
5263                 memset(&ctxt, 0, sizeof(ctxt));
5264                 vsi->info.valid_sections |=
5265                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5266                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5267                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5268                 rte_memcpy(&ctxt.info, &vsi->info,
5269                         sizeof(struct i40e_aqc_vsi_properties_data));
5270                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5271                                                 I40E_DEFAULT_TCMAP);
5272                 if (ret != I40E_SUCCESS) {
5273                         PMD_DRV_LOG(ERR,
5274                                 "Failed to configure TC queue mapping");
5275                         goto fail_msix_alloc;
5276                 }
5277                 ctxt.seid = vsi->seid;
5278                 ctxt.pf_num = hw->pf_id;
5279                 ctxt.uplink_seid = vsi->uplink_seid;
5280                 ctxt.vf_num = 0;
5281
5282                 /* Update VSI parameters */
5283                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5284                 if (ret != I40E_SUCCESS) {
5285                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5286                         goto fail_msix_alloc;
5287                 }
5288
5289                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5290                                                 sizeof(vsi->info.tc_mapping));
5291                 rte_memcpy(&vsi->info.queue_mapping,
5292                                 &ctxt.info.queue_mapping,
5293                         sizeof(vsi->info.queue_mapping));
5294                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5295                 vsi->info.valid_sections = 0;
5296
5297                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5298                                 ETH_ADDR_LEN);
5299
5300                 /**
5301                  * Updating default filter settings are necessary to prevent
5302                  * reception of tagged packets.
5303                  * Some old firmware configurations load a default macvlan
5304                  * filter which accepts both tagged and untagged packets.
5305                  * The updating is to use a normal filter instead if needed.
5306                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5307                  * The firmware with correct configurations load the default
5308                  * macvlan filter which is expected and cannot be removed.
5309                  */
5310                 i40e_update_default_filter_setting(vsi);
5311                 i40e_config_qinq(hw, vsi);
5312         } else if (type == I40E_VSI_SRIOV) {
5313                 memset(&ctxt, 0, sizeof(ctxt));
5314                 /**
5315                  * For other VSI, the uplink_seid equals to uplink VSI's
5316                  * uplink_seid since they share same VEB
5317                  */
5318                 if (uplink_vsi == NULL)
5319                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5320                 else
5321                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5322                 ctxt.pf_num = hw->pf_id;
5323                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5324                 ctxt.uplink_seid = vsi->uplink_seid;
5325                 ctxt.connection_type = 0x1;
5326                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5327
5328                 /* Use the VEB configuration if FW >= v5.0 */
5329                 if (hw->aq.fw_maj_ver >= 5) {
5330                         /* Configure switch ID */
5331                         ctxt.info.valid_sections |=
5332                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5333                         ctxt.info.switch_id =
5334                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5335                 }
5336
5337                 /* Configure port/vlan */
5338                 ctxt.info.valid_sections |=
5339                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5340                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5341                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5342                                                 hw->func_caps.enabled_tcmap);
5343                 if (ret != I40E_SUCCESS) {
5344                         PMD_DRV_LOG(ERR,
5345                                 "Failed to configure TC queue mapping");
5346                         goto fail_msix_alloc;
5347                 }
5348
5349                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5350                 ctxt.info.valid_sections |=
5351                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5352                 /**
5353                  * Since VSI is not created yet, only configure parameter,
5354                  * will add vsi below.
5355                  */
5356
5357                 i40e_config_qinq(hw, vsi);
5358         } else if (type == I40E_VSI_VMDQ2) {
5359                 memset(&ctxt, 0, sizeof(ctxt));
5360                 /*
5361                  * For other VSI, the uplink_seid equals to uplink VSI's
5362                  * uplink_seid since they share same VEB
5363                  */
5364                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5365                 ctxt.pf_num = hw->pf_id;
5366                 ctxt.vf_num = 0;
5367                 ctxt.uplink_seid = vsi->uplink_seid;
5368                 ctxt.connection_type = 0x1;
5369                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5370
5371                 ctxt.info.valid_sections |=
5372                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5373                 /* user_param carries flag to enable loop back */
5374                 if (user_param) {
5375                         ctxt.info.switch_id =
5376                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5377                         ctxt.info.switch_id |=
5378                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5379                 }
5380
5381                 /* Configure port/vlan */
5382                 ctxt.info.valid_sections |=
5383                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5384                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5385                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5386                                                 I40E_DEFAULT_TCMAP);
5387                 if (ret != I40E_SUCCESS) {
5388                         PMD_DRV_LOG(ERR,
5389                                 "Failed to configure TC queue mapping");
5390                         goto fail_msix_alloc;
5391                 }
5392                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5393                 ctxt.info.valid_sections |=
5394                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5395         } else if (type == I40E_VSI_FDIR) {
5396                 memset(&ctxt, 0, sizeof(ctxt));
5397                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5398                 ctxt.pf_num = hw->pf_id;
5399                 ctxt.vf_num = 0;
5400                 ctxt.uplink_seid = vsi->uplink_seid;
5401                 ctxt.connection_type = 0x1;     /* regular data port */
5402                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5403                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5404                                                 I40E_DEFAULT_TCMAP);
5405                 if (ret != I40E_SUCCESS) {
5406                         PMD_DRV_LOG(ERR,
5407                                 "Failed to configure TC queue mapping.");
5408                         goto fail_msix_alloc;
5409                 }
5410                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5411                 ctxt.info.valid_sections |=
5412                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5413         } else {
5414                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5415                 goto fail_msix_alloc;
5416         }
5417
5418         if (vsi->type != I40E_VSI_MAIN) {
5419                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5420                 if (ret != I40E_SUCCESS) {
5421                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5422                                     hw->aq.asq_last_status);
5423                         goto fail_msix_alloc;
5424                 }
5425                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5426                 vsi->info.valid_sections = 0;
5427                 vsi->seid = ctxt.seid;
5428                 vsi->vsi_id = ctxt.vsi_number;
5429                 vsi->sib_vsi_list.vsi = vsi;
5430                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5431                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5432                                           &vsi->sib_vsi_list, list);
5433                 } else {
5434                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5435                                           &vsi->sib_vsi_list, list);
5436                 }
5437         }
5438
5439         /* MAC/VLAN configuration */
5440         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5441         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5442
5443         ret = i40e_vsi_add_mac(vsi, &filter);
5444         if (ret != I40E_SUCCESS) {
5445                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5446                 goto fail_msix_alloc;
5447         }
5448
5449         /* Get VSI BW information */
5450         i40e_vsi_get_bw_config(vsi);
5451         return vsi;
5452 fail_msix_alloc:
5453         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5454 fail_queue_alloc:
5455         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5456 fail_mem:
5457         rte_free(vsi);
5458         return NULL;
5459 }
5460
5461 /* Configure vlan filter on or off */
5462 int
5463 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5464 {
5465         int i, num;
5466         struct i40e_mac_filter *f;
5467         void *temp;
5468         struct i40e_mac_filter_info *mac_filter;
5469         enum rte_mac_filter_type desired_filter;
5470         int ret = I40E_SUCCESS;
5471
5472         if (on) {
5473                 /* Filter to match MAC and VLAN */
5474                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5475         } else {
5476                 /* Filter to match only MAC */
5477                 desired_filter = RTE_MAC_PERFECT_MATCH;
5478         }
5479
5480         num = vsi->mac_num;
5481
5482         mac_filter = rte_zmalloc("mac_filter_info_data",
5483                                  num * sizeof(*mac_filter), 0);
5484         if (mac_filter == NULL) {
5485                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5486                 return I40E_ERR_NO_MEMORY;
5487         }
5488
5489         i = 0;
5490
5491         /* Remove all existing mac */
5492         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5493                 mac_filter[i] = f->mac_info;
5494                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5495                 if (ret) {
5496                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5497                                     on ? "enable" : "disable");
5498                         goto DONE;
5499                 }
5500                 i++;
5501         }
5502
5503         /* Override with new filter */
5504         for (i = 0; i < num; i++) {
5505                 mac_filter[i].filter_type = desired_filter;
5506                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5507                 if (ret) {
5508                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5509                                     on ? "enable" : "disable");
5510                         goto DONE;
5511                 }
5512         }
5513
5514 DONE:
5515         rte_free(mac_filter);
5516         return ret;
5517 }
5518
5519 /* Configure vlan stripping on or off */
5520 int
5521 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5522 {
5523         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5524         struct i40e_vsi_context ctxt;
5525         uint8_t vlan_flags;
5526         int ret = I40E_SUCCESS;
5527
5528         /* Check if it has been already on or off */
5529         if (vsi->info.valid_sections &
5530                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5531                 if (on) {
5532                         if ((vsi->info.port_vlan_flags &
5533                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5534                                 return 0; /* already on */
5535                 } else {
5536                         if ((vsi->info.port_vlan_flags &
5537                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5538                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5539                                 return 0; /* already off */
5540                 }
5541         }
5542
5543         if (on)
5544                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5545         else
5546                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5547         vsi->info.valid_sections =
5548                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5549         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5550         vsi->info.port_vlan_flags |= vlan_flags;
5551         ctxt.seid = vsi->seid;
5552         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5553         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5554         if (ret)
5555                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5556                             on ? "enable" : "disable");
5557
5558         return ret;
5559 }
5560
5561 static int
5562 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5563 {
5564         struct rte_eth_dev_data *data = dev->data;
5565         int ret;
5566         int mask = 0;
5567
5568         /* Apply vlan offload setting */
5569         mask = ETH_VLAN_STRIP_MASK |
5570                ETH_VLAN_FILTER_MASK |
5571                ETH_VLAN_EXTEND_MASK;
5572         ret = i40e_vlan_offload_set(dev, mask);
5573         if (ret) {
5574                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5575                 return ret;
5576         }
5577
5578         /* Apply pvid setting */
5579         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5580                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5581         if (ret)
5582                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5583
5584         return ret;
5585 }
5586
5587 static int
5588 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5589 {
5590         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5591
5592         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5593 }
5594
5595 static int
5596 i40e_update_flow_control(struct i40e_hw *hw)
5597 {
5598 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5599         struct i40e_link_status link_status;
5600         uint32_t rxfc = 0, txfc = 0, reg;
5601         uint8_t an_info;
5602         int ret;
5603
5604         memset(&link_status, 0, sizeof(link_status));
5605         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5606         if (ret != I40E_SUCCESS) {
5607                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5608                 goto write_reg; /* Disable flow control */
5609         }
5610
5611         an_info = hw->phy.link_info.an_info;
5612         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5613                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5614                 ret = I40E_ERR_NOT_READY;
5615                 goto write_reg; /* Disable flow control */
5616         }
5617         /**
5618          * If link auto negotiation is enabled, flow control needs to
5619          * be configured according to it
5620          */
5621         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5622         case I40E_LINK_PAUSE_RXTX:
5623                 rxfc = 1;
5624                 txfc = 1;
5625                 hw->fc.current_mode = I40E_FC_FULL;
5626                 break;
5627         case I40E_AQ_LINK_PAUSE_RX:
5628                 rxfc = 1;
5629                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5630                 break;
5631         case I40E_AQ_LINK_PAUSE_TX:
5632                 txfc = 1;
5633                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5634                 break;
5635         default:
5636                 hw->fc.current_mode = I40E_FC_NONE;
5637                 break;
5638         }
5639
5640 write_reg:
5641         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5642                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5643         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5644         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5645         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5646         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5647
5648         return ret;
5649 }
5650
5651 /* PF setup */
5652 static int
5653 i40e_pf_setup(struct i40e_pf *pf)
5654 {
5655         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5656         struct i40e_filter_control_settings settings;
5657         struct i40e_vsi *vsi;
5658         int ret;
5659
5660         /* Clear all stats counters */
5661         pf->offset_loaded = FALSE;
5662         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5663         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5664         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5665         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5666
5667         ret = i40e_pf_get_switch_config(pf);
5668         if (ret != I40E_SUCCESS) {
5669                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5670                 return ret;
5671         }
5672         if (pf->flags & I40E_FLAG_FDIR) {
5673                 /* make queue allocated first, let FDIR use queue pair 0*/
5674                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5675                 if (ret != I40E_FDIR_QUEUE_ID) {
5676                         PMD_DRV_LOG(ERR,
5677                                 "queue allocation fails for FDIR: ret =%d",
5678                                 ret);
5679                         pf->flags &= ~I40E_FLAG_FDIR;
5680                 }
5681         }
5682         /*  main VSI setup */
5683         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5684         if (!vsi) {
5685                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5686                 return I40E_ERR_NOT_READY;
5687         }
5688         pf->main_vsi = vsi;
5689
5690         /* Configure filter control */
5691         memset(&settings, 0, sizeof(settings));
5692         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5693                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5694         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5695                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5696         else {
5697                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5698                         hw->func_caps.rss_table_size);
5699                 return I40E_ERR_PARAM;
5700         }
5701         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5702                 hw->func_caps.rss_table_size);
5703         pf->hash_lut_size = hw->func_caps.rss_table_size;
5704
5705         /* Enable ethtype and macvlan filters */
5706         settings.enable_ethtype = TRUE;
5707         settings.enable_macvlan = TRUE;
5708         ret = i40e_set_filter_control(hw, &settings);
5709         if (ret)
5710                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5711                                                                 ret);
5712
5713         /* Update flow control according to the auto negotiation */
5714         i40e_update_flow_control(hw);
5715
5716         return I40E_SUCCESS;
5717 }
5718
5719 int
5720 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5721 {
5722         uint32_t reg;
5723         uint16_t j;
5724
5725         /**
5726          * Set or clear TX Queue Disable flags,
5727          * which is required by hardware.
5728          */
5729         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5730         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5731
5732         /* Wait until the request is finished */
5733         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5734                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5735                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5736                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5737                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5738                                                         & 0x1))) {
5739                         break;
5740                 }
5741         }
5742         if (on) {
5743                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5744                         return I40E_SUCCESS; /* already on, skip next steps */
5745
5746                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5747                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5748         } else {
5749                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5750                         return I40E_SUCCESS; /* already off, skip next steps */
5751                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5752         }
5753         /* Write the register */
5754         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5755         /* Check the result */
5756         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5757                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5758                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5759                 if (on) {
5760                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5761                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5762                                 break;
5763                 } else {
5764                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5765                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5766                                 break;
5767                 }
5768         }
5769         /* Check if it is timeout */
5770         if (j >= I40E_CHK_Q_ENA_COUNT) {
5771                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5772                             (on ? "enable" : "disable"), q_idx);
5773                 return I40E_ERR_TIMEOUT;
5774         }
5775
5776         return I40E_SUCCESS;
5777 }
5778
5779 /* Swith on or off the tx queues */
5780 static int
5781 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5782 {
5783         struct rte_eth_dev_data *dev_data = pf->dev_data;
5784         struct i40e_tx_queue *txq;
5785         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5786         uint16_t i;
5787         int ret;
5788
5789         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5790                 txq = dev_data->tx_queues[i];
5791                 /* Don't operate the queue if not configured or
5792                  * if starting only per queue */
5793                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5794                         continue;
5795                 if (on)
5796                         ret = i40e_dev_tx_queue_start(dev, i);
5797                 else
5798                         ret = i40e_dev_tx_queue_stop(dev, i);
5799                 if ( ret != I40E_SUCCESS)
5800                         return ret;
5801         }
5802
5803         return I40E_SUCCESS;
5804 }
5805
5806 int
5807 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5808 {
5809         uint32_t reg;
5810         uint16_t j;
5811
5812         /* Wait until the request is finished */
5813         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5814                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5815                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5816                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5817                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5818                         break;
5819         }
5820
5821         if (on) {
5822                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5823                         return I40E_SUCCESS; /* Already on, skip next steps */
5824                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5825         } else {
5826                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5827                         return I40E_SUCCESS; /* Already off, skip next steps */
5828                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5829         }
5830
5831         /* Write the register */
5832         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5833         /* Check the result */
5834         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5835                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5836                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5837                 if (on) {
5838                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5839                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5840                                 break;
5841                 } else {
5842                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5843                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5844                                 break;
5845                 }
5846         }
5847
5848         /* Check if it is timeout */
5849         if (j >= I40E_CHK_Q_ENA_COUNT) {
5850                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5851                             (on ? "enable" : "disable"), q_idx);
5852                 return I40E_ERR_TIMEOUT;
5853         }
5854
5855         return I40E_SUCCESS;
5856 }
5857 /* Switch on or off the rx queues */
5858 static int
5859 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5860 {
5861         struct rte_eth_dev_data *dev_data = pf->dev_data;
5862         struct i40e_rx_queue *rxq;
5863         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5864         uint16_t i;
5865         int ret;
5866
5867         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5868                 rxq = dev_data->rx_queues[i];
5869                 /* Don't operate the queue if not configured or
5870                  * if starting only per queue */
5871                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5872                         continue;
5873                 if (on)
5874                         ret = i40e_dev_rx_queue_start(dev, i);
5875                 else
5876                         ret = i40e_dev_rx_queue_stop(dev, i);
5877                 if (ret != I40E_SUCCESS)
5878                         return ret;
5879         }
5880
5881         return I40E_SUCCESS;
5882 }
5883
5884 /* Switch on or off all the rx/tx queues */
5885 int
5886 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5887 {
5888         int ret;
5889
5890         if (on) {
5891                 /* enable rx queues before enabling tx queues */
5892                 ret = i40e_dev_switch_rx_queues(pf, on);
5893                 if (ret) {
5894                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5895                         return ret;
5896                 }
5897                 ret = i40e_dev_switch_tx_queues(pf, on);
5898         } else {
5899                 /* Stop tx queues before stopping rx queues */
5900                 ret = i40e_dev_switch_tx_queues(pf, on);
5901                 if (ret) {
5902                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5903                         return ret;
5904                 }
5905                 ret = i40e_dev_switch_rx_queues(pf, on);
5906         }
5907
5908         return ret;
5909 }
5910
5911 /* Initialize VSI for TX */
5912 static int
5913 i40e_dev_tx_init(struct i40e_pf *pf)
5914 {
5915         struct rte_eth_dev_data *data = pf->dev_data;
5916         uint16_t i;
5917         uint32_t ret = I40E_SUCCESS;
5918         struct i40e_tx_queue *txq;
5919
5920         for (i = 0; i < data->nb_tx_queues; i++) {
5921                 txq = data->tx_queues[i];
5922                 if (!txq || !txq->q_set)
5923                         continue;
5924                 ret = i40e_tx_queue_init(txq);
5925                 if (ret != I40E_SUCCESS)
5926                         break;
5927         }
5928         if (ret == I40E_SUCCESS)
5929                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5930                                      ->eth_dev);
5931
5932         return ret;
5933 }
5934
5935 /* Initialize VSI for RX */
5936 static int
5937 i40e_dev_rx_init(struct i40e_pf *pf)
5938 {
5939         struct rte_eth_dev_data *data = pf->dev_data;
5940         int ret = I40E_SUCCESS;
5941         uint16_t i;
5942         struct i40e_rx_queue *rxq;
5943
5944         i40e_pf_config_mq_rx(pf);
5945         for (i = 0; i < data->nb_rx_queues; i++) {
5946                 rxq = data->rx_queues[i];
5947                 if (!rxq || !rxq->q_set)
5948                         continue;
5949
5950                 ret = i40e_rx_queue_init(rxq);
5951                 if (ret != I40E_SUCCESS) {
5952                         PMD_DRV_LOG(ERR,
5953                                 "Failed to do RX queue initialization");
5954                         break;
5955                 }
5956         }
5957         if (ret == I40E_SUCCESS)
5958                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5959                                      ->eth_dev);
5960
5961         return ret;
5962 }
5963
5964 static int
5965 i40e_dev_rxtx_init(struct i40e_pf *pf)
5966 {
5967         int err;
5968
5969         err = i40e_dev_tx_init(pf);
5970         if (err) {
5971                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5972                 return err;
5973         }
5974         err = i40e_dev_rx_init(pf);
5975         if (err) {
5976                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5977                 return err;
5978         }
5979
5980         return err;
5981 }
5982
5983 static int
5984 i40e_vmdq_setup(struct rte_eth_dev *dev)
5985 {
5986         struct rte_eth_conf *conf = &dev->data->dev_conf;
5987         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5988         int i, err, conf_vsis, j, loop;
5989         struct i40e_vsi *vsi;
5990         struct i40e_vmdq_info *vmdq_info;
5991         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5992         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5993
5994         /*
5995          * Disable interrupt to avoid message from VF. Furthermore, it will
5996          * avoid race condition in VSI creation/destroy.
5997          */
5998         i40e_pf_disable_irq0(hw);
5999
6000         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6001                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6002                 return -ENOTSUP;
6003         }
6004
6005         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6006         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6007                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6008                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6009                         pf->max_nb_vmdq_vsi);
6010                 return -ENOTSUP;
6011         }
6012
6013         if (pf->vmdq != NULL) {
6014                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6015                 return 0;
6016         }
6017
6018         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6019                                 sizeof(*vmdq_info) * conf_vsis, 0);
6020
6021         if (pf->vmdq == NULL) {
6022                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6023                 return -ENOMEM;
6024         }
6025
6026         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6027
6028         /* Create VMDQ VSI */
6029         for (i = 0; i < conf_vsis; i++) {
6030                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6031                                 vmdq_conf->enable_loop_back);
6032                 if (vsi == NULL) {
6033                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6034                         err = -1;
6035                         goto err_vsi_setup;
6036                 }
6037                 vmdq_info = &pf->vmdq[i];
6038                 vmdq_info->pf = pf;
6039                 vmdq_info->vsi = vsi;
6040         }
6041         pf->nb_cfg_vmdq_vsi = conf_vsis;
6042
6043         /* Configure Vlan */
6044         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6045         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6046                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6047                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6048                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6049                                         vmdq_conf->pool_map[i].vlan_id, j);
6050
6051                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6052                                                 vmdq_conf->pool_map[i].vlan_id);
6053                                 if (err) {
6054                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6055                                         err = -1;
6056                                         goto err_vsi_setup;
6057                                 }
6058                         }
6059                 }
6060         }
6061
6062         i40e_pf_enable_irq0(hw);
6063
6064         return 0;
6065
6066 err_vsi_setup:
6067         for (i = 0; i < conf_vsis; i++)
6068                 if (pf->vmdq[i].vsi == NULL)
6069                         break;
6070                 else
6071                         i40e_vsi_release(pf->vmdq[i].vsi);
6072
6073         rte_free(pf->vmdq);
6074         pf->vmdq = NULL;
6075         i40e_pf_enable_irq0(hw);
6076         return err;
6077 }
6078
6079 static void
6080 i40e_stat_update_32(struct i40e_hw *hw,
6081                    uint32_t reg,
6082                    bool offset_loaded,
6083                    uint64_t *offset,
6084                    uint64_t *stat)
6085 {
6086         uint64_t new_data;
6087
6088         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6089         if (!offset_loaded)
6090                 *offset = new_data;
6091
6092         if (new_data >= *offset)
6093                 *stat = (uint64_t)(new_data - *offset);
6094         else
6095                 *stat = (uint64_t)((new_data +
6096                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6097 }
6098
6099 static void
6100 i40e_stat_update_48(struct i40e_hw *hw,
6101                    uint32_t hireg,
6102                    uint32_t loreg,
6103                    bool offset_loaded,
6104                    uint64_t *offset,
6105                    uint64_t *stat)
6106 {
6107         uint64_t new_data;
6108
6109         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6110         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6111                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6112
6113         if (!offset_loaded)
6114                 *offset = new_data;
6115
6116         if (new_data >= *offset)
6117                 *stat = new_data - *offset;
6118         else
6119                 *stat = (uint64_t)((new_data +
6120                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6121
6122         *stat &= I40E_48_BIT_MASK;
6123 }
6124
6125 /* Disable IRQ0 */
6126 void
6127 i40e_pf_disable_irq0(struct i40e_hw *hw)
6128 {
6129         /* Disable all interrupt types */
6130         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6131                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6132         I40E_WRITE_FLUSH(hw);
6133 }
6134
6135 /* Enable IRQ0 */
6136 void
6137 i40e_pf_enable_irq0(struct i40e_hw *hw)
6138 {
6139         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6140                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6141                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6142                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6143         I40E_WRITE_FLUSH(hw);
6144 }
6145
6146 static void
6147 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6148 {
6149         /* read pending request and disable first */
6150         i40e_pf_disable_irq0(hw);
6151         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6152         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6153                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6154
6155         if (no_queue)
6156                 /* Link no queues with irq0 */
6157                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6158                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6159 }
6160
6161 static void
6162 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6163 {
6164         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6165         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6166         int i;
6167         uint16_t abs_vf_id;
6168         uint32_t index, offset, val;
6169
6170         if (!pf->vfs)
6171                 return;
6172         /**
6173          * Try to find which VF trigger a reset, use absolute VF id to access
6174          * since the reg is global register.
6175          */
6176         for (i = 0; i < pf->vf_num; i++) {
6177                 abs_vf_id = hw->func_caps.vf_base_id + i;
6178                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6179                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6180                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6181                 /* VFR event occurred */
6182                 if (val & (0x1 << offset)) {
6183                         int ret;
6184
6185                         /* Clear the event first */
6186                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6187                                                         (0x1 << offset));
6188                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6189                         /**
6190                          * Only notify a VF reset event occurred,
6191                          * don't trigger another SW reset
6192                          */
6193                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6194                         if (ret != I40E_SUCCESS)
6195                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6196                 }
6197         }
6198 }
6199
6200 static void
6201 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6202 {
6203         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6204         int i;
6205
6206         for (i = 0; i < pf->vf_num; i++)
6207                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6208 }
6209
6210 static void
6211 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6212 {
6213         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6214         struct i40e_arq_event_info info;
6215         uint16_t pending, opcode;
6216         int ret;
6217
6218         info.buf_len = I40E_AQ_BUF_SZ;
6219         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6220         if (!info.msg_buf) {
6221                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6222                 return;
6223         }
6224
6225         pending = 1;
6226         while (pending) {
6227                 ret = i40e_clean_arq_element(hw, &info, &pending);
6228
6229                 if (ret != I40E_SUCCESS) {
6230                         PMD_DRV_LOG(INFO,
6231                                 "Failed to read msg from AdminQ, aq_err: %u",
6232                                 hw->aq.asq_last_status);
6233                         break;
6234                 }
6235                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6236
6237                 switch (opcode) {
6238                 case i40e_aqc_opc_send_msg_to_pf:
6239                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6240                         i40e_pf_host_handle_vf_msg(dev,
6241                                         rte_le_to_cpu_16(info.desc.retval),
6242                                         rte_le_to_cpu_32(info.desc.cookie_high),
6243                                         rte_le_to_cpu_32(info.desc.cookie_low),
6244                                         info.msg_buf,
6245                                         info.msg_len);
6246                         break;
6247                 case i40e_aqc_opc_get_link_status:
6248                         ret = i40e_dev_link_update(dev, 0);
6249                         if (!ret)
6250                                 _rte_eth_dev_callback_process(dev,
6251                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6252                         break;
6253                 default:
6254                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6255                                     opcode);
6256                         break;
6257                 }
6258         }
6259         rte_free(info.msg_buf);
6260 }
6261
6262 /**
6263  * Interrupt handler triggered by NIC  for handling
6264  * specific interrupt.
6265  *
6266  * @param handle
6267  *  Pointer to interrupt handle.
6268  * @param param
6269  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6270  *
6271  * @return
6272  *  void
6273  */
6274 static void
6275 i40e_dev_interrupt_handler(void *param)
6276 {
6277         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6278         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6279         uint32_t icr0;
6280
6281         /* Disable interrupt */
6282         i40e_pf_disable_irq0(hw);
6283
6284         /* read out interrupt causes */
6285         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6286
6287         /* No interrupt event indicated */
6288         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6289                 PMD_DRV_LOG(INFO, "No interrupt event");
6290                 goto done;
6291         }
6292         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6293                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6294         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6295                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6296         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6297                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6298         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6299                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6300         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6301                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6302         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6303                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6304         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6305                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6306
6307         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6308                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6309                 i40e_dev_handle_vfr_event(dev);
6310         }
6311         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6312                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6313                 i40e_dev_handle_aq_msg(dev);
6314         }
6315
6316 done:
6317         /* Enable interrupt */
6318         i40e_pf_enable_irq0(hw);
6319         rte_intr_enable(dev->intr_handle);
6320 }
6321
6322 int
6323 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6324                          struct i40e_macvlan_filter *filter,
6325                          int total)
6326 {
6327         int ele_num, ele_buff_size;
6328         int num, actual_num, i;
6329         uint16_t flags;
6330         int ret = I40E_SUCCESS;
6331         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6332         struct i40e_aqc_add_macvlan_element_data *req_list;
6333
6334         if (filter == NULL  || total == 0)
6335                 return I40E_ERR_PARAM;
6336         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6337         ele_buff_size = hw->aq.asq_buf_size;
6338
6339         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6340         if (req_list == NULL) {
6341                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6342                 return I40E_ERR_NO_MEMORY;
6343         }
6344
6345         num = 0;
6346         do {
6347                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6348                 memset(req_list, 0, ele_buff_size);
6349
6350                 for (i = 0; i < actual_num; i++) {
6351                         rte_memcpy(req_list[i].mac_addr,
6352                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6353                         req_list[i].vlan_tag =
6354                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6355
6356                         switch (filter[num + i].filter_type) {
6357                         case RTE_MAC_PERFECT_MATCH:
6358                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6359                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6360                                 break;
6361                         case RTE_MACVLAN_PERFECT_MATCH:
6362                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6363                                 break;
6364                         case RTE_MAC_HASH_MATCH:
6365                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6366                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6367                                 break;
6368                         case RTE_MACVLAN_HASH_MATCH:
6369                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6370                                 break;
6371                         default:
6372                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6373                                 ret = I40E_ERR_PARAM;
6374                                 goto DONE;
6375                         }
6376
6377                         req_list[i].queue_number = 0;
6378
6379                         req_list[i].flags = rte_cpu_to_le_16(flags);
6380                 }
6381
6382                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6383                                                 actual_num, NULL);
6384                 if (ret != I40E_SUCCESS) {
6385                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6386                         goto DONE;
6387                 }
6388                 num += actual_num;
6389         } while (num < total);
6390
6391 DONE:
6392         rte_free(req_list);
6393         return ret;
6394 }
6395
6396 int
6397 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6398                             struct i40e_macvlan_filter *filter,
6399                             int total)
6400 {
6401         int ele_num, ele_buff_size;
6402         int num, actual_num, i;
6403         uint16_t flags;
6404         int ret = I40E_SUCCESS;
6405         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6406         struct i40e_aqc_remove_macvlan_element_data *req_list;
6407
6408         if (filter == NULL  || total == 0)
6409                 return I40E_ERR_PARAM;
6410
6411         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6412         ele_buff_size = hw->aq.asq_buf_size;
6413
6414         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6415         if (req_list == NULL) {
6416                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6417                 return I40E_ERR_NO_MEMORY;
6418         }
6419
6420         num = 0;
6421         do {
6422                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6423                 memset(req_list, 0, ele_buff_size);
6424
6425                 for (i = 0; i < actual_num; i++) {
6426                         rte_memcpy(req_list[i].mac_addr,
6427                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6428                         req_list[i].vlan_tag =
6429                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6430
6431                         switch (filter[num + i].filter_type) {
6432                         case RTE_MAC_PERFECT_MATCH:
6433                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6434                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6435                                 break;
6436                         case RTE_MACVLAN_PERFECT_MATCH:
6437                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6438                                 break;
6439                         case RTE_MAC_HASH_MATCH:
6440                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6441                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6442                                 break;
6443                         case RTE_MACVLAN_HASH_MATCH:
6444                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6445                                 break;
6446                         default:
6447                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6448                                 ret = I40E_ERR_PARAM;
6449                                 goto DONE;
6450                         }
6451                         req_list[i].flags = rte_cpu_to_le_16(flags);
6452                 }
6453
6454                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6455                                                 actual_num, NULL);
6456                 if (ret != I40E_SUCCESS) {
6457                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6458                         goto DONE;
6459                 }
6460                 num += actual_num;
6461         } while (num < total);
6462
6463 DONE:
6464         rte_free(req_list);
6465         return ret;
6466 }
6467
6468 /* Find out specific MAC filter */
6469 static struct i40e_mac_filter *
6470 i40e_find_mac_filter(struct i40e_vsi *vsi,
6471                          struct ether_addr *macaddr)
6472 {
6473         struct i40e_mac_filter *f;
6474
6475         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6476                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6477                         return f;
6478         }
6479
6480         return NULL;
6481 }
6482
6483 static bool
6484 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6485                          uint16_t vlan_id)
6486 {
6487         uint32_t vid_idx, vid_bit;
6488
6489         if (vlan_id > ETH_VLAN_ID_MAX)
6490                 return 0;
6491
6492         vid_idx = I40E_VFTA_IDX(vlan_id);
6493         vid_bit = I40E_VFTA_BIT(vlan_id);
6494
6495         if (vsi->vfta[vid_idx] & vid_bit)
6496                 return 1;
6497         else
6498                 return 0;
6499 }
6500
6501 static void
6502 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6503                        uint16_t vlan_id, bool on)
6504 {
6505         uint32_t vid_idx, vid_bit;
6506
6507         vid_idx = I40E_VFTA_IDX(vlan_id);
6508         vid_bit = I40E_VFTA_BIT(vlan_id);
6509
6510         if (on)
6511                 vsi->vfta[vid_idx] |= vid_bit;
6512         else
6513                 vsi->vfta[vid_idx] &= ~vid_bit;
6514 }
6515
6516 void
6517 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6518                      uint16_t vlan_id, bool on)
6519 {
6520         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6521         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6522         int ret;
6523
6524         if (vlan_id > ETH_VLAN_ID_MAX)
6525                 return;
6526
6527         i40e_store_vlan_filter(vsi, vlan_id, on);
6528
6529         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6530                 return;
6531
6532         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6533
6534         if (on) {
6535                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6536                                        &vlan_data, 1, NULL);
6537                 if (ret != I40E_SUCCESS)
6538                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6539         } else {
6540                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6541                                           &vlan_data, 1, NULL);
6542                 if (ret != I40E_SUCCESS)
6543                         PMD_DRV_LOG(ERR,
6544                                     "Failed to remove vlan filter");
6545         }
6546 }
6547
6548 /**
6549  * Find all vlan options for specific mac addr,
6550  * return with actual vlan found.
6551  */
6552 int
6553 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6554                            struct i40e_macvlan_filter *mv_f,
6555                            int num, struct ether_addr *addr)
6556 {
6557         int i;
6558         uint32_t j, k;
6559
6560         /**
6561          * Not to use i40e_find_vlan_filter to decrease the loop time,
6562          * although the code looks complex.
6563           */
6564         if (num < vsi->vlan_num)
6565                 return I40E_ERR_PARAM;
6566
6567         i = 0;
6568         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6569                 if (vsi->vfta[j]) {
6570                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6571                                 if (vsi->vfta[j] & (1 << k)) {
6572                                         if (i > num - 1) {
6573                                                 PMD_DRV_LOG(ERR,
6574                                                         "vlan number doesn't match");
6575                                                 return I40E_ERR_PARAM;
6576                                         }
6577                                         rte_memcpy(&mv_f[i].macaddr,
6578                                                         addr, ETH_ADDR_LEN);
6579                                         mv_f[i].vlan_id =
6580                                                 j * I40E_UINT32_BIT_SIZE + k;
6581                                         i++;
6582                                 }
6583                         }
6584                 }
6585         }
6586         return I40E_SUCCESS;
6587 }
6588
6589 static inline int
6590 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6591                            struct i40e_macvlan_filter *mv_f,
6592                            int num,
6593                            uint16_t vlan)
6594 {
6595         int i = 0;
6596         struct i40e_mac_filter *f;
6597
6598         if (num < vsi->mac_num)
6599                 return I40E_ERR_PARAM;
6600
6601         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6602                 if (i > num - 1) {
6603                         PMD_DRV_LOG(ERR, "buffer number not match");
6604                         return I40E_ERR_PARAM;
6605                 }
6606                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6607                                 ETH_ADDR_LEN);
6608                 mv_f[i].vlan_id = vlan;
6609                 mv_f[i].filter_type = f->mac_info.filter_type;
6610                 i++;
6611         }
6612
6613         return I40E_SUCCESS;
6614 }
6615
6616 static int
6617 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6618 {
6619         int i, j, num;
6620         struct i40e_mac_filter *f;
6621         struct i40e_macvlan_filter *mv_f;
6622         int ret = I40E_SUCCESS;
6623
6624         if (vsi == NULL || vsi->mac_num == 0)
6625                 return I40E_ERR_PARAM;
6626
6627         /* Case that no vlan is set */
6628         if (vsi->vlan_num == 0)
6629                 num = vsi->mac_num;
6630         else
6631                 num = vsi->mac_num * vsi->vlan_num;
6632
6633         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6634         if (mv_f == NULL) {
6635                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6636                 return I40E_ERR_NO_MEMORY;
6637         }
6638
6639         i = 0;
6640         if (vsi->vlan_num == 0) {
6641                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6642                         rte_memcpy(&mv_f[i].macaddr,
6643                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6644                         mv_f[i].filter_type = f->mac_info.filter_type;
6645                         mv_f[i].vlan_id = 0;
6646                         i++;
6647                 }
6648         } else {
6649                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6650                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6651                                         vsi->vlan_num, &f->mac_info.mac_addr);
6652                         if (ret != I40E_SUCCESS)
6653                                 goto DONE;
6654                         for (j = i; j < i + vsi->vlan_num; j++)
6655                                 mv_f[j].filter_type = f->mac_info.filter_type;
6656                         i += vsi->vlan_num;
6657                 }
6658         }
6659
6660         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6661 DONE:
6662         rte_free(mv_f);
6663
6664         return ret;
6665 }
6666
6667 int
6668 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6669 {
6670         struct i40e_macvlan_filter *mv_f;
6671         int mac_num;
6672         int ret = I40E_SUCCESS;
6673
6674         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6675                 return I40E_ERR_PARAM;
6676
6677         /* If it's already set, just return */
6678         if (i40e_find_vlan_filter(vsi,vlan))
6679                 return I40E_SUCCESS;
6680
6681         mac_num = vsi->mac_num;
6682
6683         if (mac_num == 0) {
6684                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6685                 return I40E_ERR_PARAM;
6686         }
6687
6688         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6689
6690         if (mv_f == NULL) {
6691                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6692                 return I40E_ERR_NO_MEMORY;
6693         }
6694
6695         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6696
6697         if (ret != I40E_SUCCESS)
6698                 goto DONE;
6699
6700         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6701
6702         if (ret != I40E_SUCCESS)
6703                 goto DONE;
6704
6705         i40e_set_vlan_filter(vsi, vlan, 1);
6706
6707         vsi->vlan_num++;
6708         ret = I40E_SUCCESS;
6709 DONE:
6710         rte_free(mv_f);
6711         return ret;
6712 }
6713
6714 int
6715 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6716 {
6717         struct i40e_macvlan_filter *mv_f;
6718         int mac_num;
6719         int ret = I40E_SUCCESS;
6720
6721         /**
6722          * Vlan 0 is the generic filter for untagged packets
6723          * and can't be removed.
6724          */
6725         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6726                 return I40E_ERR_PARAM;
6727
6728         /* If can't find it, just return */
6729         if (!i40e_find_vlan_filter(vsi, vlan))
6730                 return I40E_ERR_PARAM;
6731
6732         mac_num = vsi->mac_num;
6733
6734         if (mac_num == 0) {
6735                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6736                 return I40E_ERR_PARAM;
6737         }
6738
6739         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6740
6741         if (mv_f == NULL) {
6742                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6743                 return I40E_ERR_NO_MEMORY;
6744         }
6745
6746         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6747
6748         if (ret != I40E_SUCCESS)
6749                 goto DONE;
6750
6751         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6752
6753         if (ret != I40E_SUCCESS)
6754                 goto DONE;
6755
6756         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6757         if (vsi->vlan_num == 1) {
6758                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6759                 if (ret != I40E_SUCCESS)
6760                         goto DONE;
6761
6762                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6763                 if (ret != I40E_SUCCESS)
6764                         goto DONE;
6765         }
6766
6767         i40e_set_vlan_filter(vsi, vlan, 0);
6768
6769         vsi->vlan_num--;
6770         ret = I40E_SUCCESS;
6771 DONE:
6772         rte_free(mv_f);
6773         return ret;
6774 }
6775
6776 int
6777 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6778 {
6779         struct i40e_mac_filter *f;
6780         struct i40e_macvlan_filter *mv_f;
6781         int i, vlan_num = 0;
6782         int ret = I40E_SUCCESS;
6783
6784         /* If it's add and we've config it, return */
6785         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6786         if (f != NULL)
6787                 return I40E_SUCCESS;
6788         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6789                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6790
6791                 /**
6792                  * If vlan_num is 0, that's the first time to add mac,
6793                  * set mask for vlan_id 0.
6794                  */
6795                 if (vsi->vlan_num == 0) {
6796                         i40e_set_vlan_filter(vsi, 0, 1);
6797                         vsi->vlan_num = 1;
6798                 }
6799                 vlan_num = vsi->vlan_num;
6800         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6801                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6802                 vlan_num = 1;
6803
6804         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6805         if (mv_f == NULL) {
6806                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6807                 return I40E_ERR_NO_MEMORY;
6808         }
6809
6810         for (i = 0; i < vlan_num; i++) {
6811                 mv_f[i].filter_type = mac_filter->filter_type;
6812                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6813                                 ETH_ADDR_LEN);
6814         }
6815
6816         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6817                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6818                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6819                                         &mac_filter->mac_addr);
6820                 if (ret != I40E_SUCCESS)
6821                         goto DONE;
6822         }
6823
6824         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6825         if (ret != I40E_SUCCESS)
6826                 goto DONE;
6827
6828         /* Add the mac addr into mac list */
6829         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6830         if (f == NULL) {
6831                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6832                 ret = I40E_ERR_NO_MEMORY;
6833                 goto DONE;
6834         }
6835         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6836                         ETH_ADDR_LEN);
6837         f->mac_info.filter_type = mac_filter->filter_type;
6838         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6839         vsi->mac_num++;
6840
6841         ret = I40E_SUCCESS;
6842 DONE:
6843         rte_free(mv_f);
6844
6845         return ret;
6846 }
6847
6848 int
6849 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6850 {
6851         struct i40e_mac_filter *f;
6852         struct i40e_macvlan_filter *mv_f;
6853         int i, vlan_num;
6854         enum rte_mac_filter_type filter_type;
6855         int ret = I40E_SUCCESS;
6856
6857         /* Can't find it, return an error */
6858         f = i40e_find_mac_filter(vsi, addr);
6859         if (f == NULL)
6860                 return I40E_ERR_PARAM;
6861
6862         vlan_num = vsi->vlan_num;
6863         filter_type = f->mac_info.filter_type;
6864         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6865                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6866                 if (vlan_num == 0) {
6867                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6868                         return I40E_ERR_PARAM;
6869                 }
6870         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6871                         filter_type == RTE_MAC_HASH_MATCH)
6872                 vlan_num = 1;
6873
6874         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6875         if (mv_f == NULL) {
6876                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6877                 return I40E_ERR_NO_MEMORY;
6878         }
6879
6880         for (i = 0; i < vlan_num; i++) {
6881                 mv_f[i].filter_type = filter_type;
6882                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6883                                 ETH_ADDR_LEN);
6884         }
6885         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6886                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6887                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6888                 if (ret != I40E_SUCCESS)
6889                         goto DONE;
6890         }
6891
6892         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6893         if (ret != I40E_SUCCESS)
6894                 goto DONE;
6895
6896         /* Remove the mac addr into mac list */
6897         TAILQ_REMOVE(&vsi->mac_list, f, next);
6898         rte_free(f);
6899         vsi->mac_num--;
6900
6901         ret = I40E_SUCCESS;
6902 DONE:
6903         rte_free(mv_f);
6904         return ret;
6905 }
6906
6907 /* Configure hash enable flags for RSS */
6908 uint64_t
6909 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6910 {
6911         uint64_t hena = 0;
6912         int i;
6913
6914         if (!flags)
6915                 return hena;
6916
6917         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6918                 if (flags & (1ULL << i))
6919                         hena |= adapter->pctypes_tbl[i];
6920         }
6921
6922         return hena;
6923 }
6924
6925 /* Parse the hash enable flags */
6926 uint64_t
6927 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6928 {
6929         uint64_t rss_hf = 0;
6930
6931         if (!flags)
6932                 return rss_hf;
6933         int i;
6934
6935         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6936                 if (flags & adapter->pctypes_tbl[i])
6937                         rss_hf |= (1ULL << i);
6938         }
6939         return rss_hf;
6940 }
6941
6942 /* Disable RSS */
6943 static void
6944 i40e_pf_disable_rss(struct i40e_pf *pf)
6945 {
6946         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6947
6948         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6949         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6950         I40E_WRITE_FLUSH(hw);
6951 }
6952
6953 int
6954 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6955 {
6956         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6957         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6958         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
6959                            I40E_VFQF_HKEY_MAX_INDEX :
6960                            I40E_PFQF_HKEY_MAX_INDEX;
6961         int ret = 0;
6962
6963         if (!key || key_len == 0) {
6964                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6965                 return 0;
6966         } else if (key_len != (key_idx + 1) *
6967                 sizeof(uint32_t)) {
6968                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6969                 return -EINVAL;
6970         }
6971
6972         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6973                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6974                         (struct i40e_aqc_get_set_rss_key_data *)key;
6975
6976                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6977                 if (ret)
6978                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6979         } else {
6980                 uint32_t *hash_key = (uint32_t *)key;
6981                 uint16_t i;
6982
6983                 if (vsi->type == I40E_VSI_SRIOV) {
6984                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
6985                                 I40E_WRITE_REG(
6986                                         hw,
6987                                         I40E_VFQF_HKEY1(i, vsi->user_param),
6988                                         hash_key[i]);
6989
6990                 } else {
6991                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6992                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
6993                                                hash_key[i]);
6994                 }
6995                 I40E_WRITE_FLUSH(hw);
6996         }
6997
6998         return ret;
6999 }
7000
7001 static int
7002 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7003 {
7004         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7005         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7006         uint32_t reg;
7007         int ret;
7008
7009         if (!key || !key_len)
7010                 return -EINVAL;
7011
7012         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7013                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7014                         (struct i40e_aqc_get_set_rss_key_data *)key);
7015                 if (ret) {
7016                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7017                         return ret;
7018                 }
7019         } else {
7020                 uint32_t *key_dw = (uint32_t *)key;
7021                 uint16_t i;
7022
7023                 if (vsi->type == I40E_VSI_SRIOV) {
7024                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7025                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7026                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7027                         }
7028                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7029                                    sizeof(uint32_t);
7030                 } else {
7031                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7032                                 reg = I40E_PFQF_HKEY(i);
7033                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7034                         }
7035                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7036                                    sizeof(uint32_t);
7037                 }
7038         }
7039         return 0;
7040 }
7041
7042 static int
7043 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7044 {
7045         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7046         uint64_t hena;
7047         int ret;
7048
7049         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7050                                rss_conf->rss_key_len);
7051         if (ret)
7052                 return ret;
7053
7054         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7055         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7056         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7057         I40E_WRITE_FLUSH(hw);
7058
7059         return 0;
7060 }
7061
7062 static int
7063 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7064                          struct rte_eth_rss_conf *rss_conf)
7065 {
7066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7068         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7069         uint64_t hena;
7070
7071         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7072         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7073
7074         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7075                 if (rss_hf != 0) /* Enable RSS */
7076                         return -EINVAL;
7077                 return 0; /* Nothing to do */
7078         }
7079         /* RSS enabled */
7080         if (rss_hf == 0) /* Disable RSS */
7081                 return -EINVAL;
7082
7083         return i40e_hw_rss_hash_set(pf, rss_conf);
7084 }
7085
7086 static int
7087 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7088                            struct rte_eth_rss_conf *rss_conf)
7089 {
7090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7091         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092         uint64_t hena;
7093
7094         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7095                          &rss_conf->rss_key_len);
7096
7097         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7098         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7099         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7100
7101         return 0;
7102 }
7103
7104 static int
7105 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7106 {
7107         switch (filter_type) {
7108         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7109                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7110                 break;
7111         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7112                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7113                 break;
7114         case RTE_TUNNEL_FILTER_IMAC_TENID:
7115                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7116                 break;
7117         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7118                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7119                 break;
7120         case ETH_TUNNEL_FILTER_IMAC:
7121                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7122                 break;
7123         case ETH_TUNNEL_FILTER_OIP:
7124                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7125                 break;
7126         case ETH_TUNNEL_FILTER_IIP:
7127                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7128                 break;
7129         default:
7130                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7131                 return -EINVAL;
7132         }
7133
7134         return 0;
7135 }
7136
7137 /* Convert tunnel filter structure */
7138 static int
7139 i40e_tunnel_filter_convert(
7140         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7141         struct i40e_tunnel_filter *tunnel_filter)
7142 {
7143         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7144                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7145         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7146                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7147         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7148         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7149              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7150             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7151                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7152         else
7153                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7154         tunnel_filter->input.flags = cld_filter->element.flags;
7155         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7156         tunnel_filter->queue = cld_filter->element.queue_number;
7157         rte_memcpy(tunnel_filter->input.general_fields,
7158                    cld_filter->general_fields,
7159                    sizeof(cld_filter->general_fields));
7160
7161         return 0;
7162 }
7163
7164 /* Check if there exists the tunnel filter */
7165 struct i40e_tunnel_filter *
7166 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7167                              const struct i40e_tunnel_filter_input *input)
7168 {
7169         int ret;
7170
7171         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7172         if (ret < 0)
7173                 return NULL;
7174
7175         return tunnel_rule->hash_map[ret];
7176 }
7177
7178 /* Add a tunnel filter into the SW list */
7179 static int
7180 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7181                              struct i40e_tunnel_filter *tunnel_filter)
7182 {
7183         struct i40e_tunnel_rule *rule = &pf->tunnel;
7184         int ret;
7185
7186         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7187         if (ret < 0) {
7188                 PMD_DRV_LOG(ERR,
7189                             "Failed to insert tunnel filter to hash table %d!",
7190                             ret);
7191                 return ret;
7192         }
7193         rule->hash_map[ret] = tunnel_filter;
7194
7195         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7196
7197         return 0;
7198 }
7199
7200 /* Delete a tunnel filter from the SW list */
7201 int
7202 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7203                           struct i40e_tunnel_filter_input *input)
7204 {
7205         struct i40e_tunnel_rule *rule = &pf->tunnel;
7206         struct i40e_tunnel_filter *tunnel_filter;
7207         int ret;
7208
7209         ret = rte_hash_del_key(rule->hash_table, input);
7210         if (ret < 0) {
7211                 PMD_DRV_LOG(ERR,
7212                             "Failed to delete tunnel filter to hash table %d!",
7213                             ret);
7214                 return ret;
7215         }
7216         tunnel_filter = rule->hash_map[ret];
7217         rule->hash_map[ret] = NULL;
7218
7219         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7220         rte_free(tunnel_filter);
7221
7222         return 0;
7223 }
7224
7225 int
7226 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7227                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7228                         uint8_t add)
7229 {
7230         uint16_t ip_type;
7231         uint32_t ipv4_addr, ipv4_addr_le;
7232         uint8_t i, tun_type = 0;
7233         /* internal varialbe to convert ipv6 byte order */
7234         uint32_t convert_ipv6[4];
7235         int val, ret = 0;
7236         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7237         struct i40e_vsi *vsi = pf->main_vsi;
7238         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7239         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7240         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7241         struct i40e_tunnel_filter *tunnel, *node;
7242         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7243
7244         cld_filter = rte_zmalloc("tunnel_filter",
7245                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7246         0);
7247
7248         if (NULL == cld_filter) {
7249                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7250                 return -ENOMEM;
7251         }
7252         pfilter = cld_filter;
7253
7254         ether_addr_copy(&tunnel_filter->outer_mac,
7255                         (struct ether_addr *)&pfilter->element.outer_mac);
7256         ether_addr_copy(&tunnel_filter->inner_mac,
7257                         (struct ether_addr *)&pfilter->element.inner_mac);
7258
7259         pfilter->element.inner_vlan =
7260                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7261         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7262                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7263                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7264                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7265                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7266                                 &ipv4_addr_le,
7267                                 sizeof(pfilter->element.ipaddr.v4.data));
7268         } else {
7269                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7270                 for (i = 0; i < 4; i++) {
7271                         convert_ipv6[i] =
7272                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7273                 }
7274                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7275                            &convert_ipv6,
7276                            sizeof(pfilter->element.ipaddr.v6.data));
7277         }
7278
7279         /* check tunneled type */
7280         switch (tunnel_filter->tunnel_type) {
7281         case RTE_TUNNEL_TYPE_VXLAN:
7282                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7283                 break;
7284         case RTE_TUNNEL_TYPE_NVGRE:
7285                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7286                 break;
7287         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7288                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7289                 break;
7290         default:
7291                 /* Other tunnel types is not supported. */
7292                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7293                 rte_free(cld_filter);
7294                 return -EINVAL;
7295         }
7296
7297         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7298                                        &pfilter->element.flags);
7299         if (val < 0) {
7300                 rte_free(cld_filter);
7301                 return -EINVAL;
7302         }
7303
7304         pfilter->element.flags |= rte_cpu_to_le_16(
7305                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7306                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7307         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7308         pfilter->element.queue_number =
7309                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7310
7311         /* Check if there is the filter in SW list */
7312         memset(&check_filter, 0, sizeof(check_filter));
7313         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7314         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7315         if (add && node) {
7316                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7317                 rte_free(cld_filter);
7318                 return -EINVAL;
7319         }
7320
7321         if (!add && !node) {
7322                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7323                 rte_free(cld_filter);
7324                 return -EINVAL;
7325         }
7326
7327         if (add) {
7328                 ret = i40e_aq_add_cloud_filters(hw,
7329                                         vsi->seid, &cld_filter->element, 1);
7330                 if (ret < 0) {
7331                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7332                         rte_free(cld_filter);
7333                         return -ENOTSUP;
7334                 }
7335                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7336                 if (tunnel == NULL) {
7337                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7338                         rte_free(cld_filter);
7339                         return -ENOMEM;
7340                 }
7341
7342                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7343                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7344                 if (ret < 0)
7345                         rte_free(tunnel);
7346         } else {
7347                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7348                                                    &cld_filter->element, 1);
7349                 if (ret < 0) {
7350                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7351                         rte_free(cld_filter);
7352                         return -ENOTSUP;
7353                 }
7354                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7355         }
7356
7357         rte_free(cld_filter);
7358         return ret;
7359 }
7360
7361 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7362 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7363 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7364 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7365 #define I40E_TR_GRE_KEY_MASK                    0x400
7366 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7367 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7368
7369 static enum
7370 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7371 {
7372         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7373         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7374         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7375         enum i40e_status_code status = I40E_SUCCESS;
7376
7377         if (pf->support_multi_driver) {
7378                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7379                 return I40E_NOT_SUPPORTED;
7380         }
7381
7382         memset(&filter_replace, 0,
7383                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7384         memset(&filter_replace_buf, 0,
7385                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7386
7387         /* create L1 filter */
7388         filter_replace.old_filter_type =
7389                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7390         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7391         filter_replace.tr_bit = 0;
7392
7393         /* Prepare the buffer, 3 entries */
7394         filter_replace_buf.data[0] =
7395                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7396         filter_replace_buf.data[0] |=
7397                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7398         filter_replace_buf.data[2] = 0xFF;
7399         filter_replace_buf.data[3] = 0xFF;
7400         filter_replace_buf.data[4] =
7401                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7402         filter_replace_buf.data[4] |=
7403                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7404         filter_replace_buf.data[7] = 0xF0;
7405         filter_replace_buf.data[8]
7406                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7407         filter_replace_buf.data[8] |=
7408                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7409         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7410                 I40E_TR_GENEVE_KEY_MASK |
7411                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7412         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7413                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7414                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7415
7416         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7417                                                &filter_replace_buf);
7418         if (!status) {
7419                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7420                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7421                             "cloud l1 type is changed from 0x%x to 0x%x",
7422                             filter_replace.old_filter_type,
7423                             filter_replace.new_filter_type);
7424         }
7425         return status;
7426 }
7427
7428 static enum
7429 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7430 {
7431         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7432         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7433         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7434         enum i40e_status_code status = I40E_SUCCESS;
7435
7436         if (pf->support_multi_driver) {
7437                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7438                 return I40E_NOT_SUPPORTED;
7439         }
7440
7441         /* For MPLSoUDP */
7442         memset(&filter_replace, 0,
7443                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7444         memset(&filter_replace_buf, 0,
7445                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7446         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7447                 I40E_AQC_MIRROR_CLOUD_FILTER;
7448         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7449         filter_replace.new_filter_type =
7450                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7451         /* Prepare the buffer, 2 entries */
7452         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7453         filter_replace_buf.data[0] |=
7454                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7455         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7456         filter_replace_buf.data[4] |=
7457                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7458         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7459                                                &filter_replace_buf);
7460         if (status < 0)
7461                 return status;
7462         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7463                     "cloud filter type is changed from 0x%x to 0x%x",
7464                     filter_replace.old_filter_type,
7465                     filter_replace.new_filter_type);
7466
7467         /* For MPLSoGRE */
7468         memset(&filter_replace, 0,
7469                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7470         memset(&filter_replace_buf, 0,
7471                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7472
7473         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7474                 I40E_AQC_MIRROR_CLOUD_FILTER;
7475         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7476         filter_replace.new_filter_type =
7477                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7478         /* Prepare the buffer, 2 entries */
7479         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7480         filter_replace_buf.data[0] |=
7481                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7482         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7483         filter_replace_buf.data[4] |=
7484                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7485
7486         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7487                                                &filter_replace_buf);
7488         if (!status) {
7489                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7490                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7491                             "cloud filter type is changed from 0x%x to 0x%x",
7492                             filter_replace.old_filter_type,
7493                             filter_replace.new_filter_type);
7494         }
7495         return status;
7496 }
7497
7498 static enum i40e_status_code
7499 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7500 {
7501         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7502         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7503         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7504         enum i40e_status_code status = I40E_SUCCESS;
7505
7506         if (pf->support_multi_driver) {
7507                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7508                 return I40E_NOT_SUPPORTED;
7509         }
7510
7511         /* For GTP-C */
7512         memset(&filter_replace, 0,
7513                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7514         memset(&filter_replace_buf, 0,
7515                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7516         /* create L1 filter */
7517         filter_replace.old_filter_type =
7518                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7519         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7520         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7521                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7522         /* Prepare the buffer, 2 entries */
7523         filter_replace_buf.data[0] =
7524                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7525         filter_replace_buf.data[0] |=
7526                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7527         filter_replace_buf.data[2] = 0xFF;
7528         filter_replace_buf.data[3] = 0xFF;
7529         filter_replace_buf.data[4] =
7530                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7531         filter_replace_buf.data[4] |=
7532                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7533         filter_replace_buf.data[6] = 0xFF;
7534         filter_replace_buf.data[7] = 0xFF;
7535         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7536                                                &filter_replace_buf);
7537         if (status < 0)
7538                 return status;
7539         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7540                     "cloud l1 type is changed from 0x%x to 0x%x",
7541                     filter_replace.old_filter_type,
7542                     filter_replace.new_filter_type);
7543
7544         /* for GTP-U */
7545         memset(&filter_replace, 0,
7546                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7547         memset(&filter_replace_buf, 0,
7548                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7549         /* create L1 filter */
7550         filter_replace.old_filter_type =
7551                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7552         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7553         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7554                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7555         /* Prepare the buffer, 2 entries */
7556         filter_replace_buf.data[0] =
7557                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7558         filter_replace_buf.data[0] |=
7559                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7560         filter_replace_buf.data[2] = 0xFF;
7561         filter_replace_buf.data[3] = 0xFF;
7562         filter_replace_buf.data[4] =
7563                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7564         filter_replace_buf.data[4] |=
7565                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7566         filter_replace_buf.data[6] = 0xFF;
7567         filter_replace_buf.data[7] = 0xFF;
7568
7569         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7570                                                &filter_replace_buf);
7571         if (!status) {
7572                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7573                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7574                             "cloud l1 type is changed from 0x%x to 0x%x",
7575                             filter_replace.old_filter_type,
7576                             filter_replace.new_filter_type);
7577         }
7578         return status;
7579 }
7580
7581 static enum
7582 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7583 {
7584         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7585         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7586         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7587         enum i40e_status_code status = I40E_SUCCESS;
7588
7589         if (pf->support_multi_driver) {
7590                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7591                 return I40E_NOT_SUPPORTED;
7592         }
7593
7594         /* for GTP-C */
7595         memset(&filter_replace, 0,
7596                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7597         memset(&filter_replace_buf, 0,
7598                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7599         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7600         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7601         filter_replace.new_filter_type =
7602                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7603         /* Prepare the buffer, 2 entries */
7604         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7605         filter_replace_buf.data[0] |=
7606                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7607         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7608         filter_replace_buf.data[4] |=
7609                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7610         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7611                                                &filter_replace_buf);
7612         if (status < 0)
7613                 return status;
7614         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7615                     "cloud filter type is changed from 0x%x to 0x%x",
7616                     filter_replace.old_filter_type,
7617                     filter_replace.new_filter_type);
7618
7619         /* for GTP-U */
7620         memset(&filter_replace, 0,
7621                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7622         memset(&filter_replace_buf, 0,
7623                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7624         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7625         filter_replace.old_filter_type =
7626                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7627         filter_replace.new_filter_type =
7628                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7629         /* Prepare the buffer, 2 entries */
7630         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7631         filter_replace_buf.data[0] |=
7632                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7633         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7634         filter_replace_buf.data[4] |=
7635                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7636
7637         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7638                                                &filter_replace_buf);
7639         if (!status) {
7640                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7641                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7642                             "cloud filter type is changed from 0x%x to 0x%x",
7643                             filter_replace.old_filter_type,
7644                             filter_replace.new_filter_type);
7645         }
7646         return status;
7647 }
7648
7649 int
7650 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7651                       struct i40e_tunnel_filter_conf *tunnel_filter,
7652                       uint8_t add)
7653 {
7654         uint16_t ip_type;
7655         uint32_t ipv4_addr, ipv4_addr_le;
7656         uint8_t i, tun_type = 0;
7657         /* internal variable to convert ipv6 byte order */
7658         uint32_t convert_ipv6[4];
7659         int val, ret = 0;
7660         struct i40e_pf_vf *vf = NULL;
7661         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7662         struct i40e_vsi *vsi;
7663         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7664         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7665         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7666         struct i40e_tunnel_filter *tunnel, *node;
7667         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7668         uint32_t teid_le;
7669         bool big_buffer = 0;
7670
7671         cld_filter = rte_zmalloc("tunnel_filter",
7672                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7673                          0);
7674
7675         if (cld_filter == NULL) {
7676                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7677                 return -ENOMEM;
7678         }
7679         pfilter = cld_filter;
7680
7681         ether_addr_copy(&tunnel_filter->outer_mac,
7682                         (struct ether_addr *)&pfilter->element.outer_mac);
7683         ether_addr_copy(&tunnel_filter->inner_mac,
7684                         (struct ether_addr *)&pfilter->element.inner_mac);
7685
7686         pfilter->element.inner_vlan =
7687                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7688         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7689                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7690                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7691                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7692                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7693                                 &ipv4_addr_le,
7694                                 sizeof(pfilter->element.ipaddr.v4.data));
7695         } else {
7696                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7697                 for (i = 0; i < 4; i++) {
7698                         convert_ipv6[i] =
7699                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7700                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7701                 }
7702                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7703                            &convert_ipv6,
7704                            sizeof(pfilter->element.ipaddr.v6.data));
7705         }
7706
7707         /* check tunneled type */
7708         switch (tunnel_filter->tunnel_type) {
7709         case I40E_TUNNEL_TYPE_VXLAN:
7710                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7711                 break;
7712         case I40E_TUNNEL_TYPE_NVGRE:
7713                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7714                 break;
7715         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7716                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7717                 break;
7718         case I40E_TUNNEL_TYPE_MPLSoUDP:
7719                 if (!pf->mpls_replace_flag) {
7720                         i40e_replace_mpls_l1_filter(pf);
7721                         i40e_replace_mpls_cloud_filter(pf);
7722                         pf->mpls_replace_flag = 1;
7723                 }
7724                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7725                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7726                         teid_le >> 4;
7727                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7728                         (teid_le & 0xF) << 12;
7729                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7730                         0x40;
7731                 big_buffer = 1;
7732                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7733                 break;
7734         case I40E_TUNNEL_TYPE_MPLSoGRE:
7735                 if (!pf->mpls_replace_flag) {
7736                         i40e_replace_mpls_l1_filter(pf);
7737                         i40e_replace_mpls_cloud_filter(pf);
7738                         pf->mpls_replace_flag = 1;
7739                 }
7740                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7741                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7742                         teid_le >> 4;
7743                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7744                         (teid_le & 0xF) << 12;
7745                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7746                         0x0;
7747                 big_buffer = 1;
7748                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7749                 break;
7750         case I40E_TUNNEL_TYPE_GTPC:
7751                 if (!pf->gtp_replace_flag) {
7752                         i40e_replace_gtp_l1_filter(pf);
7753                         i40e_replace_gtp_cloud_filter(pf);
7754                         pf->gtp_replace_flag = 1;
7755                 }
7756                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7757                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7758                         (teid_le >> 16) & 0xFFFF;
7759                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7760                         teid_le & 0xFFFF;
7761                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7762                         0x0;
7763                 big_buffer = 1;
7764                 break;
7765         case I40E_TUNNEL_TYPE_GTPU:
7766                 if (!pf->gtp_replace_flag) {
7767                         i40e_replace_gtp_l1_filter(pf);
7768                         i40e_replace_gtp_cloud_filter(pf);
7769                         pf->gtp_replace_flag = 1;
7770                 }
7771                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7772                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7773                         (teid_le >> 16) & 0xFFFF;
7774                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7775                         teid_le & 0xFFFF;
7776                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7777                         0x0;
7778                 big_buffer = 1;
7779                 break;
7780         case I40E_TUNNEL_TYPE_QINQ:
7781                 if (!pf->qinq_replace_flag) {
7782                         ret = i40e_cloud_filter_qinq_create(pf);
7783                         if (ret < 0)
7784                                 PMD_DRV_LOG(DEBUG,
7785                                             "QinQ tunnel filter already created.");
7786                         pf->qinq_replace_flag = 1;
7787                 }
7788                 /*      Add in the General fields the values of
7789                  *      the Outer and Inner VLAN
7790                  *      Big Buffer should be set, see changes in
7791                  *      i40e_aq_add_cloud_filters
7792                  */
7793                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7794                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7795                 big_buffer = 1;
7796                 break;
7797         default:
7798                 /* Other tunnel types is not supported. */
7799                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7800                 rte_free(cld_filter);
7801                 return -EINVAL;
7802         }
7803
7804         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7805                 pfilter->element.flags =
7806                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7807         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7808                 pfilter->element.flags =
7809                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7810         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7811                 pfilter->element.flags =
7812                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7813         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7814                 pfilter->element.flags =
7815                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7816         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7817                 pfilter->element.flags |=
7818                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7819         else {
7820                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7821                                                 &pfilter->element.flags);
7822                 if (val < 0) {
7823                         rte_free(cld_filter);
7824                         return -EINVAL;
7825                 }
7826         }
7827
7828         pfilter->element.flags |= rte_cpu_to_le_16(
7829                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7830                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7831         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7832         pfilter->element.queue_number =
7833                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7834
7835         if (!tunnel_filter->is_to_vf)
7836                 vsi = pf->main_vsi;
7837         else {
7838                 if (tunnel_filter->vf_id >= pf->vf_num) {
7839                         PMD_DRV_LOG(ERR, "Invalid argument.");
7840                         rte_free(cld_filter);
7841                         return -EINVAL;
7842                 }
7843                 vf = &pf->vfs[tunnel_filter->vf_id];
7844                 vsi = vf->vsi;
7845         }
7846
7847         /* Check if there is the filter in SW list */
7848         memset(&check_filter, 0, sizeof(check_filter));
7849         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7850         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7851         check_filter.vf_id = tunnel_filter->vf_id;
7852         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7853         if (add && node) {
7854                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7855                 rte_free(cld_filter);
7856                 return -EINVAL;
7857         }
7858
7859         if (!add && !node) {
7860                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7861                 rte_free(cld_filter);
7862                 return -EINVAL;
7863         }
7864
7865         if (add) {
7866                 if (big_buffer)
7867                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7868                                                    vsi->seid, cld_filter, 1);
7869                 else
7870                         ret = i40e_aq_add_cloud_filters(hw,
7871                                         vsi->seid, &cld_filter->element, 1);
7872                 if (ret < 0) {
7873                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7874                         rte_free(cld_filter);
7875                         return -ENOTSUP;
7876                 }
7877                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7878                 if (tunnel == NULL) {
7879                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7880                         rte_free(cld_filter);
7881                         return -ENOMEM;
7882                 }
7883
7884                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7885                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7886                 if (ret < 0)
7887                         rte_free(tunnel);
7888         } else {
7889                 if (big_buffer)
7890                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7891                                 hw, vsi->seid, cld_filter, 1);
7892                 else
7893                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7894                                                    &cld_filter->element, 1);
7895                 if (ret < 0) {
7896                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7897                         rte_free(cld_filter);
7898                         return -ENOTSUP;
7899                 }
7900                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7901         }
7902
7903         rte_free(cld_filter);
7904         return ret;
7905 }
7906
7907 static int
7908 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7909 {
7910         uint8_t i;
7911
7912         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7913                 if (pf->vxlan_ports[i] == port)
7914                         return i;
7915         }
7916
7917         return -1;
7918 }
7919
7920 static int
7921 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7922 {
7923         int  idx, ret;
7924         uint8_t filter_idx;
7925         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7926
7927         idx = i40e_get_vxlan_port_idx(pf, port);
7928
7929         /* Check if port already exists */
7930         if (idx >= 0) {
7931                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7932                 return -EINVAL;
7933         }
7934
7935         /* Now check if there is space to add the new port */
7936         idx = i40e_get_vxlan_port_idx(pf, 0);
7937         if (idx < 0) {
7938                 PMD_DRV_LOG(ERR,
7939                         "Maximum number of UDP ports reached, not adding port %d",
7940                         port);
7941                 return -ENOSPC;
7942         }
7943
7944         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7945                                         &filter_idx, NULL);
7946         if (ret < 0) {
7947                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7948                 return -1;
7949         }
7950
7951         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7952                          port,  filter_idx);
7953
7954         /* New port: add it and mark its index in the bitmap */
7955         pf->vxlan_ports[idx] = port;
7956         pf->vxlan_bitmap |= (1 << idx);
7957
7958         if (!(pf->flags & I40E_FLAG_VXLAN))
7959                 pf->flags |= I40E_FLAG_VXLAN;
7960
7961         return 0;
7962 }
7963
7964 static int
7965 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7966 {
7967         int idx;
7968         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7969
7970         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7971                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7972                 return -EINVAL;
7973         }
7974
7975         idx = i40e_get_vxlan_port_idx(pf, port);
7976
7977         if (idx < 0) {
7978                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7979                 return -EINVAL;
7980         }
7981
7982         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7983                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7984                 return -1;
7985         }
7986
7987         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7988                         port, idx);
7989
7990         pf->vxlan_ports[idx] = 0;
7991         pf->vxlan_bitmap &= ~(1 << idx);
7992
7993         if (!pf->vxlan_bitmap)
7994                 pf->flags &= ~I40E_FLAG_VXLAN;
7995
7996         return 0;
7997 }
7998
7999 /* Add UDP tunneling port */
8000 static int
8001 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8002                              struct rte_eth_udp_tunnel *udp_tunnel)
8003 {
8004         int ret = 0;
8005         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8006
8007         if (udp_tunnel == NULL)
8008                 return -EINVAL;
8009
8010         switch (udp_tunnel->prot_type) {
8011         case RTE_TUNNEL_TYPE_VXLAN:
8012                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8013                 break;
8014
8015         case RTE_TUNNEL_TYPE_GENEVE:
8016         case RTE_TUNNEL_TYPE_TEREDO:
8017                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8018                 ret = -1;
8019                 break;
8020
8021         default:
8022                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8023                 ret = -1;
8024                 break;
8025         }
8026
8027         return ret;
8028 }
8029
8030 /* Remove UDP tunneling port */
8031 static int
8032 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8033                              struct rte_eth_udp_tunnel *udp_tunnel)
8034 {
8035         int ret = 0;
8036         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8037
8038         if (udp_tunnel == NULL)
8039                 return -EINVAL;
8040
8041         switch (udp_tunnel->prot_type) {
8042         case RTE_TUNNEL_TYPE_VXLAN:
8043                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8044                 break;
8045         case RTE_TUNNEL_TYPE_GENEVE:
8046         case RTE_TUNNEL_TYPE_TEREDO:
8047                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8048                 ret = -1;
8049                 break;
8050         default:
8051                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8052                 ret = -1;
8053                 break;
8054         }
8055
8056         return ret;
8057 }
8058
8059 /* Calculate the maximum number of contiguous PF queues that are configured */
8060 static int
8061 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8062 {
8063         struct rte_eth_dev_data *data = pf->dev_data;
8064         int i, num;
8065         struct i40e_rx_queue *rxq;
8066
8067         num = 0;
8068         for (i = 0; i < pf->lan_nb_qps; i++) {
8069                 rxq = data->rx_queues[i];
8070                 if (rxq && rxq->q_set)
8071                         num++;
8072                 else
8073                         break;
8074         }
8075
8076         return num;
8077 }
8078
8079 /* Configure RSS */
8080 static int
8081 i40e_pf_config_rss(struct i40e_pf *pf)
8082 {
8083         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8084         struct rte_eth_rss_conf rss_conf;
8085         uint32_t i, lut = 0;
8086         uint16_t j, num;
8087
8088         /*
8089          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8090          * It's necessary to calculate the actual PF queues that are configured.
8091          */
8092         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8093                 num = i40e_pf_calc_configured_queues_num(pf);
8094         else
8095                 num = pf->dev_data->nb_rx_queues;
8096
8097         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8098         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8099                         num);
8100
8101         if (num == 0) {
8102                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8103                 return -ENOTSUP;
8104         }
8105
8106         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8107                 if (j == num)
8108                         j = 0;
8109                 lut = (lut << 8) | (j & ((0x1 <<
8110                         hw->func_caps.rss_table_entry_width) - 1));
8111                 if ((i & 3) == 3)
8112                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8113         }
8114
8115         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8116         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8117                 i40e_pf_disable_rss(pf);
8118                 return 0;
8119         }
8120         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8121                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8122                 /* Random default keys */
8123                 static uint32_t rss_key_default[] = {0x6b793944,
8124                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8125                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8126                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8127
8128                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8129                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8130                                                         sizeof(uint32_t);
8131         }
8132
8133         return i40e_hw_rss_hash_set(pf, &rss_conf);
8134 }
8135
8136 static int
8137 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8138                                struct rte_eth_tunnel_filter_conf *filter)
8139 {
8140         if (pf == NULL || filter == NULL) {
8141                 PMD_DRV_LOG(ERR, "Invalid parameter");
8142                 return -EINVAL;
8143         }
8144
8145         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8146                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8147                 return -EINVAL;
8148         }
8149
8150         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8151                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8152                 return -EINVAL;
8153         }
8154
8155         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8156                 (is_zero_ether_addr(&filter->outer_mac))) {
8157                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8158                 return -EINVAL;
8159         }
8160
8161         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8162                 (is_zero_ether_addr(&filter->inner_mac))) {
8163                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8164                 return -EINVAL;
8165         }
8166
8167         return 0;
8168 }
8169
8170 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8171 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8172 static int
8173 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8174 {
8175         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8176         uint32_t val, reg;
8177         int ret = -EINVAL;
8178
8179         if (pf->support_multi_driver) {
8180                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8181                 return -ENOTSUP;
8182         }
8183
8184         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8185         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8186
8187         if (len == 3) {
8188                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8189         } else if (len == 4) {
8190                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8191         } else {
8192                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8193                 return ret;
8194         }
8195
8196         if (reg != val) {
8197                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8198                                                    reg, NULL);
8199                 if (ret != 0)
8200                         return ret;
8201                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8202                             "with value 0x%08x",
8203                             I40E_GL_PRS_FVBM(2), reg);
8204                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8205         } else {
8206                 ret = 0;
8207         }
8208         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8209                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8210
8211         return ret;
8212 }
8213
8214 static int
8215 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8216 {
8217         int ret = -EINVAL;
8218
8219         if (!hw || !cfg)
8220                 return -EINVAL;
8221
8222         switch (cfg->cfg_type) {
8223         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8224                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8225                 break;
8226         default:
8227                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8228                 break;
8229         }
8230
8231         return ret;
8232 }
8233
8234 static int
8235 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8236                                enum rte_filter_op filter_op,
8237                                void *arg)
8238 {
8239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8240         int ret = I40E_ERR_PARAM;
8241
8242         switch (filter_op) {
8243         case RTE_ETH_FILTER_SET:
8244                 ret = i40e_dev_global_config_set(hw,
8245                         (struct rte_eth_global_cfg *)arg);
8246                 break;
8247         default:
8248                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8249                 break;
8250         }
8251
8252         return ret;
8253 }
8254
8255 static int
8256 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8257                           enum rte_filter_op filter_op,
8258                           void *arg)
8259 {
8260         struct rte_eth_tunnel_filter_conf *filter;
8261         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8262         int ret = I40E_SUCCESS;
8263
8264         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8265
8266         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8267                 return I40E_ERR_PARAM;
8268
8269         switch (filter_op) {
8270         case RTE_ETH_FILTER_NOP:
8271                 if (!(pf->flags & I40E_FLAG_VXLAN))
8272                         ret = I40E_NOT_SUPPORTED;
8273                 break;
8274         case RTE_ETH_FILTER_ADD:
8275                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8276                 break;
8277         case RTE_ETH_FILTER_DELETE:
8278                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8279                 break;
8280         default:
8281                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8282                 ret = I40E_ERR_PARAM;
8283                 break;
8284         }
8285
8286         return ret;
8287 }
8288
8289 static int
8290 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8291 {
8292         int ret = 0;
8293         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8294
8295         /* RSS setup */
8296         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8297                 ret = i40e_pf_config_rss(pf);
8298         else
8299                 i40e_pf_disable_rss(pf);
8300
8301         return ret;
8302 }
8303
8304 /* Get the symmetric hash enable configurations per port */
8305 static void
8306 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8307 {
8308         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8309
8310         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8311 }
8312
8313 /* Set the symmetric hash enable configurations per port */
8314 static void
8315 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8316 {
8317         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8318
8319         if (enable > 0) {
8320                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8321                         PMD_DRV_LOG(INFO,
8322                                 "Symmetric hash has already been enabled");
8323                         return;
8324                 }
8325                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8326         } else {
8327                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8328                         PMD_DRV_LOG(INFO,
8329                                 "Symmetric hash has already been disabled");
8330                         return;
8331                 }
8332                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8333         }
8334         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8335         I40E_WRITE_FLUSH(hw);
8336 }
8337
8338 /*
8339  * Get global configurations of hash function type and symmetric hash enable
8340  * per flow type (pctype). Note that global configuration means it affects all
8341  * the ports on the same NIC.
8342  */
8343 static int
8344 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8345                                    struct rte_eth_hash_global_conf *g_cfg)
8346 {
8347         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8348         uint32_t reg;
8349         uint16_t i, j;
8350
8351         memset(g_cfg, 0, sizeof(*g_cfg));
8352         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8353         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8354                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8355         else
8356                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8357         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8358                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8359
8360         /*
8361          * As i40e supports less than 64 flow types, only first 64 bits need to
8362          * be checked.
8363          */
8364         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8365                 g_cfg->valid_bit_mask[i] = 0ULL;
8366                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8367         }
8368
8369         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8370
8371         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8372                 if (!adapter->pctypes_tbl[i])
8373                         continue;
8374                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8375                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8376                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8377                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8378                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8379                                         g_cfg->sym_hash_enable_mask[0] |=
8380                                                                 (1ULL << i);
8381                                 }
8382                         }
8383                 }
8384         }
8385
8386         return 0;
8387 }
8388
8389 static int
8390 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8391                               const struct rte_eth_hash_global_conf *g_cfg)
8392 {
8393         uint32_t i;
8394         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8395
8396         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8397                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8398                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8399                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8400                                                 g_cfg->hash_func);
8401                 return -EINVAL;
8402         }
8403
8404         /*
8405          * As i40e supports less than 64 flow types, only first 64 bits need to
8406          * be checked.
8407          */
8408         mask0 = g_cfg->valid_bit_mask[0];
8409         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8410                 if (i == 0) {
8411                         /* Check if any unsupported flow type configured */
8412                         if ((mask0 | i40e_mask) ^ i40e_mask)
8413                                 goto mask_err;
8414                 } else {
8415                         if (g_cfg->valid_bit_mask[i])
8416                                 goto mask_err;
8417                 }
8418         }
8419
8420         return 0;
8421
8422 mask_err:
8423         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8424
8425         return -EINVAL;
8426 }
8427
8428 /*
8429  * Set global configurations of hash function type and symmetric hash enable
8430  * per flow type (pctype). Note any modifying global configuration will affect
8431  * all the ports on the same NIC.
8432  */
8433 static int
8434 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8435                                    struct rte_eth_hash_global_conf *g_cfg)
8436 {
8437         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8438         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8439         int ret;
8440         uint16_t i, j;
8441         uint32_t reg;
8442         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8443
8444         if (pf->support_multi_driver) {
8445                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8446                 return -ENOTSUP;
8447         }
8448
8449         /* Check the input parameters */
8450         ret = i40e_hash_global_config_check(adapter, g_cfg);
8451         if (ret < 0)
8452                 return ret;
8453
8454         /*
8455          * As i40e supports less than 64 flow types, only first 64 bits need to
8456          * be configured.
8457          */
8458         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8459                 if (mask0 & (1UL << i)) {
8460                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8461                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8462
8463                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8464                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8465                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8466                                         i40e_write_global_rx_ctl(hw,
8467                                                           I40E_GLQF_HSYM(j),
8468                                                           reg);
8469                         }
8470                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8471                 }
8472         }
8473
8474         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8475         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8476                 /* Toeplitz */
8477                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8478                         PMD_DRV_LOG(DEBUG,
8479                                 "Hash function already set to Toeplitz");
8480                         goto out;
8481                 }
8482                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8483         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8484                 /* Simple XOR */
8485                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8486                         PMD_DRV_LOG(DEBUG,
8487                                 "Hash function already set to Simple XOR");
8488                         goto out;
8489                 }
8490                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8491         } else
8492                 /* Use the default, and keep it as it is */
8493                 goto out;
8494
8495         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8496         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8497
8498 out:
8499         I40E_WRITE_FLUSH(hw);
8500
8501         return 0;
8502 }
8503
8504 /**
8505  * Valid input sets for hash and flow director filters per PCTYPE
8506  */
8507 static uint64_t
8508 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8509                 enum rte_filter_type filter)
8510 {
8511         uint64_t valid;
8512
8513         static const uint64_t valid_hash_inset_table[] = {
8514                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8515                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8516                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8517                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8518                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8519                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8520                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8521                         I40E_INSET_FLEX_PAYLOAD,
8522                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8523                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8524                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8525                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8526                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8527                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8528                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8529                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8530                         I40E_INSET_FLEX_PAYLOAD,
8531                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8532                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8533                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8534                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8535                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8536                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8537                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8538                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8539                         I40E_INSET_FLEX_PAYLOAD,
8540                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8541                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8542                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8543                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8544                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8545                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8546                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8547                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8548                         I40E_INSET_FLEX_PAYLOAD,
8549                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8550                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8551                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8552                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8553                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8554                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8555                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8556                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8557                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8558                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8559                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8560                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8561                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8562                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8563                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8564                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8565                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8566                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8567                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8568                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8569                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8570                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8571                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8572                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8573                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8574                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8575                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8576                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8577                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8578                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8579                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8580                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8581                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8582                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8583                         I40E_INSET_FLEX_PAYLOAD,
8584                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8585                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8586                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8587                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8588                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8589                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8590                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8591                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8592                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8593                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8594                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8595                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8596                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8597                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8598                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8599                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8600                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8601                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8602                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8603                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8604                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8605                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8606                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8607                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8608                         I40E_INSET_FLEX_PAYLOAD,
8609                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8610                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8611                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8612                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8613                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8614                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8615                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8616                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8617                         I40E_INSET_FLEX_PAYLOAD,
8618                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8619                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8620                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8621                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8622                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8623                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8624                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8625                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8626                         I40E_INSET_FLEX_PAYLOAD,
8627                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8628                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8629                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8630                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8631                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8632                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8633                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8634                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8635                         I40E_INSET_FLEX_PAYLOAD,
8636                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8637                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8638                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8639                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8640                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8641                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8642                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8643                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8644                         I40E_INSET_FLEX_PAYLOAD,
8645                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8646                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8647                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8648                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8649                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8650                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8651                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8652                         I40E_INSET_FLEX_PAYLOAD,
8653                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8654                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8655                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8656                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8657                         I40E_INSET_FLEX_PAYLOAD,
8658         };
8659
8660         /**
8661          * Flow director supports only fields defined in
8662          * union rte_eth_fdir_flow.
8663          */
8664         static const uint64_t valid_fdir_inset_table[] = {
8665                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8666                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8667                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8668                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8669                 I40E_INSET_IPV4_TTL,
8670                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8671                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8672                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8673                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8674                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8675                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8676                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8677                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8678                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8679                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8680                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8681                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8682                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8683                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8684                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8685                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8686                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8687                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8688                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8689                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8690                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8691                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8692                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8693                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8694                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8695                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8696                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8697                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8698                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8699                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8700                 I40E_INSET_SCTP_VT,
8701                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8702                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8703                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8704                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8705                 I40E_INSET_IPV4_TTL,
8706                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8707                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8708                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8709                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8710                 I40E_INSET_IPV6_HOP_LIMIT,
8711                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8712                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8713                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8714                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8715                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8716                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8717                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8718                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8719                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8720                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8721                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8722                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8723                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8724                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8725                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8726                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8727                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8728                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8729                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8730                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8731                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8732                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8733                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8734                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8735                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8736                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8737                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8738                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8739                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8740                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8741                 I40E_INSET_SCTP_VT,
8742                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8743                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8744                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8745                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8746                 I40E_INSET_IPV6_HOP_LIMIT,
8747                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8748                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8749                 I40E_INSET_LAST_ETHER_TYPE,
8750         };
8751
8752         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8753                 return 0;
8754         if (filter == RTE_ETH_FILTER_HASH)
8755                 valid = valid_hash_inset_table[pctype];
8756         else
8757                 valid = valid_fdir_inset_table[pctype];
8758
8759         return valid;
8760 }
8761
8762 /**
8763  * Validate if the input set is allowed for a specific PCTYPE
8764  */
8765 int
8766 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8767                 enum rte_filter_type filter, uint64_t inset)
8768 {
8769         uint64_t valid;
8770
8771         valid = i40e_get_valid_input_set(pctype, filter);
8772         if (inset & (~valid))
8773                 return -EINVAL;
8774
8775         return 0;
8776 }
8777
8778 /* default input set fields combination per pctype */
8779 uint64_t
8780 i40e_get_default_input_set(uint16_t pctype)
8781 {
8782         static const uint64_t default_inset_table[] = {
8783                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8784                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8785                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8786                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8787                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8788                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8789                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8790                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8791                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8792                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8793                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8794                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8795                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8796                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8797                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8798                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8799                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8800                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8801                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8802                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8803                         I40E_INSET_SCTP_VT,
8804                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8805                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8806                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8807                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8808                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8809                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8810                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8811                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8812                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8813                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8814                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8815                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8816                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8817                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8818                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8819                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8820                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8821                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8822                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8823                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8824                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8825                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8826                         I40E_INSET_SCTP_VT,
8827                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8828                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8829                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8830                         I40E_INSET_LAST_ETHER_TYPE,
8831         };
8832
8833         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8834                 return 0;
8835
8836         return default_inset_table[pctype];
8837 }
8838
8839 /**
8840  * Parse the input set from index to logical bit masks
8841  */
8842 static int
8843 i40e_parse_input_set(uint64_t *inset,
8844                      enum i40e_filter_pctype pctype,
8845                      enum rte_eth_input_set_field *field,
8846                      uint16_t size)
8847 {
8848         uint16_t i, j;
8849         int ret = -EINVAL;
8850
8851         static const struct {
8852                 enum rte_eth_input_set_field field;
8853                 uint64_t inset;
8854         } inset_convert_table[] = {
8855                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8856                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8857                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8858                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8859                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8860                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8861                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8862                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8863                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8864                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8865                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8866                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8867                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8868                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8869                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8870                         I40E_INSET_IPV6_NEXT_HDR},
8871                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8872                         I40E_INSET_IPV6_HOP_LIMIT},
8873                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8874                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8875                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8876                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8877                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8878                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8879                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8880                         I40E_INSET_SCTP_VT},
8881                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8882                         I40E_INSET_TUNNEL_DMAC},
8883                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8884                         I40E_INSET_VLAN_TUNNEL},
8885                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8886                         I40E_INSET_TUNNEL_ID},
8887                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8888                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8889                         I40E_INSET_FLEX_PAYLOAD_W1},
8890                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8891                         I40E_INSET_FLEX_PAYLOAD_W2},
8892                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8893                         I40E_INSET_FLEX_PAYLOAD_W3},
8894                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8895                         I40E_INSET_FLEX_PAYLOAD_W4},
8896                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8897                         I40E_INSET_FLEX_PAYLOAD_W5},
8898                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8899                         I40E_INSET_FLEX_PAYLOAD_W6},
8900                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8901                         I40E_INSET_FLEX_PAYLOAD_W7},
8902                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8903                         I40E_INSET_FLEX_PAYLOAD_W8},
8904         };
8905
8906         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8907                 return ret;
8908
8909         /* Only one item allowed for default or all */
8910         if (size == 1) {
8911                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8912                         *inset = i40e_get_default_input_set(pctype);
8913                         return 0;
8914                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8915                         *inset = I40E_INSET_NONE;
8916                         return 0;
8917                 }
8918         }
8919
8920         for (i = 0, *inset = 0; i < size; i++) {
8921                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8922                         if (field[i] == inset_convert_table[j].field) {
8923                                 *inset |= inset_convert_table[j].inset;
8924                                 break;
8925                         }
8926                 }
8927
8928                 /* It contains unsupported input set, return immediately */
8929                 if (j == RTE_DIM(inset_convert_table))
8930                         return ret;
8931         }
8932
8933         return 0;
8934 }
8935
8936 /**
8937  * Translate the input set from bit masks to register aware bit masks
8938  * and vice versa
8939  */
8940 uint64_t
8941 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8942 {
8943         uint64_t val = 0;
8944         uint16_t i;
8945
8946         struct inset_map {
8947                 uint64_t inset;
8948                 uint64_t inset_reg;
8949         };
8950
8951         static const struct inset_map inset_map_common[] = {
8952                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8953                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8954                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8955                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8956                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8957                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8958                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8959                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8960                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8961                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8962                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8963                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8964                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8965                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8966                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8967                 {I40E_INSET_TUNNEL_DMAC,
8968                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8969                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8970                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8971                 {I40E_INSET_TUNNEL_SRC_PORT,
8972                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8973                 {I40E_INSET_TUNNEL_DST_PORT,
8974                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8975                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8976                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8977                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8978                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8979                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8980                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8981                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8982                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8983                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8984         };
8985
8986     /* some different registers map in x722*/
8987         static const struct inset_map inset_map_diff_x722[] = {
8988                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8989                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8990                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8991                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8992         };
8993
8994         static const struct inset_map inset_map_diff_not_x722[] = {
8995                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8996                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8997                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8998                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8999         };
9000
9001         if (input == 0)
9002                 return val;
9003
9004         /* Translate input set to register aware inset */
9005         if (type == I40E_MAC_X722) {
9006                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9007                         if (input & inset_map_diff_x722[i].inset)
9008                                 val |= inset_map_diff_x722[i].inset_reg;
9009                 }
9010         } else {
9011                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9012                         if (input & inset_map_diff_not_x722[i].inset)
9013                                 val |= inset_map_diff_not_x722[i].inset_reg;
9014                 }
9015         }
9016
9017         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9018                 if (input & inset_map_common[i].inset)
9019                         val |= inset_map_common[i].inset_reg;
9020         }
9021
9022         return val;
9023 }
9024
9025 int
9026 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9027 {
9028         uint8_t i, idx = 0;
9029         uint64_t inset_need_mask = inset;
9030
9031         static const struct {
9032                 uint64_t inset;
9033                 uint32_t mask;
9034         } inset_mask_map[] = {
9035                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9036                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9037                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9038                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9039                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9040                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9041                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9042                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9043         };
9044
9045         if (!inset || !mask || !nb_elem)
9046                 return 0;
9047
9048         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9049                 /* Clear the inset bit, if no MASK is required,
9050                  * for example proto + ttl
9051                  */
9052                 if ((inset & inset_mask_map[i].inset) ==
9053                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9054                         inset_need_mask &= ~inset_mask_map[i].inset;
9055                 if (!inset_need_mask)
9056                         return 0;
9057         }
9058         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9059                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9060                     inset_mask_map[i].inset) {
9061                         if (idx >= nb_elem) {
9062                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9063                                 return -EINVAL;
9064                         }
9065                         mask[idx] = inset_mask_map[i].mask;
9066                         idx++;
9067                 }
9068         }
9069
9070         return idx;
9071 }
9072
9073 void
9074 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9075 {
9076         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9077
9078         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9079         if (reg != val)
9080                 i40e_write_rx_ctl(hw, addr, val);
9081         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9082                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9083 }
9084
9085 void
9086 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9087 {
9088         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9089
9090         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9091         if (reg != val)
9092                 i40e_write_global_rx_ctl(hw, addr, val);
9093         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9094                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9095 }
9096
9097 static void
9098 i40e_filter_input_set_init(struct i40e_pf *pf)
9099 {
9100         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9101         enum i40e_filter_pctype pctype;
9102         uint64_t input_set, inset_reg;
9103         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9104         int num, i;
9105         uint16_t flow_type;
9106
9107         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9108              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9109                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9110
9111                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9112                         continue;
9113
9114                 input_set = i40e_get_default_input_set(pctype);
9115
9116                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9117                                                    I40E_INSET_MASK_NUM_REG);
9118                 if (num < 0)
9119                         return;
9120                 if (pf->support_multi_driver && num > 0) {
9121                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9122                         return;
9123                 }
9124                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9125                                         input_set);
9126
9127                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9128                                       (uint32_t)(inset_reg & UINT32_MAX));
9129                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9130                                      (uint32_t)((inset_reg >>
9131                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9132                 if (!pf->support_multi_driver) {
9133                         i40e_check_write_global_reg(hw,
9134                                             I40E_GLQF_HASH_INSET(0, pctype),
9135                                             (uint32_t)(inset_reg & UINT32_MAX));
9136                         i40e_check_write_global_reg(hw,
9137                                              I40E_GLQF_HASH_INSET(1, pctype),
9138                                              (uint32_t)((inset_reg >>
9139                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9140
9141                         for (i = 0; i < num; i++) {
9142                                 i40e_check_write_global_reg(hw,
9143                                                     I40E_GLQF_FD_MSK(i, pctype),
9144                                                     mask_reg[i]);
9145                                 i40e_check_write_global_reg(hw,
9146                                                   I40E_GLQF_HASH_MSK(i, pctype),
9147                                                   mask_reg[i]);
9148                         }
9149                         /*clear unused mask registers of the pctype */
9150                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9151                                 i40e_check_write_global_reg(hw,
9152                                                     I40E_GLQF_FD_MSK(i, pctype),
9153                                                     0);
9154                                 i40e_check_write_global_reg(hw,
9155                                                   I40E_GLQF_HASH_MSK(i, pctype),
9156                                                   0);
9157                         }
9158                 } else {
9159                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9160                 }
9161                 I40E_WRITE_FLUSH(hw);
9162
9163                 /* store the default input set */
9164                 if (!pf->support_multi_driver)
9165                         pf->hash_input_set[pctype] = input_set;
9166                 pf->fdir.input_set[pctype] = input_set;
9167         }
9168
9169         if (!pf->support_multi_driver) {
9170                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9171                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9172                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9173         }
9174 }
9175
9176 int
9177 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9178                          struct rte_eth_input_set_conf *conf)
9179 {
9180         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9181         enum i40e_filter_pctype pctype;
9182         uint64_t input_set, inset_reg = 0;
9183         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9184         int ret, i, num;
9185
9186         if (!conf) {
9187                 PMD_DRV_LOG(ERR, "Invalid pointer");
9188                 return -EFAULT;
9189         }
9190         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9191             conf->op != RTE_ETH_INPUT_SET_ADD) {
9192                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9193                 return -EINVAL;
9194         }
9195
9196         if (pf->support_multi_driver) {
9197                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9198                 return -ENOTSUP;
9199         }
9200
9201         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9202         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9203                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9204                 return -EINVAL;
9205         }
9206
9207         if (hw->mac.type == I40E_MAC_X722) {
9208                 /* get translated pctype value in fd pctype register */
9209                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9210                         I40E_GLQF_FD_PCTYPES((int)pctype));
9211         }
9212
9213         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9214                                    conf->inset_size);
9215         if (ret) {
9216                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9217                 return -EINVAL;
9218         }
9219
9220         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9221                 /* get inset value in register */
9222                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9223                 inset_reg <<= I40E_32_BIT_WIDTH;
9224                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9225                 input_set |= pf->hash_input_set[pctype];
9226         }
9227         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9228                                            I40E_INSET_MASK_NUM_REG);
9229         if (num < 0)
9230                 return -EINVAL;
9231
9232         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9233
9234         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9235                                     (uint32_t)(inset_reg & UINT32_MAX));
9236         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9237                                     (uint32_t)((inset_reg >>
9238                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9239         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9240
9241         for (i = 0; i < num; i++)
9242                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9243                                             mask_reg[i]);
9244         /*clear unused mask registers of the pctype */
9245         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9246                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9247                                             0);
9248         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9249         I40E_WRITE_FLUSH(hw);
9250
9251         pf->hash_input_set[pctype] = input_set;
9252         return 0;
9253 }
9254
9255 int
9256 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9257                          struct rte_eth_input_set_conf *conf)
9258 {
9259         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9260         enum i40e_filter_pctype pctype;
9261         uint64_t input_set, inset_reg = 0;
9262         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9263         int ret, i, num;
9264
9265         if (!hw || !conf) {
9266                 PMD_DRV_LOG(ERR, "Invalid pointer");
9267                 return -EFAULT;
9268         }
9269         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9270             conf->op != RTE_ETH_INPUT_SET_ADD) {
9271                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9272                 return -EINVAL;
9273         }
9274
9275         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9276
9277         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9278                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9279                 return -EINVAL;
9280         }
9281
9282         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9283                                    conf->inset_size);
9284         if (ret) {
9285                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9286                 return -EINVAL;
9287         }
9288
9289         /* get inset value in register */
9290         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9291         inset_reg <<= I40E_32_BIT_WIDTH;
9292         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9293
9294         /* Can not change the inset reg for flex payload for fdir,
9295          * it is done by writing I40E_PRTQF_FD_FLXINSET
9296          * in i40e_set_flex_mask_on_pctype.
9297          */
9298         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9299                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9300         else
9301                 input_set |= pf->fdir.input_set[pctype];
9302         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9303                                            I40E_INSET_MASK_NUM_REG);
9304         if (num < 0)
9305                 return -EINVAL;
9306         if (pf->support_multi_driver && num > 0) {
9307                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9308                 return -ENOTSUP;
9309         }
9310
9311         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9312
9313         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9314                               (uint32_t)(inset_reg & UINT32_MAX));
9315         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9316                              (uint32_t)((inset_reg >>
9317                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9318
9319         if (!pf->support_multi_driver) {
9320                 for (i = 0; i < num; i++)
9321                         i40e_check_write_global_reg(hw,
9322                                                     I40E_GLQF_FD_MSK(i, pctype),
9323                                                     mask_reg[i]);
9324                 /*clear unused mask registers of the pctype */
9325                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9326                         i40e_check_write_global_reg(hw,
9327                                                     I40E_GLQF_FD_MSK(i, pctype),
9328                                                     0);
9329                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9330         } else {
9331                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9332         }
9333         I40E_WRITE_FLUSH(hw);
9334
9335         pf->fdir.input_set[pctype] = input_set;
9336         return 0;
9337 }
9338
9339 static int
9340 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9341 {
9342         int ret = 0;
9343
9344         if (!hw || !info) {
9345                 PMD_DRV_LOG(ERR, "Invalid pointer");
9346                 return -EFAULT;
9347         }
9348
9349         switch (info->info_type) {
9350         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9351                 i40e_get_symmetric_hash_enable_per_port(hw,
9352                                         &(info->info.enable));
9353                 break;
9354         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9355                 ret = i40e_get_hash_filter_global_config(hw,
9356                                 &(info->info.global_conf));
9357                 break;
9358         default:
9359                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9360                                                         info->info_type);
9361                 ret = -EINVAL;
9362                 break;
9363         }
9364
9365         return ret;
9366 }
9367
9368 static int
9369 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9370 {
9371         int ret = 0;
9372
9373         if (!hw || !info) {
9374                 PMD_DRV_LOG(ERR, "Invalid pointer");
9375                 return -EFAULT;
9376         }
9377
9378         switch (info->info_type) {
9379         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9380                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9381                 break;
9382         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9383                 ret = i40e_set_hash_filter_global_config(hw,
9384                                 &(info->info.global_conf));
9385                 break;
9386         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9387                 ret = i40e_hash_filter_inset_select(hw,
9388                                                &(info->info.input_set_conf));
9389                 break;
9390
9391         default:
9392                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9393                                                         info->info_type);
9394                 ret = -EINVAL;
9395                 break;
9396         }
9397
9398         return ret;
9399 }
9400
9401 /* Operations for hash function */
9402 static int
9403 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9404                       enum rte_filter_op filter_op,
9405                       void *arg)
9406 {
9407         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9408         int ret = 0;
9409
9410         switch (filter_op) {
9411         case RTE_ETH_FILTER_NOP:
9412                 break;
9413         case RTE_ETH_FILTER_GET:
9414                 ret = i40e_hash_filter_get(hw,
9415                         (struct rte_eth_hash_filter_info *)arg);
9416                 break;
9417         case RTE_ETH_FILTER_SET:
9418                 ret = i40e_hash_filter_set(hw,
9419                         (struct rte_eth_hash_filter_info *)arg);
9420                 break;
9421         default:
9422                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9423                                                                 filter_op);
9424                 ret = -ENOTSUP;
9425                 break;
9426         }
9427
9428         return ret;
9429 }
9430
9431 /* Convert ethertype filter structure */
9432 static int
9433 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9434                               struct i40e_ethertype_filter *filter)
9435 {
9436         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9437         filter->input.ether_type = input->ether_type;
9438         filter->flags = input->flags;
9439         filter->queue = input->queue;
9440
9441         return 0;
9442 }
9443
9444 /* Check if there exists the ehtertype filter */
9445 struct i40e_ethertype_filter *
9446 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9447                                 const struct i40e_ethertype_filter_input *input)
9448 {
9449         int ret;
9450
9451         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9452         if (ret < 0)
9453                 return NULL;
9454
9455         return ethertype_rule->hash_map[ret];
9456 }
9457
9458 /* Add ethertype filter in SW list */
9459 static int
9460 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9461                                 struct i40e_ethertype_filter *filter)
9462 {
9463         struct i40e_ethertype_rule *rule = &pf->ethertype;
9464         int ret;
9465
9466         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9467         if (ret < 0) {
9468                 PMD_DRV_LOG(ERR,
9469                             "Failed to insert ethertype filter"
9470                             " to hash table %d!",
9471                             ret);
9472                 return ret;
9473         }
9474         rule->hash_map[ret] = filter;
9475
9476         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9477
9478         return 0;
9479 }
9480
9481 /* Delete ethertype filter in SW list */
9482 int
9483 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9484                              struct i40e_ethertype_filter_input *input)
9485 {
9486         struct i40e_ethertype_rule *rule = &pf->ethertype;
9487         struct i40e_ethertype_filter *filter;
9488         int ret;
9489
9490         ret = rte_hash_del_key(rule->hash_table, input);
9491         if (ret < 0) {
9492                 PMD_DRV_LOG(ERR,
9493                             "Failed to delete ethertype filter"
9494                             " to hash table %d!",
9495                             ret);
9496                 return ret;
9497         }
9498         filter = rule->hash_map[ret];
9499         rule->hash_map[ret] = NULL;
9500
9501         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9502         rte_free(filter);
9503
9504         return 0;
9505 }
9506
9507 /*
9508  * Configure ethertype filter, which can director packet by filtering
9509  * with mac address and ether_type or only ether_type
9510  */
9511 int
9512 i40e_ethertype_filter_set(struct i40e_pf *pf,
9513                         struct rte_eth_ethertype_filter *filter,
9514                         bool add)
9515 {
9516         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9517         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9518         struct i40e_ethertype_filter *ethertype_filter, *node;
9519         struct i40e_ethertype_filter check_filter;
9520         struct i40e_control_filter_stats stats;
9521         uint16_t flags = 0;
9522         int ret;
9523
9524         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9525                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9526                 return -EINVAL;
9527         }
9528         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9529                 filter->ether_type == ETHER_TYPE_IPv6) {
9530                 PMD_DRV_LOG(ERR,
9531                         "unsupported ether_type(0x%04x) in control packet filter.",
9532                         filter->ether_type);
9533                 return -EINVAL;
9534         }
9535         if (filter->ether_type == ETHER_TYPE_VLAN)
9536                 PMD_DRV_LOG(WARNING,
9537                         "filter vlan ether_type in first tag is not supported.");
9538
9539         /* Check if there is the filter in SW list */
9540         memset(&check_filter, 0, sizeof(check_filter));
9541         i40e_ethertype_filter_convert(filter, &check_filter);
9542         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9543                                                &check_filter.input);
9544         if (add && node) {
9545                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9546                 return -EINVAL;
9547         }
9548
9549         if (!add && !node) {
9550                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9551                 return -EINVAL;
9552         }
9553
9554         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9555                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9556         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9557                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9558         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9559
9560         memset(&stats, 0, sizeof(stats));
9561         ret = i40e_aq_add_rem_control_packet_filter(hw,
9562                         filter->mac_addr.addr_bytes,
9563                         filter->ether_type, flags,
9564                         pf->main_vsi->seid,
9565                         filter->queue, add, &stats, NULL);
9566
9567         PMD_DRV_LOG(INFO,
9568                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9569                 ret, stats.mac_etype_used, stats.etype_used,
9570                 stats.mac_etype_free, stats.etype_free);
9571         if (ret < 0)
9572                 return -ENOSYS;
9573
9574         /* Add or delete a filter in SW list */
9575         if (add) {
9576                 ethertype_filter = rte_zmalloc("ethertype_filter",
9577                                        sizeof(*ethertype_filter), 0);
9578                 if (ethertype_filter == NULL) {
9579                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9580                         return -ENOMEM;
9581                 }
9582
9583                 rte_memcpy(ethertype_filter, &check_filter,
9584                            sizeof(check_filter));
9585                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9586                 if (ret < 0)
9587                         rte_free(ethertype_filter);
9588         } else {
9589                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9590         }
9591
9592         return ret;
9593 }
9594
9595 /*
9596  * Handle operations for ethertype filter.
9597  */
9598 static int
9599 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9600                                 enum rte_filter_op filter_op,
9601                                 void *arg)
9602 {
9603         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9604         int ret = 0;
9605
9606         if (filter_op == RTE_ETH_FILTER_NOP)
9607                 return ret;
9608
9609         if (arg == NULL) {
9610                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9611                             filter_op);
9612                 return -EINVAL;
9613         }
9614
9615         switch (filter_op) {
9616         case RTE_ETH_FILTER_ADD:
9617                 ret = i40e_ethertype_filter_set(pf,
9618                         (struct rte_eth_ethertype_filter *)arg,
9619                         TRUE);
9620                 break;
9621         case RTE_ETH_FILTER_DELETE:
9622                 ret = i40e_ethertype_filter_set(pf,
9623                         (struct rte_eth_ethertype_filter *)arg,
9624                         FALSE);
9625                 break;
9626         default:
9627                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9628                 ret = -ENOSYS;
9629                 break;
9630         }
9631         return ret;
9632 }
9633
9634 static int
9635 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9636                      enum rte_filter_type filter_type,
9637                      enum rte_filter_op filter_op,
9638                      void *arg)
9639 {
9640         int ret = 0;
9641
9642         if (dev == NULL)
9643                 return -EINVAL;
9644
9645         switch (filter_type) {
9646         case RTE_ETH_FILTER_NONE:
9647                 /* For global configuration */
9648                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9649                 break;
9650         case RTE_ETH_FILTER_HASH:
9651                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9652                 break;
9653         case RTE_ETH_FILTER_MACVLAN:
9654                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9655                 break;
9656         case RTE_ETH_FILTER_ETHERTYPE:
9657                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9658                 break;
9659         case RTE_ETH_FILTER_TUNNEL:
9660                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9661                 break;
9662         case RTE_ETH_FILTER_FDIR:
9663                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9664                 break;
9665         case RTE_ETH_FILTER_GENERIC:
9666                 if (filter_op != RTE_ETH_FILTER_GET)
9667                         return -EINVAL;
9668                 *(const void **)arg = &i40e_flow_ops;
9669                 break;
9670         default:
9671                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9672                                                         filter_type);
9673                 ret = -EINVAL;
9674                 break;
9675         }
9676
9677         return ret;
9678 }
9679
9680 /*
9681  * Check and enable Extended Tag.
9682  * Enabling Extended Tag is important for 40G performance.
9683  */
9684 static void
9685 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9686 {
9687         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9688         uint32_t buf = 0;
9689         int ret;
9690
9691         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9692                                       PCI_DEV_CAP_REG);
9693         if (ret < 0) {
9694                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9695                             PCI_DEV_CAP_REG);
9696                 return;
9697         }
9698         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9699                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9700                 return;
9701         }
9702
9703         buf = 0;
9704         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9705                                       PCI_DEV_CTRL_REG);
9706         if (ret < 0) {
9707                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9708                             PCI_DEV_CTRL_REG);
9709                 return;
9710         }
9711         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9712                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9713                 return;
9714         }
9715         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9716         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9717                                        PCI_DEV_CTRL_REG);
9718         if (ret < 0) {
9719                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9720                             PCI_DEV_CTRL_REG);
9721                 return;
9722         }
9723 }
9724
9725 /*
9726  * As some registers wouldn't be reset unless a global hardware reset,
9727  * hardware initialization is needed to put those registers into an
9728  * expected initial state.
9729  */
9730 static void
9731 i40e_hw_init(struct rte_eth_dev *dev)
9732 {
9733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9734
9735         i40e_enable_extended_tag(dev);
9736
9737         /* clear the PF Queue Filter control register */
9738         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9739
9740         /* Disable symmetric hash per port */
9741         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9742 }
9743
9744 /*
9745  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9746  * however this function will return only one highest pctype index,
9747  * which is not quite correct. This is known problem of i40e driver
9748  * and needs to be fixed later.
9749  */
9750 enum i40e_filter_pctype
9751 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9752 {
9753         int i;
9754         uint64_t pctype_mask;
9755
9756         if (flow_type < I40E_FLOW_TYPE_MAX) {
9757                 pctype_mask = adapter->pctypes_tbl[flow_type];
9758                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9759                         if (pctype_mask & (1ULL << i))
9760                                 return (enum i40e_filter_pctype)i;
9761                 }
9762         }
9763         return I40E_FILTER_PCTYPE_INVALID;
9764 }
9765
9766 uint16_t
9767 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9768                         enum i40e_filter_pctype pctype)
9769 {
9770         uint16_t flowtype;
9771         uint64_t pctype_mask = 1ULL << pctype;
9772
9773         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9774              flowtype++) {
9775                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9776                         return flowtype;
9777         }
9778
9779         return RTE_ETH_FLOW_UNKNOWN;
9780 }
9781
9782 /*
9783  * On X710, performance number is far from the expectation on recent firmware
9784  * versions; on XL710, performance number is also far from the expectation on
9785  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9786  * mode is enabled and port MAC address is equal to the packet destination MAC
9787  * address. The fix for this issue may not be integrated in the following
9788  * firmware version. So the workaround in software driver is needed. It needs
9789  * to modify the initial values of 3 internal only registers for both X710 and
9790  * XL710. Note that the values for X710 or XL710 could be different, and the
9791  * workaround can be removed when it is fixed in firmware in the future.
9792  */
9793
9794 /* For both X710 and XL710 */
9795 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9796 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9797 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9798
9799 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9800 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9801
9802 /* For X722 */
9803 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9804 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9805
9806 /* For X710 */
9807 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9808 /* For XL710 */
9809 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9810 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9811
9812 static int
9813 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9814 {
9815         enum i40e_status_code status;
9816         struct i40e_aq_get_phy_abilities_resp phy_ab;
9817         int ret = -ENOTSUP;
9818         int retries = 0;
9819
9820         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9821                                               NULL);
9822
9823         while (status) {
9824                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9825                         status);
9826                 retries++;
9827                 rte_delay_us(100000);
9828                 if  (retries < 5)
9829                         status = i40e_aq_get_phy_capabilities(hw, false,
9830                                         true, &phy_ab, NULL);
9831                 else
9832                         return ret;
9833         }
9834         return 0;
9835 }
9836
9837 static void
9838 i40e_configure_registers(struct i40e_hw *hw)
9839 {
9840         static struct {
9841                 uint32_t addr;
9842                 uint64_t val;
9843         } reg_table[] = {
9844                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9845                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9846                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9847         };
9848         uint64_t reg;
9849         uint32_t i;
9850         int ret;
9851
9852         for (i = 0; i < RTE_DIM(reg_table); i++) {
9853                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9854                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9855                                 reg_table[i].val =
9856                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9857                         else /* For X710/XL710/XXV710 */
9858                                 if (hw->aq.fw_maj_ver < 6)
9859                                         reg_table[i].val =
9860                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9861                                 else
9862                                         reg_table[i].val =
9863                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9864                 }
9865
9866                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9867                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9868                                 reg_table[i].val =
9869                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9870                         else /* For X710/XL710/XXV710 */
9871                                 reg_table[i].val =
9872                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9873                 }
9874
9875                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9876                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9877                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9878                                 reg_table[i].val =
9879                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9880                         else /* For X710 */
9881                                 reg_table[i].val =
9882                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9883                 }
9884
9885                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9886                                                         &reg, NULL);
9887                 if (ret < 0) {
9888                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9889                                                         reg_table[i].addr);
9890                         break;
9891                 }
9892                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9893                                                 reg_table[i].addr, reg);
9894                 if (reg == reg_table[i].val)
9895                         continue;
9896
9897                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9898                                                 reg_table[i].val, NULL);
9899                 if (ret < 0) {
9900                         PMD_DRV_LOG(ERR,
9901                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9902                                 reg_table[i].val, reg_table[i].addr);
9903                         break;
9904                 }
9905                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9906                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9907         }
9908 }
9909
9910 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9911 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9912 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9913 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9914 static int
9915 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9916 {
9917         uint32_t reg;
9918         int ret;
9919
9920         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9921                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9922                 return -EINVAL;
9923         }
9924
9925         /* Configure for double VLAN RX stripping */
9926         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9927         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9928                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9929                 ret = i40e_aq_debug_write_register(hw,
9930                                                    I40E_VSI_TSR(vsi->vsi_id),
9931                                                    reg, NULL);
9932                 if (ret < 0) {
9933                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9934                                     vsi->vsi_id);
9935                         return I40E_ERR_CONFIG;
9936                 }
9937         }
9938
9939         /* Configure for double VLAN TX insertion */
9940         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9941         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9942                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9943                 ret = i40e_aq_debug_write_register(hw,
9944                                                    I40E_VSI_L2TAGSTXVALID(
9945                                                    vsi->vsi_id), reg, NULL);
9946                 if (ret < 0) {
9947                         PMD_DRV_LOG(ERR,
9948                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9949                                 vsi->vsi_id);
9950                         return I40E_ERR_CONFIG;
9951                 }
9952         }
9953
9954         return 0;
9955 }
9956
9957 /**
9958  * i40e_aq_add_mirror_rule
9959  * @hw: pointer to the hardware structure
9960  * @seid: VEB seid to add mirror rule to
9961  * @dst_id: destination vsi seid
9962  * @entries: Buffer which contains the entities to be mirrored
9963  * @count: number of entities contained in the buffer
9964  * @rule_id:the rule_id of the rule to be added
9965  *
9966  * Add a mirror rule for a given veb.
9967  *
9968  **/
9969 static enum i40e_status_code
9970 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9971                         uint16_t seid, uint16_t dst_id,
9972                         uint16_t rule_type, uint16_t *entries,
9973                         uint16_t count, uint16_t *rule_id)
9974 {
9975         struct i40e_aq_desc desc;
9976         struct i40e_aqc_add_delete_mirror_rule cmd;
9977         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9978                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9979                 &desc.params.raw;
9980         uint16_t buff_len;
9981         enum i40e_status_code status;
9982
9983         i40e_fill_default_direct_cmd_desc(&desc,
9984                                           i40e_aqc_opc_add_mirror_rule);
9985         memset(&cmd, 0, sizeof(cmd));
9986
9987         buff_len = sizeof(uint16_t) * count;
9988         desc.datalen = rte_cpu_to_le_16(buff_len);
9989         if (buff_len > 0)
9990                 desc.flags |= rte_cpu_to_le_16(
9991                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9992         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9993                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9994         cmd.num_entries = rte_cpu_to_le_16(count);
9995         cmd.seid = rte_cpu_to_le_16(seid);
9996         cmd.destination = rte_cpu_to_le_16(dst_id);
9997
9998         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9999         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10000         PMD_DRV_LOG(INFO,
10001                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10002                 hw->aq.asq_last_status, resp->rule_id,
10003                 resp->mirror_rules_used, resp->mirror_rules_free);
10004         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10005
10006         return status;
10007 }
10008
10009 /**
10010  * i40e_aq_del_mirror_rule
10011  * @hw: pointer to the hardware structure
10012  * @seid: VEB seid to add mirror rule to
10013  * @entries: Buffer which contains the entities to be mirrored
10014  * @count: number of entities contained in the buffer
10015  * @rule_id:the rule_id of the rule to be delete
10016  *
10017  * Delete a mirror rule for a given veb.
10018  *
10019  **/
10020 static enum i40e_status_code
10021 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10022                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10023                 uint16_t count, uint16_t rule_id)
10024 {
10025         struct i40e_aq_desc desc;
10026         struct i40e_aqc_add_delete_mirror_rule cmd;
10027         uint16_t buff_len = 0;
10028         enum i40e_status_code status;
10029         void *buff = NULL;
10030
10031         i40e_fill_default_direct_cmd_desc(&desc,
10032                                           i40e_aqc_opc_delete_mirror_rule);
10033         memset(&cmd, 0, sizeof(cmd));
10034         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10035                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10036                                                           I40E_AQ_FLAG_RD));
10037                 cmd.num_entries = count;
10038                 buff_len = sizeof(uint16_t) * count;
10039                 desc.datalen = rte_cpu_to_le_16(buff_len);
10040                 buff = (void *)entries;
10041         } else
10042                 /* rule id is filled in destination field for deleting mirror rule */
10043                 cmd.destination = rte_cpu_to_le_16(rule_id);
10044
10045         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10046                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10047         cmd.seid = rte_cpu_to_le_16(seid);
10048
10049         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10050         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10051
10052         return status;
10053 }
10054
10055 /**
10056  * i40e_mirror_rule_set
10057  * @dev: pointer to the hardware structure
10058  * @mirror_conf: mirror rule info
10059  * @sw_id: mirror rule's sw_id
10060  * @on: enable/disable
10061  *
10062  * set a mirror rule.
10063  *
10064  **/
10065 static int
10066 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10067                         struct rte_eth_mirror_conf *mirror_conf,
10068                         uint8_t sw_id, uint8_t on)
10069 {
10070         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10071         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10072         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10073         struct i40e_mirror_rule *parent = NULL;
10074         uint16_t seid, dst_seid, rule_id;
10075         uint16_t i, j = 0;
10076         int ret;
10077
10078         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10079
10080         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10081                 PMD_DRV_LOG(ERR,
10082                         "mirror rule can not be configured without veb or vfs.");
10083                 return -ENOSYS;
10084         }
10085         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10086                 PMD_DRV_LOG(ERR, "mirror table is full.");
10087                 return -ENOSPC;
10088         }
10089         if (mirror_conf->dst_pool > pf->vf_num) {
10090                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10091                                  mirror_conf->dst_pool);
10092                 return -EINVAL;
10093         }
10094
10095         seid = pf->main_vsi->veb->seid;
10096
10097         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10098                 if (sw_id <= it->index) {
10099                         mirr_rule = it;
10100                         break;
10101                 }
10102                 parent = it;
10103         }
10104         if (mirr_rule && sw_id == mirr_rule->index) {
10105                 if (on) {
10106                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10107                         return -EEXIST;
10108                 } else {
10109                         ret = i40e_aq_del_mirror_rule(hw, seid,
10110                                         mirr_rule->rule_type,
10111                                         mirr_rule->entries,
10112                                         mirr_rule->num_entries, mirr_rule->id);
10113                         if (ret < 0) {
10114                                 PMD_DRV_LOG(ERR,
10115                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10116                                         ret, hw->aq.asq_last_status);
10117                                 return -ENOSYS;
10118                         }
10119                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10120                         rte_free(mirr_rule);
10121                         pf->nb_mirror_rule--;
10122                         return 0;
10123                 }
10124         } else if (!on) {
10125                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10126                 return -ENOENT;
10127         }
10128
10129         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10130                                 sizeof(struct i40e_mirror_rule) , 0);
10131         if (!mirr_rule) {
10132                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10133                 return I40E_ERR_NO_MEMORY;
10134         }
10135         switch (mirror_conf->rule_type) {
10136         case ETH_MIRROR_VLAN:
10137                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10138                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10139                                 mirr_rule->entries[j] =
10140                                         mirror_conf->vlan.vlan_id[i];
10141                                 j++;
10142                         }
10143                 }
10144                 if (j == 0) {
10145                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10146                         rte_free(mirr_rule);
10147                         return -EINVAL;
10148                 }
10149                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10150                 break;
10151         case ETH_MIRROR_VIRTUAL_POOL_UP:
10152         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10153                 /* check if the specified pool bit is out of range */
10154                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10155                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10156                         rte_free(mirr_rule);
10157                         return -EINVAL;
10158                 }
10159                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10160                         if (mirror_conf->pool_mask & (1ULL << i)) {
10161                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10162                                 j++;
10163                         }
10164                 }
10165                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10166                         /* add pf vsi to entries */
10167                         mirr_rule->entries[j] = pf->main_vsi_seid;
10168                         j++;
10169                 }
10170                 if (j == 0) {
10171                         PMD_DRV_LOG(ERR, "pool is not specified.");
10172                         rte_free(mirr_rule);
10173                         return -EINVAL;
10174                 }
10175                 /* egress and ingress in aq commands means from switch but not port */
10176                 mirr_rule->rule_type =
10177                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10178                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10179                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10180                 break;
10181         case ETH_MIRROR_UPLINK_PORT:
10182                 /* egress and ingress in aq commands means from switch but not port*/
10183                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10184                 break;
10185         case ETH_MIRROR_DOWNLINK_PORT:
10186                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10187                 break;
10188         default:
10189                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10190                         mirror_conf->rule_type);
10191                 rte_free(mirr_rule);
10192                 return -EINVAL;
10193         }
10194
10195         /* If the dst_pool is equal to vf_num, consider it as PF */
10196         if (mirror_conf->dst_pool == pf->vf_num)
10197                 dst_seid = pf->main_vsi_seid;
10198         else
10199                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10200
10201         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10202                                       mirr_rule->rule_type, mirr_rule->entries,
10203                                       j, &rule_id);
10204         if (ret < 0) {
10205                 PMD_DRV_LOG(ERR,
10206                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10207                         ret, hw->aq.asq_last_status);
10208                 rte_free(mirr_rule);
10209                 return -ENOSYS;
10210         }
10211
10212         mirr_rule->index = sw_id;
10213         mirr_rule->num_entries = j;
10214         mirr_rule->id = rule_id;
10215         mirr_rule->dst_vsi_seid = dst_seid;
10216
10217         if (parent)
10218                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10219         else
10220                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10221
10222         pf->nb_mirror_rule++;
10223         return 0;
10224 }
10225
10226 /**
10227  * i40e_mirror_rule_reset
10228  * @dev: pointer to the device
10229  * @sw_id: mirror rule's sw_id
10230  *
10231  * reset a mirror rule.
10232  *
10233  **/
10234 static int
10235 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10236 {
10237         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10239         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10240         uint16_t seid;
10241         int ret;
10242
10243         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10244
10245         seid = pf->main_vsi->veb->seid;
10246
10247         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10248                 if (sw_id == it->index) {
10249                         mirr_rule = it;
10250                         break;
10251                 }
10252         }
10253         if (mirr_rule) {
10254                 ret = i40e_aq_del_mirror_rule(hw, seid,
10255                                 mirr_rule->rule_type,
10256                                 mirr_rule->entries,
10257                                 mirr_rule->num_entries, mirr_rule->id);
10258                 if (ret < 0) {
10259                         PMD_DRV_LOG(ERR,
10260                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10261                                 ret, hw->aq.asq_last_status);
10262                         return -ENOSYS;
10263                 }
10264                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10265                 rte_free(mirr_rule);
10266                 pf->nb_mirror_rule--;
10267         } else {
10268                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10269                 return -ENOENT;
10270         }
10271         return 0;
10272 }
10273
10274 static uint64_t
10275 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10276 {
10277         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10278         uint64_t systim_cycles;
10279
10280         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10281         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10282                         << 32;
10283
10284         return systim_cycles;
10285 }
10286
10287 static uint64_t
10288 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10289 {
10290         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10291         uint64_t rx_tstamp;
10292
10293         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10294         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10295                         << 32;
10296
10297         return rx_tstamp;
10298 }
10299
10300 static uint64_t
10301 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10302 {
10303         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10304         uint64_t tx_tstamp;
10305
10306         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10307         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10308                         << 32;
10309
10310         return tx_tstamp;
10311 }
10312
10313 static void
10314 i40e_start_timecounters(struct rte_eth_dev *dev)
10315 {
10316         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10317         struct i40e_adapter *adapter =
10318                         (struct i40e_adapter *)dev->data->dev_private;
10319         struct rte_eth_link link;
10320         uint32_t tsync_inc_l;
10321         uint32_t tsync_inc_h;
10322
10323         /* Get current link speed. */
10324         memset(&link, 0, sizeof(link));
10325         i40e_dev_link_update(dev, 1);
10326         rte_i40e_dev_atomic_read_link_status(dev, &link);
10327
10328         switch (link.link_speed) {
10329         case ETH_SPEED_NUM_40G:
10330                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10331                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10332                 break;
10333         case ETH_SPEED_NUM_10G:
10334                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10335                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10336                 break;
10337         case ETH_SPEED_NUM_1G:
10338                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10339                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10340                 break;
10341         default:
10342                 tsync_inc_l = 0x0;
10343                 tsync_inc_h = 0x0;
10344         }
10345
10346         /* Set the timesync increment value. */
10347         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10348         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10349
10350         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10351         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10352         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10353
10354         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10355         adapter->systime_tc.cc_shift = 0;
10356         adapter->systime_tc.nsec_mask = 0;
10357
10358         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10359         adapter->rx_tstamp_tc.cc_shift = 0;
10360         adapter->rx_tstamp_tc.nsec_mask = 0;
10361
10362         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10363         adapter->tx_tstamp_tc.cc_shift = 0;
10364         adapter->tx_tstamp_tc.nsec_mask = 0;
10365 }
10366
10367 static int
10368 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10369 {
10370         struct i40e_adapter *adapter =
10371                         (struct i40e_adapter *)dev->data->dev_private;
10372
10373         adapter->systime_tc.nsec += delta;
10374         adapter->rx_tstamp_tc.nsec += delta;
10375         adapter->tx_tstamp_tc.nsec += delta;
10376
10377         return 0;
10378 }
10379
10380 static int
10381 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10382 {
10383         uint64_t ns;
10384         struct i40e_adapter *adapter =
10385                         (struct i40e_adapter *)dev->data->dev_private;
10386
10387         ns = rte_timespec_to_ns(ts);
10388
10389         /* Set the timecounters to a new value. */
10390         adapter->systime_tc.nsec = ns;
10391         adapter->rx_tstamp_tc.nsec = ns;
10392         adapter->tx_tstamp_tc.nsec = ns;
10393
10394         return 0;
10395 }
10396
10397 static int
10398 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10399 {
10400         uint64_t ns, systime_cycles;
10401         struct i40e_adapter *adapter =
10402                         (struct i40e_adapter *)dev->data->dev_private;
10403
10404         systime_cycles = i40e_read_systime_cyclecounter(dev);
10405         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10406         *ts = rte_ns_to_timespec(ns);
10407
10408         return 0;
10409 }
10410
10411 static int
10412 i40e_timesync_enable(struct rte_eth_dev *dev)
10413 {
10414         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10415         uint32_t tsync_ctl_l;
10416         uint32_t tsync_ctl_h;
10417
10418         /* Stop the timesync system time. */
10419         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10420         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10421         /* Reset the timesync system time value. */
10422         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10423         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10424
10425         i40e_start_timecounters(dev);
10426
10427         /* Clear timesync registers. */
10428         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10429         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10430         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10431         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10432         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10433         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10434
10435         /* Enable timestamping of PTP packets. */
10436         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10437         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10438
10439         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10440         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10441         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10442
10443         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10444         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10445
10446         return 0;
10447 }
10448
10449 static int
10450 i40e_timesync_disable(struct rte_eth_dev *dev)
10451 {
10452         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10453         uint32_t tsync_ctl_l;
10454         uint32_t tsync_ctl_h;
10455
10456         /* Disable timestamping of transmitted PTP packets. */
10457         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10458         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10459
10460         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10461         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10462
10463         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10464         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10465
10466         /* Reset the timesync increment value. */
10467         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10468         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10469
10470         return 0;
10471 }
10472
10473 static int
10474 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10475                                 struct timespec *timestamp, uint32_t flags)
10476 {
10477         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10478         struct i40e_adapter *adapter =
10479                 (struct i40e_adapter *)dev->data->dev_private;
10480
10481         uint32_t sync_status;
10482         uint32_t index = flags & 0x03;
10483         uint64_t rx_tstamp_cycles;
10484         uint64_t ns;
10485
10486         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10487         if ((sync_status & (1 << index)) == 0)
10488                 return -EINVAL;
10489
10490         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10491         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10492         *timestamp = rte_ns_to_timespec(ns);
10493
10494         return 0;
10495 }
10496
10497 static int
10498 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10499                                 struct timespec *timestamp)
10500 {
10501         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10502         struct i40e_adapter *adapter =
10503                 (struct i40e_adapter *)dev->data->dev_private;
10504
10505         uint32_t sync_status;
10506         uint64_t tx_tstamp_cycles;
10507         uint64_t ns;
10508
10509         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10510         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10511                 return -EINVAL;
10512
10513         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10514         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10515         *timestamp = rte_ns_to_timespec(ns);
10516
10517         return 0;
10518 }
10519
10520 /*
10521  * i40e_parse_dcb_configure - parse dcb configure from user
10522  * @dev: the device being configured
10523  * @dcb_cfg: pointer of the result of parse
10524  * @*tc_map: bit map of enabled traffic classes
10525  *
10526  * Returns 0 on success, negative value on failure
10527  */
10528 static int
10529 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10530                          struct i40e_dcbx_config *dcb_cfg,
10531                          uint8_t *tc_map)
10532 {
10533         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10534         uint8_t i, tc_bw, bw_lf;
10535
10536         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10537
10538         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10539         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10540                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10541                 return -EINVAL;
10542         }
10543
10544         /* assume each tc has the same bw */
10545         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10546         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10547                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10548         /* to ensure the sum of tcbw is equal to 100 */
10549         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10550         for (i = 0; i < bw_lf; i++)
10551                 dcb_cfg->etscfg.tcbwtable[i]++;
10552
10553         /* assume each tc has the same Transmission Selection Algorithm */
10554         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10555                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10556
10557         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10558                 dcb_cfg->etscfg.prioritytable[i] =
10559                                 dcb_rx_conf->dcb_tc[i];
10560
10561         /* FW needs one App to configure HW */
10562         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10563         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10564         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10565         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10566
10567         if (dcb_rx_conf->nb_tcs == 0)
10568                 *tc_map = 1; /* tc0 only */
10569         else
10570                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10571
10572         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10573                 dcb_cfg->pfc.willing = 0;
10574                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10575                 dcb_cfg->pfc.pfcenable = *tc_map;
10576         }
10577         return 0;
10578 }
10579
10580
10581 static enum i40e_status_code
10582 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10583                               struct i40e_aqc_vsi_properties_data *info,
10584                               uint8_t enabled_tcmap)
10585 {
10586         enum i40e_status_code ret;
10587         int i, total_tc = 0;
10588         uint16_t qpnum_per_tc, bsf, qp_idx;
10589         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10590         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10591         uint16_t used_queues;
10592
10593         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10594         if (ret != I40E_SUCCESS)
10595                 return ret;
10596
10597         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10598                 if (enabled_tcmap & (1 << i))
10599                         total_tc++;
10600         }
10601         if (total_tc == 0)
10602                 total_tc = 1;
10603         vsi->enabled_tc = enabled_tcmap;
10604
10605         /* different VSI has different queues assigned */
10606         if (vsi->type == I40E_VSI_MAIN)
10607                 used_queues = dev_data->nb_rx_queues -
10608                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10609         else if (vsi->type == I40E_VSI_VMDQ2)
10610                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10611         else {
10612                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10613                 return I40E_ERR_NO_AVAILABLE_VSI;
10614         }
10615
10616         qpnum_per_tc = used_queues / total_tc;
10617         /* Number of queues per enabled TC */
10618         if (qpnum_per_tc == 0) {
10619                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10620                 return I40E_ERR_INVALID_QP_ID;
10621         }
10622         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10623                                 I40E_MAX_Q_PER_TC);
10624         bsf = rte_bsf32(qpnum_per_tc);
10625
10626         /**
10627          * Configure TC and queue mapping parameters, for enabled TC,
10628          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10629          * default queue will serve it.
10630          */
10631         qp_idx = 0;
10632         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10633                 if (vsi->enabled_tc & (1 << i)) {
10634                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10635                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10636                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10637                         qp_idx += qpnum_per_tc;
10638                 } else
10639                         info->tc_mapping[i] = 0;
10640         }
10641
10642         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10643         if (vsi->type == I40E_VSI_SRIOV) {
10644                 info->mapping_flags |=
10645                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10646                 for (i = 0; i < vsi->nb_qps; i++)
10647                         info->queue_mapping[i] =
10648                                 rte_cpu_to_le_16(vsi->base_queue + i);
10649         } else {
10650                 info->mapping_flags |=
10651                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10652                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10653         }
10654         info->valid_sections |=
10655                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10656
10657         return I40E_SUCCESS;
10658 }
10659
10660 /*
10661  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10662  * @veb: VEB to be configured
10663  * @tc_map: enabled TC bitmap
10664  *
10665  * Returns 0 on success, negative value on failure
10666  */
10667 static enum i40e_status_code
10668 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10669 {
10670         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10671         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10672         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10673         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10674         enum i40e_status_code ret = I40E_SUCCESS;
10675         int i;
10676         uint32_t bw_max;
10677
10678         /* Check if enabled_tc is same as existing or new TCs */
10679         if (veb->enabled_tc == tc_map)
10680                 return ret;
10681
10682         /* configure tc bandwidth */
10683         memset(&veb_bw, 0, sizeof(veb_bw));
10684         veb_bw.tc_valid_bits = tc_map;
10685         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10686         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10687                 if (tc_map & BIT_ULL(i))
10688                         veb_bw.tc_bw_share_credits[i] = 1;
10689         }
10690         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10691                                                    &veb_bw, NULL);
10692         if (ret) {
10693                 PMD_INIT_LOG(ERR,
10694                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10695                         hw->aq.asq_last_status);
10696                 return ret;
10697         }
10698
10699         memset(&ets_query, 0, sizeof(ets_query));
10700         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10701                                                    &ets_query, NULL);
10702         if (ret != I40E_SUCCESS) {
10703                 PMD_DRV_LOG(ERR,
10704                         "Failed to get switch_comp ETS configuration %u",
10705                         hw->aq.asq_last_status);
10706                 return ret;
10707         }
10708         memset(&bw_query, 0, sizeof(bw_query));
10709         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10710                                                   &bw_query, NULL);
10711         if (ret != I40E_SUCCESS) {
10712                 PMD_DRV_LOG(ERR,
10713                         "Failed to get switch_comp bandwidth configuration %u",
10714                         hw->aq.asq_last_status);
10715                 return ret;
10716         }
10717
10718         /* store and print out BW info */
10719         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10720         veb->bw_info.bw_max = ets_query.tc_bw_max;
10721         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10722         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10723         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10724                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10725                      I40E_16_BIT_WIDTH);
10726         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10727                 veb->bw_info.bw_ets_share_credits[i] =
10728                                 bw_query.tc_bw_share_credits[i];
10729                 veb->bw_info.bw_ets_credits[i] =
10730                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10731                 /* 4 bits per TC, 4th bit is reserved */
10732                 veb->bw_info.bw_ets_max[i] =
10733                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10734                                   RTE_LEN2MASK(3, uint8_t));
10735                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10736                             veb->bw_info.bw_ets_share_credits[i]);
10737                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10738                             veb->bw_info.bw_ets_credits[i]);
10739                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10740                             veb->bw_info.bw_ets_max[i]);
10741         }
10742
10743         veb->enabled_tc = tc_map;
10744
10745         return ret;
10746 }
10747
10748
10749 /*
10750  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10751  * @vsi: VSI to be configured
10752  * @tc_map: enabled TC bitmap
10753  *
10754  * Returns 0 on success, negative value on failure
10755  */
10756 static enum i40e_status_code
10757 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10758 {
10759         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10760         struct i40e_vsi_context ctxt;
10761         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10762         enum i40e_status_code ret = I40E_SUCCESS;
10763         int i;
10764
10765         /* Check if enabled_tc is same as existing or new TCs */
10766         if (vsi->enabled_tc == tc_map)
10767                 return ret;
10768
10769         /* configure tc bandwidth */
10770         memset(&bw_data, 0, sizeof(bw_data));
10771         bw_data.tc_valid_bits = tc_map;
10772         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10773         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10774                 if (tc_map & BIT_ULL(i))
10775                         bw_data.tc_bw_credits[i] = 1;
10776         }
10777         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10778         if (ret) {
10779                 PMD_INIT_LOG(ERR,
10780                         "AQ command Config VSI BW allocation per TC failed = %d",
10781                         hw->aq.asq_last_status);
10782                 goto out;
10783         }
10784         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10785                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10786
10787         /* Update Queue Pairs Mapping for currently enabled UPs */
10788         ctxt.seid = vsi->seid;
10789         ctxt.pf_num = hw->pf_id;
10790         ctxt.vf_num = 0;
10791         ctxt.uplink_seid = vsi->uplink_seid;
10792         ctxt.info = vsi->info;
10793         i40e_get_cap(hw);
10794         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10795         if (ret)
10796                 goto out;
10797
10798         /* Update the VSI after updating the VSI queue-mapping information */
10799         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10800         if (ret) {
10801                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10802                         hw->aq.asq_last_status);
10803                 goto out;
10804         }
10805         /* update the local VSI info with updated queue map */
10806         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10807                                         sizeof(vsi->info.tc_mapping));
10808         rte_memcpy(&vsi->info.queue_mapping,
10809                         &ctxt.info.queue_mapping,
10810                 sizeof(vsi->info.queue_mapping));
10811         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10812         vsi->info.valid_sections = 0;
10813
10814         /* query and update current VSI BW information */
10815         ret = i40e_vsi_get_bw_config(vsi);
10816         if (ret) {
10817                 PMD_INIT_LOG(ERR,
10818                          "Failed updating vsi bw info, err %s aq_err %s",
10819                          i40e_stat_str(hw, ret),
10820                          i40e_aq_str(hw, hw->aq.asq_last_status));
10821                 goto out;
10822         }
10823
10824         vsi->enabled_tc = tc_map;
10825
10826 out:
10827         return ret;
10828 }
10829
10830 /*
10831  * i40e_dcb_hw_configure - program the dcb setting to hw
10832  * @pf: pf the configuration is taken on
10833  * @new_cfg: new configuration
10834  * @tc_map: enabled TC bitmap
10835  *
10836  * Returns 0 on success, negative value on failure
10837  */
10838 static enum i40e_status_code
10839 i40e_dcb_hw_configure(struct i40e_pf *pf,
10840                       struct i40e_dcbx_config *new_cfg,
10841                       uint8_t tc_map)
10842 {
10843         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10844         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10845         struct i40e_vsi *main_vsi = pf->main_vsi;
10846         struct i40e_vsi_list *vsi_list;
10847         enum i40e_status_code ret;
10848         int i;
10849         uint32_t val;
10850
10851         /* Use the FW API if FW > v4.4*/
10852         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10853               (hw->aq.fw_maj_ver >= 5))) {
10854                 PMD_INIT_LOG(ERR,
10855                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10856                 return I40E_ERR_FIRMWARE_API_VERSION;
10857         }
10858
10859         /* Check if need reconfiguration */
10860         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10861                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10862                 return I40E_SUCCESS;
10863         }
10864
10865         /* Copy the new config to the current config */
10866         *old_cfg = *new_cfg;
10867         old_cfg->etsrec = old_cfg->etscfg;
10868         ret = i40e_set_dcb_config(hw);
10869         if (ret) {
10870                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10871                          i40e_stat_str(hw, ret),
10872                          i40e_aq_str(hw, hw->aq.asq_last_status));
10873                 return ret;
10874         }
10875         /* set receive Arbiter to RR mode and ETS scheme by default */
10876         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10877                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10878                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10879                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10880                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10881                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10882                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10883                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10884                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10885                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10886                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10887                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10888                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10889         }
10890         /* get local mib to check whether it is configured correctly */
10891         /* IEEE mode */
10892         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10893         /* Get Local DCB Config */
10894         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10895                                      &hw->local_dcbx_config);
10896
10897         /* if Veb is created, need to update TC of it at first */
10898         if (main_vsi->veb) {
10899                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10900                 if (ret)
10901                         PMD_INIT_LOG(WARNING,
10902                                  "Failed configuring TC for VEB seid=%d",
10903                                  main_vsi->veb->seid);
10904         }
10905         /* Update each VSI */
10906         i40e_vsi_config_tc(main_vsi, tc_map);
10907         if (main_vsi->veb) {
10908                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10909                         /* Beside main VSI and VMDQ VSIs, only enable default
10910                          * TC for other VSIs
10911                          */
10912                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10913                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10914                                                          tc_map);
10915                         else
10916                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10917                                                          I40E_DEFAULT_TCMAP);
10918                         if (ret)
10919                                 PMD_INIT_LOG(WARNING,
10920                                         "Failed configuring TC for VSI seid=%d",
10921                                         vsi_list->vsi->seid);
10922                         /* continue */
10923                 }
10924         }
10925         return I40E_SUCCESS;
10926 }
10927
10928 /*
10929  * i40e_dcb_init_configure - initial dcb config
10930  * @dev: device being configured
10931  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10932  *
10933  * Returns 0 on success, negative value on failure
10934  */
10935 int
10936 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10937 {
10938         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10940         int i, ret = 0;
10941
10942         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10943                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10944                 return -ENOTSUP;
10945         }
10946
10947         /* DCB initialization:
10948          * Update DCB configuration from the Firmware and configure
10949          * LLDP MIB change event.
10950          */
10951         if (sw_dcb == TRUE) {
10952                 ret = i40e_init_dcb(hw);
10953                 /* If lldp agent is stopped, the return value from
10954                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10955                  * adminq status. Otherwise, it should return success.
10956                  */
10957                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10958                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10959                         memset(&hw->local_dcbx_config, 0,
10960                                 sizeof(struct i40e_dcbx_config));
10961                         /* set dcb default configuration */
10962                         hw->local_dcbx_config.etscfg.willing = 0;
10963                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10964                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10965                         hw->local_dcbx_config.etscfg.tsatable[0] =
10966                                                 I40E_IEEE_TSA_ETS;
10967                         /* all UPs mapping to TC0 */
10968                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10969                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10970                         hw->local_dcbx_config.etsrec =
10971                                 hw->local_dcbx_config.etscfg;
10972                         hw->local_dcbx_config.pfc.willing = 0;
10973                         hw->local_dcbx_config.pfc.pfccap =
10974                                                 I40E_MAX_TRAFFIC_CLASS;
10975                         /* FW needs one App to configure HW */
10976                         hw->local_dcbx_config.numapps = 1;
10977                         hw->local_dcbx_config.app[0].selector =
10978                                                 I40E_APP_SEL_ETHTYPE;
10979                         hw->local_dcbx_config.app[0].priority = 3;
10980                         hw->local_dcbx_config.app[0].protocolid =
10981                                                 I40E_APP_PROTOID_FCOE;
10982                         ret = i40e_set_dcb_config(hw);
10983                         if (ret) {
10984                                 PMD_INIT_LOG(ERR,
10985                                         "default dcb config fails. err = %d, aq_err = %d.",
10986                                         ret, hw->aq.asq_last_status);
10987                                 return -ENOSYS;
10988                         }
10989                 } else {
10990                         PMD_INIT_LOG(ERR,
10991                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10992                                 ret, hw->aq.asq_last_status);
10993                         return -ENOTSUP;
10994                 }
10995         } else {
10996                 ret = i40e_aq_start_lldp(hw, NULL);
10997                 if (ret != I40E_SUCCESS)
10998                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10999
11000                 ret = i40e_init_dcb(hw);
11001                 if (!ret) {
11002                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11003                                 PMD_INIT_LOG(ERR,
11004                                         "HW doesn't support DCBX offload.");
11005                                 return -ENOTSUP;
11006                         }
11007                 } else {
11008                         PMD_INIT_LOG(ERR,
11009                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11010                                 ret, hw->aq.asq_last_status);
11011                         return -ENOTSUP;
11012                 }
11013         }
11014         return 0;
11015 }
11016
11017 /*
11018  * i40e_dcb_setup - setup dcb related config
11019  * @dev: device being configured
11020  *
11021  * Returns 0 on success, negative value on failure
11022  */
11023 static int
11024 i40e_dcb_setup(struct rte_eth_dev *dev)
11025 {
11026         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11027         struct i40e_dcbx_config dcb_cfg;
11028         uint8_t tc_map = 0;
11029         int ret = 0;
11030
11031         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11032                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11033                 return -ENOTSUP;
11034         }
11035
11036         if (pf->vf_num != 0)
11037                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11038
11039         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11040         if (ret) {
11041                 PMD_INIT_LOG(ERR, "invalid dcb config");
11042                 return -EINVAL;
11043         }
11044         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11045         if (ret) {
11046                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11047                 return -ENOSYS;
11048         }
11049
11050         return 0;
11051 }
11052
11053 static int
11054 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11055                       struct rte_eth_dcb_info *dcb_info)
11056 {
11057         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11058         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11059         struct i40e_vsi *vsi = pf->main_vsi;
11060         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11061         uint16_t bsf, tc_mapping;
11062         int i, j = 0;
11063
11064         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11065                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11066         else
11067                 dcb_info->nb_tcs = 1;
11068         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11069                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11070         for (i = 0; i < dcb_info->nb_tcs; i++)
11071                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11072
11073         /* get queue mapping if vmdq is disabled */
11074         if (!pf->nb_cfg_vmdq_vsi) {
11075                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11076                         if (!(vsi->enabled_tc & (1 << i)))
11077                                 continue;
11078                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11079                         dcb_info->tc_queue.tc_rxq[j][i].base =
11080                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11081                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11082                         dcb_info->tc_queue.tc_txq[j][i].base =
11083                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11084                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11085                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11086                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11087                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11088                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11089                 }
11090                 return 0;
11091         }
11092
11093         /* get queue mapping if vmdq is enabled */
11094         do {
11095                 vsi = pf->vmdq[j].vsi;
11096                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11097                         if (!(vsi->enabled_tc & (1 << i)))
11098                                 continue;
11099                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11100                         dcb_info->tc_queue.tc_rxq[j][i].base =
11101                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11102                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11103                         dcb_info->tc_queue.tc_txq[j][i].base =
11104                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11105                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11106                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11107                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11108                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11109                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11110                 }
11111                 j++;
11112         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11113         return 0;
11114 }
11115
11116 static int
11117 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11118 {
11119         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11120         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11121         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11122         uint16_t msix_intr;
11123
11124         msix_intr = intr_handle->intr_vec[queue_id];
11125         if (msix_intr == I40E_MISC_VEC_ID)
11126                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11127                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11128                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11129                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11130         else
11131                 I40E_WRITE_REG(hw,
11132                                I40E_PFINT_DYN_CTLN(msix_intr -
11133                                                    I40E_RX_VEC_START),
11134                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11135                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11136                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11137
11138         I40E_WRITE_FLUSH(hw);
11139         rte_intr_enable(&pci_dev->intr_handle);
11140
11141         return 0;
11142 }
11143
11144 static int
11145 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11146 {
11147         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11148         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11149         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11150         uint16_t msix_intr;
11151
11152         msix_intr = intr_handle->intr_vec[queue_id];
11153         if (msix_intr == I40E_MISC_VEC_ID)
11154                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11155                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11156         else
11157                 I40E_WRITE_REG(hw,
11158                                I40E_PFINT_DYN_CTLN(msix_intr -
11159                                                    I40E_RX_VEC_START),
11160                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11161         I40E_WRITE_FLUSH(hw);
11162
11163         return 0;
11164 }
11165
11166 static int i40e_get_regs(struct rte_eth_dev *dev,
11167                          struct rte_dev_reg_info *regs)
11168 {
11169         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11170         uint32_t *ptr_data = regs->data;
11171         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11172         const struct i40e_reg_info *reg_info;
11173
11174         if (ptr_data == NULL) {
11175                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11176                 regs->width = sizeof(uint32_t);
11177                 return 0;
11178         }
11179
11180         /* The first few registers have to be read using AQ operations */
11181         reg_idx = 0;
11182         while (i40e_regs_adminq[reg_idx].name) {
11183                 reg_info = &i40e_regs_adminq[reg_idx++];
11184                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11185                         for (arr_idx2 = 0;
11186                                         arr_idx2 <= reg_info->count2;
11187                                         arr_idx2++) {
11188                                 reg_offset = arr_idx * reg_info->stride1 +
11189                                         arr_idx2 * reg_info->stride2;
11190                                 reg_offset += reg_info->base_addr;
11191                                 ptr_data[reg_offset >> 2] =
11192                                         i40e_read_rx_ctl(hw, reg_offset);
11193                         }
11194         }
11195
11196         /* The remaining registers can be read using primitives */
11197         reg_idx = 0;
11198         while (i40e_regs_others[reg_idx].name) {
11199                 reg_info = &i40e_regs_others[reg_idx++];
11200                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11201                         for (arr_idx2 = 0;
11202                                         arr_idx2 <= reg_info->count2;
11203                                         arr_idx2++) {
11204                                 reg_offset = arr_idx * reg_info->stride1 +
11205                                         arr_idx2 * reg_info->stride2;
11206                                 reg_offset += reg_info->base_addr;
11207                                 ptr_data[reg_offset >> 2] =
11208                                         I40E_READ_REG(hw, reg_offset);
11209                         }
11210         }
11211
11212         return 0;
11213 }
11214
11215 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11216 {
11217         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11218
11219         /* Convert word count to byte count */
11220         return hw->nvm.sr_size << 1;
11221 }
11222
11223 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11224                            struct rte_dev_eeprom_info *eeprom)
11225 {
11226         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11227         uint16_t *data = eeprom->data;
11228         uint16_t offset, length, cnt_words;
11229         int ret_code;
11230
11231         offset = eeprom->offset >> 1;
11232         length = eeprom->length >> 1;
11233         cnt_words = length;
11234
11235         if (offset > hw->nvm.sr_size ||
11236                 offset + length > hw->nvm.sr_size) {
11237                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11238                 return -EINVAL;
11239         }
11240
11241         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11242
11243         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11244         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11245                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11246                 return -EIO;
11247         }
11248
11249         return 0;
11250 }
11251
11252 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11253                                       struct ether_addr *mac_addr)
11254 {
11255         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11256         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11257         struct i40e_vsi *vsi = pf->main_vsi;
11258         struct i40e_mac_filter_info mac_filter;
11259         struct i40e_mac_filter *f;
11260         int ret;
11261
11262         if (!is_valid_assigned_ether_addr(mac_addr)) {
11263                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11264                 return;
11265         }
11266
11267         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11268                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11269                         break;
11270         }
11271
11272         if (f == NULL) {
11273                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11274                 return;
11275         }
11276
11277         mac_filter = f->mac_info;
11278         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11279         if (ret != I40E_SUCCESS) {
11280                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11281                 return;
11282         }
11283         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11284         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11285         if (ret != I40E_SUCCESS) {
11286                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11287                 return;
11288         }
11289         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11290
11291         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11292                                   mac_addr->addr_bytes, NULL);
11293 }
11294
11295 static int
11296 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11297 {
11298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11299         struct rte_eth_dev_data *dev_data = pf->dev_data;
11300         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11301         int ret = 0;
11302
11303         /* check if mtu is within the allowed range */
11304         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11305                 return -EINVAL;
11306
11307         /* mtu setting is forbidden if port is start */
11308         if (dev_data->dev_started) {
11309                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11310                             dev_data->port_id);
11311                 return -EBUSY;
11312         }
11313
11314         if (frame_size > ETHER_MAX_LEN)
11315                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11316         else
11317                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11318
11319         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11320
11321         return ret;
11322 }
11323
11324 /* Restore ethertype filter */
11325 static void
11326 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11327 {
11328         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11329         struct i40e_ethertype_filter_list
11330                 *ethertype_list = &pf->ethertype.ethertype_list;
11331         struct i40e_ethertype_filter *f;
11332         struct i40e_control_filter_stats stats;
11333         uint16_t flags;
11334
11335         TAILQ_FOREACH(f, ethertype_list, rules) {
11336                 flags = 0;
11337                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11338                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11339                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11340                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11341                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11342
11343                 memset(&stats, 0, sizeof(stats));
11344                 i40e_aq_add_rem_control_packet_filter(hw,
11345                                             f->input.mac_addr.addr_bytes,
11346                                             f->input.ether_type,
11347                                             flags, pf->main_vsi->seid,
11348                                             f->queue, 1, &stats, NULL);
11349         }
11350         PMD_DRV_LOG(INFO, "Ethertype filter:"
11351                     " mac_etype_used = %u, etype_used = %u,"
11352                     " mac_etype_free = %u, etype_free = %u",
11353                     stats.mac_etype_used, stats.etype_used,
11354                     stats.mac_etype_free, stats.etype_free);
11355 }
11356
11357 /* Restore tunnel filter */
11358 static void
11359 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11360 {
11361         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11362         struct i40e_vsi *vsi;
11363         struct i40e_pf_vf *vf;
11364         struct i40e_tunnel_filter_list
11365                 *tunnel_list = &pf->tunnel.tunnel_list;
11366         struct i40e_tunnel_filter *f;
11367         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11368         bool big_buffer = 0;
11369
11370         TAILQ_FOREACH(f, tunnel_list, rules) {
11371                 if (!f->is_to_vf)
11372                         vsi = pf->main_vsi;
11373                 else {
11374                         vf = &pf->vfs[f->vf_id];
11375                         vsi = vf->vsi;
11376                 }
11377                 memset(&cld_filter, 0, sizeof(cld_filter));
11378                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11379                         (struct ether_addr *)&cld_filter.element.outer_mac);
11380                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11381                         (struct ether_addr *)&cld_filter.element.inner_mac);
11382                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11383                 cld_filter.element.flags = f->input.flags;
11384                 cld_filter.element.tenant_id = f->input.tenant_id;
11385                 cld_filter.element.queue_number = f->queue;
11386                 rte_memcpy(cld_filter.general_fields,
11387                            f->input.general_fields,
11388                            sizeof(f->input.general_fields));
11389
11390                 if (((f->input.flags &
11391                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11392                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11393                     ((f->input.flags &
11394                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11395                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11396                     ((f->input.flags &
11397                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11398                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11399                         big_buffer = 1;
11400
11401                 if (big_buffer)
11402                         i40e_aq_add_cloud_filters_big_buffer(hw,
11403                                              vsi->seid, &cld_filter, 1);
11404                 else
11405                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11406                                                   &cld_filter.element, 1);
11407         }
11408 }
11409
11410 /* Restore rss filter */
11411 static inline void
11412 i40e_rss_filter_restore(struct i40e_pf *pf)
11413 {
11414         struct i40e_rte_flow_rss_conf *conf =
11415                                         &pf->rss_info;
11416         if (conf->num)
11417                 i40e_config_rss_filter(pf, conf, TRUE);
11418 }
11419
11420 static void
11421 i40e_filter_restore(struct i40e_pf *pf)
11422 {
11423         i40e_ethertype_filter_restore(pf);
11424         i40e_tunnel_filter_restore(pf);
11425         i40e_fdir_filter_restore(pf);
11426         i40e_rss_filter_restore(pf);
11427 }
11428
11429 static bool
11430 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11431 {
11432         if (strcmp(dev->device->driver->name, drv->driver.name))
11433                 return false;
11434
11435         return true;
11436 }
11437
11438 bool
11439 is_i40e_supported(struct rte_eth_dev *dev)
11440 {
11441         return is_device_supported(dev, &rte_i40e_pmd);
11442 }
11443
11444 struct i40e_customized_pctype*
11445 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11446 {
11447         int i;
11448
11449         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11450                 if (pf->customized_pctype[i].index == index)
11451                         return &pf->customized_pctype[i];
11452         }
11453         return NULL;
11454 }
11455
11456 static int
11457 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11458                               uint32_t pkg_size, uint32_t proto_num,
11459                               struct rte_pmd_i40e_proto_info *proto)
11460 {
11461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11462         uint32_t pctype_num;
11463         struct rte_pmd_i40e_ptype_info *pctype;
11464         uint32_t buff_size;
11465         struct i40e_customized_pctype *new_pctype = NULL;
11466         uint8_t proto_id;
11467         uint8_t pctype_value;
11468         char name[64];
11469         uint32_t i, j, n;
11470         int ret;
11471
11472         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11473                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11474                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11475         if (ret) {
11476                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11477                 return -1;
11478         }
11479         if (!pctype_num) {
11480                 PMD_DRV_LOG(INFO, "No new pctype added");
11481                 return -1;
11482         }
11483
11484         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11485         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11486         if (!pctype) {
11487                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11488                 return -1;
11489         }
11490         /* get information about new pctype list */
11491         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11492                                         (uint8_t *)pctype, buff_size,
11493                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11494         if (ret) {
11495                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11496                 rte_free(pctype);
11497                 return -1;
11498         }
11499
11500         /* Update customized pctype. */
11501         for (i = 0; i < pctype_num; i++) {
11502                 pctype_value = pctype[i].ptype_id;
11503                 memset(name, 0, sizeof(name));
11504                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11505                         proto_id = pctype[i].protocols[j];
11506                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11507                                 continue;
11508                         for (n = 0; n < proto_num; n++) {
11509                                 if (proto[n].proto_id != proto_id)
11510                                         continue;
11511                                 strcat(name, proto[n].name);
11512                                 strcat(name, "_");
11513                                 break;
11514                         }
11515                 }
11516                 name[strlen(name) - 1] = '\0';
11517                 if (!strcmp(name, "GTPC"))
11518                         new_pctype =
11519                                 i40e_find_customized_pctype(pf,
11520                                                       I40E_CUSTOMIZED_GTPC);
11521                 else if (!strcmp(name, "GTPU_IPV4"))
11522                         new_pctype =
11523                                 i40e_find_customized_pctype(pf,
11524                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11525                 else if (!strcmp(name, "GTPU_IPV6"))
11526                         new_pctype =
11527                                 i40e_find_customized_pctype(pf,
11528                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11529                 else if (!strcmp(name, "GTPU"))
11530                         new_pctype =
11531                                 i40e_find_customized_pctype(pf,
11532                                                       I40E_CUSTOMIZED_GTPU);
11533                 if (new_pctype) {
11534                         new_pctype->pctype = pctype_value;
11535                         new_pctype->valid = true;
11536                 }
11537         }
11538
11539         rte_free(pctype);
11540         return 0;
11541 }
11542
11543 static int
11544 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11545                                uint32_t pkg_size, uint32_t proto_num,
11546                                struct rte_pmd_i40e_proto_info *proto)
11547 {
11548         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11549         uint16_t port_id = dev->data->port_id;
11550         uint32_t ptype_num;
11551         struct rte_pmd_i40e_ptype_info *ptype;
11552         uint32_t buff_size;
11553         uint8_t proto_id;
11554         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11555         uint32_t i, j, n;
11556         bool in_tunnel;
11557         int ret;
11558
11559         /* get information about new ptype num */
11560         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11561                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11562                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11563         if (ret) {
11564                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11565                 return ret;
11566         }
11567         if (!ptype_num) {
11568                 PMD_DRV_LOG(INFO, "No new ptype added");
11569                 return -1;
11570         }
11571
11572         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11573         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11574         if (!ptype) {
11575                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11576                 return -1;
11577         }
11578
11579         /* get information about new ptype list */
11580         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11581                                         (uint8_t *)ptype, buff_size,
11582                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11583         if (ret) {
11584                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11585                 rte_free(ptype);
11586                 return ret;
11587         }
11588
11589         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11590         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11591         if (!ptype_mapping) {
11592                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11593                 rte_free(ptype);
11594                 return -1;
11595         }
11596
11597         /* Update ptype mapping table. */
11598         for (i = 0; i < ptype_num; i++) {
11599                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11600                 ptype_mapping[i].sw_ptype = 0;
11601                 in_tunnel = false;
11602                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11603                         proto_id = ptype[i].protocols[j];
11604                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11605                                 continue;
11606                         for (n = 0; n < proto_num; n++) {
11607                                 if (proto[n].proto_id != proto_id)
11608                                         continue;
11609                                 memset(name, 0, sizeof(name));
11610                                 strcpy(name, proto[n].name);
11611                                 if (!strncasecmp(name, "PPPOE", 5))
11612                                         ptype_mapping[i].sw_ptype |=
11613                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11614                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11615                                          !in_tunnel) {
11616                                         ptype_mapping[i].sw_ptype |=
11617                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11618                                         ptype_mapping[i].sw_ptype |=
11619                                                 RTE_PTYPE_L4_FRAG;
11620                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11621                                            in_tunnel) {
11622                                         ptype_mapping[i].sw_ptype |=
11623                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11624                                         ptype_mapping[i].sw_ptype |=
11625                                                 RTE_PTYPE_INNER_L4_FRAG;
11626                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11627                                         ptype_mapping[i].sw_ptype |=
11628                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11629                                         in_tunnel = true;
11630                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11631                                            !in_tunnel)
11632                                         ptype_mapping[i].sw_ptype |=
11633                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11634                                 else if (!strncasecmp(name, "IPV4", 4) &&
11635                                          in_tunnel)
11636                                         ptype_mapping[i].sw_ptype |=
11637                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11638                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11639                                          !in_tunnel) {
11640                                         ptype_mapping[i].sw_ptype |=
11641                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11642                                         ptype_mapping[i].sw_ptype |=
11643                                                 RTE_PTYPE_L4_FRAG;
11644                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11645                                            in_tunnel) {
11646                                         ptype_mapping[i].sw_ptype |=
11647                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11648                                         ptype_mapping[i].sw_ptype |=
11649                                                 RTE_PTYPE_INNER_L4_FRAG;
11650                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11651                                         ptype_mapping[i].sw_ptype |=
11652                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11653                                         in_tunnel = true;
11654                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11655                                            !in_tunnel)
11656                                         ptype_mapping[i].sw_ptype |=
11657                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11658                                 else if (!strncasecmp(name, "IPV6", 4) &&
11659                                          in_tunnel)
11660                                         ptype_mapping[i].sw_ptype |=
11661                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11662                                 else if (!strncasecmp(name, "UDP", 3) &&
11663                                          !in_tunnel)
11664                                         ptype_mapping[i].sw_ptype |=
11665                                                 RTE_PTYPE_L4_UDP;
11666                                 else if (!strncasecmp(name, "UDP", 3) &&
11667                                          in_tunnel)
11668                                         ptype_mapping[i].sw_ptype |=
11669                                                 RTE_PTYPE_INNER_L4_UDP;
11670                                 else if (!strncasecmp(name, "TCP", 3) &&
11671                                          !in_tunnel)
11672                                         ptype_mapping[i].sw_ptype |=
11673                                                 RTE_PTYPE_L4_TCP;
11674                                 else if (!strncasecmp(name, "TCP", 3) &&
11675                                          in_tunnel)
11676                                         ptype_mapping[i].sw_ptype |=
11677                                                 RTE_PTYPE_INNER_L4_TCP;
11678                                 else if (!strncasecmp(name, "SCTP", 4) &&
11679                                          !in_tunnel)
11680                                         ptype_mapping[i].sw_ptype |=
11681                                                 RTE_PTYPE_L4_SCTP;
11682                                 else if (!strncasecmp(name, "SCTP", 4) &&
11683                                          in_tunnel)
11684                                         ptype_mapping[i].sw_ptype |=
11685                                                 RTE_PTYPE_INNER_L4_SCTP;
11686                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11687                                           !strncasecmp(name, "ICMPV6", 6)) &&
11688                                          !in_tunnel)
11689                                         ptype_mapping[i].sw_ptype |=
11690                                                 RTE_PTYPE_L4_ICMP;
11691                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11692                                           !strncasecmp(name, "ICMPV6", 6)) &&
11693                                          in_tunnel)
11694                                         ptype_mapping[i].sw_ptype |=
11695                                                 RTE_PTYPE_INNER_L4_ICMP;
11696                                 else if (!strncasecmp(name, "GTPC", 4)) {
11697                                         ptype_mapping[i].sw_ptype |=
11698                                                 RTE_PTYPE_TUNNEL_GTPC;
11699                                         in_tunnel = true;
11700                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11701                                         ptype_mapping[i].sw_ptype |=
11702                                                 RTE_PTYPE_TUNNEL_GTPU;
11703                                         in_tunnel = true;
11704                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11705                                         ptype_mapping[i].sw_ptype |=
11706                                                 RTE_PTYPE_TUNNEL_GRENAT;
11707                                         in_tunnel = true;
11708                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11709                                         ptype_mapping[i].sw_ptype |=
11710                                                 RTE_PTYPE_TUNNEL_L2TP;
11711                                         in_tunnel = true;
11712                                 }
11713
11714                                 break;
11715                         }
11716                 }
11717         }
11718
11719         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11720                                                 ptype_num, 0);
11721         if (ret)
11722                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11723
11724         rte_free(ptype_mapping);
11725         rte_free(ptype);
11726         return ret;
11727 }
11728
11729 void
11730 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11731                               uint32_t pkg_size)
11732 {
11733         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11734         uint32_t proto_num;
11735         struct rte_pmd_i40e_proto_info *proto;
11736         uint32_t buff_size;
11737         uint32_t i;
11738         int ret;
11739
11740         /* get information about protocol number */
11741         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11742                                        (uint8_t *)&proto_num, sizeof(proto_num),
11743                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11744         if (ret) {
11745                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11746                 return;
11747         }
11748         if (!proto_num) {
11749                 PMD_DRV_LOG(INFO, "No new protocol added");
11750                 return;
11751         }
11752
11753         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11754         proto = rte_zmalloc("new_proto", buff_size, 0);
11755         if (!proto) {
11756                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11757                 return;
11758         }
11759
11760         /* get information about protocol list */
11761         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11762                                         (uint8_t *)proto, buff_size,
11763                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11764         if (ret) {
11765                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11766                 rte_free(proto);
11767                 return;
11768         }
11769
11770         /* Check if GTP is supported. */
11771         for (i = 0; i < proto_num; i++) {
11772                 if (!strncmp(proto[i].name, "GTP", 3)) {
11773                         pf->gtp_support = true;
11774                         break;
11775                 }
11776         }
11777
11778         /* Update customized pctype info */
11779         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11780                                             proto_num, proto);
11781         if (ret)
11782                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11783
11784         /* Update customized ptype info */
11785         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11786                                            proto_num, proto);
11787         if (ret)
11788                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11789
11790         rte_free(proto);
11791 }
11792
11793 /* Create a QinQ cloud filter
11794  *
11795  * The Fortville NIC has limited resources for tunnel filters,
11796  * so we can only reuse existing filters.
11797  *
11798  * In step 1 we define which Field Vector fields can be used for
11799  * filter types.
11800  * As we do not have the inner tag defined as a field,
11801  * we have to define it first, by reusing one of L1 entries.
11802  *
11803  * In step 2 we are replacing one of existing filter types with
11804  * a new one for QinQ.
11805  * As we reusing L1 and replacing L2, some of the default filter
11806  * types will disappear,which depends on L1 and L2 entries we reuse.
11807  *
11808  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11809  *
11810  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11811  *              later when we define the cloud filter.
11812  *      a.      Valid_flags.replace_cloud = 0
11813  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11814  *      c.      New_filter = 0x10
11815  *      d.      TR bit = 0xff (optional, not used here)
11816  *      e.      Buffer – 2 entries:
11817  *              i.      Byte 0 = 8 (outer vlan FV index).
11818  *                      Byte 1 = 0 (rsv)
11819  *                      Byte 2-3 = 0x0fff
11820  *              ii.     Byte 0 = 37 (inner vlan FV index).
11821  *                      Byte 1 =0 (rsv)
11822  *                      Byte 2-3 = 0x0fff
11823  *
11824  * Step 2:
11825  * 2.   Create cloud filter using two L1 filters entries: stag and
11826  *              new filter(outer vlan+ inner vlan)
11827  *      a.      Valid_flags.replace_cloud = 1
11828  *      b.      Old_filter = 1 (instead of outer IP)
11829  *      c.      New_filter = 0x10
11830  *      d.      Buffer – 2 entries:
11831  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11832  *                      Byte 1-3 = 0 (rsv)
11833  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11834  *                      Byte 9-11 = 0 (rsv)
11835  */
11836 static int
11837 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11838 {
11839         int ret = -ENOTSUP;
11840         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11841         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11842         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11843
11844         if (pf->support_multi_driver) {
11845                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
11846                 return ret;
11847         }
11848
11849         /* Init */
11850         memset(&filter_replace, 0,
11851                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11852         memset(&filter_replace_buf, 0,
11853                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11854
11855         /* create L1 filter */
11856         filter_replace.old_filter_type =
11857                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11858         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11859         filter_replace.tr_bit = 0;
11860
11861         /* Prepare the buffer, 2 entries */
11862         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11863         filter_replace_buf.data[0] |=
11864                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11865         /* Field Vector 12b mask */
11866         filter_replace_buf.data[2] = 0xff;
11867         filter_replace_buf.data[3] = 0x0f;
11868         filter_replace_buf.data[4] =
11869                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11870         filter_replace_buf.data[4] |=
11871                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11872         /* Field Vector 12b mask */
11873         filter_replace_buf.data[6] = 0xff;
11874         filter_replace_buf.data[7] = 0x0f;
11875         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11876                         &filter_replace_buf);
11877         if (ret != I40E_SUCCESS)
11878                 return ret;
11879         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11880                     "cloud l1 type is changed from 0x%x to 0x%x",
11881                     filter_replace.old_filter_type,
11882                     filter_replace.new_filter_type);
11883
11884         /* Apply the second L2 cloud filter */
11885         memset(&filter_replace, 0,
11886                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11887         memset(&filter_replace_buf, 0,
11888                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11889
11890         /* create L2 filter, input for L2 filter will be L1 filter  */
11891         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11892         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11893         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11894
11895         /* Prepare the buffer, 2 entries */
11896         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11897         filter_replace_buf.data[0] |=
11898                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11899         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11900         filter_replace_buf.data[4] |=
11901                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11902         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11903                         &filter_replace_buf);
11904         if (!ret) {
11905                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
11906                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11907                             "cloud filter type is changed from 0x%x to 0x%x",
11908                             filter_replace.old_filter_type,
11909                             filter_replace.new_filter_type);
11910         }
11911         return ret;
11912 }
11913
11914 int
11915 i40e_config_rss_filter(struct i40e_pf *pf,
11916                 struct i40e_rte_flow_rss_conf *conf, bool add)
11917 {
11918         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11919         uint32_t i, lut = 0;
11920         uint16_t j, num;
11921         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
11922         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
11923
11924         if (!add) {
11925                 if (memcmp(conf, rss_info,
11926                         sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
11927                         i40e_pf_disable_rss(pf);
11928                         memset(rss_info, 0,
11929                                 sizeof(struct i40e_rte_flow_rss_conf));
11930                         return 0;
11931                 }
11932                 return -EINVAL;
11933         }
11934
11935         if (rss_info->num)
11936                 return -EINVAL;
11937
11938         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
11939          * It's necessary to calculate the actual PF queues that are configured.
11940          */
11941         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
11942                 num = i40e_pf_calc_configured_queues_num(pf);
11943         else
11944                 num = pf->dev_data->nb_rx_queues;
11945
11946         num = RTE_MIN(num, conf->num);
11947         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
11948                         num);
11949
11950         if (num == 0) {
11951                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
11952                 return -ENOTSUP;
11953         }
11954
11955         /* Fill in redirection table */
11956         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
11957                 if (j == num)
11958                         j = 0;
11959                 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
11960                         hw->func_caps.rss_table_entry_width) - 1));
11961                 if ((i & 3) == 3)
11962                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
11963         }
11964
11965         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
11966                 i40e_pf_disable_rss(pf);
11967                 return 0;
11968         }
11969         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
11970                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
11971                 /* Random default keys */
11972                 static uint32_t rss_key_default[] = {0x6b793944,
11973                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
11974                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
11975                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
11976
11977                 rss_conf.rss_key = (uint8_t *)rss_key_default;
11978                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
11979                                                         sizeof(uint32_t);
11980         }
11981
11982         i40e_hw_rss_hash_set(pf, &rss_conf);
11983
11984         rte_memcpy(rss_info,
11985                 conf, sizeof(struct i40e_rte_flow_rss_conf));
11986
11987         return 0;
11988 }
11989
11990 RTE_INIT(i40e_init_log);
11991 static void
11992 i40e_init_log(void)
11993 {
11994         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
11995         if (i40e_logtype_init >= 0)
11996                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11997         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
11998         if (i40e_logtype_driver >= 0)
11999                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12000 }
12001
12002 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12003                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12004                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");