drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "base/i40e_dcb.h"
  60 #include "i40e_ethdev.h"
  61 #include "i40e_rxtx.h"
  62 #include "i40e_pf.h"
  63
  64 /* Maximun number of MAC addresses */
  65 #define I40E_NUM_MACADDR_MAX       64
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 /* Default queue interrupt throttling time in microseconds */
  79 #define I40E_ITR_INDEX_DEFAULT          0
  80 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  81 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA  0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 143 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 144 static int i40e_dev_configure(struct rte_eth_dev *dev);
 145 static int i40e_dev_start(struct rte_eth_dev *dev);
 146 static void i40e_dev_stop(struct rte_eth_dev *dev);
 147 static void i40e_dev_close(struct rte_eth_dev *dev);
 148 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 149 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 150 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 151 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 152 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 153 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 154 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 155                                struct rte_eth_stats *stats);
 156 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 157                                struct rte_eth_xstats *xstats, unsigned n);
 158 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 161                                             uint16_t queue_id,
 162                                             uint8_t stat_idx,
 163                                             uint8_t is_rx);
 164 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 165                               struct rte_eth_dev_info *dev_info);
 166 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 167                                 uint16_t vlan_id,
 168                                 int on);
 169 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 170 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 171 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 172                                       uint16_t queue,
 173                                       int on);
 174 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 175 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 176 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 177 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 178                               struct rte_eth_fc_conf *fc_conf);
 179 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 180                               struct rte_eth_fc_conf *fc_conf);
 181 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 182                                        struct rte_eth_pfc_conf *pfc_conf);
 183 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 184                           struct ether_addr *mac_addr,
 185                           uint32_t index,
 186                           uint32_t pool);
 187 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 188 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 189                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 190                                     uint16_t reta_size);
 191 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 192                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 193                                    uint16_t reta_size);
 194
 195 static int i40e_get_cap(struct i40e_hw *hw);
 196 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 197 static int i40e_pf_setup(struct i40e_pf *pf);
 198 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 199 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 200 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 201 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 202 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 203                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 204 static void i40e_stat_update_48(struct i40e_hw *hw,
 205                                uint32_t hireg,
 206                                uint32_t loreg,
 207                                bool offset_loaded,
 208                                uint64_t *offset,
 209                                uint64_t *stat);
 210 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 211 static void i40e_dev_interrupt_handler(
 212                 __rte_unused struct rte_intr_handle *handle, void *param);
 213 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 214                                 uint32_t base, uint32_t num);
 215 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 216 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 217                         uint32_t base);
 218 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 219                         uint16_t num);
 220 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 221 static int i40e_veb_release(struct i40e_veb *veb);
 222 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 223                                                 struct i40e_vsi *vsi);
 224 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 225 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 226 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 227                                              struct i40e_macvlan_filter *mv_f,
 228                                              int num,
 229                                              struct ether_addr *addr);
 230 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 231                                              struct i40e_macvlan_filter *mv_f,
 232                                              int num,
 233                                              uint16_t vlan);
 234 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 235 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 236                                     struct rte_eth_rss_conf *rss_conf);
 237 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 238                                       struct rte_eth_rss_conf *rss_conf);
 239 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 240                                 struct rte_eth_udp_tunnel *udp_tunnel);
 241 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 242                                 struct rte_eth_udp_tunnel *udp_tunnel);
 243 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 244                         struct rte_eth_ethertype_filter *filter,
 245                         bool add);
 246 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 247                                 enum rte_filter_op filter_op,
 248                                 void *arg);
 249 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 250                                 enum rte_filter_type filter_type,
 251                                 enum rte_filter_op filter_op,
 252                                 void *arg);
 253 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 254                                   struct rte_eth_dcb_info *dcb_info);
 255 static void i40e_configure_registers(struct i40e_hw *hw);
 256 static void i40e_hw_init(struct i40e_hw *hw);
 257 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 258 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 259                         struct rte_eth_mirror_conf *mirror_conf,
 260                         uint8_t sw_id, uint8_t on);
 261 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 262
 263 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 264 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 265 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 266                                            struct timespec *timestamp,
 267                                            uint32_t flags);
 268 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 269                                            struct timespec *timestamp);
 270 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 271
 272
 273 static const struct rte_pci_id pci_id_i40e_map[] = {
 274 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 275 #include "rte_pci_dev_ids.h"
 276 { .vendor_id = 0, /* sentinel */ },
 277 };
 278
 279 static const struct eth_dev_ops i40e_eth_dev_ops = {
 280         .dev_configure                = i40e_dev_configure,
 281         .dev_start                    = i40e_dev_start,
 282         .dev_stop                     = i40e_dev_stop,
 283         .dev_close                    = i40e_dev_close,
 284         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 285         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 286         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 287         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 288         .dev_set_link_up              = i40e_dev_set_link_up,
 289         .dev_set_link_down            = i40e_dev_set_link_down,
 290         .link_update                  = i40e_dev_link_update,
 291         .stats_get                    = i40e_dev_stats_get,
 292         .xstats_get                   = i40e_dev_xstats_get,
 293         .stats_reset                  = i40e_dev_stats_reset,
 294         .xstats_reset                 = i40e_dev_xstats_reset,
 295         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 296         .dev_infos_get                = i40e_dev_info_get,
 297         .vlan_filter_set              = i40e_vlan_filter_set,
 298         .vlan_tpid_set                = i40e_vlan_tpid_set,
 299         .vlan_offload_set             = i40e_vlan_offload_set,
 300         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 301         .vlan_pvid_set                = i40e_vlan_pvid_set,
 302         .rx_queue_start               = i40e_dev_rx_queue_start,
 303         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 304         .tx_queue_start               = i40e_dev_tx_queue_start,
 305         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 306         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 307         .rx_queue_release             = i40e_dev_rx_queue_release,
 308         .rx_queue_count               = i40e_dev_rx_queue_count,
 309         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 310         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 311         .tx_queue_release             = i40e_dev_tx_queue_release,
 312         .dev_led_on                   = i40e_dev_led_on,
 313         .dev_led_off                  = i40e_dev_led_off,
 314         .flow_ctrl_get                = i40e_flow_ctrl_get,
 315         .flow_ctrl_set                = i40e_flow_ctrl_set,
 316         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 317         .mac_addr_add                 = i40e_macaddr_add,
 318         .mac_addr_remove              = i40e_macaddr_remove,
 319         .reta_update                  = i40e_dev_rss_reta_update,
 320         .reta_query                   = i40e_dev_rss_reta_query,
 321         .rss_hash_update              = i40e_dev_rss_hash_update,
 322         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 323         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 324         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 325         .filter_ctrl                  = i40e_dev_filter_ctrl,
 326         .rxq_info_get                 = i40e_rxq_info_get,
 327         .txq_info_get                 = i40e_txq_info_get,
 328         .mirror_rule_set              = i40e_mirror_rule_set,
 329         .mirror_rule_reset            = i40e_mirror_rule_reset,
 330         .timesync_enable              = i40e_timesync_enable,
 331         .timesync_disable             = i40e_timesync_disable,
 332         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 333         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 334         .get_dcb_info                 = i40e_dev_get_dcb_info,
 335 };
 336
 337 /* store statistics names and its offset in stats structure */
 338 struct rte_i40e_xstats_name_off {
 339         char name[RTE_ETH_XSTATS_NAME_SIZE];
 340         unsigned offset;
 341 };
 342
 343 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 344         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 345         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 346         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 347         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 348         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 349                 rx_unknown_protocol)},
 350         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 351         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 352         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 353         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 354 };
 355
 356 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 357         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 358                 tx_dropped_link_down)},
 359         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 360         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 361                 illegal_bytes)},
 362         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 363         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 364                 mac_local_faults)},
 365         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 366                 mac_remote_faults)},
 367         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 368                 rx_length_errors)},
 369         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 370         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 371         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 372         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 373         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 374         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 375                 rx_size_127)},
 376         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 377                 rx_size_255)},
 378         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 379                 rx_size_511)},
 380         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 381                 rx_size_1023)},
 382         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 383                 rx_size_1522)},
 384         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 385                 rx_size_big)},
 386         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 387                 rx_undersize)},
 388         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 389                 rx_oversize)},
 390         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 391                 mac_short_packet_dropped)},
 392         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 393                 rx_fragments)},
 394         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 395         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 396         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 397                 tx_size_127)},
 398         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 399                 tx_size_255)},
 400         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 401                 tx_size_511)},
 402         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 403                 tx_size_1023)},
 404         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 405                 tx_size_1522)},
 406         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 407                 tx_size_big)},
 408         {"rx_flow_director_atr_match_packets",
 409                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 410         {"rx_flow_director_sb_match_packets",
 411                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 412         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 413                 tx_lpi_status)},
 414         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 415                 rx_lpi_status)},
 416         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 417                 tx_lpi_count)},
 418         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 419                 rx_lpi_count)},
 420 };
 421
 422 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
 423 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
 424
 425 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 426                 sizeof(rte_i40e_stats_strings[0]))
 427 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 428                 sizeof(rte_i40e_hw_port_strings[0]))
 429 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
 430                 I40E_NB_HW_PORT_Q_STATS)
 431
 432 static struct eth_driver rte_i40e_pmd = {
 433         .pci_drv = {
 434                 .name = "rte_i40e_pmd",
 435                 .id_table = pci_id_i40e_map,
 436                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 437                         RTE_PCI_DRV_DETACHABLE,
 438         },
 439         .eth_dev_init = eth_i40e_dev_init,
 440         .eth_dev_uninit = eth_i40e_dev_uninit,
 441         .dev_private_size = sizeof(struct i40e_adapter),
 442 };
 443
 444 static inline int
 445 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 446                                      struct rte_eth_link *link)
 447 {
 448         struct rte_eth_link *dst = link;
 449         struct rte_eth_link *src = &(dev->data->dev_link);
 450
 451         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 452                                         *(uint64_t *)src) == 0)
 453                 return -1;
 454
 455         return 0;
 456 }
 457
 458 static inline int
 459 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 460                                       struct rte_eth_link *link)
 461 {
 462         struct rte_eth_link *dst = &(dev->data->dev_link);
 463         struct rte_eth_link *src = link;
 464
 465         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 466                                         *(uint64_t *)src) == 0)
 467                 return -1;
 468
 469         return 0;
 470 }
 471
 472 /*
 473  * Driver initialization routine.
 474  * Invoked once at EAL init time.
 475  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 476  */
 477 static int
 478 rte_i40e_pmd_init(const char *name __rte_unused,
 479                   const char *params __rte_unused)
 480 {
 481         PMD_INIT_FUNC_TRACE();
 482         rte_eth_driver_register(&rte_i40e_pmd);
 483
 484         return 0;
 485 }
 486
 487 static struct rte_driver rte_i40e_driver = {
 488         .type = PMD_PDEV,
 489         .init = rte_i40e_pmd_init,
 490 };
 491
 492 PMD_REGISTER_DRIVER(rte_i40e_driver);
 493
 494 /*
 495  * Initialize registers for flexible payload, which should be set by NVM.
 496  * This should be removed from code once it is fixed in NVM.
 497  */
 498 #ifndef I40E_GLQF_ORT
 499 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 500 #endif
 501 #ifndef I40E_GLQF_PIT
 502 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 503 #endif
 504
 505 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 506 {
 507         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 508         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 509         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 510         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 511         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 512         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 513         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 514         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 515         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 516         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 517
 518         /* GLQF_PIT Registers */
 519         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 520         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 521 }
 522
 523 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 524
 525 /*
 526  * Add a ethertype filter to drop all flow control frames transmitted
 527  * from VSIs.
 528 */
 529 static void
 530 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 531 {
 532         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 533         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 534                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 535                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 536         int ret;
 537
 538         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 539                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 540                                 pf->main_vsi_seid, 0,
 541                                 TRUE, NULL, NULL);
 542         if (ret)
 543                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 544                                   " frames from VSIs.");
 545 }
 546
 547 static int
 548 eth_i40e_dev_init(struct rte_eth_dev *dev)
 549 {
 550         struct rte_pci_device *pci_dev;
 551         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 552         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553         struct i40e_vsi *vsi;
 554         int ret;
 555         uint32_t len;
 556         uint8_t aq_fail = 0;
 557
 558         PMD_INIT_FUNC_TRACE();
 559
 560         dev->dev_ops = &i40e_eth_dev_ops;
 561         dev->rx_pkt_burst = i40e_recv_pkts;
 562         dev->tx_pkt_burst = i40e_xmit_pkts;
 563
 564         /* for secondary processes, we don't initialise any further as primary
 565          * has already done this work. Only check we don't need a different
 566          * RX function */
 567         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 568                 i40e_set_rx_function(dev);
 569                 i40e_set_tx_function(dev);
 570                 return 0;
 571         }
 572         pci_dev = dev->pci_dev;
 573
 574         rte_eth_copy_pci_info(dev, pci_dev);
 575
 576         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 577         pf->adapter->eth_dev = dev;
 578         pf->dev_data = dev->data;
 579
 580         hw->back = I40E_PF_TO_ADAPTER(pf);
 581         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 582         if (!hw->hw_addr) {
 583                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 584                              "as address is NULL");
 585                 return -ENODEV;
 586         }
 587
 588         hw->vendor_id = pci_dev->id.vendor_id;
 589         hw->device_id = pci_dev->id.device_id;
 590         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 591         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 592         hw->bus.device = pci_dev->addr.devid;
 593         hw->bus.func = pci_dev->addr.function;
 594         hw->adapter_stopped = 0;
 595
 596         /* Make sure all is clean before doing PF reset */
 597         i40e_clear_hw(hw);
 598
 599         /* Initialize the hardware */
 600         i40e_hw_init(hw);
 601
 602         /* Reset here to make sure all is clean for each PF */
 603         ret = i40e_pf_reset(hw);
 604         if (ret) {
 605                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 606                 return ret;
 607         }
 608
 609         /* Initialize the shared code (base driver) */
 610         ret = i40e_init_shared_code(hw);
 611         if (ret) {
 612                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 613                 return ret;
 614         }
 615
 616         /*
 617          * To work around the NVM issue,initialize registers
 618          * for flexible payload by software.
 619          * It should be removed once issues are fixed in NVM.
 620          */
 621         i40e_flex_payload_reg_init(hw);
 622
 623         /* Initialize the parameters for adminq */
 624         i40e_init_adminq_parameter(hw);
 625         ret = i40e_init_adminq(hw);
 626         if (ret != I40E_SUCCESS) {
 627                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 628                 return -EIO;
 629         }
 630         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 631                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 632                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 633                      ((hw->nvm.version >> 12) & 0xf),
 634                      ((hw->nvm.version >> 4) & 0xff),
 635                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 636
 637         /* Clear PXE mode */
 638         i40e_clear_pxe_mode(hw);
 639
 640         /*
 641          * On X710, performance number is far from the expectation on recent
 642          * firmware versions. The fix for this issue may not be integrated in
 643          * the following firmware version. So the workaround in software driver
 644          * is needed. It needs to modify the initial values of 3 internal only
 645          * registers. Note that the workaround can be removed when it is fixed
 646          * in firmware in the future.
 647          */
 648         i40e_configure_registers(hw);
 649
 650         /* Get hw capabilities */
 651         ret = i40e_get_cap(hw);
 652         if (ret != I40E_SUCCESS) {
 653                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 654                 goto err_get_capabilities;
 655         }
 656
 657         /* Initialize parameters for PF */
 658         ret = i40e_pf_parameter_init(dev);
 659         if (ret != 0) {
 660                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 661                 goto err_parameter_init;
 662         }
 663
 664         /* Initialize the queue management */
 665         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 666         if (ret < 0) {
 667                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 668                 goto err_qp_pool_init;
 669         }
 670         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 671                                 hw->func_caps.num_msix_vectors - 1);
 672         if (ret < 0) {
 673                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 674                 goto err_msix_pool_init;
 675         }
 676
 677         /* Initialize lan hmc */
 678         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 679                                 hw->func_caps.num_rx_qp, 0, 0);
 680         if (ret != I40E_SUCCESS) {
 681                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 682                 goto err_init_lan_hmc;
 683         }
 684
 685         /* Configure lan hmc */
 686         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 687         if (ret != I40E_SUCCESS) {
 688                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 689                 goto err_configure_lan_hmc;
 690         }
 691
 692         /* Get and check the mac address */
 693         i40e_get_mac_addr(hw, hw->mac.addr);
 694         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 695                 PMD_INIT_LOG(ERR, "mac address is not valid");
 696                 ret = -EIO;
 697                 goto err_get_mac_addr;
 698         }
 699         /* Copy the permanent MAC address */
 700         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 701                         (struct ether_addr *) hw->mac.perm_addr);
 702
 703         /* Disable flow control */
 704         hw->fc.requested_mode = I40E_FC_NONE;
 705         i40e_set_fc(hw, &aq_fail, TRUE);
 706
 707         /* PF setup, which includes VSI setup */
 708         ret = i40e_pf_setup(pf);
 709         if (ret) {
 710                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 711                 goto err_setup_pf_switch;
 712         }
 713
 714         vsi = pf->main_vsi;
 715
 716         /* Disable double vlan by default */
 717         i40e_vsi_config_double_vlan(vsi, FALSE);
 718
 719         if (!vsi->max_macaddrs)
 720                 len = ETHER_ADDR_LEN;
 721         else
 722                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 723
 724         /* Should be after VSI initialized */
 725         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 726         if (!dev->data->mac_addrs) {
 727                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 728                                         "for storing mac address");
 729                 goto err_mac_alloc;
 730         }
 731         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 732                                         &dev->data->mac_addrs[0]);
 733
 734         /* initialize pf host driver to setup SRIOV resource if applicable */
 735         i40e_pf_host_init(dev);
 736
 737         /* register callback func to eal lib */
 738         rte_intr_callback_register(&(pci_dev->intr_handle),
 739                 i40e_dev_interrupt_handler, (void *)dev);
 740
 741         /* configure and enable device interrupt */
 742         i40e_pf_config_irq0(hw);
 743         i40e_pf_enable_irq0(hw);
 744
 745         /* enable uio intr after callback register */
 746         rte_intr_enable(&(pci_dev->intr_handle));
 747         /*
 748          * Add an ethertype filter to drop all flow control frames transmitted
 749          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 750          * frames to wire.
 751          */
 752         i40e_add_tx_flow_control_drop_filter(pf);
 753
 754         /* initialize mirror rule list */
 755         TAILQ_INIT(&pf->mirror_list);
 756
 757         /* Init dcb to sw mode by default */
 758         ret = i40e_dcb_init_configure(dev, TRUE);
 759         if (ret != I40E_SUCCESS) {
 760                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 761                 pf->flags &= ~I40E_FLAG_DCB;
 762         }
 763
 764         return 0;
 765
 766 err_mac_alloc:
 767         i40e_vsi_release(pf->main_vsi);
 768 err_setup_pf_switch:
 769 err_get_mac_addr:
 770 err_configure_lan_hmc:
 771         (void)i40e_shutdown_lan_hmc(hw);
 772 err_init_lan_hmc:
 773         i40e_res_pool_destroy(&pf->msix_pool);
 774 err_msix_pool_init:
 775         i40e_res_pool_destroy(&pf->qp_pool);
 776 err_qp_pool_init:
 777 err_parameter_init:
 778 err_get_capabilities:
 779         (void)i40e_shutdown_adminq(hw);
 780
 781         return ret;
 782 }
 783
 784 static int
 785 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 786 {
 787         struct rte_pci_device *pci_dev;
 788         struct i40e_hw *hw;
 789         struct i40e_filter_control_settings settings;
 790         int ret;
 791         uint8_t aq_fail = 0;
 792
 793         PMD_INIT_FUNC_TRACE();
 794
 795         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 796                 return 0;
 797
 798         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 799         pci_dev = dev->pci_dev;
 800
 801         if (hw->adapter_stopped == 0)
 802                 i40e_dev_close(dev);
 803
 804         dev->dev_ops = NULL;
 805         dev->rx_pkt_burst = NULL;
 806         dev->tx_pkt_burst = NULL;
 807
 808         /* Disable LLDP */
 809         ret = i40e_aq_stop_lldp(hw, true, NULL);
 810         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 811                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 812
 813         /* Clear PXE mode */
 814         i40e_clear_pxe_mode(hw);
 815
 816         /* Unconfigure filter control */
 817         memset(&settings, 0, sizeof(settings));
 818         ret = i40e_set_filter_control(hw, &settings);
 819         if (ret)
 820                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 821                                         ret);
 822
 823         /* Disable flow control */
 824         hw->fc.requested_mode = I40E_FC_NONE;
 825         i40e_set_fc(hw, &aq_fail, TRUE);
 826
 827         /* uninitialize pf host driver */
 828         i40e_pf_host_uninit(dev);
 829
 830         rte_free(dev->data->mac_addrs);
 831         dev->data->mac_addrs = NULL;
 832
 833         /* disable uio intr before callback unregister */
 834         rte_intr_disable(&(pci_dev->intr_handle));
 835
 836         /* register callback func to eal lib */
 837         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 838                 i40e_dev_interrupt_handler, (void *)dev);
 839
 840         return 0;
 841 }
 842
 843 static int
 844 i40e_dev_configure(struct rte_eth_dev *dev)
 845 {
 846         struct i40e_adapter *ad =
 847                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 849         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 850         int i, ret;
 851
 852         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 853          * bulk allocation or vector Rx preconditions we will reset it.
 854          */
 855         ad->rx_bulk_alloc_allowed = true;
 856         ad->rx_vec_allowed = true;
 857         ad->tx_simple_allowed = true;
 858         ad->tx_vec_allowed = true;
 859
 860         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 861                 ret = i40e_fdir_setup(pf);
 862                 if (ret != I40E_SUCCESS) {
 863                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 864                         return -ENOTSUP;
 865                 }
 866                 ret = i40e_fdir_configure(dev);
 867                 if (ret < 0) {
 868                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 869                         goto err;
 870                 }
 871         } else
 872                 i40e_fdir_teardown(pf);
 873
 874         ret = i40e_dev_init_vlan(dev);
 875         if (ret < 0)
 876                 goto err;
 877
 878         /* VMDQ setup.
 879          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 880          *  RSS setting have different requirements.
 881          *  General PMD driver call sequence are NIC init, configure,
 882          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 883          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 884          *  applicable. So, VMDQ setting has to be done before
 885          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 886          *  For RSS setting, it will try to calculate actual configured RX queue
 887          *  number, which will be available after rx_queue_setup(). dev_start()
 888          *  function is good to place RSS setup.
 889          */
 890         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 891                 ret = i40e_vmdq_setup(dev);
 892                 if (ret)
 893                         goto err;
 894         }
 895
 896         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
 897                 ret = i40e_dcb_setup(dev);
 898                 if (ret) {
 899                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
 900                         goto err_dcb;
 901                 }
 902         }
 903
 904         return 0;
 905
 906 err_dcb:
 907         /* need to release vmdq resource if exists */
 908         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 909                 i40e_vsi_release(pf->vmdq[i].vsi);
 910                 pf->vmdq[i].vsi = NULL;
 911         }
 912         rte_free(pf->vmdq);
 913         pf->vmdq = NULL;
 914 err:
 915         /* need to release fdir resource if exists */
 916         i40e_fdir_teardown(pf);
 917         return ret;
 918 }
 919
 920 void
 921 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 922 {
 923         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 924         uint16_t msix_vect = vsi->msix_intr;
 925         uint16_t i;
 926
 927         for (i = 0; i < vsi->nb_qps; i++) {
 928                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 929                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 930                 rte_wmb();
 931         }
 932
 933         if (vsi->type != I40E_VSI_SRIOV) {
 934                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 935                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 936                                 msix_vect - 1), 0);
 937         } else {
 938                 uint32_t reg;
 939                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 940                         vsi->user_param + (msix_vect - 1);
 941
 942                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 943         }
 944         I40E_WRITE_FLUSH(hw);
 945 }
 946
 947 static inline uint16_t
 948 i40e_calc_itr_interval(int16_t interval)
 949 {
 950         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 951                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 952
 953         /* Convert to hardware count, as writing each 1 represents 2 us */
 954         return (interval/2);
 955 }
 956
 957 void
 958 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 959 {
 960         uint32_t val;
 961         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 962         uint16_t msix_vect = vsi->msix_intr;
 963         int i;
 964
 965         for (i = 0; i < vsi->nb_qps; i++)
 966                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 967
 968         /* Bind all RX queues to allocated MSIX interrupt */
 969         for (i = 0; i < vsi->nb_qps; i++) {
 970                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 971                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 972                         ((vsi->base_queue + i + 1) <<
 973                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 974                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 975                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 976
 977                 if (i == vsi->nb_qps - 1)
 978                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 979                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 980         }
 981
 982         /* Write first RX queue to Link list register as the head element */
 983         if (vsi->type != I40E_VSI_SRIOV) {
 984                 uint16_t interval =
 985                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 986
 987                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 988                                                 (vsi->base_queue <<
 989                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 990                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 991
 992                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 993                                                 msix_vect - 1), interval);
 994
 995 #ifndef I40E_GLINT_CTL
 996 #define I40E_GLINT_CTL                     0x0003F800
 997 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 998 #endif
 999                 /* Disable auto-mask on enabling of all none-zero  interrupt */
1000                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
1001                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
1002         } else {
1003                 uint32_t reg;
1004
1005                 /* num_msix_vectors_vf needs to minus irq0 */
1006                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1007                         vsi->user_param + (msix_vect - 1);
1008
1009                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
1010                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1011                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1012         }
1013
1014         I40E_WRITE_FLUSH(hw);
1015 }
1016
1017 static void
1018 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1019 {
1020         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1021         uint16_t interval = i40e_calc_itr_interval(\
1022                         RTE_LIBRTE_I40E_ITR_INTERVAL);
1023
1024         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
1025                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
1026                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1027                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1028                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1029 }
1030
1031 static void
1032 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1033 {
1034         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1035
1036         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
1037 }
1038
1039 static inline uint8_t
1040 i40e_parse_link_speed(uint16_t eth_link_speed)
1041 {
1042         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1043
1044         switch (eth_link_speed) {
1045         case ETH_LINK_SPEED_40G:
1046                 link_speed = I40E_LINK_SPEED_40GB;
1047                 break;
1048         case ETH_LINK_SPEED_20G:
1049                 link_speed = I40E_LINK_SPEED_20GB;
1050                 break;
1051         case ETH_LINK_SPEED_10G:
1052                 link_speed = I40E_LINK_SPEED_10GB;
1053                 break;
1054         case ETH_LINK_SPEED_1000:
1055                 link_speed = I40E_LINK_SPEED_1GB;
1056                 break;
1057         case ETH_LINK_SPEED_100:
1058                 link_speed = I40E_LINK_SPEED_100MB;
1059                 break;
1060         }
1061
1062         return link_speed;
1063 }
1064
1065 static int
1066 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1067 {
1068         enum i40e_status_code status;
1069         struct i40e_aq_get_phy_abilities_resp phy_ab;
1070         struct i40e_aq_set_phy_config phy_conf;
1071         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1072                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1073                         I40E_AQ_PHY_FLAG_LOW_POWER;
1074         const uint8_t advt = I40E_LINK_SPEED_40GB |
1075                         I40E_LINK_SPEED_10GB |
1076                         I40E_LINK_SPEED_1GB |
1077                         I40E_LINK_SPEED_100MB;
1078         int ret = -ENOTSUP;
1079
1080         /* Skip it on 40G interfaces, as a workaround for the link issue */
1081         if (i40e_is_40G_device(hw->device_id))
1082                 return I40E_SUCCESS;
1083
1084         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1085                                               NULL);
1086         if (status)
1087                 return ret;
1088
1089         memset(&phy_conf, 0, sizeof(phy_conf));
1090
1091         /* bits 0-2 use the values from get_phy_abilities_resp */
1092         abilities &= ~mask;
1093         abilities |= phy_ab.abilities & mask;
1094
1095         /* update ablities and speed */
1096         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1097                 phy_conf.link_speed = advt;
1098         else
1099                 phy_conf.link_speed = force_speed;
1100
1101         phy_conf.abilities = abilities;
1102
1103         /* use get_phy_abilities_resp value for the rest */
1104         phy_conf.phy_type = phy_ab.phy_type;
1105         phy_conf.eee_capability = phy_ab.eee_capability;
1106         phy_conf.eeer = phy_ab.eeer_val;
1107         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1108
1109         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1110                     phy_ab.abilities, phy_ab.link_speed);
1111         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1112                     phy_conf.abilities, phy_conf.link_speed);
1113
1114         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1115         if (status)
1116                 return ret;
1117
1118         return I40E_SUCCESS;
1119 }
1120
1121 static int
1122 i40e_apply_link_speed(struct rte_eth_dev *dev)
1123 {
1124         uint8_t speed;
1125         uint8_t abilities = 0;
1126         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         struct rte_eth_conf *conf = &dev->data->dev_conf;
1128
1129         speed = i40e_parse_link_speed(conf->link_speed);
1130         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1131         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1132                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1133         else
1134                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1135
1136         return i40e_phy_conf_link(hw, abilities, speed);
1137 }
1138
1139 static int
1140 i40e_dev_start(struct rte_eth_dev *dev)
1141 {
1142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1144         struct i40e_vsi *main_vsi = pf->main_vsi;
1145         int ret, i;
1146
1147         hw->adapter_stopped = 0;
1148
1149         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1150                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1151                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1152                              dev->data->dev_conf.link_duplex,
1153                              dev->data->port_id);
1154                 return -EINVAL;
1155         }
1156
1157         /* Initialize VSI */
1158         ret = i40e_dev_rxtx_init(pf);
1159         if (ret != I40E_SUCCESS) {
1160                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1161                 goto err_up;
1162         }
1163
1164         /* Map queues with MSIX interrupt */
1165         i40e_vsi_queues_bind_intr(main_vsi);
1166         i40e_vsi_enable_queues_intr(main_vsi);
1167
1168         /* Map VMDQ VSI queues with MSIX interrupt */
1169         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1170                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1171                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1172         }
1173
1174         /* enable FDIR MSIX interrupt */
1175         if (pf->fdir.fdir_vsi) {
1176                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1177                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1178         }
1179
1180         /* Enable all queues which have been configured */
1181         ret = i40e_dev_switch_queues(pf, TRUE);
1182         if (ret != I40E_SUCCESS) {
1183                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1184                 goto err_up;
1185         }
1186
1187         /* Enable receiving broadcast packets */
1188         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1189         if (ret != I40E_SUCCESS)
1190                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1191
1192         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1193                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1194                                                 true, NULL);
1195                 if (ret != I40E_SUCCESS)
1196                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1197         }
1198
1199         /* Apply link configure */
1200         ret = i40e_apply_link_speed(dev);
1201         if (I40E_SUCCESS != ret) {
1202                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1203                 goto err_up;
1204         }
1205
1206         return I40E_SUCCESS;
1207
1208 err_up:
1209         i40e_dev_switch_queues(pf, FALSE);
1210         i40e_dev_clear_queues(dev);
1211
1212         return ret;
1213 }
1214
1215 static void
1216 i40e_dev_stop(struct rte_eth_dev *dev)
1217 {
1218         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1219         struct i40e_vsi *main_vsi = pf->main_vsi;
1220         struct i40e_mirror_rule *p_mirror;
1221         int i;
1222
1223         /* Disable all queues */
1224         i40e_dev_switch_queues(pf, FALSE);
1225
1226         /* un-map queues with interrupt registers */
1227         i40e_vsi_disable_queues_intr(main_vsi);
1228         i40e_vsi_queues_unbind_intr(main_vsi);
1229
1230         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1231                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1232                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1233         }
1234
1235         if (pf->fdir.fdir_vsi) {
1236                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1237                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1238         }
1239         /* Clear all queues and release memory */
1240         i40e_dev_clear_queues(dev);
1241
1242         /* Set link down */
1243         i40e_dev_set_link_down(dev);
1244
1245         /* Remove all mirror rules */
1246         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1247                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1248                 rte_free(p_mirror);
1249         }
1250         pf->nb_mirror_rule = 0;
1251
1252 }
1253
1254 static void
1255 i40e_dev_close(struct rte_eth_dev *dev)
1256 {
1257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1258         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259         uint32_t reg;
1260         int i;
1261
1262         PMD_INIT_FUNC_TRACE();
1263
1264         i40e_dev_stop(dev);
1265         hw->adapter_stopped = 1;
1266         i40e_dev_free_queues(dev);
1267
1268         /* Disable interrupt */
1269         i40e_pf_disable_irq0(hw);
1270         rte_intr_disable(&(dev->pci_dev->intr_handle));
1271
1272         /* shutdown and destroy the HMC */
1273         i40e_shutdown_lan_hmc(hw);
1274
1275         /* release all the existing VSIs and VEBs */
1276         i40e_fdir_teardown(pf);
1277         i40e_vsi_release(pf->main_vsi);
1278
1279         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1280                 i40e_vsi_release(pf->vmdq[i].vsi);
1281                 pf->vmdq[i].vsi = NULL;
1282         }
1283
1284         rte_free(pf->vmdq);
1285         pf->vmdq = NULL;
1286
1287         /* shutdown the adminq */
1288         i40e_aq_queue_shutdown(hw, true);
1289         i40e_shutdown_adminq(hw);
1290
1291         i40e_res_pool_destroy(&pf->qp_pool);
1292         i40e_res_pool_destroy(&pf->msix_pool);
1293
1294         /* force a PF reset to clean anything leftover */
1295         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1296         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1297                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1298         I40E_WRITE_FLUSH(hw);
1299 }
1300
1301 static void
1302 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1303 {
1304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1306         struct i40e_vsi *vsi = pf->main_vsi;
1307         int status;
1308
1309         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1310                                                         true, NULL);
1311         if (status != I40E_SUCCESS)
1312                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1313
1314         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1315                                                         TRUE, NULL);
1316         if (status != I40E_SUCCESS)
1317                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1318
1319 }
1320
1321 static void
1322 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1323 {
1324         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1325         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         struct i40e_vsi *vsi = pf->main_vsi;
1327         int status;
1328
1329         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1330                                                         false, NULL);
1331         if (status != I40E_SUCCESS)
1332                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1333
1334         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1335                                                         false, NULL);
1336         if (status != I40E_SUCCESS)
1337                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1338 }
1339
1340 static void
1341 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1342 {
1343         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1344         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1345         struct i40e_vsi *vsi = pf->main_vsi;
1346         int ret;
1347
1348         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1349         if (ret != I40E_SUCCESS)
1350                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1351 }
1352
1353 static void
1354 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1355 {
1356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1358         struct i40e_vsi *vsi = pf->main_vsi;
1359         int ret;
1360
1361         if (dev->data->promiscuous == 1)
1362                 return; /* must remain in all_multicast mode */
1363
1364         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1365                                 vsi->seid, FALSE, NULL);
1366         if (ret != I40E_SUCCESS)
1367                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1368 }
1369
1370 /*
1371  * Set device link up.
1372  */
1373 static int
1374 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1375 {
1376         /* re-apply link speed setting */
1377         return i40e_apply_link_speed(dev);
1378 }
1379
1380 /*
1381  * Set device link down.
1382  */
1383 static int
1384 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1385 {
1386         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1387         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1388         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389
1390         return i40e_phy_conf_link(hw, abilities, speed);
1391 }
1392
1393 int
1394 i40e_dev_link_update(struct rte_eth_dev *dev,
1395                      int wait_to_complete)
1396 {
1397 #define CHECK_INTERVAL 100  /* 100ms */
1398 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1399         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         struct i40e_link_status link_status;
1401         struct rte_eth_link link, old;
1402         int status;
1403         unsigned rep_cnt = MAX_REPEAT_TIME;
1404
1405         memset(&link, 0, sizeof(link));
1406         memset(&old, 0, sizeof(old));
1407         memset(&link_status, 0, sizeof(link_status));
1408         rte_i40e_dev_atomic_read_link_status(dev, &old);
1409
1410         do {
1411                 /* Get link status information from hardware */
1412                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1413                 if (status != I40E_SUCCESS) {
1414                         link.link_speed = ETH_LINK_SPEED_100;
1415                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1416                         PMD_DRV_LOG(ERR, "Failed to get link info");
1417                         goto out;
1418                 }
1419
1420                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1421                 if (!wait_to_complete)
1422                         break;
1423
1424                 rte_delay_ms(CHECK_INTERVAL);
1425         } while (!link.link_status && rep_cnt--);
1426
1427         if (!link.link_status)
1428                 goto out;
1429
1430         /* i40e uses full duplex only */
1431         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1432
1433         /* Parse the link status */
1434         switch (link_status.link_speed) {
1435         case I40E_LINK_SPEED_100MB:
1436                 link.link_speed = ETH_LINK_SPEED_100;
1437                 break;
1438         case I40E_LINK_SPEED_1GB:
1439                 link.link_speed = ETH_LINK_SPEED_1000;
1440                 break;
1441         case I40E_LINK_SPEED_10GB:
1442                 link.link_speed = ETH_LINK_SPEED_10G;
1443                 break;
1444         case I40E_LINK_SPEED_20GB:
1445                 link.link_speed = ETH_LINK_SPEED_20G;
1446                 break;
1447         case I40E_LINK_SPEED_40GB:
1448                 link.link_speed = ETH_LINK_SPEED_40G;
1449                 break;
1450         default:
1451                 link.link_speed = ETH_LINK_SPEED_100;
1452                 break;
1453         }
1454
1455 out:
1456         rte_i40e_dev_atomic_write_link_status(dev, &link);
1457         if (link.link_status == old.link_status)
1458                 return -1;
1459
1460         return 0;
1461 }
1462
1463 /* Get all the statistics of a VSI */
1464 void
1465 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1466 {
1467         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1468         struct i40e_eth_stats *nes = &vsi->eth_stats;
1469         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1470         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1471
1472         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1473                             vsi->offset_loaded, &oes->rx_bytes,
1474                             &nes->rx_bytes);
1475         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1476                             vsi->offset_loaded, &oes->rx_unicast,
1477                             &nes->rx_unicast);
1478         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1479                             vsi->offset_loaded, &oes->rx_multicast,
1480                             &nes->rx_multicast);
1481         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1482                             vsi->offset_loaded, &oes->rx_broadcast,
1483                             &nes->rx_broadcast);
1484         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1485                             &oes->rx_discards, &nes->rx_discards);
1486         /* GLV_REPC not supported */
1487         /* GLV_RMPC not supported */
1488         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1489                             &oes->rx_unknown_protocol,
1490                             &nes->rx_unknown_protocol);
1491         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1492                             vsi->offset_loaded, &oes->tx_bytes,
1493                             &nes->tx_bytes);
1494         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1495                             vsi->offset_loaded, &oes->tx_unicast,
1496                             &nes->tx_unicast);
1497         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1498                             vsi->offset_loaded, &oes->tx_multicast,
1499                             &nes->tx_multicast);
1500         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1501                             vsi->offset_loaded,  &oes->tx_broadcast,
1502                             &nes->tx_broadcast);
1503         /* GLV_TDPC not supported */
1504         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1505                             &oes->tx_errors, &nes->tx_errors);
1506         vsi->offset_loaded = true;
1507
1508         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1509                     vsi->vsi_id);
1510         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1511         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1512         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1513         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1514         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1515         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1516                     nes->rx_unknown_protocol);
1517         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1518         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1519         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1520         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1521         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1522         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1523         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1524                     vsi->vsi_id);
1525 }
1526
1527 static void
1528 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1529 {
1530         unsigned int i;
1531         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1532         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1533         /* Get statistics of struct i40e_eth_stats */
1534         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1535                             I40E_GLPRT_GORCL(hw->port),
1536                             pf->offset_loaded, &os->eth.rx_bytes,
1537                             &ns->eth.rx_bytes);
1538         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1539                             I40E_GLPRT_UPRCL(hw->port),
1540                             pf->offset_loaded, &os->eth.rx_unicast,
1541                             &ns->eth.rx_unicast);
1542         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1543                             I40E_GLPRT_MPRCL(hw->port),
1544                             pf->offset_loaded, &os->eth.rx_multicast,
1545                             &ns->eth.rx_multicast);
1546         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1547                             I40E_GLPRT_BPRCL(hw->port),
1548                             pf->offset_loaded, &os->eth.rx_broadcast,
1549                             &ns->eth.rx_broadcast);
1550         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1551                             pf->offset_loaded, &os->eth.rx_discards,
1552                             &ns->eth.rx_discards);
1553         /* GLPRT_REPC not supported */
1554         /* GLPRT_RMPC not supported */
1555         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1556                             pf->offset_loaded,
1557                             &os->eth.rx_unknown_protocol,
1558                             &ns->eth.rx_unknown_protocol);
1559         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1560                             I40E_GLPRT_GOTCL(hw->port),
1561                             pf->offset_loaded, &os->eth.tx_bytes,
1562                             &ns->eth.tx_bytes);
1563         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1564                             I40E_GLPRT_UPTCL(hw->port),
1565                             pf->offset_loaded, &os->eth.tx_unicast,
1566                             &ns->eth.tx_unicast);
1567         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1568                             I40E_GLPRT_MPTCL(hw->port),
1569                             pf->offset_loaded, &os->eth.tx_multicast,
1570                             &ns->eth.tx_multicast);
1571         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1572                             I40E_GLPRT_BPTCL(hw->port),
1573                             pf->offset_loaded, &os->eth.tx_broadcast,
1574                             &ns->eth.tx_broadcast);
1575         /* GLPRT_TEPC not supported */
1576
1577         /* additional port specific stats */
1578         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1579                             pf->offset_loaded, &os->tx_dropped_link_down,
1580                             &ns->tx_dropped_link_down);
1581         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1582                             pf->offset_loaded, &os->crc_errors,
1583                             &ns->crc_errors);
1584         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1585                             pf->offset_loaded, &os->illegal_bytes,
1586                             &ns->illegal_bytes);
1587         /* GLPRT_ERRBC not supported */
1588         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1589                             pf->offset_loaded, &os->mac_local_faults,
1590                             &ns->mac_local_faults);
1591         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1592                             pf->offset_loaded, &os->mac_remote_faults,
1593                             &ns->mac_remote_faults);
1594         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1595                             pf->offset_loaded, &os->rx_length_errors,
1596                             &ns->rx_length_errors);
1597         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1598                             pf->offset_loaded, &os->link_xon_rx,
1599                             &ns->link_xon_rx);
1600         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1601                             pf->offset_loaded, &os->link_xoff_rx,
1602                             &ns->link_xoff_rx);
1603         for (i = 0; i < 8; i++) {
1604                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1605                                     pf->offset_loaded,
1606                                     &os->priority_xon_rx[i],
1607                                     &ns->priority_xon_rx[i]);
1608                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1609                                     pf->offset_loaded,
1610                                     &os->priority_xoff_rx[i],
1611                                     &ns->priority_xoff_rx[i]);
1612         }
1613         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1614                             pf->offset_loaded, &os->link_xon_tx,
1615                             &ns->link_xon_tx);
1616         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1617                             pf->offset_loaded, &os->link_xoff_tx,
1618                             &ns->link_xoff_tx);
1619         for (i = 0; i < 8; i++) {
1620                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1621                                     pf->offset_loaded,
1622                                     &os->priority_xon_tx[i],
1623                                     &ns->priority_xon_tx[i]);
1624                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1625                                     pf->offset_loaded,
1626                                     &os->priority_xoff_tx[i],
1627                                     &ns->priority_xoff_tx[i]);
1628                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1629                                     pf->offset_loaded,
1630                                     &os->priority_xon_2_xoff[i],
1631                                     &ns->priority_xon_2_xoff[i]);
1632         }
1633         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1634                             I40E_GLPRT_PRC64L(hw->port),
1635                             pf->offset_loaded, &os->rx_size_64,
1636                             &ns->rx_size_64);
1637         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1638                             I40E_GLPRT_PRC127L(hw->port),
1639                             pf->offset_loaded, &os->rx_size_127,
1640                             &ns->rx_size_127);
1641         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1642                             I40E_GLPRT_PRC255L(hw->port),
1643                             pf->offset_loaded, &os->rx_size_255,
1644                             &ns->rx_size_255);
1645         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1646                             I40E_GLPRT_PRC511L(hw->port),
1647                             pf->offset_loaded, &os->rx_size_511,
1648                             &ns->rx_size_511);
1649         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1650                             I40E_GLPRT_PRC1023L(hw->port),
1651                             pf->offset_loaded, &os->rx_size_1023,
1652                             &ns->rx_size_1023);
1653         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1654                             I40E_GLPRT_PRC1522L(hw->port),
1655                             pf->offset_loaded, &os->rx_size_1522,
1656                             &ns->rx_size_1522);
1657         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1658                             I40E_GLPRT_PRC9522L(hw->port),
1659                             pf->offset_loaded, &os->rx_size_big,
1660                             &ns->rx_size_big);
1661         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1662                             pf->offset_loaded, &os->rx_undersize,
1663                             &ns->rx_undersize);
1664         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1665                             pf->offset_loaded, &os->rx_fragments,
1666                             &ns->rx_fragments);
1667         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1668                             pf->offset_loaded, &os->rx_oversize,
1669                             &ns->rx_oversize);
1670         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1671                             pf->offset_loaded, &os->rx_jabber,
1672                             &ns->rx_jabber);
1673         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1674                             I40E_GLPRT_PTC64L(hw->port),
1675                             pf->offset_loaded, &os->tx_size_64,
1676                             &ns->tx_size_64);
1677         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1678                             I40E_GLPRT_PTC127L(hw->port),
1679                             pf->offset_loaded, &os->tx_size_127,
1680                             &ns->tx_size_127);
1681         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1682                             I40E_GLPRT_PTC255L(hw->port),
1683                             pf->offset_loaded, &os->tx_size_255,
1684                             &ns->tx_size_255);
1685         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1686                             I40E_GLPRT_PTC511L(hw->port),
1687                             pf->offset_loaded, &os->tx_size_511,
1688                             &ns->tx_size_511);
1689         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1690                             I40E_GLPRT_PTC1023L(hw->port),
1691                             pf->offset_loaded, &os->tx_size_1023,
1692                             &ns->tx_size_1023);
1693         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1694                             I40E_GLPRT_PTC1522L(hw->port),
1695                             pf->offset_loaded, &os->tx_size_1522,
1696                             &ns->tx_size_1522);
1697         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1698                             I40E_GLPRT_PTC9522L(hw->port),
1699                             pf->offset_loaded, &os->tx_size_big,
1700                             &ns->tx_size_big);
1701         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1702                            pf->offset_loaded,
1703                            &os->fd_sb_match, &ns->fd_sb_match);
1704         /* GLPRT_MSPDC not supported */
1705         /* GLPRT_XEC not supported */
1706
1707         pf->offset_loaded = true;
1708
1709         if (pf->main_vsi)
1710                 i40e_update_vsi_stats(pf->main_vsi);
1711 }
1712
1713 /* Get all statistics of a port */
1714 static void
1715 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1716 {
1717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1720         unsigned i;
1721
1722         /* call read registers - updates values, now write them to struct */
1723         i40e_read_stats_registers(pf, hw);
1724
1725         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1726                                                 ns->eth.rx_broadcast;
1727         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1728                                                 ns->eth.tx_broadcast;
1729         stats->ibytes   = ns->eth.rx_bytes;
1730         stats->obytes   = ns->eth.tx_bytes;
1731         stats->oerrors  = ns->eth.tx_errors;
1732         stats->imcasts  = ns->eth.rx_multicast;
1733         stats->fdirmatch = ns->fd_sb_match;
1734
1735         /* Rx Errors */
1736         stats->ibadcrc  = ns->crc_errors;
1737         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1738                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1739         stats->imissed  = ns->eth.rx_discards;
1740         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1741
1742         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1743         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1744         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1745         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1746         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1747         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1748         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1749                     ns->eth.rx_unknown_protocol);
1750         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1751         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1752         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1753         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1754         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1755         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1756
1757         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1758                     ns->tx_dropped_link_down);
1759         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1760         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1761                     ns->illegal_bytes);
1762         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1763         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1764                     ns->mac_local_faults);
1765         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1766                     ns->mac_remote_faults);
1767         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1768                     ns->rx_length_errors);
1769         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1770         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1771         for (i = 0; i < 8; i++) {
1772                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1773                                 i, ns->priority_xon_rx[i]);
1774                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1775                                 i, ns->priority_xoff_rx[i]);
1776         }
1777         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1778         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1779         for (i = 0; i < 8; i++) {
1780                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1781                                 i, ns->priority_xon_tx[i]);
1782                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1783                                 i, ns->priority_xoff_tx[i]);
1784                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1785                                 i, ns->priority_xon_2_xoff[i]);
1786         }
1787         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1788         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1789         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1790         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1791         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1792         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1793         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1794         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1795         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1796         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1797         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1798         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1799         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1800         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1801         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1802         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1803         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1804         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1805         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1806                         ns->mac_short_packet_dropped);
1807         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1808                     ns->checksum_error);
1809         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1810         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1811 }
1812
1813 static void
1814 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
1815 {
1816         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818         struct i40e_hw_port_stats *hw_stats = &pf->stats;
1819
1820         /* The hw registers are cleared on read */
1821         pf->offset_loaded = false;
1822         i40e_read_stats_registers(pf, hw);
1823
1824         /* reset software counters */
1825         memset(hw_stats, 0, sizeof(*hw_stats));
1826 }
1827
1828 static int
1829 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1830                     unsigned n)
1831 {
1832         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1833         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834         unsigned i, count = 0;
1835         struct i40e_hw_port_stats *hw_stats = &pf->stats;
1836
1837         if (n < I40E_NB_XSTATS)
1838                 return I40E_NB_XSTATS;
1839
1840         i40e_read_stats_registers(pf, hw);
1841
1842         /* Reset */
1843         if (xstats == NULL)
1844                 return 0;
1845
1846         /* Get stats from i40e_eth_stats struct */
1847         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
1848                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1849                          "%s", rte_i40e_stats_strings[i].name);
1850                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
1851                         rte_i40e_stats_strings[i].offset);
1852                 count++;
1853         }
1854
1855         /* Get individiual stats from i40e_hw_port struct */
1856         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
1857                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1858                          "%s", rte_i40e_hw_port_strings[i].name);
1859                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1860                                 rte_i40e_hw_port_strings[i].offset);
1861                 count++;
1862         }
1863
1864         /* Get per-queue stats from i40e_hw_port struct */
1865         for (i = 0; i < 8; i++) {
1866                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1867                          "rx_q%u_xon_priority_packets", i);
1868                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1869                                 offsetof(struct i40e_hw_port_stats,
1870                                          priority_xon_rx[i]));
1871                 count++;
1872
1873                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1874                          "rx_q%u_xoff_priority_packets", i);
1875                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1876                                 offsetof(struct i40e_hw_port_stats,
1877                                          priority_xoff_rx[i]));
1878                 count++;
1879
1880                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1881                          "tx_q%u_xon_priority_packets", i);
1882                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1883                                 offsetof(struct i40e_hw_port_stats,
1884                                          priority_xon_tx[i]));
1885                 count++;
1886
1887                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1888                          "tx_q%u_xoff_priority_packets", i);
1889                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1890                                 offsetof(struct i40e_hw_port_stats,
1891                                          priority_xoff_tx[i]));
1892                 count++;
1893
1894                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1895                          "xx_q%u_xon_to_xoff_priority_packets", i);
1896                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1897                                 offsetof(struct i40e_hw_port_stats,
1898                                          priority_xon_2_xoff[i]));
1899                 count++;
1900         }
1901
1902         return I40E_NB_XSTATS;
1903 }
1904
1905 /* Reset the statistics */
1906 static void
1907 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1908 {
1909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1910
1911         /* It results in reloading the start point of each counter */
1912         pf->offset_loaded = false;
1913 }
1914
1915 static int
1916 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1917                                  __rte_unused uint16_t queue_id,
1918                                  __rte_unused uint8_t stat_idx,
1919                                  __rte_unused uint8_t is_rx)
1920 {
1921         PMD_INIT_FUNC_TRACE();
1922
1923         return -ENOSYS;
1924 }
1925
1926 static void
1927 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1928 {
1929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1930         struct i40e_vsi *vsi = pf->main_vsi;
1931
1932         dev_info->max_rx_queues = vsi->nb_qps;
1933         dev_info->max_tx_queues = vsi->nb_qps;
1934         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1935         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1936         dev_info->max_mac_addrs = vsi->max_macaddrs;
1937         dev_info->max_vfs = dev->pci_dev->max_vfs;
1938         dev_info->rx_offload_capa =
1939                 DEV_RX_OFFLOAD_VLAN_STRIP |
1940                 DEV_RX_OFFLOAD_QINQ_STRIP |
1941                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1942                 DEV_RX_OFFLOAD_UDP_CKSUM |
1943                 DEV_RX_OFFLOAD_TCP_CKSUM;
1944         dev_info->tx_offload_capa =
1945                 DEV_TX_OFFLOAD_VLAN_INSERT |
1946                 DEV_TX_OFFLOAD_QINQ_INSERT |
1947                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1948                 DEV_TX_OFFLOAD_UDP_CKSUM |
1949                 DEV_TX_OFFLOAD_TCP_CKSUM |
1950                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1951                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1952                 DEV_TX_OFFLOAD_TCP_TSO;
1953         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1954                                                 sizeof(uint32_t);
1955         dev_info->reta_size = pf->hash_lut_size;
1956         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1957
1958         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1959                 .rx_thresh = {
1960                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1961                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1962                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1963                 },
1964                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1965                 .rx_drop_en = 0,
1966         };
1967
1968         dev_info->default_txconf = (struct rte_eth_txconf) {
1969                 .tx_thresh = {
1970                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1971                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1972                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1973                 },
1974                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1975                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1976                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1977                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1978         };
1979
1980         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1981                 .nb_max = I40E_MAX_RING_DESC,
1982                 .nb_min = I40E_MIN_RING_DESC,
1983                 .nb_align = I40E_ALIGN_RING_DESC,
1984         };
1985
1986         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1987                 .nb_max = I40E_MAX_RING_DESC,
1988                 .nb_min = I40E_MIN_RING_DESC,
1989                 .nb_align = I40E_ALIGN_RING_DESC,
1990         };
1991
1992         if (pf->flags & I40E_FLAG_VMDQ) {
1993                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1994                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1995                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1996                                                 pf->max_nb_vmdq_vsi;
1997                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1998                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1999                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2000         }
2001 }
2002
2003 static int
2004 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2005 {
2006         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2007         struct i40e_vsi *vsi = pf->main_vsi;
2008         PMD_INIT_FUNC_TRACE();
2009
2010         if (on)
2011                 return i40e_vsi_add_vlan(vsi, vlan_id);
2012         else
2013                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2014 }
2015
2016 static void
2017 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2018                    __rte_unused uint16_t tpid)
2019 {
2020         PMD_INIT_FUNC_TRACE();
2021 }
2022
2023 static void
2024 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2025 {
2026         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2027         struct i40e_vsi *vsi = pf->main_vsi;
2028
2029         if (mask & ETH_VLAN_STRIP_MASK) {
2030                 /* Enable or disable VLAN stripping */
2031                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2032                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2033                 else
2034                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2035         }
2036
2037         if (mask & ETH_VLAN_EXTEND_MASK) {
2038                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2039                         i40e_vsi_config_double_vlan(vsi, TRUE);
2040                 else
2041                         i40e_vsi_config_double_vlan(vsi, FALSE);
2042         }
2043 }
2044
2045 static void
2046 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2047                           __rte_unused uint16_t queue,
2048                           __rte_unused int on)
2049 {
2050         PMD_INIT_FUNC_TRACE();
2051 }
2052
2053 static int
2054 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2055 {
2056         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2057         struct i40e_vsi *vsi = pf->main_vsi;
2058         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2059         struct i40e_vsi_vlan_pvid_info info;
2060
2061         memset(&info, 0, sizeof(info));
2062         info.on = on;
2063         if (info.on)
2064                 info.config.pvid = pvid;
2065         else {
2066                 info.config.reject.tagged =
2067                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2068                 info.config.reject.untagged =
2069                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2070         }
2071
2072         return i40e_vsi_vlan_pvid_set(vsi, &info);
2073 }
2074
2075 static int
2076 i40e_dev_led_on(struct rte_eth_dev *dev)
2077 {
2078         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         uint32_t mode = i40e_led_get(hw);
2080
2081         if (mode == 0)
2082                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2083
2084         return 0;
2085 }
2086
2087 static int
2088 i40e_dev_led_off(struct rte_eth_dev *dev)
2089 {
2090         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         uint32_t mode = i40e_led_get(hw);
2092
2093         if (mode != 0)
2094                 i40e_led_set(hw, 0, false);
2095
2096         return 0;
2097 }
2098
2099 static int
2100 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2101 {
2102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2104
2105         fc_conf->pause_time = pf->fc_conf.pause_time;
2106         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2107         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2108
2109          /* Return current mode according to actual setting*/
2110         switch (hw->fc.current_mode) {
2111         case I40E_FC_FULL:
2112                 fc_conf->mode = RTE_FC_FULL;
2113                 break;
2114         case I40E_FC_TX_PAUSE:
2115                 fc_conf->mode = RTE_FC_TX_PAUSE;
2116                 break;
2117         case I40E_FC_RX_PAUSE:
2118                 fc_conf->mode = RTE_FC_RX_PAUSE;
2119                 break;
2120         case I40E_FC_NONE:
2121         default:
2122                 fc_conf->mode = RTE_FC_NONE;
2123         };
2124
2125         return 0;
2126 }
2127
2128 static int
2129 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2130 {
2131         uint32_t mflcn_reg, fctrl_reg, reg;
2132         uint32_t max_high_water;
2133         uint8_t i, aq_failure;
2134         int err;
2135         struct i40e_hw *hw;
2136         struct i40e_pf *pf;
2137         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2138                 [RTE_FC_NONE] = I40E_FC_NONE,
2139                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2140                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2141                 [RTE_FC_FULL] = I40E_FC_FULL
2142         };
2143
2144         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2145
2146         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2147         if ((fc_conf->high_water > max_high_water) ||
2148                         (fc_conf->high_water < fc_conf->low_water)) {
2149                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2150                         "High_water must <= %d.", max_high_water);
2151                 return -EINVAL;
2152         }
2153
2154         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2156         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2157
2158         pf->fc_conf.pause_time = fc_conf->pause_time;
2159         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2160         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2161
2162         PMD_INIT_FUNC_TRACE();
2163
2164         /* All the link flow control related enable/disable register
2165          * configuration is handle by the F/W
2166          */
2167         err = i40e_set_fc(hw, &aq_failure, true);
2168         if (err < 0)
2169                 return -ENOSYS;
2170
2171         if (i40e_is_40G_device(hw->device_id)) {
2172                 /* Configure flow control refresh threshold,
2173                  * the value for stat_tx_pause_refresh_timer[8]
2174                  * is used for global pause operation.
2175                  */
2176
2177                 I40E_WRITE_REG(hw,
2178                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2179                                pf->fc_conf.pause_time);
2180
2181                 /* configure the timer value included in transmitted pause
2182                  * frame,
2183                  * the value for stat_tx_pause_quanta[8] is used for global
2184                  * pause operation
2185                  */
2186                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2187                                pf->fc_conf.pause_time);
2188
2189                 fctrl_reg = I40E_READ_REG(hw,
2190                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2191
2192                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2193                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2194                 else
2195                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2196
2197                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2198                                fctrl_reg);
2199         } else {
2200                 /* Configure pause time (2 TCs per register) */
2201                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2202                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2203                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2204
2205                 /* Configure flow control refresh threshold value */
2206                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2207                                pf->fc_conf.pause_time / 2);
2208
2209                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2210
2211                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2212                  *depending on configuration
2213                  */
2214                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2215                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2216                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2217                 } else {
2218                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2219                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2220                 }
2221
2222                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2223         }
2224
2225         /* config the water marker both based on the packets and bytes */
2226         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2227                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2228                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2229         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2230                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2231                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2232         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2233                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2234                        << I40E_KILOSHIFT);
2235         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2236                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2237                        << I40E_KILOSHIFT);
2238
2239         I40E_WRITE_FLUSH(hw);
2240
2241         return 0;
2242 }
2243
2244 static int
2245 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2246                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2247 {
2248         PMD_INIT_FUNC_TRACE();
2249
2250         return -ENOSYS;
2251 }
2252
2253 /* Add a MAC address, and update filters */
2254 static void
2255 i40e_macaddr_add(struct rte_eth_dev *dev,
2256                  struct ether_addr *mac_addr,
2257                  __rte_unused uint32_t index,
2258                  uint32_t pool)
2259 {
2260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2261         struct i40e_mac_filter_info mac_filter;
2262         struct i40e_vsi *vsi;
2263         int ret;
2264
2265         /* If VMDQ not enabled or configured, return */
2266         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2267                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2268                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2269                         pool);
2270                 return;
2271         }
2272
2273         if (pool > pf->nb_cfg_vmdq_vsi) {
2274                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2275                                 pool, pf->nb_cfg_vmdq_vsi);
2276                 return;
2277         }
2278
2279         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2280         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2281
2282         if (pool == 0)
2283                 vsi = pf->main_vsi;
2284         else
2285                 vsi = pf->vmdq[pool - 1].vsi;
2286
2287         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2288         if (ret != I40E_SUCCESS) {
2289                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2290                 return;
2291         }
2292 }
2293
2294 /* Remove a MAC address, and update filters */
2295 static void
2296 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2297 {
2298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2299         struct i40e_vsi *vsi;
2300         struct rte_eth_dev_data *data = dev->data;
2301         struct ether_addr *macaddr;
2302         int ret;
2303         uint32_t i;
2304         uint64_t pool_sel;
2305
2306         macaddr = &(data->mac_addrs[index]);
2307
2308         pool_sel = dev->data->mac_pool_sel[index];
2309
2310         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2311                 if (pool_sel & (1ULL << i)) {
2312                         if (i == 0)
2313                                 vsi = pf->main_vsi;
2314                         else {
2315                                 /* No VMDQ pool enabled or configured */
2316                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2317                                         (i > pf->nb_cfg_vmdq_vsi)) {
2318                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2319                                                         "/configured");
2320                                         return;
2321                                 }
2322                                 vsi = pf->vmdq[i - 1].vsi;
2323                         }
2324                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2325
2326                         if (ret) {
2327                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2328                                 return;
2329                         }
2330                 }
2331         }
2332 }
2333
2334 /* Set perfect match or hash match of MAC and VLAN for a VF */
2335 static int
2336 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2337                  struct rte_eth_mac_filter *filter,
2338                  bool add)
2339 {
2340         struct i40e_hw *hw;
2341         struct i40e_mac_filter_info mac_filter;
2342         struct ether_addr old_mac;
2343         struct ether_addr *new_mac;
2344         struct i40e_pf_vf *vf = NULL;
2345         uint16_t vf_id;
2346         int ret;
2347
2348         if (pf == NULL) {
2349                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2350                 return -EINVAL;
2351         }
2352         hw = I40E_PF_TO_HW(pf);
2353
2354         if (filter == NULL) {
2355                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2356                 return -EINVAL;
2357         }
2358
2359         new_mac = &filter->mac_addr;
2360
2361         if (is_zero_ether_addr(new_mac)) {
2362                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2363                 return -EINVAL;
2364         }
2365
2366         vf_id = filter->dst_id;
2367
2368         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2369                 PMD_DRV_LOG(ERR, "Invalid argument.");
2370                 return -EINVAL;
2371         }
2372         vf = &pf->vfs[vf_id];
2373
2374         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2375                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2376                 return -EINVAL;
2377         }
2378
2379         if (add) {
2380                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2381                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2382                                 ETHER_ADDR_LEN);
2383                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2384                                  ETHER_ADDR_LEN);
2385
2386                 mac_filter.filter_type = filter->filter_type;
2387                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2388                 if (ret != I40E_SUCCESS) {
2389                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2390                         return -1;
2391                 }
2392                 ether_addr_copy(new_mac, &pf->dev_addr);
2393         } else {
2394                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2395                                 ETHER_ADDR_LEN);
2396                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2397                 if (ret != I40E_SUCCESS) {
2398                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2399                         return -1;
2400                 }
2401
2402                 /* Clear device address as it has been removed */
2403                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2404                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2405         }
2406
2407         return 0;
2408 }
2409
2410 /* MAC filter handle */
2411 static int
2412 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2413                 void *arg)
2414 {
2415         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2416         struct rte_eth_mac_filter *filter;
2417         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2418         int ret = I40E_NOT_SUPPORTED;
2419
2420         filter = (struct rte_eth_mac_filter *)(arg);
2421
2422         switch (filter_op) {
2423         case RTE_ETH_FILTER_NOP:
2424                 ret = I40E_SUCCESS;
2425                 break;
2426         case RTE_ETH_FILTER_ADD:
2427                 i40e_pf_disable_irq0(hw);
2428                 if (filter->is_vf)
2429                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2430                 i40e_pf_enable_irq0(hw);
2431                 break;
2432         case RTE_ETH_FILTER_DELETE:
2433                 i40e_pf_disable_irq0(hw);
2434                 if (filter->is_vf)
2435                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2436                 i40e_pf_enable_irq0(hw);
2437                 break;
2438         default:
2439                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2440                 ret = I40E_ERR_PARAM;
2441                 break;
2442         }
2443
2444         return ret;
2445 }
2446
2447 static int
2448 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2449 {
2450         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2451         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2452         int ret;
2453
2454         if (!lut)
2455                 return -EINVAL;
2456
2457         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2458                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2459                                           lut, lut_size);
2460                 if (ret) {
2461                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2462                         return ret;
2463                 }
2464         } else {
2465                 uint32_t *lut_dw = (uint32_t *)lut;
2466                 uint16_t i, lut_size_dw = lut_size / 4;
2467
2468                 for (i = 0; i < lut_size_dw; i++)
2469                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2470         }
2471
2472         return 0;
2473 }
2474
2475 static int
2476 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2477 {
2478         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2479         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2480         int ret;
2481
2482         if (!vsi || !lut)
2483                 return -EINVAL;
2484
2485         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2486                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2487                                           lut, lut_size);
2488                 if (ret) {
2489                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2490                         return ret;
2491                 }
2492         } else {
2493                 uint32_t *lut_dw = (uint32_t *)lut;
2494                 uint16_t i, lut_size_dw = lut_size / 4;
2495
2496                 for (i = 0; i < lut_size_dw; i++)
2497                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2498                 I40E_WRITE_FLUSH(hw);
2499         }
2500
2501         return 0;
2502 }
2503
2504 static int
2505 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2506                          struct rte_eth_rss_reta_entry64 *reta_conf,
2507                          uint16_t reta_size)
2508 {
2509         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2510         uint16_t i, lut_size = pf->hash_lut_size;
2511         uint16_t idx, shift;
2512         uint8_t *lut;
2513         int ret;
2514
2515         if (reta_size != lut_size ||
2516                 reta_size > ETH_RSS_RETA_SIZE_512) {
2517                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2518                         "(%d) doesn't match the number hardware can supported "
2519                                         "(%d)\n", reta_size, lut_size);
2520                 return -EINVAL;
2521         }
2522
2523         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2524         if (!lut) {
2525                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2526                 return -ENOMEM;
2527         }
2528         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2529         if (ret)
2530                 goto out;
2531         for (i = 0; i < reta_size; i++) {
2532                 idx = i / RTE_RETA_GROUP_SIZE;
2533                 shift = i % RTE_RETA_GROUP_SIZE;
2534                 if (reta_conf[idx].mask & (1ULL << shift))
2535                         lut[i] = reta_conf[idx].reta[shift];
2536         }
2537         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2538
2539 out:
2540         rte_free(lut);
2541
2542         return ret;
2543 }
2544
2545 static int
2546 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2547                         struct rte_eth_rss_reta_entry64 *reta_conf,
2548                         uint16_t reta_size)
2549 {
2550         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2551         uint16_t i, lut_size = pf->hash_lut_size;
2552         uint16_t idx, shift;
2553         uint8_t *lut;
2554         int ret;
2555
2556         if (reta_size != lut_size ||
2557                 reta_size > ETH_RSS_RETA_SIZE_512) {
2558                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2559                         "(%d) doesn't match the number hardware can supported "
2560                                         "(%d)\n", reta_size, lut_size);
2561                 return -EINVAL;
2562         }
2563
2564         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2565         if (!lut) {
2566                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2567                 return -ENOMEM;
2568         }
2569
2570         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2571         if (ret)
2572                 goto out;
2573         for (i = 0; i < reta_size; i++) {
2574                 idx = i / RTE_RETA_GROUP_SIZE;
2575                 shift = i % RTE_RETA_GROUP_SIZE;
2576                 if (reta_conf[idx].mask & (1ULL << shift))
2577                         reta_conf[idx].reta[shift] = lut[i];
2578         }
2579
2580 out:
2581         rte_free(lut);
2582
2583         return ret;
2584 }
2585
2586 /**
2587  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2588  * @hw:   pointer to the HW structure
2589  * @mem:  pointer to mem struct to fill out
2590  * @size: size of memory requested
2591  * @alignment: what to align the allocation to
2592  **/
2593 enum i40e_status_code
2594 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2595                         struct i40e_dma_mem *mem,
2596                         u64 size,
2597                         u32 alignment)
2598 {
2599         static uint64_t id = 0;
2600         const struct rte_memzone *mz = NULL;
2601         char z_name[RTE_MEMZONE_NAMESIZE];
2602
2603         if (!mem)
2604                 return I40E_ERR_PARAM;
2605
2606         id++;
2607         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2608 #ifdef RTE_LIBRTE_XEN_DOM0
2609         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2610                                          alignment, RTE_PGSIZE_2M);
2611 #else
2612         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2613                                          alignment);
2614 #endif
2615         if (!mz)
2616                 return I40E_ERR_NO_MEMORY;
2617
2618         mem->id = id;
2619         mem->size = size;
2620         mem->va = mz->addr;
2621 #ifdef RTE_LIBRTE_XEN_DOM0
2622         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2623 #else
2624         mem->pa = mz->phys_addr;
2625 #endif
2626
2627         return I40E_SUCCESS;
2628 }
2629
2630 /**
2631  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2632  * @hw:   pointer to the HW structure
2633  * @mem:  ptr to mem struct to free
2634  **/
2635 enum i40e_status_code
2636 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2637                     struct i40e_dma_mem *mem)
2638 {
2639         if (!mem || !mem->va)
2640                 return I40E_ERR_PARAM;
2641
2642         mem->va = NULL;
2643         mem->pa = (u64)0;
2644
2645         return I40E_SUCCESS;
2646 }
2647
2648 /**
2649  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2650  * @hw:   pointer to the HW structure
2651  * @mem:  pointer to mem struct to fill out
2652  * @size: size of memory requested
2653  **/
2654 enum i40e_status_code
2655 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2656                          struct i40e_virt_mem *mem,
2657                          u32 size)
2658 {
2659         if (!mem)
2660                 return I40E_ERR_PARAM;
2661
2662         mem->size = size;
2663         mem->va = rte_zmalloc("i40e", size, 0);
2664
2665         if (mem->va)
2666                 return I40E_SUCCESS;
2667         else
2668                 return I40E_ERR_NO_MEMORY;
2669 }
2670
2671 /**
2672  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2673  * @hw:   pointer to the HW structure
2674  * @mem:  pointer to mem struct to free
2675  **/
2676 enum i40e_status_code
2677 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2678                      struct i40e_virt_mem *mem)
2679 {
2680         if (!mem)
2681                 return I40E_ERR_PARAM;
2682
2683         rte_free(mem->va);
2684         mem->va = NULL;
2685
2686         return I40E_SUCCESS;
2687 }
2688
2689 void
2690 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2691 {
2692         rte_spinlock_init(&sp->spinlock);
2693 }
2694
2695 void
2696 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2697 {
2698         rte_spinlock_lock(&sp->spinlock);
2699 }
2700
2701 void
2702 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2703 {
2704         rte_spinlock_unlock(&sp->spinlock);
2705 }
2706
2707 void
2708 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2709 {
2710         return;
2711 }
2712
2713 /**
2714  * Get the hardware capabilities, which will be parsed
2715  * and saved into struct i40e_hw.
2716  */
2717 static int
2718 i40e_get_cap(struct i40e_hw *hw)
2719 {
2720         struct i40e_aqc_list_capabilities_element_resp *buf;
2721         uint16_t len, size = 0;
2722         int ret;
2723
2724         /* Calculate a huge enough buff for saving response data temporarily */
2725         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2726                                                 I40E_MAX_CAP_ELE_NUM;
2727         buf = rte_zmalloc("i40e", len, 0);
2728         if (!buf) {
2729                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2730                 return I40E_ERR_NO_MEMORY;
2731         }
2732
2733         /* Get, parse the capabilities and save it to hw */
2734         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2735                         i40e_aqc_opc_list_func_capabilities, NULL);
2736         if (ret != I40E_SUCCESS)
2737                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2738
2739         /* Free the temporary buffer after being used */
2740         rte_free(buf);
2741
2742         return ret;
2743 }
2744
2745 static int
2746 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2747 {
2748         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2749         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2750         uint16_t qp_count = 0, vsi_count = 0;
2751
2752         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2753                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2754                 return -EINVAL;
2755         }
2756         /* Add the parameter init for LFC */
2757         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2758         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2759         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2760
2761         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2762         pf->max_num_vsi = hw->func_caps.num_vsis;
2763         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
2764         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2765         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2766
2767         /* FDir queue/VSI allocation */
2768         pf->fdir_qp_offset = 0;
2769         if (hw->func_caps.fd) {
2770                 pf->flags |= I40E_FLAG_FDIR;
2771                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2772         } else {
2773                 pf->fdir_nb_qps = 0;
2774         }
2775         qp_count += pf->fdir_nb_qps;
2776         vsi_count += 1;
2777
2778         /* LAN queue/VSI allocation */
2779         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
2780         if (!hw->func_caps.rss) {
2781                 pf->lan_nb_qps = 1;
2782         } else {
2783                 pf->flags |= I40E_FLAG_RSS;
2784                 if (hw->mac.type == I40E_MAC_X722)
2785                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
2786                 pf->lan_nb_qps = pf->lan_nb_qp_max;
2787         }
2788         qp_count += pf->lan_nb_qps;
2789         vsi_count += 1;
2790
2791         /* VF queue/VSI allocation */
2792         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
2793         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2794                 pf->flags |= I40E_FLAG_SRIOV;
2795                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2796                 pf->vf_num = dev->pci_dev->max_vfs;
2797                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
2798                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
2799                             pf->vf_nb_qps * pf->vf_num);
2800         } else {
2801                 pf->vf_nb_qps = 0;
2802                 pf->vf_num = 0;
2803         }
2804         qp_count += pf->vf_nb_qps * pf->vf_num;
2805         vsi_count += pf->vf_num;
2806
2807         /* VMDq queue/VSI allocation */
2808         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
2809         if (hw->func_caps.vmdq) {
2810                 pf->flags |= I40E_FLAG_VMDQ;
2811                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
2812                 pf->max_nb_vmdq_vsi = 1;
2813                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues per VMDQ VSI, "
2814                             "in total %u queues", pf->max_nb_vmdq_vsi,
2815                             pf->vmdq_nb_qps,
2816                             pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
2817         } else {
2818                 pf->vmdq_nb_qps = 0;
2819                 pf->max_nb_vmdq_vsi = 0;
2820         }
2821         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2822         vsi_count += pf->max_nb_vmdq_vsi;
2823
2824         if (hw->func_caps.dcb)
2825                 pf->flags |= I40E_FLAG_DCB;
2826
2827         if (qp_count > hw->func_caps.num_tx_qp) {
2828                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
2829                             "the hardware maximum %u", qp_count,
2830                             hw->func_caps.num_tx_qp);
2831                 return -EINVAL;
2832         }
2833         if (vsi_count > hw->func_caps.num_vsis) {
2834                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
2835                             "the hardware maximum %u", vsi_count,
2836                             hw->func_caps.num_vsis);
2837                 return -EINVAL;
2838         }
2839
2840         return 0;
2841 }
2842
2843 static int
2844 i40e_pf_get_switch_config(struct i40e_pf *pf)
2845 {
2846         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2847         struct i40e_aqc_get_switch_config_resp *switch_config;
2848         struct i40e_aqc_switch_config_element_resp *element;
2849         uint16_t start_seid = 0, num_reported;
2850         int ret;
2851
2852         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2853                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2854         if (!switch_config) {
2855                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2856                 return -ENOMEM;
2857         }
2858
2859         /* Get the switch configurations */
2860         ret = i40e_aq_get_switch_config(hw, switch_config,
2861                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2862         if (ret != I40E_SUCCESS) {
2863                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2864                 goto fail;
2865         }
2866         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2867         if (num_reported != 1) { /* The number should be 1 */
2868                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2869                 goto fail;
2870         }
2871
2872         /* Parse the switch configuration elements */
2873         element = &(switch_config->element[0]);
2874         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2875                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2876                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2877         } else
2878                 PMD_DRV_LOG(INFO, "Unknown element type");
2879
2880 fail:
2881         rte_free(switch_config);
2882
2883         return ret;
2884 }
2885
2886 static int
2887 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2888                         uint32_t num)
2889 {
2890         struct pool_entry *entry;
2891
2892         if (pool == NULL || num == 0)
2893                 return -EINVAL;
2894
2895         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2896         if (entry == NULL) {
2897                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2898                 return -ENOMEM;
2899         }
2900
2901         /* queue heap initialize */
2902         pool->num_free = num;
2903         pool->num_alloc = 0;
2904         pool->base = base;
2905         LIST_INIT(&pool->alloc_list);
2906         LIST_INIT(&pool->free_list);
2907
2908         /* Initialize element  */
2909         entry->base = 0;
2910         entry->len = num;
2911
2912         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2913         return 0;
2914 }
2915
2916 static void
2917 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2918 {
2919         struct pool_entry *entry;
2920
2921         if (pool == NULL)
2922                 return;
2923
2924         LIST_FOREACH(entry, &pool->alloc_list, next) {
2925                 LIST_REMOVE(entry, next);
2926                 rte_free(entry);
2927         }
2928
2929         LIST_FOREACH(entry, &pool->free_list, next) {
2930                 LIST_REMOVE(entry, next);
2931                 rte_free(entry);
2932         }
2933
2934         pool->num_free = 0;
2935         pool->num_alloc = 0;
2936         pool->base = 0;
2937         LIST_INIT(&pool->alloc_list);
2938         LIST_INIT(&pool->free_list);
2939 }
2940
2941 static int
2942 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2943                        uint32_t base)
2944 {
2945         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2946         uint32_t pool_offset;
2947         int insert;
2948
2949         if (pool == NULL) {
2950                 PMD_DRV_LOG(ERR, "Invalid parameter");
2951                 return -EINVAL;
2952         }
2953
2954         pool_offset = base - pool->base;
2955         /* Lookup in alloc list */
2956         LIST_FOREACH(entry, &pool->alloc_list, next) {
2957                 if (entry->base == pool_offset) {
2958                         valid_entry = entry;
2959                         LIST_REMOVE(entry, next);
2960                         break;
2961                 }
2962         }
2963
2964         /* Not find, return */
2965         if (valid_entry == NULL) {
2966                 PMD_DRV_LOG(ERR, "Failed to find entry");
2967                 return -EINVAL;
2968         }
2969
2970         /**
2971          * Found it, move it to free list  and try to merge.
2972          * In order to make merge easier, always sort it by qbase.
2973          * Find adjacent prev and last entries.
2974          */
2975         prev = next = NULL;
2976         LIST_FOREACH(entry, &pool->free_list, next) {
2977                 if (entry->base > valid_entry->base) {
2978                         next = entry;
2979                         break;
2980                 }
2981                 prev = entry;
2982         }
2983
2984         insert = 0;
2985         /* Try to merge with next one*/
2986         if (next != NULL) {
2987                 /* Merge with next one */
2988                 if (valid_entry->base + valid_entry->len == next->base) {
2989                         next->base = valid_entry->base;
2990                         next->len += valid_entry->len;
2991                         rte_free(valid_entry);
2992                         valid_entry = next;
2993                         insert = 1;
2994                 }
2995         }
2996
2997         if (prev != NULL) {
2998                 /* Merge with previous one */
2999                 if (prev->base + prev->len == valid_entry->base) {
3000                         prev->len += valid_entry->len;
3001                         /* If it merge with next one, remove next node */
3002                         if (insert == 1) {
3003                                 LIST_REMOVE(valid_entry, next);
3004                                 rte_free(valid_entry);
3005                         } else {
3006                                 rte_free(valid_entry);
3007                                 insert = 1;
3008                         }
3009                 }
3010         }
3011
3012         /* Not find any entry to merge, insert */
3013         if (insert == 0) {
3014                 if (prev != NULL)
3015                         LIST_INSERT_AFTER(prev, valid_entry, next);
3016                 else if (next != NULL)
3017                         LIST_INSERT_BEFORE(next, valid_entry, next);
3018                 else /* It's empty list, insert to head */
3019                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3020         }
3021
3022         pool->num_free += valid_entry->len;
3023         pool->num_alloc -= valid_entry->len;
3024
3025         return 0;
3026 }
3027
3028 static int
3029 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3030                        uint16_t num)
3031 {
3032         struct pool_entry *entry, *valid_entry;
3033
3034         if (pool == NULL || num == 0) {
3035                 PMD_DRV_LOG(ERR, "Invalid parameter");
3036                 return -EINVAL;
3037         }
3038
3039         if (pool->num_free < num) {
3040                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3041                             num, pool->num_free);
3042                 return -ENOMEM;
3043         }
3044
3045         valid_entry = NULL;
3046         /* Lookup  in free list and find most fit one */
3047         LIST_FOREACH(entry, &pool->free_list, next) {
3048                 if (entry->len >= num) {
3049                         /* Find best one */
3050                         if (entry->len == num) {
3051                                 valid_entry = entry;
3052                                 break;
3053                         }
3054                         if (valid_entry == NULL || valid_entry->len > entry->len)
3055                                 valid_entry = entry;
3056                 }
3057         }
3058
3059         /* Not find one to satisfy the request, return */
3060         if (valid_entry == NULL) {
3061                 PMD_DRV_LOG(ERR, "No valid entry found");
3062                 return -ENOMEM;
3063         }
3064         /**
3065          * The entry have equal queue number as requested,
3066          * remove it from alloc_list.
3067          */
3068         if (valid_entry->len == num) {
3069                 LIST_REMOVE(valid_entry, next);
3070         } else {
3071                 /**
3072                  * The entry have more numbers than requested,
3073                  * create a new entry for alloc_list and minus its
3074                  * queue base and number in free_list.
3075                  */
3076                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3077                 if (entry == NULL) {
3078                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3079                                     "resource pool");
3080                         return -ENOMEM;
3081                 }
3082                 entry->base = valid_entry->base;
3083                 entry->len = num;
3084                 valid_entry->base += num;
3085                 valid_entry->len -= num;
3086                 valid_entry = entry;
3087         }
3088
3089         /* Insert it into alloc list, not sorted */
3090         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3091
3092         pool->num_free -= valid_entry->len;
3093         pool->num_alloc += valid_entry->len;
3094
3095         return (valid_entry->base + pool->base);
3096 }
3097
3098 /**
3099  * bitmap_is_subset - Check whether src2 is subset of src1
3100  **/
3101 static inline int
3102 bitmap_is_subset(uint8_t src1, uint8_t src2)
3103 {
3104         return !((src1 ^ src2) & src2);
3105 }
3106
3107 static int
3108 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3109 {
3110         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3111
3112         /* If DCB is not supported, only default TC is supported */
3113         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3114                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3115                 return -EINVAL;
3116         }
3117
3118         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3119                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3120                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3121                             enabled_tcmap);
3122                 return -EINVAL;
3123         }
3124         return I40E_SUCCESS;
3125 }
3126
3127 int
3128 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3129                                 struct i40e_vsi_vlan_pvid_info *info)
3130 {
3131         struct i40e_hw *hw;
3132         struct i40e_vsi_context ctxt;
3133         uint8_t vlan_flags = 0;
3134         int ret;
3135
3136         if (vsi == NULL || info == NULL) {
3137                 PMD_DRV_LOG(ERR, "invalid parameters");
3138                 return I40E_ERR_PARAM;
3139         }
3140
3141         if (info->on) {
3142                 vsi->info.pvid = info->config.pvid;
3143                 /**
3144                  * If insert pvid is enabled, only tagged pkts are
3145                  * allowed to be sent out.
3146                  */
3147                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3148                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3149         } else {
3150                 vsi->info.pvid = 0;
3151                 if (info->config.reject.tagged == 0)
3152                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3153
3154                 if (info->config.reject.untagged == 0)
3155                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3156         }
3157         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3158                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3159         vsi->info.port_vlan_flags |= vlan_flags;
3160         vsi->info.valid_sections =
3161                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3162         memset(&ctxt, 0, sizeof(ctxt));
3163         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3164         ctxt.seid = vsi->seid;
3165
3166         hw = I40E_VSI_TO_HW(vsi);
3167         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3168         if (ret != I40E_SUCCESS)
3169                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3170
3171         return ret;
3172 }
3173
3174 static int
3175 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3176 {
3177         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3178         int i, ret;
3179         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3180
3181         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3182         if (ret != I40E_SUCCESS)
3183                 return ret;
3184
3185         if (!vsi->seid) {
3186                 PMD_DRV_LOG(ERR, "seid not valid");
3187                 return -EINVAL;
3188         }
3189
3190         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3191         tc_bw_data.tc_valid_bits = enabled_tcmap;
3192         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3193                 tc_bw_data.tc_bw_credits[i] =
3194                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3195
3196         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3197         if (ret != I40E_SUCCESS) {
3198                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3199                 return ret;
3200         }
3201
3202         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3203                                         sizeof(vsi->info.qs_handle));
3204         return I40E_SUCCESS;
3205 }
3206
3207 static int
3208 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3209                                  struct i40e_aqc_vsi_properties_data *info,
3210                                  uint8_t enabled_tcmap)
3211 {
3212         int ret, i, total_tc = 0;
3213         uint16_t qpnum_per_tc, bsf, qp_idx;
3214
3215         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3216         if (ret != I40E_SUCCESS)
3217                 return ret;
3218
3219         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3220                 if (enabled_tcmap & (1 << i))
3221                         total_tc++;
3222         vsi->enabled_tc = enabled_tcmap;
3223
3224         /* Number of queues per enabled TC */
3225         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3226         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3227         bsf = rte_bsf32(qpnum_per_tc);
3228
3229         /* Adjust the queue number to actual queues that can be applied */
3230         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3231                 vsi->nb_qps = qpnum_per_tc * total_tc;
3232
3233         /**
3234          * Configure TC and queue mapping parameters, for enabled TC,
3235          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3236          * default queue will serve it.
3237          */
3238         qp_idx = 0;
3239         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3240                 if (vsi->enabled_tc & (1 << i)) {
3241                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3242                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3243                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3244                         qp_idx += qpnum_per_tc;
3245                 } else
3246                         info->tc_mapping[i] = 0;
3247         }
3248
3249         /* Associate queue number with VSI */
3250         if (vsi->type == I40E_VSI_SRIOV) {
3251                 info->mapping_flags |=
3252                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3253                 for (i = 0; i < vsi->nb_qps; i++)
3254                         info->queue_mapping[i] =
3255                                 rte_cpu_to_le_16(vsi->base_queue + i);
3256         } else {
3257                 info->mapping_flags |=
3258                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3259                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3260         }
3261         info->valid_sections |=
3262                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3263
3264         return I40E_SUCCESS;
3265 }
3266
3267 static int
3268 i40e_veb_release(struct i40e_veb *veb)
3269 {
3270         struct i40e_vsi *vsi;
3271         struct i40e_hw *hw;
3272
3273         if (veb == NULL || veb->associate_vsi == NULL)
3274                 return -EINVAL;
3275
3276         if (!TAILQ_EMPTY(&veb->head)) {
3277                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3278                 return -EACCES;
3279         }
3280
3281         vsi = veb->associate_vsi;
3282         hw = I40E_VSI_TO_HW(vsi);
3283
3284         vsi->uplink_seid = veb->uplink_seid;
3285         i40e_aq_delete_element(hw, veb->seid, NULL);
3286         rte_free(veb);
3287         vsi->veb = NULL;
3288         return I40E_SUCCESS;
3289 }
3290
3291 /* Setup a veb */
3292 static struct i40e_veb *
3293 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3294 {
3295         struct i40e_veb *veb;
3296         int ret;
3297         struct i40e_hw *hw;
3298
3299         if (NULL == pf || vsi == NULL) {
3300                 PMD_DRV_LOG(ERR, "veb setup failed, "
3301                             "associated VSI shouldn't null");
3302                 return NULL;
3303         }
3304         hw = I40E_PF_TO_HW(pf);
3305
3306         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3307         if (!veb) {
3308                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3309                 goto fail;
3310         }
3311
3312         veb->associate_vsi = vsi;
3313         TAILQ_INIT(&veb->head);
3314         veb->uplink_seid = vsi->uplink_seid;
3315
3316         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3317                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3318
3319         if (ret != I40E_SUCCESS) {
3320                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3321                             hw->aq.asq_last_status);
3322                 goto fail;
3323         }
3324
3325         /* get statistics index */
3326         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3327                                 &veb->stats_idx, NULL, NULL, NULL);
3328         if (ret != I40E_SUCCESS) {
3329                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3330                             hw->aq.asq_last_status);
3331                 goto fail;
3332         }
3333
3334         /* Get VEB bandwidth, to be implemented */
3335         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3336         vsi->uplink_seid = veb->seid;
3337
3338         return veb;
3339 fail:
3340         rte_free(veb);
3341         return NULL;
3342 }
3343
3344 int
3345 i40e_vsi_release(struct i40e_vsi *vsi)
3346 {
3347         struct i40e_pf *pf;
3348         struct i40e_hw *hw;
3349         struct i40e_vsi_list *vsi_list;
3350         int ret;
3351         struct i40e_mac_filter *f;
3352
3353         if (!vsi)
3354                 return I40E_SUCCESS;
3355
3356         pf = I40E_VSI_TO_PF(vsi);
3357         hw = I40E_VSI_TO_HW(vsi);
3358
3359         /* VSI has child to attach, release child first */
3360         if (vsi->veb) {
3361                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3362                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3363                                 return -1;
3364                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3365                 }
3366                 i40e_veb_release(vsi->veb);
3367         }
3368
3369         /* Remove all macvlan filters of the VSI */
3370         i40e_vsi_remove_all_macvlan_filter(vsi);
3371         TAILQ_FOREACH(f, &vsi->mac_list, next)
3372                 rte_free(f);
3373
3374         if (vsi->type != I40E_VSI_MAIN) {
3375                 /* Remove vsi from parent's sibling list */
3376                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3377                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3378                         return I40E_ERR_PARAM;
3379                 }
3380                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3381                                 &vsi->sib_vsi_list, list);
3382
3383                 /* Remove all switch element of the VSI */
3384                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3385                 if (ret != I40E_SUCCESS)
3386                         PMD_DRV_LOG(ERR, "Failed to delete element");
3387         }
3388         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3389
3390         if (vsi->type != I40E_VSI_SRIOV)
3391                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3392         rte_free(vsi);
3393
3394         return I40E_SUCCESS;
3395 }
3396
3397 static int
3398 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3399 {
3400         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3401         struct i40e_aqc_remove_macvlan_element_data def_filter;
3402         struct i40e_mac_filter_info filter;
3403         int ret;
3404
3405         if (vsi->type != I40E_VSI_MAIN)
3406                 return I40E_ERR_CONFIG;
3407         memset(&def_filter, 0, sizeof(def_filter));
3408         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3409                                         ETH_ADDR_LEN);
3410         def_filter.vlan_tag = 0;
3411         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3412                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3413         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3414         if (ret != I40E_SUCCESS) {
3415                 struct i40e_mac_filter *f;
3416                 struct ether_addr *mac;
3417
3418                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3419                             "macvlan filter");
3420                 /* It needs to add the permanent mac into mac list */
3421                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3422                 if (f == NULL) {
3423                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3424                         return I40E_ERR_NO_MEMORY;
3425                 }
3426                 mac = &f->mac_info.mac_addr;
3427                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3428                                 ETH_ADDR_LEN);
3429                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3430                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3431                 vsi->mac_num++;
3432
3433                 return ret;
3434         }
3435         (void)rte_memcpy(&filter.mac_addr,
3436                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3437         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3438         return i40e_vsi_add_mac(vsi, &filter);
3439 }
3440
3441 static int
3442 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3443 {
3444         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3445         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3446         struct i40e_hw *hw = &vsi->adapter->hw;
3447         i40e_status ret;
3448         int i;
3449
3450         memset(&bw_config, 0, sizeof(bw_config));
3451         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3452         if (ret != I40E_SUCCESS) {
3453                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3454                             hw->aq.asq_last_status);
3455                 return ret;
3456         }
3457
3458         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3459         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3460                                         &ets_sla_config, NULL);
3461         if (ret != I40E_SUCCESS) {
3462                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3463                             "configuration %u", hw->aq.asq_last_status);
3464                 return ret;
3465         }
3466
3467         /* Not store the info yet, just print out */
3468         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3469         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3470         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3471                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3472                             ets_sla_config.share_credits[i]);
3473                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3474                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3475                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3476                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3477                             (i * 4));
3478         }
3479
3480         return 0;
3481 }
3482
3483 /* Setup a VSI */
3484 struct i40e_vsi *
3485 i40e_vsi_setup(struct i40e_pf *pf,
3486                enum i40e_vsi_type type,
3487                struct i40e_vsi *uplink_vsi,
3488                uint16_t user_param)
3489 {
3490         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3491         struct i40e_vsi *vsi;
3492         struct i40e_mac_filter_info filter;
3493         int ret;
3494         struct i40e_vsi_context ctxt;
3495         struct ether_addr broadcast =
3496                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3497
3498         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3499                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3500                             "VSI link shouldn't be NULL");
3501                 return NULL;
3502         }
3503
3504         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3505                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3506                             "uplink VSI should be NULL");
3507                 return NULL;
3508         }
3509
3510         /* If uplink vsi didn't setup VEB, create one first */
3511         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3512                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3513
3514                 if (NULL == uplink_vsi->veb) {
3515                         PMD_DRV_LOG(ERR, "VEB setup failed");
3516                         return NULL;
3517                 }
3518         }
3519
3520         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3521         if (!vsi) {
3522                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3523                 return NULL;
3524         }
3525         TAILQ_INIT(&vsi->mac_list);
3526         vsi->type = type;
3527         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3528         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3529         vsi->parent_vsi = uplink_vsi;
3530         vsi->user_param = user_param;
3531         /* Allocate queues */
3532         switch (vsi->type) {
3533         case I40E_VSI_MAIN  :
3534                 vsi->nb_qps = pf->lan_nb_qps;
3535                 break;
3536         case I40E_VSI_SRIOV :
3537                 vsi->nb_qps = pf->vf_nb_qps;
3538                 break;
3539         case I40E_VSI_VMDQ2:
3540                 vsi->nb_qps = pf->vmdq_nb_qps;
3541                 break;
3542         case I40E_VSI_FDIR:
3543                 vsi->nb_qps = pf->fdir_nb_qps;
3544                 break;
3545         default:
3546                 goto fail_mem;
3547         }
3548         /*
3549          * The filter status descriptor is reported in rx queue 0,
3550          * while the tx queue for fdir filter programming has no
3551          * such constraints, can be non-zero queues.
3552          * To simplify it, choose FDIR vsi use queue 0 pair.
3553          * To make sure it will use queue 0 pair, queue allocation
3554          * need be done before this function is called
3555          */
3556         if (type != I40E_VSI_FDIR) {
3557                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3558                         if (ret < 0) {
3559                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3560                                                 vsi->seid, ret);
3561                                 goto fail_mem;
3562                         }
3563                         vsi->base_queue = ret;
3564         } else
3565                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3566
3567         /* VF has MSIX interrupt in VF range, don't allocate here */
3568         if (type != I40E_VSI_SRIOV) {
3569                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3570                 if (ret < 0) {
3571                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3572                         goto fail_queue_alloc;
3573                 }
3574                 vsi->msix_intr = ret;
3575         } else
3576                 vsi->msix_intr = 0;
3577         /* Add VSI */
3578         if (type == I40E_VSI_MAIN) {
3579                 /* For main VSI, no need to add since it's default one */
3580                 vsi->uplink_seid = pf->mac_seid;
3581                 vsi->seid = pf->main_vsi_seid;
3582                 /* Bind queues with specific MSIX interrupt */
3583                 /**
3584                  * Needs 2 interrupt at least, one for misc cause which will
3585                  * enabled from OS side, Another for queues binding the
3586                  * interrupt from device side only.
3587                  */
3588
3589                 /* Get default VSI parameters from hardware */
3590                 memset(&ctxt, 0, sizeof(ctxt));
3591                 ctxt.seid = vsi->seid;
3592                 ctxt.pf_num = hw->pf_id;
3593                 ctxt.uplink_seid = vsi->uplink_seid;
3594                 ctxt.vf_num = 0;
3595                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3596                 if (ret != I40E_SUCCESS) {
3597                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3598                         goto fail_msix_alloc;
3599                 }
3600                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3601                         sizeof(struct i40e_aqc_vsi_properties_data));
3602                 vsi->vsi_id = ctxt.vsi_number;
3603                 vsi->info.valid_sections = 0;
3604
3605                 /* Configure tc, enabled TC0 only */
3606                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3607                         I40E_SUCCESS) {
3608                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3609                         goto fail_msix_alloc;
3610                 }
3611
3612                 /* TC, queue mapping */
3613                 memset(&ctxt, 0, sizeof(ctxt));
3614                 vsi->info.valid_sections |=
3615                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3616                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3617                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3618                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3619                         sizeof(struct i40e_aqc_vsi_properties_data));
3620                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3621                                                 I40E_DEFAULT_TCMAP);
3622                 if (ret != I40E_SUCCESS) {
3623                         PMD_DRV_LOG(ERR, "Failed to configure "
3624                                     "TC queue mapping");
3625                         goto fail_msix_alloc;
3626                 }
3627                 ctxt.seid = vsi->seid;
3628                 ctxt.pf_num = hw->pf_id;
3629                 ctxt.uplink_seid = vsi->uplink_seid;
3630                 ctxt.vf_num = 0;
3631
3632                 /* Update VSI parameters */
3633                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3634                 if (ret != I40E_SUCCESS) {
3635                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3636                         goto fail_msix_alloc;
3637                 }
3638
3639                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3640                                                 sizeof(vsi->info.tc_mapping));
3641                 (void)rte_memcpy(&vsi->info.queue_mapping,
3642                                 &ctxt.info.queue_mapping,
3643                         sizeof(vsi->info.queue_mapping));
3644                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3645                 vsi->info.valid_sections = 0;
3646
3647                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3648                                 ETH_ADDR_LEN);
3649
3650                 /**
3651                  * Updating default filter settings are necessary to prevent
3652                  * reception of tagged packets.
3653                  * Some old firmware configurations load a default macvlan
3654                  * filter which accepts both tagged and untagged packets.
3655                  * The updating is to use a normal filter instead if needed.
3656                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3657                  * The firmware with correct configurations load the default
3658                  * macvlan filter which is expected and cannot be removed.
3659                  */
3660                 i40e_update_default_filter_setting(vsi);
3661                 i40e_config_qinq(hw, vsi);
3662         } else if (type == I40E_VSI_SRIOV) {
3663                 memset(&ctxt, 0, sizeof(ctxt));
3664                 /**
3665                  * For other VSI, the uplink_seid equals to uplink VSI's
3666                  * uplink_seid since they share same VEB
3667                  */
3668                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3669                 ctxt.pf_num = hw->pf_id;
3670                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3671                 ctxt.uplink_seid = vsi->uplink_seid;
3672                 ctxt.connection_type = 0x1;
3673                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3674
3675                 /**
3676                  * Do not configure switch ID to enable VEB switch by
3677                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3678                  * if the source mac address of packet sent from VF is not
3679                  * listed in the VEB's mac table, the VEB will switch the
3680                  * packet back to the VF. Need to enable it when HW issue
3681                  * is fixed.
3682                  */
3683
3684                 /* Configure port/vlan */
3685                 ctxt.info.valid_sections |=
3686                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3687                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3688                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3689                                                 I40E_DEFAULT_TCMAP);
3690                 if (ret != I40E_SUCCESS) {
3691                         PMD_DRV_LOG(ERR, "Failed to configure "
3692                                     "TC queue mapping");
3693                         goto fail_msix_alloc;
3694                 }
3695                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3696                 ctxt.info.valid_sections |=
3697                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3698                 /**
3699                  * Since VSI is not created yet, only configure parameter,
3700                  * will add vsi below.
3701                  */
3702
3703                 i40e_config_qinq(hw, vsi);
3704         } else if (type == I40E_VSI_VMDQ2) {
3705                 memset(&ctxt, 0, sizeof(ctxt));
3706                 /*
3707                  * For other VSI, the uplink_seid equals to uplink VSI's
3708                  * uplink_seid since they share same VEB
3709                  */
3710                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3711                 ctxt.pf_num = hw->pf_id;
3712                 ctxt.vf_num = 0;
3713                 ctxt.uplink_seid = vsi->uplink_seid;
3714                 ctxt.connection_type = 0x1;
3715                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3716
3717                 ctxt.info.valid_sections |=
3718                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3719                 /* user_param carries flag to enable loop back */
3720                 if (user_param) {
3721                         ctxt.info.switch_id =
3722                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3723                         ctxt.info.switch_id |=
3724                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3725                 }
3726
3727                 /* Configure port/vlan */
3728                 ctxt.info.valid_sections |=
3729                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3730                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3731                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3732                                                 I40E_DEFAULT_TCMAP);
3733                 if (ret != I40E_SUCCESS) {
3734                         PMD_DRV_LOG(ERR, "Failed to configure "
3735                                         "TC queue mapping");
3736                         goto fail_msix_alloc;
3737                 }
3738                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3739                 ctxt.info.valid_sections |=
3740                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3741         } else if (type == I40E_VSI_FDIR) {
3742                 memset(&ctxt, 0, sizeof(ctxt));
3743                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3744                 ctxt.pf_num = hw->pf_id;
3745                 ctxt.vf_num = 0;
3746                 ctxt.uplink_seid = vsi->uplink_seid;
3747                 ctxt.connection_type = 0x1;     /* regular data port */
3748                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3749                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3750                                                 I40E_DEFAULT_TCMAP);
3751                 if (ret != I40E_SUCCESS) {
3752                         PMD_DRV_LOG(ERR, "Failed to configure "
3753                                         "TC queue mapping.");
3754                         goto fail_msix_alloc;
3755                 }
3756                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3757                 ctxt.info.valid_sections |=
3758                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3759         } else {
3760                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3761                 goto fail_msix_alloc;
3762         }
3763
3764         if (vsi->type != I40E_VSI_MAIN) {
3765                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3766                 if (ret != I40E_SUCCESS) {
3767                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3768                                     hw->aq.asq_last_status);
3769                         goto fail_msix_alloc;
3770                 }
3771                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3772                 vsi->info.valid_sections = 0;
3773                 vsi->seid = ctxt.seid;
3774                 vsi->vsi_id = ctxt.vsi_number;
3775                 vsi->sib_vsi_list.vsi = vsi;
3776                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3777                                 &vsi->sib_vsi_list, list);
3778         }
3779
3780         /* MAC/VLAN configuration */
3781         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3782         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3783
3784         ret = i40e_vsi_add_mac(vsi, &filter);
3785         if (ret != I40E_SUCCESS) {
3786                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3787                 goto fail_msix_alloc;
3788         }
3789
3790         /* Get VSI BW information */
3791         i40e_vsi_dump_bw_config(vsi);
3792         return vsi;
3793 fail_msix_alloc:
3794         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3795 fail_queue_alloc:
3796         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3797 fail_mem:
3798         rte_free(vsi);
3799         return NULL;
3800 }
3801
3802 /* Configure vlan stripping on or off */
3803 int
3804 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3805 {
3806         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3807         struct i40e_vsi_context ctxt;
3808         uint8_t vlan_flags;
3809         int ret = I40E_SUCCESS;
3810
3811         /* Check if it has been already on or off */
3812         if (vsi->info.valid_sections &
3813                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3814                 if (on) {
3815                         if ((vsi->info.port_vlan_flags &
3816                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3817                                 return 0; /* already on */
3818                 } else {
3819                         if ((vsi->info.port_vlan_flags &
3820                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3821                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3822                                 return 0; /* already off */
3823                 }
3824         }
3825
3826         if (on)
3827                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3828         else
3829                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3830         vsi->info.valid_sections =
3831                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3832         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3833         vsi->info.port_vlan_flags |= vlan_flags;
3834         ctxt.seid = vsi->seid;
3835         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3836         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3837         if (ret)
3838                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3839                             on ? "enable" : "disable");
3840
3841         return ret;
3842 }
3843
3844 static int
3845 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3846 {
3847         struct rte_eth_dev_data *data = dev->data;
3848         int ret;
3849
3850         /* Apply vlan offload setting */
3851         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3852
3853         /* Apply double-vlan setting, not implemented yet */
3854
3855         /* Apply pvid setting */
3856         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3857                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3858         if (ret)
3859                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3860
3861         return ret;
3862 }
3863
3864 static int
3865 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3866 {
3867         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3868
3869         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3870 }
3871
3872 static int
3873 i40e_update_flow_control(struct i40e_hw *hw)
3874 {
3875 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3876         struct i40e_link_status link_status;
3877         uint32_t rxfc = 0, txfc = 0, reg;
3878         uint8_t an_info;
3879         int ret;
3880
3881         memset(&link_status, 0, sizeof(link_status));
3882         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3883         if (ret != I40E_SUCCESS) {
3884                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3885                 goto write_reg; /* Disable flow control */
3886         }
3887
3888         an_info = hw->phy.link_info.an_info;
3889         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3890                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3891                 ret = I40E_ERR_NOT_READY;
3892                 goto write_reg; /* Disable flow control */
3893         }
3894         /**
3895          * If link auto negotiation is enabled, flow control needs to
3896          * be configured according to it
3897          */
3898         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3899         case I40E_LINK_PAUSE_RXTX:
3900                 rxfc = 1;
3901                 txfc = 1;
3902                 hw->fc.current_mode = I40E_FC_FULL;
3903                 break;
3904         case I40E_AQ_LINK_PAUSE_RX:
3905                 rxfc = 1;
3906                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3907                 break;
3908         case I40E_AQ_LINK_PAUSE_TX:
3909                 txfc = 1;
3910                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3911                 break;
3912         default:
3913                 hw->fc.current_mode = I40E_FC_NONE;
3914                 break;
3915         }
3916
3917 write_reg:
3918         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3919                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3920         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3921         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3922         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3923         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3924
3925         return ret;
3926 }
3927
3928 /* PF setup */
3929 static int
3930 i40e_pf_setup(struct i40e_pf *pf)
3931 {
3932         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3933         struct i40e_filter_control_settings settings;
3934         struct i40e_vsi *vsi;
3935         int ret;
3936
3937         /* Clear all stats counters */
3938         pf->offset_loaded = FALSE;
3939         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3940         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3941
3942         ret = i40e_pf_get_switch_config(pf);
3943         if (ret != I40E_SUCCESS) {
3944                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3945                 return ret;
3946         }
3947         if (pf->flags & I40E_FLAG_FDIR) {
3948                 /* make queue allocated first, let FDIR use queue pair 0*/
3949                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3950                 if (ret != I40E_FDIR_QUEUE_ID) {
3951                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3952                                     " ret =%d", ret);
3953                         pf->flags &= ~I40E_FLAG_FDIR;
3954                 }
3955         }
3956         /*  main VSI setup */
3957         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3958         if (!vsi) {
3959                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3960                 return I40E_ERR_NOT_READY;
3961         }
3962         pf->main_vsi = vsi;
3963
3964         /* Configure filter control */
3965         memset(&settings, 0, sizeof(settings));
3966         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3967                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3968         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3969                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3970         else {
3971                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3972                                                 hw->func_caps.rss_table_size);
3973                 return I40E_ERR_PARAM;
3974         }
3975         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3976                         "size: %u\n", hw->func_caps.rss_table_size);
3977         pf->hash_lut_size = hw->func_caps.rss_table_size;
3978
3979         /* Enable ethtype and macvlan filters */
3980         settings.enable_ethtype = TRUE;
3981         settings.enable_macvlan = TRUE;
3982         ret = i40e_set_filter_control(hw, &settings);
3983         if (ret)
3984                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3985                                                                 ret);
3986
3987         /* Update flow control according to the auto negotiation */
3988         i40e_update_flow_control(hw);
3989
3990         return I40E_SUCCESS;
3991 }
3992
3993 int
3994 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3995 {
3996         uint32_t reg;
3997         uint16_t j;
3998
3999         /**
4000          * Set or clear TX Queue Disable flags,
4001          * which is required by hardware.
4002          */
4003         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4004         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4005
4006         /* Wait until the request is finished */
4007         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4008                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4009                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4010                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4011                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4012                                                         & 0x1))) {
4013                         break;
4014                 }
4015         }
4016         if (on) {
4017                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4018                         return I40E_SUCCESS; /* already on, skip next steps */
4019
4020                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4021                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4022         } else {
4023                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4024                         return I40E_SUCCESS; /* already off, skip next steps */
4025                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4026         }
4027         /* Write the register */
4028         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4029         /* Check the result */
4030         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4031                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4032                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4033                 if (on) {
4034                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4035                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4036                                 break;
4037                 } else {
4038                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4039                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4040                                 break;
4041                 }
4042         }
4043         /* Check if it is timeout */
4044         if (j >= I40E_CHK_Q_ENA_COUNT) {
4045                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4046                             (on ? "enable" : "disable"), q_idx);
4047                 return I40E_ERR_TIMEOUT;
4048         }
4049
4050         return I40E_SUCCESS;
4051 }
4052
4053 /* Swith on or off the tx queues */
4054 static int
4055 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4056 {
4057         struct rte_eth_dev_data *dev_data = pf->dev_data;
4058         struct i40e_tx_queue *txq;
4059         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4060         uint16_t i;
4061         int ret;
4062
4063         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4064                 txq = dev_data->tx_queues[i];
4065                 /* Don't operate the queue if not configured or
4066                  * if starting only per queue */
4067                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4068                         continue;
4069                 if (on)
4070                         ret = i40e_dev_tx_queue_start(dev, i);
4071                 else
4072                         ret = i40e_dev_tx_queue_stop(dev, i);
4073                 if ( ret != I40E_SUCCESS)
4074                         return ret;
4075         }
4076
4077         return I40E_SUCCESS;
4078 }
4079
4080 int
4081 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4082 {
4083         uint32_t reg;
4084         uint16_t j;
4085
4086         /* Wait until the request is finished */
4087         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4088                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4089                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4090                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4091                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4092                         break;
4093         }
4094
4095         if (on) {
4096                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4097                         return I40E_SUCCESS; /* Already on, skip next steps */
4098                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4099         } else {
4100                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4101                         return I40E_SUCCESS; /* Already off, skip next steps */
4102                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4103         }
4104
4105         /* Write the register */
4106         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4107         /* Check the result */
4108         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4109                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4110                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4111                 if (on) {
4112                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4113                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4114                                 break;
4115                 } else {
4116                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4117                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4118                                 break;
4119                 }
4120         }
4121
4122         /* Check if it is timeout */
4123         if (j >= I40E_CHK_Q_ENA_COUNT) {
4124                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4125                             (on ? "enable" : "disable"), q_idx);
4126                 return I40E_ERR_TIMEOUT;
4127         }
4128
4129         return I40E_SUCCESS;
4130 }
4131 /* Switch on or off the rx queues */
4132 static int
4133 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4134 {
4135         struct rte_eth_dev_data *dev_data = pf->dev_data;
4136         struct i40e_rx_queue *rxq;
4137         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4138         uint16_t i;
4139         int ret;
4140
4141         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4142                 rxq = dev_data->rx_queues[i];
4143                 /* Don't operate the queue if not configured or
4144                  * if starting only per queue */
4145                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4146                         continue;
4147                 if (on)
4148                         ret = i40e_dev_rx_queue_start(dev, i);
4149                 else
4150                         ret = i40e_dev_rx_queue_stop(dev, i);
4151                 if (ret != I40E_SUCCESS)
4152                         return ret;
4153         }
4154
4155         return I40E_SUCCESS;
4156 }
4157
4158 /* Switch on or off all the rx/tx queues */
4159 int
4160 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4161 {
4162         int ret;
4163
4164         if (on) {
4165                 /* enable rx queues before enabling tx queues */
4166                 ret = i40e_dev_switch_rx_queues(pf, on);
4167                 if (ret) {
4168                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4169                         return ret;
4170                 }
4171                 ret = i40e_dev_switch_tx_queues(pf, on);
4172         } else {
4173                 /* Stop tx queues before stopping rx queues */
4174                 ret = i40e_dev_switch_tx_queues(pf, on);
4175                 if (ret) {
4176                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4177                         return ret;
4178                 }
4179                 ret = i40e_dev_switch_rx_queues(pf, on);
4180         }
4181
4182         return ret;
4183 }
4184
4185 /* Initialize VSI for TX */
4186 static int
4187 i40e_dev_tx_init(struct i40e_pf *pf)
4188 {
4189         struct rte_eth_dev_data *data = pf->dev_data;
4190         uint16_t i;
4191         uint32_t ret = I40E_SUCCESS;
4192         struct i40e_tx_queue *txq;
4193
4194         for (i = 0; i < data->nb_tx_queues; i++) {
4195                 txq = data->tx_queues[i];
4196                 if (!txq || !txq->q_set)
4197                         continue;
4198                 ret = i40e_tx_queue_init(txq);
4199                 if (ret != I40E_SUCCESS)
4200                         break;
4201         }
4202         if (ret == I40E_SUCCESS)
4203                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4204                                      ->eth_dev);
4205
4206         return ret;
4207 }
4208
4209 /* Initialize VSI for RX */
4210 static int
4211 i40e_dev_rx_init(struct i40e_pf *pf)
4212 {
4213         struct rte_eth_dev_data *data = pf->dev_data;
4214         int ret = I40E_SUCCESS;
4215         uint16_t i;
4216         struct i40e_rx_queue *rxq;
4217
4218         i40e_pf_config_mq_rx(pf);
4219         for (i = 0; i < data->nb_rx_queues; i++) {
4220                 rxq = data->rx_queues[i];
4221                 if (!rxq || !rxq->q_set)
4222                         continue;
4223
4224                 ret = i40e_rx_queue_init(rxq);
4225                 if (ret != I40E_SUCCESS) {
4226                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4227                                     "initialization");
4228                         break;
4229                 }
4230         }
4231         if (ret == I40E_SUCCESS)
4232                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4233                                      ->eth_dev);
4234
4235         return ret;
4236 }
4237
4238 static int
4239 i40e_dev_rxtx_init(struct i40e_pf *pf)
4240 {
4241         int err;
4242
4243         err = i40e_dev_tx_init(pf);
4244         if (err) {
4245                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4246                 return err;
4247         }
4248         err = i40e_dev_rx_init(pf);
4249         if (err) {
4250                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4251                 return err;
4252         }
4253
4254         return err;
4255 }
4256
4257 static int
4258 i40e_vmdq_setup(struct rte_eth_dev *dev)
4259 {
4260         struct rte_eth_conf *conf = &dev->data->dev_conf;
4261         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4262         int i, err, conf_vsis, j, loop;
4263         struct i40e_vsi *vsi;
4264         struct i40e_vmdq_info *vmdq_info;
4265         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4266         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4267
4268         /*
4269          * Disable interrupt to avoid message from VF. Furthermore, it will
4270          * avoid race condition in VSI creation/destroy.
4271          */
4272         i40e_pf_disable_irq0(hw);
4273
4274         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4275                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4276                 return -ENOTSUP;
4277         }
4278
4279         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4280         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4281                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4282                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4283                         pf->max_nb_vmdq_vsi);
4284                 return -ENOTSUP;
4285         }
4286
4287         if (pf->vmdq != NULL) {
4288                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4289                 return 0;
4290         }
4291
4292         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4293                                 sizeof(*vmdq_info) * conf_vsis, 0);
4294
4295         if (pf->vmdq == NULL) {
4296                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4297                 return -ENOMEM;
4298         }
4299
4300         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4301
4302         /* Create VMDQ VSI */
4303         for (i = 0; i < conf_vsis; i++) {
4304                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4305                                 vmdq_conf->enable_loop_back);
4306                 if (vsi == NULL) {
4307                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4308                         err = -1;
4309                         goto err_vsi_setup;
4310                 }
4311                 vmdq_info = &pf->vmdq[i];
4312                 vmdq_info->pf = pf;
4313                 vmdq_info->vsi = vsi;
4314         }
4315         pf->nb_cfg_vmdq_vsi = conf_vsis;
4316
4317         /* Configure Vlan */
4318         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4319         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4320                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4321                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4322                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4323                                         vmdq_conf->pool_map[i].vlan_id, j);
4324
4325                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4326                                                 vmdq_conf->pool_map[i].vlan_id);
4327                                 if (err) {
4328                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4329                                         err = -1;
4330                                         goto err_vsi_setup;
4331                                 }
4332                         }
4333                 }
4334         }
4335
4336         i40e_pf_enable_irq0(hw);
4337
4338         return 0;
4339
4340 err_vsi_setup:
4341         for (i = 0; i < conf_vsis; i++)
4342                 if (pf->vmdq[i].vsi == NULL)
4343                         break;
4344                 else
4345                         i40e_vsi_release(pf->vmdq[i].vsi);
4346
4347         rte_free(pf->vmdq);
4348         pf->vmdq = NULL;
4349         i40e_pf_enable_irq0(hw);
4350         return err;
4351 }
4352
4353 static void
4354 i40e_stat_update_32(struct i40e_hw *hw,
4355                    uint32_t reg,
4356                    bool offset_loaded,
4357                    uint64_t *offset,
4358                    uint64_t *stat)
4359 {
4360         uint64_t new_data;
4361
4362         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4363         if (!offset_loaded)
4364                 *offset = new_data;
4365
4366         if (new_data >= *offset)
4367                 *stat = (uint64_t)(new_data - *offset);
4368         else
4369                 *stat = (uint64_t)((new_data +
4370                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4371 }
4372
4373 static void
4374 i40e_stat_update_48(struct i40e_hw *hw,
4375                    uint32_t hireg,
4376                    uint32_t loreg,
4377                    bool offset_loaded,
4378                    uint64_t *offset,
4379                    uint64_t *stat)
4380 {
4381         uint64_t new_data;
4382
4383         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4384         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4385                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4386
4387         if (!offset_loaded)
4388                 *offset = new_data;
4389
4390         if (new_data >= *offset)
4391                 *stat = new_data - *offset;
4392         else
4393                 *stat = (uint64_t)((new_data +
4394                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4395
4396         *stat &= I40E_48_BIT_MASK;
4397 }
4398
4399 /* Disable IRQ0 */
4400 void
4401 i40e_pf_disable_irq0(struct i40e_hw *hw)
4402 {
4403         /* Disable all interrupt types */
4404         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4405         I40E_WRITE_FLUSH(hw);
4406 }
4407
4408 /* Enable IRQ0 */
4409 void
4410 i40e_pf_enable_irq0(struct i40e_hw *hw)
4411 {
4412         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4413                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4414                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4415                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4416         I40E_WRITE_FLUSH(hw);
4417 }
4418
4419 static void
4420 i40e_pf_config_irq0(struct i40e_hw *hw)
4421 {
4422         /* read pending request and disable first */
4423         i40e_pf_disable_irq0(hw);
4424         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4425         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4426                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4427
4428         /* Link no queues with irq0 */
4429         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4430                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4431 }
4432
4433 static void
4434 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4435 {
4436         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4438         int i;
4439         uint16_t abs_vf_id;
4440         uint32_t index, offset, val;
4441
4442         if (!pf->vfs)
4443                 return;
4444         /**
4445          * Try to find which VF trigger a reset, use absolute VF id to access
4446          * since the reg is global register.
4447          */
4448         for (i = 0; i < pf->vf_num; i++) {
4449                 abs_vf_id = hw->func_caps.vf_base_id + i;
4450                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4451                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4452                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4453                 /* VFR event occured */
4454                 if (val & (0x1 << offset)) {
4455                         int ret;
4456
4457                         /* Clear the event first */
4458                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4459                                                         (0x1 << offset));
4460                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4461                         /**
4462                          * Only notify a VF reset event occured,
4463                          * don't trigger another SW reset
4464                          */
4465                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4466                         if (ret != I40E_SUCCESS)
4467                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4468                 }
4469         }
4470 }
4471
4472 static void
4473 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4474 {
4475         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4476         struct i40e_arq_event_info info;
4477         uint16_t pending, opcode;
4478         int ret;
4479
4480         info.buf_len = I40E_AQ_BUF_SZ;
4481         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4482         if (!info.msg_buf) {
4483                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4484                 return;
4485         }
4486
4487         pending = 1;
4488         while (pending) {
4489                 ret = i40e_clean_arq_element(hw, &info, &pending);
4490
4491                 if (ret != I40E_SUCCESS) {
4492                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4493                                     "aq_err: %u", hw->aq.asq_last_status);
4494                         break;
4495                 }
4496                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4497
4498                 switch (opcode) {
4499                 case i40e_aqc_opc_send_msg_to_pf:
4500                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4501                         i40e_pf_host_handle_vf_msg(dev,
4502                                         rte_le_to_cpu_16(info.desc.retval),
4503                                         rte_le_to_cpu_32(info.desc.cookie_high),
4504                                         rte_le_to_cpu_32(info.desc.cookie_low),
4505                                         info.msg_buf,
4506                                         info.msg_len);
4507                         break;
4508                 default:
4509                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4510                                     opcode);
4511                         break;
4512                 }
4513         }
4514         rte_free(info.msg_buf);
4515 }
4516
4517 /*
4518  * Interrupt handler is registered as the alarm callback for handling LSC
4519  * interrupt in a definite of time, in order to wait the NIC into a stable
4520  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4521  * no need for link down interrupt.
4522  */
4523 static void
4524 i40e_dev_interrupt_delayed_handler(void *param)
4525 {
4526         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4527         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4528         uint32_t icr0;
4529
4530         /* read interrupt causes again */
4531         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4532
4533 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4534         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4535                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4536         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4537                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4538         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4539                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4540         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4541                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4542         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4543                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4544                                                                 "state\n");
4545         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4546                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4547         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4548                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4549 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4550
4551         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4552                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4553                 i40e_dev_handle_vfr_event(dev);
4554         }
4555         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4556                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4557                 i40e_dev_handle_aq_msg(dev);
4558         }
4559
4560         /* handle the link up interrupt in an alarm callback */
4561         i40e_dev_link_update(dev, 0);
4562         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4563
4564         i40e_pf_enable_irq0(hw);
4565         rte_intr_enable(&(dev->pci_dev->intr_handle));
4566 }
4567
4568 /**
4569  * Interrupt handler triggered by NIC  for handling
4570  * specific interrupt.
4571  *
4572  * @param handle
4573  *  Pointer to interrupt handle.
4574  * @param param
4575  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4576  *
4577  * @return
4578  *  void
4579  */
4580 static void
4581 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4582                            void *param)
4583 {
4584         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4586         uint32_t icr0;
4587
4588         /* Disable interrupt */
4589         i40e_pf_disable_irq0(hw);
4590
4591         /* read out interrupt causes */
4592         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4593
4594         /* No interrupt event indicated */
4595         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4596                 PMD_DRV_LOG(INFO, "No interrupt event");
4597                 goto done;
4598         }
4599 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4600         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4601                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4602         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4603                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4604         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4605                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4606         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4607                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4608         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4609                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4610         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4611                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4612         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4613                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4614 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4615
4616         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4617                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4618                 i40e_dev_handle_vfr_event(dev);
4619         }
4620         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4621                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4622                 i40e_dev_handle_aq_msg(dev);
4623         }
4624
4625         /* Link Status Change interrupt */
4626         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4627 #define I40E_US_PER_SECOND 1000000
4628                 struct rte_eth_link link;
4629
4630                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4631                 memset(&link, 0, sizeof(link));
4632                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4633                 i40e_dev_link_update(dev, 0);
4634
4635                 /*
4636                  * For link up interrupt, it needs to wait 1 second to let the
4637                  * hardware be a stable state. Otherwise several consecutive
4638                  * interrupts can be observed.
4639                  * For link down interrupt, no need to wait.
4640                  */
4641                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4642                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4643                         return;
4644                 else
4645                         _rte_eth_dev_callback_process(dev,
4646                                 RTE_ETH_EVENT_INTR_LSC);
4647         }
4648
4649 done:
4650         /* Enable interrupt */
4651         i40e_pf_enable_irq0(hw);
4652         rte_intr_enable(&(dev->pci_dev->intr_handle));
4653 }
4654
4655 static int
4656 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4657                          struct i40e_macvlan_filter *filter,
4658                          int total)
4659 {
4660         int ele_num, ele_buff_size;
4661         int num, actual_num, i;
4662         uint16_t flags;
4663         int ret = I40E_SUCCESS;
4664         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4665         struct i40e_aqc_add_macvlan_element_data *req_list;
4666
4667         if (filter == NULL  || total == 0)
4668                 return I40E_ERR_PARAM;
4669         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4670         ele_buff_size = hw->aq.asq_buf_size;
4671
4672         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4673         if (req_list == NULL) {
4674                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4675                 return I40E_ERR_NO_MEMORY;
4676         }
4677
4678         num = 0;
4679         do {
4680                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4681                 memset(req_list, 0, ele_buff_size);
4682
4683                 for (i = 0; i < actual_num; i++) {
4684                         (void)rte_memcpy(req_list[i].mac_addr,
4685                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4686                         req_list[i].vlan_tag =
4687                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4688
4689                         switch (filter[num + i].filter_type) {
4690                         case RTE_MAC_PERFECT_MATCH:
4691                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4692                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4693                                 break;
4694                         case RTE_MACVLAN_PERFECT_MATCH:
4695                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4696                                 break;
4697                         case RTE_MAC_HASH_MATCH:
4698                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4699                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4700                                 break;
4701                         case RTE_MACVLAN_HASH_MATCH:
4702                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4703                                 break;
4704                         default:
4705                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4706                                 ret = I40E_ERR_PARAM;
4707                                 goto DONE;
4708                         }
4709
4710                         req_list[i].queue_number = 0;
4711
4712                         req_list[i].flags = rte_cpu_to_le_16(flags);
4713                 }
4714
4715                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4716                                                 actual_num, NULL);
4717                 if (ret != I40E_SUCCESS) {
4718                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4719                         goto DONE;
4720                 }
4721                 num += actual_num;
4722         } while (num < total);
4723
4724 DONE:
4725         rte_free(req_list);
4726         return ret;
4727 }
4728
4729 static int
4730 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4731                             struct i40e_macvlan_filter *filter,
4732                             int total)
4733 {
4734         int ele_num, ele_buff_size;
4735         int num, actual_num, i;
4736         uint16_t flags;
4737         int ret = I40E_SUCCESS;
4738         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4739         struct i40e_aqc_remove_macvlan_element_data *req_list;
4740
4741         if (filter == NULL  || total == 0)
4742                 return I40E_ERR_PARAM;
4743
4744         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4745         ele_buff_size = hw->aq.asq_buf_size;
4746
4747         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4748         if (req_list == NULL) {
4749                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4750                 return I40E_ERR_NO_MEMORY;
4751         }
4752
4753         num = 0;
4754         do {
4755                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4756                 memset(req_list, 0, ele_buff_size);
4757
4758                 for (i = 0; i < actual_num; i++) {
4759                         (void)rte_memcpy(req_list[i].mac_addr,
4760                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4761                         req_list[i].vlan_tag =
4762                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4763
4764                         switch (filter[num + i].filter_type) {
4765                         case RTE_MAC_PERFECT_MATCH:
4766                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4767                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4768                                 break;
4769                         case RTE_MACVLAN_PERFECT_MATCH:
4770                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4771                                 break;
4772                         case RTE_MAC_HASH_MATCH:
4773                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4774                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4775                                 break;
4776                         case RTE_MACVLAN_HASH_MATCH:
4777                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4778                                 break;
4779                         default:
4780                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4781                                 ret = I40E_ERR_PARAM;
4782                                 goto DONE;
4783                         }
4784                         req_list[i].flags = rte_cpu_to_le_16(flags);
4785                 }
4786
4787                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4788                                                 actual_num, NULL);
4789                 if (ret != I40E_SUCCESS) {
4790                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4791                         goto DONE;
4792                 }
4793                 num += actual_num;
4794         } while (num < total);
4795
4796 DONE:
4797         rte_free(req_list);
4798         return ret;
4799 }
4800
4801 /* Find out specific MAC filter */
4802 static struct i40e_mac_filter *
4803 i40e_find_mac_filter(struct i40e_vsi *vsi,
4804                          struct ether_addr *macaddr)
4805 {
4806         struct i40e_mac_filter *f;
4807
4808         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4809                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4810                         return f;
4811         }
4812
4813         return NULL;
4814 }
4815
4816 static bool
4817 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4818                          uint16_t vlan_id)
4819 {
4820         uint32_t vid_idx, vid_bit;
4821
4822         if (vlan_id > ETH_VLAN_ID_MAX)
4823                 return 0;
4824
4825         vid_idx = I40E_VFTA_IDX(vlan_id);
4826         vid_bit = I40E_VFTA_BIT(vlan_id);
4827
4828         if (vsi->vfta[vid_idx] & vid_bit)
4829                 return 1;
4830         else
4831                 return 0;
4832 }
4833
4834 static void
4835 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4836                          uint16_t vlan_id, bool on)
4837 {
4838         uint32_t vid_idx, vid_bit;
4839
4840         if (vlan_id > ETH_VLAN_ID_MAX)
4841                 return;
4842
4843         vid_idx = I40E_VFTA_IDX(vlan_id);
4844         vid_bit = I40E_VFTA_BIT(vlan_id);
4845
4846         if (on)
4847                 vsi->vfta[vid_idx] |= vid_bit;
4848         else
4849                 vsi->vfta[vid_idx] &= ~vid_bit;
4850 }
4851
4852 /**
4853  * Find all vlan options for specific mac addr,
4854  * return with actual vlan found.
4855  */
4856 static inline int
4857 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4858                            struct i40e_macvlan_filter *mv_f,
4859                            int num, struct ether_addr *addr)
4860 {
4861         int i;
4862         uint32_t j, k;
4863
4864         /**
4865          * Not to use i40e_find_vlan_filter to decrease the loop time,
4866          * although the code looks complex.
4867           */
4868         if (num < vsi->vlan_num)
4869                 return I40E_ERR_PARAM;
4870
4871         i = 0;
4872         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4873                 if (vsi->vfta[j]) {
4874                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4875                                 if (vsi->vfta[j] & (1 << k)) {
4876                                         if (i > num - 1) {
4877                                                 PMD_DRV_LOG(ERR, "vlan number "
4878                                                             "not match");
4879                                                 return I40E_ERR_PARAM;
4880                                         }
4881                                         (void)rte_memcpy(&mv_f[i].macaddr,
4882                                                         addr, ETH_ADDR_LEN);
4883                                         mv_f[i].vlan_id =
4884                                                 j * I40E_UINT32_BIT_SIZE + k;
4885                                         i++;
4886                                 }
4887                         }
4888                 }
4889         }
4890         return I40E_SUCCESS;
4891 }
4892
4893 static inline int
4894 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4895                            struct i40e_macvlan_filter *mv_f,
4896                            int num,
4897                            uint16_t vlan)
4898 {
4899         int i = 0;
4900         struct i40e_mac_filter *f;
4901
4902         if (num < vsi->mac_num)
4903                 return I40E_ERR_PARAM;
4904
4905         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4906                 if (i > num - 1) {
4907                         PMD_DRV_LOG(ERR, "buffer number not match");
4908                         return I40E_ERR_PARAM;
4909                 }
4910                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4911                                 ETH_ADDR_LEN);
4912                 mv_f[i].vlan_id = vlan;
4913                 mv_f[i].filter_type = f->mac_info.filter_type;
4914                 i++;
4915         }
4916
4917         return I40E_SUCCESS;
4918 }
4919
4920 static int
4921 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4922 {
4923         int i, num;
4924         struct i40e_mac_filter *f;
4925         struct i40e_macvlan_filter *mv_f;
4926         int ret = I40E_SUCCESS;
4927
4928         if (vsi == NULL || vsi->mac_num == 0)
4929                 return I40E_ERR_PARAM;
4930
4931         /* Case that no vlan is set */
4932         if (vsi->vlan_num == 0)
4933                 num = vsi->mac_num;
4934         else
4935                 num = vsi->mac_num * vsi->vlan_num;
4936
4937         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4938         if (mv_f == NULL) {
4939                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4940                 return I40E_ERR_NO_MEMORY;
4941         }
4942
4943         i = 0;
4944         if (vsi->vlan_num == 0) {
4945                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4946                         (void)rte_memcpy(&mv_f[i].macaddr,
4947                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4948                         mv_f[i].vlan_id = 0;
4949                         i++;
4950                 }
4951         } else {
4952                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4953                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4954                                         vsi->vlan_num, &f->mac_info.mac_addr);
4955                         if (ret != I40E_SUCCESS)
4956                                 goto DONE;
4957                         i += vsi->vlan_num;
4958                 }
4959         }
4960
4961         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4962 DONE:
4963         rte_free(mv_f);
4964
4965         return ret;
4966 }
4967
4968 int
4969 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4970 {
4971         struct i40e_macvlan_filter *mv_f;
4972         int mac_num;
4973         int ret = I40E_SUCCESS;
4974
4975         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4976                 return I40E_ERR_PARAM;
4977
4978         /* If it's already set, just return */
4979         if (i40e_find_vlan_filter(vsi,vlan))
4980                 return I40E_SUCCESS;
4981
4982         mac_num = vsi->mac_num;
4983
4984         if (mac_num == 0) {
4985                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4986                 return I40E_ERR_PARAM;
4987         }
4988
4989         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4990
4991         if (mv_f == NULL) {
4992                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4993                 return I40E_ERR_NO_MEMORY;
4994         }
4995
4996         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4997
4998         if (ret != I40E_SUCCESS)
4999                 goto DONE;
5000
5001         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5002
5003         if (ret != I40E_SUCCESS)
5004                 goto DONE;
5005
5006         i40e_set_vlan_filter(vsi, vlan, 1);
5007
5008         vsi->vlan_num++;
5009         ret = I40E_SUCCESS;
5010 DONE:
5011         rte_free(mv_f);
5012         return ret;
5013 }
5014
5015 int
5016 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5017 {
5018         struct i40e_macvlan_filter *mv_f;
5019         int mac_num;
5020         int ret = I40E_SUCCESS;
5021
5022         /**
5023          * Vlan 0 is the generic filter for untagged packets
5024          * and can't be removed.
5025          */
5026         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5027                 return I40E_ERR_PARAM;
5028
5029         /* If can't find it, just return */
5030         if (!i40e_find_vlan_filter(vsi, vlan))
5031                 return I40E_ERR_PARAM;
5032
5033         mac_num = vsi->mac_num;
5034
5035         if (mac_num == 0) {
5036                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5037                 return I40E_ERR_PARAM;
5038         }
5039
5040         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5041
5042         if (mv_f == NULL) {
5043                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5044                 return I40E_ERR_NO_MEMORY;
5045         }
5046
5047         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5048
5049         if (ret != I40E_SUCCESS)
5050                 goto DONE;
5051
5052         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5053
5054         if (ret != I40E_SUCCESS)
5055                 goto DONE;
5056
5057         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5058         if (vsi->vlan_num == 1) {
5059                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5060                 if (ret != I40E_SUCCESS)
5061                         goto DONE;
5062
5063                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5064                 if (ret != I40E_SUCCESS)
5065                         goto DONE;
5066         }
5067
5068         i40e_set_vlan_filter(vsi, vlan, 0);
5069
5070         vsi->vlan_num--;
5071         ret = I40E_SUCCESS;
5072 DONE:
5073         rte_free(mv_f);
5074         return ret;
5075 }
5076
5077 int
5078 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5079 {
5080         struct i40e_mac_filter *f;
5081         struct i40e_macvlan_filter *mv_f;
5082         int i, vlan_num = 0;
5083         int ret = I40E_SUCCESS;
5084
5085         /* If it's add and we've config it, return */
5086         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5087         if (f != NULL)
5088                 return I40E_SUCCESS;
5089         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5090                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5091
5092                 /**
5093                  * If vlan_num is 0, that's the first time to add mac,
5094                  * set mask for vlan_id 0.
5095                  */
5096                 if (vsi->vlan_num == 0) {
5097                         i40e_set_vlan_filter(vsi, 0, 1);
5098                         vsi->vlan_num = 1;
5099                 }
5100                 vlan_num = vsi->vlan_num;
5101         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5102                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5103                 vlan_num = 1;
5104
5105         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5106         if (mv_f == NULL) {
5107                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5108                 return I40E_ERR_NO_MEMORY;
5109         }
5110
5111         for (i = 0; i < vlan_num; i++) {
5112                 mv_f[i].filter_type = mac_filter->filter_type;
5113                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5114                                 ETH_ADDR_LEN);
5115         }
5116
5117         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5118                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5119                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5120                                         &mac_filter->mac_addr);
5121                 if (ret != I40E_SUCCESS)
5122                         goto DONE;
5123         }
5124
5125         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5126         if (ret != I40E_SUCCESS)
5127                 goto DONE;
5128
5129         /* Add the mac addr into mac list */
5130         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5131         if (f == NULL) {
5132                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5133                 ret = I40E_ERR_NO_MEMORY;
5134                 goto DONE;
5135         }
5136         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5137                         ETH_ADDR_LEN);
5138         f->mac_info.filter_type = mac_filter->filter_type;
5139         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5140         vsi->mac_num++;
5141
5142         ret = I40E_SUCCESS;
5143 DONE:
5144         rte_free(mv_f);
5145
5146         return ret;
5147 }
5148
5149 int
5150 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5151 {
5152         struct i40e_mac_filter *f;
5153         struct i40e_macvlan_filter *mv_f;
5154         int i, vlan_num;
5155         enum rte_mac_filter_type filter_type;
5156         int ret = I40E_SUCCESS;
5157
5158         /* Can't find it, return an error */
5159         f = i40e_find_mac_filter(vsi, addr);
5160         if (f == NULL)
5161                 return I40E_ERR_PARAM;
5162
5163         vlan_num = vsi->vlan_num;
5164         filter_type = f->mac_info.filter_type;
5165         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5166                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5167                 if (vlan_num == 0) {
5168                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5169                         return I40E_ERR_PARAM;
5170                 }
5171         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5172                         filter_type == RTE_MAC_HASH_MATCH)
5173                 vlan_num = 1;
5174
5175         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5176         if (mv_f == NULL) {
5177                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5178                 return I40E_ERR_NO_MEMORY;
5179         }
5180
5181         for (i = 0; i < vlan_num; i++) {
5182                 mv_f[i].filter_type = filter_type;
5183                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5184                                 ETH_ADDR_LEN);
5185         }
5186         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5187                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5188                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5189                 if (ret != I40E_SUCCESS)
5190                         goto DONE;
5191         }
5192
5193         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5194         if (ret != I40E_SUCCESS)
5195                 goto DONE;
5196
5197         /* Remove the mac addr into mac list */
5198         TAILQ_REMOVE(&vsi->mac_list, f, next);
5199         rte_free(f);
5200         vsi->mac_num--;
5201
5202         ret = I40E_SUCCESS;
5203 DONE:
5204         rte_free(mv_f);
5205         return ret;
5206 }
5207
5208 /* Configure hash enable flags for RSS */
5209 uint64_t
5210 i40e_config_hena(uint64_t flags)
5211 {
5212         uint64_t hena = 0;
5213
5214         if (!flags)
5215                 return hena;
5216
5217         if (flags & ETH_RSS_FRAG_IPV4)
5218                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5219         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5220                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5221         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5222                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5223         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5224                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5225         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5226                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5227         if (flags & ETH_RSS_FRAG_IPV6)
5228                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5229         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5230                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5231         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5232                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5233         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5234                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5235         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5236                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5237         if (flags & ETH_RSS_L2_PAYLOAD)
5238                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5239
5240         return hena;
5241 }
5242
5243 /* Parse the hash enable flags */
5244 uint64_t
5245 i40e_parse_hena(uint64_t flags)
5246 {
5247         uint64_t rss_hf = 0;
5248
5249         if (!flags)
5250                 return rss_hf;
5251         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5252                 rss_hf |= ETH_RSS_FRAG_IPV4;
5253         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5254                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5255         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5256                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5257         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5258                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5259         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5260                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5261         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5262                 rss_hf |= ETH_RSS_FRAG_IPV6;
5263         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5264                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5265         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5266                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5267         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5268                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5269         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5270                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5271         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5272                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5273
5274         return rss_hf;
5275 }
5276
5277 /* Disable RSS */
5278 static void
5279 i40e_pf_disable_rss(struct i40e_pf *pf)
5280 {
5281         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5282         uint64_t hena;
5283
5284         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5285         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5286         hena &= ~I40E_RSS_HENA_ALL;
5287         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5288         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5289         I40E_WRITE_FLUSH(hw);
5290 }
5291
5292 static int
5293 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5294 {
5295         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5296         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5297         int ret = 0;
5298
5299         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5300                 sizeof(uint32_t)))
5301                 return -EINVAL;
5302
5303         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5304                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5305                         (struct i40e_aqc_get_set_rss_key_data *)key;
5306
5307                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5308                 if (ret)
5309                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5310                                      "via AQ");
5311         } else {
5312                 uint32_t *hash_key = (uint32_t *)key;
5313                 uint16_t i;
5314
5315                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5316                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5317                 I40E_WRITE_FLUSH(hw);
5318         }
5319
5320         return ret;
5321 }
5322
5323 static int
5324 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5325 {
5326         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5327         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5328         int ret;
5329
5330         if (!key || !key_len)
5331                 return -EINVAL;
5332
5333         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5334                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5335                         (struct i40e_aqc_get_set_rss_key_data *)key);
5336                 if (ret) {
5337                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5338                         return ret;
5339                 }
5340         } else {
5341                 uint32_t *key_dw = (uint32_t *)key;
5342                 uint16_t i;
5343
5344                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5345                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5346         }
5347         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5348
5349         return 0;
5350 }
5351
5352 static int
5353 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5354 {
5355         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5356         uint64_t rss_hf;
5357         uint64_t hena;
5358         int ret;
5359
5360         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5361                                rss_conf->rss_key_len);
5362         if (ret)
5363                 return ret;
5364
5365         rss_hf = rss_conf->rss_hf;
5366         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5367         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5368         hena &= ~I40E_RSS_HENA_ALL;
5369         hena |= i40e_config_hena(rss_hf);
5370         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5371         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5372         I40E_WRITE_FLUSH(hw);
5373
5374         return 0;
5375 }
5376
5377 static int
5378 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5379                          struct rte_eth_rss_conf *rss_conf)
5380 {
5381         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5382         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5383         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5384         uint64_t hena;
5385
5386         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5387         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5388         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5389                 if (rss_hf != 0) /* Enable RSS */
5390                         return -EINVAL;
5391                 return 0; /* Nothing to do */
5392         }
5393         /* RSS enabled */
5394         if (rss_hf == 0) /* Disable RSS */
5395                 return -EINVAL;
5396
5397         return i40e_hw_rss_hash_set(pf, rss_conf);
5398 }
5399
5400 static int
5401 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5402                            struct rte_eth_rss_conf *rss_conf)
5403 {
5404         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5405         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406         uint64_t hena;
5407
5408         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5409                          &rss_conf->rss_key_len);
5410
5411         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5412         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5413         rss_conf->rss_hf = i40e_parse_hena(hena);
5414
5415         return 0;
5416 }
5417
5418 static int
5419 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5420 {
5421         switch (filter_type) {
5422         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5423                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5424                 break;
5425         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5426                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5427                 break;
5428         case RTE_TUNNEL_FILTER_IMAC_TENID:
5429                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5430                 break;
5431         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5432                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5433                 break;
5434         case ETH_TUNNEL_FILTER_IMAC:
5435                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5436                 break;
5437         default:
5438                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5439                 return -EINVAL;
5440         }
5441
5442         return 0;
5443 }
5444
5445 static int
5446 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5447                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5448                         uint8_t add)
5449 {
5450         uint16_t ip_type;
5451         uint8_t tun_type = 0;
5452         int val, ret = 0;
5453         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5454         struct i40e_vsi *vsi = pf->main_vsi;
5455         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5456         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5457
5458         cld_filter = rte_zmalloc("tunnel_filter",
5459                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5460                 0);
5461
5462         if (NULL == cld_filter) {
5463                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5464                 return -EINVAL;
5465         }
5466         pfilter = cld_filter;
5467
5468         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5469                         sizeof(struct ether_addr));
5470         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5471                         sizeof(struct ether_addr));
5472
5473         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5474         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5475                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5476                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5477                                 &tunnel_filter->ip_addr,
5478                                 sizeof(pfilter->ipaddr.v4.data));
5479         } else {
5480                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5481                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5482                                 &tunnel_filter->ip_addr,
5483                                 sizeof(pfilter->ipaddr.v6.data));
5484         }
5485
5486         /* check tunneled type */
5487         switch (tunnel_filter->tunnel_type) {
5488         case RTE_TUNNEL_TYPE_VXLAN:
5489                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5490                 break;
5491         case RTE_TUNNEL_TYPE_NVGRE:
5492                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5493                 break;
5494         default:
5495                 /* Other tunnel types is not supported. */
5496                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5497                 rte_free(cld_filter);
5498                 return -EINVAL;
5499         }
5500
5501         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5502                                                 &pfilter->flags);
5503         if (val < 0) {
5504                 rte_free(cld_filter);
5505                 return -EINVAL;
5506         }
5507
5508         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5509                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5510         pfilter->tenant_id = tunnel_filter->tenant_id;
5511         pfilter->queue_number = tunnel_filter->queue_id;
5512
5513         if (add)
5514                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5515         else
5516                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5517                                                 cld_filter, 1);
5518
5519         rte_free(cld_filter);
5520         return ret;
5521 }
5522
5523 static int
5524 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5525 {
5526         uint8_t i;
5527
5528         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5529                 if (pf->vxlan_ports[i] == port)
5530                         return i;
5531         }
5532
5533         return -1;
5534 }
5535
5536 static int
5537 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5538 {
5539         int  idx, ret;
5540         uint8_t filter_idx;
5541         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5542
5543         idx = i40e_get_vxlan_port_idx(pf, port);
5544
5545         /* Check if port already exists */
5546         if (idx >= 0) {
5547                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5548                 return -EINVAL;
5549         }
5550
5551         /* Now check if there is space to add the new port */
5552         idx = i40e_get_vxlan_port_idx(pf, 0);
5553         if (idx < 0) {
5554                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5555                         "not adding port %d", port);
5556                 return -ENOSPC;
5557         }
5558
5559         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5560                                         &filter_idx, NULL);
5561         if (ret < 0) {
5562                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5563                 return -1;
5564         }
5565
5566         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5567                          port,  filter_idx);
5568
5569         /* New port: add it and mark its index in the bitmap */
5570         pf->vxlan_ports[idx] = port;
5571         pf->vxlan_bitmap |= (1 << idx);
5572
5573         if (!(pf->flags & I40E_FLAG_VXLAN))
5574                 pf->flags |= I40E_FLAG_VXLAN;
5575
5576         return 0;
5577 }
5578
5579 static int
5580 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5581 {
5582         int idx;
5583         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5584
5585         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5586                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5587                 return -EINVAL;
5588         }
5589
5590         idx = i40e_get_vxlan_port_idx(pf, port);
5591
5592         if (idx < 0) {
5593                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5594                 return -EINVAL;
5595         }
5596
5597         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5598                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5599                 return -1;
5600         }
5601
5602         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5603                         port, idx);
5604
5605         pf->vxlan_ports[idx] = 0;
5606         pf->vxlan_bitmap &= ~(1 << idx);
5607
5608         if (!pf->vxlan_bitmap)
5609                 pf->flags &= ~I40E_FLAG_VXLAN;
5610
5611         return 0;
5612 }
5613
5614 /* Add UDP tunneling port */
5615 static int
5616 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5617                         struct rte_eth_udp_tunnel *udp_tunnel)
5618 {
5619         int ret = 0;
5620         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5621
5622         if (udp_tunnel == NULL)
5623                 return -EINVAL;
5624
5625         switch (udp_tunnel->prot_type) {
5626         case RTE_TUNNEL_TYPE_VXLAN:
5627                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5628                 break;
5629
5630         case RTE_TUNNEL_TYPE_GENEVE:
5631         case RTE_TUNNEL_TYPE_TEREDO:
5632                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5633                 ret = -1;
5634                 break;
5635
5636         default:
5637                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5638                 ret = -1;
5639                 break;
5640         }
5641
5642         return ret;
5643 }
5644
5645 /* Remove UDP tunneling port */
5646 static int
5647 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5648                         struct rte_eth_udp_tunnel *udp_tunnel)
5649 {
5650         int ret = 0;
5651         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5652
5653         if (udp_tunnel == NULL)
5654                 return -EINVAL;
5655
5656         switch (udp_tunnel->prot_type) {
5657         case RTE_TUNNEL_TYPE_VXLAN:
5658                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5659                 break;
5660         case RTE_TUNNEL_TYPE_GENEVE:
5661         case RTE_TUNNEL_TYPE_TEREDO:
5662                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5663                 ret = -1;
5664                 break;
5665         default:
5666                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5667                 ret = -1;
5668                 break;
5669         }
5670
5671         return ret;
5672 }
5673
5674 /* Calculate the maximum number of contiguous PF queues that are configured */
5675 static int
5676 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5677 {
5678         struct rte_eth_dev_data *data = pf->dev_data;
5679         int i, num;
5680         struct i40e_rx_queue *rxq;
5681
5682         num = 0;
5683         for (i = 0; i < pf->lan_nb_qps; i++) {
5684                 rxq = data->rx_queues[i];
5685                 if (rxq && rxq->q_set)
5686                         num++;
5687                 else
5688                         break;
5689         }
5690
5691         return num;
5692 }
5693
5694 /* Configure RSS */
5695 static int
5696 i40e_pf_config_rss(struct i40e_pf *pf)
5697 {
5698         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5699         struct rte_eth_rss_conf rss_conf;
5700         uint32_t i, lut = 0;
5701         uint16_t j, num;
5702
5703         /*
5704          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5705          * It's necessary to calulate the actual PF queues that are configured.
5706          */
5707         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
5708                 num = i40e_pf_calc_configured_queues_num(pf);
5709         else
5710                 num = pf->dev_data->nb_rx_queues;
5711
5712         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
5713         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5714                         num);
5715
5716         if (num == 0) {
5717                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5718                 return -ENOTSUP;
5719         }
5720
5721         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5722                 if (j == num)
5723                         j = 0;
5724                 lut = (lut << 8) | (j & ((0x1 <<
5725                         hw->func_caps.rss_table_entry_width) - 1));
5726                 if ((i & 3) == 3)
5727                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5728         }
5729
5730         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5731         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5732                 i40e_pf_disable_rss(pf);
5733                 return 0;
5734         }
5735         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5736                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5737                 /* Random default keys */
5738                 static uint32_t rss_key_default[] = {0x6b793944,
5739                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5740                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5741                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5742
5743                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5744                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5745                                                         sizeof(uint32_t);
5746         }
5747
5748         return i40e_hw_rss_hash_set(pf, &rss_conf);
5749 }
5750
5751 static int
5752 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5753                         struct rte_eth_tunnel_filter_conf *filter)
5754 {
5755         if (pf == NULL || filter == NULL) {
5756                 PMD_DRV_LOG(ERR, "Invalid parameter");
5757                 return -EINVAL;
5758         }
5759
5760         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5761                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5762                 return -EINVAL;
5763         }
5764
5765         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5766                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5767                 return -EINVAL;
5768         }
5769
5770         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5771                 (is_zero_ether_addr(filter->outer_mac))) {
5772                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5773                 return -EINVAL;
5774         }
5775
5776         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5777                 (is_zero_ether_addr(filter->inner_mac))) {
5778                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5779                 return -EINVAL;
5780         }
5781
5782         return 0;
5783 }
5784
5785 static int
5786 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5787                         void *arg)
5788 {
5789         struct rte_eth_tunnel_filter_conf *filter;
5790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5791         int ret = I40E_SUCCESS;
5792
5793         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5794
5795         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5796                 return I40E_ERR_PARAM;
5797
5798         switch (filter_op) {
5799         case RTE_ETH_FILTER_NOP:
5800                 if (!(pf->flags & I40E_FLAG_VXLAN))
5801                         ret = I40E_NOT_SUPPORTED;
5802         case RTE_ETH_FILTER_ADD:
5803                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5804                 break;
5805         case RTE_ETH_FILTER_DELETE:
5806                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5807                 break;
5808         default:
5809                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5810                 ret = I40E_ERR_PARAM;
5811                 break;
5812         }
5813
5814         return ret;
5815 }
5816
5817 static int
5818 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5819 {
5820         int ret = 0;
5821         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5822
5823         /* RSS setup */
5824         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5825                 ret = i40e_pf_config_rss(pf);
5826         else
5827                 i40e_pf_disable_rss(pf);
5828
5829         return ret;
5830 }
5831
5832 /* Get the symmetric hash enable configurations per port */
5833 static void
5834 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5835 {
5836         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5837
5838         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5839 }
5840
5841 /* Set the symmetric hash enable configurations per port */
5842 static void
5843 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5844 {
5845         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5846
5847         if (enable > 0) {
5848                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5849                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5850                                                         "been enabled");
5851                         return;
5852                 }
5853                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5854         } else {
5855                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5856                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5857                                                         "been disabled");
5858                         return;
5859                 }
5860                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5861         }
5862         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5863         I40E_WRITE_FLUSH(hw);
5864 }
5865
5866 /*
5867  * Get global configurations of hash function type and symmetric hash enable
5868  * per flow type (pctype). Note that global configuration means it affects all
5869  * the ports on the same NIC.
5870  */
5871 static int
5872 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5873                                    struct rte_eth_hash_global_conf *g_cfg)
5874 {
5875         uint32_t reg, mask = I40E_FLOW_TYPES;
5876         uint16_t i;
5877         enum i40e_filter_pctype pctype;
5878
5879         memset(g_cfg, 0, sizeof(*g_cfg));
5880         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5881         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5882                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5883         else
5884                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5885         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5886                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5887
5888         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5889                 if (!(mask & (1UL << i)))
5890                         continue;
5891                 mask &= ~(1UL << i);
5892                 /* Bit set indicats the coresponding flow type is supported */
5893                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5894                 pctype = i40e_flowtype_to_pctype(i);
5895                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5896                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5897                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5898         }
5899
5900         return 0;
5901 }
5902
5903 static int
5904 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5905 {
5906         uint32_t i;
5907         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5908
5909         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5910                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5911                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5912                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5913                                                 g_cfg->hash_func);
5914                 return -EINVAL;
5915         }
5916
5917         /*
5918          * As i40e supports less than 32 flow types, only first 32 bits need to
5919          * be checked.
5920          */
5921         mask0 = g_cfg->valid_bit_mask[0];
5922         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5923                 if (i == 0) {
5924                         /* Check if any unsupported flow type configured */
5925                         if ((mask0 | i40e_mask) ^ i40e_mask)
5926                                 goto mask_err;
5927                 } else {
5928                         if (g_cfg->valid_bit_mask[i])
5929                                 goto mask_err;
5930                 }
5931         }
5932
5933         return 0;
5934
5935 mask_err:
5936         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5937
5938         return -EINVAL;
5939 }
5940
5941 /*
5942  * Set global configurations of hash function type and symmetric hash enable
5943  * per flow type (pctype). Note any modifying global configuration will affect
5944  * all the ports on the same NIC.
5945  */
5946 static int
5947 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5948                                    struct rte_eth_hash_global_conf *g_cfg)
5949 {
5950         int ret;
5951         uint16_t i;
5952         uint32_t reg;
5953         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5954         enum i40e_filter_pctype pctype;
5955
5956         /* Check the input parameters */
5957         ret = i40e_hash_global_config_check(g_cfg);
5958         if (ret < 0)
5959                 return ret;
5960
5961         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5962                 if (!(mask0 & (1UL << i)))
5963                         continue;
5964                 mask0 &= ~(1UL << i);
5965                 pctype = i40e_flowtype_to_pctype(i);
5966                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5967                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5968                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5969         }
5970
5971         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5972         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5973                 /* Toeplitz */
5974                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5975                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5976                                                                 "Toeplitz");
5977                         goto out;
5978                 }
5979                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5980         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5981                 /* Simple XOR */
5982                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5983                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5984                                                         "Simple XOR");
5985                         goto out;
5986                 }
5987                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5988         } else
5989                 /* Use the default, and keep it as it is */
5990                 goto out;
5991
5992         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5993
5994 out:
5995         I40E_WRITE_FLUSH(hw);
5996
5997         return 0;
5998 }
5999
6000 static int
6001 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6002 {
6003         int ret = 0;
6004
6005         if (!hw || !info) {
6006                 PMD_DRV_LOG(ERR, "Invalid pointer");
6007                 return -EFAULT;
6008         }
6009
6010         switch (info->info_type) {
6011         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6012                 i40e_get_symmetric_hash_enable_per_port(hw,
6013                                         &(info->info.enable));
6014                 break;
6015         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6016                 ret = i40e_get_hash_filter_global_config(hw,
6017                                 &(info->info.global_conf));
6018                 break;
6019         default:
6020                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6021                                                         info->info_type);
6022                 ret = -EINVAL;
6023                 break;
6024         }
6025
6026         return ret;
6027 }
6028
6029 static int
6030 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6031 {
6032         int ret = 0;
6033
6034         if (!hw || !info) {
6035                 PMD_DRV_LOG(ERR, "Invalid pointer");
6036                 return -EFAULT;
6037         }
6038
6039         switch (info->info_type) {
6040         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6041                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
6042                 break;
6043         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6044                 ret = i40e_set_hash_filter_global_config(hw,
6045                                 &(info->info.global_conf));
6046                 break;
6047         default:
6048                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6049                                                         info->info_type);
6050                 ret = -EINVAL;
6051                 break;
6052         }
6053
6054         return ret;
6055 }
6056
6057 /* Operations for hash function */
6058 static int
6059 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
6060                       enum rte_filter_op filter_op,
6061                       void *arg)
6062 {
6063         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6064         int ret = 0;
6065
6066         switch (filter_op) {
6067         case RTE_ETH_FILTER_NOP:
6068                 break;
6069         case RTE_ETH_FILTER_GET:
6070                 ret = i40e_hash_filter_get(hw,
6071                         (struct rte_eth_hash_filter_info *)arg);
6072                 break;
6073         case RTE_ETH_FILTER_SET:
6074                 ret = i40e_hash_filter_set(hw,
6075                         (struct rte_eth_hash_filter_info *)arg);
6076                 break;
6077         default:
6078                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
6079                                                                 filter_op);
6080                 ret = -ENOTSUP;
6081                 break;
6082         }
6083
6084         return ret;
6085 }
6086
6087 /*
6088  * Configure ethertype filter, which can director packet by filtering
6089  * with mac address and ether_type or only ether_type
6090  */
6091 static int
6092 i40e_ethertype_filter_set(struct i40e_pf *pf,
6093                         struct rte_eth_ethertype_filter *filter,
6094                         bool add)
6095 {
6096         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6097         struct i40e_control_filter_stats stats;
6098         uint16_t flags = 0;
6099         int ret;
6100
6101         if (filter->queue >= pf->dev_data->nb_rx_queues) {
6102                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6103                 return -EINVAL;
6104         }
6105         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6106                 filter->ether_type == ETHER_TYPE_IPv6) {
6107                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6108                         " control packet filter.", filter->ether_type);
6109                 return -EINVAL;
6110         }
6111         if (filter->ether_type == ETHER_TYPE_VLAN)
6112                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
6113                         " not supported.");
6114
6115         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
6116                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
6117         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
6118                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
6119         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
6120
6121         memset(&stats, 0, sizeof(stats));
6122         ret = i40e_aq_add_rem_control_packet_filter(hw,
6123                         filter->mac_addr.addr_bytes,
6124                         filter->ether_type, flags,
6125                         pf->main_vsi->seid,
6126                         filter->queue, add, &stats, NULL);
6127
6128         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
6129                          " mac_etype_used = %u, etype_used = %u,"
6130                          " mac_etype_free = %u, etype_free = %u\n",
6131                          ret, stats.mac_etype_used, stats.etype_used,
6132                          stats.mac_etype_free, stats.etype_free);
6133         if (ret < 0)
6134                 return -ENOSYS;
6135         return 0;
6136 }
6137
6138 /*
6139  * Handle operations for ethertype filter.
6140  */
6141 static int
6142 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
6143                                 enum rte_filter_op filter_op,
6144                                 void *arg)
6145 {
6146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6147         int ret = 0;
6148
6149         if (filter_op == RTE_ETH_FILTER_NOP)
6150                 return ret;
6151
6152         if (arg == NULL) {
6153                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6154                             filter_op);
6155                 return -EINVAL;
6156         }
6157
6158         switch (filter_op) {
6159         case RTE_ETH_FILTER_ADD:
6160                 ret = i40e_ethertype_filter_set(pf,
6161                         (struct rte_eth_ethertype_filter *)arg,
6162                         TRUE);
6163                 break;
6164         case RTE_ETH_FILTER_DELETE:
6165                 ret = i40e_ethertype_filter_set(pf,
6166                         (struct rte_eth_ethertype_filter *)arg,
6167                         FALSE);
6168                 break;
6169         default:
6170                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6171                 ret = -ENOSYS;
6172                 break;
6173         }
6174         return ret;
6175 }
6176
6177 static int
6178 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
6179                      enum rte_filter_type filter_type,
6180                      enum rte_filter_op filter_op,
6181                      void *arg)
6182 {
6183         int ret = 0;
6184
6185         if (dev == NULL)
6186                 return -EINVAL;
6187
6188         switch (filter_type) {
6189         case RTE_ETH_FILTER_HASH:
6190                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
6191                 break;
6192         case RTE_ETH_FILTER_MACVLAN:
6193                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
6194                 break;
6195         case RTE_ETH_FILTER_ETHERTYPE:
6196                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
6197                 break;
6198         case RTE_ETH_FILTER_TUNNEL:
6199                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
6200                 break;
6201         case RTE_ETH_FILTER_FDIR:
6202                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
6203                 break;
6204         default:
6205                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6206                                                         filter_type);
6207                 ret = -EINVAL;
6208                 break;
6209         }
6210
6211         return ret;
6212 }
6213
6214 /*
6215  * As some registers wouldn't be reset unless a global hardware reset,
6216  * hardware initialization is needed to put those registers into an
6217  * expected initial state.
6218  */
6219 static void
6220 i40e_hw_init(struct i40e_hw *hw)
6221 {
6222         /* clear the PF Queue Filter control register */
6223         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
6224
6225         /* Disable symmetric hash per port */
6226         i40e_set_symmetric_hash_enable_per_port(hw, 0);
6227 }
6228
6229 enum i40e_filter_pctype
6230 i40e_flowtype_to_pctype(uint16_t flow_type)
6231 {
6232         static const enum i40e_filter_pctype pctype_table[] = {
6233                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
6234                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
6235                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
6236                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
6237                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
6238                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
6239                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
6240                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
6241                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
6242                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
6243                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
6244                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
6245                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
6246                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
6247                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
6248                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
6249                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
6250                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
6251                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
6252         };
6253
6254         return pctype_table[flow_type];
6255 }
6256
6257 uint16_t
6258 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
6259 {
6260         static const uint16_t flowtype_table[] = {
6261                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
6262                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6263                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
6264                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6265                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
6266                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6267                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
6268                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6269                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
6270                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
6271                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6272                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
6273                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6274                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
6275                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6276                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
6277                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6278                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
6279                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
6280         };
6281
6282         return flowtype_table[pctype];
6283 }
6284
6285 /*
6286  * On X710, performance number is far from the expectation on recent firmware
6287  * versions; on XL710, performance number is also far from the expectation on
6288  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
6289  * mode is enabled and port MAC address is equal to the packet destination MAC
6290  * address. The fix for this issue may not be integrated in the following
6291  * firmware version. So the workaround in software driver is needed. It needs
6292  * to modify the initial values of 3 internal only registers for both X710 and
6293  * XL710. Note that the values for X710 or XL710 could be different, and the
6294  * workaround can be removed when it is fixed in firmware in the future.
6295  */
6296
6297 /* For both X710 and XL710 */
6298 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
6299 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
6300
6301 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
6302 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
6303
6304 /* For X710 */
6305 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
6306 /* For XL710 */
6307 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
6308 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
6309
6310 static void
6311 i40e_configure_registers(struct i40e_hw *hw)
6312 {
6313         static struct {
6314                 uint32_t addr;
6315                 uint64_t val;
6316         } reg_table[] = {
6317                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
6318                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
6319                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
6320         };
6321         uint64_t reg;
6322         uint32_t i;
6323         int ret;
6324
6325         for (i = 0; i < RTE_DIM(reg_table); i++) {
6326                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
6327                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
6328                                 reg_table[i].val =
6329                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
6330                         else /* For X710 */
6331                                 reg_table[i].val =
6332                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
6333                 }
6334
6335                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
6336                                                         &reg, NULL);
6337                 if (ret < 0) {
6338                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
6339                                                         reg_table[i].addr);
6340                         break;
6341                 }
6342                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
6343                                                 reg_table[i].addr, reg);
6344                 if (reg == reg_table[i].val)
6345                         continue;
6346
6347                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
6348                                                 reg_table[i].val, NULL);
6349                 if (ret < 0) {
6350                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
6351                                 "address of 0x%"PRIx32, reg_table[i].val,
6352                                                         reg_table[i].addr);
6353                         break;
6354                 }
6355                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
6356                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
6357         }
6358 }
6359
6360 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
6361 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
6362 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
6363 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
6364 static int
6365 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
6366 {
6367         uint32_t reg;
6368         int ret;
6369
6370         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
6371                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
6372                 return -EINVAL;
6373         }
6374
6375         /* Configure for double VLAN RX stripping */
6376         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
6377         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
6378                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
6379                 ret = i40e_aq_debug_write_register(hw,
6380                                                    I40E_VSI_TSR(vsi->vsi_id),
6381                                                    reg, NULL);
6382                 if (ret < 0) {
6383                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
6384                                     vsi->vsi_id);
6385                         return I40E_ERR_CONFIG;
6386                 }
6387         }
6388
6389         /* Configure for double VLAN TX insertion */
6390         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
6391         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
6392                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
6393                 ret = i40e_aq_debug_write_register(hw,
6394                                                    I40E_VSI_L2TAGSTXVALID(
6395                                                    vsi->vsi_id), reg, NULL);
6396                 if (ret < 0) {
6397                         PMD_DRV_LOG(ERR, "Failed to update "
6398                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
6399                         return I40E_ERR_CONFIG;
6400                 }
6401         }
6402
6403         return 0;
6404 }
6405
6406 /**
6407  * i40e_aq_add_mirror_rule
6408  * @hw: pointer to the hardware structure
6409  * @seid: VEB seid to add mirror rule to
6410  * @dst_id: destination vsi seid
6411  * @entries: Buffer which contains the entities to be mirrored
6412  * @count: number of entities contained in the buffer
6413  * @rule_id:the rule_id of the rule to be added
6414  *
6415  * Add a mirror rule for a given veb.
6416  *
6417  **/
6418 static enum i40e_status_code
6419 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
6420                         uint16_t seid, uint16_t dst_id,
6421                         uint16_t rule_type, uint16_t *entries,
6422                         uint16_t count, uint16_t *rule_id)
6423 {
6424         struct i40e_aq_desc desc;
6425         struct i40e_aqc_add_delete_mirror_rule cmd;
6426         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
6427                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
6428                 &desc.params.raw;
6429         uint16_t buff_len;
6430         enum i40e_status_code status;
6431
6432         i40e_fill_default_direct_cmd_desc(&desc,
6433                                           i40e_aqc_opc_add_mirror_rule);
6434         memset(&cmd, 0, sizeof(cmd));
6435
6436         buff_len = sizeof(uint16_t) * count;
6437         desc.datalen = rte_cpu_to_le_16(buff_len);
6438         if (buff_len > 0)
6439                 desc.flags |= rte_cpu_to_le_16(
6440                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6441         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6442                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6443         cmd.num_entries = rte_cpu_to_le_16(count);
6444         cmd.seid = rte_cpu_to_le_16(seid);
6445         cmd.destination = rte_cpu_to_le_16(dst_id);
6446
6447         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6448         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
6449         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
6450                          "rule_id = %u"
6451                          " mirror_rules_used = %u, mirror_rules_free = %u,",
6452                          hw->aq.asq_last_status, resp->rule_id,
6453                          resp->mirror_rules_used, resp->mirror_rules_free);
6454         *rule_id = rte_le_to_cpu_16(resp->rule_id);
6455
6456         return status;
6457 }
6458
6459 /**
6460  * i40e_aq_del_mirror_rule
6461  * @hw: pointer to the hardware structure
6462  * @seid: VEB seid to add mirror rule to
6463  * @entries: Buffer which contains the entities to be mirrored
6464  * @count: number of entities contained in the buffer
6465  * @rule_id:the rule_id of the rule to be delete
6466  *
6467  * Delete a mirror rule for a given veb.
6468  *
6469  **/
6470 static enum i40e_status_code
6471 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
6472                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
6473                 uint16_t count, uint16_t rule_id)
6474 {
6475         struct i40e_aq_desc desc;
6476         struct i40e_aqc_add_delete_mirror_rule cmd;
6477         uint16_t buff_len = 0;
6478         enum i40e_status_code status;
6479         void *buff = NULL;
6480
6481         i40e_fill_default_direct_cmd_desc(&desc,
6482                                           i40e_aqc_opc_delete_mirror_rule);
6483         memset(&cmd, 0, sizeof(cmd));
6484         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
6485                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
6486                                                           I40E_AQ_FLAG_RD));
6487                 cmd.num_entries = count;
6488                 buff_len = sizeof(uint16_t) * count;
6489                 desc.datalen = rte_cpu_to_le_16(buff_len);
6490                 buff = (void *)entries;
6491         } else
6492                 /* rule id is filled in destination field for deleting mirror rule */
6493                 cmd.destination = rte_cpu_to_le_16(rule_id);
6494
6495         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6496                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6497         cmd.seid = rte_cpu_to_le_16(seid);
6498
6499         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6500         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
6501
6502         return status;
6503 }
6504
6505 /**
6506  * i40e_mirror_rule_set
6507  * @dev: pointer to the hardware structure
6508  * @mirror_conf: mirror rule info
6509  * @sw_id: mirror rule's sw_id
6510  * @on: enable/disable
6511  *
6512  * set a mirror rule.
6513  *
6514  **/
6515 static int
6516 i40e_mirror_rule_set(struct rte_eth_dev *dev,
6517                         struct rte_eth_mirror_conf *mirror_conf,
6518                         uint8_t sw_id, uint8_t on)
6519 {
6520         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6521         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6522         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6523         struct i40e_mirror_rule *parent = NULL;
6524         uint16_t seid, dst_seid, rule_id;
6525         uint16_t i, j = 0;
6526         int ret;
6527
6528         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
6529
6530         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
6531                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
6532                         " without veb or vfs.");
6533                 return -ENOSYS;
6534         }
6535         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
6536                 PMD_DRV_LOG(ERR, "mirror table is full.");
6537                 return -ENOSPC;
6538         }
6539         if (mirror_conf->dst_pool > pf->vf_num) {
6540                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6541                                  mirror_conf->dst_pool);
6542                 return -EINVAL;
6543         }
6544
6545         seid = pf->main_vsi->veb->seid;
6546
6547         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6548                 if (sw_id <= it->index) {
6549                         mirr_rule = it;
6550                         break;
6551                 }
6552                 parent = it;
6553         }
6554         if (mirr_rule && sw_id == mirr_rule->index) {
6555                 if (on) {
6556                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6557                         return -EEXIST;
6558                 } else {
6559                         ret = i40e_aq_del_mirror_rule(hw, seid,
6560                                         mirr_rule->rule_type,
6561                                         mirr_rule->entries,
6562                                         mirr_rule->num_entries, mirr_rule->id);
6563                         if (ret < 0) {
6564                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6565                                                    " ret = %d, aq_err = %d.",
6566                                                    ret, hw->aq.asq_last_status);
6567                                 return -ENOSYS;
6568                         }
6569                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6570                         rte_free(mirr_rule);
6571                         pf->nb_mirror_rule--;
6572                         return 0;
6573                 }
6574         } else if (!on) {
6575                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6576                 return -ENOENT;
6577         }
6578
6579         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6580                                 sizeof(struct i40e_mirror_rule) , 0);
6581         if (!mirr_rule) {
6582                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6583                 return I40E_ERR_NO_MEMORY;
6584         }
6585         switch (mirror_conf->rule_type) {
6586         case ETH_MIRROR_VLAN:
6587                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6588                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6589                                 mirr_rule->entries[j] =
6590                                         mirror_conf->vlan.vlan_id[i];
6591                                 j++;
6592                         }
6593                 }
6594                 if (j == 0) {
6595                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6596                         rte_free(mirr_rule);
6597                         return -EINVAL;
6598                 }
6599                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6600                 break;
6601         case ETH_MIRROR_VIRTUAL_POOL_UP:
6602         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6603                 /* check if the specified pool bit is out of range */
6604                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6605                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6606                         rte_free(mirr_rule);
6607                         return -EINVAL;
6608                 }
6609                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6610                         if (mirror_conf->pool_mask & (1ULL << i)) {
6611                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6612                                 j++;
6613                         }
6614                 }
6615                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6616                         /* add pf vsi to entries */
6617                         mirr_rule->entries[j] = pf->main_vsi_seid;
6618                         j++;
6619                 }
6620                 if (j == 0) {
6621                         PMD_DRV_LOG(ERR, "pool is not specified.");
6622                         rte_free(mirr_rule);
6623                         return -EINVAL;
6624                 }
6625                 /* egress and ingress in aq commands means from switch but not port */
6626                 mirr_rule->rule_type =
6627                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6628                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6629                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6630                 break;
6631         case ETH_MIRROR_UPLINK_PORT:
6632                 /* egress and ingress in aq commands means from switch but not port*/
6633                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6634                 break;
6635         case ETH_MIRROR_DOWNLINK_PORT:
6636                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6637                 break;
6638         default:
6639                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6640                         mirror_conf->rule_type);
6641                 rte_free(mirr_rule);
6642                 return -EINVAL;
6643         }
6644
6645         /* If the dst_pool is equal to vf_num, consider it as PF */
6646         if (mirror_conf->dst_pool == pf->vf_num)
6647                 dst_seid = pf->main_vsi_seid;
6648         else
6649                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6650
6651         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6652                                       mirr_rule->rule_type, mirr_rule->entries,
6653                                       j, &rule_id);
6654         if (ret < 0) {
6655                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6656                                    " ret = %d, aq_err = %d.",
6657                                    ret, hw->aq.asq_last_status);
6658                 rte_free(mirr_rule);
6659                 return -ENOSYS;
6660         }
6661
6662         mirr_rule->index = sw_id;
6663         mirr_rule->num_entries = j;
6664         mirr_rule->id = rule_id;
6665         mirr_rule->dst_vsi_seid = dst_seid;
6666
6667         if (parent)
6668                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6669         else
6670                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6671
6672         pf->nb_mirror_rule++;
6673         return 0;
6674 }
6675
6676 /**
6677  * i40e_mirror_rule_reset
6678  * @dev: pointer to the device
6679  * @sw_id: mirror rule's sw_id
6680  *
6681  * reset a mirror rule.
6682  *
6683  **/
6684 static int
6685 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6686 {
6687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6689         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6690         uint16_t seid;
6691         int ret;
6692
6693         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6694
6695         seid = pf->main_vsi->veb->seid;
6696
6697         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6698                 if (sw_id == it->index) {
6699                         mirr_rule = it;
6700                         break;
6701                 }
6702         }
6703         if (mirr_rule) {
6704                 ret = i40e_aq_del_mirror_rule(hw, seid,
6705                                 mirr_rule->rule_type,
6706                                 mirr_rule->entries,
6707                                 mirr_rule->num_entries, mirr_rule->id);
6708                 if (ret < 0) {
6709                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6710                                            " status = %d, aq_err = %d.",
6711                                            ret, hw->aq.asq_last_status);
6712                         return -ENOSYS;
6713                 }
6714                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6715                 rte_free(mirr_rule);
6716                 pf->nb_mirror_rule--;
6717         } else {
6718                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6719                 return -ENOENT;
6720         }
6721         return 0;
6722 }
6723
6724 static int
6725 i40e_timesync_enable(struct rte_eth_dev *dev)
6726 {
6727         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6728         struct rte_eth_link *link = &dev->data->dev_link;
6729         uint32_t tsync_ctl_l;
6730         uint32_t tsync_ctl_h;
6731         uint32_t tsync_inc_l;
6732         uint32_t tsync_inc_h;
6733
6734         switch (link->link_speed) {
6735         case ETH_LINK_SPEED_40G:
6736                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6737                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6738                 break;
6739         case ETH_LINK_SPEED_10G:
6740                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6741                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6742                 break;
6743         case ETH_LINK_SPEED_1000:
6744                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6745                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6746                 break;
6747         default:
6748                 tsync_inc_l = 0x0;
6749                 tsync_inc_h = 0x0;
6750         }
6751
6752         /* Clear timesync registers. */
6753         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6754         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6755         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6756         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6757         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6758         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6759         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6760
6761         /* Set the timesync increment value. */
6762         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6763         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6764
6765         /* Enable timestamping of PTP packets. */
6766         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6767         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6768
6769         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6770         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6771         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6772
6773         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6774         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6775
6776         return 0;
6777 }
6778
6779 static int
6780 i40e_timesync_disable(struct rte_eth_dev *dev)
6781 {
6782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         uint32_t tsync_ctl_l;
6784         uint32_t tsync_ctl_h;
6785
6786         /* Disable timestamping of transmitted PTP packets. */
6787         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6788         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6789
6790         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6791         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6792
6793         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6794         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6795
6796         /* Set the timesync increment value. */
6797         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6798         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6799
6800         return 0;
6801 }
6802
6803 static int
6804 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6805                                 struct timespec *timestamp, uint32_t flags)
6806 {
6807         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6808         uint32_t sync_status;
6809         uint32_t rx_stmpl;
6810         uint32_t rx_stmph;
6811         uint32_t index = flags & 0x03;
6812
6813         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6814         if ((sync_status & (1 << index)) == 0)
6815                 return -EINVAL;
6816
6817         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6818         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6819
6820         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6821         timestamp->tv_nsec = 0;
6822
6823         return  0;
6824 }
6825
6826 static int
6827 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6828                                 struct timespec *timestamp)
6829 {
6830         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6831         uint32_t sync_status;
6832         uint32_t tx_stmpl;
6833         uint32_t tx_stmph;
6834
6835         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6836         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6837                 return -EINVAL;
6838
6839         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6840         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6841
6842         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6843         timestamp->tv_nsec = 0;
6844
6845         return  0;
6846 }
6847
6848 /*
6849  * i40e_parse_dcb_configure - parse dcb configure from user
6850  * @dev: the device being configured
6851  * @dcb_cfg: pointer of the result of parse
6852  * @*tc_map: bit map of enabled traffic classes
6853  *
6854  * Returns 0 on success, negative value on failure
6855  */
6856 static int
6857 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
6858                          struct i40e_dcbx_config *dcb_cfg,
6859                          uint8_t *tc_map)
6860 {
6861         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
6862         uint8_t i, tc_bw, bw_lf;
6863
6864         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
6865
6866         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6867         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
6868                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
6869                 return -EINVAL;
6870         }
6871
6872         /* assume each tc has the same bw */
6873         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
6874         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6875                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
6876         /* to ensure the sum of tcbw is equal to 100 */
6877         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
6878         for (i = 0; i < bw_lf; i++)
6879                 dcb_cfg->etscfg.tcbwtable[i]++;
6880
6881         /* assume each tc has the same Transmission Selection Algorithm */
6882         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6883                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
6884
6885         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
6886                 dcb_cfg->etscfg.prioritytable[i] =
6887                                 dcb_rx_conf->dcb_tc[i];
6888
6889         /* FW needs one App to configure HW */
6890         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
6891         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
6892         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
6893         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
6894
6895         if (dcb_rx_conf->nb_tcs == 0)
6896                 *tc_map = 1; /* tc0 only */
6897         else
6898                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
6899
6900         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
6901                 dcb_cfg->pfc.willing = 0;
6902                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
6903                 dcb_cfg->pfc.pfcenable = *tc_map;
6904         }
6905         return 0;
6906 }
6907
6908 /*
6909  * i40e_vsi_get_bw_info - Query VSI BW Information
6910  * @vsi: the VSI being queried
6911  *
6912  * Returns 0 on success, negative value on failure
6913  */
6914 static int
6915 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
6916 {
6917         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
6918         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
6919         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6920         int i, ret;
6921         uint32_t tc_bw_max;
6922
6923         /* Get the VSI level BW configuration */
6924         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
6925         if (ret) {
6926                 PMD_INIT_LOG(ERR,
6927                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
6928                          i40e_stat_str(hw, ret),
6929                          i40e_aq_str(hw, hw->aq.asq_last_status));
6930                 return -EINVAL;
6931         }
6932
6933         /* Get the VSI level BW configuration per TC */
6934         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6935                                                   NULL);
6936         if (ret) {
6937                 PMD_INIT_LOG(ERR,
6938                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
6939                          i40e_stat_str(hw, ret),
6940                          i40e_aq_str(hw, hw->aq.asq_last_status));
6941                 return -EINVAL;
6942         }
6943
6944         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
6945                 PMD_INIT_LOG(WARNING,
6946                          "Enabled TCs mismatch from querying VSI BW info"
6947                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
6948                          bw_ets_config.tc_valid_bits);
6949                 /* Still continuing */
6950         }
6951
6952         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
6953         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
6954         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
6955                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
6956         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6957                 vsi->bw_info.bw_ets_share_credits[i] =
6958                                 bw_ets_config.share_credits[i];
6959                 vsi->bw_info.bw_ets_limit_credits[i] =
6960                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
6961                 /* 3 bits out of 4 for each TC */
6962                 vsi->bw_info.bw_ets_max_quanta[i] =
6963                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
6964                 PMD_INIT_LOG(DEBUG,
6965                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
6966                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
6967         }
6968
6969         return 0;
6970 }
6971
6972 static int
6973 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
6974                               struct i40e_aqc_vsi_properties_data *info,
6975                               uint8_t enabled_tcmap)
6976 {
6977         int ret, i, total_tc = 0;
6978         uint16_t qpnum_per_tc, bsf, qp_idx;
6979         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
6980
6981         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
6982         if (ret != I40E_SUCCESS)
6983                 return ret;
6984
6985         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6986                 if (enabled_tcmap & (1 << i))
6987                         total_tc++;
6988         }
6989         if (total_tc == 0)
6990                 total_tc = 1;
6991         vsi->enabled_tc = enabled_tcmap;
6992
6993         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
6994         /* Number of queues per enabled TC */
6995         if (qpnum_per_tc == 0) {
6996                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
6997                 return I40E_ERR_INVALID_QP_ID;
6998         }
6999         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
7000                                 I40E_MAX_Q_PER_TC);
7001         bsf = rte_bsf32(qpnum_per_tc);
7002
7003         /**
7004          * Configure TC and queue mapping parameters, for enabled TC,
7005          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
7006          * default queue will serve it.
7007          */
7008         qp_idx = 0;
7009         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7010                 if (vsi->enabled_tc & (1 << i)) {
7011                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
7012                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
7013                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
7014                         qp_idx += qpnum_per_tc;
7015                 } else
7016                         info->tc_mapping[i] = 0;
7017         }
7018
7019         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
7020         if (vsi->type == I40E_VSI_SRIOV) {
7021                 info->mapping_flags |=
7022                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
7023                 for (i = 0; i < vsi->nb_qps; i++)
7024                         info->queue_mapping[i] =
7025                                 rte_cpu_to_le_16(vsi->base_queue + i);
7026         } else {
7027                 info->mapping_flags |=
7028                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
7029                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
7030         }
7031         info->valid_sections |=
7032                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
7033
7034         return I40E_SUCCESS;
7035 }
7036
7037 /*
7038  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
7039  * @vsi: VSI to be configured
7040  * @tc_map: enabled TC bitmap
7041  *
7042  * Returns 0 on success, negative value on failure
7043  */
7044 static int
7045 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
7046 {
7047         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
7048         struct i40e_vsi_context ctxt;
7049         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7050         int ret = 0;
7051         int i;
7052
7053         /* Check if enabled_tc is same as existing or new TCs */
7054         if (vsi->enabled_tc == tc_map)
7055                 return ret;
7056
7057         /* configure tc bandwidth */
7058         memset(&bw_data, 0, sizeof(bw_data));
7059         bw_data.tc_valid_bits = tc_map;
7060         /* Enable ETS TCs with equal BW Share for now across all VSIs */
7061         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7062                 if (tc_map & BIT_ULL(i))
7063                         bw_data.tc_bw_credits[i] = 1;
7064         }
7065         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
7066         if (ret) {
7067                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
7068                         " per TC failed = %d",
7069                         hw->aq.asq_last_status);
7070                 goto out;
7071         }
7072         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
7073                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
7074
7075         /* Update Queue Pairs Mapping for currently enabled UPs */
7076         ctxt.seid = vsi->seid;
7077         ctxt.pf_num = hw->pf_id;
7078         ctxt.vf_num = 0;
7079         ctxt.uplink_seid = vsi->uplink_seid;
7080         ctxt.info = vsi->info;
7081         i40e_get_cap(hw);
7082         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
7083         if (ret)
7084                 goto out;
7085
7086         /* Update the VSI after updating the VSI queue-mapping information */
7087         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7088         if (ret) {
7089                 PMD_INIT_LOG(ERR, "Failed to configure "
7090                             "TC queue mapping = %d",
7091                             hw->aq.asq_last_status);
7092                 goto out;
7093         }
7094         /* update the local VSI info with updated queue map */
7095         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
7096                                         sizeof(vsi->info.tc_mapping));
7097         (void)rte_memcpy(&vsi->info.queue_mapping,
7098                         &ctxt.info.queue_mapping,
7099                 sizeof(vsi->info.queue_mapping));
7100         vsi->info.mapping_flags = ctxt.info.mapping_flags;
7101         vsi->info.valid_sections = 0;
7102
7103         /* Update current VSI BW information */
7104         ret = i40e_vsi_get_bw_info(vsi);
7105         if (ret) {
7106                 PMD_INIT_LOG(ERR,
7107                          "Failed updating vsi bw info, err %s aq_err %s",
7108                          i40e_stat_str(hw, ret),
7109                          i40e_aq_str(hw, hw->aq.asq_last_status));
7110                 goto out;
7111         }
7112
7113         vsi->enabled_tc = tc_map;
7114
7115 out:
7116         return ret;
7117 }
7118
7119 /*
7120  * i40e_dcb_hw_configure - program the dcb setting to hw
7121  * @pf: pf the configuration is taken on
7122  * @new_cfg: new configuration
7123  * @tc_map: enabled TC bitmap
7124  *
7125  * Returns 0 on success, negative value on failure
7126  */
7127 static enum i40e_status_code
7128 i40e_dcb_hw_configure(struct i40e_pf *pf,
7129                       struct i40e_dcbx_config *new_cfg,
7130                       uint8_t tc_map)
7131 {
7132         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7133         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
7134         struct i40e_vsi *main_vsi = pf->main_vsi;
7135         struct i40e_vsi_list *vsi_list;
7136         int i, ret;
7137         uint32_t val;
7138
7139         /* Use the FW API if FW > v4.4*/
7140         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
7141                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
7142                                   " to configure DCB");
7143                 return I40E_ERR_FIRMWARE_API_VERSION;
7144         }
7145
7146         /* Check if need reconfiguration */
7147         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
7148                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
7149                 return I40E_SUCCESS;
7150         }
7151
7152         /* Copy the new config to the current config */
7153         *old_cfg = *new_cfg;
7154         old_cfg->etsrec = old_cfg->etscfg;
7155         ret = i40e_set_dcb_config(hw);
7156         if (ret) {
7157                 PMD_INIT_LOG(ERR,
7158                          "Set DCB Config failed, err %s aq_err %s\n",
7159                          i40e_stat_str(hw, ret),
7160                          i40e_aq_str(hw, hw->aq.asq_last_status));
7161                 return ret;
7162         }
7163         /* set receive Arbiter to RR mode and ETS scheme by default */
7164         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
7165                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
7166                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
7167                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
7168                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
7169                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
7170                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
7171                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
7172                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
7173                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
7174                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
7175                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
7176                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
7177         }
7178         /* get local mib to check whether it is configured correctly */
7179         /* IEEE mode */
7180         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
7181         /* Get Local DCB Config */
7182         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
7183                                      &hw->local_dcbx_config);
7184
7185         /* Update each VSI */
7186         i40e_vsi_config_tc(main_vsi, tc_map);
7187         if (main_vsi->veb) {
7188                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
7189                         /* Beside main VSI, only enable default
7190                          * TC for other VSIs
7191                          */
7192                         ret = i40e_vsi_config_tc(vsi_list->vsi,
7193                                                 I40E_DEFAULT_TCMAP);
7194                         if (ret)
7195                                 PMD_INIT_LOG(WARNING,
7196                                          "Failed configuring TC for VSI seid=%d\n",
7197                                          vsi_list->vsi->seid);
7198                         /* continue */
7199                 }
7200         }
7201         return I40E_SUCCESS;
7202 }
7203
7204 /*
7205  * i40e_dcb_init_configure - initial dcb config
7206  * @dev: device being configured
7207  * @sw_dcb: indicate whether dcb is sw configured or hw offload
7208  *
7209  * Returns 0 on success, negative value on failure
7210  */
7211 static int
7212 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
7213 {
7214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7215         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7216         int ret = 0;
7217
7218         if ((pf->flags & I40E_FLAG_DCB) == 0) {
7219                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7220                 return -ENOTSUP;
7221         }
7222
7223         /* DCB initialization:
7224          * Update DCB configuration from the Firmware and configure
7225          * LLDP MIB change event.
7226          */
7227         if (sw_dcb == TRUE) {
7228                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
7229                 if (ret != I40E_SUCCESS)
7230                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
7231
7232                 ret = i40e_init_dcb(hw);
7233                 /* if sw_dcb, lldp agent is stopped, the return from
7234                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
7235                  * adminq status.
7236                  */
7237                 if (ret != I40E_SUCCESS &&
7238                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
7239                         memset(&hw->local_dcbx_config, 0,
7240                                 sizeof(struct i40e_dcbx_config));
7241                         /* set dcb default configuration */
7242                         hw->local_dcbx_config.etscfg.willing = 0;
7243                         hw->local_dcbx_config.etscfg.maxtcs = 0;
7244                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
7245                         hw->local_dcbx_config.etscfg.tsatable[0] =
7246                                                 I40E_IEEE_TSA_ETS;
7247                         hw->local_dcbx_config.etsrec =
7248                                 hw->local_dcbx_config.etscfg;
7249                         hw->local_dcbx_config.pfc.willing = 0;
7250                         hw->local_dcbx_config.pfc.pfccap =
7251                                                 I40E_MAX_TRAFFIC_CLASS;
7252                         /* FW needs one App to configure HW */
7253                         hw->local_dcbx_config.numapps = 1;
7254                         hw->local_dcbx_config.app[0].selector =
7255                                                 I40E_APP_SEL_ETHTYPE;
7256                         hw->local_dcbx_config.app[0].priority = 3;
7257                         hw->local_dcbx_config.app[0].protocolid =
7258                                                 I40E_APP_PROTOID_FCOE;
7259                         ret = i40e_set_dcb_config(hw);
7260                         if (ret) {
7261                                 PMD_INIT_LOG(ERR, "default dcb config fails."
7262                                         " err = %d, aq_err = %d.", ret,
7263                                           hw->aq.asq_last_status);
7264                                 return -ENOSYS;
7265                         }
7266                 } else {
7267                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
7268                                           " aq_err = %d.", ret,
7269                                           hw->aq.asq_last_status);
7270                         return -ENOTSUP;
7271                 }
7272         } else {
7273                 ret = i40e_aq_start_lldp(hw, NULL);
7274                 if (ret != I40E_SUCCESS)
7275                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
7276
7277                 ret = i40e_init_dcb(hw);
7278                 if (!ret) {
7279                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
7280                                 PMD_INIT_LOG(ERR, "HW doesn't support"
7281                                                   " DCBX offload.");
7282                                 return -ENOTSUP;
7283                         }
7284                 } else {
7285                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
7286                                           " aq_err = %d.", ret,
7287                                           hw->aq.asq_last_status);
7288                         return -ENOTSUP;
7289                 }
7290         }
7291         return 0;
7292 }
7293
7294 /*
7295  * i40e_dcb_setup - setup dcb related config
7296  * @dev: device being configured
7297  *
7298  * Returns 0 on success, negative value on failure
7299  */
7300 static int
7301 i40e_dcb_setup(struct rte_eth_dev *dev)
7302 {
7303         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7304         struct i40e_dcbx_config dcb_cfg;
7305         uint8_t tc_map = 0;
7306         int ret = 0;
7307
7308         if ((pf->flags & I40E_FLAG_DCB) == 0) {
7309                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7310                 return -ENOTSUP;
7311         }
7312
7313         if (pf->vf_num != 0 ||
7314             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
7315                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
7316
7317         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
7318         if (ret) {
7319                 PMD_INIT_LOG(ERR, "invalid dcb config");
7320                 return -EINVAL;
7321         }
7322         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
7323         if (ret) {
7324                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
7325                 return -ENOSYS;
7326         }
7327         return 0;
7328 }
7329
7330 static int
7331 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
7332                       struct rte_eth_dcb_info *dcb_info)
7333 {
7334         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7335         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7336         struct i40e_vsi *vsi = pf->main_vsi;
7337         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
7338         uint16_t bsf, tc_mapping;
7339         int i;
7340
7341         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7342                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
7343         else
7344                 dcb_info->nb_tcs = 1;
7345         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7346                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
7347         for (i = 0; i < dcb_info->nb_tcs; i++)
7348                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
7349
7350         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7351                 if (vsi->enabled_tc & (1 << i)) {
7352                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
7353                         /* only main vsi support multi TCs */
7354                         dcb_info->tc_queue.tc_rxq[0][i].base =
7355                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
7356                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
7357                         dcb_info->tc_queue.tc_txq[0][i].base =
7358                                 dcb_info->tc_queue.tc_rxq[0][i].base;
7359                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
7360                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
7361                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
7362                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
7363                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
7364                 }
7365         }
7366         return 0;
7367 }